diff options
-rw-r--r-- | drivers/staging/bcm/Macros.h | 337 |
1 files changed, 167 insertions, 170 deletions
diff --git a/drivers/staging/bcm/Macros.h b/drivers/staging/bcm/Macros.h index 916bebb7ed5..46ed99c5376 100644 --- a/drivers/staging/bcm/Macros.h +++ b/drivers/staging/bcm/Macros.h | |||
@@ -1,17 +1,17 @@ | |||
1 | /************************************* | 1 | /************************************* |
2 | * Macros.h | 2 | * Macros.h |
3 | **************************************/ | 3 | **************************************/ |
4 | #ifndef __MACROS_H__ | 4 | #ifndef __MACROS_H__ |
5 | #define __MACROS_H__ | 5 | #define __MACROS_H__ |
6 | 6 | ||
7 | #define TX_TIMER_PERIOD 10 //10 msec | 7 | #define TX_TIMER_PERIOD 10 /*10 msec*/ |
8 | #define MAX_CLASSIFIERS 100 | 8 | #define MAX_CLASSIFIERS 100 |
9 | //#define MAX_CLASSIFIERS_PER_SF 20 | 9 | /* #define MAX_CLASSIFIERS_PER_SF 20 */ |
10 | #define MAX_TARGET_DSX_BUFFERS 24 | 10 | #define MAX_TARGET_DSX_BUFFERS 24 |
11 | 11 | ||
12 | #define MAX_CNTRL_PKTS 100 | 12 | #define MAX_CNTRL_PKTS 100 |
13 | #define MAX_DATA_PKTS 200 | 13 | #define MAX_DATA_PKTS 200 |
14 | #define MAX_ETH_SIZE 1536 | 14 | #define MAX_ETH_SIZE 1536 |
15 | #define MAX_CNTL_PKT_SIZE 2048 | 15 | #define MAX_CNTL_PKT_SIZE 2048 |
16 | 16 | ||
17 | #define MTU_SIZE 1400 | 17 | #define MTU_SIZE 1400 |
@@ -20,102 +20,102 @@ | |||
20 | #define MAC_ADDR_REGISTER 0xbf60d000 | 20 | #define MAC_ADDR_REGISTER 0xbf60d000 |
21 | 21 | ||
22 | 22 | ||
23 | ///////////Quality of Service/////////////////////////// | 23 | /* Quality of Service */ |
24 | #define NO_OF_QUEUES 17 | 24 | #define NO_OF_QUEUES 17 |
25 | #define HiPriority NO_OF_QUEUES-1 | 25 | #define HiPriority (NO_OF_QUEUES-1) |
26 | #define LowPriority 0 | 26 | #define LowPriority 0 |
27 | #define BE 2 | 27 | #define BE 2 |
28 | #define rtPS 4 | 28 | #define rtPS 4 |
29 | #define ERTPS 5 | 29 | #define ERTPS 5 |
30 | #define UGS 6 | 30 | #define UGS 6 |
31 | 31 | ||
32 | #define BE_BUCKET_SIZE 1024*1024*100 //32kb | 32 | #define BE_BUCKET_SIZE (1024*1024*100) /* 32kb */ |
33 | #define rtPS_BUCKET_SIZE 1024*1024*100 //8kb | 33 | #define rtPS_BUCKET_SIZE (1024*1024*100) /* 8kb */ |
34 | #define MAX_ALLOWED_RATE 1024*1024*100 | 34 | #define MAX_ALLOWED_RATE (1024*1024*100) |
35 | #define TX_PACKET_THRESHOLD 10 | 35 | #define TX_PACKET_THRESHOLD 10 |
36 | #define XSECONDS 1*HZ | 36 | #define XSECONDS (1*HZ) |
37 | #define DSC_ACTIVATE_REQUEST 248 | 37 | #define DSC_ACTIVATE_REQUEST 248 |
38 | #define QUEUE_DEPTH_OFFSET 0x1fc01000 | 38 | #define QUEUE_DEPTH_OFFSET 0x1fc01000 |
39 | #define MAX_DEVICE_DESC_SIZE 2040 | 39 | #define MAX_DEVICE_DESC_SIZE 2040 |
40 | #define MAX_CTRL_QUEUE_LEN 100 | 40 | #define MAX_CTRL_QUEUE_LEN 100 |
41 | #define MAX_APP_QUEUE_LEN 200 | 41 | #define MAX_APP_QUEUE_LEN 200 |
42 | #define MAX_LATENCY_ALLOWED 0xFFFFFFFF | 42 | #define MAX_LATENCY_ALLOWED 0xFFFFFFFF |
43 | #define DEFAULT_UG_INTERVAL 250 | 43 | #define DEFAULT_UG_INTERVAL 250 |
44 | #define DEFAULT_UGI_FACTOR 4 | 44 | #define DEFAULT_UGI_FACTOR 4 |
45 | 45 | ||
46 | #define DEFAULT_PERSFCOUNT 60 | 46 | #define DEFAULT_PERSFCOUNT 60 |
47 | #define MAX_CONNECTIONS 10 | 47 | #define MAX_CONNECTIONS 10 |
48 | #define MAX_CLASS_NAME_LENGTH 32 | 48 | #define MAX_CLASS_NAME_LENGTH 32 |
49 | 49 | ||
50 | #define ETH_LENGTH_OF_ADDRESS 6 | 50 | #define ETH_LENGTH_OF_ADDRESS 6 |
51 | #define MAX_MULTICAST_ADDRESSES 32 | 51 | #define MAX_MULTICAST_ADDRESSES 32 |
52 | #define IP_LENGTH_OF_ADDRESS 4 | 52 | #define IP_LENGTH_OF_ADDRESS 4 |
53 | 53 | ||
54 | #define IP_PACKET_ONLY_MODE 0 | 54 | #define IP_PACKET_ONLY_MODE 0 |
55 | #define ETH_PACKET_TUNNELING_MODE 1 | 55 | #define ETH_PACKET_TUNNELING_MODE 1 |
56 | 56 | ||
57 | ////////////Link Request////////////// | 57 | /* Link Request */ |
58 | #define SET_MAC_ADDRESS_REQUEST 0 | 58 | #define SET_MAC_ADDRESS_REQUEST 0 |
59 | #define SYNC_UP_REQUEST 1 | 59 | #define SYNC_UP_REQUEST 1 |
60 | #define SYNCED_UP 2 | 60 | #define SYNCED_UP 2 |
61 | #define LINK_UP_REQUEST 3 | 61 | #define LINK_UP_REQUEST 3 |
62 | #define LINK_CONNECTED 4 | 62 | #define LINK_CONNECTED 4 |
63 | #define SYNC_UP_NOTIFICATION 2 | 63 | #define SYNC_UP_NOTIFICATION 2 |
64 | #define LINK_UP_NOTIFICATION 4 | 64 | #define LINK_UP_NOTIFICATION 4 |
65 | 65 | ||
66 | 66 | ||
67 | #define LINK_NET_ENTRY 0x0002 | 67 | #define LINK_NET_ENTRY 0x0002 |
68 | #define HMC_STATUS 0x0004 | 68 | #define HMC_STATUS 0x0004 |
69 | #define LINK_UP_CONTROL_REQ 0x83 | 69 | #define LINK_UP_CONTROL_REQ 0x83 |
70 | 70 | ||
71 | #define STATS_POINTER_REQ_STATUS 0x86 | 71 | #define STATS_POINTER_REQ_STATUS 0x86 |
72 | #define NETWORK_ENTRY_REQ_PAYLOAD 198 | 72 | #define NETWORK_ENTRY_REQ_PAYLOAD 198 |
73 | #define LINK_DOWN_REQ_PAYLOAD 226 | 73 | #define LINK_DOWN_REQ_PAYLOAD 226 |
74 | #define SYNC_UP_REQ_PAYLOAD 228 | 74 | #define SYNC_UP_REQ_PAYLOAD 228 |
75 | #define STATISTICS_POINTER_REQ 237 | 75 | #define STATISTICS_POINTER_REQ 237 |
76 | #define LINK_UP_REQ_PAYLOAD 245 | 76 | #define LINK_UP_REQ_PAYLOAD 245 |
77 | #define LINK_UP_ACK 246 | 77 | #define LINK_UP_ACK 246 |
78 | 78 | ||
79 | #define STATS_MSG_SIZE 4 | 79 | #define STATS_MSG_SIZE 4 |
80 | #define INDEX_TO_DATA 4 | 80 | #define INDEX_TO_DATA 4 |
81 | 81 | ||
82 | #define GO_TO_IDLE_MODE_PAYLOAD 210 | 82 | #define GO_TO_IDLE_MODE_PAYLOAD 210 |
83 | #define COME_UP_FROM_IDLE_MODE_PAYLOAD 211 | 83 | #define COME_UP_FROM_IDLE_MODE_PAYLOAD 211 |
84 | #define IDLE_MODE_SF_UPDATE_MSG 187 | 84 | #define IDLE_MODE_SF_UPDATE_MSG 187 |
85 | 85 | ||
86 | #define SKB_RESERVE_ETHERNET_HEADER 16 | 86 | #define SKB_RESERVE_ETHERNET_HEADER 16 |
87 | #define SKB_RESERVE_PHS_BYTES 32 | 87 | #define SKB_RESERVE_PHS_BYTES 32 |
88 | 88 | ||
89 | #define IP_PACKET_ONLY_MODE 0 | 89 | #define IP_PACKET_ONLY_MODE 0 |
90 | #define ETH_PACKET_TUNNELING_MODE 1 | 90 | #define ETH_PACKET_TUNNELING_MODE 1 |
91 | 91 | ||
92 | #define ETH_CS_802_3 1 | 92 | #define ETH_CS_802_3 1 |
93 | #define ETH_CS_802_1Q_VLAN 3 | 93 | #define ETH_CS_802_1Q_VLAN 3 |
94 | #define IPV4_CS 1 | 94 | #define IPV4_CS 1 |
95 | #define IPV6_CS 2 | 95 | #define IPV6_CS 2 |
96 | #define ETH_CS_MASK 0x3f | 96 | #define ETH_CS_MASK 0x3f |
97 | 97 | ||
98 | /** \brief Validity bit maps for TLVs in packet classification rule */ | 98 | /** \brief Validity bit maps for TLVs in packet classification rule */ |
99 | 99 | ||
100 | #define PKT_CLASSIFICATION_USER_PRIORITY_VALID 0 | 100 | #define PKT_CLASSIFICATION_USER_PRIORITY_VALID 0 |
101 | #define PKT_CLASSIFICATION_VLANID_VALID 1 | 101 | #define PKT_CLASSIFICATION_VLANID_VALID 1 |
102 | 102 | ||
103 | #ifndef MIN | 103 | #ifndef MIN |
104 | #define MIN(_a, _b) ((_a) < (_b)? (_a): (_b)) | 104 | #define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b)) |
105 | #endif | 105 | #endif |
106 | 106 | ||
107 | 107 | ||
108 | /*Leader related terms */ | 108 | /*Leader related terms */ |
109 | #define LEADER_STATUS 0x00 | 109 | #define LEADER_STATUS 0x00 |
110 | #define LEADER_STATUS_TCP_ACK 0x1 | 110 | #define LEADER_STATUS_TCP_ACK 0x1 |
111 | #define LEADER_SIZE sizeof(LEADER) | 111 | #define LEADER_SIZE sizeof(LEADER) |
112 | #define MAC_ADDR_REQ_SIZE sizeof(PACKETTOSEND) | 112 | #define MAC_ADDR_REQ_SIZE sizeof(PACKETTOSEND) |
113 | #define SS_INFO_REQ_SIZE sizeof(PACKETTOSEND) | 113 | #define SS_INFO_REQ_SIZE sizeof(PACKETTOSEND) |
114 | #define CM_REQUEST_SIZE LEADER_SIZE + sizeof(stLocalSFChangeRequest) | 114 | #define CM_REQUEST_SIZE (LEADER_SIZE + sizeof(stLocalSFChangeRequest)) |
115 | #define IDLE_REQ_SIZE sizeof(PACKETTOSEND) | 115 | #define IDLE_REQ_SIZE sizeof(PACKETTOSEND) |
116 | 116 | ||
117 | 117 | ||
118 | #define MAX_TRANSFER_CTRL_BYTE_USB 2 * 1024 | 118 | #define MAX_TRANSFER_CTRL_BYTE_USB (2*1024) |
119 | 119 | ||
120 | #define GET_MAILBOX1_REG_REQUEST 0x87 | 120 | #define GET_MAILBOX1_REG_REQUEST 0x87 |
121 | #define GET_MAILBOX1_REG_RESPONSE 0x67 | 121 | #define GET_MAILBOX1_REG_RESPONSE 0x67 |
@@ -124,40 +124,40 @@ | |||
124 | #define TRANSMIT_NETWORK_DATA 0x00 | 124 | #define TRANSMIT_NETWORK_DATA 0x00 |
125 | #define RECEIVED_NETWORK_DATA 0x20 | 125 | #define RECEIVED_NETWORK_DATA 0x20 |
126 | 126 | ||
127 | #define CM_RESPONSES 0xA0 | 127 | #define CM_RESPONSES 0xA0 |
128 | #define STATUS_RSP 0xA1 | 128 | #define STATUS_RSP 0xA1 |
129 | #define LINK_CONTROL_RESP 0xA2 | 129 | #define LINK_CONTROL_RESP 0xA2 |
130 | #define IDLE_MODE_STATUS 0xA3 | 130 | #define IDLE_MODE_STATUS 0xA3 |
131 | #define STATS_POINTER_RESP 0xA6 | 131 | #define STATS_POINTER_RESP 0xA6 |
132 | #define MGMT_MSG_INFO_SW_STATUS 0xA7 | 132 | #define MGMT_MSG_INFO_SW_STATUS 0xA7 |
133 | #define AUTH_SS_HOST_MSG 0xA8 | 133 | #define AUTH_SS_HOST_MSG 0xA8 |
134 | 134 | ||
135 | #define CM_DSA_ACK_PAYLOAD 247 | 135 | #define CM_DSA_ACK_PAYLOAD 247 |
136 | #define CM_DSC_ACK_PAYLOAD 248 | 136 | #define CM_DSC_ACK_PAYLOAD 248 |
137 | #define CM_DSD_ACK_PAYLOAD 249 | 137 | #define CM_DSD_ACK_PAYLOAD 249 |
138 | #define CM_DSDEACTVATE 250 | 138 | #define CM_DSDEACTVATE 250 |
139 | #define TOTAL_MASKED_ADDRESS_IN_BYTES 32 | 139 | #define TOTAL_MASKED_ADDRESS_IN_BYTES 32 |
140 | 140 | ||
141 | #define MAC_REQ 0 | 141 | #define MAC_REQ 0 |
142 | #define LINK_RESP 1 | 142 | #define LINK_RESP 1 |
143 | #define RSSI_INDICATION 2 | 143 | #define RSSI_INDICATION 2 |
144 | 144 | ||
145 | #define SS_INFO 4 | 145 | #define SS_INFO 4 |
146 | #define STATISTICS_INFO 5 | 146 | #define STATISTICS_INFO 5 |
147 | #define CM_INDICATION 6 | 147 | #define CM_INDICATION 6 |
148 | #define PARAM_RESP 7 | 148 | #define PARAM_RESP 7 |
149 | #define BUFFER_1K 1024 | 149 | #define BUFFER_1K 1024 |
150 | #define BUFFER_2K BUFFER_1K*2 | 150 | #define BUFFER_2K (BUFFER_1K*2) |
151 | #define BUFFER_4K BUFFER_2K*2 | 151 | #define BUFFER_4K (BUFFER_2K*2) |
152 | #define BUFFER_8K BUFFER_4K*2 | 152 | #define BUFFER_8K (BUFFER_4K*2) |
153 | #define BUFFER_16K BUFFER_8K*2 | 153 | #define BUFFER_16K (BUFFER_8K*2) |
154 | #define DOWNLINK_DIR 0 | 154 | #define DOWNLINK_DIR 0 |
155 | #define UPLINK_DIR 1 | 155 | #define UPLINK_DIR 1 |
156 | 156 | ||
157 | #define BCM_SIGNATURE "BECEEM" | 157 | #define BCM_SIGNATURE "BECEEM" |
158 | 158 | ||
159 | 159 | ||
160 | #define GPIO_OUTPUT_REGISTER 0x0F00003C | 160 | #define GPIO_OUTPUT_REGISTER 0x0F00003C |
161 | #define BCM_GPIO_OUTPUT_SET_REG 0x0F000040 | 161 | #define BCM_GPIO_OUTPUT_SET_REG 0x0F000040 |
162 | #define BCM_GPIO_OUTPUT_CLR_REG 0x0F000044 | 162 | #define BCM_GPIO_OUTPUT_CLR_REG 0x0F000044 |
163 | #define GPIO_MODE_REGISTER 0x0F000034 | 163 | #define GPIO_MODE_REGISTER 0x0F000034 |
@@ -165,44 +165,43 @@ | |||
165 | 165 | ||
166 | 166 | ||
167 | typedef struct _LINK_STATE { | 167 | typedef struct _LINK_STATE { |
168 | UCHAR ucLinkStatus; | 168 | UCHAR ucLinkStatus; |
169 | UCHAR bIdleMode; | 169 | UCHAR bIdleMode; |
170 | UCHAR bShutdownMode; | 170 | UCHAR bShutdownMode; |
171 | }LINK_STATE, *PLINK_STATE; | 171 | } LINK_STATE, *PLINK_STATE; |
172 | 172 | ||
173 | 173 | ||
174 | enum enLinkStatus { | 174 | enum enLinkStatus { |
175 | WAIT_FOR_SYNC = 1, | 175 | WAIT_FOR_SYNC = 1, |
176 | PHY_SYNC_ACHIVED = 2, | 176 | PHY_SYNC_ACHIVED = 2, |
177 | LINKUP_IN_PROGRESS = 3, | 177 | LINKUP_IN_PROGRESS = 3, |
178 | LINKUP_DONE = 4, | 178 | LINKUP_DONE = 4, |
179 | DREG_RECEIVED = 5, | 179 | DREG_RECEIVED = 5, |
180 | LINK_STATUS_RESET_RECEIVED = 6, | 180 | LINK_STATUS_RESET_RECEIVED = 6, |
181 | PERIODIC_WAKE_UP_NOTIFICATION_FRM_FW = 7, | 181 | PERIODIC_WAKE_UP_NOTIFICATION_FRM_FW = 7, |
182 | LINK_SHUTDOWN_REQ_FROM_FIRMWARE = 8, | 182 | LINK_SHUTDOWN_REQ_FROM_FIRMWARE = 8, |
183 | COMPLETE_WAKE_UP_NOTIFICATION_FRM_FW =9 | 183 | COMPLETE_WAKE_UP_NOTIFICATION_FRM_FW = 9 |
184 | }; | 184 | }; |
185 | 185 | ||
186 | typedef enum _E_PHS_DSC_ACTION | 186 | typedef enum _E_PHS_DSC_ACTION { |
187 | { | 187 | eAddPHSRule = 0, |
188 | eAddPHSRule=0, | ||
189 | eSetPHSRule, | 188 | eSetPHSRule, |
190 | eDeletePHSRule, | 189 | eDeletePHSRule, |
191 | eDeleteAllPHSRules | 190 | eDeleteAllPHSRules |
192 | }E_PHS_DSC_ACTION; | 191 | } E_PHS_DSC_ACTION; |
193 | 192 | ||
194 | 193 | ||
195 | #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ 0x89 // Host to Mac | 194 | #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ 0x89 /* Host to Mac */ |
196 | #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP 0xA9 // Mac to Host | 195 | #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP 0xA9 /* Mac to Host */ |
197 | #define MASK_DISABLE_HEADER_SUPPRESSION 0x10 //0b000010000 | 196 | #define MASK_DISABLE_HEADER_SUPPRESSION 0x10 /* 0b000010000 */ |
198 | #define MINIMUM_PENDING_DESCRIPTORS 5 | 197 | #define MINIMUM_PENDING_DESCRIPTORS 5 |
199 | 198 | ||
200 | #define SHUTDOWN_HOSTINITIATED_REQUESTPAYLOAD 0xCC | 199 | #define SHUTDOWN_HOSTINITIATED_REQUESTPAYLOAD 0xCC |
201 | #define SHUTDOWN_ACK_FROM_DRIVER 0x1 | 200 | #define SHUTDOWN_ACK_FROM_DRIVER 0x1 |
202 | #define SHUTDOWN_NACK_FROM_DRIVER 0x2 | 201 | #define SHUTDOWN_NACK_FROM_DRIVER 0x2 |
203 | 202 | ||
204 | #define LINK_SYNC_UP_SUBTYPE 0x0001 | 203 | #define LINK_SYNC_UP_SUBTYPE 0x0001 |
205 | #define LINK_SYNC_DOWN_SUBTYPE 0x0001 | 204 | #define LINK_SYNC_DOWN_SUBTYPE 0x0001 |
206 | 205 | ||
207 | 206 | ||
208 | 207 | ||
@@ -226,9 +225,9 @@ typedef enum _E_PHS_DSC_ACTION | |||
226 | 225 | ||
227 | #define MAX_PENDING_CTRL_PACKET (MAX_CTRL_QUEUE_LEN-10) | 226 | #define MAX_PENDING_CTRL_PACKET (MAX_CTRL_QUEUE_LEN-10) |
228 | 227 | ||
229 | #define WIMAX_MAX_MTU (MTU_SIZE + ETH_HLEN) | 228 | #define WIMAX_MAX_MTU (MTU_SIZE + ETH_HLEN) |
230 | #define AUTO_LINKUP_ENABLE 0x2 | 229 | #define AUTO_LINKUP_ENABLE 0x2 |
231 | #define AUTO_SYNC_DISABLE 0x1 | 230 | #define AUTO_SYNC_DISABLE 0x1 |
232 | #define AUTO_FIRM_DOWNLOAD 0x1 | 231 | #define AUTO_FIRM_DOWNLOAD 0x1 |
233 | #define SETTLE_DOWN_TIME 50 | 232 | #define SETTLE_DOWN_TIME 50 |
234 | 233 | ||
@@ -242,9 +241,9 @@ typedef enum _E_PHS_DSC_ACTION | |||
242 | #define TARGET_CAN_NOT_GO_TO_IDLE_MODE 3 | 241 | #define TARGET_CAN_NOT_GO_TO_IDLE_MODE 3 |
243 | #define IDLE_MODE_PAYLOAD_LENGTH 8 | 242 | #define IDLE_MODE_PAYLOAD_LENGTH 8 |
244 | 243 | ||
245 | #define IP_HEADER(Buffer) ((IPHeaderFormat*)(Buffer)) | 244 | #define IP_HEADER(Buffer) ((IPHeaderFormat *)(Buffer)) |
246 | #define IPV4 4 | 245 | #define IPV4 4 |
247 | #define IP_VERSION(byte) (((byte&0xF0)>>4)) | 246 | #define IP_VERSION(byte) (((byte&0xF0)>>4)) |
248 | 247 | ||
249 | #define SET_MAC_ADDRESS 193 | 248 | #define SET_MAC_ADDRESS 193 |
250 | #define SET_MAC_ADDRESS_RESPONSE 236 | 249 | #define SET_MAC_ADDRESS_RESPONSE 236 |
@@ -263,15 +262,15 @@ typedef enum _E_PHS_DSC_ACTION | |||
263 | 262 | ||
264 | #define INVALID_QUEUE_INDEX NO_OF_QUEUES | 263 | #define INVALID_QUEUE_INDEX NO_OF_QUEUES |
265 | 264 | ||
266 | #define INVALID_PID (pid_t)-1 | 265 | #define INVALID_PID ((pid_t)-1) |
267 | #define DDR_80_MHZ 0 | 266 | #define DDR_80_MHZ 0 |
268 | #define DDR_100_MHZ 1 | 267 | #define DDR_100_MHZ 1 |
269 | #define DDR_120_MHZ 2 // Additional Frequency for T3LP | 268 | #define DDR_120_MHZ 2 /* Additional Frequency for T3LP */ |
270 | #define DDR_133_MHZ 3 | 269 | #define DDR_133_MHZ 3 |
271 | #define DDR_140_MHZ 4 // Not Used (Reserved for future) | 270 | #define DDR_140_MHZ 4 /* Not Used (Reserved for future) */ |
272 | #define DDR_160_MHZ 5 // Additional Frequency for T3LP | 271 | #define DDR_160_MHZ 5 /* Additional Frequency for T3LP */ |
273 | #define DDR_180_MHZ 6 // Not Used (Reserved for future) | 272 | #define DDR_180_MHZ 6 /* Not Used (Reserved for future) */ |
274 | #define DDR_200_MHZ 7 // Not Used (Reserved for future) | 273 | #define DDR_200_MHZ 7 /* Not Used (Reserved for future) */ |
275 | 274 | ||
276 | #define MIPS_200_MHZ 0 | 275 | #define MIPS_200_MHZ 0 |
277 | #define MIPS_160_MHZ 1 | 276 | #define MIPS_160_MHZ 1 |
@@ -291,27 +290,27 @@ typedef enum _E_PHS_DSC_ACTION | |||
291 | #define EEPROM_REJECT_REG_3 0x0f003008 | 290 | #define EEPROM_REJECT_REG_3 0x0f003008 |
292 | #define EEPROM_REJECT_REG_4 0x0f003020 | 291 | #define EEPROM_REJECT_REG_4 0x0f003020 |
293 | #define EEPROM_REJECT_MASK 0x0fffffff | 292 | #define EEPROM_REJECT_MASK 0x0fffffff |
294 | #define VSG_MODE 0x3 | 293 | #define VSG_MODE 0x3 |
295 | 294 | ||
296 | /* Idle Mode Related Registers */ | 295 | /* Idle Mode Related Registers */ |
297 | #define DEBUG_INTERRUPT_GENERATOR_REGISTOR 0x0F00007C | 296 | #define DEBUG_INTERRUPT_GENERATOR_REGISTOR 0x0F00007C |
298 | #define SW_ABORT_IDLEMODE_LOC 0x0FF01FFC | 297 | #define SW_ABORT_IDLEMODE_LOC 0x0FF01FFC |
299 | 298 | ||
300 | #define SW_ABORT_IDLEMODE_PATTERN 0xd0ea1d1e | 299 | #define SW_ABORT_IDLEMODE_PATTERN 0xd0ea1d1e |
301 | #define DEVICE_INT_OUT_EP_REG0 0x0F011870 | 300 | #define DEVICE_INT_OUT_EP_REG0 0x0F011870 |
302 | #define DEVICE_INT_OUT_EP_REG1 0x0F011874 | 301 | #define DEVICE_INT_OUT_EP_REG1 0x0F011874 |
303 | 302 | ||
304 | #define BIN_FILE "/lib/firmware/macxvi200.bin" | 303 | #define BIN_FILE "/lib/firmware/macxvi200.bin" |
305 | #define CFG_FILE "/lib/firmware/macxvi.cfg" | 304 | #define CFG_FILE "/lib/firmware/macxvi.cfg" |
306 | #define SF_MAX_ALLOWED_PACKETS_TO_BACKUP 128 | 305 | #define SF_MAX_ALLOWED_PACKETS_TO_BACKUP 128 |
307 | #define MIN_VAL(x,y) ((x)<(y)?(x):(y)) | 306 | #define MIN_VAL(x, y) ((x) < (y) ? (x) : (y)) |
308 | #define MAC_ADDRESS_SIZE 6 | 307 | #define MAC_ADDRESS_SIZE 6 |
309 | #define EEPROM_COMMAND_Q_REG 0x0F003018 | 308 | #define EEPROM_COMMAND_Q_REG 0x0F003018 |
310 | #define EEPROM_READ_DATA_Q_REG 0x0F003020 | 309 | #define EEPROM_READ_DATA_Q_REG 0x0F003020 |
311 | #define CHIP_ID_REG 0x0F000000 | 310 | #define CHIP_ID_REG 0x0F000000 |
312 | #define GPIO_MODE_REG 0x0F000034 | 311 | #define GPIO_MODE_REG 0x0F000034 |
313 | #define GPIO_OUTPUT_REG 0x0F00003C | 312 | #define GPIO_OUTPUT_REG 0x0F00003C |
314 | #define WIMAX_MAX_ALLOWED_RATE 1024*1024*50 | 313 | #define WIMAX_MAX_ALLOWED_RATE (1024*1024*50) |
315 | 314 | ||
316 | #define T3 0xbece0300 | 315 | #define T3 0xbece0300 |
317 | #define TARGET_SFID_TXDESC_MAP_LOC 0xBFFFF400 | 316 | #define TARGET_SFID_TXDESC_MAP_LOC 0xBFFFF400 |
@@ -319,31 +318,29 @@ typedef enum _E_PHS_DSC_ACTION | |||
319 | #define RWM_READ 0 | 318 | #define RWM_READ 0 |
320 | #define RWM_WRITE 1 | 319 | #define RWM_WRITE 1 |
321 | 320 | ||
322 | #define T3LPB 0xbece3300 | 321 | #define T3LPB 0xbece3300 |
323 | #define BCS220_2 0xbece3311 | 322 | #define BCS220_2 0xbece3311 |
324 | #define BCS220_2BC 0xBECE3310 | 323 | #define BCS220_2BC 0xBECE3310 |
325 | #define BCS250_BC 0xbece3301 | 324 | #define BCS250_BC 0xbece3301 |
326 | #define BCS220_3 0xbece3321 | 325 | #define BCS220_3 0xbece3321 |
327 | 326 | ||
328 | 327 | ||
329 | #define HPM_CONFIG_LDO145 0x0F000D54 | 328 | #define HPM_CONFIG_LDO145 0x0F000D54 |
330 | #define HPM_CONFIG_MSW 0x0F000D58 | 329 | #define HPM_CONFIG_MSW 0x0F000D58 |
331 | 330 | ||
332 | #define T3B 0xbece0310 | 331 | #define T3B 0xbece0310 |
333 | typedef enum eNVM_TYPE | 332 | typedef enum eNVM_TYPE { |
334 | { | ||
335 | NVM_AUTODETECT = 0, | 333 | NVM_AUTODETECT = 0, |
336 | NVM_EEPROM, | 334 | NVM_EEPROM, |
337 | NVM_FLASH, | 335 | NVM_FLASH, |
338 | NVM_UNKNOWN | 336 | NVM_UNKNOWN |
339 | }NVM_TYPE; | 337 | } NVM_TYPE; |
340 | 338 | ||
341 | typedef enum ePMU_MODES | 339 | typedef enum ePMU_MODES { |
342 | { | ||
343 | HYBRID_MODE_7C = 0, | 340 | HYBRID_MODE_7C = 0, |
344 | INTERNAL_MODE_6 = 1, | 341 | INTERNAL_MODE_6 = 1, |
345 | HYBRID_MODE_6 = 2 | 342 | HYBRID_MODE_6 = 2 |
346 | }PMU_MODE; | 343 | } PMU_MODE; |
347 | 344 | ||
348 | #define MAX_RDM_WRM_RETIRES 1 | 345 | #define MAX_RDM_WRM_RETIRES 1 |
349 | 346 | ||
@@ -360,4 +357,4 @@ enum eAbortPattern { | |||
360 | #define SKB_CB_LATENCY_OFFSET 1 | 357 | #define SKB_CB_LATENCY_OFFSET 1 |
361 | #define SKB_CB_TCPACK_OFFSET 2 | 358 | #define SKB_CB_TCPACK_OFFSET 2 |
362 | 359 | ||
363 | #endif //__MACROS_H__ | 360 | #endif /* __MACROS_H__ */ |