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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-12 02:32:03 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-13 13:01:57 -0400
commitea0a591a28b9249ea585f2cf8045e43f57f48fbb (patch)
tree2168e570830b4526c5aaff54b9b84fead2513099 /sound/soc/tegra/tegra_i2s.h
parentecfb1adf5f037eaff0b678918d84a8febd9f1c3e (diff)
ASoC: Optimise clock management for WM8915 Speyside
Dynamically enable and disable the FLL on the WM8915, configuring the system clock to 256fs for 48kHz when the device is active but reverting to using the input 32.768kHz clock directly at other times to support features such as jack detection with minimal power consumption. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Acked-by: Liam Girdwood <lrg@ti.com>
Diffstat (limited to 'sound/soc/tegra/tegra_i2s.h')
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