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authorYevgeny Petrilin <yevgenyp@mellanox.co.il>2008-08-06 23:14:06 -0400
committerRoland Dreier <rolandd@cisco.com>2008-08-06 23:14:06 -0400
commitf780a9f119caa48088b230836a7fa73d1096de7c (patch)
tree513fb3aa4342a481aa1f4101675ea2e9c41bc28a /include
parent6e86841d05f371b5b9b86ce76c02aaee83352298 (diff)
mlx4_core: Add ethernet fields to CQE struct
Add ethernet-related fields to struct mlx4_cqe so that the mlx4_en ethernet NIC driver can share the same definition. Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mlx4/cq.h36
1 files changed, 24 insertions, 12 deletions
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
index 071cf96cf01..6f65b2c8bb8 100644
--- a/include/linux/mlx4/cq.h
+++ b/include/linux/mlx4/cq.h
@@ -39,17 +39,18 @@
39#include <linux/mlx4/doorbell.h> 39#include <linux/mlx4/doorbell.h>
40 40
41struct mlx4_cqe { 41struct mlx4_cqe {
42 __be32 my_qpn; 42 __be32 vlan_my_qpn;
43 __be32 immed_rss_invalid; 43 __be32 immed_rss_invalid;
44 __be32 g_mlpath_rqpn; 44 __be32 g_mlpath_rqpn;
45 u8 sl; 45 __be16 sl_vid;
46 u8 reserved1;
47 __be16 rlid; 46 __be16 rlid;
48 __be32 ipoib_status; 47 __be16 status;
48 u8 ipv6_ext_mask;
49 u8 badfcs_enc;
49 __be32 byte_cnt; 50 __be32 byte_cnt;
50 __be16 wqe_index; 51 __be16 wqe_index;
51 __be16 checksum; 52 __be16 checksum;
52 u8 reserved2[3]; 53 u8 reserved[3];
53 u8 owner_sr_opcode; 54 u8 owner_sr_opcode;
54}; 55};
55 56
@@ -64,6 +65,11 @@ struct mlx4_err_cqe {
64}; 65};
65 66
66enum { 67enum {
68 MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
69 MLX4_CQE_QPN_MASK = 0xffffff,
70};
71
72enum {
67 MLX4_CQE_OWNER_MASK = 0x80, 73 MLX4_CQE_OWNER_MASK = 0x80,
68 MLX4_CQE_IS_SEND_MASK = 0x40, 74 MLX4_CQE_IS_SEND_MASK = 0x40,
69 MLX4_CQE_OPCODE_MASK = 0x1f 75 MLX4_CQE_OPCODE_MASK = 0x1f
@@ -86,13 +92,19 @@ enum {
86}; 92};
87 93
88enum { 94enum {
89 MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22, 95 MLX4_CQE_STATUS_IPV4 = 1 << 6,
90 MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23, 96 MLX4_CQE_STATUS_IPV4F = 1 << 7,
91 MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24, 97 MLX4_CQE_STATUS_IPV6 = 1 << 8,
92 MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25, 98 MLX4_CQE_STATUS_IPV4OPT = 1 << 9,
93 MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26, 99 MLX4_CQE_STATUS_TCP = 1 << 10,
94 MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27, 100 MLX4_CQE_STATUS_UDP = 1 << 11,
95 MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28, 101 MLX4_CQE_STATUS_IPOK = 1 << 12,
102};
103
104enum {
105 MLX4_CQE_LLC = 1,
106 MLX4_CQE_SNAP = 1 << 1,
107 MLX4_CQE_BAD_FCS = 1 << 4,
96}; 108};
97 109
98static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, 110static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,