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authorLinus Torvalds <torvalds@merom.osdl.org>2006-11-08 13:23:03 -0500
committerLinus Torvalds <torvalds@merom.osdl.org>2006-11-08 13:23:03 -0500
commit6c0ffb9d2fd987c79c6cbb81c3f3011c63749b1a (patch)
treeae135f5fcc6ab29f3fc0d057f4a9c10e5be58cbf /include
parent464908d7e2a9f77cb50ee905cda8a59e5b4e50e4 (diff)
x86-64: clean up io-apic accesses
This is just commit 130fe05dbc0114609cfef9815c0c5580b42decfa ported to x86-64, for all the same reasons. It cleans up the IO-APIC accesses in order to then fix the ordering issues. We move the accessor functions (that were only used by io_apic.c) out of a header file, and use proper memory-mapped accesses rather than making up our own "volatile" pointers. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-x86_64/io_apic.h34
1 files changed, 0 insertions, 34 deletions
diff --git a/include/asm-x86_64/io_apic.h b/include/asm-x86_64/io_apic.h
index 171ec2dc8c0..561ecbfd4cb 100644
--- a/include/asm-x86_64/io_apic.h
+++ b/include/asm-x86_64/io_apic.h
@@ -12,10 +12,6 @@
12 12
13#define APIC_MISMATCH_DEBUG 13#define APIC_MISMATCH_DEBUG
14 14
15#define IO_APIC_BASE(idx) \
16 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
17 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
18
19/* 15/*
20 * The structure of the IO-APIC: 16 * The structure of the IO-APIC:
21 */ 17 */
@@ -119,36 +115,6 @@ extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
119/* non-0 if default (table-less) MP configuration */ 115/* non-0 if default (table-less) MP configuration */
120extern int mpc_default_type; 116extern int mpc_default_type;
121 117
122static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
123{
124 *IO_APIC_BASE(apic) = reg;
125 return *(IO_APIC_BASE(apic)+4);
126}
127
128static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
129{
130 *IO_APIC_BASE(apic) = reg;
131 *(IO_APIC_BASE(apic)+4) = value;
132}
133
134/*
135 * Re-write a value: to be used for read-modify-write
136 * cycles where the read already set up the index register.
137 */
138static inline void io_apic_modify(unsigned int apic, unsigned int value)
139{
140 *(IO_APIC_BASE(apic)+4) = value;
141}
142
143/*
144 * Synchronize the IO-APIC and the CPU by doing
145 * a dummy read from the IO-APIC
146 */
147static inline void io_apic_sync(unsigned int apic)
148{
149 (void) *(IO_APIC_BASE(apic)+4);
150}
151
152/* 1 if "noapic" boot option passed */ 118/* 1 if "noapic" boot option passed */
153extern int skip_ioapic_setup; 119extern int skip_ioapic_setup;
154 120