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authorBastian Hecht <hechtb@googlemail.com>2012-03-01 04:48:40 -0500
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-03-26 19:43:08 -0400
commit3f2e924b26989bbe1ad600a83fdc72a3056104d1 (patch)
tree2fb1cefdca093b69d184fbf2601db00bee899c9f /include
parent0b3f0d12eff1ed23496fcf4cf468e1d317516e53 (diff)
mtd: sh_flctl: Add FLHOLDCR register
Add a register used in new FLCTL hardware and a feature flag for it. Signed-off-by: Bastian Hecht <hechtb@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mtd/sh_flctl.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index c7082820703..8bcf299cb9b 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -38,6 +38,7 @@
38#define FLDTFIFO(f) (f->reg + 0x24) 38#define FLDTFIFO(f) (f->reg + 0x24)
39#define FLECFIFO(f) (f->reg + 0x28) 39#define FLECFIFO(f) (f->reg + 0x28)
40#define FLTRCR(f) (f->reg + 0x2C) 40#define FLTRCR(f) (f->reg + 0x2C)
41#define FLHOLDCR(f) (f->reg + 0x38)
41#define FL4ECCRESULT0(f) (f->reg + 0x80) 42#define FL4ECCRESULT0(f) (f->reg + 0x80)
42#define FL4ECCRESULT1(f) (f->reg + 0x84) 43#define FL4ECCRESULT1(f) (f->reg + 0x84)
43#define FL4ECCRESULT2(f) (f->reg + 0x88) 44#define FL4ECCRESULT2(f) (f->reg + 0x88)
@@ -109,6 +110,15 @@
109#define TRSTRT (0x1 << 0) /* translation start */ 110#define TRSTRT (0x1 << 0) /* translation start */
110#define TREND (0x1 << 1) /* translation end */ 111#define TREND (0x1 << 1) /* translation end */
111 112
113/*
114 * FLHOLDCR control bits
115 *
116 * HOLDEN: Bus Occupancy Enable (inverted)
117 * Enable this bit when the external bus might be used in between transfers.
118 * If not set and the bus gets used by other modules, a deadlock occurs.
119 */
120#define HOLDEN (0x1 << 0)
121
112/* FL4ECCCR control bits */ 122/* FL4ECCCR control bits */
113#define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */ 123#define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */
114#define _4ECCEND (0x1 << 1) /* 4 symbols end */ 124#define _4ECCEND (0x1 << 1) /* 4 symbols end */
@@ -138,6 +148,7 @@ struct sh_flctl {
138 148
139 unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */ 149 unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */
140 unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */ 150 unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */
151 unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */
141}; 152};
142 153
143struct sh_flctl_platform_data { 154struct sh_flctl_platform_data {
@@ -146,6 +157,7 @@ struct sh_flctl_platform_data {
146 unsigned long flcmncr_val; 157 unsigned long flcmncr_val;
147 158
148 unsigned has_hwecc:1; 159 unsigned has_hwecc:1;
160 unsigned use_holden:1;
149}; 161};
150 162
151static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo) 163static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)