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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /include/video
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'include/video')
-rw-r--r--include/video/auo_k190xfb.h106
-rw-r--r--include/video/da8xx-fb.h28
-rw-r--r--include/video/edid.h6
-rw-r--r--include/video/exynos_dp.h131
-rw-r--r--include/video/exynos_mipi_dsim.h360
-rw-r--r--include/video/omap-panel-n8x0.h15
-rw-r--r--include/video/omap-panel-nokia-dsi.h11
-rw-r--r--include/video/omap-panel-picodlp.h23
-rw-r--r--include/video/omap-panel-tfp410.h35
-rw-r--r--include/video/omapdss.h487
-rw-r--r--include/video/omapvrfb.h68
-rw-r--r--include/video/sa1100fb.h63
-rw-r--r--include/video/samsung_fimd.h469
-rw-r--r--include/video/sh_mipi_dsi.h26
-rw-r--r--include/video/sh_mobile_hdmi.h14
-rw-r--r--include/video/sh_mobile_lcdc.h180
-rw-r--r--include/video/sh_mobile_meram.h94
-rw-r--r--include/video/udlfb.h2
-rw-r--r--include/video/vga.h22
19 files changed, 239 insertions, 1901 deletions
diff --git a/include/video/auo_k190xfb.h b/include/video/auo_k190xfb.h
deleted file mode 100644
index 609efe8c686..00000000000
--- a/include/video/auo_k190xfb.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * Definitions for AUO-K190X framebuffer drivers
3 *
4 * Copyright (C) 2012 Heiko Stuebner <heiko@sntech.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _LINUX_VIDEO_AUO_K190XFB_H_
12#define _LINUX_VIDEO_AUO_K190XFB_H_
13
14/* Controller standby command needs a param */
15#define AUOK190X_QUIRK_STANDBYPARAM (1 << 0)
16
17/* Controller standby is completely broken */
18#define AUOK190X_QUIRK_STANDBYBROKEN (1 << 1)
19
20/*
21 * Resolutions for the displays
22 */
23#define AUOK190X_RESOLUTION_800_600 0
24#define AUOK190X_RESOLUTION_1024_768 1
25
26/*
27 * struct used by auok190x. board specific stuff comes from *board
28 */
29struct auok190xfb_par {
30 struct fb_info *info;
31 struct auok190x_board *board;
32
33 struct regulator *regulator;
34
35 struct mutex io_lock;
36 struct delayed_work work;
37 wait_queue_head_t waitq;
38 int resolution;
39 int rotation;
40 int consecutive_threshold;
41 int update_cnt;
42
43 /* panel and controller informations */
44 int epd_type;
45 int panel_size_int;
46 int panel_size_float;
47 int panel_model;
48 int tcon_version;
49 int lut_version;
50
51 /* individual controller callbacks */
52 void (*update_partial)(struct auok190xfb_par *par, u16 y1, u16 y2);
53 void (*update_all)(struct auok190xfb_par *par);
54 bool (*need_refresh)(struct auok190xfb_par *par);
55 void (*init)(struct auok190xfb_par *par);
56 void (*recover)(struct auok190xfb_par *par);
57
58 int update_mode; /* mode to use for updates */
59 int last_mode; /* update mode last used */
60 int flash;
61
62 /* power management */
63 int autosuspend_delay;
64 bool standby;
65 bool manual_standby;
66};
67
68/**
69 * Board specific platform-data
70 * @init: initialize the controller interface
71 * @cleanup: cleanup the controller interface
72 * @wait_for_rdy: wait until the controller is not busy anymore
73 * @set_ctl: change an interface control
74 * @set_hdb: write a value to the data register
75 * @get_hdb: read a value from the data register
76 * @setup_irq: method to setup the irq handling on the busy gpio
77 * @gpio_nsleep: sleep gpio
78 * @gpio_nrst: reset gpio
79 * @gpio_nbusy: busy gpio
80 * @resolution: one of the AUOK190X_RESOLUTION constants
81 * @rotation: rotation of the framebuffer
82 * @quirks: controller quirks to honor
83 * @fps: frames per second for defio
84 */
85struct auok190x_board {
86 int (*init)(struct auok190xfb_par *);
87 void (*cleanup)(struct auok190xfb_par *);
88 int (*wait_for_rdy)(struct auok190xfb_par *);
89
90 void (*set_ctl)(struct auok190xfb_par *, unsigned char, u8);
91 void (*set_hdb)(struct auok190xfb_par *, u16);
92 u16 (*get_hdb)(struct auok190xfb_par *);
93
94 int (*setup_irq)(struct fb_info *);
95
96 int gpio_nsleep;
97 int gpio_nrst;
98 int gpio_nbusy;
99
100 int resolution;
101 int rotation;
102 int quirks;
103 int fps;
104};
105
106#endif
diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h
index f88825928dd..89d43b3d4cb 100644
--- a/include/video/da8xx-fb.h
+++ b/include/video/da8xx-fb.h
@@ -12,6 +12,10 @@
12#ifndef DA8XX_FB_H 12#ifndef DA8XX_FB_H
13#define DA8XX_FB_H 13#define DA8XX_FB_H
14 14
15enum panel_type {
16 QVGA = 0
17};
18
15enum panel_shade { 19enum panel_shade {
16 MONOCHROME = 0, 20 MONOCHROME = 0,
17 COLOR_ACTIVE, 21 COLOR_ACTIVE,
@@ -23,6 +27,13 @@ enum raster_load_mode {
23 LOAD_PALETTE, 27 LOAD_PALETTE,
24}; 28};
25 29
30struct display_panel {
31 enum panel_type panel_type; /* QVGA */
32 int max_bpp;
33 int min_bpp;
34 enum panel_shade panel_shade;
35};
36
26struct da8xx_lcdc_platform_data { 37struct da8xx_lcdc_platform_data {
27 const char manu_name[10]; 38 const char manu_name[10];
28 void *controller_data; 39 void *controller_data;
@@ -31,7 +42,7 @@ struct da8xx_lcdc_platform_data {
31}; 42};
32 43
33struct lcd_ctrl_config { 44struct lcd_ctrl_config {
34 enum panel_shade panel_shade; 45 const struct display_panel *p_disp_panel;
35 46
36 /* AC Bias Pin Frequency */ 47 /* AC Bias Pin Frequency */
37 int ac_bias; 48 int ac_bias;
@@ -57,14 +68,20 @@ struct lcd_ctrl_config {
57 /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ 68 /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
58 unsigned char mono_8bit_mode; 69 unsigned char mono_8bit_mode;
59 70
71 /* Invert line clock */
72 unsigned char invert_line_clock;
73
74 /* Invert frame clock */
75 unsigned char invert_frm_clock;
76
60 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ 77 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
61 unsigned char sync_edge; 78 unsigned char sync_edge;
62 79
80 /* Horizontal and Vertical Sync: Control: 0=ignore */
81 unsigned char sync_ctrl;
82
63 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ 83 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
64 unsigned char raster_order; 84 unsigned char raster_order;
65
66 /* DMA FIFO threshold */
67 int fifo_th;
68}; 85};
69 86
70struct lcd_sync_arg { 87struct lcd_sync_arg {
@@ -83,8 +100,5 @@ struct lcd_sync_arg {
83#define FBIPUT_HSYNC _IOW('F', 9, int) 100#define FBIPUT_HSYNC _IOW('F', 9, int)
84#define FBIPUT_VSYNC _IOW('F', 10, int) 101#define FBIPUT_VSYNC _IOW('F', 10, int)
85 102
86/* Proprietary FB_SYNC_ flags */
87#define FB_SYNC_CLK_INVERT 0x40000000
88
89#endif /* ifndef DA8XX_FB_H */ 103#endif /* ifndef DA8XX_FB_H */
90 104
diff --git a/include/video/edid.h b/include/video/edid.h
index c5f19870491..928c342b33d 100644
--- a/include/video/edid.h
+++ b/include/video/edid.h
@@ -1,14 +1,16 @@
1#ifndef __linux_video_edid_h__ 1#ifndef __linux_video_edid_h__
2#define __linux_video_edid_h__ 2#define __linux_video_edid_h__
3 3
4#if !defined(__KERNEL__) || defined(CONFIG_X86)
5
4struct edid_info { 6struct edid_info {
5 unsigned char dummy[128]; 7 unsigned char dummy[128];
6}; 8};
7 9
8#ifdef __KERNEL__ 10#ifdef __KERNEL__
9#ifdef CONFIG_X86
10extern struct edid_info edid_info; 11extern struct edid_info edid_info;
11#endif 12#endif /* __KERNEL__ */
13
12#endif 14#endif
13 15
14#endif /* __linux_video_edid_h__ */ 16#endif /* __linux_video_edid_h__ */
diff --git a/include/video/exynos_dp.h b/include/video/exynos_dp.h
deleted file mode 100644
index bd8cabd344d..00000000000
--- a/include/video/exynos_dp.h
+++ /dev/null
@@ -1,131 +0,0 @@
1/*
2 * Samsung SoC DP device support
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _EXYNOS_DP_H
13#define _EXYNOS_DP_H
14
15#define DP_TIMEOUT_LOOP_COUNT 100
16#define MAX_CR_LOOP 5
17#define MAX_EQ_LOOP 5
18
19enum link_rate_type {
20 LINK_RATE_1_62GBPS = 0x06,
21 LINK_RATE_2_70GBPS = 0x0a
22};
23
24enum link_lane_count_type {
25 LANE_COUNT1 = 1,
26 LANE_COUNT2 = 2,
27 LANE_COUNT4 = 4
28};
29
30enum link_training_state {
31 START,
32 CLOCK_RECOVERY,
33 EQUALIZER_TRAINING,
34 FINISHED,
35 FAILED
36};
37
38enum voltage_swing_level {
39 VOLTAGE_LEVEL_0,
40 VOLTAGE_LEVEL_1,
41 VOLTAGE_LEVEL_2,
42 VOLTAGE_LEVEL_3,
43};
44
45enum pre_emphasis_level {
46 PRE_EMPHASIS_LEVEL_0,
47 PRE_EMPHASIS_LEVEL_1,
48 PRE_EMPHASIS_LEVEL_2,
49 PRE_EMPHASIS_LEVEL_3,
50};
51
52enum pattern_set {
53 PRBS7,
54 D10_2,
55 TRAINING_PTN1,
56 TRAINING_PTN2,
57 DP_NONE
58};
59
60enum color_space {
61 COLOR_RGB,
62 COLOR_YCBCR422,
63 COLOR_YCBCR444
64};
65
66enum color_depth {
67 COLOR_6,
68 COLOR_8,
69 COLOR_10,
70 COLOR_12
71};
72
73enum color_coefficient {
74 COLOR_YCBCR601,
75 COLOR_YCBCR709
76};
77
78enum dynamic_range {
79 VESA,
80 CEA
81};
82
83enum pll_status {
84 PLL_UNLOCKED,
85 PLL_LOCKED
86};
87
88enum clock_recovery_m_value_type {
89 CALCULATED_M,
90 REGISTER_M
91};
92
93enum video_timing_recognition_type {
94 VIDEO_TIMING_FROM_CAPTURE,
95 VIDEO_TIMING_FROM_REGISTER
96};
97
98enum analog_power_block {
99 AUX_BLOCK,
100 CH0_BLOCK,
101 CH1_BLOCK,
102 CH2_BLOCK,
103 CH3_BLOCK,
104 ANALOG_TOTAL,
105 POWER_ALL
106};
107
108struct video_info {
109 char *name;
110
111 bool h_sync_polarity;
112 bool v_sync_polarity;
113 bool interlaced;
114
115 enum color_space color_space;
116 enum dynamic_range dynamic_range;
117 enum color_coefficient ycbcr_coeff;
118 enum color_depth color_depth;
119
120 enum link_rate_type link_rate;
121 enum link_lane_count_type lane_count;
122};
123
124struct exynos_dp_platdata {
125 struct video_info *video_info;
126
127 void (*phy_init)(void);
128 void (*phy_exit)(void);
129};
130
131#endif /* _EXYNOS_DP_H */
diff --git a/include/video/exynos_mipi_dsim.h b/include/video/exynos_mipi_dsim.h
deleted file mode 100644
index 83ce5e667d4..00000000000
--- a/include/video/exynos_mipi_dsim.h
+++ /dev/null
@@ -1,360 +0,0 @@
1/* include/video/exynos_mipi_dsim.h
2 *
3 * Platform data header for Samsung SoC MIPI-DSIM.
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd
6 *
7 * InKi Dae <inki.dae@samsung.com>
8 * Donghwa Lee <dh09.lee@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef _EXYNOS_MIPI_DSIM_H
16#define _EXYNOS_MIPI_DSIM_H
17
18#include <linux/device.h>
19#include <linux/fb.h>
20
21#define PANEL_NAME_SIZE (32)
22
23/*
24 * Enumerate display interface type.
25 *
26 * DSIM_COMMAND means cpu interface and rgb interface for DSIM_VIDEO.
27 *
28 * P.S. MIPI DSI Master has two display controller intefaces, RGB Interface
29 * for main display and CPU Interface(same as I80 Interface) for main
30 * and sub display.
31 */
32enum mipi_dsim_interface_type {
33 DSIM_COMMAND,
34 DSIM_VIDEO
35};
36
37enum mipi_dsim_virtual_ch_no {
38 DSIM_VIRTUAL_CH_0,
39 DSIM_VIRTUAL_CH_1,
40 DSIM_VIRTUAL_CH_2,
41 DSIM_VIRTUAL_CH_3
42};
43
44enum mipi_dsim_burst_mode_type {
45 DSIM_NON_BURST_SYNC_EVENT,
46 DSIM_BURST_SYNC_EVENT,
47 DSIM_NON_BURST_SYNC_PULSE,
48 DSIM_BURST,
49 DSIM_NON_VIDEO_MODE
50};
51
52enum mipi_dsim_no_of_data_lane {
53 DSIM_DATA_LANE_1,
54 DSIM_DATA_LANE_2,
55 DSIM_DATA_LANE_3,
56 DSIM_DATA_LANE_4
57};
58
59enum mipi_dsim_byte_clk_src {
60 DSIM_PLL_OUT_DIV8,
61 DSIM_EXT_CLK_DIV8,
62 DSIM_EXT_CLK_BYPASS
63};
64
65enum mipi_dsim_pixel_format {
66 DSIM_CMD_3BPP,
67 DSIM_CMD_8BPP,
68 DSIM_CMD_12BPP,
69 DSIM_CMD_16BPP,
70 DSIM_VID_16BPP_565,
71 DSIM_VID_18BPP_666PACKED,
72 DSIM_18BPP_666LOOSELYPACKED,
73 DSIM_24BPP_888
74};
75
76/*
77 * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
78 *
79 * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
80 * @eot_disable: enable or disable EoT packet in HS mode.
81 * @auto_vertical_cnt: specifies auto vertical count mode.
82 * in Video mode, the vertical line transition uses line counter
83 * configured by VSA, VBP, and Vertical resolution.
84 * If this bit is set to '1', the line counter does not use VSA and VBP
85 * registers.(in command mode, this variable is ignored)
86 * @hse: set horizontal sync event mode.
87 * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
88 * start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
89 * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
90 * (in mommand mode, this variable is ignored)
91 * @hfp: specifies HFP disable mode.
92 * if this variable is set, DSI master ignores HFP area in VIDEO mode.
93 * (in command mode, this variable is ignored)
94 * @hbp: specifies HBP disable mode.
95 * if this variable is set, DSI master ignores HBP area in VIDEO mode.
96 * (in command mode, this variable is ignored)
97 * @hsa: specifies HSA disable mode.
98 * if this variable is set, DSI master ignores HSA area in VIDEO mode.
99 * (in command mode, this variable is ignored)
100 * @cma_allow: specifies the number of horizontal lines, where command packet
101 * transmission is allowed after Stable VFP period.
102 * @e_interface: specifies interface to be used.(CPU or RGB interface)
103 * @e_virtual_ch: specifies virtual channel number that main or
104 * sub diaplsy uses.
105 * @e_pixel_format: specifies pixel stream format for main or sub display.
106 * @e_burst_mode: selects Burst mode in Video mode.
107 * in Non-burst mode, RGB data area is filled with RGB data and NULL
108 * packets, according to input bandwidth of RGB interface.
109 * In Burst mode, RGB data area is filled with RGB data only.
110 * @e_no_data_lane: specifies data lane count to be used by Master.
111 * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
112 * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
113 * @pll_stable_time: specifies the PLL Timer for stability of the ganerated
114 * clock(System clock cycle base)
115 * if the timer value goes to 0x00000000, the clock stable bit of status
116 * and interrupt register is set.
117 * @esc_clk: specifies escape clock frequency for getting the escape clock
118 * prescaler value.
119 * @stop_holding_cnt: specifies the interval value between transmitting
120 * read packet(or write "set_tear_on" command) and BTA request.
121 * after transmitting read packet or write "set_tear_on" command,
122 * BTA requests to D-PHY automatically. this counter value specifies
123 * the interval between them.
124 * @bta_timeout: specifies the timer for BTA.
125 * this register specifies time out from BTA request to change
126 * the direction with respect to Tx escape clock.
127 * @rx_timeout: specifies the timer for LP Rx mode timeout.
128 * this register specifies time out on how long RxValid deasserts,
129 * after RxLpdt asserts with respect to Tx escape clock.
130 * - RxValid specifies Rx data valid indicator.
131 * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
132 * - RxValid and RxLpdt specifies signal from D-PHY.
133 */
134struct mipi_dsim_config {
135 unsigned char auto_flush;
136 unsigned char eot_disable;
137
138 unsigned char auto_vertical_cnt;
139 unsigned char hse;
140 unsigned char hfp;
141 unsigned char hbp;
142 unsigned char hsa;
143 unsigned char cmd_allow;
144
145 enum mipi_dsim_interface_type e_interface;
146 enum mipi_dsim_virtual_ch_no e_virtual_ch;
147 enum mipi_dsim_pixel_format e_pixel_format;
148 enum mipi_dsim_burst_mode_type e_burst_mode;
149 enum mipi_dsim_no_of_data_lane e_no_data_lane;
150 enum mipi_dsim_byte_clk_src e_byte_clk;
151
152 /*
153 * ===========================================
154 * | P | M | S | MHz |
155 * -------------------------------------------
156 * | 3 | 100 | 3 | 100 |
157 * | 3 | 100 | 2 | 200 |
158 * | 3 | 63 | 1 | 252 |
159 * | 4 | 100 | 1 | 300 |
160 * | 4 | 110 | 1 | 330 |
161 * | 12 | 350 | 1 | 350 |
162 * | 3 | 100 | 1 | 400 |
163 * | 4 | 150 | 1 | 450 |
164 * | 6 | 118 | 1 | 472 |
165 * | 3 | 120 | 1 | 480 |
166 * | 12 | 250 | 0 | 500 |
167 * | 4 | 100 | 0 | 600 |
168 * | 3 | 81 | 0 | 648 |
169 * | 3 | 88 | 0 | 704 |
170 * | 3 | 90 | 0 | 720 |
171 * | 3 | 100 | 0 | 800 |
172 * | 12 | 425 | 0 | 850 |
173 * | 4 | 150 | 0 | 900 |
174 * | 12 | 475 | 0 | 950 |
175 * | 6 | 250 | 0 | 1000 |
176 * -------------------------------------------
177 */
178
179 /*
180 * pms could be calculated as the following.
181 * M * 24 / P * 2 ^ S = MHz
182 */
183 unsigned char p;
184 unsigned short m;
185 unsigned char s;
186
187 unsigned int pll_stable_time;
188 unsigned long esc_clk;
189
190 unsigned short stop_holding_cnt;
191 unsigned char bta_timeout;
192 unsigned short rx_timeout;
193};
194
195/*
196 * struct mipi_dsim_device - global interface for mipi-dsi driver.
197 *
198 * @dev: driver model representation of the device.
199 * @id: unique device id.
200 * @clock: pointer to MIPI-DSI clock of clock framework.
201 * @irq: interrupt number to MIPI-DSI controller.
202 * @reg_base: base address to memory mapped SRF of MIPI-DSI controller.
203 * (virtual address)
204 * @lock: the mutex protecting this data structure.
205 * @dsim_info: infomation for configuring mipi-dsi controller.
206 * @master_ops: callbacks to mipi-dsi operations.
207 * @dsim_lcd_dev: pointer to activated ddi device.
208 * (it would be registered by mipi-dsi driver.)
209 * @dsim_lcd_drv: pointer to activated_ddi driver.
210 * (it would be registered by mipi-dsi driver.)
211 * @lcd_info: pointer to mipi_lcd_info structure.
212 * @state: specifies status of MIPI-DSI controller.
213 * the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
214 * @data_lane: specifiec enabled data lane number.
215 * this variable would be set by driver according to e_no_data_lane
216 * automatically.
217 * @e_clk_src: select byte clock source.
218 * @pd: pointer to MIPI-DSI driver platform data.
219 */
220struct mipi_dsim_device {
221 struct device *dev;
222 int id;
223 struct resource *res;
224 struct clk *clock;
225 unsigned int irq;
226 void __iomem *reg_base;
227 struct mutex lock;
228
229 struct mipi_dsim_config *dsim_config;
230 struct mipi_dsim_master_ops *master_ops;
231 struct mipi_dsim_lcd_device *dsim_lcd_dev;
232 struct mipi_dsim_lcd_driver *dsim_lcd_drv;
233
234 unsigned int state;
235 unsigned int data_lane;
236 unsigned int e_clk_src;
237 bool suspended;
238
239 struct mipi_dsim_platform_data *pd;
240};
241
242/*
243 * struct mipi_dsim_platform_data - interface to platform data
244 * for mipi-dsi driver.
245 *
246 * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
247 * lcd panel driver searched would be actived.
248 * @dsim_config: pointer of structure for configuring mipi-dsi controller.
249 * @enabled: indicate whether mipi controller got enabled or not.
250 * @lcd_panel_info: pointer for lcd panel specific structure.
251 * this structure specifies width, height, timing and polarity and so on.
252 * @phy_enable: pointer to a callback controlling D-PHY enable/reset
253 */
254struct mipi_dsim_platform_data {
255 char lcd_panel_name[PANEL_NAME_SIZE];
256
257 struct mipi_dsim_config *dsim_config;
258 unsigned int enabled;
259 void *lcd_panel_info;
260
261 int (*phy_enable)(struct platform_device *pdev, bool on);
262};
263
264/*
265 * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
266 *
267 * @cmd_write: transfer command to lcd panel at LP mode.
268 * @cmd_read: read command from rx register.
269 * @get_dsim_frame_done: get the status that all screen data have been
270 * transferred to mipi-dsi.
271 * @clear_dsim_frame_done: clear frame done status.
272 * @get_fb_frame_done: get frame done status of display controller.
273 * @trigger: trigger display controller.
274 * - this one would be used only in case of CPU mode.
275 * @set_early_blank_mode: set framebuffer blank mode.
276 * - this callback should be called prior to fb_blank() by a client driver
277 * only if needing.
278 * @set_blank_mode: set framebuffer blank mode.
279 * - this callback should be called after fb_blank() by a client driver
280 * only if needing.
281 */
282
283struct mipi_dsim_master_ops {
284 int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
285 const unsigned char *data0, unsigned int data1);
286 int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
287 unsigned int data0, unsigned int req_size, u8 *rx_buf);
288 int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
289 int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
290
291 int (*get_fb_frame_done)(struct fb_info *info);
292 void (*trigger)(struct fb_info *info);
293 int (*set_early_blank_mode)(struct mipi_dsim_device *dsim, int power);
294 int (*set_blank_mode)(struct mipi_dsim_device *dsim, int power);
295};
296
297/*
298 * device structure for mipi-dsi based lcd panel.
299 *
300 * @name: name of the device to use with this device, or an
301 * alias for that name.
302 * @dev: driver model representation of the device.
303 * @id: id of device to be registered.
304 * @bus_id: bus id for identifing connected bus
305 * and this bus id should be same as id of mipi_dsim_device.
306 * @irq: irq number for signaling when framebuffer transfer of
307 * lcd panel module is completed.
308 * this irq would be used only for MIPI-DSI based CPU mode lcd panel.
309 * @master: pointer to mipi-dsi master device object.
310 * @platform_data: lcd panel specific platform data.
311 */
312struct mipi_dsim_lcd_device {
313 char *name;
314 struct device dev;
315 int id;
316 int bus_id;
317 int irq;
318 int panel_reverse;
319
320 struct mipi_dsim_device *master;
321 void *platform_data;
322};
323
324/*
325 * driver structure for mipi-dsi based lcd panel.
326 *
327 * this structure should be registered by lcd panel driver.
328 * mipi-dsi driver seeks lcd panel registered through name field
329 * and calls these callback functions in appropriate time.
330 *
331 * @name: name of the driver to use with this device, or an
332 * alias for that name.
333 * @id: id of driver to be registered.
334 * this id would be used for finding device object registered.
335 */
336struct mipi_dsim_lcd_driver {
337 char *name;
338 int id;
339
340 void (*power_on)(struct mipi_dsim_lcd_device *dsim_dev, int enable);
341 void (*set_sequence)(struct mipi_dsim_lcd_device *dsim_dev);
342 int (*probe)(struct mipi_dsim_lcd_device *dsim_dev);
343 int (*remove)(struct mipi_dsim_lcd_device *dsim_dev);
344 void (*shutdown)(struct mipi_dsim_lcd_device *dsim_dev);
345 int (*suspend)(struct mipi_dsim_lcd_device *dsim_dev);
346 int (*resume)(struct mipi_dsim_lcd_device *dsim_dev);
347};
348
349/*
350 * register mipi_dsim_lcd_device to mipi-dsi master.
351 */
352int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
353 *lcd_dev);
354/**
355 * register mipi_dsim_lcd_driver object defined by lcd panel driver
356 * to mipi-dsi driver.
357 */
358int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
359 *lcd_drv);
360#endif /* _EXYNOS_MIPI_DSIM_H */
diff --git a/include/video/omap-panel-n8x0.h b/include/video/omap-panel-n8x0.h
deleted file mode 100644
index 50a1302e2cf..00000000000
--- a/include/video/omap-panel-n8x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef __OMAP_PANEL_N8X0_H
2#define __OMAP_PANEL_N8X0_H
3
4struct omap_dss_device;
5
6struct panel_n8x0_data {
7 int (*platform_enable)(struct omap_dss_device *dssdev);
8 void (*platform_disable)(struct omap_dss_device *dssdev);
9 int panel_reset;
10 int ctrl_pwrdown;
11
12 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
13};
14
15#endif
diff --git a/include/video/omap-panel-nokia-dsi.h b/include/video/omap-panel-nokia-dsi.h
index 04219a29553..921ae932722 100644
--- a/include/video/omap-panel-nokia-dsi.h
+++ b/include/video/omap-panel-nokia-dsi.h
@@ -10,8 +10,9 @@ struct omap_dss_device;
10 * @ext_te_gpio: external TE GPIO 10 * @ext_te_gpio: external TE GPIO
11 * @esd_interval: interval of ESD checks, 0 = disabled (ms) 11 * @esd_interval: interval of ESD checks, 0 = disabled (ms)
12 * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms) 12 * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms)
13 * @use_dsi_backlight: true if panel uses DSI command to control backlight 13 * @max_backlight_level: maximum backlight level
14 * @pin_config: DSI pin configuration 14 * @set_backlight: pointer to backlight set function
15 * @get_backlight: pointer to backlight get function
15 */ 16 */
16struct nokia_dsi_panel_data { 17struct nokia_dsi_panel_data {
17 const char *name; 18 const char *name;
@@ -24,9 +25,9 @@ struct nokia_dsi_panel_data {
24 unsigned esd_interval; 25 unsigned esd_interval;
25 unsigned ulps_timeout; 26 unsigned ulps_timeout;
26 27
27 bool use_dsi_backlight; 28 int max_backlight_level;
28 29 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
29 struct omap_dsi_pin_config pin_config; 30 int (*get_backlight)(struct omap_dss_device *dssdev);
30}; 31};
31 32
32#endif /* __OMAP_NOKIA_DSI_PANEL_H */ 33#endif /* __OMAP_NOKIA_DSI_PANEL_H */
diff --git a/include/video/omap-panel-picodlp.h b/include/video/omap-panel-picodlp.h
deleted file mode 100644
index 1c342ef6f3a..00000000000
--- a/include/video/omap-panel-picodlp.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * panel data for picodlp panel
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * Author: Mayuresh Janorkar <mayur@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#ifndef __PANEL_PICODLP_H
13#define __PANEL_PICODLP_H
14/**
15 * struct : picodlp panel data
16 * picodlp_adapter_id: i2c_adapter number for picodlp
17 */
18struct picodlp_panel_data {
19 int picodlp_adapter_id;
20 int emu_done_gpio;
21 int pwrgood_gpio;
22};
23#endif /* __PANEL_PICODLP_H */
diff --git a/include/video/omap-panel-tfp410.h b/include/video/omap-panel-tfp410.h
deleted file mode 100644
index aef35e48bc7..00000000000
--- a/include/video/omap-panel-tfp410.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Header for TFP410 chip driver
3 *
4 * Copyright (C) 2011 Texas Instruments Inc
5 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef __OMAP_PANEL_TFP410_H
21#define __OMAP_PANEL_TFP410_H
22
23struct omap_dss_device;
24
25/**
26 * struct tfp410_platform_data - panel driver configuration data
27 * @i2c_bus_num: i2c bus id for the panel
28 * @power_down_gpio: gpio number for PD pin (or -1 if not available)
29 */
30struct tfp410_platform_data {
31 int i2c_bus_num;
32 int power_down_gpio;
33};
34
35#endif /* __OMAP_PANEL_TFP410_H */
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index caefa093337..3b55ef22f8d 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -21,7 +21,6 @@
21#include <linux/list.h> 21#include <linux/list.h>
22#include <linux/kobject.h> 22#include <linux/kobject.h>
23#include <linux/device.h> 23#include <linux/device.h>
24#include <linux/interrupt.h>
25 24
26#define DISPC_IRQ_FRAMEDONE (1 << 0) 25#define DISPC_IRQ_FRAMEDONE (1 << 0)
27#define DISPC_IRQ_VSYNC (1 << 1) 26#define DISPC_IRQ_VSYNC (1 << 1)
@@ -42,23 +41,11 @@
42#define DISPC_IRQ_WAKEUP (1 << 16) 41#define DISPC_IRQ_WAKEUP (1 << 16)
43#define DISPC_IRQ_SYNC_LOST2 (1 << 17) 42#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
44#define DISPC_IRQ_VSYNC2 (1 << 18) 43#define DISPC_IRQ_VSYNC2 (1 << 18)
45#define DISPC_IRQ_VID3_END_WIN (1 << 19)
46#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
47#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) 44#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
48#define DISPC_IRQ_FRAMEDONE2 (1 << 22) 45#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
49#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
50#define DISPC_IRQ_FRAMEDONETV (1 << 24)
51#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
52#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
53#define DISPC_IRQ_VSYNC3 (1 << 28)
54#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
55#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
56 46
57struct omap_dss_device; 47struct omap_dss_device;
58struct omap_overlay_manager; 48struct omap_overlay_manager;
59struct dss_lcd_mgr_config;
60struct snd_aes_iec958;
61struct snd_cea_861_aud_if;
62 49
63enum omap_display_type { 50enum omap_display_type {
64 OMAP_DISPLAY_TYPE_NONE = 0, 51 OMAP_DISPLAY_TYPE_NONE = 0,
@@ -73,16 +60,13 @@ enum omap_display_type {
73enum omap_plane { 60enum omap_plane {
74 OMAP_DSS_GFX = 0, 61 OMAP_DSS_GFX = 0,
75 OMAP_DSS_VIDEO1 = 1, 62 OMAP_DSS_VIDEO1 = 1,
76 OMAP_DSS_VIDEO2 = 2, 63 OMAP_DSS_VIDEO2 = 2
77 OMAP_DSS_VIDEO3 = 3,
78 OMAP_DSS_WB = 4,
79}; 64};
80 65
81enum omap_channel { 66enum omap_channel {
82 OMAP_DSS_CHANNEL_LCD = 0, 67 OMAP_DSS_CHANNEL_LCD = 0,
83 OMAP_DSS_CHANNEL_DIGIT = 1, 68 OMAP_DSS_CHANNEL_DIGIT = 1,
84 OMAP_DSS_CHANNEL_LCD2 = 2, 69 OMAP_DSS_CHANNEL_LCD2 = 2,
85 OMAP_DSS_CHANNEL_LCD3 = 3,
86}; 70};
87 71
88enum omap_color_mode { 72enum omap_color_mode {
@@ -107,6 +91,11 @@ enum omap_color_mode {
107 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ 91 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
108}; 92};
109 93
94enum omap_lcd_display_type {
95 OMAP_DSS_LCD_DISPLAY_STN,
96 OMAP_DSS_LCD_DISPLAY_TFT,
97};
98
110enum omap_dss_load_mode { 99enum omap_dss_load_mode {
111 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, 100 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
112 OMAP_DSS_LOAD_CLUT_ONLY = 1, 101 OMAP_DSS_LOAD_CLUT_ONLY = 1,
@@ -124,15 +113,15 @@ enum omap_rfbi_te_mode {
124 OMAP_DSS_RFBI_TE_MODE_2 = 2, 113 OMAP_DSS_RFBI_TE_MODE_2 = 2,
125}; 114};
126 115
127enum omap_dss_signal_level { 116enum omap_panel_config {
128 OMAPDSS_SIG_ACTIVE_HIGH = 0, 117 OMAP_DSS_LCD_IVS = 1<<0,
129 OMAPDSS_SIG_ACTIVE_LOW = 1, 118 OMAP_DSS_LCD_IHS = 1<<1,
130}; 119 OMAP_DSS_LCD_IPC = 1<<2,
120 OMAP_DSS_LCD_IEO = 1<<3,
121 OMAP_DSS_LCD_RF = 1<<4,
122 OMAP_DSS_LCD_ONOFF = 1<<5,
131 123
132enum omap_dss_signal_edge { 124 OMAP_DSS_LCD_TFT = 1<<20,
133 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
134 OMAPDSS_DRIVE_SIG_RISING_EDGE,
135 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
136}; 125};
137 126
138enum omap_dss_venc_type { 127enum omap_dss_venc_type {
@@ -140,18 +129,6 @@ enum omap_dss_venc_type {
140 OMAP_DSS_VENC_TYPE_SVIDEO, 129 OMAP_DSS_VENC_TYPE_SVIDEO,
141}; 130};
142 131
143enum omap_dss_dsi_pixel_format {
144 OMAP_DSS_DSI_FMT_RGB888,
145 OMAP_DSS_DSI_FMT_RGB666,
146 OMAP_DSS_DSI_FMT_RGB666_PACKED,
147 OMAP_DSS_DSI_FMT_RGB565,
148};
149
150enum omap_dss_dsi_mode {
151 OMAP_DSS_DSI_CMD_MODE = 0,
152 OMAP_DSS_DSI_VIDEO_MODE,
153};
154
155enum omap_display_caps { 132enum omap_display_caps {
156 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, 133 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
157 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, 134 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
@@ -160,19 +137,19 @@ enum omap_display_caps {
160enum omap_dss_display_state { 137enum omap_dss_display_state {
161 OMAP_DSS_DISPLAY_DISABLED = 0, 138 OMAP_DSS_DISPLAY_DISABLED = 0,
162 OMAP_DSS_DISPLAY_ACTIVE, 139 OMAP_DSS_DISPLAY_ACTIVE,
140 OMAP_DSS_DISPLAY_SUSPENDED,
163}; 141};
164 142
165enum omap_dss_audio_state { 143/* XXX perhaps this should be removed */
166 OMAP_DSS_AUDIO_DISABLED = 0, 144enum omap_dss_overlay_managers {
167 OMAP_DSS_AUDIO_ENABLED, 145 OMAP_DSS_OVL_MGR_LCD,
168 OMAP_DSS_AUDIO_CONFIGURED, 146 OMAP_DSS_OVL_MGR_TV,
169 OMAP_DSS_AUDIO_PLAYING, 147 OMAP_DSS_OVL_MGR_LCD2,
170}; 148};
171 149
172enum omap_dss_rotation_type { 150enum omap_dss_rotation_type {
173 OMAP_DSS_ROT_DMA = 1 << 0, 151 OMAP_DSS_ROT_DMA = 0,
174 OMAP_DSS_ROT_VRFB = 1 << 1, 152 OMAP_DSS_ROT_VRFB = 1,
175 OMAP_DSS_ROT_TILER = 1 << 2,
176}; 153};
177 154
178/* clockwise rotation angle */ 155/* clockwise rotation angle */
@@ -185,15 +162,11 @@ enum omap_dss_rotation_angle {
185 162
186enum omap_overlay_caps { 163enum omap_overlay_caps {
187 OMAP_DSS_OVL_CAP_SCALE = 1 << 0, 164 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
188 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, 165 OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
189 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
190 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
191 OMAP_DSS_OVL_CAP_POS = 1 << 4,
192 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
193}; 166};
194 167
195enum omap_overlay_manager_caps { 168enum omap_overlay_manager_caps {
196 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ 169 OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
197}; 170};
198 171
199enum omap_dss_clk_source { 172enum omap_dss_clk_source {
@@ -207,20 +180,6 @@ enum omap_dss_clk_source {
207 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ 180 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
208}; 181};
209 182
210enum omap_hdmi_flags {
211 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
212};
213
214enum omap_dss_output_id {
215 OMAP_DSS_OUTPUT_DPI = 1 << 0,
216 OMAP_DSS_OUTPUT_DBI = 1 << 1,
217 OMAP_DSS_OUTPUT_SDI = 1 << 2,
218 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
219 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
220 OMAP_DSS_OUTPUT_VENC = 1 << 5,
221 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
222};
223
224/* RFBI */ 183/* RFBI */
225 184
226struct rfbi_timings { 185struct rfbi_timings {
@@ -256,77 +215,26 @@ void rfbi_bus_lock(void);
256void rfbi_bus_unlock(void); 215void rfbi_bus_unlock(void);
257 216
258/* DSI */ 217/* DSI */
259
260struct omap_dss_dsi_videomode_timings {
261 /* DSI video mode blanking data */
262 /* Unit: byte clock cycles */
263 u16 hsa;
264 u16 hfp;
265 u16 hbp;
266 /* Unit: line clocks */
267 u16 vsa;
268 u16 vfp;
269 u16 vbp;
270
271 /* DSI blanking modes */
272 int blanking_mode;
273 int hsa_blanking_mode;
274 int hbp_blanking_mode;
275 int hfp_blanking_mode;
276
277 /* Video port sync events */
278 bool vp_vsync_end;
279 bool vp_hsync_end;
280
281 bool ddr_clk_always_on;
282 int window_sync;
283};
284
285void dsi_bus_lock(struct omap_dss_device *dssdev); 218void dsi_bus_lock(struct omap_dss_device *dssdev);
286void dsi_bus_unlock(struct omap_dss_device *dssdev); 219void dsi_bus_unlock(struct omap_dss_device *dssdev);
287int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 220int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
288 int len); 221 int len);
289int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 222int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
290 int len); 223 u8 dcs_cmd);
291int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
292int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
293int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 224int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
294 u8 param); 225 u8 param);
295int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
296 u8 param);
297int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
298 u8 param1, u8 param2);
299int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 226int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
300 u8 *data, int len); 227 u8 *data, int len);
301int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
302 u8 *data, int len);
303int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 228int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
304 u8 *buf, int buflen); 229 u8 *buf, int buflen);
305int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, 230int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
306 int buflen); 231 u8 *data);
307int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, 232int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
308 u8 *buf, int buflen); 233 u8 *data1, u8 *data2);
309int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
310 u8 param1, u8 param2, u8 *buf, int buflen);
311int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 234int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
312 u16 len); 235 u16 len);
313int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); 236int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
314int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); 237int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
315int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
316void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
317
318enum omapdss_version {
319 OMAPDSS_VER_UNKNOWN = 0,
320 OMAPDSS_VER_OMAP24xx,
321 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
322 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
323 OMAPDSS_VER_OMAP3630,
324 OMAPDSS_VER_AM35xx,
325 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
326 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
327 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
328 OMAPDSS_VER_OMAP5,
329};
330 238
331/* Board specific data */ 239/* Board specific data */
332struct omap_dss_board_info { 240struct omap_dss_board_info {
@@ -334,16 +242,23 @@ struct omap_dss_board_info {
334 int num_devices; 242 int num_devices;
335 struct omap_dss_device **devices; 243 struct omap_dss_device **devices;
336 struct omap_dss_device *default_device; 244 struct omap_dss_device *default_device;
337 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); 245 void (*dsi_mux_pads)(bool enable);
338 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
339 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
340 enum omapdss_version version;
341}; 246};
342 247
248#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
343/* Init with the board info */ 249/* Init with the board info */
344extern int omap_display_init(struct omap_dss_board_info *board_data); 250extern int omap_display_init(struct omap_dss_board_info *board_data);
345/* HDMI mux init*/ 251#else
346extern int omap_hdmi_init(enum omap_hdmi_flags flags); 252static inline int omap_display_init(struct omap_dss_board_info *board_data)
253{
254 return 0;
255}
256#endif
257
258struct omap_display_platform_data {
259 struct omap_dss_board_info *board_data;
260 /* TODO: Additional members to be added when PM is considered */
261};
347 262
348struct omap_video_timings { 263struct omap_video_timings {
349 /* Unit: pixels */ 264 /* Unit: pixels */
@@ -364,19 +279,6 @@ struct omap_video_timings {
364 u16 vfp; /* Vertical front porch */ 279 u16 vfp; /* Vertical front porch */
365 /* Unit: line clocks */ 280 /* Unit: line clocks */
366 u16 vbp; /* Vertical back porch */ 281 u16 vbp; /* Vertical back porch */
367
368 /* Vsync logic level */
369 enum omap_dss_signal_level vsync_level;
370 /* Hsync logic level */
371 enum omap_dss_signal_level hsync_level;
372 /* Interlaced or Progressive timings */
373 bool interlace;
374 /* Pixel clock edge to drive LCD data */
375 enum omap_dss_signal_edge data_pclk_edge;
376 /* Data enable logic level */
377 enum omap_dss_signal_level de_level;
378 /* Pixel clock edges to drive HSYNC and VSYNC signals */
379 enum omap_dss_signal_edge sync_pclk_edge;
380}; 282};
381 283
382#ifdef CONFIG_OMAP2_DSS_VENC 284#ifdef CONFIG_OMAP2_DSS_VENC
@@ -395,7 +297,10 @@ struct omap_dss_cpr_coefs {
395}; 297};
396 298
397struct omap_overlay_info { 299struct omap_overlay_info {
300 bool enabled;
301
398 u32 paddr; 302 u32 paddr;
303 void __iomem *vaddr;
399 u32 p_uv_addr; /* for NV12 format */ 304 u32 p_uv_addr; /* for NV12 format */
400 u16 screen_width; 305 u16 screen_width;
401 u16 width; 306 u16 width;
@@ -411,7 +316,6 @@ struct omap_overlay_info {
411 u16 out_height; /* if 0, out_height == height */ 316 u16 out_height; /* if 0, out_height == height */
412 u8 global_alpha; 317 u8 global_alpha;
413 u8 pre_mult_alpha; 318 u8 pre_mult_alpha;
414 u8 zorder;
415}; 319};
416 320
417struct omap_overlay { 321struct omap_overlay {
@@ -420,27 +324,16 @@ struct omap_overlay {
420 324
421 /* static fields */ 325 /* static fields */
422 const char *name; 326 const char *name;
423 enum omap_plane id; 327 int id;
424 enum omap_color_mode supported_modes; 328 enum omap_color_mode supported_modes;
425 enum omap_overlay_caps caps; 329 enum omap_overlay_caps caps;
426 330
427 /* dynamic fields */ 331 /* dynamic fields */
428 struct omap_overlay_manager *manager; 332 struct omap_overlay_manager *manager;
333 struct omap_overlay_info info;
429 334
430 /* 335 /* if true, info has been changed, but not applied() yet */
431 * The following functions do not block: 336 bool info_dirty;
432 *
433 * is_enabled
434 * set_overlay_info
435 * get_overlay_info
436 *
437 * The rest of the functions may block and cannot be called from
438 * interrupt context
439 */
440
441 int (*enable)(struct omap_overlay *ovl);
442 int (*disable)(struct omap_overlay *ovl);
443 bool (*is_enabled)(struct omap_overlay *ovl);
444 337
445 int (*set_manager)(struct omap_overlay *ovl, 338 int (*set_manager)(struct omap_overlay *ovl,
446 struct omap_overlay_manager *mgr); 339 struct omap_overlay_manager *mgr);
@@ -452,8 +345,6 @@ struct omap_overlay {
452 struct omap_overlay_info *info); 345 struct omap_overlay_info *info);
453 346
454 int (*wait_for_go)(struct omap_overlay *ovl); 347 int (*wait_for_go)(struct omap_overlay *ovl);
455
456 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
457}; 348};
458 349
459struct omap_overlay_manager_info { 350struct omap_overlay_manager_info {
@@ -463,7 +354,7 @@ struct omap_overlay_manager_info {
463 u32 trans_key; 354 u32 trans_key;
464 bool trans_enabled; 355 bool trans_enabled;
465 356
466 bool partial_alpha_enabled; 357 bool alpha_enabled;
467 358
468 bool cpr_enable; 359 bool cpr_enable;
469 struct omap_dss_cpr_coefs cpr_coefs; 360 struct omap_dss_cpr_coefs cpr_coefs;
@@ -471,32 +362,27 @@ struct omap_overlay_manager_info {
471 362
472struct omap_overlay_manager { 363struct omap_overlay_manager {
473 struct kobject kobj; 364 struct kobject kobj;
365 struct list_head list;
474 366
475 /* static fields */ 367 /* static fields */
476 const char *name; 368 const char *name;
477 enum omap_channel id; 369 int id;
478 enum omap_overlay_manager_caps caps; 370 enum omap_overlay_manager_caps caps;
479 struct list_head overlays; 371 int num_overlays;
372 struct omap_overlay **overlays;
480 enum omap_display_type supported_displays; 373 enum omap_display_type supported_displays;
481 enum omap_dss_output_id supported_outputs;
482 374
483 /* dynamic fields */ 375 /* dynamic fields */
484 struct omap_dss_output *output; 376 struct omap_dss_device *device;
485 377 struct omap_overlay_manager_info info;
486 /* 378
487 * The following functions do not block: 379 bool device_changed;
488 * 380 /* if true, info has been changed but not applied() yet */
489 * set_manager_info 381 bool info_dirty;
490 * get_manager_info 382
491 * apply 383 int (*set_device)(struct omap_overlay_manager *mgr,
492 * 384 struct omap_dss_device *dssdev);
493 * The rest of the functions may block and cannot be called from 385 int (*unset_device)(struct omap_overlay_manager *mgr);
494 * interrupt context
495 */
496
497 int (*set_output)(struct omap_overlay_manager *mgr,
498 struct omap_dss_output *output);
499 int (*unset_output)(struct omap_overlay_manager *mgr);
500 386
501 int (*set_manager_info)(struct omap_overlay_manager *mgr, 387 int (*set_manager_info)(struct omap_overlay_manager *mgr,
502 struct omap_overlay_manager_info *info); 388 struct omap_overlay_manager_info *info);
@@ -507,53 +393,8 @@ struct omap_overlay_manager {
507 int (*wait_for_go)(struct omap_overlay_manager *mgr); 393 int (*wait_for_go)(struct omap_overlay_manager *mgr);
508 int (*wait_for_vsync)(struct omap_overlay_manager *mgr); 394 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
509 395
510 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr); 396 int (*enable)(struct omap_overlay_manager *mgr);
511}; 397 int (*disable)(struct omap_overlay_manager *mgr);
512
513/* 22 pins means 1 clk lane and 10 data lanes */
514#define OMAP_DSS_MAX_DSI_PINS 22
515
516struct omap_dsi_pin_config {
517 int num_pins;
518 /*
519 * pin numbers in the following order:
520 * clk+, clk-
521 * data1+, data1-
522 * data2+, data2-
523 * ...
524 */
525 int pins[OMAP_DSS_MAX_DSI_PINS];
526};
527
528struct omap_dss_writeback_info {
529 u32 paddr;
530 u32 p_uv_addr;
531 u16 buf_width;
532 u16 width;
533 u16 height;
534 enum omap_color_mode color_mode;
535 u8 rotation;
536 enum omap_dss_rotation_type rotation_type;
537 bool mirror;
538 u8 pre_mult_alpha;
539};
540
541struct omap_dss_output {
542 struct list_head list;
543
544 /* display type supported by the output */
545 enum omap_display_type type;
546
547 /* output instance */
548 enum omap_dss_output_id id;
549
550 /* output's platform device pointer */
551 struct platform_device *pdev;
552
553 /* dynamic fields */
554 struct omap_overlay_manager *manager;
555
556 struct omap_dss_device *device;
557}; 398};
558 399
559struct omap_dss_device { 400struct omap_dss_device {
@@ -578,6 +419,17 @@ struct omap_dss_device {
578 } sdi; 419 } sdi;
579 420
580 struct { 421 struct {
422 u8 clk_lane;
423 u8 clk_pol;
424 u8 data1_lane;
425 u8 data1_pol;
426 u8 data2_lane;
427 u8 data2_pol;
428 u8 data3_lane;
429 u8 data3_pol;
430 u8 data4_lane;
431 u8 data4_pol;
432
581 int module; 433 int module;
582 434
583 bool ext_te; 435 bool ext_te;
@@ -602,7 +454,6 @@ struct omap_dss_device {
602 } dispc; 454 } dispc;
603 455
604 struct { 456 struct {
605 /* regn is one greater than TRM's REGN value */
606 u16 regn; 457 u16 regn;
607 u16 regm; 458 u16 regm;
608 u16 regm_dispc; 459 u16 regm_dispc;
@@ -613,7 +464,6 @@ struct omap_dss_device {
613 } dsi; 464 } dsi;
614 465
615 struct { 466 struct {
616 /* regn is one greater than TRM's REGN value */
617 u16 regn; 467 u16 regn;
618 u16 regm2; 468 u16 regm2;
619 } hdmi; 469 } hdmi;
@@ -622,9 +472,11 @@ struct omap_dss_device {
622 struct { 472 struct {
623 struct omap_video_timings timings; 473 struct omap_video_timings timings;
624 474
625 enum omap_dss_dsi_pixel_format dsi_pix_fmt; 475 int acbi; /* ac-bias pin transitions per interrupt */
626 enum omap_dss_dsi_mode dsi_mode; 476 /* Unit: line clocks */
627 struct omap_dss_dsi_videomode_timings dsi_vm_timings; 477 int acb; /* ac-bias pin frequency */
478
479 enum omap_panel_config config;
628 } panel; 480 } panel;
629 481
630 struct { 482 struct {
@@ -650,12 +502,10 @@ struct omap_dss_device {
650 502
651 enum omap_display_caps caps; 503 enum omap_display_caps caps;
652 504
653 struct omap_dss_output *output; 505 struct omap_overlay_manager *manager;
654 506
655 enum omap_dss_display_state state; 507 enum omap_dss_display_state state;
656 508
657 enum omap_dss_audio_state audio_state;
658
659 /* platform specific */ 509 /* platform specific */
660 int (*platform_enable)(struct omap_dss_device *dssdev); 510 int (*platform_enable)(struct omap_dss_device *dssdev);
661 void (*platform_disable)(struct omap_dss_device *dssdev); 511 void (*platform_disable)(struct omap_dss_device *dssdev);
@@ -663,18 +513,6 @@ struct omap_dss_device {
663 int (*get_backlight)(struct omap_dss_device *dssdev); 513 int (*get_backlight)(struct omap_dss_device *dssdev);
664}; 514};
665 515
666struct omap_dss_hdmi_data
667{
668 int ct_cp_hpd_gpio;
669 int ls_oe_gpio;
670 int hpd_gpio;
671};
672
673struct omap_dss_audio {
674 struct snd_aes_iec958 *iec;
675 struct snd_cea_861_aud_if *cea;
676};
677
678struct omap_dss_driver { 516struct omap_dss_driver {
679 struct device_driver driver; 517 struct device_driver driver;
680 518
@@ -683,6 +521,8 @@ struct omap_dss_driver {
683 521
684 int (*enable)(struct omap_dss_device *display); 522 int (*enable)(struct omap_dss_device *display);
685 void (*disable)(struct omap_dss_device *display); 523 void (*disable)(struct omap_dss_device *display);
524 int (*suspend)(struct omap_dss_device *display);
525 int (*resume)(struct omap_dss_device *display);
686 int (*run_test)(struct omap_dss_device *display, int test); 526 int (*run_test)(struct omap_dss_device *display, int test);
687 527
688 int (*update)(struct omap_dss_device *dssdev, 528 int (*update)(struct omap_dss_device *dssdev,
@@ -717,31 +557,8 @@ struct omap_dss_driver {
717 557
718 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); 558 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
719 u32 (*get_wss)(struct omap_dss_device *dssdev); 559 u32 (*get_wss)(struct omap_dss_device *dssdev);
720
721 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
722 bool (*detect)(struct omap_dss_device *dssdev);
723
724 /*
725 * For display drivers that support audio. This encompasses
726 * HDMI and DisplayPort at the moment.
727 */
728 /*
729 * Note: These functions might sleep. Do not call while
730 * holding a spinlock/readlock.
731 */
732 int (*audio_enable)(struct omap_dss_device *dssdev);
733 void (*audio_disable)(struct omap_dss_device *dssdev);
734 bool (*audio_supported)(struct omap_dss_device *dssdev);
735 int (*audio_config)(struct omap_dss_device *dssdev,
736 struct omap_dss_audio *audio);
737 /* Note: These functions may not sleep */
738 int (*audio_start)(struct omap_dss_device *dssdev);
739 void (*audio_stop)(struct omap_dss_device *dssdev);
740
741}; 560};
742 561
743enum omapdss_version omapdss_get_version(void);
744
745int omap_dss_register_driver(struct omap_dss_driver *); 562int omap_dss_register_driver(struct omap_dss_driver *);
746void omap_dss_unregister_driver(struct omap_dss_driver *); 563void omap_dss_unregister_driver(struct omap_dss_driver *);
747 564
@@ -751,77 +568,27 @@ void omap_dss_put_device(struct omap_dss_device *dssdev);
751struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); 568struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
752struct omap_dss_device *omap_dss_find_device(void *data, 569struct omap_dss_device *omap_dss_find_device(void *data,
753 int (*match)(struct omap_dss_device *dssdev, void *data)); 570 int (*match)(struct omap_dss_device *dssdev, void *data));
754const char *omapdss_get_default_display_name(void);
755 571
756int omap_dss_start_device(struct omap_dss_device *dssdev); 572int omap_dss_start_device(struct omap_dss_device *dssdev);
757void omap_dss_stop_device(struct omap_dss_device *dssdev); 573void omap_dss_stop_device(struct omap_dss_device *dssdev);
758 574
759int dss_feat_get_num_mgrs(void);
760int dss_feat_get_num_ovls(void);
761enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
762enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
763enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
764
765
766
767int omap_dss_get_num_overlay_managers(void); 575int omap_dss_get_num_overlay_managers(void);
768struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); 576struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
769 577
770int omap_dss_get_num_overlays(void); 578int omap_dss_get_num_overlays(void);
771struct omap_overlay *omap_dss_get_overlay(int num); 579struct omap_overlay *omap_dss_get_overlay(int num);
772 580
773struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
774int omapdss_output_set_device(struct omap_dss_output *out,
775 struct omap_dss_device *dssdev);
776int omapdss_output_unset_device(struct omap_dss_output *out);
777
778void omapdss_default_get_resolution(struct omap_dss_device *dssdev, 581void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
779 u16 *xres, u16 *yres); 582 u16 *xres, u16 *yres);
780int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); 583int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
781void omapdss_default_get_timings(struct omap_dss_device *dssdev,
782 struct omap_video_timings *timings);
783 584
784typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 585typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
785int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 586int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
786int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 587int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
787 588
788u32 dispc_read_irqstatus(void); 589int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
789void dispc_clear_irqstatus(u32 mask); 590int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
790u32 dispc_read_irqenable(void); 591 unsigned long timeout);
791void dispc_write_irqenable(u32 mask);
792
793int dispc_request_irq(irq_handler_t handler, void *dev_id);
794void dispc_free_irq(void *dev_id);
795
796int dispc_runtime_get(void);
797void dispc_runtime_put(void);
798
799void dispc_mgr_enable(enum omap_channel channel, bool enable);
800bool dispc_mgr_is_enabled(enum omap_channel channel);
801u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
802u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
803u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
804bool dispc_mgr_go_busy(enum omap_channel channel);
805void dispc_mgr_go(enum omap_channel channel);
806void dispc_mgr_set_lcd_config(enum omap_channel channel,
807 const struct dss_lcd_mgr_config *config);
808void dispc_mgr_set_timings(enum omap_channel channel,
809 const struct omap_video_timings *timings);
810void dispc_mgr_setup(enum omap_channel channel,
811 const struct omap_overlay_manager_info *info);
812
813int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
814 const struct omap_overlay_info *oi,
815 const struct omap_video_timings *timings,
816 int *x_predecim, int *y_predecim);
817
818int dispc_ovl_enable(enum omap_plane plane, bool enable);
819bool dispc_ovl_enabled(enum omap_plane plane);
820void dispc_ovl_set_channel_out(enum omap_plane plane,
821 enum omap_channel channel);
822int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
823 bool replication, const struct omap_video_timings *mgr_timings,
824 bool mem_to_mem);
825 592
826#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) 593#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
827#define to_dss_device(x) container_of((x), struct omap_dss_device, dev) 594#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
@@ -829,25 +596,17 @@ int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
829void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 596void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
830 bool enable); 597 bool enable);
831int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); 598int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
832void omapdss_dsi_set_timings(struct omap_dss_device *dssdev, 599
833 struct omap_video_timings *timings); 600int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
834void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h); 601 u16 *x, u16 *y, u16 *w, u16 *h,
835void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev, 602 bool enlarge_update_area);
836 enum omap_dss_dsi_pixel_format fmt); 603int omap_dsi_update(struct omap_dss_device *dssdev,
837void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev, 604 int channel,
838 enum omap_dss_dsi_mode mode); 605 u16 x, u16 y, u16 w, u16 h,
839void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
840 struct omap_dss_dsi_videomode_timings *timings);
841
842int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
843 void (*callback)(int, void *), void *data); 606 void (*callback)(int, void *), void *data);
844int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); 607int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
845int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); 608int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
846void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); 609void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
847int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
848 const struct omap_dsi_pin_config *pin_cfg);
849int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
850 unsigned long ddr_clk, unsigned long lp_clk);
851 610
852int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); 611int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
853void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, 612void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
@@ -855,60 +614,22 @@ void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
855 614
856int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); 615int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
857void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); 616void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
858void omapdss_dpi_set_timings(struct omap_dss_device *dssdev, 617void dpi_set_timings(struct omap_dss_device *dssdev,
859 struct omap_video_timings *timings); 618 struct omap_video_timings *timings);
860int dpi_check_timings(struct omap_dss_device *dssdev, 619int dpi_check_timings(struct omap_dss_device *dssdev,
861 struct omap_video_timings *timings); 620 struct omap_video_timings *timings);
862void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
863 621
864int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); 622int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
865void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); 623void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
866void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
867 struct omap_video_timings *timings);
868void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
869 624
870int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); 625int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
871void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); 626void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
872int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *), 627int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
873 void *data); 628 u16 *x, u16 *y, u16 *w, u16 *h);
874int omap_rfbi_configure(struct omap_dss_device *dssdev); 629int omap_rfbi_update(struct omap_dss_device *dssdev,
875void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h); 630 u16 x, u16 y, u16 w, u16 h,
876void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev, 631 void (*callback)(void *), void *data);
877 int pixel_size); 632int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
878void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
879 int data_lines); 633 int data_lines);
880void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
881 struct rfbi_timings *timings);
882
883int omapdss_compat_init(void);
884void omapdss_compat_uninit(void);
885
886struct dss_mgr_ops {
887 void (*start_update)(struct omap_overlay_manager *mgr);
888 int (*enable)(struct omap_overlay_manager *mgr);
889 void (*disable)(struct omap_overlay_manager *mgr);
890 void (*set_timings)(struct omap_overlay_manager *mgr,
891 const struct omap_video_timings *timings);
892 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
893 const struct dss_lcd_mgr_config *config);
894 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
895 void (*handler)(void *), void *data);
896 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
897 void (*handler)(void *), void *data);
898};
899 634
900int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
901void dss_uninstall_mgr_ops(void);
902
903void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
904 const struct omap_video_timings *timings);
905void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
906 const struct dss_lcd_mgr_config *config);
907int dss_mgr_enable(struct omap_overlay_manager *mgr);
908void dss_mgr_disable(struct omap_overlay_manager *mgr);
909void dss_mgr_start_update(struct omap_overlay_manager *mgr);
910int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
911 void (*handler)(void *), void *data);
912void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
913 void (*handler)(void *), void *data);
914#endif 635#endif
diff --git a/include/video/omapvrfb.h b/include/video/omapvrfb.h
deleted file mode 100644
index bb0bd89f8bc..00000000000
--- a/include/video/omapvrfb.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * VRFB Rotation Engine
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#ifndef __OMAP_VRFB_H__
22#define __OMAP_VRFB_H__
23
24#define OMAP_VRFB_LINE_LEN 2048
25
26struct vrfb {
27 u8 context;
28 void __iomem *vaddr[4];
29 unsigned long paddr[4];
30 u16 xres;
31 u16 yres;
32 u16 xoffset;
33 u16 yoffset;
34 u8 bytespp;
35 bool yuv_mode;
36};
37
38#ifdef CONFIG_OMAP2_VRFB
39extern bool omap_vrfb_supported(void);
40extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
41extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
42extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
43 u8 bytespp);
44extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
45extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
46extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
47 u16 width, u16 height,
48 unsigned bytespp, bool yuv_mode);
49extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
50extern void omap_vrfb_restore_context(void);
51
52#else
53static inline bool omap_vrfb_supported(void) { return false; }
54static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
55static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
56static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
57 u8 bytespp) {}
58static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
59 { return 0; }
60static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
61 { return 0; }
62static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
63 u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
64static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
65 { return 0; }
66static inline void omap_vrfb_restore_context(void) {}
67#endif
68#endif /* __VRFB_H */
diff --git a/include/video/sa1100fb.h b/include/video/sa1100fb.h
deleted file mode 100644
index 4ab40965378..00000000000
--- a/include/video/sa1100fb.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * StrongARM 1100 LCD Controller Frame Buffer Device
3 *
4 * Copyright (C) 1999 Eric A. Thomas
5 * Based on acornfb.c Copyright (C) Russell King.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 */
11#ifndef _VIDEO_SA1100FB_H
12#define _VIDEO_SA1100FB_H
13
14#include <linux/fb.h>
15#include <linux/types.h>
16
17#define RGB_4 0
18#define RGB_8 1
19#define RGB_16 2
20#define NR_RGB 3
21
22/* These are the bitfields for each display depth that we support. */
23struct sa1100fb_rgb {
24 struct fb_bitfield red;
25 struct fb_bitfield green;
26 struct fb_bitfield blue;
27 struct fb_bitfield transp;
28};
29
30/* This structure describes the machine which we are running on. */
31struct sa1100fb_mach_info {
32 u_long pixclock;
33
34 u_short xres;
35 u_short yres;
36
37 u_char bpp;
38 u_char hsync_len;
39 u_char left_margin;
40 u_char right_margin;
41
42 u_char vsync_len;
43 u_char upper_margin;
44 u_char lower_margin;
45 u_char sync;
46
47 u_int cmap_greyscale:1,
48 cmap_inverse:1,
49 cmap_static:1,
50 unused:29;
51
52 u_int lccr0;
53 u_int lccr3;
54
55 /* Overrides for the default RGB maps */
56 const struct sa1100fb_rgb *rgb[NR_RGB];
57
58 void (*backlight_power)(int);
59 void (*lcd_power)(int);
60 void (*set_visual)(u32);
61};
62
63#endif
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
deleted file mode 100644
index e7554486a2b..00000000000
--- a/include/video/samsung_fimd.h
+++ /dev/null
@@ -1,469 +0,0 @@
1/* include/video/samsung_fimd.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - new-style fimd and framebuffer register definitions
9 *
10 * This is the register set for the fimd and new style framebuffer interface
11 * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
12 * S3C64XX series such as the S3C6400 and S3C6410.
13 *
14 * The file does not contain the cpu specific items which are based on
15 * whichever architecture is selected, it only contains the core of the
16 * register set. See <mach/regs-fb.h> to get the specifics.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21*/
22
23/* VIDCON0 */
24
25#define VIDCON0 (0x00)
26#define VIDCON0_INTERLACE (1 << 29)
27#define VIDCON0_VIDOUT_MASK (0x7 << 26)
28#define VIDCON0_VIDOUT_SHIFT (26)
29#define VIDCON0_VIDOUT_RGB (0x0 << 26)
30#define VIDCON0_VIDOUT_TV (0x1 << 26)
31#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
32#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
33#define VIDCON0_VIDOUT_WB_RGB (0x4 << 26)
34#define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26)
35#define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26)
36
37#define VIDCON0_L1_DATA_MASK (0x7 << 23)
38#define VIDCON0_L1_DATA_SHIFT (23)
39#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
40#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
41#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
42#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
43#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
44#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
45
46#define VIDCON0_L0_DATA_MASK (0x7 << 20)
47#define VIDCON0_L0_DATA_SHIFT (20)
48#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
49#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
50#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
51#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
52#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
53#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
54
55#define VIDCON0_PNRMODE_MASK (0x3 << 17)
56#define VIDCON0_PNRMODE_SHIFT (17)
57#define VIDCON0_PNRMODE_RGB (0x0 << 17)
58#define VIDCON0_PNRMODE_BGR (0x1 << 17)
59#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
60#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
61
62#define VIDCON0_CLKVALUP (1 << 16)
63#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
64#define VIDCON0_CLKVAL_F_SHIFT (6)
65#define VIDCON0_CLKVAL_F_LIMIT (0xff)
66#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
67#define VIDCON0_VLCKFREE (1 << 5)
68#define VIDCON0_CLKDIR (1 << 4)
69
70#define VIDCON0_CLKSEL_MASK (0x3 << 2)
71#define VIDCON0_CLKSEL_SHIFT (2)
72#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
73#define VIDCON0_CLKSEL_LCD (0x1 << 2)
74#define VIDCON0_CLKSEL_27M (0x3 << 2)
75
76#define VIDCON0_ENVID (1 << 1)
77#define VIDCON0_ENVID_F (1 << 0)
78
79#define VIDCON1 (0x04)
80#define VIDCON1_LINECNT_MASK (0x7ff << 16)
81#define VIDCON1_LINECNT_SHIFT (16)
82#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
83#define VIDCON1_FSTATUS_EVEN (1 << 15)
84#define VIDCON1_VSTATUS_MASK (0x3 << 13)
85#define VIDCON1_VSTATUS_SHIFT (13)
86#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
87#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
88#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
89#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
90#define VIDCON1_VCLK_MASK (0x3 << 9)
91#define VIDCON1_VCLK_HOLD (0x0 << 9)
92#define VIDCON1_VCLK_RUN (0x1 << 9)
93
94#define VIDCON1_INV_VCLK (1 << 7)
95#define VIDCON1_INV_HSYNC (1 << 6)
96#define VIDCON1_INV_VSYNC (1 << 5)
97#define VIDCON1_INV_VDEN (1 << 4)
98
99/* VIDCON2 */
100
101#define VIDCON2 (0x08)
102#define VIDCON2_EN601 (1 << 23)
103#define VIDCON2_TVFMTSEL_SW (1 << 14)
104
105#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
106#define VIDCON2_TVFMTSEL1_SHIFT (12)
107#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
108#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
109#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
110
111#define VIDCON2_ORGYCbCr (1 << 8)
112#define VIDCON2_YUVORDCrCb (1 << 7)
113
114/* PRTCON (S3C6410, S5PC100)
115 * Might not be present in the S3C6410 documentation,
116 * but tests prove it's there almost for sure; shouldn't hurt in any case.
117 */
118#define PRTCON (0x0c)
119#define PRTCON_PROTECT (1 << 11)
120
121/* VIDTCON0 */
122
123#define VIDTCON0 (0x10)
124#define VIDTCON0_VBPDE_MASK (0xff << 24)
125#define VIDTCON0_VBPDE_SHIFT (24)
126#define VIDTCON0_VBPDE_LIMIT (0xff)
127#define VIDTCON0_VBPDE(_x) ((_x) << 24)
128
129#define VIDTCON0_VBPD_MASK (0xff << 16)
130#define VIDTCON0_VBPD_SHIFT (16)
131#define VIDTCON0_VBPD_LIMIT (0xff)
132#define VIDTCON0_VBPD(_x) ((_x) << 16)
133
134#define VIDTCON0_VFPD_MASK (0xff << 8)
135#define VIDTCON0_VFPD_SHIFT (8)
136#define VIDTCON0_VFPD_LIMIT (0xff)
137#define VIDTCON0_VFPD(_x) ((_x) << 8)
138
139#define VIDTCON0_VSPW_MASK (0xff << 0)
140#define VIDTCON0_VSPW_SHIFT (0)
141#define VIDTCON0_VSPW_LIMIT (0xff)
142#define VIDTCON0_VSPW(_x) ((_x) << 0)
143
144/* VIDTCON1 */
145
146#define VIDTCON1 (0x14)
147#define VIDTCON1_VFPDE_MASK (0xff << 24)
148#define VIDTCON1_VFPDE_SHIFT (24)
149#define VIDTCON1_VFPDE_LIMIT (0xff)
150#define VIDTCON1_VFPDE(_x) ((_x) << 24)
151
152#define VIDTCON1_HBPD_MASK (0xff << 16)
153#define VIDTCON1_HBPD_SHIFT (16)
154#define VIDTCON1_HBPD_LIMIT (0xff)
155#define VIDTCON1_HBPD(_x) ((_x) << 16)
156
157#define VIDTCON1_HFPD_MASK (0xff << 8)
158#define VIDTCON1_HFPD_SHIFT (8)
159#define VIDTCON1_HFPD_LIMIT (0xff)
160#define VIDTCON1_HFPD(_x) ((_x) << 8)
161
162#define VIDTCON1_HSPW_MASK (0xff << 0)
163#define VIDTCON1_HSPW_SHIFT (0)
164#define VIDTCON1_HSPW_LIMIT (0xff)
165#define VIDTCON1_HSPW(_x) ((_x) << 0)
166
167#define VIDTCON2 (0x18)
168#define VIDTCON2 (0x18)
169#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
170#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
171#define VIDTCON2_LINEVAL_SHIFT (11)
172#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
173#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
174
175#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
176#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
177#define VIDTCON2_HOZVAL_SHIFT (0)
178#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
179#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
180
181/* WINCONx */
182
183#define WINCON(_win) (0x20 + ((_win) * 4))
184#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
185#define WINCONx_CSCWIDTH_SHIFT (26)
186#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
187#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
188#define WINCONx_ENLOCAL (1 << 22)
189#define WINCONx_BUFSTATUS (1 << 21)
190#define WINCONx_BUFSEL (1 << 20)
191#define WINCONx_BUFAUTOEN (1 << 19)
192#define WINCONx_BITSWP (1 << 18)
193#define WINCONx_BYTSWP (1 << 17)
194#define WINCONx_HAWSWP (1 << 16)
195#define WINCONx_WSWP (1 << 15)
196#define WINCONx_YCbCr (1 << 13)
197#define WINCONx_BURSTLEN_MASK (0x3 << 9)
198#define WINCONx_BURSTLEN_SHIFT (9)
199#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
200#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
201#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
202#define WINCONx_ENWIN (1 << 0)
203
204#define WINCON0_BPPMODE_MASK (0xf << 2)
205#define WINCON0_BPPMODE_SHIFT (2)
206#define WINCON0_BPPMODE_1BPP (0x0 << 2)
207#define WINCON0_BPPMODE_2BPP (0x1 << 2)
208#define WINCON0_BPPMODE_4BPP (0x2 << 2)
209#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
210#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
211#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
212#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
213#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
214
215#define WINCON1_LOCALSEL_CAMIF (1 << 23)
216#define WINCON1_BLD_PIX (1 << 6)
217#define WINCON1_BPPMODE_MASK (0xf << 2)
218#define WINCON1_BPPMODE_SHIFT (2)
219#define WINCON1_BPPMODE_1BPP (0x0 << 2)
220#define WINCON1_BPPMODE_2BPP (0x1 << 2)
221#define WINCON1_BPPMODE_4BPP (0x2 << 2)
222#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
223#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
224#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
225#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
226#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
227#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
228#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
229#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
230#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
231#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
232#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
233#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
234#define WINCON1_ALPHA_SEL (1 << 1)
235
236/* S5PV210 */
237#define SHADOWCON (0x34)
238#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
239/* DMA channels (all windows) */
240#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
241/* Local input channels (windows 0-2) */
242#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
243
244/* VIDOSDx */
245
246#define VIDOSD_BASE (0x40)
247#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
248#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
249#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
250#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
251#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
252
253#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
254#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
255#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
256#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
257#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
258
259#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
260#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
261#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
262#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
263#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
264
265#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
266#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
267#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
268#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
269#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
270
271/* For VIDOSD[1..4]C */
272#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
273#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
274#define VIDISD14C_ALPHA0_G_SHIFT (16)
275#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
276#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
277#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
278#define VIDISD14C_ALPHA0_B_SHIFT (12)
279#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
280#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
281#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
282#define VIDISD14C_ALPHA1_R_SHIFT (8)
283#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
284#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
285#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
286#define VIDISD14C_ALPHA1_G_SHIFT (4)
287#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
288#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
289#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
290#define VIDISD14C_ALPHA1_B_SHIFT (0)
291#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
292#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
293
294/* Video buffer addresses */
295#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
296#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
297#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
298#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
299#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
300
301#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
302#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
303#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
304#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
305#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
306
307#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
308#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
309#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
310#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
311#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
312
313/* Interrupt controls and status */
314
315#define VIDINTCON0 (0x130)
316#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
317#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
318#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
319#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
320
321#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
322#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
323#define VIDINTCON0_INT_I80IFDONE (1 << 17)
324
325#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
326#define VIDINTCON0_FRAMESEL0_SHIFT (15)
327#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
328#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
329#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
330#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
331
332#define VIDINTCON0_FRAMESEL1 (1 << 13)
333#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
334#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
335#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
336#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
337#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
338
339#define VIDINTCON0_INT_FRAME (1 << 12)
340#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
341#define VIDINTCON0_FIFIOSEL_SHIFT (5)
342#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
343#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
344#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
345#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
346#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
347
348#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
349#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
350#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
351#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
352#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
353#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
354#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
355
356#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
357#define VIDINTCON0_INT_FIFO_SHIFT (0)
358#define VIDINTCON0_INT_ENABLE (1 << 0)
359
360#define VIDINTCON1 (0x134)
361#define VIDINTCON1_INT_I180 (1 << 2)
362#define VIDINTCON1_INT_FRAME (1 << 1)
363#define VIDINTCON1_INT_FIFO (1 << 0)
364
365/* Window colour-key control registers */
366#define WKEYCON (0x140) /* 6410,V210 */
367
368#define WKEYCON0 (0x00)
369#define WKEYCON1 (0x04)
370
371#define WxKEYCON0_KEYBL_EN (1 << 26)
372#define WxKEYCON0_KEYEN_F (1 << 25)
373#define WxKEYCON0_DIRCON (1 << 24)
374#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
375#define WxKEYCON0_COMPKEY_SHIFT (0)
376#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
377#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
378#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
379#define WxKEYCON1_COLVAL_SHIFT (0)
380#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
381#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
382
383/* Dithering control */
384#define DITHMODE (0x170)
385#define DITHMODE_R_POS_MASK (0x3 << 5)
386#define DITHMODE_R_POS_SHIFT (5)
387#define DITHMODE_R_POS_8BIT (0x0 << 5)
388#define DITHMODE_R_POS_6BIT (0x1 << 5)
389#define DITHMODE_R_POS_5BIT (0x2 << 5)
390#define DITHMODE_G_POS_MASK (0x3 << 3)
391#define DITHMODE_G_POS_SHIFT (3)
392#define DITHMODE_G_POS_8BIT (0x0 << 3)
393#define DITHMODE_G_POS_6BIT (0x1 << 3)
394#define DITHMODE_G_POS_5BIT (0x2 << 3)
395#define DITHMODE_B_POS_MASK (0x3 << 1)
396#define DITHMODE_B_POS_SHIFT (1)
397#define DITHMODE_B_POS_8BIT (0x0 << 1)
398#define DITHMODE_B_POS_6BIT (0x1 << 1)
399#define DITHMODE_B_POS_5BIT (0x2 << 1)
400#define DITHMODE_DITH_EN (1 << 0)
401
402/* Window blanking (MAP) */
403#define WINxMAP(_win) (0x180 + ((_win) * 4))
404#define WINxMAP_MAP (1 << 24)
405#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
406#define WINxMAP_MAP_COLOUR_SHIFT (0)
407#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
408#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
409
410/* Winodw palette control */
411#define WPALCON (0x1A0)
412#define WPALCON_PAL_UPDATE (1 << 9)
413#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
414#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
415#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
416#define WPALCON_W1PAL_MASK (0x7 << 3)
417#define WPALCON_W1PAL_SHIFT (3)
418#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
419#define WPALCON_W1PAL_24BPP (0x1 << 3)
420#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
421#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
422#define WPALCON_W1PAL_18BPP (0x4 << 3)
423#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
424#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
425#define WPALCON_W0PAL_MASK (0x7 << 0)
426#define WPALCON_W0PAL_SHIFT (0)
427#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
428#define WPALCON_W0PAL_24BPP (0x1 << 0)
429#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
430#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
431#define WPALCON_W0PAL_18BPP (0x4 << 0)
432#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
433#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
434
435/* Blending equation control */
436#define BLENDCON (0x260)
437#define BLENDCON_NEW_MASK (1 << 0)
438#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
439#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
440
441#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
442
443/* Notes on per-window bpp settings
444 *
445 * Value Win0 Win1 Win2 Win3 Win 4
446 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
447 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
448 * 0010 4(P) 4(P) 4(P) 4(P) -none-
449 * 0011 8(P) 8(P) -none- -none- -none-
450 * 0100 -none- 8(A232) 8(A232) -none- -none-
451 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
452 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
453 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
454 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
455 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
456 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
457 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
458 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
459 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
460 * 1110 -none- -none- -none- -none- -none-
461 * 1111 -none- -none- -none- -none- -none-
462*/
463
464/* FIMD Version 8 register offset definitions */
465#define FIMD_V8_VIDTCON0 (0x20010)
466#define FIMD_V8_VIDTCON1 (0x20014)
467#define FIMD_V8_VIDTCON2 (0x20018)
468#define FIMD_V8_VIDTCON3 (0x2001C)
469#define FIMD_V8_VIDCON1 (0x20004)
diff --git a/include/video/sh_mipi_dsi.h b/include/video/sh_mipi_dsi.h
index a01f197e6ac..6cb95c977de 100644
--- a/include/video/sh_mipi_dsi.h
+++ b/include/video/sh_mipi_dsi.h
@@ -25,35 +25,17 @@ enum sh_mipi_dsi_data_fmt {
25 MIPI_YUV420, 25 MIPI_YUV420,
26}; 26};
27 27
28#define SH_MIPI_DSI_HSABM (1 << 0) 28struct sh_mobile_lcdc_chan_cfg;
29#define SH_MIPI_DSI_HBPBM (1 << 1)
30#define SH_MIPI_DSI_HFPBM (1 << 2)
31#define SH_MIPI_DSI_BL2E (1 << 3)
32#define SH_MIPI_DSI_VSEE (1 << 4)
33#define SH_MIPI_DSI_HSEE (1 << 5)
34#define SH_MIPI_DSI_HSAE (1 << 6)
35
36#define SH_MIPI_DSI_HSbyteCLK (1 << 24)
37#define SH_MIPI_DSI_HS6divCLK (1 << 25)
38#define SH_MIPI_DSI_HS4divCLK (1 << 26)
39 29
40#define SH_MIPI_DSI_SYNC_PULSES_MODE (SH_MIPI_DSI_VSEE | \ 30#define SH_MIPI_DSI_HSABM (1 << 0)
41 SH_MIPI_DSI_HSEE | \ 31#define SH_MIPI_DSI_HSPBM (1 << 1)
42 SH_MIPI_DSI_HSAE)
43#define SH_MIPI_DSI_SYNC_EVENTS_MODE (0)
44#define SH_MIPI_DSI_SYNC_BURST_MODE (SH_MIPI_DSI_BL2E)
45 32
46struct sh_mipi_dsi_info { 33struct sh_mipi_dsi_info {
47 enum sh_mipi_dsi_data_fmt data_format; 34 enum sh_mipi_dsi_data_fmt data_format;
48 int channel; 35 struct sh_mobile_lcdc_chan_cfg *lcd_chan;
49 int lane;
50 unsigned long flags; 36 unsigned long flags;
51 u32 clksrc; 37 u32 clksrc;
52 u32 phyctrl; /* for extra setting */
53 unsigned int vsynw_offset; 38 unsigned int vsynw_offset;
54 int (*set_dot_clock)(struct platform_device *pdev,
55 void __iomem *base,
56 int enable);
57}; 39};
58 40
59#endif 41#endif
diff --git a/include/video/sh_mobile_hdmi.h b/include/video/sh_mobile_hdmi.h
index 63d20efa254..b56932927d0 100644
--- a/include/video/sh_mobile_hdmi.h
+++ b/include/video/sh_mobile_hdmi.h
@@ -18,11 +18,9 @@ struct clk;
18/* 18/*
19 * flags format 19 * flags format
20 * 20 *
21 * 0x00000CBA 21 * 0x0000000A
22 * 22 *
23 * A: Audio source select 23 * A: Audio source select
24 * B: Int output option
25 * C: Chip specific option
26 */ 24 */
27 25
28/* Audio source select */ 26/* Audio source select */
@@ -32,15 +30,9 @@ struct clk;
32#define HDMI_SND_SRC_DSD (2 << 0) 30#define HDMI_SND_SRC_DSD (2 << 0)
33#define HDMI_SND_SRC_HBR (3 << 0) 31#define HDMI_SND_SRC_HBR (3 << 0)
34 32
35/* Int output option */
36#define HDMI_OUTPUT_PUSH_PULL (1 << 4) /* System control : output mode */
37#define HDMI_OUTPUT_POLARITY_HI (1 << 5) /* System control : output polarity */
38
39/* Chip specific option */
40#define HDMI_32BIT_REG (1 << 8)
41#define HDMI_HAS_HTOP1 (1 << 9)
42
43struct sh_mobile_hdmi_info { 33struct sh_mobile_hdmi_info {
34 struct sh_mobile_lcdc_chan_cfg *lcd_chan;
35 struct device *lcd_dev;
44 unsigned int flags; 36 unsigned int flags;
45 long (*clk_optimize_parent)(unsigned long target, unsigned long *best_freq, 37 long (*clk_optimize_parent)(unsigned long target, unsigned long *best_freq,
46 unsigned long *parent_freq); 38 unsigned long *parent_freq);
diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h
index 2605fa8adb9..d964e68fc61 100644
--- a/include/video/sh_mobile_lcdc.h
+++ b/include/video/sh_mobile_lcdc.h
@@ -4,123 +4,26 @@
4#include <linux/fb.h> 4#include <linux/fb.h>
5#include <video/sh_mobile_meram.h> 5#include <video/sh_mobile_meram.h>
6 6
7/* Register definitions */
8#define _LDDCKR 0x410
9#define LDDCKR_ICKSEL_BUS (0 << 16)
10#define LDDCKR_ICKSEL_MIPI (1 << 16)
11#define LDDCKR_ICKSEL_HDMI (2 << 16)
12#define LDDCKR_ICKSEL_EXT (3 << 16)
13#define LDDCKR_ICKSEL_MASK (7 << 16)
14#define LDDCKR_MOSEL (1 << 6)
15#define _LDDCKSTPR 0x414
16#define _LDINTR 0x468
17#define LDINTR_FE (1 << 10)
18#define LDINTR_VSE (1 << 9)
19#define LDINTR_VEE (1 << 8)
20#define LDINTR_FS (1 << 2)
21#define LDINTR_VSS (1 << 1)
22#define LDINTR_VES (1 << 0)
23#define LDINTR_STATUS_MASK (0xff << 0)
24#define _LDSR 0x46c
25#define LDSR_MSS (1 << 10)
26#define LDSR_MRS (1 << 8)
27#define LDSR_AS (1 << 1)
28#define _LDCNT1R 0x470
29#define LDCNT1R_DE (1 << 0)
30#define _LDCNT2R 0x474
31#define LDCNT2R_BR (1 << 8)
32#define LDCNT2R_MD (1 << 3)
33#define LDCNT2R_SE (1 << 2)
34#define LDCNT2R_ME (1 << 1)
35#define LDCNT2R_DO (1 << 0)
36#define _LDRCNTR 0x478
37#define LDRCNTR_SRS (1 << 17)
38#define LDRCNTR_SRC (1 << 16)
39#define LDRCNTR_MRS (1 << 1)
40#define LDRCNTR_MRC (1 << 0)
41#define _LDDDSR 0x47c
42#define LDDDSR_LS (1 << 2)
43#define LDDDSR_WS (1 << 1)
44#define LDDDSR_BS (1 << 0)
45
46#define LDMT1R_VPOL (1 << 28)
47#define LDMT1R_HPOL (1 << 27)
48#define LDMT1R_DWPOL (1 << 26)
49#define LDMT1R_DIPOL (1 << 25)
50#define LDMT1R_DAPOL (1 << 24)
51#define LDMT1R_HSCNT (1 << 17)
52#define LDMT1R_DWCNT (1 << 16)
53#define LDMT1R_IFM (1 << 12)
54#define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
55#define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
56#define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
57#define LDMT1R_MIFTYP_RGB12B (0x6 << 0)
58#define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
59#define LDMT1R_MIFTYP_RGB18 (0xa << 0)
60#define LDMT1R_MIFTYP_RGB24 (0xb << 0)
61#define LDMT1R_MIFTYP_YCBCR (0xf << 0)
62#define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
63#define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
64#define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
65#define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
66#define LDMT1R_MIFTYP_SYS9 (0x4 << 0)
67#define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
68#define LDMT1R_MIFTYP_SYS16A (0x7 << 0)
69#define LDMT1R_MIFTYP_SYS16B (0x8 << 0)
70#define LDMT1R_MIFTYP_SYS16C (0x9 << 0)
71#define LDMT1R_MIFTYP_SYS18 (0xa << 0)
72#define LDMT1R_MIFTYP_SYS24 (0xb << 0)
73#define LDMT1R_MIFTYP_MASK (0xf << 0)
74
75#define LDDFR_CF1 (1 << 18)
76#define LDDFR_CF0 (1 << 17)
77#define LDDFR_CC (1 << 16)
78#define LDDFR_YF_420 (0 << 8)
79#define LDDFR_YF_422 (1 << 8)
80#define LDDFR_YF_444 (2 << 8)
81#define LDDFR_YF_MASK (3 << 8)
82#define LDDFR_PKF_ARGB32 (0x00 << 0)
83#define LDDFR_PKF_RGB16 (0x03 << 0)
84#define LDDFR_PKF_RGB24 (0x0b << 0)
85#define LDDFR_PKF_MASK (0x1f << 0)
86
87#define LDSM1R_OS (1 << 0)
88
89#define LDSM2R_OSTRG (1 << 0)
90
91#define LDPMR_LPS (3 << 0)
92
93#define _LDDWD0R 0x800
94#define LDDWDxR_WDACT (1 << 28)
95#define LDDWDxR_RSW (1 << 24)
96#define _LDDRDR 0x840
97#define LDDRDR_RSR (1 << 24)
98#define LDDRDR_DRD_MASK (0x3ffff << 0)
99#define _LDDWAR 0x900
100#define LDDWAR_WA (1 << 0)
101#define _LDDRAR 0x904
102#define LDDRAR_RA (1 << 0)
103
104enum { 7enum {
105 RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */ 8 RGB8, /* 24bpp, 8:8:8 */
106 RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */ 9 RGB9, /* 18bpp, 9:9 */
107 RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */ 10 RGB12A, /* 24bpp, 12:12 */
108 RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */ 11 RGB12B, /* 12bpp */
109 RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */ 12 RGB16, /* 16bpp */
110 RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */ 13 RGB18, /* 18bpp */
111 RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */ 14 RGB24, /* 24bpp */
112 YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */ 15 YUV422, /* 16bpp */
113 SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */ 16 SYS8A, /* 24bpp, 8:8:8 */
114 SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */ 17 SYS8B, /* 18bpp, 8:8:2 */
115 SYS8C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */ 18 SYS8C, /* 18bpp, 2:8:8 */
116 SYS8D = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */ 19 SYS8D, /* 16bpp, 8:8 */
117 SYS9 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9, /* 18bpp, 9:9 */ 20 SYS9, /* 18bpp, 9:9 */
118 SYS12 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */ 21 SYS12, /* 24bpp, 12:12 */
119 SYS16A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A, /* 16bpp */ 22 SYS16A, /* 16bpp */
120 SYS16B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B, /* 18bpp, 16:2 */ 23 SYS16B, /* 18bpp, 16:2 */
121 SYS16C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C, /* 18bpp, 2:16 */ 24 SYS16C, /* 18bpp, 2:16 */
122 SYS18 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */ 25 SYS18, /* 18bpp */
123 SYS24 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */ 26 SYS24, /* 24bpp */
124}; 27};
125 28
126enum { LCDC_CHAN_DISABLED = 0, 29enum { LCDC_CHAN_DISABLED = 0,
@@ -147,51 +50,50 @@ struct sh_mobile_lcdc_sys_bus_ops {
147 unsigned long (*read_data)(void *handle); 50 unsigned long (*read_data)(void *handle);
148}; 51};
149 52
150struct sh_mobile_lcdc_panel_cfg { 53struct module;
151 unsigned long width; /* Panel width in mm */ 54struct sh_mobile_lcdc_board_cfg {
152 unsigned long height; /* Panel height in mm */ 55 struct module *owner;
153 int (*setup_sys)(void *sys_ops_handle, 56 void *board_data;
57 int (*setup_sys)(void *board_data, void *sys_ops_handle,
154 struct sh_mobile_lcdc_sys_bus_ops *sys_ops); 58 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
155 void (*start_transfer)(void *sys_ops_handle, 59 void (*start_transfer)(void *board_data, void *sys_ops_handle,
156 struct sh_mobile_lcdc_sys_bus_ops *sys_ops); 60 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
157 void (*display_on)(void); 61 void (*display_on)(void *board_data, struct fb_info *info);
158 void (*display_off)(void); 62 void (*display_off)(void *board_data);
63 int (*set_brightness)(void *board_data, int brightness);
64 int (*get_brightness)(void *board_data);
65};
66
67struct sh_mobile_lcdc_lcd_size_cfg { /* width and height of panel in mm */
68 unsigned long width;
69 unsigned long height;
159}; 70};
160 71
161/* backlight info */ 72/* backlight info */
162struct sh_mobile_lcdc_bl_info { 73struct sh_mobile_lcdc_bl_info {
163 const char *name; 74 const char *name;
164 int max_brightness; 75 int max_brightness;
165 int (*set_brightness)(int brightness);
166};
167
168struct sh_mobile_lcdc_overlay_cfg {
169 int fourcc;
170 unsigned int max_xres;
171 unsigned int max_yres;
172}; 76};
173 77
174struct sh_mobile_lcdc_chan_cfg { 78struct sh_mobile_lcdc_chan_cfg {
175 int chan; 79 int chan;
176 int fourcc; 80 int bpp;
177 int colorspace;
178 int interface_type; /* selects RGBn or SYSn I/F, see above */ 81 int interface_type; /* selects RGBn or SYSn I/F, see above */
179 int clock_divider; 82 int clock_divider;
180 unsigned long flags; /* LCDC_FLAGS_... */ 83 unsigned long flags; /* LCDC_FLAGS_... */
181 const struct fb_videomode *lcd_modes; 84 const struct fb_videomode *lcd_cfg;
182 int num_modes; 85 int num_cfg;
183 struct sh_mobile_lcdc_panel_cfg panel_cfg; 86 struct sh_mobile_lcdc_lcd_size_cfg lcd_size_cfg;
87 struct sh_mobile_lcdc_board_cfg board_cfg;
184 struct sh_mobile_lcdc_bl_info bl_info; 88 struct sh_mobile_lcdc_bl_info bl_info;
185 struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */ 89 struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
186 const struct sh_mobile_meram_cfg *meram_cfg; 90 int nonstd;
187 91 struct sh_mobile_meram_cfg *meram_cfg;
188 struct platform_device *tx_dev; /* HDMI/DSI transmitter device */
189}; 92};
190 93
191struct sh_mobile_lcdc_info { 94struct sh_mobile_lcdc_info {
192 int clock_source; 95 int clock_source;
193 struct sh_mobile_lcdc_chan_cfg ch[2]; 96 struct sh_mobile_lcdc_chan_cfg ch[2];
194 struct sh_mobile_lcdc_overlay_cfg overlays[4];
195 struct sh_mobile_meram_info *meram_dev; 97 struct sh_mobile_meram_info *meram_dev;
196}; 98};
197 99
diff --git a/include/video/sh_mobile_meram.h b/include/video/sh_mobile_meram.h
index 062e6e7f955..af602d602b2 100644
--- a/include/video/sh_mobile_meram.h
+++ b/include/video/sh_mobile_meram.h
@@ -15,80 +15,54 @@ enum {
15 15
16 16
17struct sh_mobile_meram_priv; 17struct sh_mobile_meram_priv;
18struct sh_mobile_meram_ops;
18 19
19/*
20 * struct sh_mobile_meram_info - MERAM platform data
21 * @reserved_icbs: Bitmask of reserved ICBs (for instance used through UIO)
22 */
23struct sh_mobile_meram_info { 20struct sh_mobile_meram_info {
24 int addr_mode; 21 int addr_mode;
25 u32 reserved_icbs; 22 struct sh_mobile_meram_ops *ops;
26 struct sh_mobile_meram_priv *priv; 23 struct sh_mobile_meram_priv *priv;
27 struct platform_device *pdev; 24 struct platform_device *pdev;
28}; 25};
29 26
30/* icb config */ 27/* icb config */
31struct sh_mobile_meram_icb_cfg { 28struct sh_mobile_meram_icb {
32 unsigned int meram_size; /* MERAM Buffer Size to use */ 29 int marker_icb; /* ICB # for Marker ICB */
30 int cache_icb; /* ICB # for Cache ICB */
31 int meram_offset; /* MERAM Buffer Offset to use */
32 int meram_size; /* MERAM Buffer Size to use */
33
34 int cache_unit; /* bytes to cache per ICB */
33}; 35};
34 36
35struct sh_mobile_meram_cfg { 37struct sh_mobile_meram_cfg {
36 struct sh_mobile_meram_icb_cfg icb[2]; 38 struct sh_mobile_meram_icb icb[2];
39 int pixelformat;
40 int current_reg;
37}; 41};
38 42
39#if defined(CONFIG_FB_SH_MOBILE_MERAM) || \ 43struct module;
40 defined(CONFIG_FB_SH_MOBILE_MERAM_MODULE) 44struct sh_mobile_meram_ops {
41unsigned long sh_mobile_meram_alloc(struct sh_mobile_meram_info *meram_dev, 45 struct module *module;
42 size_t size); 46 /* register usage of meram */
43void sh_mobile_meram_free(struct sh_mobile_meram_info *meram_dev, 47 int (*meram_register)(struct sh_mobile_meram_info *meram_dev,
44 unsigned long mem, size_t size); 48 struct sh_mobile_meram_cfg *cfg,
45void *sh_mobile_meram_cache_alloc(struct sh_mobile_meram_info *dev, 49 int xres, int yres, int pixelformat,
46 const struct sh_mobile_meram_cfg *cfg, 50 unsigned long base_addr_y,
47 unsigned int xres, unsigned int yres, 51 unsigned long base_addr_c,
48 unsigned int pixelformat, 52 unsigned long *icb_addr_y,
49 unsigned int *pitch); 53 unsigned long *icb_addr_c, int *pitch);
50void sh_mobile_meram_cache_free(struct sh_mobile_meram_info *dev, void *data);
51void sh_mobile_meram_cache_update(struct sh_mobile_meram_info *dev, void *data,
52 unsigned long base_addr_y,
53 unsigned long base_addr_c,
54 unsigned long *icb_addr_y,
55 unsigned long *icb_addr_c);
56#else
57static inline unsigned long
58sh_mobile_meram_alloc(struct sh_mobile_meram_info *meram_dev, size_t size)
59{
60 return 0;
61}
62
63static inline void
64sh_mobile_meram_free(struct sh_mobile_meram_info *meram_dev,
65 unsigned long mem, size_t size)
66{
67}
68 54
69static inline void * 55 /* unregister usage of meram */
70sh_mobile_meram_cache_alloc(struct sh_mobile_meram_info *dev, 56 int (*meram_unregister)(struct sh_mobile_meram_info *meram_dev,
71 const struct sh_mobile_meram_cfg *cfg, 57 struct sh_mobile_meram_cfg *cfg);
72 unsigned int xres, unsigned int yres,
73 unsigned int pixelformat,
74 unsigned int *pitch)
75{
76 return ERR_PTR(-ENODEV);
77}
78 58
79static inline void 59 /* update meram settings */
80sh_mobile_meram_cache_free(struct sh_mobile_meram_info *dev, void *data) 60 int (*meram_update)(struct sh_mobile_meram_info *meram_dev,
81{ 61 struct sh_mobile_meram_cfg *cfg,
82} 62 unsigned long base_addr_y,
83 63 unsigned long base_addr_c,
84static inline void 64 unsigned long *icb_addr_y,
85sh_mobile_meram_cache_update(struct sh_mobile_meram_info *dev, void *data, 65 unsigned long *icb_addr_c);
86 unsigned long base_addr_y, 66};
87 unsigned long base_addr_c,
88 unsigned long *icb_addr_y,
89 unsigned long *icb_addr_c)
90{
91}
92#endif
93 67
94#endif /* __VIDEO_SH_MOBILE_MERAM_H__ */ 68#endif /* __VIDEO_SH_MOBILE_MERAM_H__ */
diff --git a/include/video/udlfb.h b/include/video/udlfb.h
index f9466fa54ba..69d485a4a02 100644
--- a/include/video/udlfb.h
+++ b/include/video/udlfb.h
@@ -41,7 +41,6 @@ struct dlfb_data {
41 char *backing_buffer; 41 char *backing_buffer;
42 int fb_count; 42 int fb_count;
43 bool virtualized; /* true when physical usb device not present */ 43 bool virtualized; /* true when physical usb device not present */
44 struct delayed_work init_framebuffer_work;
45 struct delayed_work free_framebuffer_work; 44 struct delayed_work free_framebuffer_work;
46 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */ 45 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
47 atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */ 46 atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */
@@ -51,7 +50,6 @@ struct dlfb_data {
51 int base16; 50 int base16;
52 int base8; 51 int base8;
53 u32 pseudo_palette[256]; 52 u32 pseudo_palette[256];
54 int blank_mode; /*one of FB_BLANK_ */
55 /* blit-only rendering path metrics, exposed through sysfs */ 53 /* blit-only rendering path metrics, exposed through sysfs */
56 atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */ 54 atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */
57 atomic_t bytes_identical; /* saved effort with backbuffer comparison */ 55 atomic_t bytes_identical; /* saved effort with backbuffer comparison */
diff --git a/include/video/vga.h b/include/video/vga.h
index cac567f22e6..2b8691f7d25 100644
--- a/include/video/vga.h
+++ b/include/video/vga.h
@@ -19,7 +19,29 @@
19 19
20#include <linux/types.h> 20#include <linux/types.h>
21#include <asm/io.h> 21#include <asm/io.h>
22#ifndef CONFIG_AMIGA
22#include <asm/vga.h> 23#include <asm/vga.h>
24#else
25/*
26 * FIXME
27 * Ugh, we don't have PCI space, so map readb() and friends to use Zorro space
28 * for MMIO accesses. This should make cirrusfb work again on Amiga
29 */
30#undef inb_p
31#undef inw_p
32#undef outb_p
33#undef outw
34#undef readb
35#undef writeb
36#undef writew
37#define inb_p(port) 0
38#define inw_p(port) 0
39#define outb_p(port, val) do { } while (0)
40#define outw(port, val) do { } while (0)
41#define readb z_readb
42#define writeb z_writeb
43#define writew z_writew
44#endif
23#include <asm/byteorder.h> 45#include <asm/byteorder.h>
24 46
25 47
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 00:12:18 -0500