diff options
author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2009-07-09 21:14:35 -0400 |
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committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-05-10 10:44:50 -0400 |
commit | e9bd2e73793bf0f7fcd8f94b532bb8f5c5b44171 (patch) | |
tree | 850cc08ec621dea67cdaf8bb5ef03f14ee452815 /include/linux | |
parent | d5381642ab01b084787925acdf26b5524d434476 (diff) |
i7core_edac: Adds write unlock to MC registers
The public Intel Xeon 5500 volume 2 datasheet describes, on page 53,
session 2.6.7 a register that can lock/unlock Memory Controller the
configuration register, called MC_CFG_CONTROL.
Adds support for it in the hope that software error injection would
work. With my tests with Xeon 35xx, there's still something missing.
With a program that does sequencial bit writes at dev 0.0, sometimes, it
produces error injection, after unblocking the MC_CFG_CONTROL (and,
sometimes, it just locks my testing machine).
I'll try later to discover by trial and error what's the register that
solves this issue on Xeon 35xx.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'include/linux')
-rw-r--r-- | include/linux/pci_ids.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index c5dd0994bd7..9d5bfe86ba7 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h | |||
@@ -2548,6 +2548,7 @@ | |||
2548 | #define PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR 0x2c31 | 2548 | #define PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR 0x2c31 |
2549 | #define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK 0x2c32 | 2549 | #define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK 0x2c32 |
2550 | #define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC 0x2c33 | 2550 | #define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC 0x2c33 |
2551 | #define PCI_DEVICE_ID_INTEL_I7_NOCORE 0x2c41 | ||
2551 | #define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 | 2552 | #define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 |
2552 | #define PCI_DEVICE_ID_INTEL_IOAT_TBG4 0x3429 | 2553 | #define PCI_DEVICE_ID_INTEL_IOAT_TBG4 0x3429 |
2553 | #define PCI_DEVICE_ID_INTEL_IOAT_TBG5 0x342a | 2554 | #define PCI_DEVICE_ID_INTEL_IOAT_TBG5 0x342a |