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authorLinus Torvalds <torvalds@linux-foundation.org>2012-01-18 15:34:09 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-01-18 15:34:09 -0500
commit92b5abbb44e05cdbc4483219f30a435dd871a8ea (patch)
tree15490d1c7fd415575ec6beec1baa5ce89f747bf9 /include/linux
parentccb19d263fd1c9e34948e2158c53eacbff369344 (diff)
parentdf3481399042200792822b6243e36a95a557b57e (diff)
Merge git://git.infradead.org/users/willy/linux-nvme
* git://git.infradead.org/users/willy/linux-nvme: (105 commits) NVMe: Set number of queues correctly NVMe: Version 0.8 NVMe: Set queue flags correctly NVMe: Simplify nvme_unmap_user_pages NVMe: Mark the end of the sg list NVMe: Fix DMA mapping for admin commands NVMe: Rename IO_TIMEOUT to NVME_IO_TIMEOUT NVMe: Merge the nvme_bio and nvme_prp data structures NVMe: Change nvme_completion_fn to take a dev NVMe: Change get_nvmeq to take a dev instead of a namespace NVMe: Simplify completion handling NVMe: Update Identify Controller data structure NVMe: Implement doorbell stride capability NVMe: Version 0.7 NVMe: Don't probe namespace 0 Fix calculation of number of pages in a PRP List NVMe: Create nvme_identify and nvme_get_features functions NVMe: Fix memory leak in nvme_dev_add() NVMe: Fix calls to dma_unmap_sg NVMe: Correct sg list setup in nvme_map_user_pages ...
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/nvme.h434
1 files changed, 434 insertions, 0 deletions
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
new file mode 100644
index 00000000000..9490a00529f
--- /dev/null
+++ b/include/linux/nvme.h
@@ -0,0 +1,434 @@
1/*
2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef _LINUX_NVME_H
20#define _LINUX_NVME_H
21
22#include <linux/types.h>
23
24struct nvme_bar {
25 __u64 cap; /* Controller Capabilities */
26 __u32 vs; /* Version */
27 __u32 intms; /* Interrupt Mask Set */
28 __u32 intmc; /* Interrupt Mask Clear */
29 __u32 cc; /* Controller Configuration */
30 __u32 rsvd1; /* Reserved */
31 __u32 csts; /* Controller Status */
32 __u32 rsvd2; /* Reserved */
33 __u32 aqa; /* Admin Queue Attributes */
34 __u64 asq; /* Admin SQ Base Address */
35 __u64 acq; /* Admin CQ Base Address */
36};
37
38#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
39#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
40
41enum {
42 NVME_CC_ENABLE = 1 << 0,
43 NVME_CC_CSS_NVM = 0 << 4,
44 NVME_CC_MPS_SHIFT = 7,
45 NVME_CC_ARB_RR = 0 << 11,
46 NVME_CC_ARB_WRRU = 1 << 11,
47 NVME_CC_ARB_VS = 7 << 11,
48 NVME_CC_SHN_NONE = 0 << 14,
49 NVME_CC_SHN_NORMAL = 1 << 14,
50 NVME_CC_SHN_ABRUPT = 2 << 14,
51 NVME_CC_IOSQES = 6 << 16,
52 NVME_CC_IOCQES = 4 << 20,
53 NVME_CSTS_RDY = 1 << 0,
54 NVME_CSTS_CFS = 1 << 1,
55 NVME_CSTS_SHST_NORMAL = 0 << 2,
56 NVME_CSTS_SHST_OCCUR = 1 << 2,
57 NVME_CSTS_SHST_CMPLT = 2 << 2,
58};
59
60struct nvme_id_power_state {
61 __le16 max_power; /* centiwatts */
62 __u16 rsvd2;
63 __le32 entry_lat; /* microseconds */
64 __le32 exit_lat; /* microseconds */
65 __u8 read_tput;
66 __u8 read_lat;
67 __u8 write_tput;
68 __u8 write_lat;
69 __u8 rsvd16[16];
70};
71
72#define NVME_VS(major, minor) (major << 16 | minor)
73
74struct nvme_id_ctrl {
75 __le16 vid;
76 __le16 ssvid;
77 char sn[20];
78 char mn[40];
79 char fr[8];
80 __u8 rab;
81 __u8 ieee[3];
82 __u8 mic;
83 __u8 mdts;
84 __u8 rsvd78[178];
85 __le16 oacs;
86 __u8 acl;
87 __u8 aerl;
88 __u8 frmw;
89 __u8 lpa;
90 __u8 elpe;
91 __u8 npss;
92 __u8 rsvd264[248];
93 __u8 sqes;
94 __u8 cqes;
95 __u8 rsvd514[2];
96 __le32 nn;
97 __le16 oncs;
98 __le16 fuses;
99 __u8 fna;
100 __u8 vwc;
101 __le16 awun;
102 __le16 awupf;
103 __u8 rsvd530[1518];
104 struct nvme_id_power_state psd[32];
105 __u8 vs[1024];
106};
107
108struct nvme_lbaf {
109 __le16 ms;
110 __u8 ds;
111 __u8 rp;
112};
113
114struct nvme_id_ns {
115 __le64 nsze;
116 __le64 ncap;
117 __le64 nuse;
118 __u8 nsfeat;
119 __u8 nlbaf;
120 __u8 flbas;
121 __u8 mc;
122 __u8 dpc;
123 __u8 dps;
124 __u8 rsvd30[98];
125 struct nvme_lbaf lbaf[16];
126 __u8 rsvd192[192];
127 __u8 vs[3712];
128};
129
130enum {
131 NVME_NS_FEAT_THIN = 1 << 0,
132 NVME_LBAF_RP_BEST = 0,
133 NVME_LBAF_RP_BETTER = 1,
134 NVME_LBAF_RP_GOOD = 2,
135 NVME_LBAF_RP_DEGRADED = 3,
136};
137
138struct nvme_lba_range_type {
139 __u8 type;
140 __u8 attributes;
141 __u8 rsvd2[14];
142 __u64 slba;
143 __u64 nlb;
144 __u8 guid[16];
145 __u8 rsvd48[16];
146};
147
148enum {
149 NVME_LBART_TYPE_FS = 0x01,
150 NVME_LBART_TYPE_RAID = 0x02,
151 NVME_LBART_TYPE_CACHE = 0x03,
152 NVME_LBART_TYPE_SWAP = 0x04,
153
154 NVME_LBART_ATTRIB_TEMP = 1 << 0,
155 NVME_LBART_ATTRIB_HIDE = 1 << 1,
156};
157
158/* I/O commands */
159
160enum nvme_opcode {
161 nvme_cmd_flush = 0x00,
162 nvme_cmd_write = 0x01,
163 nvme_cmd_read = 0x02,
164 nvme_cmd_write_uncor = 0x04,
165 nvme_cmd_compare = 0x05,
166 nvme_cmd_dsm = 0x09,
167};
168
169struct nvme_common_command {
170 __u8 opcode;
171 __u8 flags;
172 __u16 command_id;
173 __le32 nsid;
174 __u32 cdw2[2];
175 __le64 metadata;
176 __le64 prp1;
177 __le64 prp2;
178 __u32 cdw10[6];
179};
180
181struct nvme_rw_command {
182 __u8 opcode;
183 __u8 flags;
184 __u16 command_id;
185 __le32 nsid;
186 __u64 rsvd2;
187 __le64 metadata;
188 __le64 prp1;
189 __le64 prp2;
190 __le64 slba;
191 __le16 length;
192 __le16 control;
193 __le32 dsmgmt;
194 __le32 reftag;
195 __le16 apptag;
196 __le16 appmask;
197};
198
199enum {
200 NVME_RW_LR = 1 << 15,
201 NVME_RW_FUA = 1 << 14,
202 NVME_RW_DSM_FREQ_UNSPEC = 0,
203 NVME_RW_DSM_FREQ_TYPICAL = 1,
204 NVME_RW_DSM_FREQ_RARE = 2,
205 NVME_RW_DSM_FREQ_READS = 3,
206 NVME_RW_DSM_FREQ_WRITES = 4,
207 NVME_RW_DSM_FREQ_RW = 5,
208 NVME_RW_DSM_FREQ_ONCE = 6,
209 NVME_RW_DSM_FREQ_PREFETCH = 7,
210 NVME_RW_DSM_FREQ_TEMP = 8,
211 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
212 NVME_RW_DSM_LATENCY_IDL