diff options
| author | Rafał Miłecki <zajec5@gmail.com> | 2011-04-20 05:12:30 -0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-04-25 14:50:15 -0400 |
| commit | 9f2e731d1d278d853def1567735d8a823668a3c8 (patch) | |
| tree | 5377f196137b4b66540d5a0332585004c804be2e /include/linux/ssb | |
| parent | 767ad6a0a2342d42f6f03b50198418b1475e0a7b (diff) | |
ssb: cc: add & fix defines
We probably got false positive results for checking PLL being down.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/ssb')
| -rw-r--r-- | include/linux/ssb/ssb_driver_chipcommon.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h index 2cdf249b4e5..4f2d77a0c02 100644 --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h | |||
| @@ -131,6 +131,9 @@ | |||
| 131 | #define SSB_CHIPCO_GPIOIRQ 0x0074 | 131 | #define SSB_CHIPCO_GPIOIRQ 0x0074 |
| 132 | #define SSB_CHIPCO_WATCHDOG 0x0080 | 132 | #define SSB_CHIPCO_WATCHDOG 0x0080 |
| 133 | #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ | 133 | #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ |
| 134 | #define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF | ||
| 135 | #define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0 | ||
| 136 | #define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000 | ||
| 134 | #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16 | 137 | #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16 |
| 135 | #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ | 138 | #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ |
| 136 | #define SSB_CHIPCO_CLOCK_N 0x0090 | 139 | #define SSB_CHIPCO_CLOCK_N 0x0090 |
| @@ -189,8 +192,10 @@ | |||
| 189 | #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */ | 192 | #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */ |
| 190 | #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ | 193 | #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ |
| 191 | #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ | 194 | #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ |
| 192 | #define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */ | 195 | #define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */ |
| 193 | #define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */ | 196 | #define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */ |
| 197 | #define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */ | ||
| 198 | #define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */ | ||
| 194 | #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ | 199 | #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ |
| 195 | #define SSB_CHIPCO_UART0_DATA 0x0300 | 200 | #define SSB_CHIPCO_UART0_DATA 0x0300 |
| 196 | #define SSB_CHIPCO_UART0_IMR 0x0304 | 201 | #define SSB_CHIPCO_UART0_IMR 0x0304 |