diff options
author | Rafał Miłecki <zajec5@gmail.com> | 2011-12-08 12:02:21 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-12-13 15:30:49 -0500 |
commit | 8a5ac6ecd56756ee72588627aa23ab6cf9b790db (patch) | |
tree | de3fea105315782161688cd7a9c22634422e1fd6 /include/linux/ssb | |
parent | adf5ace5d8161b962afe90e77922728a425b6933 (diff) |
ssb: extract FEM info from SPROM
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/ssb')
-rw-r--r-- | include/linux/ssb/ssb.h | 9 | ||||
-rw-r--r-- | include/linux/ssb/ssb_regs.h | 17 |
2 files changed, 26 insertions, 0 deletions
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 061e560251b..dcf35b0f303 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h | |||
@@ -94,6 +94,15 @@ struct ssb_sprom { | |||
94 | } ghz5; /* 5GHz band */ | 94 | } ghz5; /* 5GHz band */ |
95 | } antenna_gain; | 95 | } antenna_gain; |
96 | 96 | ||
97 | struct { | ||
98 | struct { | ||
99 | u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; | ||
100 | } ghz2; | ||
101 | struct { | ||
102 | u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; | ||
103 | } ghz5; | ||
104 | } fem; | ||
105 | |||
97 | /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */ | 106 | /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */ |
98 | }; | 107 | }; |
99 | 108 | ||
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h index 98941203a27..c814ae6eeb2 100644 --- a/include/linux/ssb/ssb_regs.h +++ b/include/linux/ssb/ssb_regs.h | |||
@@ -432,6 +432,23 @@ | |||
432 | #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ | 432 | #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ |
433 | #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ | 433 | #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ |
434 | #define SSB_SPROM8_RXPO5G_SHIFT 8 | 434 | #define SSB_SPROM8_RXPO5G_SHIFT 8 |
435 | #define SSB_SPROM8_FEM2G 0x00AE | ||
436 | #define SSB_SPROM8_FEM5G 0x00B0 | ||
437 | #define SSB_SROM8_FEM_TSSIPOS 0x0001 | ||
438 | #define SSB_SROM8_FEM_TSSIPOS_SHIFT 0 | ||
439 | #define SSB_SROM8_FEM_EXTPA_GAIN 0x0006 | ||
440 | #define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1 | ||
441 | #define SSB_SROM8_FEM_PDET_RANGE 0x00F8 | ||
442 | #define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3 | ||
443 | #define SSB_SROM8_FEM_TR_ISO 0x0700 | ||
444 | #define SSB_SROM8_FEM_TR_ISO_SHIFT 8 | ||
445 | #define SSB_SROM8_FEM_ANTSWLUT 0xF800 | ||
446 | #define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11 | ||
447 | #define SSB_SPROM8_THERMAL 0x00B2 | ||
448 | #define SSB_SPROM8_MPWR_RAWTS 0x00B4 | ||
449 | #define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6 | ||
450 | #define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8 | ||
451 | #define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA | ||
435 | #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ | 452 | #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ |
436 | #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ | 453 | #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ |
437 | #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ | 454 | #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |