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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /include/linux/mpu6000.h
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'include/linux/mpu6000.h')
-rw-r--r--include/linux/mpu6000.h406
1 files changed, 406 insertions, 0 deletions
diff --git a/include/linux/mpu6000.h b/include/linux/mpu6000.h
new file mode 100644
index 00000000000..5a63c8f07b7
--- /dev/null
+++ b/include/linux/mpu6000.h
@@ -0,0 +1,406 @@
1/*
2 $License:
3 Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program. If not, see <http://www.gnu.org/licenses/>.
17 $
18 */
19
20/**
21 * @defgroup
22 * @brief
23 *
24 * @{
25 * @file mpu6000.h
26 * @brief
27 */
28
29#ifndef __MPU6000_H_
30#define __MPU6000_H_
31
32#define MPU_NAME "mpu6000"
33#define DEFAULT_MPU_SLAVEADDR 0x68
34
35/*==== M_HW REGISTER SET ====*/
36enum {
37 MPUREG_XG_OFFS_TC = 0, /* 0x00 */
38 MPUREG_YG_OFFS_TC, /* 0x00 */
39 MPUREG_ZG_OFFS_TC, /* 0x00 */
40 MPUREG_X_FINE_GAIN, /* 0x00 */
41 MPUREG_Y_FINE_GAIN, /* 0x00 */
42 MPUREG_Z_FINE_GAIN, /* 0x00 */
43 MPUREG_XA_OFFS_H, /* 0x00 */
44 MPUREG_XA_OFFS_L_TC, /* 0x00 */
45 MPUREG_YA_OFFS_H, /* 0x00 */
46 MPUREG_YA_OFFS_L_TC, /* 0x00 */
47 MPUREG_ZA_OFFS_H, /* 0x00 */
48 MPUREG_ZA_OFFS_L_TC, /* 0xB */
49 MPUREG_0C_RSVD, /* 0x00 */
50 MPUREG_0D_RSVD, /* 0x00 */
51 MPUREG_0E_RSVD, /* 0x00 */
52 MPUREG_0F_RSVD, /* 0x00 */
53 MPUREG_10_RSVD, /* 0x00 */
54 MPUREG_11_RSVD, /* 0x00 */
55 MPUREG_12_RSVD, /* 0x00 */
56 MPUREG_XG_OFFS_USRH, /* 0x00 */
57 MPUREG_XG_OFFS_USRL, /* 0x00 */
58 MPUREG_YG_OFFS_USRH, /* 0x00 */
59 MPUREG_YG_OFFS_USRL, /* 0x00 */
60 MPUREG_ZG_OFFS_USRH, /* 0x00 */
61 MPUREG_ZG_OFFS_USRL, /* 0x00 */
62 MPUREG_SMPLRT_DIV, /* 0x19 */
63 MPUREG_CONFIG, /* 0x1A ==> DLPF_FS_SYNC */
64 MPUREG_GYRO_CONFIG, /* 0x00 */
65 MPUREG_ACCEL_CONFIG, /* 0x00 */
66 MPUREG_ACCEL_FF_THR, /* 0x00 */
67 MPUREG_ACCEL_FF_DUR, /* 0x00 */
68 MPUREG_ACCEL_MOT_THR, /* 0x00 */
69 MPUREG_ACCEL_MOT_DUR, /* 0x00 */
70 MPUREG_ACCEL_ZRMOT_THR, /* 0x00 */
71 MPUREG_ACCEL_ZRMOT_DUR, /* 0x00 */
72 MPUREG_FIFO_EN, /* 0x23 */
73 MPUREG_I2C_MST_CTRL, /* 0x00 */
74 MPUREG_I2C_SLV0_ADDR, /* 0x25 */
75 MPUREG_I2C_SLV0_REG, /* 0x00 */
76 MPUREG_I2C_SLV0_CTRL, /* 0x00 */
77 MPUREG_I2C_SLV1_ADDR, /* 0x28 */
78 MPUREG_I2C_SLV1_REG_PASSWORD, /* 0x00 */
79 MPUREG_I2C_SLV1_CTRL, /* 0x00 */
80 MPUREG_I2C_SLV2_ADDR, /* 0x2B */
81 MPUREG_I2C_SLV2_REG, /* 0x00 */
82 MPUREG_I2C_SLV2_CTRL, /* 0x00 */
83 MPUREG_I2C_SLV3_ADDR, /* 0x2E */
84 MPUREG_I2C_SLV3_REG, /* 0x00 */
85 MPUREG_I2C_SLV3_CTRL, /* 0x00 */
86 MPUREG_I2C_SLV4_ADDR, /* 0x31 */
87 MPUREG_I2C_SLV4_REG, /* 0x00 */
88 MPUREG_I2C_SLV4_DO, /* 0x00 */
89 MPUREG_I2C_SLV4_CTRL, /* 0x00 */
90 MPUREG_I2C_SLV4_DI, /* 0x00 */
91 MPUREG_I2C_MST_STATUS, /* 0x36 */
92 MPUREG_INT_PIN_CFG, /* 0x37 ==> -* INT_CFG */
93 MPUREG_INT_ENABLE, /* 0x38 ==> / */
94 MPUREG_DMP_INT_STATUS, /* 0x39 */
95 MPUREG_INT_STATUS, /* 0x3A */
96 MPUREG_ACCEL_XOUT_H, /* 0x3B */
97 MPUREG_ACCEL_XOUT_L, /* 0x00 */
98 MPUREG_ACCEL_YOUT_H, /* 0x00 */
99 MPUREG_ACCEL_YOUT_L, /* 0x00 */
100 MPUREG_ACCEL_ZOUT_H, /* 0x00 */
101 MPUREG_ACCEL_ZOUT_L, /* 0x00 */
102 MPUREG_TEMP_OUT_H, /* 0x41 */
103 MPUREG_TEMP_OUT_L, /* 0x00 */
104 MPUREG_GYRO_XOUT_H, /* 0x43 */
105 MPUREG_GYRO_XOUT_L, /* 0x00 */
106 MPUREG_GYRO_YOUT_H, /* 0x00 */
107 MPUREG_GYRO_YOUT_L, /* 0x00 */
108 MPUREG_GYRO_ZOUT_H, /* 0x00 */
109 MPUREG_GYRO_ZOUT_L, /* 0x00 */
110 MPUREG_EXT_SLV_SENS_DATA_00, /* 0x49 */
111 MPUREG_EXT_SLV_SENS_DATA_01, /* 0x00 */
112 MPUREG_EXT_SLV_SENS_DATA_02, /* 0x00 */
113 MPUREG_EXT_SLV_SENS_DATA_03, /* 0x00 */
114 MPUREG_EXT_SLV_SENS_DATA_04, /* 0x00 */
115 MPUREG_EXT_SLV_SENS_DATA_05, /* 0x00 */
116 MPUREG_EXT_SLV_SENS_DATA_06, /* 0x4F */
117 MPUREG_EXT_SLV_SENS_DATA_07, /* 0x00 */
118 MPUREG_EXT_SLV_SENS_DATA_08, /* 0x00 */
119 MPUREG_EXT_SLV_SENS_DATA_09, /* 0x00 */
120 MPUREG_EXT_SLV_SENS_DATA_10, /* 0x00 */
121 MPUREG_EXT_SLV_SENS_DATA_11, /* 0x00 */
122 MPUREG_EXT_SLV_SENS_DATA_12, /* 0x55 */
123 MPUREG_EXT_SLV_SENS_DATA_13, /* 0x00 */
124 MPUREG_EXT_SLV_SENS_DATA_14, /* 0x00 */
125 MPUREG_EXT_SLV_SENS_DATA_15, /* 0x00 */
126 MPUREG_EXT_SLV_SENS_DATA_16, /* 0x00 */
127 MPUREG_EXT_SLV_SENS_DATA_17, /* 0x00 */
128 MPUREG_EXT_SLV_SENS_DATA_18, /* 0x5B */
129 MPUREG_EXT_SLV_SENS_DATA_19, /* 0x00 */
130 MPUREG_EXT_SLV_SENS_DATA_20, /* 0x00 */
131 MPUREG_EXT_SLV_SENS_DATA_21, /* 0x00 */
132 MPUREG_EXT_SLV_SENS_DATA_22, /* 0x00 */
133 MPUREG_EXT_SLV_SENS_DATA_23, /* 0x00 */
134 ACCEL_INTEL_STATUS, /* 0x61 */
135 MPUREG_62_RSVD, /* 0x00 */
136 MPUREG_63_RSVD, /* 0x00 */
137 MPUREG_64_RSVD, /* 0x00 */
138 MPUREG_65_RSVD, /* 0x00 */
139 MPUREG_66_RSVD, /* 0x00 */
140 MPUREG_67_RSVD, /* 0x00 */
141 SIGNAL_PATH_RESET, /* 0x68 */
142 ACCEL_INTEL_CTRL, /* 0x69 */
143 MPUREG_USER_CTRL, /* 0x6A */
144 MPUREG_PWR_MGMT_1, /* 0x6B */
145 MPUREG_PWR_MGMT_2, /* 0x00 */
146 MPUREG_BANK_SEL, /* 0x6D */
147 MPUREG_MEM_START_ADDR, /* 0x6E */
148 MPUREG_MEM_R_W, /* 0x6F */
149 MPUREG_PRGM_STRT_ADDRH, /* 0x00 */
150 MPUREG_PRGM_STRT_ADDRL, /* 0x00 */
151 MPUREG_FIFO_COUNTH, /* 0x72 */
152 MPUREG_FIFO_COUNTL, /* 0x00 */
153 MPUREG_FIFO_R_W, /* 0x74 */
154 MPUREG_WHOAMI, /* 0x75,117 */
155
156 NUM_OF_MPU_REGISTERS /* = 0x76,118 */
157};
158
159/*==== M_HW MEMORY ====*/
160enum MPU_MEMORY_BANKS {
161 MEM_RAM_BANK_0 = 0,
162 MEM_RAM_BANK_1,
163 MEM_RAM_BANK_2,
164 MEM_RAM_BANK_3,
165 MEM_RAM_BANK_4,
166 MEM_RAM_BANK_5,
167 MEM_RAM_BANK_6,
168 MEM_RAM_BANK_7,
169 MEM_RAM_BANK_8,
170 MEM_RAM_BANK_9,
171 MEM_RAM_BANK_10,
172 MEM_RAM_BANK_11,
173 MPU_MEM_NUM_RAM_BANKS,
174 MPU_MEM_OTP_BANK_0 = 16
175};
176
177
178/*==== M_HW parameters ====*/
179
180#define NUM_REGS (NUM_OF_MPU_REGISTERS)
181#define START_SENS_REGS (0x3B)
182#define NUM_SENS_REGS (0x60-START_SENS_REGS+1)
183
184/*---- MPU Memory ----*/
185#define NUM_BANKS (MPU_MEM_NUM_RAM_BANKS)
186#define BANK_SIZE (256)
187#define MEM_SIZE (NUM_BANKS*BANK_SIZE)
188#define MPU_MEM_BANK_SIZE (BANK_SIZE) /*alternative name */
189
190#define FIFO_HW_SIZE (1024)
191
192#define NUM_EXT_SLAVES (4)
193
194
195/*==== BITS FOR M_HW ====*/
196
197/*---- M_HW 'FIFO_EN' register (23) ----*/
198#define BIT_TEMP_OUT 0x80
199#define BIT_GYRO_XOUT 0x40
200#define BIT_GYRO_YOUT 0x20
201#define BIT_GYRO_ZOUT 0x10
202#define BIT_ACCEL 0x08
203#define BIT_SLV_2 0x04
204#define BIT_SLV_1 0x02
205#define BIT_SLV_0 0x01
206/*---- M_HW 'CONFIG' register (1A) ----*/
207/*NONE 0xC0 */
208#define BITS_EXT_SYNC_SET 0x38
209#define BITS_DLPF_CFG 0x07
210/*---- M_HW 'GYRO_CONFIG' register (1B) ----*/
211/* voluntarily modified label from BITS_FS_SEL to
212 * BITS_GYRO_FS_SEL to avoid confusion with MPU
213 */
214#define BITS_GYRO_FS_SEL 0x18
215/*NONE 0x07 */
216/*---- M_HW 'ACCEL_CONFIG' register (1C) ----*/
217#define BITS_ACCEL_FS_SEL 0x18
218#define BITS_ACCEL_HPF 0x07
219/*---- M_HW 'I2C_MST_CTRL' register (24) ----*/
220#define BIT_MULT_MST_DIS 0x80
221#define BIT_WAIT_FOR_ES 0x40
222#define BIT_I2C_MST_VDDIO 0x20
223/*NONE 0x10 */
224#define BITS_I2C_MST_CLK 0x0F
225/*---- M_HW 'I2C_SLV?_CTRL' register (27,2A,2D,30) ----*/
226#define BIT_SLV_ENABLE 0x80
227#define BIT_SLV_BYTE_SW 0x40
228/*NONE 0x20 */
229#define BIT_SLV_GRP 0x10
230#define BITS_SLV_LENG 0x0F
231/*---- M_HW 'I2C_SLV4_ADDR' register (31) ----*/
232#define BIT_I2C_SLV4_RNW 0x80
233/*---- M_HW 'I2C_SLV4_CTRL' register (34) ----*/
234#define BIT_I2C_SLV4_EN 0x80
235#define BIT_SLV4_DONE_INT_EN 0x40
236/*NONE 0x3F */
237/*---- M_HW 'I2C_MST_STATUS' register (36) ----*/
238#define BIT_PASSTHROUGH 0x80
239#define BIT_I2C_SLV4_DONE 0x40
240#define BIT_I2C_LOST_ARB 0x20
241#define BIT_I2C_SLV4_NACK 0x10
242#define BIT_I2C_SLV3_NACK 0x08
243#define BIT_I2C_SLV2_NACK 0x04
244#define BIT_I2C_SLV1_NACK 0x02
245#define BIT_I2C_SLV0_NACK 0x01
246/*---- M_HW 'INT_PIN_CFG' register (37) ----*/
247#define BIT_ACTL 0x80
248#define BIT_ACTL_LOW 0x80
249#define BIT_ACTL_HIGH 0x00
250#define BIT_OPEN 0x40
251#define BIT_LATCH_INT_EN 0x20
252#define BIT_INT_ANYRD_2CLEAR 0x10
253#define BIT_ACTL_FSYNC 0x08
254#define BIT_FSYNC_INT_EN 0x04
255#define BIT_BYPASS_EN 0x02
256#define BIT_CLKOUT_EN 0x01
257/*---- M_HW 'INT_ENABLE' register (38) ----*/
258#define BIT_FF_EN 0x80
259#define BIT_MOT_EN 0x40
260#define BIT_ZMOT_EN 0x20
261#define BIT_FIFO_OVERFLOW_EN 0x10
262#define BIT_I2C_MST_INT_EN 0x08
263#define BIT_PLL_RDY_EN 0x04
264#define BIT_DMP_INT_EN 0x02
265#define BIT_RAW_RDY_EN 0x01
266/*---- M_HW 'DMP_INT_STATUS' register (39) ----*/
267/*NONE 0x80 */
268/*NONE 0x40 */
269#define BIT_DMP_INT_5 0x20
270#define BIT_DMP_INT_4 0x10
271#define BIT_DMP_INT_3 0x08
272#define BIT_DMP_INT_2 0x04
273#define BIT_DMP_INT_1 0x02
274#define BIT_DMP_INT_0 0x01
275/*---- M_HW 'INT_STATUS' register (3A) ----*/
276#define BIT_FF_INT 0x80
277#define BIT_MOT_INT 0x40
278#define BIT_ZMOT_INT 0x20
279#define BIT_FIFO_OVERFLOW_INT 0x10
280#define BIT_I2C_MST_INT 0x08
281#define BIT_PLL_RDY_INT 0x04
282#define BIT_DMP_INT 0x02
283#define BIT_RAW_DATA_RDY_INT 0x01
284/*---- M_HW 'BANK_SEL' register (6D) ----*/
285#define BIT_PRFTCH_EN 0x40
286#define BIT_CFG_USER_BANK 0x20
287#define BITS_MEM_SEL 0x1f
288/*---- M_HW 'USER_CTRL' register (6A) ----*/
289#define BIT_DMP_EN 0x80
290#define BIT_FIFO_EN 0x40
291#define BIT_I2C_MST_EN 0x20
292#define BIT_I2C_IF_DIS 0x10
293#define BIT_DMP_RST 0x08
294#define BIT_FIFO_RST 0x04
295#define BIT_I2C_MST_RST 0x02
296#define BIT_SIG_COND_RST 0x01
297/*---- M_HW 'PWR_MGMT_1' register (6B) ----*/
298#define BIT_H_RESET 0x80
299#define BITS_PWRSEL 0x70
300#define BIT_WKUP_INT 0x08
301#define BITS_CLKSEL 0x07
302/*---- M_HW 'PWR_MGMT_2' register (6C) ----*/
303#define BITS_LPA_WAKE_CTRL 0xC0
304#define BIT_STBY_XA 0x20
305#define BIT_STBY_YA 0x10
306#define BIT_STBY_ZA 0x08
307#define BIT_STBY_XG 0x04
308#define BIT_STBY_YG 0x02
309#define BIT_STBY_ZG 0x01
310
311/* although it has 6, this refers to the gyros */
312#define MPU_NUM_AXES (3)
313
314#define ACCEL_MOT_THR_LSB (32) /* mg */
315#define ACCEL_MOT_DUR_LSB (1)
316#define ACCEL_ZRMOT_THR_LSB_CONVERSION(mg) ((mg *1000)/255)
317#define ACCEL_ZRMOT_DUR_LSB (64)
318
319/*----------------------------------------------------------------------------*/
320/*---- Alternative names to take care of conflicts with current mpu3050.h ----*/
321/*----------------------------------------------------------------------------*/
322
323/*-- registers --*/
324#define MPUREG_DLPF_FS_SYNC MPUREG_CONFIG /* 0x1A */
325
326#define MPUREG_PRODUCT_ID MPUREG_WHOAMI /* 0x75 HACK!*/
327#define MPUREG_PWR_MGM MPUREG_PWR_MGMT_1 /* 0x6B */
328#define MPUREG_FIFO_EN1 MPUREG_FIFO_EN /* 0x23 */
329#define MPUREG_DMP_CFG_1 MPUREG_PRGM_STRT_ADDRH /* 0x70 */
330#define MPUREG_DMP_CFG_2 MPUREG_PRGM_STRT_ADDRL /* 0x71 */
331#define MPUREG_INT_CFG MPUREG_INT_ENABLE /* 0x38 */
332#define MPUREG_X_OFFS_USRH MPUREG_XG_OFFS_USRH /* 0x13 */
333#define MPUREG_WHO_AM_I MPUREG_WHOAMI /* 0x75 */
334#define MPUREG_23_RSVD MPUREG_EXT_SLV_SENS_DATA_00 /* 0x49 */
335#define MPUREG_AUX_SLV_ADDR MPUREG_I2C_SLV0_ADDR /* 0x25 */
336#define MPUREG_ACCEL_BURST_ADDR MPUREG_I2C_SLV0_REG /* 0x26 */
337
338/*-- bits --*/
339/* 'USER_CTRL' register */
340#define BIT_AUX_IF_EN BIT_I2C_MST_EN
341#define BIT_AUX_RD_LENG BIT_I2C_MST_EN
342#define BIT_IME_IF_RST BIT_I2C_MST_RST
343#define BIT_GYRO_RST BIT_SIG_COND_RST
344/* 'INT_ENABLE' register */
345#define BIT_RAW_RDY BIT_RAW_DATA_RDY_INT
346#define BIT_MPU_RDY_EN BIT_PLL_RDY_EN
347/* 'INT_STATUS' register */
348#define BIT_INT_STATUS_FIFO_OVERLOW BIT_FIFO_OVERFLOW_INT
349
350
351
352/*---- M_HW Silicon Revisions ----*/
353#define MPU_SILICON_REV_A1 1 /* M_HW A1 Device */
354#define MPU_SILICON_REV_B1 2 /* M_HW B1 Device */
355
356/*---- structure containing control variables used by MLDL ----*/
357/*---- MPU clock source settings ----*/
358/*---- MPU filter selections ----*/
359enum mpu_filter {
360 MPU_FILTER_256HZ_NOLPF2 = 0,
361 MPU_FILTER_188HZ,
362 MPU_FILTER_98HZ,
363 MPU_FILTER_42HZ,
364 MPU_FILTER_20HZ,
365 MPU_FILTER_10HZ,
366 MPU_FILTER_5HZ,
367 MPU_FILTER_2100HZ_NOLPF,
368 NUM_MPU_FILTER
369};
370
371enum mpu_fullscale {
372 MPU_FS_250DPS = 0,
373 MPU_FS_500DPS,
374 MPU_FS_1000DPS,
375 MPU_FS_2000DPS,
376 NUM_MPU_FS
377};
378
379enum mpu_clock_sel {
380 MPU_CLK_SEL_INTERNAL = 0,
381 MPU_CLK_SEL_PLLGYROX,
382 MPU_CLK_SEL_PLLGYROY,
383 MPU_CLK_SEL_PLLGYROZ,
384 MPU_CLK_SEL_PLLEXT32K,
385 MPU_CLK_SEL_PLLEXT19M,
386 MPU_CLK_SEL_RESERVED,
387 MPU_CLK_SEL_STOP,
388 NUM_CLK_SEL
389};
390
391enum mpu_ext_sync {
392 MPU_EXT_SYNC_NONE = 0,
393 MPU_EXT_SYNC_TEMP,
394 MPU_EXT_SYNC_GYROX,
395 MPU_EXT_SYNC_GYROY,
396 MPU_EXT_SYNC_GYROZ,
397 MPU_EXT_SYNC_ACCELX,
398 MPU_EXT_SYNC_ACCELY,
399 MPU_EXT_SYNC_ACCELZ,
400 NUM_MPU_EXT_SYNC
401};
402
403#define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \
404 ((ext_sync << 5) | (full_scale << 3) | lpf)
405
406#endif /* __IMU6000_H_ */
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