aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/mlx4
diff options
context:
space:
mode:
authorOr Gerlitz <ogerlitz@mellanox.com>2011-06-15 10:41:42 -0400
committerRoland Dreier <roland@purestorage.com>2011-07-19 00:04:32 -0400
commit52eafc68d601afd699b023201b0c6be5209f39ce (patch)
tree01a65357f2f39b07836c44f8b2cd490e5cd62853 /include/linux/mlx4
parent6451c712fef3b13bb3fc5a41adadc539e0d06a42 (diff)
mlx4_core: Extend capability flags to 64 bits
The latest firmware adds a second dword containing more device flags, so extend the device capabilities flags field from 32 to 64 bits. Derived from patch by Eli Cohen <eli@mellanox.co.il> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.co.il> Signed-off-by: Roland Dreier <roland@purestorage.com>
Diffstat (limited to 'include/linux/mlx4')
-rw-r--r--include/linux/mlx4/device.h34
1 files changed, 17 insertions, 17 deletions
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 8985768e2c0..f337e989b70 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -58,22 +58,22 @@ enum {
58}; 58};
59 59
60enum { 60enum {
61 MLX4_DEV_CAP_FLAG_RC = 1 << 0, 61 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
62 MLX4_DEV_CAP_FLAG_UC = 1 << 1, 62 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
63 MLX4_DEV_CAP_FLAG_UD = 1 << 2, 63 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
64 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6, 64 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
65 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7, 65 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
66 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8, 66 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
67 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9, 67 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
68 MLX4_DEV_CAP_FLAG_DPDP = 1 << 12, 68 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
69 MLX4_DEV_CAP_FLAG_BLH = 1 << 15, 69 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
70 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16, 70 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
71 MLX4_DEV_CAP_FLAG_APM = 1 << 17, 71 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
72 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18, 72 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
73 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19, 73 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
74 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20, 74 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
75 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21, 75 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
76 MLX4_DEV_CAP_FLAG_IBOE = 1 << 30 76 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30
77}; 77};
78 78
79enum { 79enum {
@@ -253,7 +253,7 @@ struct mlx4_caps {
253 int mtt_entry_sz; 253 int mtt_entry_sz;
254 u32 max_msg_sz; 254 u32 max_msg_sz;
255 u32 page_size_cap; 255 u32 page_size_cap;
256 u32 flags; 256 u64 flags;
257 u32 bmme_flags; 257 u32 bmme_flags;
258 u32 reserved_lkey; 258 u32 reserved_lkey;
259 u16 stat_rate_support; 259 u16 stat_rate_support;