Patched in Tegra support.

81 files changed, 1043 insertions, 21471 deletions

diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h
deleted file mode 100644
index 478672ed0c3..00000000000
--- a/include/linux/mfd/88pm80x.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * Marvell 88PM80x Interface
- *
- * Copyright (C) 2012 Marvell International Ltd.
- * Qiao Zhou <zhouqiao@marvell.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __LINUX_MFD_88PM80X_H
-#define __LINUX_MFD_88PM80X_H
-
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/regmap.h>
-#include <linux/atomic.h>
-
-#define PM80X_VERSION_MASK              (0xFF)  /* 80X chip ID mask */
-enum {
-        CHIP_INVALID = 0,
-        CHIP_PM800,
-        CHIP_PM805,
-        CHIP_MAX,
-};
-
-enum {
-        PM800_ID_BUCK1 = 0,
-        PM800_ID_BUCK2,
-        PM800_ID_BUCK3,
-        PM800_ID_BUCK4,
-        PM800_ID_BUCK5,
-
-        PM800_ID_LDO1,
-        PM800_ID_LDO2,
-        PM800_ID_LDO3,
-        PM800_ID_LDO4,
-        PM800_ID_LDO5,
-        PM800_ID_LDO6,
-        PM800_ID_LDO7,
-        PM800_ID_LDO8,
-        PM800_ID_LDO9,
-        PM800_ID_LDO10,
-        PM800_ID_LDO11,
-        PM800_ID_LDO12,
-        PM800_ID_LDO13,
-        PM800_ID_LDO14,
-        PM800_ID_LDO15,
-        PM800_ID_LDO16,
-        PM800_ID_LDO17,
-        PM800_ID_LDO18,
-        PM800_ID_LDO19,
-
-        PM800_ID_RG_MAX,
-};
-#define PM800_MAX_REGULATOR     PM800_ID_RG_MAX /* 5 Bucks, 19 LDOs */
-#define PM800_NUM_BUCK (5)      /*5 Bucks */
-#define PM800_NUM_LDO (19)      /*19 Bucks */
-
-/* page 0 basic: slave adder 0x60 */
-
-#define PM800_STATUS_1                  (0x01)
-#define PM800_ONKEY_STS1                (1 << 0)
-#define PM800_EXTON_STS1                (1 << 1)
-#define PM800_CHG_STS1                  (1 << 2)
-#define PM800_BAT_STS1                  (1 << 3)
-#define PM800_VBUS_STS1                 (1 << 4)
-#define PM800_LDO_PGOOD_STS1    (1 << 5)
-#define PM800_BUCK_PGOOD_STS1   (1 << 6)
-
-#define PM800_STATUS_2                  (0x02)
-#define PM800_RTC_ALARM_STS2    (1 << 0)
-
-/* Wakeup Registers */
-#define PM800_WAKEUP1           (0x0D)
-
-#define PM800_WAKEUP2           (0x0E)
-#define PM800_WAKEUP2_INV_INT           (1 << 0)
-#define PM800_WAKEUP2_INT_CLEAR         (1 << 1)
-#define PM800_WAKEUP2_INT_MASK          (1 << 2)
-
-#define PM800_POWER_UP_LOG      (0x10)
-
-/* Referance and low power registers */
-#define PM800_LOW_POWER1                (0x20)
-#define PM800_LOW_POWER2                (0x21)
-#define PM800_LOW_POWER_CONFIG3 (0x22)
-#define PM800_LOW_POWER_CONFIG4 (0x23)
-
-/* GPIO register */
-#define PM800_GPIO_0_1_CNTRL            (0x30)
-#define PM800_GPIO0_VAL                         (1 << 0)
-#define PM800_GPIO0_GPIO_MODE(x)        (x << 1)
-#define PM800_GPIO1_VAL                         (1 << 4)
-#define PM800_GPIO1_GPIO_MODE(x)        (x << 5)
-
-#define PM800_GPIO_2_3_CNTRL            (0x31)
-#define PM800_GPIO2_VAL                         (1 << 0)
-#define PM800_GPIO2_GPIO_MODE(x)        (x << 1)
-#define PM800_GPIO3_VAL                         (1 << 4)
-#define PM800_GPIO3_GPIO_MODE(x)        (x << 5)
-#define PM800_GPIO3_MODE_MASK           0x1F
-#define PM800_GPIO3_HEADSET_MODE        PM800_GPIO3_GPIO_MODE(6)
-
-#define PM800_GPIO_4_CNTRL                      (0x32)
-#define PM800_GPIO4_VAL                         (1 << 0)
-#define PM800_GPIO4_GPIO_MODE(x)        (x << 1)
-
-#define PM800_HEADSET_CNTRL             (0x38)
-#define PM800_HEADSET_DET_EN            (1 << 7)
-#define PM800_HSDET_SLP                 (1 << 1)
-/* PWM register */
-#define PM800_PWM1              (0x40)
-#define PM800_PWM2              (0x41)
-#define PM800_PWM3              (0x42)
-#define PM800_PWM4              (0x43)
-
-/* RTC Registers */
-#define PM800_RTC_CONTROL               (0xD0)
-#define PM800_RTC_MISC1                 (0xE1)
-#define PM800_RTC_MISC2                 (0xE2)
-#define PM800_RTC_MISC3                 (0xE3)
-#define PM800_RTC_MISC4                 (0xE4)
-#define PM800_RTC_MISC5                 (0xE7)
-/* bit definitions of RTC Register 1 (0xD0) */
-#define PM800_ALARM1_EN                 (1 << 0)
-#define PM800_ALARM_WAKEUP              (1 << 4)
-#define PM800_ALARM                     (1 << 5)
-#define PM800_RTC1_USE_XO               (1 << 7)
-
-/* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */
-
-/* buck registers */
-#define PM800_SLEEP_BUCK1       (0x30)
-
-/* BUCK Sleep Mode Register 1: BUCK[1..4] */
-#define PM800_BUCK_SLP1         (0x5A)
-#define PM800_BUCK1_SLP1_SHIFT  0
-#define PM800_BUCK1_SLP1_MASK   (0x3 << PM800_BUCK1_SLP1_SHIFT)
-
-/* page 2 GPADC: slave adder 0x02 */
-#define PM800_GPADC_MEAS_EN1            (0x01)
-#define PM800_MEAS_EN1_VBAT         (1 << 2)
-#define PM800_GPADC_MEAS_EN2            (0x02)
-#define PM800_MEAS_EN2_RFTMP        (1 << 0)
-#define PM800_MEAS_GP0_EN                       (1 << 2)
-#define PM800_MEAS_GP1_EN                       (1 << 3)
-#define PM800_MEAS_GP2_EN                       (1 << 4)
-#define PM800_MEAS_GP3_EN                       (1 << 5)
-#define PM800_MEAS_GP4_EN                       (1 << 6)
-
-#define PM800_GPADC_MISC_CONFIG1        (0x05)
-#define PM800_GPADC_MISC_CONFIG2        (0x06)
-#define PM800_GPADC_MISC_GPFSM_EN       (1 << 0)
-#define PM800_GPADC_SLOW_MODE(x)        (x << 3)
-
-#define PM800_GPADC_MISC_CONFIG3                (0x09)
-#define PM800_GPADC_MISC_CONFIG4                (0x0A)
-
-#define PM800_GPADC_PREBIAS1                    (0x0F)
-#define PM800_GPADC0_GP_PREBIAS_TIME(x) (x << 0)
-#define PM800_GPADC_PREBIAS2                    (0x10)
-
-#define PM800_GP_BIAS_ENA1                              (0x14)
-#define PM800_GPADC_GP_BIAS_EN0                 (1 << 0)
-#define PM800_GPADC_GP_BIAS_EN1                 (1 << 1)
-#define PM800_GPADC_GP_BIAS_EN2                 (1 << 2)
-#define PM800_GPADC_GP_BIAS_EN3                 (1 << 3)
-
-#define PM800_GP_BIAS_OUT1              (0x15)
-#define PM800_BIAS_OUT_GP0              (1 << 0)
-#define PM800_BIAS_OUT_GP1              (1 << 1)
-#define PM800_BIAS_OUT_GP2              (1 << 2)
-#define PM800_BIAS_OUT_GP3              (1 << 3)
-
-#define PM800_GPADC0_LOW_TH             0x20
-#define PM800_GPADC1_LOW_TH             0x21
-#define PM800_GPADC2_LOW_TH             0x22
-#define PM800_GPADC3_LOW_TH             0x23
-#define PM800_GPADC4_LOW_TH             0x24
-
-#define PM800_GPADC0_UPP_TH             0x30
-#define PM800_GPADC1_UPP_TH             0x31
-#define PM800_GPADC2_UPP_TH             0x32
-#define PM800_GPADC3_UPP_TH             0x33
-#define PM800_GPADC4_UPP_TH             0x34
-
-#define PM800_VBBAT_MEAS1               0x40
-#define PM800_VBBAT_MEAS2               0x41
-#define PM800_VBAT_MEAS1                0x42
-#define PM800_VBAT_MEAS2                0x43
-#define PM800_VSYS_MEAS1                0x44
-#define PM800_VSYS_MEAS2                0x45
-#define PM800_VCHG_MEAS1                0x46
-#define PM800_VCHG_MEAS2                0x47
-#define PM800_TINT_MEAS1                0x50
-#define PM800_TINT_MEAS2                0x51
-#define PM800_PMOD_MEAS1                0x52
-#define PM800_PMOD_MEAS2                0x53
-
-#define PM800_GPADC0_MEAS1              0x54
-#define PM800_GPADC0_MEAS2              0x55
-#define PM800_GPADC1_MEAS1              0x56
-#define PM800_GPADC1_MEAS2              0x57
-#define PM800_GPADC2_MEAS1              0x58
-#define PM800_GPADC2_MEAS2              0x59
-#define PM800_GPADC3_MEAS1              0x5A
-#define PM800_GPADC3_MEAS2              0x5B
-#define PM800_GPADC4_MEAS1              0x5C
-#define PM800_GPADC4_MEAS2              0x5D
-
-#define PM800_GPADC4_AVG1               0xA8
-#define PM800_GPADC4_AVG2               0xA9
-
-/* 88PM805 Registers */
-#define PM805_MAIN_POWERUP              (0x01)
-#define PM805_INT_STATUS0               (0x02)  /* for ena/dis all interrupts */
-
-#define PM805_STATUS0_INT_CLEAR         (1 << 0)
-#define PM805_STATUS0_INV_INT           (1 << 1)
-#define PM800_STATUS0_INT_MASK          (1 << 2)
-
-#define PM805_INT_STATUS1               (0x03)
-
-#define PM805_INT1_HP1_SHRT             (1 << 0)
-#define PM805_INT1_HP2_SHRT             (1 << 1)
-#define PM805_INT1_MIC_CONFLICT         (1 << 2)
-#define PM805_INT1_CLIP_FAULT           (1 << 3)
-#define PM805_INT1_LDO_OFF                      (1 << 4)
-#define PM805_INT1_SRC_DPLL_LOCK        (1 << 5)
-
-#define PM805_INT_STATUS2               (0x04)
-
-#define PM805_INT2_MIC_DET                      (1 << 0)
-#define PM805_INT2_SHRT_BTN_DET         (1 << 1)
-#define PM805_INT2_VOLM_BTN_DET         (1 << 2)
-#define PM805_INT2_VOLP_BTN_DET         (1 << 3)
-#define PM805_INT2_RAW_PLL_FAULT        (1 << 4)
-#define PM805_INT2_FINE_PLL_FAULT       (1 << 5)
-
-#define PM805_INT_MASK1                 (0x05)
-#define PM805_INT_MASK2                 (0x06)
-#define PM805_SHRT_BTN_DET              (1 << 1)
-
-/* number of status and int reg in a row */
-#define PM805_INT_REG_NUM               (2)
-
-#define PM805_MIC_DET1                  (0x07)
-#define PM805_MIC_DET_EN_MIC_DET (1 << 0)
-#define PM805_MIC_DET2                  (0x08)
-#define PM805_MIC_DET_STATUS1   (0x09)
-
-#define PM805_MIC_DET_STATUS3   (0x0A)
-#define PM805_AUTO_SEQ_STATUS1  (0x0B)
-#define PM805_AUTO_SEQ_STATUS2  (0x0C)
-
-#define PM805_ADC_SETTING1              (0x10)
-#define PM805_ADC_SETTING2              (0x11)
-#define PM805_ADC_SETTING3              (0x11)
-#define PM805_ADC_GAIN1                 (0x12)
-#define PM805_ADC_GAIN2                 (0x13)
-#define PM805_DMIC_SETTING              (0x15)
-#define PM805_DWS_SETTING               (0x16)
-#define PM805_MIC_CONFLICT_STS  (0x17)
-
-#define PM805_PDM_SETTING1              (0x20)
-#define PM805_PDM_SETTING2              (0x21)
-#define PM805_PDM_SETTING3              (0x22)
-#define PM805_PDM_CONTROL1              (0x23)
-#define PM805_PDM_CONTROL2              (0x24)
-#define PM805_PDM_CONTROL3              (0x25)
-
-#define PM805_HEADPHONE_SETTING                 (0x26)
-#define PM805_HEADPHONE_GAIN_A2A                (0x27)
-#define PM805_HEADPHONE_SHORT_STATE             (0x28)
-#define PM805_EARPHONE_SETTING                  (0x29)
-#define PM805_AUTO_SEQ_SETTING                  (0x2A)
-
-struct pm80x_rtc_pdata {
-        int             vrtc;
-        int             rtc_wakeup;
-};
-
-struct pm80x_subchip {
-        struct i2c_client *power_page;  /* chip client for power page */
-        struct i2c_client *gpadc_page;  /* chip client for gpadc page */
-        struct regmap *regmap_power;
-        struct regmap *regmap_gpadc;
-        unsigned short power_page_addr; /* power page I2C address */
-        unsigned short gpadc_page_addr; /* gpadc page I2C address */
-};
-
-struct pm80x_chip {
-        struct pm80x_subchip *subchip;
-        struct device *dev;
-        struct i2c_client *client;
-        struct i2c_client *companion;
-        struct regmap *regmap;
-        struct regmap_irq_chip *regmap_irq_chip;
-        struct regmap_irq_chip_data *irq_data;
-        unsigned char version;
-        int id;
-        int irq;
-        int irq_mode;
-        unsigned long wu_flag;
-        spinlock_t lock;
-};
-
-struct pm80x_platform_data {
-        struct pm80x_rtc_pdata *rtc;
-        unsigned short power_page_addr; /* power page I2C address */
-        unsigned short gpadc_page_addr; /* gpadc page I2C address */
-        int irq_mode;           /* Clear interrupt by read/write(0/1) */
-        int batt_det;           /* enable/disable */
-        int (*plat_config)(struct pm80x_chip *chip,
-                                struct pm80x_platform_data *pdata);
-};
-
-extern const struct dev_pm_ops pm80x_pm_ops;
-extern const struct regmap_config pm80x_regmap_config;
-
-static inline int pm80x_request_irq(struct pm80x_chip *pm80x, int irq,
-                                     irq_handler_t handler, unsigned long flags,
-                                     const char *name, void *data)
-{
-        if (!pm80x->irq_data)
-                return -EINVAL;
-        return request_threaded_irq(regmap_irq_get_virq(pm80x->irq_data, irq),
-                                    NULL, handler, flags, name, data);
-}
-
-static inline void pm80x_free_irq(struct pm80x_chip *pm80x, int irq, void *data)
-{
-        if (!pm80x->irq_data)
-                return;
-        free_irq(regmap_irq_get_virq(pm80x->irq_data, irq), data);
-}
-
-#ifdef CONFIG_PM
-static inline int pm80x_dev_suspend(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
-        int irq = platform_get_irq(pdev, 0);
-
-        if (device_may_wakeup(dev))
-                set_bit((1 << irq), &chip->wu_flag);
-
-        return 0;
-}
-
-static inline int pm80x_dev_resume(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
-        int irq = platform_get_irq(pdev, 0);
-
-        if (device_may_wakeup(dev))
-                clear_bit((1 << irq), &chip->wu_flag);
-
-        return 0;
-}
-#endif
-
-extern int pm80x_init(struct i2c_client *client,
-                      const struct i2c_device_id *id);
-extern int pm80x_deinit(struct i2c_client *client);
-#endif /* __LINUX_MFD_88PM80X_H */
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index cd97530205c..63b4fb8e3b6 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -34,26 +34,27 @@ enum {
         PM8606_ID_MAX,
 };
 
+enum {
+        PM8606_BACKLIGHT1 = 0,
+        PM8606_BACKLIGHT2,
+        PM8606_BACKLIGHT3,
+};
+
+enum {
+        PM8606_LED1_RED = 0,
+        PM8606_LED1_GREEN,
+        PM8606_LED1_BLUE,
+        PM8606_LED2_RED,
+        PM8606_LED2_GREEN,
+        PM8606_LED2_BLUE,
+        PM8607_LED_VIBRATOR,
+};
+
 
 /* 8606 Registers */
 #define PM8606_DCM_BOOST                (0x00)
 #define PM8606_PWM                      (0x01)
 
-#define PM8607_MISC2                    (0x42)
-
-/* Power Up Log Register */
-#define PM8607_POWER_UP_LOG             (0x3F)
-
-/* Charger Control Registers */
-#define PM8607_CCNT                     (0x47)
-#define PM8607_CHG_CTRL1                (0x48)
-#define PM8607_CHG_CTRL2                (0x49)
-#define PM8607_CHG_CTRL3                (0x4A)
-#define PM8607_CHG_CTRL4                (0x4B)
-#define PM8607_CHG_CTRL5                (0x4C)
-#define PM8607_CHG_CTRL6                (0x4D)
-#define PM8607_CHG_CTRL7                (0x4E)
-
 /* Backlight Registers */
 #define PM8606_WLED1A                   (0x02)
 #define PM8606_WLED1B                   (0x03)
@@ -135,7 +136,6 @@ enum {
         PM8607_ID_LDO13,
         PM8607_ID_LDO14,
         PM8607_ID_LDO15,
-        PM8606_ID_PREG,
 
         PM8607_ID_RG_MAX,
 };
@@ -204,71 +204,6 @@ enum {
 #define PM8607_PD_PREBIAS               (0x56)  /* prebias time */
 #define PM8607_GPADC_MISC1              (0x57)
 
-/* bit definitions of  MEAS_EN1*/
-#define PM8607_MEAS_EN1_VBAT            (1 << 0)
-#define PM8607_MEAS_EN1_VCHG            (1 << 1)
-#define PM8607_MEAS_EN1_VSYS            (1 << 2)
-#define PM8607_MEAS_EN1_TINT            (1 << 3)
-#define PM8607_MEAS_EN1_RFTMP           (1 << 4)
-#define PM8607_MEAS_EN1_TBAT            (1 << 5)
-#define PM8607_MEAS_EN1_GPADC2          (1 << 6)
-#define PM8607_MEAS_EN1_GPADC3          (1 << 7)
-
-/* Battery Monitor Registers */
-#define PM8607_GP_BIAS2                 (0x5A)
-#define PM8607_VBAT_LOWTH               (0x5B)
-#define PM8607_VCHG_LOWTH               (0x5C)
-#define PM8607_VSYS_LOWTH               (0x5D)
-#define PM8607_TINT_LOWTH               (0x5E)
-#define PM8607_GPADC0_LOWTH             (0x5F)
-#define PM8607_GPADC1_LOWTH             (0x60)
-#define PM8607_GPADC2_LOWTH             (0x61)
-#define PM8607_GPADC3_LOWTH             (0x62)
-#define PM8607_VBAT_HIGHTH              (0x63)
-#define PM8607_VCHG_HIGHTH              (0x64)
-#define PM8607_VSYS_HIGHTH              (0x65)
-#define PM8607_TINT_HIGHTH              (0x66)
-#define PM8607_GPADC0_HIGHTH            (0x67)
-#define PM8607_GPADC1_HIGHTH            (0x68)
-#define PM8607_GPADC2_HIGHTH            (0x69)
-#define PM8607_GPADC3_HIGHTH            (0x6A)
-#define PM8607_IBAT_MEAS1               (0x6B)
-#define PM8607_IBAT_MEAS2               (0x6C)
-#define PM8607_VBAT_MEAS1               (0x6D)
-#define PM8607_VBAT_MEAS2               (0x6E)
-#define PM8607_VCHG_MEAS1               (0x6F)
-#define PM8607_VCHG_MEAS2               (0x70)
-#define PM8607_VSYS_MEAS1               (0x71)
-#define PM8607_VSYS_MEAS2               (0x72)
-#define PM8607_TINT_MEAS1               (0x73)
-#define PM8607_TINT_MEAS2               (0x74)
-#define PM8607_GPADC0_MEAS1             (0x75)
-#define PM8607_GPADC0_MEAS2             (0x76)
-#define PM8607_GPADC1_MEAS1             (0x77)
-#define PM8607_GPADC1_MEAS2             (0x78)
-#define PM8607_GPADC2_MEAS1             (0x79)
-#define PM8607_GPADC2_MEAS2             (0x7A)
-#define PM8607_GPADC3_MEAS1             (0x7B)
-#define PM8607_GPADC3_MEAS2             (0x7C)
-#define PM8607_CCNT_MEAS1               (0x95)
-#define PM8607_CCNT_MEAS2               (0x96)
-#define PM8607_VBAT_AVG                 (0x97)
-#define PM8607_VCHG_AVG                 (0x98)
-#define PM8607_VSYS_AVG                 (0x99)
-#define PM8607_VBAT_MIN                 (0x9A)
-#define PM8607_VCHG_MIN                 (0x9B)
-#define PM8607_VSYS_MIN                 (0x9C)
-#define PM8607_VBAT_MAX                 (0x9D)
-#define PM8607_VCHG_MAX                 (0x9E)
-#define PM8607_VSYS_MAX                 (0x9F)
-
-#define PM8607_GPADC_MISC2              (0x59)
-#define PM8607_GPADC0_GP_BIAS_A0        (1 << 0)
-#define PM8607_GPADC1_GP_BIAS_A1        (1 << 1)
-#define PM8607_GPADC2_GP_BIAS_A2        (1 << 2)
-#define PM8607_GPADC3_GP_BIAS_A3        (1 << 3)
-#define PM8607_GPADC2_GP_BIAS_OUT2      (1 << 6)
-
 /* RTC Control Registers */
 #define PM8607_RTC1                     (0xA0)
 #define PM8607_RTC_COUNTER1             (0xA1)
@@ -328,22 +263,6 @@ enum {
 #define PM8607_PD_PREBIAS_MASK          (0x1F << 0)
 #define PM8607_PD_PRECHG_MASK           (7 << 5)
 
-#define PM8606_REF_GP_OSC_OFF         0
-#define PM8606_REF_GP_OSC_ON          1
-#define PM8606_REF_GP_OSC_UNKNOWN     2
-
-/* Clients of reference group and 8MHz oscillator in 88PM8606 */
-enum pm8606_ref_gp_and_osc_clients {
-        REF_GP_NO_CLIENTS       = 0,
-        WLED1_DUTY              = (1<<0), /*PF 0x02.7:0*/
-        WLED2_DUTY              = (1<<1), /*PF 0x04.7:0*/
-        WLED3_DUTY              = (1<<2), /*PF 0x06.7:0*/
-        RGB1_ENABLE             = (1<<3), /*PF 0x07.1*/
-        RGB2_ENABLE             = (1<<4), /*PF 0x07.2*/
-        LDO_VBR_EN              = (1<<5), /*PF 0x12.0*/
-        REF_GP_MAX_CLIENT       = 0xFFFF
-};
-
 /* Interrupt Number in 88PM8607 */
 enum {
         PM8607_IRQ_ONKEY,
@@ -378,24 +297,19 @@ enum {
 
 struct pm860x_chip {
         struct device           *dev;
+        struct mutex            io_lock;
         struct mutex            irq_lock;
-        struct mutex            osc_lock;
         struct i2c_client       *client;
         struct i2c_client       *companion;     /* companion chip client */
-        struct regmap           *regmap;
-        struct regmap           *regmap_companion;
 
         int                     buck3_double;   /* DVC ramp slope double */
-        int                     companion_addr;
-        unsigned short          osc_vote;
+        unsigned short          companion_addr;
         int                     id;
         int                     irq_mode;
         int                     irq_base;
         int                     core_irq;
         unsigned char           chip_version;
-        unsigned char           osc_status;
 
-        unsigned int            wakeup_flag;
 };
 
 enum {
@@ -404,12 +318,16 @@ enum {
 };
 
 struct pm860x_backlight_pdata {
+        int             id;
         int             pwm;
         int             iset;
+        unsigned long   flags;
 };
 
 struct pm860x_led_pdata {
+        int             id;
         int             iset;
+        unsigned long   flags;
 };
 
 struct pm860x_rtc_pdata {
@@ -430,8 +348,7 @@ struct pm860x_touch_pdata {
 };
 
 struct pm860x_power_pdata {
-        int             max_capacity;
-        int             resistor;
+        unsigned        fast_charge;    /* charge current */
 };
 
 struct pm860x_platform_data {
@@ -440,35 +357,17 @@ struct pm860x_platform_data {
         struct pm860x_rtc_pdata         *rtc;
         struct pm860x_touch_pdata       *touch;
         struct pm860x_power_pdata       *power;
-        struct regulator_init_data      *buck1;
-        struct regulator_init_data      *buck2;
-        struct regulator_init_data      *buck3;
-        struct regulator_init_data      *ldo1;
-        struct regulator_init_data      *ldo2;
-        struct regulator_init_data      *ldo3;
-        struct regulator_init_data      *ldo4;
-        struct regulator_init_data      *ldo5;
-        struct regulator_init_data      *ldo6;
-        struct regulator_init_data      *ldo7;
-        struct regulator_init_data      *ldo8;
-        struct regulator_init_data      *ldo9;
-        struct regulator_init_data      *ldo10;
-        struct regulator_init_data      *ldo12;
-        struct regulator_init_data      *ldo_vibrator;
-        struct regulator_init_data      *ldo14;
-        struct charger_desc             *chg_desc;
-
-        int             companion_addr; /* I2C address of companion chip */
+        struct regulator_init_data      *regulator;
+
+        unsigned short  companion_addr; /* I2C address of companion chip */
         int             i2c_port;       /* Controlled by GI2C or PI2C */
         int             irq_mode;       /* Clear interrupt by read/write(0/1) */
         int             irq_base;       /* IRQ base number of 88pm860x */
         int             num_leds;
         int             num_backlights;
+        int             num_regulators;
 };
 
-extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short);
-extern int pm8606_osc_disable(struct pm860x_chip *, unsigned short);
-
 extern int pm860x_reg_read(struct i2c_client *, int);
 extern int pm860x_reg_write(struct i2c_client *, int, unsigned char);
 extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *);
@@ -484,4 +383,8 @@ extern int pm860x_page_bulk_write(struct i2c_client *, int, int,
 extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char,
                                 unsigned char);
 
+extern int pm860x_device_init(struct pm860x_chip *chip,
+                              struct pm860x_platform_data *pdata) __devinit ;
+extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ;
+
 #endif /* __LINUX_MFD_88PM860X_H */
diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/ab3100.h
deleted file mode 100644
index afd3080bde2..00000000000
--- a/include/linux/mfd/ab3100.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright (C) 2007-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * AB3100 core access functions
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- *
- */
-
-#include <linux/regulator/machine.h>
-
-struct device;
-
-#ifndef MFD_AB3100_H
-#define MFD_AB3100_H
-
-
-#define AB3100_P1A      0xc0
-#define AB3100_P1B      0xc1
-#define AB3100_P1C      0xc2
-#define AB3100_P1D      0xc3
-#define AB3100_P1E      0xc4
-#define AB3100_P1F      0xc5
-#define AB3100_P1G      0xc6
-#define AB3100_R2A      0xc7
-#define AB3100_R2B      0xc8
-
-/*
- * AB3100, EVENTA1, A2 and A3 event register flags
- * these are catenated into a single 32-bit flag in the code
- * for event notification broadcasts.
- */
-#define AB3100_EVENTA1_ONSWA                            (0x01<<16)
-#define AB3100_EVENTA1_ONSWB                            (0x02<<16)
-#define AB3100_EVENTA1_ONSWC                            (0x04<<16)
-#define AB3100_EVENTA1_DCIO                             (0x08<<16)
-#define AB3100_EVENTA1_OVER_TEMP                        (0x10<<16)
-#define AB3100_EVENTA1_SIM_OFF                          (0x20<<16)
-#define AB3100_EVENTA1_VBUS                             (0x40<<16)
-#define AB3100_EVENTA1_VSET_USB                         (0x80<<16)
-
-#define AB3100_EVENTA2_READY_TX                         (0x01<<8)
-#define AB3100_EVENTA2_READY_RX                         (0x02<<8)
-#define AB3100_EVENTA2_OVERRUN_ERROR                    (0x04<<8)
-#define AB3100_EVENTA2_FRAMING_ERROR                    (0x08<<8)
-#define AB3100_EVENTA2_CHARG_OVERCURRENT                (0x10<<8)
-#define AB3100_EVENTA2_MIDR                             (0x20<<8)
-#define AB3100_EVENTA2_BATTERY_REM                      (0x40<<8)
-#define AB3100_EVENTA2_ALARM                            (0x80<<8)
-
-#define AB3100_EVENTA3_ADC_TRIG5                        (0x01)
-#define AB3100_EVENTA3_ADC_TRIG4                        (0x02)
-#define AB3100_EVENTA3_ADC_TRIG3                        (0x04)
-#define AB3100_EVENTA3_ADC_TRIG2                        (0x08)
-#define AB3100_EVENTA3_ADC_TRIGVBAT                     (0x10)
-#define AB3100_EVENTA3_ADC_TRIGVTX                      (0x20)
-#define AB3100_EVENTA3_ADC_TRIG1                        (0x40)
-#define AB3100_EVENTA3_ADC_TRIG0                        (0x80)
-
-/* AB3100, STR register flags */
-#define AB3100_STR_ONSWA                                (0x01)
-#define AB3100_STR_ONSWB                                (0x02)
-#define AB3100_STR_ONSWC                                (0x04)
-#define AB3100_STR_DCIO                                 (0x08)
-#define AB3100_STR_BOOT_MODE                            (0x10)
-#define AB3100_STR_SIM_OFF                              (0x20)
-#define AB3100_STR_BATT_REMOVAL                         (0x40)
-#define AB3100_STR_VBUS                                 (0x80)
-
-/*
- * AB3100 contains 8 regulators, one external regulator controller
- * and a buck converter, further the LDO E and buck converter can
- * have separate settings if they are in sleep mode, this is
- * modeled as a separate regulator.
- */
-#define AB3100_NUM_REGULATORS                           10
-
-/**
- * struct ab3100
- * @access_mutex: lock out concurrent accesses to the AB3100 registers
- * @dev: pointer to the containing device
- * @i2c_client: I2C client for this chip
- * @testreg_client: secondary client for test registers
- * @chip_name: name of this chip variant
- * @chip_id: 8 bit chip ID for this chip variant
- * @event_subscribers: event subscribers are listed here
- * @startup_events: a copy of the first reading of the event registers
- * @startup_events_read: whether the first events have been read
- *
- * This struct is PRIVATE and devices using it should NOT
- * access ANY fields. It is used as a token for calling the
- * AB3100 functions.
- */
-struct ab3100 {
-        struct mutex access_mutex;
-        struct device *dev;
-        struct i2c_client *i2c_client;
-        struct i2c_client *testreg_client;
-        char chip_name[32];
-        u8 chip_id;
-        struct blocking_notifier_head event_subscribers;
-        u8 startup_events[3];
-        bool startup_events_read;
-};
-
-/**
- * struct ab3100_platform_data
- * Data supplied to initialize board connections to the AB3100
- * @reg_constraints: regulator constraints for target board
- *     the order of these constraints are: LDO A, C, D, E,
- *     F, G, H, K, EXT and BUCK.
- * @reg_initvals: initial values for the regulator registers
- *     plus two sleep settings for LDO E and the BUCK converter.
- *     exactly AB3100_NUM_REGULATORS+2 values must be sent in.
- *     Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
- *     BUCK sleep, LDO D. (LDO D need to be initialized last.)
- * @external_voltage: voltage level of the external regulator.
- */
-struct ab3100_platform_data {
-        struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
-        u8 reg_initvals[AB3100_NUM_REGULATORS+2];
-        int external_voltage;
-};
-
-int ab3100_event_register(struct ab3100 *ab3100,
-                          struct notifier_block *nb);
-int ab3100_event_unregister(struct ab3100 *ab3100,
-                            struct notifier_block *nb);
-
-#endif /*  MFD_AB3100_H */
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 2138bd33021..896b5e47f16 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -1,9 +1,12 @@
 /*
  * Copyright (C) 2007-2009 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
+ * AB3100 core access functions
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
  *
  * ABX500 core access functions.
- * The abx500 interface is used for the Analog Baseband chips.
+ * The abx500 interface is used for the Analog Baseband chip
+ * ab3100, ab3550, ab5500, and ab8500.
  *
  * Author: Mattias Wallin <mattias.wallin@stericsson.com>
  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
@@ -11,278 +14,190 @@
  * Author: Rickard Andersson <rickard.andersson@stericsson.com>
  */
 
+#include <linux/device.h>
 #include <linux/regulator/machine.h>
 
-struct device;
-
 #ifndef MFD_ABX500_H
 #define MFD_ABX500_H
 
-/**
- * struct abx500_init_setting
- * Initial value of the registers for driver to use during setup.
- */
-struct abx500_init_settings {
-        u8 bank;
-        u8 reg;
-        u8 setting;
-};
+#define AB3100_P1A      0xc0
+#define AB3100_P1B      0xc1
+#define AB3100_P1C      0xc2
+#define AB3100_P1D      0xc3
+#define AB3100_P1E      0xc4
+#define AB3100_P1F      0xc5
+#define AB3100_P1G      0xc6
+#define AB3100_R2A      0xc7
+#define AB3100_R2B      0xc8
+#define AB3550_P1A      0x10
+#define AB5500_1_0      0x20
+#define AB5500_2_0      0x21
+#define AB5500_2_1      0x22
+
+/* AB8500 CIDs*/
+#define AB8500_CUTEARLY 0x00
+#define AB8500_CUT1P0   0x10
+#define AB8500_CUT1P1   0x11
+#define AB8500_CUT2P0   0x20
+#define AB8500_CUT3P0   0x30
 
-/* Battery driver related data */
 /*
- * ADC for the battery thermistor.
- * When using the ABx500_ADC_THERM_BATCTRL the battery ID resistor is combined
- * with a NTC resistor to both identify the battery and to measure its
- * temperature. Different phone manufactures uses different techniques to both
- * identify the battery and to read its temperature.
- */
-enum abx500_adc_therm {
-        ABx500_ADC_THERM_BATCTRL,
-        ABx500_ADC_THERM_BATTEMP,
-};
-
-/**
- * struct abx500_res_to_temp - defines one point in a temp to res curve. To
- * be used in battery packs that combines the identification resistor with a
- * NTC resistor.
- * @temp:                       battery pack temperature in Celcius
- * @resist:                     NTC resistor net total resistance
- */
-struct abx500_res_to_temp {
-        int temp;
-        int resist;
-};
-
-/**
- * struct abx500_v_to_cap - Table for translating voltage to capacity
- * @voltage:            Voltage in mV
- * @capacity:           Capacity in percent
+ * AB3100, EVENTA1, A2 and A3 event register flags
+ * these are catenated into a single 32-bit flag in the code
+ * for event notification broadcasts.
  */
-struct abx500_v_to_cap {
-        int voltage;
-        int capacity;
-};
-
-/* Forward declaration */
-struct abx500_fg;
+#define AB3100_EVENTA1_ONSWA                            (0x01<<16)
+#define AB3100_EVENTA1_ONSWB                            (0x02<<16)
+#define AB3100_EVENTA1_ONSWC                            (0x04<<16)
+#define AB3100_EVENTA1_DCIO                             (0x08<<16)
+#define AB3100_EVENTA1_OVER_TEMP                        (0x10<<16)
+#define AB3100_EVENTA1_SIM_OFF                          (0x20<<16)
+#define AB3100_EVENTA1_VBUS                             (0x40<<16)
+#define AB3100_EVENTA1_VSET_USB                         (0x80<<16)
+
+#define AB3100_EVENTA2_READY_TX                         (0x01<<8)
+#define AB3100_EVENTA2_READY_RX                         (0x02<<8)
+#define AB3100_EVENTA2_OVERRUN_ERROR                    (0x04<<8)
+#define AB3100_EVENTA2_FRAMING_ERROR                    (0x08<<8)
+#define AB3100_EVENTA2_CHARG_OVERCURRENT                (0x10<<8)
+#define AB3100_EVENTA2_MIDR                             (0x20<<8)
+#define AB3100_EVENTA2_BATTERY_REM                      (0x40<<8)
+#define AB3100_EVENTA2_ALARM                            (0x80<<8)
+
+#define AB3100_EVENTA3_ADC_TRIG5                        (0x01)
+#define AB3100_EVENTA3_ADC_TRIG4                        (0x02)
+#define AB3100_EVENTA3_ADC_TRIG3                        (0x04)
+#define AB3100_EVENTA3_ADC_TRIG2                        (0x08)
+#define AB3100_EVENTA3_ADC_TRIGVBAT                     (0x10)
+#define AB3100_EVENTA3_ADC_TRIGVTX                      (0x20)
+#define AB3100_EVENTA3_ADC_TRIG1                        (0x40)
+#define AB3100_EVENTA3_ADC_TRIG0                        (0x80)
+
+/* AB3100, STR register flags */
+#define AB3100_STR_ONSWA                                (0x01)
+#define AB3100_STR_ONSWB                                (0x02)
+#define AB3100_STR_ONSWC                                (0x04)
+#define AB3100_STR_DCIO                                 (0x08)
+#define AB3100_STR_BOOT_MODE                            (0x10)
+#define AB3100_STR_SIM_OFF                              (0x20)
+#define AB3100_STR_BATT_REMOVAL                         (0x40)
+#define AB3100_STR_VBUS                                 (0x80)
 
-/**
- * struct abx500_fg_parameters - Fuel gauge algorithm parameters, in seconds
- * if not specified
- * @recovery_sleep_timer:       Time between measurements while recovering
- * @recovery_total_time:        Total recovery time
- * @init_timer:                 Measurement interval during startup
- * @init_discard_time:          Time we discard voltage measurement at startup
- * @init_total_time:            Total init time during startup
- * @high_curr_time:             Time current has to be high to go to recovery
- * @accu_charging:              FG accumulation time while charging
- * @accu_high_curr:             FG accumulation time in high current mode
- * @high_curr_threshold:        High current threshold, in mA
- * @lowbat_threshold:           Low battery threshold, in mV
- * @overbat_threshold:          Over battery threshold, in mV
- * @battok_falling_th_sel0      Threshold in mV for battOk signal sel0
- *                              Resolution in 50 mV step.
- * @battok_raising_th_sel1      Threshold in mV for battOk signal sel1
- *                              Resolution in 50 mV step.
- * @user_cap_limit              Capacity reported from user must be within this
- *                              limit to be considered as sane, in percentage
- *                              points.
- * @maint_thres                 This is the threshold where we stop reporting
- *                              battery full while in maintenance, in per cent
+/*
+ * AB3100 contains 8 regulators, one external regulator controller
+ * and a buck converter, further the LDO E and buck converter can
+ * have separate settings if they are in sleep mode, this is
+ * modeled as a separate regulator.
  */
-struct abx500_fg_parameters {
-        int recovery_sleep_timer;
-        int recovery_total_time;
-        int init_timer;
-        int init_discard_time;
-        int init_total_time;
-        int high_curr_time;
-        int accu_charging;
-        int accu_high_curr;
-        int high_curr_threshold;
-        int lowbat_threshold;
-        int overbat_threshold;
-        int battok_falling_th_sel0;
-        int battok_raising_th_sel1;
-        int user_cap_limit;
-        int maint_thres;
-};
+#define AB3100_NUM_REGULATORS                           10
 
 /**
- * struct abx500_charger_maximization - struct used by the board config.
- * @use_maxi:           Enable maximization for this battery type
- * @maxi_chg_curr:      Maximum charger current allowed
- * @maxi_wait_cycles:   cycles to wait before setting charger current
- * @charger_curr_step   delta between two charger current settings (mA)
+ * struct ab3100
+ * @access_mutex: lock out concurrent accesses to the AB3100 registers
+ * @dev: pointer to the containing device
+ * @i2c_client: I2C client for this chip
+ * @testreg_client: secondary client for test registers
+ * @chip_name: name of this chip variant
+ * @chip_id: 8 bit chip ID for this chip variant
+ * @event_subscribers: event subscribers are listed here
+ * @startup_events: a copy of the first reading of the event registers
+ * @startup_events_read: whether the first events have been read
+ *
+ * This struct is PRIVATE and devices using it should NOT
+ * access ANY fields. It is used as a token for calling the
+ * AB3100 functions.
  */
-struct abx500_maxim_parameters {
-        bool ena_maxi;
-        int chg_curr;
-        int wait_cycles;
-        int charger_curr_step;
+struct ab3100 {
+        struct mutex access_mutex;
+        struct device *dev;
+        struct i2c_client *i2c_client;
+        struct i2c_client *testreg_client;
+        char chip_name[32];
+        u8 chip_id;
+        struct blocking_notifier_head event_subscribers;
+        u8 startup_events[3];
+        bool startup_events_read;
 };
 
 /**
- * struct abx500_battery_type - different batteries supported
- * @name:                       battery technology
- * @resis_high:                 battery upper resistance limit
- * @resis_low:                  battery lower resistance limit
- * @charge_full_design:         Maximum battery capacity in mAh
- * @nominal_voltage:            Nominal voltage of the battery in mV
- * @termination_vol:            max voltage upto which battery can be charged
- * @termination_curr            battery charging termination current in mA
- * @recharge_vol                battery voltage limit that will trigger a new
- *                              full charging cycle in the case where maintenan-
- *                              -ce charging has been disabled
- * @normal_cur_lvl:             charger current in normal state in mA
- * @normal_vol_lvl:             charger voltage in normal state in mV
- * @maint_a_cur_lvl:            charger current in maintenance A state in mA
- * @maint_a_vol_lvl:            charger voltage in maintenance A state in mV
- * @maint_a_chg_timer_h:        charge time in maintenance A state
- * @maint_b_cur_lvl:            charger current in maintenance B state in mA
- * @maint_b_vol_lvl:            charger voltage in maintenance B state in mV
- * @maint_b_chg_timer_h:        charge time in maintenance B state
- * @low_high_cur_lvl:           charger current in temp low/high state in mA
- * @low_high_vol_lvl:           charger voltage in temp low/high state in mV'
- * @battery_resistance:         battery inner resistance in mOhm.
- * @n_r_t_tbl_elements:         number of elements in r_to_t_tbl
- * @r_to_t_tbl:                 table containing resistance to temp points
- * @n_v_cap_tbl_elements:       number of elements in v_to_cap_tbl
- * @v_to_cap_tbl:               Voltage to capacity (in %) table
- * @n_batres_tbl_elements       number of elements in the batres_tbl
- * @batres_tbl                  battery internal resistance vs temperature table
+ * struct ab3100_platform_data
+ * Data supplied to initialize board connections to the AB3100
+ * @reg_constraints: regulator constraints for target board
+ *     the order of these constraints are: LDO A, C, D, E,
+ *     F, G, H, K, EXT and BUCK.
+ * @reg_initvals: initial values for the regulator registers
+ *     plus two sleep settings for LDO E and the BUCK converter.
+ *     exactly AB3100_NUM_REGULATORS+2 values must be sent in.
+ *     Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
+ *     BUCK sleep, LDO D. (LDO D need to be initialized last.)
+ * @external_voltage: voltage level of the external regulator.
  */
-struct abx500_battery_type {
-        int name;
-        int resis_high;
-        int resis_low;
-        int charge_full_design;
-        int nominal_voltage;
-        int termination_vol;
-        int termination_curr;
-        int recharge_vol;
-        int normal_cur_lvl;
-        int normal_vol_lvl;
-        int maint_a_cur_lvl;
-        int maint_a_vol_lvl;
-        int maint_a_chg_timer_h;
-        int maint_b_cur_lvl;
-        int maint_b_vol_lvl;
-        int maint_b_chg_timer_h;
-        int low_high_cur_lvl;
-        int low_high_vol_lvl;
-        int battery_resistance;
-        int n_temp_tbl_elements;
-        struct abx500_res_to_temp *r_to_t_tbl;
-        int n_v_cap_tbl_elements;
-        struct abx500_v_to_cap *v_to_cap_tbl;
-        int n_batres_tbl_elements;
-        struct batres_vs_temp *batres_tbl;
+struct ab3100_platform_data {
+        struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
+        u8 reg_initvals[AB3100_NUM_REGULATORS+2];
+        int external_voltage;
 };
 
-/**
- * struct abx500_bm_capacity_levels - abx500 capacity level data
- * @critical:           critical capacity level in percent
- * @low:                low capacity level in percent
- * @normal:             normal capacity level in percent
- * @high:               high capacity level in percent
- * @full:               full capacity level in percent
- */
-struct abx500_bm_capacity_levels {
-        int critical;
-        int low;
-        int normal;
-        int high;
-        int full;
+int ab3100_event_register(struct ab3100 *ab3100,
+                          struct notifier_block *nb);
+int ab3100_event_unregister(struct ab3100 *ab3100,
+                            struct notifier_block *nb);
+
+/* AB3550, STR register flags */
+#define AB3550_STR_ONSWA                                (0x01)
+#define AB3550_STR_ONSWB                                (0x02)
+#define AB3550_STR_ONSWC                                (0x04)
+#define AB3550_STR_DCIO                                 (0x08)
+#define AB3550_STR_BOOT_MODE                            (0x10)
+#define AB3550_STR_SIM_OFF                              (0x20)
+#define AB3550_STR_BATT_REMOVAL                         (0x40)
+#define AB3550_STR_VBUS                                 (0x80)
+
+/* Interrupt mask registers */
+#define AB3550_IMR1 0x29
+#define AB3550_IMR2 0x2a
+#define AB3550_IMR3 0x2b
+#define AB3550_IMR4 0x2c
+#define AB3550_IMR5 0x2d
+
+enum ab3550_devid {
+        AB3550_DEVID_ADC,
+        AB3550_DEVID_DAC,
+        AB3550_DEVID_LEDS,
+        AB3550_DEVID_POWER,
+        AB3550_DEVID_REGULATORS,
+        AB3550_DEVID_SIM,
+        AB3550_DEVID_UART,
+        AB3550_DEVID_RTC,
+        AB3550_DEVID_CHARGER,
+        AB3550_DEVID_FUELGAUGE,
+        AB3550_DEVID_VIBRATOR,
+        AB3550_DEVID_CODEC,
+        AB3550_NUM_DEVICES,
 };
 
 /**
- * struct abx500_bm_charger_parameters - Charger specific parameters
- * @usb_volt_max:       maximum allowed USB charger voltage in mV
- * @usb_curr_max:       maximum allowed USB charger current in mA
- * @ac_volt_max:        maximum allowed AC charger voltage in mV
- * @ac_curr_max:        maximum allowed AC charger current in mA
+ * struct abx500_init_setting
+ * Initial value of the registers for driver to use during setup.
  */
-struct abx500_bm_charger_parameters {
-        int usb_volt_max;
-        int usb_curr_max;
-        int ac_volt_max;
-        int ac_curr_max;
+struct abx500_init_settings {
+        u8 bank;
+        u8 reg;
+        u8 setting;
 };
 
 /**
- * struct abx500_bm_data - abx500 battery management data
- * @temp_under          under this temp, charging is stopped
- * @temp_low            between this temp and temp_under charging is reduced
- * @temp_high           between this temp and temp_over charging is reduced
- * @temp_over           over this temp, charging is stopped
- * @temp_now            present battery temperature
- * @temp_interval_chg   temperature measurement interval in s when charging
- * @temp_interval_nochg temperature measurement interval in s when not charging
- * @main_safety_tmr_h   safety timer for main charger
- * @usb_safety_tmr_h    safety timer for usb charger
- * @bkup_bat_v          voltage which we charge the backup battery with
- * @bkup_bat_i          current which we charge the backup battery with
- * @no_maintenance      indicates that maintenance charging is disabled
- * @abx500_adc_therm    placement of thermistor, batctrl or battemp adc
- * @chg_unknown_bat     flag to enable charging of unknown batteries
- * @enable_overshoot    flag to enable VBAT overshoot control
- * @auto_trig           flag to enable auto adc trigger
- * @fg_res              resistance of FG resistor in 0.1mOhm
- * @n_btypes            number of elements in array bat_type
- * @batt_id             index of the identified battery in array bat_type
- * @interval_charging   charge alg cycle period time when charging (sec)
- * @interval_not_charging charge alg cycle period time when not charging (sec)
- * @temp_hysteresis     temperature hysteresis
- * @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
- * @maxi:               maximization parameters
- * @cap_levels          capacity in percent for the different capacity levels
- * @bat_type            table of supported battery types
- * @chg_params          charger parameters
- * @fg_params           fuel gauge parameters
+ * struct ab3550_platform_data
+ * Data supplied to initialize board connections to the AB3550
  */
-struct abx500_bm_data {
-        int temp_under;
-        int temp_low;
-        int temp_high;
-        int temp_over;
-        int temp_now;
-        int temp_interval_chg;
-        int temp_interval_nochg;
-        int main_safety_tmr_h;
-        int usb_safety_tmr_h;
-        int bkup_bat_v;
-        int bkup_bat_i;
-        bool no_maintenance;
-        bool chg_unknown_bat;
-        bool enable_overshoot;
-        bool auto_trig;
-        enum abx500_adc_therm adc_therm;
-        int fg_res;
-        int n_btypes;
-        int batt_id;
-        int interval_charging;
-        int interval_not_charging;
-        int temp_hysteresis;
-        int gnd_lift_resistance;
-        const struct abx500_maxim_parameters *maxi;
-        const struct abx500_bm_capacity_levels *cap_levels;
-        struct abx500_battery_type *bat_type;
-        const struct abx500_bm_charger_parameters *chg_params;
-        const struct abx500_fg_parameters *fg_params;
+struct ab3550_platform_data {
+        struct {unsigned int base; unsigned int count; } irq;
+        void *dev_data[AB3550_NUM_DEVICES];
+        size_t dev_data_sz[AB3550_NUM_DEVICES];
+        struct abx500_init_settings *init_settings;
+        unsigned int init_settings_sz;
 };
 
-extern struct abx500_bm_data ab8500_bm_data;
-
-enum {
-        NTC_EXTERNAL = 0,
-        NTC_INTERNAL,
-};
-
-int bmdevs_of_probe(struct device *dev,
-                struct device_node *np,
-                struct abx500_bm_data **battery);
-
 int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
         u8 value);
 int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
diff --git a/include/linux/mfd/abx500/ab8500-bm.h b/include/linux/mfd/abx500/ab8500-bm.h
deleted file mode 100644
index 44310c98ee6..00000000000
--- a/include/linux/mfd/abx500/ab8500-bm.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
- * Copyright ST-Ericsson 2012.
- *
- * Author: Arun Murthy <arun.murthy@stericsson.com>
- * Licensed under GPLv2.
- */
-
-#ifndef _AB8500_BM_H
-#define _AB8500_BM_H
-
-#include <linux/kernel.h>
-#include <linux/mfd/abx500.h>
-
-/*
- * System control 2 register offsets.
- * bank = 0x02
- */
-#define AB8500_MAIN_WDOG_CTRL_REG       0x01
-#define AB8500_LOW_BAT_REG              0x03
-#define AB8500_BATT_OK_REG              0x04
-/*
- * USB/ULPI register offsets
- * Bank : 0x5
- */
-#define AB8500_USB_LINE_STAT_REG        0x80
-
-/*
- * Charger / status register offfsets
- * Bank : 0x0B
- */
-#define AB8500_CH_STATUS1_REG           0x00
-#define AB8500_CH_STATUS2_REG           0x01
-#define AB8500_CH_USBCH_STAT1_REG       0x02
-#define AB8500_CH_USBCH_STAT2_REG       0x03
-#define AB8500_CH_FSM_STAT_REG          0x04
-#define AB8500_CH_STAT_REG              0x05
-
-/*
- * Charger / control register offfsets
- * Bank : 0x0B
- */
-#define AB8500_CH_VOLT_LVL_REG          0x40
-#define AB8500_CH_VOLT_LVL_MAX_REG      0x41  /*Only in Cut2.0*/
-#define AB8500_CH_OPT_CRNTLVL_REG       0x42
-#define AB8500_CH_OPT_CRNTLVL_MAX_REG   0x43  /*Only in Cut2.0*/
-#define AB8500_CH_WD_TIMER_REG          0x50
-#define AB8500_CHARG_WD_CTRL            0x51
-#define AB8500_BTEMP_HIGH_TH            0x52
-#define AB8500_LED_INDICATOR_PWM_CTRL   0x53
-#define AB8500_LED_INDICATOR_PWM_DUTY   0x54
-#define AB8500_BATT_OVV                 0x55
-#define AB8500_CHARGER_CTRL             0x56
-#define AB8500_BAT_CTRL_CURRENT_SOURCE  0x60  /*Only in Cut2.0*/
-
-/*
- * Charger / main control register offsets
- * Bank : 0x0B
- */
-#define AB8500_MCH_CTRL1                0x80
-#define AB8500_MCH_CTRL2                0x81
-#define AB8500_MCH_IPT_CURLVL_REG       0x82
-#define AB8500_CH_WD_REG                0x83
-
-/*
- * Charger / USB control register offsets
- * Bank : 0x0B
- */
-#define AB8500_USBCH_CTRL1_REG          0xC0
-#define AB8500_USBCH_CTRL2_REG          0xC1
-#define AB8500_USBCH_IPT_CRNTLVL_REG    0xC2
-
-/*
- * Gas Gauge register offsets
- * Bank : 0x0C
- */
-#define AB8500_GASG_CC_CTRL_REG         0x00
-#define AB8500_GASG_CC_ACCU1_REG        0x01
-#define AB8500_GASG_CC_ACCU2_REG        0x02
-#define AB8500_GASG_CC_ACCU3_REG        0x03
-#define AB8500_GASG_CC_ACCU4_REG        0x04
-#define AB8500_GASG_CC_SMPL_CNTRL_REG   0x05
-#define AB8500_GASG_CC_SMPL_CNTRH_REG   0x06
-#define AB8500_GASG_CC_SMPL_CNVL_REG    0x07
-#define AB8500_GASG_CC_SMPL_CNVH_REG    0x08
-#define AB8500_GASG_CC_CNTR_AVGOFF_REG  0x09
-#define AB8500_GASG_CC_OFFSET_REG       0x0A
-#define AB8500_GASG_CC_NCOV_ACCU        0x10
-#define AB8500_GASG_CC_NCOV_ACCU_CTRL   0x11
-#define AB8500_GASG_CC_NCOV_ACCU_LOW    0x12
-#define AB8500_GASG_CC_NCOV_ACCU_MED    0x13
-#define AB8500_GASG_CC_NCOV_ACCU_HIGH   0x14
-
-/*
- * Interrupt register offsets
- * Bank : 0x0E
- */
-#define AB8500_IT_SOURCE2_REG           0x01
-#define AB8500_IT_SOURCE21_REG          0x14
-
-/*
- * RTC register offsets
- * Bank: 0x0F
- */
-#define AB8500_RTC_BACKUP_CHG_REG       0x0C
-#define AB8500_RTC_CC_CONF_REG          0x01
-#define AB8500_RTC_CTRL_REG             0x0B
-
-/*
- * OTP register offsets
- * Bank : 0x15
- */
-#define AB8500_OTP_CONF_15              0x0E
-
-/* GPADC constants from AB8500 spec, UM0836 */
-#define ADC_RESOLUTION                  1024
-#define ADC_CH_MAIN_MIN                 0
-#define ADC_CH_MAIN_MAX                 20030
-#define ADC_CH_VBUS_MIN                 0
-#define ADC_CH_VBUS_MAX                 20030
-#define ADC_CH_VBAT_MIN                 2300
-#define ADC_CH_VBAT_MAX                 4800
-#define ADC_CH_BKBAT_MIN                0
-#define ADC_CH_BKBAT_MAX                3200
-
-/* Main charge i/p current */
-#define MAIN_CH_IP_CUR_0P9A             0x80
-#define MAIN_CH_IP_CUR_1P0A             0x90
-#define MAIN_CH_IP_CUR_1P1A             0xA0
-#define MAIN_CH_IP_CUR_1P2A             0xB0
-#define MAIN_CH_IP_CUR_1P3A             0xC0
-#define MAIN_CH_IP_CUR_1P4A             0xD0
-#define MAIN_CH_IP_CUR_1P5A             0xE0
-
-/* ChVoltLevel */
-#define CH_VOL_LVL_3P5                  0x00
-#define CH_VOL_LVL_4P0                  0x14
-#define CH_VOL_LVL_4P05                 0x16
-#define CH_VOL_LVL_4P1                  0x1B
-#define CH_VOL_LVL_4P15                 0x20
-#define CH_VOL_LVL_4P2                  0x25
-#define CH_VOL_LVL_4P6                  0x4D
-
-/* ChOutputCurrentLevel */
-#define CH_OP_CUR_LVL_0P1               0x00
-#define CH_OP_CUR_LVL_0P2               0x01
-#define CH_OP_CUR_LVL_0P3               0x02
-#define CH_OP_CUR_LVL_0P4               0x03
-#define CH_OP_CUR_LVL_0P5               0x04
-#define CH_OP_CUR_LVL_0P6               0x05
-#define CH_OP_CUR_LVL_0P7               0x06
-#define CH_OP_CUR_LVL_0P8               0x07
-#define CH_OP_CUR_LVL_0P9               0x08
-#define CH_OP_CUR_LVL_1P4               0x0D
-#define CH_OP_CUR_LVL_1P5               0x0E
-#define CH_OP_CUR_LVL_1P6               0x0F
-
-/* BTEMP High thermal limits */
-#define BTEMP_HIGH_TH_57_0              0x00
-#define BTEMP_HIGH_TH_52                0x01
-#define BTEMP_HIGH_TH_57_1              0x02
-#define BTEMP_HIGH_TH_62                0x03
-
-/* current is mA */
-#define USB_0P1A                        100
-#define USB_0P2A                        200
-#define USB_0P3A                        300
-#define USB_0P4A                        400
-#define USB_0P5A                        500
-
-#define LOW_BAT_3P1V                    0x20
-#define LOW_BAT_2P3V                    0x00
-#define LOW_BAT_RESET                   0x01
-#define LOW_BAT_ENABLE                  0x01
-
-/* Backup battery constants */
-#define BUP_ICH_SEL_50UA                0x00
-#define BUP_ICH_SEL_150UA               0x04
-#define BUP_ICH_SEL_300UA               0x08
-#define BUP_ICH_SEL_700UA               0x0C
-
-#define BUP_VCH_SEL_2P5V                0x00
-#define BUP_VCH_SEL_2P6V                0x01
-#define BUP_VCH_SEL_2P8V                0x02
-#define BUP_VCH_SEL_3P1V                0x03
-
-/* Battery OVV constants */
-#define BATT_OVV_ENA                    0x02
-#define BATT_OVV_TH_3P7                 0x00
-#define BATT_OVV_TH_4P75                0x01
-
-/* A value to indicate over voltage */
-#define BATT_OVV_VALUE                  4750
-
-/* VBUS OVV constants */
-#define VBUS_OVV_SELECT_MASK            0x78
-#define VBUS_OVV_SELECT_5P6V            0x00
-#define VBUS_OVV_SELECT_5P7V            0x08
-#define VBUS_OVV_SELECT_5P8V            0x10
-#define VBUS_OVV_SELECT_5P9V            0x18
-#define VBUS_OVV_SELECT_6P0V            0x20
-#define VBUS_OVV_SELECT_6P1V            0x28
-#define VBUS_OVV_SELECT_6P2V            0x30
-#define VBUS_OVV_SELECT_6P3V            0x38
-
-#define VBUS_AUTO_IN_CURR_LIM_ENA       0x04
-
-/* Fuel Gauge constants */
-#define RESET_ACCU                      0x02
-#define READ_REQ                        0x01
-#define CC_DEEP_SLEEP_ENA               0x02
-#define CC_PWR_UP_ENA                   0x01
-#define CC_SAMPLES_40                   0x28
-#define RD_NCONV_ACCU_REQ               0x01
-#define CC_CALIB                        0x08
-#define CC_INTAVGOFFSET_ENA             0x10
-#define CC_MUXOFFSET                    0x80
-#define CC_INT_CAL_N_AVG_MASK           0x60
-#define CC_INT_CAL_SAMPLES_16           0x40
-#define CC_INT_CAL_SAMPLES_8            0x20
-#define CC_INT_CAL_SAMPLES_4            0x00
-
-/* RTC constants */
-#define RTC_BUP_CH_ENA                  0x10
-
-/* BatCtrl Current Source Constants */
-#define BAT_CTRL_7U_ENA                 0x01
-#define BAT_CTRL_20U_ENA                0x02
-#define BAT_CTRL_CMP_ENA                0x04
-#define FORCE_BAT_CTRL_CMP_HIGH         0x08
-#define BAT_CTRL_PULL_UP_ENA            0x10
-
-/* Battery type */
-#define BATTERY_UNKNOWN                 00
-
-/**
- * struct res_to_temp - defines one point in a temp to res curve. To
- * be used in battery packs that combines the identification resistor with a
- * NTC resistor.
- * @temp:                       battery pack temperature in Celcius
- * @resist:                     NTC resistor net total resistance
- */
-struct res_to_temp {
-        int temp;
-        int resist;
-};
-
-/**
- * struct batres_vs_temp - defines one point in a temp vs battery internal
- * resistance curve.
- * @temp:                       battery pack temperature in Celcius
- * @resist:                     battery internal reistance in mOhm
- */
-struct batres_vs_temp {
-        int temp;
-        int resist;
-};
-
-/* Forward declaration */
-struct ab8500_fg;
-
-/**
- * struct ab8500_fg_parameters - Fuel gauge algorithm parameters, in seconds
- * if not specified
- * @recovery_sleep_timer:       Time between measurements while recovering
- * @recovery_total_time:        Total recovery time
- * @init_timer:                 Measurement interval during startup
- * @init_discard_time:          Time we discard voltage measurement at startup
- * @init_total_time:            Total init time during startup
- * @high_curr_time:             Time current has to be high to go to recovery
- * @accu_charging:              FG accumulation time while charging
- * @accu_high_curr:             FG accumulation time in high current mode
- * @high_curr_threshold:        High current threshold, in mA
- * @lowbat_threshold:           Low battery threshold, in mV
- * @battok_falling_th_sel0      Threshold in mV for battOk signal sel0
- *                              Resolution in 50 mV step.
- * @battok_raising_th_sel1      Threshold in mV for battOk signal sel1
- *                              Resolution in 50 mV step.
- * @user_cap_limit              Capacity reported from user must be within this
- *                              limit to be considered as sane, in percentage
- *                              points.
- * @maint_thres                 This is the threshold where we stop reporting
- *                              battery full while in maintenance, in per cent
- */
-struct ab8500_fg_parameters {
-        int recovery_sleep_timer;
-        int recovery_total_time;
-        int init_timer;
-        int init_discard_time;
-        int init_total_time;
-        int high_curr_time;
-        int accu_charging;
-        int accu_high_curr;
-        int high_curr_threshold;
-        int lowbat_threshold;
-        int battok_falling_th_sel0;
-        int battok_raising_th_sel1;
-        int user_cap_limit;
-        int maint_thres;
-};
-
-/**
- * struct ab8500_charger_maximization - struct used by the board config.
- * @use_maxi:           Enable maximization for this battery type
- * @maxi_chg_curr:      Maximum charger current allowed
- * @maxi_wait_cycles:   cycles to wait before setting charger current
- * @charger_curr_step   delta between two charger current settings (mA)
- */
-struct ab8500_maxim_parameters {
-        bool ena_maxi;
-        int chg_curr;
-        int wait_cycles;
-        int charger_curr_step;
-};
-
-/**
- * struct ab8500_bm_capacity_levels - ab8500 capacity level data
- * @critical:           critical capacity level in percent
- * @low:                low capacity level in percent
- * @normal:             normal capacity level in percent
- * @high:               high capacity level in percent
- * @full:               full capacity level in percent
- */
-struct ab8500_bm_capacity_levels {
-        int critical;
-        int low;
-        int normal;
-        int high;
-        int full;
-};
-
-/**
- * struct ab8500_bm_charger_parameters - Charger specific parameters
- * @usb_volt_max:       maximum allowed USB charger voltage in mV
- * @usb_curr_max:       maximum allowed USB charger current in mA
- * @ac_volt_max:        maximum allowed AC charger voltage in mV
- * @ac_curr_max:        maximum allowed AC charger current in mA
- */
-struct ab8500_bm_charger_parameters {
-        int usb_volt_max;
-        int usb_curr_max;
-        int ac_volt_max;
-        int ac_curr_max;
-};
-
-/**
- * struct ab8500_bm_data - ab8500 battery management data
- * @temp_under          under this temp, charging is stopped
- * @temp_low            between this temp and temp_under charging is reduced
- * @temp_high           between this temp and temp_over charging is reduced
- * @temp_over           over this temp, charging is stopped
- * @temp_interval_chg   temperature measurement interval in s when charging
- * @temp_interval_nochg temperature measurement interval in s when not charging
- * @main_safety_tmr_h   safety timer for main charger
- * @usb_safety_tmr_h    safety timer for usb charger
- * @bkup_bat_v          voltage which we charge the backup battery with
- * @bkup_bat_i          current which we charge the backup battery with
- * @no_maintenance      indicates that maintenance charging is disabled
- * @adc_therm           placement of thermistor, batctrl or battemp adc
- * @chg_unknown_bat     flag to enable charging of unknown batteries
- * @enable_overshoot    flag to enable VBAT overshoot control
- * @fg_res              resistance of FG resistor in 0.1mOhm
- * @n_btypes            number of elements in array bat_type
- * @batt_id             index of the identified battery in array bat_type
- * @interval_charging   charge alg cycle period time when charging (sec)
- * @interval_not_charging charge alg cycle period time when not charging (sec)
- * @temp_hysteresis     temperature hysteresis
- * @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
- * @maxi:               maximization parameters
- * @cap_levels          capacity in percent for the different capacity levels
- * @bat_type            table of supported battery types
- * @chg_params          charger parameters
- * @fg_params           fuel gauge parameters
- */
-struct ab8500_bm_data {
-        int temp_under;
-        int temp_low;
-        int temp_high;
-        int temp_over;
-        int temp_interval_chg;
-        int temp_interval_nochg;
-        int main_safety_tmr_h;
-        int usb_safety_tmr_h;
-        int bkup_bat_v;
-        int bkup_bat_i;
-        bool no_maintenance;
-        bool chg_unknown_bat;
-        bool enable_overshoot;
-        enum abx500_adc_therm adc_therm;
-        int fg_res;
-        int n_btypes;
-        int batt_id;
-        int interval_charging;
-        int interval_not_charging;
-        int temp_hysteresis;
-        int gnd_lift_resistance;
-        const struct ab8500_maxim_parameters *maxi;
-        const struct ab8500_bm_capacity_levels *cap_levels;
-        const struct ab8500_bm_charger_parameters *chg_params;
-        const struct ab8500_fg_parameters *fg_params;
-};
-
-struct ab8500_charger_platform_data {
-        char **supplied_to;
-        size_t num_supplicants;
-        bool autopower_cfg;
-};
-
-struct ab8500_btemp_platform_data {
-        char **supplied_to;
-        size_t num_supplicants;
-};
-
-struct ab8500_fg_platform_data {
-        char **supplied_to;
-        size_t num_supplicants;
-};
-
-struct ab8500_chargalg_platform_data {
-        char **supplied_to;
-        size_t num_supplicants;
-};
-struct ab8500_btemp;
-struct ab8500_gpadc;
-struct ab8500_fg;
-#ifdef CONFIG_AB8500_BM
-void ab8500_fg_reinit(void);
-void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA);
-struct ab8500_btemp *ab8500_btemp_get(void);
-int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp);
-struct ab8500_fg *ab8500_fg_get(void);
-int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev);
-int ab8500_fg_inst_curr_start(struct ab8500_fg *di);
-int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res);
-int ab8500_fg_inst_curr_done(struct ab8500_fg *di);
-
-#else
-int ab8500_fg_inst_curr_done(struct ab8500_fg *di)
-{
-}
-static void ab8500_fg_reinit(void)
-{
-}
-static void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA)
-{
-}
-static struct ab8500_btemp *ab8500_btemp_get(void)
-{
-        return NULL;
-}
-static int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp)
-{
-        return 0;
-}
-struct ab8500_fg *ab8500_fg_get(void)
-{
-        return NULL;
-}
-static int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev)
-{
-        return -ENODEV;
-}
-
-static inline int ab8500_fg_inst_curr_start(struct ab8500_fg *di)
-{
-        return -ENODEV;
-}
-
-static inline int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res)
-{
-        return -ENODEV;
-}
-
-#endif
-#endif /* _AB8500_BM_H */
diff --git a/include/linux/mfd/abx500/ab8500-codec.h b/include/linux/mfd/abx500/ab8500-codec.h
deleted file mode 100644
index d7079413def..00000000000
--- a/include/linux/mfd/abx500/ab8500-codec.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2012
- *
- * Author: Ola Lilja <ola.o.lilja@stericsson.com>
- *         for ST-Ericsson.
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef AB8500_CORE_CODEC_H
-#define AB8500_CORE_CODEC_H
-
-/* Mic-types */
-enum amic_type {
-        AMIC_TYPE_SINGLE_ENDED,
-        AMIC_TYPE_DIFFERENTIAL
-};
-
-/* Mic-biases */
-enum amic_micbias {
-        AMIC_MICBIAS_VAMIC1,
-        AMIC_MICBIAS_VAMIC2,
-        AMIC_MICBIAS_UNKNOWN
-};
-
-/* Bias-voltage */
-enum ear_cm_voltage {
-        EAR_CMV_0_95V,
-        EAR_CMV_1_10V,
-        EAR_CMV_1_27V,
-        EAR_CMV_1_58V,
-        EAR_CMV_UNKNOWN
-};
-
-/* Analog microphone settings */
-struct amic_settings {
-        enum amic_type mic1_type;
-        enum amic_type mic2_type;
-        enum amic_micbias mic1a_micbias;
-        enum amic_micbias mic1b_micbias;
-        enum amic_micbias mic2_micbias;
-};
-
-/* Platform data structure for the audio-parts of the AB8500 */
-struct ab8500_codec_platform_data {
-        struct amic_settings amics;
-        enum ear_cm_voltage ear_cmv;
-};
-
-#endif
diff --git a/include/linux/mfd/abx500/ab8500-gpadc.h b/include/linux/mfd/abx500/ab8500-gpadc.h
deleted file mode 100644
index 252966769d9..00000000000
--- a/include/linux/mfd/abx500/ab8500-gpadc.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2010 ST-Ericsson SA
- * Licensed under GPLv2.
- *
- * Author: Arun R Murthy <arun.murthy@stericsson.com>
- * Author: Daniel Willerud <daniel.willerud@stericsson.com>
- */
-
-#ifndef _AB8500_GPADC_H
-#define _AB8500_GPADC_H
-
-/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2) */
-#define BAT_CTRL        0x01
-#define BTEMP_BALL      0x02
-#define MAIN_CHARGER_V  0x03
-#define ACC_DETECT1     0x04
-#define ACC_DETECT2     0x05
-#define ADC_AUX1        0x06
-#define ADC_AUX2        0x07
-#define MAIN_BAT_V      0x08
-#define VBUS_V          0x09
-#define MAIN_CHARGER_C  0x0A
-#define USB_CHARGER_C   0x0B
-#define BK_BAT_V        0x0C
-#define DIE_TEMP        0x0D
-
-struct ab8500_gpadc;
-
-struct ab8500_gpadc *ab8500_gpadc_get(char *name);
-int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel);
-int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel);
-int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
-    u8 channel, int ad_value);
-
-#endif /* _AB8500_GPADC_H */
diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h
deleted file mode 100644
index 2387c207ea8..00000000000
--- a/include/linux/mfd/abx500/ab8500-gpio.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright ST-Ericsson 2010.
- *
- * Author: Bibek Basu <bibek.basu@stericsson.com>
- * Licensed under GPLv2.
- */
-
-#ifndef _AB8500_GPIO_H
-#define _AB8500_GPIO_H
-
-/*
- * Platform data to register a block: only the initial gpio/irq number.
- * Array sizes are large enough to contain all AB8500 and AB9540 GPIO
- * registers.
- */
-
-struct ab8500_gpio_platform_data {
-        int gpio_base;
-        u32 irq_base;
-        u8  config_reg[8];
-};
-
-#endif /* _AB8500_GPIO_H */
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
deleted file mode 100644
index 10eb50973c3..00000000000
--- a/include/linux/mfd/abx500/ab8500-sysctrl.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
- * License terms: GNU General Public License (GPL) version 2
- */
-#ifndef __AB8500_SYSCTRL_H
-#define __AB8500_SYSCTRL_H
-
-#include <linux/bitops.h>
-
-#ifdef CONFIG_AB8500_CORE
-
-int ab8500_sysctrl_read(u16 reg, u8 *value);
-int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
-
-#else
-
-static inline int ab8500_sysctrl_read(u16 reg, u8 *value)
-{
-        return 0;
-}
-
-static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
-{
-        return 0;
-}
-
-#endif /* CONFIG_AB8500_CORE */
-
-static inline int ab8500_sysctrl_set(u16 reg, u8 bits)
-{
-        return ab8500_sysctrl_write(reg, bits, bits);
-}
-
-static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
-{
-        return ab8500_sysctrl_write(reg, bits, 0);
-}
-
-/* Registers */
-#define AB8500_TURNONSTATUS             0x100
-#define AB8500_RESETSTATUS              0x101
-#define AB8500_PONKEY1PRESSSTATUS       0x102
-#define AB8500_SYSCLKREQSTATUS          0x142
-#define AB8500_STW4500CTRL1             0x180
-#define AB8500_STW4500CTRL2             0x181
-#define AB8500_STW4500CTRL3             0x200
-#define AB8500_MAINWDOGCTRL             0x201
-#define AB8500_MAINWDOGTIMER            0x202
-#define AB8500_LOWBAT                   0x203
-#define AB8500_BATTOK                   0x204
-#define AB8500_SYSCLKTIMER              0x205
-#define AB8500_SMPSCLKCTRL              0x206
-#define AB8500_SMPSCLKSEL1              0x207
-#define AB8500_SMPSCLKSEL2              0x208
-#define AB8500_SMPSCLKSEL3              0x209
-#define AB8500_SYSULPCLKCONF            0x20A
-#define AB8500_SYSULPCLKCTRL1           0x20B
-#define AB8500_SYSCLKCTRL               0x20C
-#define AB8500_SYSCLKREQ1VALID          0x20D
-#define AB8500_SYSTEMCTRLSUP            0x20F
-#define AB8500_SYSCLKREQ1RFCLKBUF       0x210
-#define AB8500_SYSCLKREQ2RFCLKBUF       0x211
-#define AB8500_SYSCLKREQ3RFCLKBUF       0x212
-#define AB8500_SYSCLKREQ4RFCLKBUF       0x213
-#define AB8500_SYSCLKREQ5RFCLKBUF       0x214
-#define AB8500_SYSCLKREQ6RFCLKBUF       0x215
-#define AB8500_SYSCLKREQ7RFCLKBUF       0x216
-#define AB8500_SYSCLKREQ8RFCLKBUF       0x217
-#define AB8500_DITHERCLKCTRL            0x220
-#define AB8500_SWATCTRL                 0x230
-#define AB8500_HIQCLKCTRL               0x232
-#define AB8500_VSIMSYSCLKCTRL           0x233
-#define AB9540_SYSCLK12BUFCTRL          0x234
-#define AB9540_SYSCLK12CONFCTRL         0x235
-#define AB9540_SYSCLK12BUFCTRL2         0x236
-#define AB9540_SYSCLK12BUF1VALID        0x237
-#define AB9540_SYSCLK12BUF2VALID        0x238
-#define AB9540_SYSCLK12BUF3VALID        0x239
-#define AB9540_SYSCLK12BUF4VALID        0x23A
-
-/* Bits */
-#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
-#define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
-#define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
-#define AB8500_TURNONSTATUS_RTCALARM BIT(3)
-#define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
-#define AB8500_TURNONSTATUS_VBUSDET BIT(5)
-#define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
-
-#define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
-#define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
-
-#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F
-#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0
-
-#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
-#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1)
-#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2)
-#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3)
-#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4)
-#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5)
-#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6)
-#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7)
-
-#define AB8500_STW4500CTRL1_SWOFF BIT(0)
-#define AB8500_STW4500CTRL1_SWRESET4500N BIT(1)
-#define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2)
-
-#define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0)
-#define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1)
-#define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2)
-#define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3)
-#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4)
-#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5)
-#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6)
-#define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7)
-
-#define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0)
-#define AB8500_STW4500CTRL3_RESETAUDN BIT(1)
-#define AB8500_STW4500CTRL3_RESETDENCN BIT(2)
-#define AB8500_STW4500CTRL3_THSDENA BIT(3)
-
-#define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0)
-#define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1)
-#define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4)
-
-#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F
-#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0
-
-#define AB8500_LOWBAT_LOWBATENA BIT(0)
-#define AB8500_LOWBAT_LOWBAT_MASK 0x7E
-#define AB8500_LOWBAT_LOWBAT_SHIFT 1
-
-#define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F
-#define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0
-#define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0
-#define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4
-
-#define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F
-#define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0
-#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0
-#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4
-
-#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03
-#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0
-#define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2)
-
-#define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07
-#define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0
-#define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38
-#define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3
-
-#define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07
-#define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0
-#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38
-#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3
-
-#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07
-#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0
-#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38
-#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3
-
-#define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03
-#define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0
-#define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2)
-#define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3)
-#define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4)
-#define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5)
-#define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6)
-#define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7)
-
-#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03
-#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0
-#define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2)
-#define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3)
-#define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4)
-#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5)
-#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6)
-#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7)
-
-#define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0)
-#define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1)
-#define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
-
-#define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0)
-#define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1)
-#define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2)
-
-#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03
-#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0
-#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C
-#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2
-#define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4)
-
-#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2)
-#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3)
-#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4)
-
-#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2)
-#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3)
-#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4)
-
-#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2)
-#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3)
-#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4)
-
-#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2)
-#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3)
-#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4)
-
-#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2)
-#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3)
-#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4)
-
-#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2)
-#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3)
-#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4)
-
-#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2)
-#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3)
-#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4)
-
-#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2)
-#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3)
-#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4)
-
-#define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0)
-#define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1)
-#define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2)
-#define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3)
-#define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4)
-#define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5)
-#define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0
-#define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6
-
-#define AB8500_SWATCTRL_UPDATERF BIT(0)
-#define AB8500_SWATCTRL_SWATENABLE BIT(1)
-#define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C
-#define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2
-#define AB8500_SWATCTRL_SWATBIT5 BIT(6)
-
-#define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0)
-#define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1)
-#define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2)
-#define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3)
-#define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4)
-#define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5)
-#define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6)
-#define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7)
-
-#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0)
-#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1)
-#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2)
-#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3)
-#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4)
-#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
-#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
-#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
-
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
-#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
-
-#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
-#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
-#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
-#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
-#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
-#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
-#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
-
-#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
-#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
-#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
-#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
-
-#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
-#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
-
-#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
-#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
-
-#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
-#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
-
-#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
-#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
-
-#endif /* __AB8500_SYSCTRL_H */
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
deleted file mode 100644
index 1cb5698b4d7..00000000000
--- a/include/linux/mfd/abx500/ab8500.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License v2
- * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
- */
-#ifndef MFD_AB8500_H
-#define MFD_AB8500_H
-
-#include <linux/atomic.h>
-#include <linux/mutex.h>
-#include <linux/irqdomain.h>
-
-struct device;
-
-/*
- * AB IC versions
- *
- * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
- * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
- * print of version string.
- */
-enum ab8500_version {
-        AB8500_VERSION_AB8500 = 0x0,
-        AB8500_VERSION_AB8505 = 0x1,
-        AB8500_VERSION_AB9540 = 0x2,
-        AB8500_VERSION_AB8540 = 0x3,
-        AB8500_VERSION_UNDEFINED,
-};
-
-/* AB8500 CIDs*/
-#define AB8500_CUTEARLY 0x00
-#define AB8500_CUT1P0   0x10
-#define AB8500_CUT1P1   0x11
-#define AB8500_CUT2P0   0x20
-#define AB8500_CUT3P0   0x30
-#define AB8500_CUT3P3   0x33
-
-/*
- * AB8500 bank addresses
- */
-#define AB8500_SYS_CTRL1_BLOCK  0x1
-#define AB8500_SYS_CTRL2_BLOCK  0x2
-#define AB8500_REGU_CTRL1       0x3
-#define AB8500_REGU_CTRL2       0x4
-#define AB8500_USB              0x5
-#define AB8500_TVOUT            0x6
-#define AB8500_DBI              0x7
-#define AB8500_ECI_AV_ACC       0x8
-#define AB8500_RESERVED         0x9
-#define AB8500_GPADC            0xA
-#define AB8500_CHARGER          0xB
-#define AB8500_GAS_GAUGE        0xC
-#define AB8500_AUDIO            0xD
-#define AB8500_INTERRUPT        0xE
-#define AB8500_RTC              0xF
-#define AB8500_MISC             0x10
-#define AB8500_DEVELOPMENT      0x11
-#define AB8500_DEBUG            0x12
-#define AB8500_PROD_TEST        0x13
-#define AB8500_OTP_EMUL         0x15
-
-/*
- * Interrupts
- * Values used to index into array ab8500_irq_regoffset[] defined in
- * drivers/mdf/ab8500-core.c
- */
-/* Definitions for AB8500 and AB9540 */
-/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
-#define AB8500_INT_MAIN_EXT_CH_NOT_OK   0 /* not 8505/9540 */
-#define AB8500_INT_UN_PLUG_TV_DET       1 /* not 8505/9540 */
-#define AB8500_INT_PLUG_TV_DET          2 /* not 8505/9540 */
-#define AB8500_INT_TEMP_WARM            3
-#define AB8500_INT_PON_KEY2DB_F         4
-#define AB8500_INT_PON_KEY2DB_R         5
-#define AB8500_INT_PON_KEY1DB_F         6
-#define AB8500_INT_PON_KEY1DB_R         7
-/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
-#define AB8500_INT_BATT_OVV             8
-#define AB8500_INT_MAIN_CH_UNPLUG_DET   10 /* not 8505 */
-#define AB8500_INT_MAIN_CH_PLUG_DET     11 /* not 8505 */
-#define AB8500_INT_VBUS_DET_F           14
-#define AB8500_INT_VBUS_DET_R           15
-/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
-#define AB8500_INT_VBUS_CH_DROP_END     16
-#define AB8500_INT_RTC_60S              17
-#define AB8500_INT_RTC_ALARM            18
-#define AB8500_INT_BAT_CTRL_INDB        20
-#define AB8500_INT_CH_WD_EXP            21
-#define AB8500_INT_VBUS_OVV             22
-#define AB8500_INT_MAIN_CH_DROP_END     23 /* not 8505/9540 */
-/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
-#define AB8500_INT_CCN_CONV_ACC         24
-#define AB8500_INT_INT_AUD              25
-#define AB8500_INT_CCEOC                26
-#define AB8500_INT_CC_INT_CALIB         27
-#define AB8500_INT_LOW_BAT_F            28
-#define AB8500_INT_LOW_BAT_R            29
-#define AB8500_INT_BUP_CHG_NOT_OK       30
-#define AB8500_INT_BUP_CHG_OK           31
-/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
-#define AB8500_INT_GP_HW_ADC_CONV_END   32 /* not 8505 */
-#define AB8500_INT_ACC_DETECT_1DB_F     33
-#define AB8500_INT_ACC_DETECT_1DB_R     34
-#define AB8500_INT_ACC_DETECT_22DB_F    35
-#define AB8500_INT_ACC_DETECT_22DB_R    36
-#define AB8500_INT_ACC_DETECT_21DB_F    37
-#define AB8500_INT_ACC_DETECT_21DB_R    38
-#define AB8500_INT_GP_SW_ADC_CONV_END   39
-/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
-#define AB8500_INT_GPIO6R               40 /* not 8505/9540 */
-#define AB8500_INT_GPIO7R               41 /* not 8505/9540 */
-#define AB8500_INT_GPIO8R               42 /* not 8505/9540 */
-#define AB8500_INT_GPIO9R               43 /* not 8505/9540 */
-#define AB8500_INT_GPIO10R              44
-#define AB8500_INT_GPIO11R              45
-#define AB8500_INT_GPIO12R              46 /* not 8505 */
-#define AB8500_INT_GPIO13R              47
-/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
-#define AB8500_INT_GPIO24R              48 /* not 8505 */
-#define AB8500_INT_GPIO25R              49 /* not 8505 */
-#define AB8500_INT_GPIO36R              50 /* not 8505/9540 */
-#define AB8500_INT_GPIO37R              51 /* not 8505/9540 */
-#define AB8500_INT_GPIO38R              52 /* not 8505/9540 */
-#define AB8500_INT_GPIO39R              53 /* not 8505/9540 */
-#define AB8500_INT_GPIO40R              54
-#define AB8500_INT_GPIO41R              55
-/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
-#define AB8500_INT_GPIO6F               56 /* not 8505/9540 */
-#define AB8500_INT_GPIO7F               57 /* not 8505/9540 */
-#define AB8500_INT_GPIO8F               58 /* not 8505/9540 */
-#define AB8500_INT_GPIO9F               59 /* not 8505/9540 */
-#define AB8500_INT_GPIO10F              60
-#define AB8500_INT_GPIO11F              61
-#define AB8500_INT_GPIO12F              62 /* not 8505 */
-#define AB8500_INT_GPIO13F              63
-/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
-#define AB8500_INT_GPIO24F              64 /* not 8505 */
-#define AB8500_INT_GPIO25F              65 /* not 8505 */
-#define AB8500_INT_GPIO36F              66 /* not 8505/9540 */
-#define AB8500_INT_GPIO37F              67 /* not 8505/9540 */
-#define AB8500_INT_GPIO38F              68 /* not 8505/9540 */
-#define AB8500_INT_GPIO39F              69 /* not 8505/9540 */
-#define AB8500_INT_GPIO40F              70
-#define AB8500_INT_GPIO41F              71
-/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
-#define AB8500_INT_ADP_SOURCE_ERROR     72
-#define AB8500_INT_ADP_SINK_ERROR       73
-#define AB8500_INT_ADP_PROBE_PLUG       74
-#define AB8500_INT_ADP_PROBE_UNPLUG     75
-#define AB8500_INT_ADP_SENSE_OFF        76
-#define AB8500_INT_USB_PHY_POWER_ERR    78
-#define AB8500_INT_USB_LINK_STATUS      79
-/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
-#define AB8500_INT_BTEMP_LOW            80
-#define AB8500_INT_BTEMP_LOW_MEDIUM     81
-#define AB8500_INT_BTEMP_MEDIUM_HIGH    82
-#define AB8500_INT_BTEMP_HIGH           83
-/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
-#define AB8500_INT_SRP_DETECT           88
-#define AB8500_INT_USB_CHARGER_NOT_OKR  89
-#define AB8500_INT_ID_WAKEUP_R          90
-#define AB8500_INT_ID_DET_R1R           92
-#define AB8500_INT_ID_DET_R2R           93
-#define AB8500_INT_ID_DET_R3R           94
-#define AB8500_INT_ID_DET_R4R           95
-/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
-#define AB8500_INT_ID_WAKEUP_F          96
-#define AB8500_INT_ID_DET_R1F           98
-#define AB8500_INT_ID_DET_R2F           99
-#define AB8500_INT_ID_DET_R3F           100
-#define AB8500_INT_ID_DET_R4F           101
-#define AB8500_INT_CHAUTORESTARTAFTSEC  102
-#define AB8500_INT_CHSTOPBYSEC          103
-/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
-#define AB8500_INT_USB_CH_TH_PROT_F     104
-#define AB8500_INT_USB_CH_TH_PROT_R    105
-#define AB8500_INT_MAIN_CH_TH_PROT_F    106 /* not 8505/9540 */
-#define AB8500_INT_MAIN_CH_TH_PROT_R    107 /* not 8505/9540 */
-#define AB8500_INT_CHCURLIMNOHSCHIRP    109
-#define AB8500_INT_CHCURLIMHSCHIRP      110
-#define AB8500_INT_XTAL32K_KO           111
-
-/* Definitions for AB9540 */
-/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
-#define AB9540_INT_GPIO50R              113
-#define AB9540_INT_GPIO51R              114 /* not 8505 */
-#define AB9540_INT_GPIO52R              115
-#define AB9540_INT_GPIO53R              116
-#define AB9540_INT_GPIO54R              117 /* not 8505 */
-#define AB9540_INT_IEXT_CH_RF_BFN_R     118
-#define AB9540_INT_IEXT_CH_RF_BFN_F     119
-/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
-#define AB9540_INT_GPIO50F              121
-#define AB9540_INT_GPIO51F              122 /* not 8505 */
-#define AB9540_INT_GPIO52F              123
-#define AB9540_INT_GPIO53F              124
-#define AB9540_INT_GPIO54F              125 /* not 8505 */
-/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
-#define AB8505_INT_KEYSTUCK             128
-#define AB8505_INT_IKR                  129
-#define AB8505_INT_IKP                  130
-#define AB8505_INT_KP                   131
-#define AB8505_INT_KEYDEGLITCH          132
-#define AB8505_INT_MODPWRSTATUSF        134
-#define AB8505_INT_MODPWRSTATUSR        135
-
-/*
- * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
- * entire platform. This is a "compile time" constant so this must be set to
- * the largest possible value that may be encountered with different AB SOCs.
- * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
- * which is larger.
- */
-#define AB8500_NR_IRQS                  112
-#define AB8505_NR_IRQS                  136
-#define AB9540_NR_IRQS                  136
-/* This is set to the roof of any AB8500 chip variant IRQ counts */
-#define AB8500_MAX_NR_IRQS              AB9540_NR_IRQS
-
-#define AB8500_NUM_IRQ_REGS             14
-#define AB9540_NUM_IRQ_REGS             17
-
-/**
- * struct ab8500 - ab8500 internal structure
- * @dev: parent device
- * @lock: read/write operations lock
- * @irq_lock: genirq bus lock
- * @transfer_ongoing: 0 if no transfer ongoing
- * @irq: irq line
- * @irq_domain: irq domain
- * @version: chip version id (e.g. ab8500 or ab9540)
- * @chip_id: chip revision id
- * @write: register write
- * @write_masked: masked register write
- * @read: register read
- * @rx_buf: rx buf for SPI
- * @tx_buf: tx buf for SPI
- * @mask: cache of IRQ regs for bus lock
- * @oldmask: cache of previous IRQ regs for bus lock
- * @mask_size: Actual number of valid entries in mask[], oldmask[] and
- * irq_reg_offset
- * @irq_reg_offset: Array of offsets into IRQ registers
- */
-struct ab8500 {
-        struct device   *dev;
-        struct mutex    lock;
-        struct mutex    irq_lock;
-        atomic_t        transfer_ongoing;
-        int             irq_base;
-        int             irq;
-        struct irq_domain  *domain;
-        enum ab8500_version version;
-        u8              chip_id;
-
-        int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
-        int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
-        int (*read)(struct ab8500 *ab8500, u16 addr);
-
-        unsigned long   tx_buf[4];
-        unsigned long   rx_buf[4];
-
-        u8 *mask;
-        u8 *oldmask;
-        int mask_size;
-        const int *irq_reg_offset;
-};
-
-struct regulator_reg_init;
-struct regulator_init_data;
-struct ab8500_gpio_platform_data;
-struct ab8500_codec_platform_data;
-
-/**
- * struct ab8500_platform_data - AB8500 platform data
- * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
- * @init: board-specific initialization after detection of ab8500
- * @num_regulator_reg_init: number of regulator init registers
- * @regulator_reg_init: regulator init registers
- * @num_regulator: number of regulators
- * @regulator: machine-specific constraints for regulators
- */
-struct ab8500_platform_data {
-        int irq_base;
-        void (*init) (struct ab8500 *);
-        int num_regulator_reg_init;
-        struct ab8500_regulator_reg_init *regulator_reg_init;
-        int num_regulator;
-        struct regulator_init_data *regulator;
-        struct ab8500_gpio_platform_data *gpio;
-        struct ab8500_codec_platform_data *codec;
-};
-
-extern int ab8500_init(struct ab8500 *ab8500,
-                                 enum ab8500_version version);
-extern int ab8500_exit(struct ab8500 *ab8500);
-
-extern int ab8500_suspend(struct ab8500 *ab8500);
-
-static inline int is_ab8500(struct ab8500 *ab)
-{
-        return ab->version == AB8500_VERSION_AB8500;
-}
-
-static inline int is_ab8505(struct ab8500 *ab)
-{
-        return ab->version == AB8500_VERSION_AB8505;
-}
-
-static inline int is_ab9540(struct ab8500 *ab)
-{
-        return ab->version == AB8500_VERSION_AB9540;
-}
-
-static inline int is_ab8540(struct ab8500 *ab)
-{
-        return ab->version == AB8500_VERSION_AB8540;
-}
-
-/* exclude also ab8505, ab9540... */
-static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
-{
-        return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
-}
-
-/* exclude also ab8505, ab9540... */
-static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
-{
-        return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
-}
-
-/* exclude also ab8505, ab9540... */
-static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
-{
-        return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
-}
-
-/* exclude also ab8505, ab9540... */
-static inline int is_ab8500_2p0(struct ab8500 *ab)
-{
-        return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
-}
-
-#endif /* MFD_AB8500_H */
diff --git a/include/linux/mfd/abx500/ux500_chargalg.h b/include/linux/mfd/abx500/ux500_chargalg.h
deleted file mode 100644
index 9b07725750c..00000000000
--- a/include/linux/mfd/abx500/ux500_chargalg.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2012
- * Author: Johan Gardsmark <johan.gardsmark@stericsson.com> for ST-Ericsson.
- * License terms:  GNU General Public License (GPL), version 2
- */
-
-#ifndef _UX500_CHARGALG_H
-#define _UX500_CHARGALG_H
-
-#include <linux/power_supply.h>
-
-#define psy_to_ux500_charger(x) container_of((x), \
-                struct ux500_charger, psy)
-
-/* Forward declaration */
-struct ux500_charger;
-
-struct ux500_charger_ops {
-        int (*enable) (struct ux500_charger *, int, int, int);
-        int (*kick_wd) (struct ux500_charger *);
-        int (*update_curr) (struct ux500_charger *, int);
-};
-
-/**
- * struct ux500_charger - power supply ux500 charger sub class
- * @psy                 power supply base class
- * @ops                 ux500 charger operations
- * @max_out_volt        maximum output charger voltage in mV
- * @max_out_curr        maximum output charger current in mA
- */
-struct ux500_charger {
-        struct power_supply psy;
-        struct ux500_charger_ops ops;
-        int max_out_volt;
-        int max_out_curr;
-};
-
-#endif
diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
deleted file mode 100644
index a580363a7d2..00000000000
--- a/include/linux/mfd/arizona/core.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Arizona MFD internals
- *
- * Copyright 2012 Wolfson Microelectronics plc
- *
- * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _WM_ARIZONA_CORE_H
-#define _WM_ARIZONA_CORE_H
-
-#include <linux/interrupt.h>
-#include <linux/regmap.h>
-#include <linux/regulator/consumer.h>
-#include <linux/mfd/arizona/pdata.h>
-
-#define ARIZONA_MAX_CORE_SUPPLIES 3
-
-enum arizona_type {
-        WM5102 = 1,
-        WM5110 = 2,
-};
-
-#define ARIZONA_IRQ_GP1                    0
-#define ARIZONA_IRQ_GP2                    1
-#define ARIZONA_IRQ_GP3                    2
-#define ARIZONA_IRQ_GP4                    3
-#define ARIZONA_IRQ_GP5_FALL               4
-#define ARIZONA_IRQ_GP5_RISE               5
-#define ARIZONA_IRQ_JD_FALL                6
-#define ARIZONA_IRQ_JD_RISE                7
-#define ARIZONA_IRQ_DSP1_RAM_RDY           8
-#define ARIZONA_IRQ_DSP2_RAM_RDY           9
-#define ARIZONA_IRQ_DSP3_RAM_RDY          10
-#define ARIZONA_IRQ_DSP4_RAM_RDY          11
-#define ARIZONA_IRQ_DSP_IRQ1              12
-#define ARIZONA_IRQ_DSP_IRQ2              13
-#define ARIZONA_IRQ_DSP_IRQ3              14
-#define ARIZONA_IRQ_DSP_IRQ4              15
-#define ARIZONA_IRQ_DSP_IRQ5              16
-#define ARIZONA_IRQ_DSP_IRQ6              17
-#define ARIZONA_IRQ_DSP_IRQ7              18
-#define ARIZONA_IRQ_DSP_IRQ8              19
-#define ARIZONA_IRQ_SPK_SHUTDOWN_WARN     20
-#define ARIZONA_IRQ_SPK_SHUTDOWN          21
-#define ARIZONA_IRQ_MICDET                22
-#define ARIZONA_IRQ_HPDET                 23
-#define ARIZONA_IRQ_WSEQ_DONE             24
-#define ARIZONA_IRQ_DRC2_SIG_DET          25
-#define ARIZONA_IRQ_DRC1_SIG_DET          26
-#define ARIZONA_IRQ_ASRC2_LOCK            27
-#define ARIZONA_IRQ_ASRC1_LOCK            28
-#define ARIZONA_IRQ_UNDERCLOCKED          29
-#define ARIZONA_IRQ_OVERCLOCKED           30
-#define ARIZONA_IRQ_FLL2_LOCK             31
-#define ARIZONA_IRQ_FLL1_LOCK             32
-#define ARIZONA_IRQ_CLKGEN_ERR            33
-#define ARIZONA_IRQ_CLKGEN_ERR_ASYNC      34
-#define ARIZONA_IRQ_ASRC_CFG_ERR          35
-#define ARIZONA_IRQ_AIF3_ERR              36
-#define ARIZONA_IRQ_AIF2_ERR              37
-#define ARIZONA_IRQ_AIF1_ERR              38
-#define ARIZONA_IRQ_CTRLIF_ERR            39
-#define ARIZONA_IRQ_MIXER_DROPPED_SAMPLES 40
-#define ARIZONA_IRQ_ASYNC_CLK_ENA_LOW     41
-#define ARIZONA_IRQ_SYSCLK_ENA_LOW        42
-#define ARIZONA_IRQ_ISRC1_CFG_ERR         43
-#define ARIZONA_IRQ_ISRC2_CFG_ERR         44
-#define ARIZONA_IRQ_BOOT_DONE             45
-#define ARIZONA_IRQ_DCS_DAC_DONE          46
-#define ARIZONA_IRQ_DCS_HP_DONE           47
-#define ARIZONA_IRQ_FLL2_CLOCK_OK         48
-#define ARIZONA_IRQ_FLL1_CLOCK_OK         49
-
-#define ARIZONA_NUM_IRQ                   50
-
-struct snd_soc_dapm_context;
-
-struct arizona {
-        struct regmap *regmap;
-        struct device *dev;
-
-        enum arizona_type type;
-        unsigned int rev;
-
-        int num_core_supplies;
-        struct regulator_bulk_data core_supplies[ARIZONA_MAX_CORE_SUPPLIES];
-        struct regulator *dcvdd;
-
-        struct arizona_pdata pdata;
-
-        int irq;
-        struct irq_domain *virq;
-        struct regmap_irq_chip_data *aod_irq_chip;
-        struct regmap_irq_chip_data *irq_chip;
-
-        struct mutex clk_lock;
-        int clk32k_ref;
-
-        struct snd_soc_dapm_context *dapm;
-};
-
-int arizona_clk32k_enable(struct arizona *arizona);
-int arizona_clk32k_disable(struct arizona *arizona);
-
-int arizona_request_irq(struct arizona *arizona, int irq, char *name,
-                        irq_handler_t handler, void *data);
-void arizona_free_irq(struct arizona *arizona, int irq, void *data);
-int arizona_set_irq_wake(struct arizona *arizona, int irq, int on);
-
-int wm5102_patch(struct arizona *arizona);
-int wm5110_patch(struct arizona *arizona);
-
-#endif
diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h
deleted file mode 100644
index 8b1d1daaae1..00000000000
--- a/include/linux/mfd/arizona/pdata.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Platform data for Arizona devices
- *
- * Copyright 2012 Wolfson Microelectronics. PLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _ARIZONA_PDATA_H
-#define _ARIZONA_PDATA_H
-
-#define ARIZONA_GPN_DIR                          0x8000  /* GPN_DIR */
-#define ARIZONA_GPN_DIR_MASK                     0x8000  /* GPN_DIR */
-#define ARIZONA_GPN_DIR_SHIFT                        15  /* GPN_DIR */
-#define ARIZONA_GPN_DIR_WIDTH                         1  /* GPN_DIR */
-#define ARIZONA_GPN_PU                           0x4000  /* GPN_PU */
-#define ARIZONA_GPN_PU_MASK                      0x4000  /* GPN_PU */
-#define ARIZONA_GPN_PU_SHIFT                         14  /* GPN_PU */
-#define ARIZONA_GPN_PU_WIDTH                          1  /* GPN_PU */
-#define ARIZONA_GPN_PD                           0x2000  /* GPN_PD */
-#define ARIZONA_GPN_PD_MASK                      0x2000  /* GPN_PD */
-#define ARIZONA_GPN_PD_SHIFT                         13  /* GPN_PD */
-#define ARIZONA_GPN_PD_WIDTH                          1  /* GPN_PD */
-#define ARIZONA_GPN_LVL                          0x0800  /* GPN_LVL */
-#define ARIZONA_GPN_LVL_MASK                     0x0800  /* GPN_LVL */
-#define ARIZONA_GPN_LVL_SHIFT                        11  /* GPN_LVL */
-#define ARIZONA_GPN_LVL_WIDTH                         1  /* GPN_LVL */
-#define ARIZONA_GPN_POL                          0x0400  /* GPN_POL */
-#define ARIZONA_GPN_POL_MASK                     0x0400  /* GPN_POL */
-#define ARIZONA_GPN_POL_SHIFT                        10  /* GPN_POL */
-#define ARIZONA_GPN_POL_WIDTH                         1  /* GPN_POL */
-#define ARIZONA_GPN_OP_CFG                       0x0200  /* GPN_OP_CFG */
-#define ARIZONA_GPN_OP_CFG_MASK                  0x0200  /* GPN_OP_CFG */
-#define ARIZONA_GPN_OP_CFG_SHIFT                      9  /* GPN_OP_CFG */
-#define ARIZONA_GPN_OP_CFG_WIDTH                      1  /* GPN_OP_CFG */
-#define ARIZONA_GPN_DB                           0x0100  /* GPN_DB */
-#define ARIZONA_GPN_DB_MASK                      0x0100  /* GPN_DB */
-#define ARIZONA_GPN_DB_SHIFT                          8  /* GPN_DB */
-#define ARIZONA_GPN_DB_WIDTH                          1  /* GPN_DB */
-#define ARIZONA_GPN_FN_MASK                      0x007F  /* GPN_FN - [6:0] */
-#define ARIZONA_GPN_FN_SHIFT                          0  /* GPN_FN - [6:0] */
-#define ARIZONA_GPN_FN_WIDTH                          7  /* GPN_FN - [6:0] */
-
-#define ARIZONA_MAX_GPIO 5
-
-#define ARIZONA_32KZ_MCLK1 1
-#define ARIZONA_32KZ_MCLK2 2
-#define ARIZONA_32KZ_NONE  3
-
-#define ARIZONA_MAX_INPUT 4
-
-#define ARIZONA_DMIC_MICVDD   0
-#define ARIZONA_DMIC_MICBIAS1 1
-#define ARIZONA_DMIC_MICBIAS2 2
-#define ARIZONA_DMIC_MICBIAS3 3
-
-#define ARIZONA_INMODE_DIFF 0
-#define ARIZONA_INMODE_SE   1
-#define ARIZONA_INMODE_DMIC 2
-
-#define ARIZONA_MAX_OUTPUT 6
-
-#define ARIZONA_HAP_ACT_ERM 0
-#define ARIZONA_HAP_ACT_LRA 2
-
-#define ARIZONA_MAX_PDM_SPK 2
-
-struct regulator_init_data;
-
-struct arizona_micd_config {
-        unsigned int src;
-        unsigned int bias;
-        bool gpio;
-};
-
-struct arizona_pdata {
-        int reset;      /** GPIO controlling /RESET, if any */
-        int ldoena;     /** GPIO controlling LODENA, if any */
-
-        /** Regulator configuration for MICVDD */
-        struct regulator_init_data *micvdd;
-
-        /** Regulator configuration for LDO1 */
-        struct regulator_init_data *ldo1;
-
-        /** If a direct 32kHz clock is provided on an MCLK specify it here */
-        int clk32k_src;
-
-        bool irq_active_high; /** IRQ polarity */
-
-        /* Base GPIO */
-        int gpio_base;
-
-        /** Pin state for GPIO pins */
-        int gpio_defaults[ARIZONA_MAX_GPIO];
-
-        /** GPIO for mic detection polarity */
-        int micd_pol_gpio;
-
-        /** Headset polarity configurations */
-        struct arizona_micd_config *micd_configs;
-        int num_micd_configs;
-
-        /** Reference voltage for DMIC inputs */
-        int dmic_ref[ARIZONA_MAX_INPUT];
-
-        /** Mode of input structures */
-        int inmode[ARIZONA_MAX_INPUT];
-
-        /** Mode for outputs */
-        bool out_mono[ARIZONA_MAX_OUTPUT];
-
-        /** PDM speaker mute setting */
-        unsigned int spk_mute[ARIZONA_MAX_PDM_SPK];
-
-        /** PDM speaker format */
-        unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK];
-
-        /** Haptic actuator type */
-        unsigned int hap_act;
-};
-
-#endif
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
deleted file mode 100644
index 1f6fe31a4d5..00000000000
--- a/include/linux/mfd/arizona/registers.h
+++ /dev/null
@@ -1,6611 +0,0 @@
-/*
- * ARIZONA register definitions
- *
- * Copyright 2012 Wolfson Microelectronics plc
- *
- * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _ARIZONA_REGISTERS_H
-#define _ARIZONA_REGISTERS_H
-
-/*
- * Register values.
- */
-#define ARIZONA_SOFTWARE_RESET                   0x00
-#define ARIZONA_DEVICE_REVISION                  0x01
-#define ARIZONA_CTRL_IF_SPI_CFG_1                0x08
-#define ARIZONA_CTRL_IF_I2C1_CFG_1               0x09
-#define ARIZONA_CTRL_IF_I2C2_CFG_1               0x0A
-#define ARIZONA_CTRL_IF_I2C1_CFG_2               0x0B
-#define ARIZONA_CTRL_IF_I2C2_CFG_2               0x0C
-#define ARIZONA_CTRL_IF_STATUS_1                 0x0D
-#define ARIZONA_WRITE_SEQUENCER_CTRL_0           0x16
-#define ARIZONA_WRITE_SEQUENCER_CTRL_1           0x17
-#define ARIZONA_WRITE_SEQUENCER_CTRL_2           0x18
-#define ARIZONA_WRITE_SEQUENCER_PROM             0x1A
-#define ARIZONA_TONE_GENERATOR_1                 0x20
-#define ARIZONA_TONE_GENERATOR_2                 0x21
-#define ARIZONA_TONE_GENERATOR_3                 0x22
-#define ARIZONA_TONE_GENERATOR_4                 0x23
-#define ARIZONA_TONE_GENERATOR_5                 0x24
-#define ARIZONA_PWM_DRIVE_1                      0x30
-#define ARIZONA_PWM_DRIVE_2                      0x31
-#define ARIZONA_PWM_DRIVE_3                      0x32
-#define ARIZONA_WAKE_CONTROL                     0x40
-#define ARIZONA_SEQUENCE_CONTROL                 0x41
-#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1    0x61
-#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2    0x62
-#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3    0x63
-#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4    0x64
-#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68
-#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69
-#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A
-#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B
-#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C
-#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D
-#define ARIZONA_COMFORT_NOISE_GENERATOR          0x70
-#define ARIZONA_HAPTICS_CONTROL_1                0x90
-#define ARIZONA_HAPTICS_CONTROL_2                0x91
-#define ARIZONA_HAPTICS_PHASE_1_INTENSITY        0x92
-#define ARIZONA_HAPTICS_PHASE_1_DURATION         0x93
-#define ARIZONA_HAPTICS_PHASE_2_INTENSITY        0x94
-#define ARIZONA_HAPTICS_PHASE_2_DURATION         0x95
-#define ARIZONA_HAPTICS_PHASE_3_INTENSITY        0x96
-#define ARIZONA_HAPTICS_PHASE_3_DURATION         0x97
-#define ARIZONA_HAPTICS_STATUS                   0x98
-#define ARIZONA_CLOCK_32K_1                      0x100
-#define ARIZONA_SYSTEM_CLOCK_1                   0x101
-#define ARIZONA_SAMPLE_RATE_1                    0x102
-#define ARIZONA_SAMPLE_RATE_2                    0x103
-#define ARIZONA_SAMPLE_RATE_3                    0x104
-#define ARIZONA_SAMPLE_RATE_1_STATUS             0x10A
-#define ARIZONA_SAMPLE_RATE_2_STATUS             0x10B
-#define ARIZONA_SAMPLE_RATE_3_STATUS             0x10C
-#define ARIZONA_ASYNC_CLOCK_1                    0x112
-#define ARIZONA_ASYNC_SAMPLE_RATE_1              0x113
-#define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS       0x11B
-#define ARIZONA_OUTPUT_SYSTEM_CLOCK              0x149
-#define ARIZONA_OUTPUT_ASYNC_CLOCK               0x14A
-#define ARIZONA_RATE_ESTIMATOR_1                 0x152
-#define ARIZONA_RATE_ESTIMATOR_2                 0x153
-#define ARIZONA_RATE_ESTIMATOR_3                 0x154
-#define ARIZONA_RATE_ESTIMATOR_4                 0x155
-#define ARIZONA_RATE_ESTIMATOR_5                 0x156
-#define ARIZONA_DYNAMIC_FREQUENCY_SCALING_1      0x161
-#define ARIZONA_FLL1_CONTROL_1                   0x171
-#define ARIZONA_FLL1_CONTROL_2                   0x172
-#define ARIZONA_FLL1_CONTROL_3                   0x173
-#define ARIZONA_FLL1_CONTROL_4                   0x174
-#define ARIZONA_FLL1_CONTROL_5                   0x175
-#define ARIZONA_FLL1_CONTROL_6                   0x176
-#define ARIZONA_FLL1_LOOP_FILTER_TEST_1          0x177
-#define ARIZONA_FLL1_NCO_TEST_0                  0x178
-#define ARIZONA_FLL1_SYNCHRONISER_1              0x181
-#define ARIZONA_FLL1_SYNCHRONISER_2              0x182
-#define ARIZONA_FLL1_SYNCHRONISER_3              0x183
-#define ARIZONA_FLL1_SYNCHRONISER_4              0x184
-#define ARIZONA_FLL1_SYNCHRONISER_5              0x185
-#define ARIZONA_FLL1_SYNCHRONISER_6              0x186
-#define ARIZONA_FLL1_SPREAD_SPECTRUM             0x189
-#define ARIZONA_FLL1_GPIO_CLOCK                  0x18A
-#define ARIZONA_FLL2_CONTROL_1                   0x191
-#define ARIZONA_FLL2_CONTROL_2                   0x192
-#define ARIZONA_FLL2_CONTROL_3                   0x193
-#define ARIZONA_FLL2_CONTROL_4                   0x194
-#define ARIZONA_FLL2_CONTROL_5                   0x195
-#define ARIZONA_FLL2_CONTROL_6                   0x196
-#define ARIZONA_FLL2_LOOP_FILTER_TEST_1          0x197
-#define ARIZONA_FLL2_NCO_TEST_0                  0x198
-#define ARIZONA_FLL2_SYNCHRONISER_1              0x1A1
-#define ARIZONA_FLL2_SYNCHRONISER_2              0x1A2
-#define ARIZONA_FLL2_SYNCHRONISER_3              0x1A3
-#define ARIZONA_FLL2_SYNCHRONISER_4              0x1A4
-#define ARIZONA_FLL2_SYNCHRONISER_5              0x1A5
-#define ARIZONA_FLL2_SYNCHRONISER_6              0x1A6
-#define ARIZONA_FLL2_SPREAD_SPECTRUM             0x1A9
-#define ARIZONA_FLL2_GPIO_CLOCK                  0x1AA
-#define ARIZONA_MIC_CHARGE_PUMP_1                0x200
-#define ARIZONA_LDO1_CONTROL_1                   0x210
-#define ARIZONA_LDO1_CONTROL_2                   0x212
-#define ARIZONA_LDO2_CONTROL_1                   0x213
-#define ARIZONA_MIC_BIAS_CTRL_1                  0x218
-#define ARIZONA_MIC_BIAS_CTRL_2                  0x219
-#define ARIZONA_MIC_BIAS_CTRL_3                  0x21A
-#define ARIZONA_ACCESSORY_DETECT_MODE_1          0x293
-#define ARIZONA_HEADPHONE_DETECT_1               0x29B
-#define ARIZONA_HEADPHONE_DETECT_2               0x29C
-#define ARIZONA_MIC_DETECT_1                     0x2A3
-#define ARIZONA_MIC_DETECT_2                     0x2A4
-#define ARIZONA_MIC_DETECT_3                     0x2A5
-#define ARIZONA_MIC_NOISE_MIX_CONTROL_1          0x2C3
-#define ARIZONA_ISOLATION_CONTROL                0x2CB
-#define ARIZONA_JACK_DETECT_ANALOGUE             0x2D3
-#define ARIZONA_INPUT_ENABLES                    0x300
-#define ARIZONA_INPUT_ENABLES_STATUS             0x301
-#define ARIZONA_INPUT_RATE                       0x308
-#define ARIZONA_INPUT_VOLUME_RAMP                0x309
-#define ARIZONA_IN1L_CONTROL                     0x310
-#define ARIZONA_ADC_DIGITAL_VOLUME_1L            0x311
-#define ARIZONA_DMIC1L_CONTROL                   0x312
-#define ARIZONA_IN1R_CONTROL                     0x314
-#define ARIZONA_ADC_DIGITAL_VOLUME_1R            0x315
-#define ARIZONA_DMIC1R_CONTROL                   0x316
-#define ARIZONA_IN2L_CONTROL                     0x318
-#define ARIZONA_ADC_DIGITAL_VOLUME_2L            0x319
-#define ARIZONA_DMIC2L_CONTROL                   0x31A
-#define ARIZONA_IN2R_CONTROL                     0x31C
-#define ARIZONA_ADC_DIGITAL_VOLUME_2R            0x31D
-#define ARIZONA_DMIC2R_CONTROL                   0x31E
-#define ARIZONA_IN3L_CONTROL                     0x320
-#define ARIZONA_ADC_DIGITAL_VOLUME_3L            0x321
-#define ARIZONA_DMIC3L_CONTROL                   0x322
-#define ARIZONA_IN3R_CONTROL                     0x324
-#define ARIZONA_ADC_DIGITAL_VOLUME_3R            0x325
-#define ARIZONA_DMIC3R_CONTROL                   0x326
-#define ARIZONA_IN4L_CONTROL                     0x328
-#define ARIZONA_ADC_DIGITAL_VOLUME_4L            0x329
-#define ARIZONA_DMIC4L_CONTROL                   0x32A
-#define ARIZONA_ADC_DIGITAL_VOLUME_4R            0x32D
-#define ARIZONA_DMIC4R_CONTROL                   0x32E
-#define ARIZONA_OUTPUT_ENABLES_1                 0x400
-#define ARIZONA_OUTPUT_STATUS_1                  0x401
-#define ARIZONA_RAW_OUTPUT_STATUS_1              0x406
-#define ARIZONA_OUTPUT_RATE_1                    0x408
-#define ARIZONA_OUTPUT_VOLUME_RAMP               0x409
-#define ARIZONA_OUTPUT_PATH_CONFIG_1L            0x410
-#define ARIZONA_DAC_DIGITAL_VOLUME_1L            0x411
-#define ARIZONA_DAC_VOLUME_LIMIT_1L              0x412
-#define ARIZONA_NOISE_GATE_SELECT_1L             0x413
-#define ARIZONA_OUTPUT_PATH_CONFIG_1R            0x414
-#define ARIZONA_DAC_DIGITAL_VOLUME_1R            0x415
-#define ARIZONA_DAC_VOLUME_LIMIT_1R              0x416
-#define ARIZONA_NOISE_GATE_SELECT_1R             0x417
-#define ARIZONA_OUTPUT_PATH_CONFIG_2L            0x418
-#define ARIZONA_DAC_DIGITAL_VOLUME_2L            0x419
-#define ARIZONA_DAC_VOLUME_LIMIT_2L              0x41A
-#define ARIZONA_NOISE_GATE_SELECT_2L             0x41B
-#define ARIZONA_OUTPUT_PATH_CONFIG_2R            0x41C
-#define ARIZONA_DAC_DIGITAL_VOLUME_2R            0x41D
-#define ARIZONA_DAC_VOLUME_LIMIT_2R              0x41E
-#define ARIZONA_NOISE_GATE_SELECT_2R             0x41F
-#define ARIZONA_OUTPUT_PATH_CONFIG_3L            0x420
-#define ARIZONA_DAC_DIGITAL_VOLUME_3L            0x421
-#define ARIZONA_DAC_VOLUME_LIMIT_3L              0x422
-#define ARIZONA_NOISE_GATE_SELECT_3L             0x423
-#define ARIZONA_OUTPUT_PATH_CONFIG_3R            0x424
-#define ARIZONA_DAC_DIGITAL_VOLUME_3R            0x425
-#define ARIZONA_DAC_VOLUME_LIMIT_3R              0x426
-#define ARIZONA_NOISE_GATE_SELECT_3R             0x427
-#define ARIZONA_OUTPUT_PATH_CONFIG_4L            0x428
-#define ARIZONA_DAC_DIGITAL_VOLUME_4L            0x429
-#define ARIZONA_OUT_VOLUME_4L                    0x42A
-#define ARIZONA_NOISE_GATE_SELECT_4L             0x42B
-#define ARIZONA_OUTPUT_PATH_CONFIG_4R            0x42C
-#define ARIZONA_DAC_DIGITAL_VOLUME_4R            0x42D
-#define ARIZONA_OUT_VOLUME_4R                    0x42E
-#define ARIZONA_NOISE_GATE_SELECT_4R             0x42F
-#define ARIZONA_OUTPUT_PATH_CONFIG_5L            0x430
-#define ARIZONA_DAC_DIGITAL_VOLUME_5L            0x431
-#define ARIZONA_DAC_VOLUME_LIMIT_5L              0x432
-#define ARIZONA_NOISE_GATE_SELECT_5L             0x433
-#define ARIZONA_OUTPUT_PATH_CONFIG_5R            0x434
-#define ARIZONA_DAC_DIGITAL_VOLUME_5R            0x435
-#define ARIZONA_DAC_VOLUME_LIMIT_5R              0x436
-#define ARIZONA_NOISE_GATE_SELECT_5R             0x437
-#define ARIZONA_OUTPUT_PATH_CONFIG_6L            0x438
-#define ARIZONA_DAC_DIGITAL_VOLUME_6L            0x439
-#define ARIZONA_DAC_VOLUME_LIMIT_6L              0x43A
-#define ARIZONA_NOISE_GATE_SELECT_6L             0x43B
-#define ARIZONA_OUTPUT_PATH_CONFIG_6R            0x43C
-#define ARIZONA_DAC_DIGITAL_VOLUME_6R            0x43D
-#define ARIZONA_DAC_VOLUME_LIMIT_6R              0x43E
-#define ARIZONA_NOISE_GATE_SELECT_6R             0x43F
-#define ARIZONA_DAC_AEC_CONTROL_1                0x450
-#define ARIZONA_NOISE_GATE_CONTROL               0x458
-#define ARIZONA_PDM_SPK1_CTRL_1                  0x490
-#define ARIZONA_PDM_SPK1_CTRL_2                  0x491
-#define ARIZONA_PDM_SPK2_CTRL_1                  0x492
-#define ARIZONA_PDM_SPK2_CTRL_2                  0x493
-#define ARIZONA_DAC_COMP_1                       0x4DC
-#define ARIZONA_DAC_COMP_2                       0x4DD
-#define ARIZONA_DAC_COMP_3                       0x4DE
-#define ARIZONA_DAC_COMP_4                       0x4DF
-#define ARIZONA_AIF1_BCLK_CTRL                   0x500
-#define ARIZONA_AIF1_TX_PIN_CTRL                 0x501
-#define ARIZONA_AIF1_RX_PIN_CTRL                 0x502
-#define ARIZONA_AIF1_RATE_CTRL                   0x503
-#define ARIZONA_AIF1_FORMAT                      0x504
-#define ARIZONA_AIF1_TX_BCLK_RATE                0x505
-#define ARIZONA_AIF1_RX_BCLK_RATE                0x506
-#define ARIZONA_AIF1_FRAME_CTRL_1                0x507
-#define ARIZONA_AIF1_FRAME_CTRL_2                0x508
-#define ARIZONA_AIF1_FRAME_CTRL_3                0x509
-#define ARIZONA_AIF1_FRAME_CTRL_4                0x50A
-#define ARIZONA_AIF1_FRAME_CTRL_5                0x50B
-#define ARIZONA_AIF1_FRAME_CTRL_6                0x50C
-#define ARIZONA_AIF1_FRAME_CTRL_7                0x50D
-#define ARIZONA_AIF1_FRAME_CTRL_8                0x50E
-#define ARIZONA_AIF1_FRAME_CTRL_9                0x50F
-#define ARIZONA_AIF1_FRAME_CTRL_10               0x510
-#define ARIZONA_AIF1_FRAME_CTRL_11               0x511
-#define ARIZONA_AIF1_FRAME_CTRL_12               0x512
-#define ARIZONA_AIF1_FRAME_CTRL_13               0x513
-#define ARIZONA_AIF1_FRAME_CTRL_14               0x514
-#define ARIZONA_AIF1_FRAME_CTRL_15               0x515
-#define ARIZONA_AIF1_FRAME_CTRL_16               0x516
-#define ARIZONA_AIF1_FRAME_CTRL_17               0x517
-#define ARIZONA_AIF1_FRAME_CTRL_18               0x518
-#define ARIZONA_AIF1_TX_ENABLES                  0x519
-#define ARIZONA_AIF1_RX_ENABLES                  0x51A
-#define ARIZONA_AIF1_FORCE_WRITE                 0x51B
-#define ARIZONA_AIF2_BCLK_CTRL                   0x540
-#define ARIZONA_AIF2_TX_PIN_CTRL                 0x541
-#define ARIZONA_AIF2_RX_PIN_CTRL                 0x542
-#define ARIZONA_AIF2_RATE_CTRL                   0x543
-#define ARIZONA_AIF2_FORMAT                      0x544
-#define ARIZONA_AIF2_TX_BCLK_RATE                0x545
-#define ARIZONA_AIF2_RX_BCLK_RATE                0x546
-#define ARIZONA_AIF2_FRAME_CTRL_1                0x547
-#define ARIZONA_AIF2_FRAME_CTRL_2                0x548
-#define ARIZONA_AIF2_FRAME_CTRL_3                0x549
-#define ARIZONA_AIF2_FRAME_CTRL_4                0x54A
-#define ARIZONA_AIF2_FRAME_CTRL_11               0x551
-#define ARIZONA_AIF2_FRAME_CTRL_12               0x552
-#define ARIZONA_AIF2_TX_ENABLES                  0x559
-#define ARIZONA_AIF2_RX_ENABLES                  0x55A
-#define ARIZONA_AIF2_FORCE_WRITE                 0x55B
-#define ARIZONA_AIF3_BCLK_CTRL                   0x580
-#define ARIZONA_AIF3_TX_PIN_CTRL                 0x581
-#define ARIZONA_AIF3_RX_PIN_CTRL                 0x582
-#define ARIZONA_AIF3_RATE_CTRL                   0x583
-#define ARIZONA_AIF3_FORMAT                      0x584
-#define ARIZONA_AIF3_TX_BCLK_RATE                0x585
-#define ARIZONA_AIF3_RX_BCLK_RATE                0x586
-#define ARIZONA_AIF3_FRAME_CTRL_1                0x587
-#define ARIZONA_AIF3_FRAME_CTRL_2                0x588
-#define ARIZONA_AIF3_FRAME_CTRL_3                0x589
-#define ARIZONA_AIF3_FRAME_CTRL_4                0x58A
-#define ARIZONA_AIF3_FRAME_CTRL_11               0x591
-#define ARIZONA_AIF3_FRAME_CTRL_12               0x592
-#define ARIZONA_AIF3_TX_ENABLES                  0x599
-#define ARIZONA_AIF3_RX_ENABLES                  0x59A
-#define ARIZONA_AIF3_FORCE_WRITE                 0x59B
-#define ARIZONA_SLIMBUS_FRAMER_REF_GEAR          0x5E3
-#define ARIZONA_SLIMBUS_RATES_1                  0x5E5
-#define ARIZONA_SLIMBUS_RATES_2                  0x5E6
-#define ARIZONA_SLIMBUS_RATES_3                  0x5E7
-#define ARIZONA_SLIMBUS_RATES_4                  0x5E8
-#define ARIZONA_SLIMBUS_RATES_5                  0x5E9
-#define ARIZONA_SLIMBUS_RATES_6                  0x5EA
-#define ARIZONA_SLIMBUS_RATES_7                  0x5EB
-#define ARIZONA_SLIMBUS_RATES_8                  0x5EC
-#define ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE        0x5F5
-#define ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE        0x5F6
-#define ARIZONA_SLIMBUS_RX_PORT_STATUS           0x5F7
-#define ARIZONA_SLIMBUS_TX_PORT_STATUS           0x5F8
-#define ARIZONA_PWM1MIX_INPUT_1_SOURCE           0x640
-#define ARIZONA_PWM1MIX_INPUT_1_VOLUME           0x641
-#define ARIZONA_PWM1MIX_INPUT_2_SOURCE           0x642
-#define ARIZONA_PWM1MIX_INPUT_2_VOLUME           0x643
-#define ARIZONA_PWM1MIX_INPUT_3_SOURCE           0x644
-#define ARIZONA_PWM1MIX_INPUT_3_VOLUME           0x645
-#define ARIZONA_PWM1MIX_INPUT_4_SOURCE           0x646
-#define ARIZONA_PWM1MIX_INPUT_4_VOLUME           0x647
-#define ARIZONA_PWM2MIX_INPUT_1_SOURCE           0x648
-#define ARIZONA_PWM2MIX_INPUT_1_VOLUME           0x649
-#define ARIZONA_PWM2MIX_INPUT_2_SOURCE           0x64A
-#define ARIZONA_PWM2MIX_INPUT_2_VOLUME           0x64B
-#define ARIZONA_PWM2MIX_INPUT_3_SOURCE           0x64C
-#define ARIZONA_PWM2MIX_INPUT_3_VOLUME           0x64D
-#define ARIZONA_PWM2MIX_INPUT_4_SOURCE           0x64E
-#define ARIZONA_PWM2MIX_INPUT_4_VOLUME           0x64F
-#define ARIZONA_MICMIX_INPUT_1_SOURCE            0x660
-#define ARIZONA_MICMIX_INPUT_1_VOLUME            0x661
-#define ARIZONA_MICMIX_INPUT_2_SOURCE            0x662
-#define ARIZONA_MICMIX_INPUT_2_VOLUME            0x663
-#define ARIZONA_MICMIX_INPUT_3_SOURCE            0x664
-#define ARIZONA_MICMIX_INPUT_3_VOLUME            0x665
-#define ARIZONA_MICMIX_INPUT_4_SOURCE            0x666
-#define ARIZONA_MICMIX_INPUT_4_VOLUME            0x667
-#define ARIZONA_NOISEMIX_INPUT_1_SOURCE          0x668
-#define ARIZONA_NOISEMIX_INPUT_1_VOLUME          0x669
-#define ARIZONA_NOISEMIX_INPUT_2_SOURCE          0x66A
-#define ARIZONA_NOISEMIX_INPUT_2_VOLUME          0x66B
-#define ARIZONA_NOISEMIX_INPUT_3_SOURCE          0x66C
-#define ARIZONA_NOISEMIX_INPUT_3_VOLUME          0x66D
-#define ARIZONA_NOISEMIX_INPUT_4_SOURCE          0x66E
-#define ARIZONA_NOISEMIX_INPUT_4_VOLUME          0x66F
-#define ARIZONA_OUT1LMIX_INPUT_1_SOURCE          0x680
-#define ARIZONA_OUT1LMIX_INPUT_1_VOLUME          0x681
-#define ARIZONA_OUT1LMIX_INPUT_2_SOURCE          0x682
-#define ARIZONA_OUT1LMIX_INPUT_2_VOLUME          0x683
-#define ARIZONA_OUT1LMIX_INPUT_3_SOURCE          0x684
-#define ARIZONA_OUT1LMIX_INPUT_3_VOLUME          0x685
-#define ARIZONA_OUT1LMIX_INPUT_4_SOURCE          0x686
-#define ARIZONA_OUT1LMIX_INPUT_4_VOLUME          0x687
-#define ARIZONA_OUT1RMIX_INPUT_1_SOURCE          0x688
-#define ARIZONA_OUT1RMIX_INPUT_1_VOLUME          0x689
-#define ARIZONA_OUT1RMIX_INPUT_2_SOURCE          0x68A
-#define ARIZONA_OUT1RMIX_INPUT_2_VOLUME          0x68B
-#define ARIZONA_OUT1RMIX_INPUT_3_SOURCE          0x68C
-#define ARIZONA_OUT1RMIX_INPUT_3_VOLUME          0x68D
-#define ARIZONA_OUT1RMIX_INPUT_4_SOURCE          0x68E
-#define ARIZONA_OUT1RMIX_INPUT_4_VOLUME          0x68F
-#define ARIZONA_OUT2LMIX_INPUT_1_SOURCE          0x690
-#define ARIZONA_OUT2LMIX_INPUT_1_VOLUME          0x691
-#define ARIZONA_OUT2LMIX_INPUT_2_SOURCE          0x692
-#define ARIZONA_OUT2LMIX_INPUT_2_VOLUME          0x693
-#define ARIZONA_OUT2LMIX_INPUT_3_SOURCE          0x694
-#define ARIZONA_OUT2LMIX_INPUT_3_VOLUME          0x695
-#define ARIZONA_OUT2LMIX_INPUT_4_SOURCE          0x696
-#define ARIZONA_OUT2LMIX_INPUT_4_VOLUME          0x697
-#define ARIZONA_OUT2RMIX_INPUT_1_SOURCE          0x698
-#define ARIZONA_OUT2RMIX_INPUT_1_VOLUME          0x699
-#define ARIZONA_OUT2RMIX_INPUT_2_SOURCE          0x69A
-#define ARIZONA_OUT2RMIX_INPUT_2_VOLUME          0x69B
-#define ARIZONA_OUT2RMIX_INPUT_3_SOURCE          0x69C
-#define ARIZONA_OUT2RMIX_INPUT_3_VOLUME          0x69D
-#define ARIZONA_OUT2RMIX_INPUT_4_SOURCE          0x69E
-#define ARIZONA_OUT2RMIX_INPUT_4_VOLUME          0x69F
-#define ARIZONA_OUT3LMIX_INPUT_1_SOURCE          0x6A0
-#define ARIZONA_OUT3LMIX_INPUT_1_VOLUME          0x6A1
-#define ARIZONA_OUT3LMIX_INPUT_2_SOURCE          0x6A2
-#define ARIZONA_OUT3LMIX_INPUT_2_VOLUME          0x6A3
-#define ARIZONA_OUT3LMIX_INPUT_3_SOURCE          0x6A4
-#define ARIZONA_OUT3LMIX_INPUT_3_VOLUME          0x6A5
-#define ARIZONA_OUT3LMIX_INPUT_4_SOURCE          0x6A6
-#define ARIZONA_OUT3LMIX_INPUT_4_VOLUME          0x6A7
-#define ARIZONA_OUT3RMIX_INPUT_1_SOURCE          0x6A8
-#define ARIZONA_OUT3RMIX_INPUT_1_VOLUME          0x6A9
-#define ARIZONA_OUT3RMIX_INPUT_2_SOURCE          0x6AA
-#define ARIZONA_OUT3RMIX_INPUT_2_VOLUME          0x6AB
-#define ARIZONA_OUT3RMIX_INPUT_3_SOURCE          0x6AC
-#define ARIZONA_OUT3RMIX_INPUT_3_VOLUME          0x6AD
-#define ARIZONA_OUT3RMIX_INPUT_4_SOURCE          0x6AE
-#define ARIZONA_OUT3RMIX_INPUT_4_VOLUME          0x6AF
-#define ARIZONA_OUT4LMIX_INPUT_1_SOURCE          0x6B0
-#define ARIZONA_OUT4LMIX_INPUT_1_VOLUME          0x6B1
-#define ARIZONA_OUT4LMIX_INPUT_2_SOURCE          0x6B2
-#define ARIZONA_OUT4LMIX_INPUT_2_VOLUME          0x6B3
-#define ARIZONA_OUT4LMIX_INPUT_3_SOURCE          0x6B4
-#define ARIZONA_OUT4LMIX_INPUT_3_VOLUME          0x6B5
-#define ARIZONA_OUT4LMIX_INPUT_4_SOURCE          0x6B6
-#define ARIZONA_OUT4LMIX_INPUT_4_VOLUME          0x6B7
-#define ARIZONA_OUT4RMIX_INPUT_1_SOURCE          0x6B8
-#define ARIZONA_OUT4RMIX_INPUT_1_VOLUME          0x6B9
-#define ARIZONA_OUT4RMIX_INPUT_2_SOURCE          0x6BA
-#define ARIZONA_OUT4RMIX_INPUT_2_VOLUME          0x6BB
-#define ARIZONA_OUT4RMIX_INPUT_3_SOURCE          0x6BC
-#define ARIZONA_OUT4RMIX_INPUT_3_VOLUME          0x6BD
-#define ARIZONA_OUT4RMIX_INPUT_4_SOURCE          0x6BE
-#define ARIZONA_OUT4RMIX_INPUT_4_VOLUME          0x6BF
-#define ARIZONA_OUT5LMIX_INPUT_1_SOURCE          0x6C0
-#define ARIZONA_OUT5LMIX_INPUT_1_VOLUME          0x6C1
-#define ARIZONA_OUT5LMIX_INPUT_2_SOURCE          0x6C2
-#define ARIZONA_OUT5LMIX_INPUT_2_VOLUME          0x6C3
-#define ARIZONA_OUT5LMIX_INPUT_3_SOURCE          0x6C4
-#define ARIZONA_OUT5LMIX_INPUT_3_VOLUME          0x6C5
-#define ARIZONA_OUT5LMIX_INPUT_4_SOURCE          0x6C6
-#define ARIZONA_OUT5LMIX_INPUT_4_VOLUME          0x6C7
-#define ARIZONA_OUT5RMIX_INPUT_1_SOURCE          0x6C8
-#define ARIZONA_OUT5RMIX_INPUT_1_VOLUME          0x6C9
-#define ARIZONA_OUT5RMIX_INPUT_2_SOURCE          0x6CA
-#define ARIZONA_OUT5RMIX_INPUT_2_VOLUME          0x6CB
-#define ARIZONA_OUT5RMIX_INPUT_3_SOURCE          0x6CC
-#define ARIZONA_OUT5RMIX_INPUT_3_VOLUME          0x6CD
-#define ARIZONA_OUT5RMIX_INPUT_4_SOURCE          0x6CE
-#define ARIZONA_OUT5RMIX_INPUT_4_VOLUME          0x6CF
-#define ARIZONA_OUT6LMIX_INPUT_1_SOURCE          0x6D0
-#define ARIZONA_OUT6LMIX_INPUT_1_VOLUME          0x6D1
-#define ARIZONA_OUT6LMIX_INPUT_2_SOURCE          0x6D2
-#define ARIZONA_OUT6LMIX_INPUT_2_VOLUME          0x6D3
-#define ARIZONA_OUT6LMIX_INPUT_3_SOURCE          0x6D4
-#define ARIZONA_OUT6LMIX_INPUT_3_VOLUME          0x6D5
-#define ARIZONA_OUT6LMIX_INPUT_4_SOURCE          0x6D6
-#define ARIZONA_OUT6LMIX_INPUT_4_VOLUME          0x6D7
-#define ARIZONA_OUT6RMIX_INPUT_1_SOURCE          0x6D8
-#define ARIZONA_OUT6RMIX_INPUT_1_VOLUME          0x6D9
-#define ARIZONA_OUT6RMIX_INPUT_2_SOURCE          0x6DA
-#define ARIZONA_OUT6RMIX_INPUT_2_VOLUME          0x6DB
-#define ARIZONA_OUT6RMIX_INPUT_3_SOURCE          0x6DC
-#define ARIZONA_OUT6RMIX_INPUT_3_VOLUME          0x6DD
-#define ARIZONA_OUT6RMIX_INPUT_4_SOURCE          0x6DE
-#define ARIZONA_OUT6RMIX_INPUT_4_VOLUME          0x6DF
-#define ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE        0x700
-#define ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME        0x701
-#define ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE        0x702
-#define ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME        0x703
-#define ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE        0x704
-#define ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME        0x705
-#define ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE        0x706
-#define ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME        0x707
-#define ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE        0x708
-#define ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME        0x709
-#define ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE        0x70A
-#define ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME        0x70B
-#define ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE        0x70C
-#define ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME        0x70D
-#define ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE        0x70E
-#define ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME        0x70F
-#define ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE        0x710
-#define ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME        0x711
-#define ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE        0x712
-#define ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME        0x713
-#define ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE        0x714
-#define ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME        0x715
-#define ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE        0x716
-#define ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME        0x717
-#define ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE        0x718
-#define ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME        0x719
-#define ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE        0x71A
-#define ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME        0x71B
-#define ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE        0x71C
-#define ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME        0x71D
-#define ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE        0x71E
-#define ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME        0x71F
-#define ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE        0x720
-#define ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME        0x721
-#define ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE        0x722
-#define ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME        0x723
-#define ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE        0x724
-#define ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME        0x725
-#define ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE        0x726
-#define ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME        0x727
-#define ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE        0x728
-#define ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME        0x729
-#define ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE        0x72A
-#define ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME        0x72B
-#define ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE        0x72C
-#define ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME        0x72D
-#define ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE        0x72E
-#define ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME        0x72F
-#define ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE        0x730
-#define ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME        0x731
-#define ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE        0x732
-#define ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME        0x733
-#define ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE        0x734
-#define ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME        0x735
-#define ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE        0x736
-#define ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME        0x737
-#define ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE        0x738
-#define ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME        0x739
-#define ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE        0x73A
-#define ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME        0x73B
-#define ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE        0x73C
-#define ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME        0x73D
-#define ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE        0x73E
-#define ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME        0x73F
-#define ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE        0x740
-#define ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME        0x741
-#define ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE        0x742
-#define ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME        0x743
-#define ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE        0x744
-#define ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME        0x745
-#define ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE        0x746
-#define ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME        0x747
-#define ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE        0x748
-#define ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME        0x749
-#define ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE        0x74A
-#define ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME        0x74B
-#define ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE        0x74C
-#define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME        0x74D
-#define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE        0x74E
-#define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME        0x74F
-#define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE        0x780
-#define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME        0x781
-#define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE        0x782
-#define ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME        0x783
-#define ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE        0x784
-#define ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME        0x785
-#define ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE        0x786
-#define ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME        0x787
-#define ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE        0x788
-#define ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME        0x789
-#define ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE        0x78A
-#define ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME        0x78B
-#define ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE        0x78C
-#define ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME        0x78D
-#define ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE        0x78E
-#define ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME        0x78F
-#define ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE        0x7C0
-#define ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME        0x7C1
-#define ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE        0x7C2
-#define ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME        0x7C3
-#define ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE        0x7C4
-#define ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME        0x7C5
-#define ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE        0x7C6
-#define ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME        0x7C7
-#define ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE        0x7C8
-#define ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME        0x7C9
-#define ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE        0x7CA
-#define ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME        0x7CB
-#define ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE        0x7CC
-#define ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME        0x7CD
-#define ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE        0x7CE
-#define ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME        0x7CF
-#define ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE        0x7D0
-#define ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME        0x7D1
-#define ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE        0x7D2
-#define ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME        0x7D3
-#define ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE        0x7D4
-#define ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME        0x7D5
-#define ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE        0x7D6
-#define ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME        0x7D7
-#define ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE        0x7D8
-#define ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME        0x7D9
-#define ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE        0x7DA
-#define ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME        0x7DB
-#define ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE        0x7DC
-#define ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME        0x7DD
-#define ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE        0x7DE
-#define ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME        0x7DF
-#define ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE        0x7E0
-#define ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME        0x7E1
-#define ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE        0x7E2
-#define ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME        0x7E3
-#define ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE        0x7E4
-#define ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME        0x7E5
-#define ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE        0x7E6
-#define ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME        0x7E7
-#define ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE        0x7E8
-#define ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME        0x7E9
-#define ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE        0x7EA
-#define ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME        0x7EB
-#define ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE        0x7EC
-#define ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME        0x7ED
-#define ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE        0x7EE
-#define ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME        0x7EF
-#define ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE        0x7F0
-#define ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME        0x7F1
-#define ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE        0x7F2
-#define ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME        0x7F3
-#define ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE        0x7F4
-#define ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME        0x7F5
-#define ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE        0x7F6
-#define ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME        0x7F7
-#define ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE        0x7F8
-#define ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME        0x7F9
-#define ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE        0x7FA
-#define ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME        0x7FB
-#define ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE        0x7FC
-#define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME        0x7FD
-#define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE        0x7FE
-#define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME        0x7FF
-#define ARIZONA_EQ1MIX_INPUT_1_SOURCE            0x880
-#define ARIZONA_EQ1MIX_INPUT_1_VOLUME            0x881
-#define ARIZONA_EQ1MIX_INPUT_2_SOURCE            0x882
-#define ARIZONA_EQ1MIX_INPUT_2_VOLUME            0x883
-#define ARIZONA_EQ1MIX_INPUT_3_SOURCE            0x884
-#define ARIZONA_EQ1MIX_INPUT_3_VOLUME            0x885
-#define ARIZONA_EQ1MIX_INPUT_4_SOURCE            0x886
-#define ARIZONA_EQ1MIX_INPUT_4_VOLUME            0x887
-#define ARIZONA_EQ2MIX_INPUT_1_SOURCE            0x888
-#define ARIZONA_EQ2MIX_INPUT_1_VOLUME            0x889
-#define ARIZONA_EQ2MIX_INPUT_2_SOURCE            0x88A
-#define ARIZONA_EQ2MIX_INPUT_2_VOLUME            0x88B
-#define ARIZONA_EQ2MIX_INPUT_3_SOURCE            0x88C
-#define ARIZONA_EQ2MIX_INPUT_3_VOLUME            0x88D
-#define ARIZONA_EQ2MIX_INPUT_4_SOURCE            0x88E
-#define ARIZONA_EQ2MIX_INPUT_4_VOLUME            0x88F
-#define ARIZONA_EQ3MIX_INPUT_1_SOURCE            0x890
-#define ARIZONA_EQ3MIX_INPUT_1_VOLUME            0x891
-#define ARIZONA_EQ3MIX_INPUT_2_SOURCE            0x892
-#define ARIZONA_EQ3MIX_INPUT_2_VOLUME            0x893
-#define ARIZONA_EQ3MIX_INPUT_3_SOURCE            0x894
-#define ARIZONA_EQ3MIX_INPUT_3_VOLUME            0x895
-#define ARIZONA_EQ3MIX_INPUT_4_SOURCE            0x896
-#define ARIZONA_EQ3MIX_INPUT_4_VOLUME            0x897
-#define ARIZONA_EQ4MIX_INPUT_1_SOURCE            0x898
-#define ARIZONA_EQ4MIX_INPUT_1_VOLUME            0x899
-#define ARIZONA_EQ4MIX_INPUT_2_SOURCE            0x89A
-#define ARIZONA_EQ4MIX_INPUT_2_VOLUME            0x89B
-#define ARIZONA_EQ4MIX_INPUT_3_SOURCE            0x89C
-#define ARIZONA_EQ4MIX_INPUT_3_VOLUME            0x89D
-#define ARIZONA_EQ4MIX_INPUT_4_SOURCE            0x89E
-#define ARIZONA_EQ4MIX_INPUT_4_VOLUME            0x89F
-#define ARIZONA_DRC1LMIX_INPUT_1_SOURCE          0x8C0
-#define ARIZONA_DRC1LMIX_INPUT_1_VOLUME          0x8C1
-#define ARIZONA_DRC1LMIX_INPUT_2_SOURCE          0x8C2
-#define ARIZONA_DRC1LMIX_INPUT_2_VOLUME          0x8C3
-#define ARIZONA_DRC1LMIX_INPUT_3_SOURCE          0x8C4
-#define ARIZONA_DRC1LMIX_INPUT_3_VOLUME          0x8C5
-#define ARIZONA_DRC1LMIX_INPUT_4_SOURCE          0x8C6
-#define ARIZONA_DRC1LMIX_INPUT_4_VOLUME          0x8C7
-#define ARIZONA_DRC1RMIX_INPUT_1_SOURCE          0x8C8
-#define ARIZONA_DRC1RMIX_INPUT_1_VOLUME          0x8C9
-#define ARIZONA_DRC1RMIX_INPUT_2_SOURCE          0x8CA
-#define ARIZONA_DRC1RMIX_INPUT_2_VOLUME          0x8CB
-#define ARIZONA_DRC1RMIX_INPUT_3_SOURCE          0x8CC
-#define ARIZONA_DRC1RMIX_INPUT_3_VOLUME          0x8CD
-#define ARIZONA_DRC1RMIX_INPUT_4_SOURCE          0x8CE
-#define ARIZONA_DRC1RMIX_INPUT_4_VOLUME          0x8CF
-#define ARIZONA_DRC2LMIX_INPUT_1_SOURCE          0x8D0
-#define ARIZONA_DRC2LMIX_INPUT_1_VOLUME          0x8D1
-#define ARIZONA_DRC2LMIX_INPUT_2_SOURCE          0x8D2
-#define ARIZONA_DRC2LMIX_INPUT_2_VOLUME          0x8D3
-#define ARIZONA_DRC2LMIX_INPUT_3_SOURCE          0x8D4
-#define ARIZONA_DRC2LMIX_INPUT_3_VOLUME          0x8D5
-#define ARIZONA_DRC2LMIX_INPUT_4_SOURCE          0x8D6
-#define ARIZONA_DRC2LMIX_INPUT_4_VOLUME          0x8D7
-#define ARIZONA_DRC2RMIX_INPUT_1_SOURCE          0x8D8
-#define ARIZONA_DRC2RMIX_INPUT_1_VOLUME          0x8D9
-#define ARIZONA_DRC2RMIX_INPUT_2_SOURCE          0x8DA
-#define ARIZONA_DRC2RMIX_INPUT_2_VOLUME          0x8DB
-#define ARIZONA_DRC2RMIX_INPUT_3_SOURCE          0x8DC
-#define ARIZONA_DRC2RMIX_INPUT_3_VOLUME          0x8DD
-#define ARIZONA_DRC2RMIX_INPUT_4_SOURCE          0x8DE
-#define ARIZONA_DRC2RMIX_INPUT_4_VOLUME          0x8DF
-#define ARIZONA_HPLP1MIX_INPUT_1_SOURCE          0x900
-#define ARIZONA_HPLP1MIX_INPUT_1_VOLUME          0x901
-#define ARIZONA_HPLP1MIX_INPUT_2_SOURCE          0x902
-#define ARIZONA_HPLP1MIX_INPUT_2_VOLUME          0x903
-#define ARIZONA_HPLP1MIX_INPUT_3_SOURCE          0x904
-#define ARIZONA_HPLP1MIX_INPUT_3_VOLUME          0x905
-#define ARIZONA_HPLP1MIX_INPUT_4_SOURCE          0x906
-#define ARIZONA_HPLP1MIX_INPUT_4_VOLUME          0x907
-#define ARIZONA_HPLP2MIX_INPUT_1_SOURCE          0x908
-#define ARIZONA_HPLP2MIX_INPUT_1_VOLUME          0x909
-#define ARIZONA_HPLP2MIX_INPUT_2_SOURCE          0x90A
-#define ARIZONA_HPLP2MIX_INPUT_2_VOLUME          0x90B
-#define ARIZONA_HPLP2MIX_INPUT_3_SOURCE          0x90C
-#define ARIZONA_HPLP2MIX_INPUT_3_VOLUME          0x90D
-#define ARIZONA_HPLP2MIX_INPUT_4_SOURCE          0x90E
-#define ARIZONA_HPLP2MIX_INPUT_4_VOLUME          0x90F
-#define ARIZONA_HPLP3MIX_INPUT_1_SOURCE          0x910
-#define ARIZONA_HPLP3MIX_INPUT_1_VOLUME          0x911
-#define ARIZONA_HPLP3MIX_INPUT_2_SOURCE          0x912
-#define ARIZONA_HPLP3MIX_INPUT_2_VOLUME          0x913
-#define ARIZONA_HPLP3MIX_INPUT_3_SOURCE          0x914
-#define ARIZONA_HPLP3MIX_INPUT_3_VOLUME          0x915
-#define ARIZONA_HPLP3MIX_INPUT_4_SOURCE          0x916
-#define ARIZONA_HPLP3MIX_INPUT_4_VOLUME          0x917
-#define ARIZONA_HPLP4MIX_INPUT_1_SOURCE          0x918
-#define ARIZONA_HPLP4MIX_INPUT_1_VOLUME          0x919
-#define ARIZONA_HPLP4MIX_INPUT_2_SOURCE          0x91A
-#define ARIZONA_HPLP4MIX_INPUT_2_VOLUME          0x91B
-#define ARIZONA_HPLP4MIX_INPUT_3_SOURCE          0x91C
-#define ARIZONA_HPLP4MIX_INPUT_3_VOLUME          0x91D
-#define ARIZONA_HPLP4MIX_INPUT_4_SOURCE          0x91E
-#define ARIZONA_HPLP4MIX_INPUT_4_VOLUME          0x91F
-#define ARIZONA_DSP1LMIX_INPUT_1_SOURCE          0x940
-#define ARIZONA_DSP1LMIX_INPUT_1_VOLUME          0x941
-#define ARIZONA_DSP1LMIX_INPUT_2_SOURCE          0x942
-#define ARIZONA_DSP1LMIX_INPUT_2_VOLUME          0x943
-#define ARIZONA_DSP1LMIX_INPUT_3_SOURCE          0x944
-#define ARIZONA_DSP1LMIX_INPUT_3_VOLUME          0x945
-#define ARIZONA_DSP1LMIX_INPUT_4_SOURCE          0x946
-#define ARIZONA_DSP1LMIX_INPUT_4_VOLUME          0x947
-#define ARIZONA_DSP1RMIX_INPUT_1_SOURCE          0x948
-#define ARIZONA_DSP1RMIX_INPUT_1_VOLUME          0x949
-#define ARIZONA_DSP1RMIX_INPUT_2_SOURCE          0x94A
-#define ARIZONA_DSP1RMIX_INPUT_2_VOLUME          0x94B
-#define ARIZONA_DSP1RMIX_INPUT_3_SOURCE          0x94C
-#define ARIZONA_DSP1RMIX_INPUT_3_VOLUME          0x94D
-#define ARIZONA_DSP1RMIX_INPUT_4_SOURCE          0x94E
-#define ARIZONA_DSP1RMIX_INPUT_4_VOLUME          0x94F
-#define ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE       0x950
-#define ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE       0x958
-#define ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE       0x960
-#define ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE       0x968
-#define ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE       0x970
-#define ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE       0x978
-#define ARIZONA_DSP2LMIX_INPUT_1_SOURCE          0x980
-#define ARIZONA_DSP2LMIX_INPUT_1_VOLUME          0x981
-#define ARIZONA_DSP2LMIX_INPUT_2_SOURCE          0x982
-#define ARIZONA_DSP2LMIX_INPUT_2_VOLUME          0x983
-#define ARIZONA_DSP2LMIX_INPUT_3_SOURCE          0x984
-#define ARIZONA_DSP2LMIX_INPUT_3_VOLUME          0x985
-#define ARIZONA_DSP2LMIX_INPUT_4_SOURCE          0x986
-#define ARIZONA_DSP2LMIX_INPUT_4_VOLUME          0x987
-#define ARIZONA_DSP2RMIX_INPUT_1_SOURCE          0x988
-#define ARIZONA_DSP2RMIX_INPUT_1_VOLUME          0x989
-#define ARIZONA_DSP2RMIX_INPUT_2_SOURCE          0x98A
-#define ARIZONA_DSP2RMIX_INPUT_2_VOLUME          0x98B
-#define ARIZONA_DSP2RMIX_INPUT_3_SOURCE          0x98C
-#define ARIZONA_DSP2RMIX_INPUT_3_VOLUME          0x98D
-#define ARIZONA_DSP2RMIX_INPUT_4_SOURCE          0x98E
-#define ARIZONA_DSP2RMIX_INPUT_4_VOLUME          0x98F
-#define ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE       0x990
-#define ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE       0x998
-#define ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE       0x9A0
-#define ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE       0x9A8
-#define ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE       0x9B0
-#define ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE       0x9B8
-#define ARIZONA_DSP3LMIX_INPUT_1_SOURCE          0x9C0
-#define ARIZONA_DSP3LMIX_INPUT_1_VOLUME          0x9C1
-#define ARIZONA_DSP3LMIX_INPUT_2_SOURCE          0x9C2
-#define ARIZONA_DSP3LMIX_INPUT_2_VOLUME          0x9C3
-#define ARIZONA_DSP3LMIX_INPUT_3_SOURCE          0x9C4
-#define ARIZONA_DSP3LMIX_INPUT_3_VOLUME          0x9C5
-#define ARIZONA_DSP3LMIX_INPUT_4_SOURCE          0x9C6
-#define ARIZONA_DSP3LMIX_INPUT_4_VOLUME          0x9C7
-#define ARIZONA_DSP3RMIX_INPUT_1_SOURCE          0x9C8
-#define ARIZONA_DSP3RMIX_INPUT_1_VOLUME          0x9C9
-#define ARIZONA_DSP3RMIX_INPUT_2_SOURCE          0x9CA
-#define ARIZONA_DSP3RMIX_INPUT_2_VOLUME          0x9CB
-#define ARIZONA_DSP3RMIX_INPUT_3_SOURCE          0x9CC
-#define ARIZONA_DSP3RMIX_INPUT_3_VOLUME          0x9CD
-#define ARIZONA_DSP3RMIX_INPUT_4_SOURCE          0x9CE
-#define ARIZONA_DSP3RMIX_INPUT_4_VOLUME          0x9CF
-#define ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE       0x9D0
-#define ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE       0x9D8
-#define ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE       0x9E0
-#define ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE       0x9E8
-#define ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE       0x9F0
-#define ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE       0x9F8
-#define ARIZONA_DSP4LMIX_INPUT_1_SOURCE          0xA00
-#define ARIZONA_DSP4LMIX_INPUT_1_VOLUME          0xA01
-#define ARIZONA_DSP4LMIX_INPUT_2_SOURCE          0xA02
-#define ARIZONA_DSP4LMIX_INPUT_2_VOLUME          0xA03
-#define ARIZONA_DSP4LMIX_INPUT_3_SOURCE          0xA04
-#define ARIZONA_DSP4LMIX_INPUT_3_VOLUME          0xA05
-#define ARIZONA_DSP4LMIX_INPUT_4_SOURCE          0xA06
-#define ARIZONA_DSP4LMIX_INPUT_4_VOLUME          0xA07
-#define ARIZONA_DSP4RMIX_INPUT_1_SOURCE          0xA08
-#define ARIZONA_DSP4RMIX_INPUT_1_VOLUME          0xA09
-#define ARIZONA_DSP4RMIX_INPUT_2_SOURCE          0xA0A
-#define ARIZONA_DSP4RMIX_INPUT_2_VOLUME          0xA0B
-#define ARIZONA_DSP4RMIX_INPUT_3_SOURCE          0xA0C
-#define ARIZONA_DSP4RMIX_INPUT_3_VOLUME          0xA0D
-#define ARIZONA_DSP4RMIX_INPUT_4_SOURCE          0xA0E
-#define ARIZONA_DSP4RMIX_INPUT_4_VOLUME          0xA0F
-#define ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE       0xA10
-#define ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE       0xA18
-#define ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE       0xA20
-#define ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE       0xA28
-#define ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE       0xA30
-#define ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE       0xA38
-#define ARIZONA_ASRC1LMIX_INPUT_1_SOURCE         0xA80
-#define ARIZONA_ASRC1RMIX_INPUT_1_SOURCE         0xA88
-#define ARIZONA_ASRC2LMIX_INPUT_1_SOURCE         0xA90
-#define ARIZONA_ASRC2RMIX_INPUT_1_SOURCE         0xA98
-#define ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE      0xB00
-#define ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE      0xB08
-#define ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE      0xB10
-#define ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE      0xB18
-#define ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE      0xB20
-#define ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE      0xB28
-#define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE      0xB30
-#define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE      0xB38
-#define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE      0xB40
-#define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE      0xB48
-#define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE      0xB60
-#define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE      0xB68
-#define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE      0xB30
-#define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE      0xB38
-#define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE      0xB40
-#define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE      0xB48
-#define ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE      0xB50
-#define ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE      0xB58
-#define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE      0xB60
-#define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE      0xB68
-#define ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE      0xB70
-#define ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE      0xB78
-#define ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE      0xB80
-#define ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE      0xB88
-#define ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE      0xB90
-#define ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE      0xB98
-#define ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE      0xBA0
-#define ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE      0xBA8
-#define ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE      0xBB0
-#define ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE      0xBB8
-#define ARIZONA_GPIO1_CTRL                       0xC00
-#define ARIZONA_GPIO2_CTRL                       0xC01
-#define ARIZONA_GPIO3_CTRL                       0xC02
-#define ARIZONA_GPIO4_CTRL                       0xC03
-#define ARIZONA_GPIO5_CTRL                       0xC04
-#define ARIZONA_IRQ_CTRL_1                       0xC0F
-#define ARIZONA_GPIO_DEBOUNCE_CONFIG             0xC10
-#define ARIZONA_MISC_PAD_CTRL_1                  0xC20
-#define ARIZONA_MISC_PAD_CTRL_2                  0xC21
-#define ARIZONA_MISC_PAD_CTRL_3                  0xC22
-#define ARIZONA_MISC_PAD_CTRL_4                  0xC23
-#define ARIZONA_MISC_PAD_CTRL_5                  0xC24
-#define ARIZONA_MISC_PAD_CTRL_6                  0xC25
-#define ARIZONA_MISC_PAD_CTRL_7                  0xC30
-#define ARIZONA_MISC_PAD_CTRL_8                  0xC31
-#define ARIZONA_MISC_PAD_CTRL_9                  0xC32
-#define ARIZONA_MISC_PAD_CTRL_10                 0xC33
-#define ARIZONA_MISC_PAD_CTRL_11                 0xC34
-#define ARIZONA_MISC_PAD_CTRL_12                 0xC35
-#define ARIZONA_MISC_PAD_CTRL_13                 0xC36
-#define ARIZONA_MISC_PAD_CTRL_14                 0xC37
-#define ARIZONA_MISC_PAD_CTRL_15                 0xC38
-#define ARIZONA_MISC_PAD_CTRL_16                 0xC39
-#define ARIZONA_MISC_PAD_CTRL_17                 0xC3A
-#define ARIZONA_MISC_PAD_CTRL_18                 0xC3B
-#define ARIZONA_INTERRUPT_STATUS_1               0xD00
-#define ARIZONA_INTERRUPT_STATUS_2               0xD01
-#define ARIZONA_INTERRUPT_STATUS_3               0xD02
-#define ARIZONA_INTERRUPT_STATUS_4               0xD03
-#define ARIZONA_INTERRUPT_STATUS_5               0xD04
-#define ARIZONA_INTERRUPT_STATUS_1_MASK          0xD08
-#define ARIZONA_INTERRUPT_STATUS_2_MASK          0xD09
-#define ARIZONA_INTERRUPT_STATUS_3_MASK          0xD0A
-#define ARIZONA_INTERRUPT_STATUS_4_MASK          0xD0B
-#define ARIZONA_INTERRUPT_STATUS_5_MASK          0xD0C
-#define ARIZONA_INTERRUPT_CONTROL                0xD0F
-#define ARIZONA_IRQ2_STATUS_1                    0xD10
-#define ARIZONA_IRQ2_STATUS_2                    0xD11
-#define ARIZONA_IRQ2_STATUS_3                    0xD12
-#define ARIZONA_IRQ2_STATUS_4                    0xD13
-#define ARIZONA_IRQ2_STATUS_5                    0xD14
-#define ARIZONA_IRQ2_STATUS_1_MASK               0xD18
-#define ARIZONA_IRQ2_STATUS_2_MASK               0xD19
-#define ARIZONA_IRQ2_STATUS_3_MASK               0xD1A
-#define ARIZONA_IRQ2_STATUS_4_MASK               0xD1B
-#define ARIZONA_IRQ2_STATUS_5_MASK               0xD1C
-#define ARIZONA_IRQ2_CONTROL                     0xD1F
-#define ARIZONA_INTERRUPT_RAW_STATUS_2           0xD20
-#define ARIZONA_INTERRUPT_RAW_STATUS_3           0xD21
-#define ARIZONA_INTERRUPT_RAW_STATUS_4           0xD22
-#define ARIZONA_INTERRUPT_RAW_STATUS_5           0xD23
-#define ARIZONA_INTERRUPT_RAW_STATUS_6           0xD24
-#define ARIZONA_INTERRUPT_RAW_STATUS_7           0xD25
-#define ARIZONA_INTERRUPT_RAW_STATUS_8           0xD26
-#define ARIZONA_IRQ_PIN_STATUS                   0xD40
-#define ARIZONA_ADSP2_IRQ0                       0xD41
-#define ARIZONA_AOD_WKUP_AND_TRIG                0xD50
-#define ARIZONA_AOD_IRQ1                         0xD51
-#define ARIZONA_AOD_IRQ2                         0xD52
-#define ARIZONA_AOD_IRQ_MASK_IRQ1                0xD53
-#define ARIZONA_AOD_IRQ_MASK_IRQ2                0xD54
-#define ARIZONA_AOD_IRQ_RAW_STATUS               0xD55
-#define ARIZONA_JACK_DETECT_DEBOUNCE             0xD56
-#define ARIZONA_FX_CTRL1                         0xE00
-#define ARIZONA_FX_CTRL2                         0xE01
-#define ARIZONA_EQ1_1                            0xE10
-#define ARIZONA_EQ1_2                            0xE11
-#define ARIZONA_EQ1_3                            0xE12
-#define ARIZONA_EQ1_4                            0xE13
-#define ARIZONA_EQ1_5                            0xE14
-#define ARIZONA_EQ1_6                            0xE15
-#define ARIZONA_EQ1_7                            0xE16
-#define ARIZONA_EQ1_8                            0xE17
-#define ARIZONA_EQ1_9                            0xE18
-#define ARIZONA_EQ1_10                           0xE19
-#define ARIZONA_EQ1_11                           0xE1A
-#define ARIZONA_EQ1_12                           0xE1B
-#define ARIZONA_EQ1_13                           0xE1C
-#define ARIZONA_EQ1_14                           0xE1D
-#define ARIZONA_EQ1_15                           0xE1E
-#define ARIZONA_EQ1_16                           0xE1F
-#define ARIZONA_EQ1_17                           0xE20
-#define ARIZONA_EQ1_18                           0xE21
-#define ARIZONA_EQ1_19                           0xE22
-#define ARIZONA_EQ1_20                           0xE23
-#define ARIZONA_EQ1_21                           0xE24
-#define ARIZONA_EQ2_1                            0xE26
-#define ARIZONA_EQ2_2                            0xE27
-#define ARIZONA_EQ2_3                            0xE28
-#define ARIZONA_EQ2_4                            0xE29
-#define ARIZONA_EQ2_5                            0xE2A
-#define ARIZONA_EQ2_6                            0xE2B
-#define ARIZONA_EQ2_7                            0xE2C
-#define ARIZONA_EQ2_8                            0xE2D
-#define ARIZONA_EQ2_9                            0xE2E
-#define ARIZONA_EQ2_10                           0xE2F
-#define ARIZONA_EQ2_11                           0xE30
-#define ARIZONA_EQ2_12                           0xE31
-#define ARIZONA_EQ2_13                           0xE32
-#define ARIZONA_EQ2_14                           0xE33
-#define ARIZONA_EQ2_15                           0xE34
-#define ARIZONA_EQ2_16                           0xE35
-#define ARIZONA_EQ2_17                           0xE36
-#define ARIZONA_EQ2_18                           0xE37
-#define ARIZONA_EQ2_19                           0xE38
-#define ARIZONA_EQ2_20                           0xE39
-#define ARIZONA_EQ2_21                           0xE3A
-#define ARIZONA_EQ3_1                            0xE3C
-#define ARIZONA_EQ3_2                            0xE3D
-#define ARIZONA_EQ3_3                            0xE3E
-#define ARIZONA_EQ3_4                            0xE3F
-#define ARIZONA_EQ3_5                            0xE40
-#define ARIZONA_EQ3_6                            0xE41
-#define ARIZONA_EQ3_7                            0xE42
-#define ARIZONA_EQ3_8                            0xE43
-#define ARIZONA_EQ3_9                            0xE44
-#define ARIZONA_EQ3_10                           0xE45
-#define ARIZONA_EQ3_11                           0xE46
-#define ARIZONA_EQ3_12                           0xE47
-#define ARIZONA_EQ3_13                           0xE48
-#define ARIZONA_EQ3_14                           0xE49
-#define ARIZONA_EQ3_15                           0xE4A
-#define ARIZONA_EQ3_16                           0xE4B
-#define ARIZONA_EQ3_17                           0xE4C
-#define ARIZONA_EQ3_18                           0xE4D
-#define ARIZONA_EQ3_19                           0xE4E
-#define ARIZONA_EQ3_20                           0xE4F
-#define ARIZONA_EQ3_21                           0xE50
-#define ARIZONA_EQ4_1                            0xE52
-#define ARIZONA_EQ4_2                            0xE53
-#define ARIZONA_EQ4_3                            0xE54
-#define ARIZONA_EQ4_4                            0xE55
-#define ARIZONA_EQ4_5                            0xE56
-#define ARIZONA_EQ4_6                            0xE57
-#define ARIZONA_EQ4_7                            0xE58
-#define ARIZONA_EQ4_8                            0xE59
-#define ARIZONA_EQ4_9                            0xE5A
-#define ARIZONA_EQ4_10                           0xE5B
-#define ARIZONA_EQ4_11                           0xE5C
-#define ARIZONA_EQ4_12                           0xE5D
-#define ARIZONA_EQ4_13                           0xE5E
-#define ARIZONA_EQ4_14                           0xE5F
-#define ARIZONA_EQ4_15                           0xE60
-#define ARIZONA_EQ4_16                           0xE61
-#define ARIZONA_EQ4_17                           0xE62
-#define ARIZONA_EQ4_18                           0xE63
-#define ARIZONA_EQ4_19                           0xE64
-#define ARIZONA_EQ4_20                           0xE65
-#define ARIZONA_EQ4_21                           0xE66
-#define ARIZONA_DRC1_CTRL1                       0xE80
-#define ARIZONA_DRC1_CTRL2                       0xE81
-#define ARIZONA_DRC1_CTRL3                       0xE82
-#define ARIZONA_DRC1_CTRL4                       0xE83
-#define ARIZONA_DRC1_CTRL5                       0xE84
-#define ARIZONA_DRC2_CTRL1                       0xE89
-#define ARIZONA_DRC2_CTRL2                       0xE8A
-#define ARIZONA_DRC2_CTRL3                       0xE8B
-#define ARIZONA_DRC2_CTRL4                       0xE8C
-#define ARIZONA_DRC2_CTRL5                       0xE8D
-#define ARIZONA_HPLPF1_1                         0xEC0
-#define ARIZONA_HPLPF1_2                         0xEC1
-#define ARIZONA_HPLPF2_1                         0xEC4
-#define ARIZONA_HPLPF2_2                         0xEC5
-#define ARIZONA_HPLPF3_1                         0xEC8
-#define ARIZONA_HPLPF3_2                         0xEC9
-#define ARIZONA_HPLPF4_1                         0xECC
-#define ARIZONA_HPLPF4_2                         0xECD
-#define ARIZONA_ASRC_ENABLE                      0xEE0
-#define ARIZONA_ASRC_STATUS                      0xEE1
-#define ARIZONA_ASRC_RATE1                       0xEE2
-#define ARIZONA_ASRC_RATE2                       0xEE3
-#define ARIZONA_ISRC_1_CTRL_1                    0xEF0
-#define ARIZONA_ISRC_1_CTRL_2                    0xEF1
-#define ARIZONA_ISRC_1_CTRL_3                    0xEF2
-#define ARIZONA_ISRC_2_CTRL_1                    0xEF3
-#define ARIZONA_ISRC_2_CTRL_2                    0xEF4
-#define ARIZONA_ISRC_2_CTRL_3                    0xEF5
-#define ARIZONA_ISRC_3_CTRL_1                    0xEF6
-#define ARIZONA_ISRC_3_CTRL_2                    0xEF7
-#define ARIZONA_ISRC_3_CTRL_3                    0xEF8
-#define ARIZONA_CLOCK_CONTROL                    0xF00
-#define ARIZONA_ANC_SRC                          0xF01
-#define ARIZONA_DSP_STATUS                       0xF02
-#define ARIZONA_DSP1_CONTROL_1                   0x1100
-#define ARIZONA_DSP1_CLOCKING_1                  0x1101
-#define ARIZONA_DSP1_STATUS_1                    0x1104
-#define ARIZONA_DSP1_STATUS_2                    0x1105
-#define ARIZONA_DSP1_STATUS_3                    0x1106
-#define ARIZONA_DSP2_CONTROL_1                   0x1200
-#define ARIZONA_DSP2_CLOCKING_1                  0x1201
-#define ARIZONA_DSP2_STATUS_1                    0x1204
-#define ARIZONA_DSP2_STATUS_2                    0x1205
-#define ARIZONA_DSP3_CONTROL_1                   0x1300
-#define ARIZONA_DSP3_CLOCKING_1                  0x1301
-#define ARIZONA_DSP3_STATUS_1                    0x1304
-#define ARIZONA_DSP3_STATUS_2                    0x1305
-#define ARIZONA_DSP4_CONTROL_1                   0x1400
-#define ARIZONA_DSP4_CLOCKING_1                  0x1401
-#define ARIZONA_DSP4_STATUS_1                    0x1404
-#define ARIZONA_DSP4_STATUS_2                    0x1405
-
-/*
- * Field Definitions.
- */
-
-/*
- * R0 (0x00) - software reset
- */
-#define ARIZONA_SW_RST_DEV_ID1_MASK              0xFFFF  /* SW_RST_DEV_ID1 - [15:0] */
-#define ARIZONA_SW_RST_DEV_ID1_SHIFT                  0  /* SW_RST_DEV_ID1 - [15:0] */
-#define ARIZONA_SW_RST_DEV_ID1_WIDTH                 16  /* SW_RST_DEV_ID1 - [15:0] */
-
-/*
- * R1 (0x01) - Device Revision
- */
-#define ARIZONA_DEVICE_REVISION_MASK             0x00FF  /* DEVICE_REVISION - [7:0] */
-#define ARIZONA_DEVICE_REVISION_SHIFT                 0  /* DEVICE_REVISION - [7:0] */
-#define ARIZONA_DEVICE_REVISION_WIDTH                 8  /* DEVICE_REVISION - [7:0] */
-
-/*
- * R8 (0x08) - Ctrl IF SPI CFG 1
- */
-#define ARIZONA_SPI_CFG                          0x0010  /* SPI_CFG */
-#define ARIZONA_SPI_CFG_MASK                     0x0010  /* SPI_CFG */
-#define ARIZONA_SPI_CFG_SHIFT                         4  /* SPI_CFG */
-#define ARIZONA_SPI_CFG_WIDTH                         1  /* SPI_CFG */
-#define ARIZONA_SPI_4WIRE                        0x0008  /* SPI_4WIRE */
-#define ARIZONA_SPI_4WIRE_MASK                   0x0008  /* SPI_4WIRE */
-#define ARIZONA_SPI_4WIRE_SHIFT                       3  /* SPI_4WIRE */
-#define ARIZONA_SPI_4WIRE_WIDTH                       1  /* SPI_4WIRE */
-#define ARIZONA_SPI_AUTO_INC_MASK                0x0003  /* SPI_AUTO_INC - [1:0] */
-#define ARIZONA_SPI_AUTO_INC_SHIFT                    0  /* SPI_AUTO_INC - [1:0] */
-#define ARIZONA_SPI_AUTO_INC_WIDTH                    2  /* SPI_AUTO_INC - [1:0] */
-
-/*
- * R9 (0x09) - Ctrl IF I2C1 CFG 1
- */
-#define ARIZONA_I2C1_AUTO_INC_MASK               0x0003  /* I2C1_AUTO_INC - [1:0] */
-#define ARIZONA_I2C1_AUTO_INC_SHIFT                   0  /* I2C1_AUTO_INC - [1:0] */
-#define ARIZONA_I2C1_AUTO_INC_WIDTH                   2  /* I2C1_AUTO_INC - [1:0] */
-
-/*
- * R13 (0x0D) - Ctrl IF Status 1
- */
-#define ARIZONA_I2C1_BUSY                        0x0020  /* I2C1_BUSY */
-#define ARIZONA_I2C1_BUSY_MASK                   0x0020  /* I2C1_BUSY */
-#define ARIZONA_I2C1_BUSY_SHIFT                       5  /* I2C1_BUSY */
-#define ARIZONA_I2C1_BUSY_WIDTH                       1  /* I2C1_BUSY */
-#define ARIZONA_SPI_BUSY                         0x0010  /* SPI_BUSY */
-#define ARIZONA_SPI_BUSY_MASK                    0x0010  /* SPI_BUSY */
-#define ARIZONA_SPI_BUSY_SHIFT                        4  /* SPI_BUSY */
-#define ARIZONA_SPI_BUSY_WIDTH                        1  /* SPI_BUSY */
-
-/*
- * R22 (0x16) - Write Sequencer Ctrl 0
- */
-#define ARIZONA_WSEQ_ABORT                       0x0800  /* WSEQ_ABORT */
-#define ARIZONA_WSEQ_ABORT_MASK                  0x0800  /* WSEQ_ABORT */
-#define ARIZONA_WSEQ_ABORT_SHIFT                     11  /* WSEQ_ABORT */
-#define ARIZONA_WSEQ_ABORT_WIDTH                      1  /* WSEQ_ABORT */
-#define ARIZONA_WSEQ_START                       0x0400  /* WSEQ_START */
-#define ARIZONA_WSEQ_START_MASK                  0x0400  /* WSEQ_START */
-#define ARIZONA_WSEQ_START_SHIFT                     10  /* WSEQ_START */
-#define ARIZONA_WSEQ_START_WIDTH                      1  /* WSEQ_START */
-#define ARIZONA_WSEQ_ENA                         0x0200  /* WSEQ_ENA */
-#define ARIZONA_WSEQ_ENA_MASK                    0x0200  /* WSEQ_ENA */
-#define ARIZONA_WSEQ_ENA_SHIFT                        9  /* WSEQ_ENA */
-#define ARIZONA_WSEQ_ENA_WIDTH                        1  /* WSEQ_ENA */
-#define ARIZONA_WSEQ_START_INDEX_MASK            0x01FF  /* WSEQ_START_INDEX - [8:0] */
-#define ARIZONA_WSEQ_START_INDEX_SHIFT                0  /* WSEQ_START_INDEX - [8:0] */
-#define ARIZONA_WSEQ_START_INDEX_WIDTH                9  /* WSEQ_START_INDEX - [8:0] */
-
-/*
- * R23 (0x17) - Write Sequencer Ctrl 1
- */
-#define ARIZONA_WSEQ_BUSY                        0x0200  /* WSEQ_BUSY */
-#define ARIZONA_WSEQ_BUSY_MASK                   0x0200  /* WSEQ_BUSY */
-#define ARIZONA_WSEQ_BUSY_SHIFT                       9  /* WSEQ_BUSY */
-#define ARIZONA_WSEQ_BUSY_WIDTH                       1  /* WSEQ_BUSY */
-#define ARIZONA_WSEQ_CURRENT_INDEX_MASK          0x01FF  /* WSEQ_CURRENT_INDEX - [8:0] */
-#define ARIZONA_WSEQ_CURRENT_INDEX_SHIFT              0  /* WSEQ_CURRENT_INDEX - [8:0] */
-#define ARIZONA_WSEQ_CURRENT_INDEX_WIDTH              9  /* WSEQ_CURRENT_INDEX - [8:0] */
-
-/*
- * R24 (0x18) - Write Sequencer Ctrl 2
- */
-#define ARIZONA_LOAD_DEFAULTS                    0x0002  /* LOAD_DEFAULTS */
-#define ARIZONA_LOAD_DEFAULTS_MASK               0x0002  /* LOAD_DEFAULTS */
-#define ARIZONA_LOAD_DEFAULTS_SHIFT                   1  /* LOAD_DEFAULTS */
-#define ARIZONA_LOAD_DEFAULTS_WIDTH                   1  /* LOAD_DEFAULTS */
-#define ARIZONA_WSEQ_LOAD_MEM                    0x0001  /* WSEQ_LOAD_MEM */
-#define ARIZONA_WSEQ_LOAD_MEM_MASK               0x0001  /* WSEQ_LOAD_MEM */
-#define ARIZONA_WSEQ_LOAD_MEM_SHIFT                   0  /* WSEQ_LOAD_MEM */
-#define ARIZONA_WSEQ_LOAD_MEM_WIDTH                   1  /* WSEQ_LOAD_MEM */
-
-/*
- * R26 (0x1A) - Write Sequencer PROM
- */
-#define ARIZONA_WSEQ_OTP_WRITE                   0x0001  /* WSEQ_OTP_WRITE */
-#define ARIZONA_WSEQ_OTP_WRITE_MASK              0x0001  /* WSEQ_OTP_WRITE */
-#define ARIZONA_WSEQ_OTP_WRITE_SHIFT                  0  /* WSEQ_OTP_WRITE */
-#define ARIZONA_WSEQ_OTP_WRITE_WIDTH                  1  /* WSEQ_OTP_WRITE */
-
-/*
- * R32 (0x20) - Tone Generator 1
- */
-#define ARIZONA_TONE_RATE_MASK                   0x7800  /* TONE_RATE - [14:11] */
-#define ARIZONA_TONE_RATE_SHIFT                      11  /* TONE_RATE - [14:11] */
-#define ARIZONA_TONE_RATE_WIDTH                       4  /* TONE_RATE - [14:11] */
-#define ARIZONA_TONE_OFFSET_MASK                 0x0300  /* TONE_OFFSET - [9:8] */
-#define ARIZONA_TONE_OFFSET_SHIFT                     8  /* TONE_OFFSET - [9:8] */
-#define ARIZONA_TONE_OFFSET_WIDTH                     2  /* TONE_OFFSET - [9:8] */
-#define ARIZONA_TONE2_OVD                        0x0020  /* TONE2_OVD */
-#define ARIZONA_TONE2_OVD_MASK                   0x0020  /* TONE2_OVD */
-#define ARIZONA_TONE2_OVD_SHIFT                       5  /* TONE2_OVD */
-#define ARIZONA_TONE2_OVD_WIDTH                       1  /* TONE2_OVD */
-#define ARIZONA_TONE1_OVD                        0x0010  /* TONE1_OVD */
-#define ARIZONA_TONE1_OVD_MASK                   0x0010  /* TONE1_OVD */
-#define ARIZONA_TONE1_OVD_SHIFT                       4  /* TONE1_OVD */
-#define ARIZONA_TONE1_OVD_WIDTH                       1  /* TONE1_OVD */
-#define ARIZONA_TONE2_ENA                        0x0002  /* TONE2_ENA */
-#define ARIZONA_TONE2_ENA_MASK                   0x0002  /* TONE2_ENA */
-#define ARIZONA_TONE2_ENA_SHIFT                       1  /* TONE2_ENA */
-#define ARIZONA_TONE2_ENA_WIDTH                       1  /* TONE2_ENA */
-#define ARIZONA_TONE1_ENA                        0x0001  /* TONE1_ENA */
-#define ARIZONA_TONE1_ENA_MASK                   0x0001  /* TONE1_ENA */
-#define ARIZONA_TONE1_ENA_SHIFT                       0  /* TONE1_ENA */
-#define ARIZONA_TONE1_ENA_WIDTH                       1  /* TONE1_ENA */
-
-/*
- * R33 (0x21) - Tone Generator 2
- */
-#define ARIZONA_TONE1_LVL_0_MASK                 0xFFFF  /* TONE1_LVL - [15:0] */
-#define ARIZONA_TONE1_LVL_0_SHIFT                     0  /* TONE1_LVL - [15:0] */
-#define ARIZONA_TONE1_LVL_0_WIDTH                    16  /* TONE1_LVL - [15:0] */
-
-/*
- * R34 (0x22) - Tone Generator 3
- */
-#define ARIZONA_TONE1_LVL_MASK                   0x00FF  /* TONE1_LVL - [7:0] */
-#define ARIZONA_TONE1_LVL_SHIFT                       0  /* TONE1_LVL - [7:0] */
-#define ARIZONA_TONE1_LVL_WIDTH                       8  /* TONE1_LVL - [7:0] */
-
-/*
- * R35 (0x23) - Tone Generator 4
- */
-#define ARIZONA_TONE2_LVL_0_MASK                 0xFFFF  /* TONE2_LVL - [15:0] */
-#define ARIZONA_TONE2_LVL_0_SHIFT                     0  /* TONE2_LVL - [15:0] */
-#define ARIZONA_TONE2_LVL_0_WIDTH                    16  /* TONE2_LVL - [15:0] */
-
-/*
- * R36 (0x24) - Tone Generator 5
- */
-#define ARIZONA_TONE2_LVL_MASK                   0x00FF  /* TONE2_LVL - [7:0] */
-#define ARIZONA_TONE2_LVL_SHIFT                       0  /* TONE2_LVL - [7:0] */
-#define ARIZONA_TONE2_LVL_WIDTH                       8  /* TONE2_LVL - [7:0] */
-
-/*
- * R48 (0x30) - PWM Drive 1
- */
-#define ARIZONA_PWM_RATE_MASK                    0x7800  /* PWM_RATE - [14:11] */
-#define ARIZONA_PWM_RATE_SHIFT                       11  /* PWM_RATE - [14:11] */
-#define ARIZONA_PWM_RATE_WIDTH                        4  /* PWM_RATE - [14:11] */
-#define ARIZONA_PWM_CLK_SEL_MASK                 0x0700  /* PWM_CLK_SEL - [10:8] */
-#define ARIZONA_PWM_CLK_SEL_SHIFT                     8  /* PWM_CLK_SEL - [10:8] */
-#define ARIZONA_PWM_CLK_SEL_WIDTH                     3  /* PWM_CLK_SEL - [10:8] */
-#define ARIZONA_PWM2_OVD                         0x0020  /* PWM2_OVD */
-#define ARIZONA_PWM2_OVD_MASK                    0x0020  /* PWM2_OVD */
-#define ARIZONA_PWM2_OVD_SHIFT                        5  /* PWM2_OVD */
-#define ARIZONA_PWM2_OVD_WIDTH                        1  /* PWM2_OVD */
-#define ARIZONA_PWM1_OVD                         0x0010  /* PWM1_OVD */
-#define ARIZONA_PWM1_OVD_MASK                    0x0010  /* PWM1_OVD */
-#define ARIZONA_PWM1_OVD_SHIFT                        4  /* PWM1_OVD */
-#define ARIZONA_PWM1_OVD_WIDTH                        1  /* PWM1_OVD */
-#define ARIZONA_PWM2_ENA                         0x0002  /* PWM2_ENA */
-#define ARIZONA_PWM2_ENA_MASK                    0x0002  /* PWM2_ENA */
-#define ARIZONA_PWM2_ENA_SHIFT                        1  /* PWM2_ENA */
-#define ARIZONA_PWM2_ENA_WIDTH                        1  /* PWM2_ENA */
-#define ARIZONA_PWM1_ENA                         0x0001  /* PWM1_ENA */
-#define ARIZONA_PWM1_ENA_MASK                    0x0001  /* PWM1_ENA */
-#define ARIZONA_PWM1_ENA_SHIFT                        0  /* PWM1_ENA */
-#define ARIZONA_PWM1_ENA_WIDTH                        1  /* PWM1_ENA */
-
-/*
- * R49 (0x31) - PWM Drive 2
- */
-#define ARIZONA_PWM1_LVL_MASK                    0x03FF  /* PWM1_LVL - [9:0] */
-#define ARIZONA_PWM1_LVL_SHIFT                        0  /* PWM1_LVL - [9:0] */
-#define ARIZONA_PWM1_LVL_WIDTH                       10  /* PWM1_LVL - [9:0] */
-
-/*
- * R50 (0x32) - PWM Drive 3
- */
-#define ARIZONA_PWM2_LVL_MASK                    0x03FF  /* PWM2_LVL - [9:0] */
-#define ARIZONA_PWM2_LVL_SHIFT                        0  /* PWM2_LVL - [9:0] */
-#define ARIZONA_PWM2_LVL_WIDTH                       10  /* PWM2_LVL - [9:0] */
-
-/*
- * R64 (0x40) - Wake control
- */
-#define ARIZONA_WKUP_GP5_FALL                    0x0020  /* WKUP_GP5_FALL */
-#define ARIZONA_WKUP_GP5_FALL_MASK               0x0020  /* WKUP_GP5_FALL */
-#define ARIZONA_WKUP_GP5_FALL_SHIFT                   5  /* WKUP_GP5_FALL */
-#define ARIZONA_WKUP_GP5_FALL_WIDTH                   1  /* WKUP_GP5_FALL */
-#define ARIZONA_WKUP_GP5_RISE                    0x0010  /* WKUP_GP5_RISE */
-#define ARIZONA_WKUP_GP5_RISE_MASK               0x0010  /* WKUP_GP5_RISE */
-#define ARIZONA_WKUP_GP5_RISE_SHIFT                   4  /* WKUP_GP5_RISE */
-#define ARIZONA_WKUP_GP5_RISE_WIDTH                   1  /* WKUP_GP5_RISE */
-#define ARIZONA_WKUP_JD1_FALL                    0x0008  /* WKUP_JD1_FALL */
-#define ARIZONA_WKUP_JD1_FALL_MASK               0x0008  /* WKUP_JD1_FALL */
-#define ARIZONA_WKUP_JD1_FALL_SHIFT                   3  /* WKUP_JD1_FALL */
-#define ARIZONA_WKUP_JD1_FALL_WIDTH                   1  /* WKUP_JD1_FALL */
-#define ARIZONA_WKUP_JD1_RISE                    0x0004  /* WKUP_JD1_RISE */
-#define ARIZONA_WKUP_JD1_RISE_MASK               0x0004  /* WKUP_JD1_RISE */
-#define ARIZONA_WKUP_JD1_RISE_SHIFT                   2  /* WKUP_JD1_RISE */
-#define ARIZONA_WKUP_JD1_RISE_WIDTH                   1  /* WKUP_JD1_RISE */
-#define ARIZONA_WKUP_JD2_FALL                    0x0002  /* WKUP_JD2_FALL */
-#define ARIZONA_WKUP_JD2_FALL_MASK               0x0002  /* WKUP_JD2_FALL */
-#define ARIZONA_WKUP_JD2_FALL_SHIFT                   1  /* WKUP_JD2_FALL */
-#define ARIZONA_WKUP_JD2_FALL_WIDTH                   1  /* WKUP_JD2_FALL */
-#define ARIZONA_WKUP_JD2_RISE                    0x0001  /* WKUP_JD2_RISE */
-#define ARIZONA_WKUP_JD2_RISE_MASK               0x0001  /* WKUP_JD2_RISE */
-#define ARIZONA_WKUP_JD2_RISE_SHIFT                   0  /* WKUP_JD2_RISE */
-#define ARIZONA_WKUP_JD2_RISE_WIDTH                   1  /* WKUP_JD2_RISE */
-
-/*
- * R65 (0x41) - Sequence control
- */
-#define ARIZONA_WSEQ_ENA_GP5_FALL                0x0020  /* WSEQ_ENA_GP5_FALL */
-#define ARIZONA_WSEQ_ENA_GP5_FALL_MASK           0x0020  /* WSEQ_ENA_GP5_FALL */
-#define ARIZONA_WSEQ_ENA_GP5_FALL_SHIFT               5  /* WSEQ_ENA_GP5_FALL */
-#define ARIZONA_WSEQ_ENA_GP5_FALL_WIDTH               1  /* WSEQ_ENA_GP5_FALL */
-#define ARIZONA_WSEQ_ENA_GP5_RISE                0x0010  /* WSEQ_ENA_GP5_RISE */
-#define ARIZONA_WSEQ_ENA_GP5_RISE_MASK           0x0010  /* WSEQ_ENA_GP5_RISE */
-#define ARIZONA_WSEQ_ENA_GP5_RISE_SHIFT               4  /* WSEQ_ENA_GP5_RISE */
-#define ARIZONA_WSEQ_ENA_GP5_RISE_WIDTH               1  /* WSEQ_ENA_GP5_RISE */
-#define ARIZONA_WSEQ_ENA_JD1_FALL                0x0008  /* WSEQ_ENA_JD1_FALL */
-#define ARIZONA_WSEQ_ENA_JD1_FALL_MASK           0x0008  /* WSEQ_ENA_JD1_FALL */
-#define ARIZONA_WSEQ_ENA_JD1_FALL_SHIFT               3  /* WSEQ_ENA_JD1_FALL */
-#define ARIZONA_WSEQ_ENA_JD1_FALL_WIDTH               1  /* WSEQ_ENA_JD1_FALL */
-#define ARIZONA_WSEQ_ENA_JD1_RISE                0x0004  /* WSEQ_ENA_JD1_RISE */
-#define ARIZONA_WSEQ_ENA_JD1_RISE_MASK           0x0004  /* WSEQ_ENA_JD1_RISE */
-#define ARIZONA_WSEQ_ENA_JD1_RISE_SHIFT               2  /* WSEQ_ENA_JD1_RISE */
-#define ARIZONA_WSEQ_ENA_JD1_RISE_WIDTH               1  /* WSEQ_ENA_JD1_RISE */
-#define ARIZONA_WSEQ_ENA_JD2_FALL                0x0002  /* WSEQ_ENA_JD2_FALL */
-#define ARIZONA_WSEQ_ENA_JD2_FALL_MASK           0x0002  /* WSEQ_ENA_JD2_FALL */
-#define ARIZONA_WSEQ_ENA_JD2_FALL_SHIFT               1  /* WSEQ_ENA_JD2_FALL */
-#define ARIZONA_WSEQ_ENA_JD2_FALL_WIDTH               1  /* WSEQ_ENA_JD2_FALL */
-#define ARIZONA_WSEQ_ENA_JD2_RISE                0x0001  /* WSEQ_ENA_JD2_RISE */
-#define ARIZONA_WSEQ_ENA_JD2_RISE_MASK           0x0001  /* WSEQ_ENA_JD2_RISE */
-#define ARIZONA_WSEQ_ENA_JD2_RISE_SHIFT               0  /* WSEQ_ENA_JD2_RISE */
-#define ARIZONA_WSEQ_ENA_JD2_RISE_WIDTH               1  /* WSEQ_ENA_JD2_RISE */
-
-/*
- * R97 (0x61) - Sample Rate Sequence Select 1
- */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_MASK 0x01FF  /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_SHIFT      0  /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_WIDTH      9  /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
-
-/*
- * R98 (0x62) - Sample Rate Sequence Select 2
- */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_MASK 0x01FF  /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_SHIFT      0  /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_WIDTH      9  /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
-
-/*
- * R99 (0x63) - Sample Rate Sequence Select 3
- */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_MASK 0x01FF  /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_SHIFT      0  /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_WIDTH      9  /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
-
-/*
- * R100 (0x64) - Sample Rate Sequence Select 4
- */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_MASK 0x01FF  /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_SHIFT      0  /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_WIDTH      9  /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
-
-/*
- * R104 (0x68) - Always On Triggers Sequence Select 1
- */
-#define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_MASK      0x01FF  /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_SHIFT          0  /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_WIDTH          9  /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
-
-/*
- * R105 (0x69) - Always On Triggers Sequence Select 2
- */
-#define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_MASK      0x01FF  /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_SHIFT          0  /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_WIDTH          9  /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
-
-/*
- * R106 (0x6A) - Always On Triggers Sequence Select 3
- */
-#define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_MASK      0x01FF  /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_SHIFT          0  /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_WIDTH          9  /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
-
-/*
- * R107 (0x6B) - Always On Triggers Sequence Select 4
- */
-#define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_MASK      0x01FF  /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_SHIFT          0  /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_WIDTH          9  /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
-
-/*
- * R108 (0x6C) - Always On Triggers Sequence Select 5
- */
-#define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_MASK      0x01FF  /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_SHIFT          0  /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_WIDTH          9  /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
-
-/*
- * R109 (0x6D) - Always On Triggers Sequence Select 6
- */
-#define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_MASK      0x01FF  /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_SHIFT          0  /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
-#define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_WIDTH          9  /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
-
-/*
- * R112 (0x70) - Comfort Noise Generator
- */
-#define ARIZONA_NOISE_GEN_RATE_MASK              0x7800  /* NOISE_GEN_RATE - [14:11] */
-#define ARIZONA_NOISE_GEN_RATE_SHIFT                 11  /* NOISE_GEN_RATE - [14:11] */
-#define ARIZONA_NOISE_GEN_RATE_WIDTH                  4  /* NOISE_GEN_RATE - [14:11] */
-#define ARIZONA_NOISE_GEN_ENA                    0x0020  /* NOISE_GEN_ENA */
-#define ARIZONA_NOISE_GEN_ENA_MASK               0x0020  /* NOISE_GEN_ENA */
-#define ARIZONA_NOISE_GEN_ENA_SHIFT                   5  /* NOISE_GEN_ENA */
-#define ARIZONA_NOISE_GEN_ENA_WIDTH                   1  /* NOISE_GEN_ENA */
-#define ARIZONA_NOISE_GEN_GAIN_MASK              0x001F  /* NOISE_GEN_GAIN - [4:0] */
-#define ARIZONA_NOISE_GEN_GAIN_SHIFT                  0  /* NOISE_GEN_GAIN - [4:0] */
-#define ARIZONA_NOISE_GEN_GAIN_WIDTH                  5  /* NOISE_GEN_GAIN - [4:0] */
-
-/*
- * R144 (0x90) - Haptics Control 1
- */
-#define ARIZONA_HAP_RATE_MASK                    0x7800  /* HAP_RATE - [14:11] */
-#define ARIZONA_HAP_RATE_SHIFT                       11  /* HAP_RATE - [14:11] */
-#define ARIZONA_HAP_RATE_WIDTH                        4  /* HAP_RATE - [14:11] */
-#define ARIZONA_ONESHOT_TRIG                     0x0010  /* ONESHOT_TRIG */
-#define ARIZONA_ONESHOT_TRIG_MASK                0x0010  /* ONESHOT_TRIG */
-#define ARIZONA_ONESHOT_TRIG_SHIFT                    4  /* ONESHOT_TRIG */
-#define ARIZONA_ONESHOT_TRIG_WIDTH                    1  /* ONESHOT_TRIG */
-#define ARIZONA_HAP_CTRL_MASK                    0x000C  /* HAP_CTRL - [3:2] */
-#define ARIZONA_HAP_CTRL_SHIFT                        2  /* HAP_CTRL - [3:2] */
-#define ARIZONA_HAP_CTRL_WIDTH                        2  /* HAP_CTRL - [3:2] */
-#define ARIZONA_HAP_ACT                          0x0002  /* HAP_ACT */
-#define ARIZONA_HAP_ACT_MASK                     0x0002  /* HAP_ACT */
-#define ARIZONA_HAP_ACT_SHIFT                         1  /* HAP_ACT */
-#define ARIZONA_HAP_ACT_WIDTH                         1  /* HAP_ACT */
-
-/*
- * R145 (0x91) - Haptics Control 2
- */
-#define ARIZONA_LRA_FREQ_MASK                    0x7FFF  /* LRA_FREQ - [14:0] */
-#define ARIZONA_LRA_FREQ_SHIFT                        0  /* LRA_FREQ - [14:0] */
-#define ARIZONA_LRA_FREQ_WIDTH                       15  /* LRA_FREQ - [14:0] */
-
-/*
- * R146 (0x92) - Haptics phase 1 intensity
- */
-#define ARIZONA_PHASE1_INTENSITY_MASK            0x00FF  /* PHASE1_INTENSITY - [7:0] */
-#define ARIZONA_PHASE1_INTENSITY_SHIFT                0  /* PHASE1_INTENSITY - [7:0] */
-#define ARIZONA_PHASE1_INTENSITY_WIDTH                8  /* PHASE1_INTENSITY - [7:0] */
-
-/*
- * R147 (0x93) - Haptics phase 1 duration
- */
-#define ARIZONA_PHASE1_DURATION_MASK             0x01FF  /* PHASE1_DURATION - [8:0] */
-#define ARIZONA_PHASE1_DURATION_SHIFT                 0  /* PHASE1_DURATION - [8:0] */
-#define ARIZONA_PHASE1_DURATION_WIDTH                 9  /* PHASE1_DURATION - [8:0] */
-
-/*
- * R148 (0x94) - Haptics phase 2 intensity
- */
-#define ARIZONA_PHASE2_INTENSITY_MASK            0x00FF  /* PHASE2_INTENSITY - [7:0] */
-#define ARIZONA_PHASE2_INTENSITY_SHIFT                0  /* PHASE2_INTENSITY - [7:0] */
-#define ARIZONA_PHASE2_INTENSITY_WIDTH                8  /* PHASE2_INTENSITY - [7:0] */
-
-/*
- * R149 (0x95) - Haptics phase 2 duration
- */
-#define ARIZONA_PHASE2_DURATION_MASK             0x07FF  /* PHASE2_DURATION - [10:0] */
-#define ARIZONA_PHASE2_DURATION_SHIFT                 0  /* PHASE2_DURATION - [10:0] */
-#define ARIZONA_PHASE2_DURATION_WIDTH                11  /* PHASE2_DURATION - [10:0] */
-
-/*
- * R150 (0x96) - Haptics phase 3 intensity
- */
-#define ARIZONA_PHASE3_INTENSITY_MASK            0x00FF  /* PHASE3_INTENSITY - [7:0] */
-#define ARIZONA_PHASE3_INTENSITY_SHIFT                0  /* PHASE3_INTENSITY - [7:0] */
-#define ARIZONA_PHASE3_INTENSITY_WIDTH                8  /* PHASE3_INTENSITY - [7:0] */
-
-/*
- * R151 (0x97) - Haptics phase 3 duration
- */
-#define ARIZONA_PHASE3_DURATION_MASK             0x01FF  /* PHASE3_DURATION - [8:0] */
-#define ARIZONA_PHASE3_DURATION_SHIFT                 0  /* PHASE3_DURATION - [8:0] */
-#define ARIZONA_PHASE3_DURATION_WIDTH                 9  /* PHASE3_DURATION - [8:0] */
-
-/*
- * R152 (0x98) - Haptics Status
- */
-#define ARIZONA_ONESHOT_STS                      0x0001  /* ONESHOT_STS */
-#define ARIZONA_ONESHOT_STS_MASK                 0x0001  /* ONESHOT_STS */
-#define ARIZONA_ONESHOT_STS_SHIFT                     0  /* ONESHOT_STS */
-#define ARIZONA_ONESHOT_STS_WIDTH                     1  /* ONESHOT_STS */
-
-/*
- * R256 (0x100) - Clock 32k 1
- */
-#define ARIZONA_CLK_32K_ENA                      0x0040  /* CLK_32K_ENA */
-#define ARIZONA_CLK_32K_ENA_MASK                 0x0040  /* CLK_32K_ENA */
-#define ARIZONA_CLK_32K_ENA_SHIFT                     6  /* CLK_32K_ENA */
-#define ARIZONA_CLK_32K_ENA_WIDTH                     1  /* CLK_32K_ENA */
-#define ARIZONA_CLK_32K_SRC_MASK                 0x0003  /* CLK_32K_SRC - [1:0] */
-#define ARIZONA_CLK_32K_SRC_SHIFT                     0  /* CLK_32K_SRC - [1:0] */
-#define ARIZONA_CLK_32K_SRC_WIDTH                     2  /* CLK_32K_SRC - [1:0] */
-
-/*
- * R257 (0x101) - System Clock 1
- */
-#define ARIZONA_SYSCLK_FRAC                      0x8000  /* SYSCLK_FRAC */
-#define ARIZONA_SYSCLK_FRAC_MASK                 0x8000  /* SYSCLK_FRAC */
-#define ARIZONA_SYSCLK_FRAC_SHIFT                    15  /* SYSCLK_FRAC */
-#define ARIZONA_SYSCLK_FRAC_WIDTH                     1  /* SYSCLK_FRAC */
-#define ARIZONA_SYSCLK_FREQ_MASK                 0x0700  /* SYSCLK_FREQ - [10:8] */
-#define ARIZONA_SYSCLK_FREQ_SHIFT                     8  /* SYSCLK_FREQ - [10:8] */
-#define ARIZONA_SYSCLK_FREQ_WIDTH                     3  /* SYSCLK_FREQ - [10:8] */
-#define ARIZONA_SYSCLK_ENA                       0x0040  /* SYSCLK_ENA */
-#define ARIZONA_SYSCLK_ENA_MASK                  0x0040  /* SYSCLK_ENA */
-#define ARIZONA_SYSCLK_ENA_SHIFT                      6  /* SYSCLK_ENA */
-#define ARIZONA_SYSCLK_ENA_WIDTH                      1  /* SYSCLK_ENA */
-#define ARIZONA_SYSCLK_SRC_MASK                  0x000F  /* SYSCLK_SRC - [3:0] */
-#define ARIZONA_SYSCLK_SRC_SHIFT                      0  /* SYSCLK_SRC - [3:0] */
-#define ARIZONA_SYSCLK_SRC_WIDTH                      4  /* SYSCLK_SRC - [3:0] */
-
-/*
- * R258 (0x102) - Sample rate 1
- */
-#define ARIZONA_SAMPLE_RATE_1_MASK               0x001F  /* SAMPLE_RATE_1 - [4:0] */
-#define ARIZONA_SAMPLE_RATE_1_SHIFT                   0  /* SAMPLE_RATE_1 - [4:0] */
-#define ARIZONA_SAMPLE_RATE_1_WIDTH                   5  /* SAMPLE_RATE_1 - [4:0] */
-
-/*
- * R259 (0x103) - Sample rate 2
- */
-#define ARIZONA_SAMPLE_RATE_2_MASK               0x001F  /* SAMPLE_RATE_2 - [4:0] */
-#define ARIZONA_SAMPLE_RATE_2_SHIFT                   0  /* SAMPLE_RATE_2 - [4:0] */
-#define ARIZONA_SAMPLE_RATE_2_WIDTH                   5  /* SAMPLE_RATE_2 - [4:0] */
-
-/*
- * R260 (0x104) - Sample rate 3
- */
-#define ARIZONA_SAMPLE_RATE_3_MASK               0x001F  /* SAMPLE_RATE_3 - [4:0] */
-#define ARIZONA_SAMPLE_RATE_3_SHIFT                   0  /* SAMPLE_RATE_3 - [4:0] */
-#define ARIZONA_SAMPLE_RATE_3_WIDTH                   5  /* SAMPLE_RATE_3 - [4:0] */
-
-/*
- * R266 (0x10A) - Sample rate 1 status
- */
-#define ARIZONA_SAMPLE_RATE_1_STS_MASK           0x001F  /* SAMPLE_RATE_1_STS - [4:0] */
-#define ARIZONA_SAMPLE_RATE_1_STS_SHIFT               0  /* SAMPLE_RATE_1_STS - [4:0] */
-#define ARIZONA_SAMPLE_RATE_1_STS_WIDTH               5  /* SAMPLE_RATE_1_STS - [4:0] */
-
-/*
- * R267 (0x10B) - Sample rate 2 status
- */
-#define ARIZONA_SAMPLE_RATE_2_STS_MASK           0x001F  /* SAMPLE_RATE_2_STS - [4:0] */
-#define ARIZONA_SAMPLE_RATE_2_STS_SHIFT               0  /* SAMPLE_RATE_2_STS - [4:0] */
-#define ARIZONA_SAMPLE_RATE_2_STS_WIDTH               5  /* SAMPLE_RATE_2_STS - [4:0] */
-
-/*
- * R268 (0x10C) - Sample rate 3 status
- */
-#define ARIZONA_SAMPLE_RATE_3_STS_MASK           0x001F  /* SAMPLE_RATE_3_STS - [4:0] */
-#define ARIZONA_SAMPLE_RATE_3_STS_SHIFT               0  /* SAMPLE_RATE_3_STS - [4:0] */
-#define ARIZONA_SAMPLE_RATE_3_STS_WIDTH               5  /* SAMPLE_RATE_3_STS - [4:0] */
-
-/*
- * R274 (0x112) - Async clock 1
- */
-#define ARIZONA_ASYNC_CLK_FREQ_MASK              0x0700  /* ASYNC_CLK_FREQ - [10:8] */
-#define ARIZONA_ASYNC_CLK_FREQ_SHIFT                  8  /* ASYNC_CLK_FREQ - [10:8] */
-#define ARIZONA_ASYNC_CLK_FREQ_WIDTH                  3  /* ASYNC_CLK_FREQ - [10:8] */
-#define ARIZONA_ASYNC_CLK_ENA                    0x0040  /* ASYNC_CLK_ENA */
-#define ARIZONA_ASYNC_CLK_ENA_MASK               0x0040  /* ASYNC_CLK_ENA */
-#define ARIZONA_ASYNC_CLK_ENA_SHIFT                   6  /* ASYNC_CLK_ENA */
-#define ARIZONA_ASYNC_CLK_ENA_WIDTH                   1  /* ASYNC_CLK_ENA */
-#define ARIZONA_ASYNC_CLK_SRC_MASK               0x000F  /* ASYNC_CLK_SRC - [3:0] */
-#define ARIZONA_ASYNC_CLK_SRC_SHIFT                   0  /* ASYNC_CLK_SRC - [3:0] */
-#define ARIZONA_ASYNC_CLK_SRC_WIDTH                   4  /* ASYNC_CLK_SRC - [3:0] */
-
-/*
- * R275 (0x113) - Async sample rate 1
- */
-#define ARIZONA_ASYNC_SAMPLE_RATE_MASK           0x001F  /* ASYNC_SAMPLE_RATE - [4:0] */
-#define ARIZONA_ASYNC_SAMPLE_RATE_SHIFT               0  /* ASYNC_SAMPLE_RATE - [4:0] */
-#define ARIZONA_ASYNC_SAMPLE_RATE_WIDTH               5  /* ASYNC_SAMPLE_RATE - [4:0] */
-
-/*
- * R283 (0x11B) - Async sample rate 1 status
- */
-#define ARIZONA_ASYNC_SAMPLE_RATE_STS_MASK       0x001F  /* ASYNC_SAMPLE_RATE_STS - [4:0] */
-#define ARIZONA_ASYNC_SAMPLE_RATE_STS_SHIFT           0  /* ASYNC_SAMPLE_RATE_STS - [4:0] */
-#define ARIZONA_ASYNC_SAMPLE_RATE_STS_WIDTH           5  /* ASYNC_SAMPLE_RATE_STS - [4:0] */
-
-/*
- * R329 (0x149) - Output system clock
- */
-#define ARIZONA_OPCLK_ENA                        0x8000  /* OPCLK_ENA */
-#define ARIZONA_OPCLK_ENA_MASK                   0x8000  /* OPCLK_ENA */
-#define ARIZONA_OPCLK_ENA_SHIFT                      15  /* OPCLK_ENA */
-#define ARIZONA_OPCLK_ENA_WIDTH                       1  /* OPCLK_ENA */
-#define ARIZONA_OPCLK_DIV_MASK                   0x00F8  /* OPCLK_DIV - [7:3] */
-#define ARIZONA_OPCLK_DIV_SHIFT                       3  /* OPCLK_DIV - [7:3] */
-#define ARIZONA_OPCLK_DIV_WIDTH                       5  /* OPCLK_DIV - [7:3] */
-#define ARIZONA_OPCLK_SEL_MASK                   0x0007  /* OPCLK_SEL - [2:0] */
-#define ARIZONA_OPCLK_SEL_SHIFT                       0  /* OPCLK_SEL - [2:0] */
-#define ARIZONA_OPCLK_SEL_WIDTH                       3  /* OPCLK_SEL - [2:0] */
-
-/*
- * R330 (0x14A) - Output async clock
- */
-#define ARIZONA_OPCLK_ASYNC_ENA                  0x8000  /* OPCLK_ASYNC_ENA */
-#define ARIZONA_OPCLK_ASYNC_ENA_MASK             0x8000  /* OPCLK_ASYNC_ENA */
-#define ARIZONA_OPCLK_ASYNC_ENA_SHIFT                15  /* OPCLK_ASYNC_ENA */
-#define ARIZONA_OPCLK_ASYNC_ENA_WIDTH                 1  /* OPCLK_ASYNC_ENA */
-#define ARIZONA_OPCLK_ASYNC_DIV_MASK             0x00F8  /* OPCLK_ASYNC_DIV - [7:3] */
-#define ARIZONA_OPCLK_ASYNC_DIV_SHIFT                 3  /* OPCLK_ASYNC_DIV - [7:3] */
-#define ARIZONA_OPCLK_ASYNC_DIV_WIDTH                 5  /* OPCLK_ASYNC_DIV - [7:3] */
-#define ARIZONA_OPCLK_ASYNC_SEL_MASK             0x0007  /* OPCLK_ASYNC_SEL - [2:0] */
-#define ARIZONA_OPCLK_ASYNC_SEL_SHIFT                 0  /* OPCLK_ASYNC_SEL - [2:0] */
-#define ARIZONA_OPCLK_ASYNC_SEL_WIDTH                 3  /* OPCLK_ASYNC_SEL - [2:0] */
-
-/*
- * R338 (0x152) - Rate Estimator 1
- */
-#define ARIZONA_TRIG_ON_STARTUP                  0x0010  /* TRIG_ON_STARTUP */
-#define ARIZONA_TRIG_ON_STARTUP_MASK             0x0010  /* TRIG_ON_STARTUP */
-#define ARIZONA_TRIG_ON_STARTUP_SHIFT                 4  /* TRIG_ON_STARTUP */
-#define ARIZONA_TRIG_ON_STARTUP_WIDTH                 1  /* TRIG_ON_STARTUP */
-#define ARIZONA_LRCLK_SRC_MASK                   0x000E  /* LRCLK_SRC - [3:1] */
-#define ARIZONA_LRCLK_SRC_SHIFT                       1  /* LRCLK_SRC - [3:1] */
-#define ARIZONA_LRCLK_SRC_WIDTH                       3  /* LRCLK_SRC - [3:1] */
-#define ARIZONA_RATE_EST_ENA                     0x0001  /* RATE_EST_ENA */
-#define ARIZONA_RATE_EST_ENA_MASK                0x0001  /* RATE_EST_ENA */
-#define ARIZONA_RATE_EST_ENA_SHIFT                    0  /* RATE_EST_ENA */
-#define ARIZONA_RATE_EST_ENA_WIDTH                    1  /* RATE_EST_ENA */
-
-/*
- * R339 (0x153) - Rate Estimator 2
- */
-#define ARIZONA_SAMPLE_RATE_DETECT_A_MASK        0x001F  /* SAMPLE_RATE_DETECT_A - [4:0] */
-#define ARIZONA_SAMPLE_RATE_DETECT_A_SHIFT            0  /* SAMPLE_RATE_DETECT_A - [4:0] */
-#define ARIZONA_SAMPLE_RATE_DETECT_A_WIDTH            5  /* SAMPLE_RATE_DETECT_A - [4:0] */
-
-/*
- * R340 (0x154) - Rate Estimator 3
- */
-#define ARIZONA_SAMPLE_RATE_DETECT_B_MASK        0x001F  /* SAMPLE_RATE_DETECT_B - [4:0] */
-#define ARIZONA_SAMPLE_RATE_DETECT_B_SHIFT            0  /* SAMPLE_RATE_DETECT_B - [4:0] */
-#define ARIZONA_SAMPLE_RATE_DETECT_B_WIDTH            5  /* SAMPLE_RATE_DETECT_B - [4:0] */
-
-/*
- * R341 (0x155) - Rate Estimator 4
- */
-#define ARIZONA_SAMPLE_RATE_DETECT_C_MASK        0x001F  /* SAMPLE_RATE_DETECT_C - [4:0] */
-#define ARIZONA_SAMPLE_RATE_DETECT_C_SHIFT            0  /* SAMPLE_RATE_DETECT_C - [4:0] */
-#define ARIZONA_SAMPLE_RATE_DETECT_C_WIDTH            5  /* SAMPLE_RATE_DETECT_C - [4:0] */
-
-/*
- * R342 (0x156) - Rate Estimator 5
- */
-#define ARIZONA_SAMPLE_RATE_DETECT_D_MASK        0x001F  /* SAMPLE_RATE_DETECT_D - [4:0] */
-#define ARIZONA_SAMPLE_RATE_DETECT_D_SHIFT            0  /* SAMPLE_RATE_DETECT_D - [4:0] */
-#define ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH            5  /* SAMPLE_RATE_DETECT_D - [4:0] */
-
-/*
- * R353 (0x161) - Dynamic Frequency Scaling 1
- */
-#define ARIZONA_SUBSYS_MAX_FREQ                  0x0001  /* SUBSYS_MAX_FREQ */
-#define ARIZONA_SUBSYS_MAX_FREQ_SHIFT                 0  /* SUBSYS_MAX_FREQ */
-#define ARIZONA_SUBSYS_MAX_FREQ_WIDTH                 1  /* SUBSYS_MAX_FREQ */
-
-/*
- * R369 (0x171) - FLL1 Control 1
- */
-#define ARIZONA_FLL1_FREERUN                     0x0002  /* FLL1_FREERUN */
-#define ARIZONA_FLL1_FREERUN_MASK                0x0002  /* FLL1_FREERUN */
-#define ARIZONA_FLL1_FREERUN_SHIFT                    1  /* FLL1_FREERUN */
-#define ARIZONA_FLL1_FREERUN_WIDTH                    1  /* FLL1_FREERUN */
-#define ARIZONA_FLL1_ENA                         0x0001  /* FLL1_ENA */
-#define ARIZONA_FLL1_ENA_MASK                    0x0001  /* FLL1_ENA */
-#define ARIZONA_FLL1_ENA_SHIFT                        0  /* FLL1_ENA */
-#define ARIZONA_FLL1_ENA_WIDTH                        1  /* FLL1_ENA */
-
-/*
- * R370 (0x172) - FLL1 Control 2
- */
-#define ARIZONA_FLL1_CTRL_UPD                    0x8000  /* FLL1_CTRL_UPD */
-#define ARIZONA_FLL1_CTRL_UPD_MASK               0x8000  /* FLL1_CTRL_UPD */
-#define ARIZONA_FLL1_CTRL_UPD_SHIFT                  15  /* FLL1_CTRL_UPD */
-#define ARIZONA_FLL1_CTRL_UPD_WIDTH                   1  /* FLL1_CTRL_UPD */
-#define ARIZONA_FLL1_N_MASK                      0x03FF  /* FLL1_N - [9:0] */
-#define ARIZONA_FLL1_N_SHIFT                          0  /* FLL1_N - [9:0] */
-#define ARIZONA_FLL1_N_WIDTH                         10  /* FLL1_N - [9:0] */
-
-/*
- * R371 (0x173) - FLL1 Control 3
- */
-#define ARIZONA_FLL1_THETA_MASK                  0xFFFF  /* FLL1_THETA - [15:0] */
-#define ARIZONA_FLL1_THETA_SHIFT                      0  /* FLL1_THETA - [15:0] */
-#define ARIZONA_FLL1_THETA_WIDTH                     16  /* FLL1_THETA - [15:0] */
-
-/*
- * R372 (0x174) - FLL1 Control 4
- */
-#define ARIZONA_FLL1_LAMBDA_MASK                 0xFFFF  /* FLL1_LAMBDA - [15:0] */
-#define ARIZONA_FLL1_LAMBDA_SHIFT                     0  /* FLL1_LAMBDA - [15:0] */
-#define ARIZONA_FLL1_LAMBDA_WIDTH                    16  /* FLL1_LAMBDA - [15:0] */
-
-/*
- * R373 (0x175) - FLL1 Control 5
- */
-#define ARIZONA_FLL1_FRATIO_MASK                 0x0700  /* FLL1_FRATIO - [10:8] */
-#define ARIZONA_FLL1_FRATIO_SHIFT                     8  /* FLL1_FRATIO - [10:8] */
-#define ARIZONA_FLL1_FRATIO_WIDTH                     3  /* FLL1_FRATIO - [10:8] */
-#define ARIZONA_FLL1_OUTDIV_MASK                 0x000E  /* FLL1_OUTDIV - [3:1] */
-#define ARIZONA_FLL1_OUTDIV_SHIFT                     1  /* FLL1_OUTDIV - [3:1] */
-#define ARIZONA_FLL1_OUTDIV_WIDTH                     3  /* FLL1_OUTDIV - [3:1] */
-
-/*
- * R374 (0x176) - FLL1 Control 6
- */
-#define ARIZONA_FLL1_CLK_REF_DIV_MASK            0x00C0  /* FLL1_CLK_REF_DIV - [7:6] */
-#define ARIZONA_FLL1_CLK_REF_DIV_SHIFT                6  /* FLL1_CLK_REF_DIV - [7:6] */
-#define ARIZONA_FLL1_CLK_REF_DIV_WIDTH                2  /* FLL1_CLK_REF_DIV - [7:6] */
-#define ARIZONA_FLL1_CLK_REF_SRC_MASK            0x000F  /* FLL1_CLK_REF_SRC - [3:0] */
-#define ARIZONA_FLL1_CLK_REF_SRC_SHIFT                0  /* FLL1_CLK_REF_SRC - [3:0] */
-#define ARIZONA_FLL1_CLK_REF_SRC_WIDTH                4  /* FLL1_CLK_REF_SRC - [3:0] */
-
-/*
- * R375 (0x177) - FLL1 Loop Filter Test 1
- */
-#define ARIZONA_FLL1_FRC_INTEG_UPD               0x8000  /* FLL1_FRC_INTEG_UPD */
-#define ARIZONA_FLL1_FRC_INTEG_UPD_MASK          0x8000  /* FLL1_FRC_INTEG_UPD */
-#define ARIZONA_FLL1_FRC_INTEG_UPD_SHIFT             15  /* FLL1_FRC_INTEG_UPD */
-#define ARIZONA_FLL1_FRC_INTEG_UPD_WIDTH              1  /* FLL1_FRC_INTEG_UPD */
-#define ARIZONA_FLL1_FRC_INTEG_VAL_MASK          0x0FFF  /* FLL1_FRC_INTEG_VAL - [11:0] */
-#define ARIZONA_FLL1_FRC_INTEG_VAL_SHIFT              0  /* FLL1_FRC_INTEG_VAL - [11:0] */
-#define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH             12  /* FLL1_FRC_INTEG_VAL - [11:0] */
-
-/*
- * R385 (0x181) - FLL1 Synchroniser 1
- */
-#define ARIZONA_FLL1_SYNC_ENA                    0x0001  /* FLL1_SYNC_ENA */
-#define ARIZONA_FLL1_SYNC_ENA_MASK               0x0001  /* FLL1_SYNC_ENA */
-#define ARIZONA_FLL1_SYNC_ENA_SHIFT                   0  /* FLL1_SYNC_ENA */
-#define ARIZONA_FLL1_SYNC_ENA_WIDTH                   1  /* FLL1_SYNC_ENA */
-
-/*
- * R386 (0x182) - FLL1 Synchroniser 2
- */
-#define ARIZONA_FLL1_SYNC_N_MASK                 0x03FF  /* FLL1_SYNC_N - [9:0] */
-#define ARIZONA_FLL1_SYNC_N_SHIFT                     0  /* FLL1_SYNC_N - [9:0] */
-#define ARIZONA_FLL1_SYNC_N_WIDTH                    10  /* FLL1_SYNC_N - [9:0] */
-
-/*
- * R387 (0x183) - FLL1 Synchroniser 3
- */
-#define ARIZONA_FLL1_SYNC_THETA_MASK             0xFFFF  /* FLL1_SYNC_THETA - [15:0] */
-#define ARIZONA_FLL1_SYNC_THETA_SHIFT                 0  /* FLL1_SYNC_THETA - [15:0] */
-#define ARIZONA_FLL1_SYNC_THETA_WIDTH                16  /* FLL1_SYNC_THETA - [15:0] */
-
-/*
- * R388 (0x184) - FLL1 Synchroniser 4
- */
-#define ARIZONA_FLL1_SYNC_LAMBDA_MASK            0xFFFF  /* FLL1_SYNC_LAMBDA - [15:0] */
-#define ARIZONA_FLL1_SYNC_LAMBDA_SHIFT                0  /* FLL1_SYNC_LAMBDA - [15:0] */
-#define ARIZONA_FLL1_SYNC_LAMBDA_WIDTH               16  /* FLL1_SYNC_LAMBDA - [15:0] */
-
-/*
- * R389 (0x185) - FLL1 Synchroniser 5
- */
-#define ARIZONA_FLL1_SYNC_FRATIO_MASK            0x0700  /* FLL1_SYNC_FRATIO - [10:8] */
-#define ARIZONA_FLL1_SYNC_FRATIO_SHIFT                8  /* FLL1_SYNC_FRATIO - [10:8] */
-#define ARIZONA_FLL1_SYNC_FRATIO_WIDTH                3  /* FLL1_SYNC_FRATIO - [10:8] */
-
-/*
- * R390 (0x186) - FLL1 Synchroniser 6
- */
-#define ARIZONA_FLL1_CLK_SYNC_DIV_MASK           0x00C0  /* FLL1_CLK_SYNC_DIV - [7:6] */
-#define ARIZONA_FLL1_CLK_SYNC_DIV_SHIFT               6  /* FLL1_CLK_SYNC_DIV - [7:6] */
-#define ARIZONA_FLL1_CLK_SYNC_DIV_WIDTH               2  /* FLL1_CLK_SYNC_DIV - [7:6] */
-#define ARIZONA_FLL1_CLK_SYNC_SRC_MASK           0x000F  /* FLL1_CLK_SYNC_SRC - [3:0] */
-#define ARIZONA_FLL1_CLK_SYNC_SRC_SHIFT               0  /* FLL1_CLK_SYNC_SRC - [3:0] */
-#define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH               4  /* FLL1_CLK_SYNC_SRC - [3:0] */
-
-/*
- * R393 (0x189) - FLL1 Spread Spectrum
- */
-#define ARIZONA_FLL1_SS_AMPL_MASK                0x0030  /* FLL1_SS_AMPL - [5:4] */
-#define ARIZONA_FLL1_SS_AMPL_SHIFT                    4  /* FLL1_SS_AMPL - [5:4] */
-#define ARIZONA_FLL1_SS_AMPL_WIDTH                    2  /* FLL1_SS_AMPL - [5:4] */
-#define ARIZONA_FLL1_SS_FREQ_MASK                0x000C  /* FLL1_SS_FREQ - [3:2] */
-#define ARIZONA_FLL1_SS_FREQ_SHIFT                    2  /* FLL1_SS_FREQ - [3:2] */
-#define ARIZONA_FLL1_SS_FREQ_WIDTH                    2  /* FLL1_SS_FREQ - [3:2] */
-#define ARIZONA_FLL1_SS_SEL_MASK                 0x0003  /* FLL1_SS_SEL - [1:0] */
-#define ARIZONA_FLL1_SS_SEL_SHIFT                     0  /* FLL1_SS_SEL - [1:0] */
-#define ARIZONA_FLL1_SS_SEL_WIDTH                     2  /* FLL1_SS_SEL - [1:0] */
-
-/*
- * R394 (0x18A) - FLL1 GPIO Clock
- */
-#define ARIZONA_FLL1_GPDIV_MASK                  0x00FE  /* FLL1_GPDIV - [7:1] */
-#define ARIZONA_FLL1_GPDIV_SHIFT                      1  /* FLL1_GPDIV - [7:1] */
-#define ARIZONA_FLL1_GPDIV_WIDTH                      7  /* FLL1_GPDIV - [7:1] */
-#define ARIZONA_FLL1_GPDIV_ENA                   0x0001  /* FLL1_GPDIV_ENA */
-#define ARIZONA_FLL1_GPDIV_ENA_MASK              0x0001  /* FLL1_GPDIV_ENA */
-#define ARIZONA_FLL1_GPDIV_ENA_SHIFT                  0  /* FLL1_GPDIV_ENA */
-#define ARIZONA_FLL1_GPDIV_ENA_WIDTH                  1  /* FLL1_GPDIV_ENA */
-
-/*
- * R401 (0x191) - FLL2 Control 1
- */
-#define ARIZONA_FLL2_FREERUN                     0x0002  /* FLL2_FREERUN */
-#define ARIZONA_FLL2_FREERUN_MASK                0x0002  /* FLL2_FREERUN */
-#define ARIZONA_FLL2_FREERUN_SHIFT                    1  /* FLL2_FREERUN */
-#define ARIZONA_FLL2_FREERUN_WIDTH                    1  /* FLL2_FREERUN */
-#define ARIZONA_FLL2_ENA                         0x0001  /* FLL2_ENA */
-#define ARIZONA_FLL2_ENA_MASK                    0x0001  /* FLL2_ENA */
-#define ARIZONA_FLL2_ENA_SHIFT                        0  /* FLL2_ENA */
-#define ARIZONA_FLL2_ENA_WIDTH                        1  /* FLL2_ENA */
-
-/*
- * R402 (0x192) - FLL2 Control 2
- */
-#define ARIZONA_FLL2_CTRL_UPD                    0x8000  /* FLL2_CTRL_UPD */
-#define ARIZONA_FLL2_CTRL_UPD_MASK               0x8000  /* FLL2_CTRL_UPD */
-#define ARIZONA_FLL2_CTRL_UPD_SHIFT                  15  /* FLL2_CTRL_UPD */
-#define ARIZONA_FLL2_CTRL_UPD_WIDTH                   1  /* FLL2_CTRL_UPD */
-#define ARIZONA_FLL2_N_MASK                      0x03FF  /* FLL2_N - [9:0] */
-#define ARIZONA_FLL2_N_SHIFT                          0  /* FLL2_N - [9:0] */
-#define ARIZONA_FLL2_N_WIDTH                         10  /* FLL2_N - [9:0] */
-
-/*
- * R403 (0x193) - FLL2 Control 3
- */
-#define ARIZONA_FLL2_THETA_MASK                  0xFFFF  /* FLL2_THETA - [15:0] */
-#define ARIZONA_FLL2_THETA_SHIFT                      0  /* FLL2_THETA - [15:0] */
-#define ARIZONA_FLL2_THETA_WIDTH                     16  /* FLL2_THETA - [15:0] */
-
-/*
- * R404 (0x194) - FLL2 Control 4
- */
-#define ARIZONA_FLL2_LAMBDA_MASK                 0xFFFF  /* FLL2_LAMBDA - [15:0] */
-#define ARIZONA_FLL2_LAMBDA_SHIFT                     0  /* FLL2_LAMBDA - [15:0] */
-#define ARIZONA_FLL2_LAMBDA_WIDTH                    16  /* FLL2_LAMBDA - [15:0] */
-
-/*
- * R405 (0x195) - FLL2 Control 5
- */
-#define ARIZONA_FLL2_FRATIO_MASK                 0x0700  /* FLL2_FRATIO - [10:8] */
-#define ARIZONA_FLL2_FRATIO_SHIFT                     8  /* FLL2_FRATIO - [10:8] */
-#define ARIZONA_FLL2_FRATIO_WIDTH                     3  /* FLL2_FRATIO - [10:8] */
-#define ARIZONA_FLL2_OUTDIV_MASK                 0x000E  /* FLL2_OUTDIV - [3:1] */
-#define ARIZONA_FLL2_OUTDIV_SHIFT                     1  /* FLL2_OUTDIV - [3:1] */
-#define ARIZONA_FLL2_OUTDIV_WIDTH                     3  /* FLL2_OUTDIV - [3:1] */
-
-/*
- * R406 (0x196) - FLL2 Control 6
- */
-#define ARIZONA_FLL2_CLK_REF_DIV_MASK            0x00C0  /* FLL2_CLK_REF_DIV - [7:6] */
-#define ARIZONA_FLL2_CLK_REF_DIV_SHIFT                6  /* FLL2_CLK_REF_DIV - [7:6] */
-#define ARIZONA_FLL2_CLK_REF_DIV_WIDTH                2  /* FLL2_CLK_REF_DIV - [7:6] */
-#define ARIZONA_FLL2_CLK_REF_SRC_MASK            0x000F  /* FLL2_CLK_REF_SRC - [3:0] */
-#define ARIZONA_FLL2_CLK_REF_SRC_SHIFT                0  /* FLL2_CLK_REF_SRC - [3:0] */
-#define ARIZONA_FLL2_CLK_REF_SRC_WIDTH                4  /* FLL2_CLK_REF_SRC - [3:0] */
-
-/*
- * R407 (0x197) - FLL2 Loop Filter Test 1
- */
-#define ARIZONA_FLL2_FRC_INTEG_UPD               0x8000  /* FLL2_FRC_INTEG_UPD */
-#define ARIZONA_FLL2_FRC_INTEG_UPD_MASK          0x8000  /* FLL2_FRC_INTEG_UPD */
-#define ARIZONA_FLL2_FRC_INTEG_UPD_SHIFT             15  /* FLL2_FRC_INTEG_UPD */
-#define ARIZONA_FLL2_FRC_INTEG_UPD_WIDTH              1  /* FLL2_FRC_INTEG_UPD */
-#define ARIZONA_FLL2_FRC_INTEG_VAL_MASK          0x0FFF  /* FLL2_FRC_INTEG_VAL - [11:0] */
-#define ARIZONA_FLL2_FRC_INTEG_VAL_SHIFT              0  /* FLL2_FRC_INTEG_VAL - [11:0] */
-#define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH             12  /* FLL2_FRC_INTEG_VAL - [11:0] */
-
-/*
- * R417 (0x1A1) - FLL2 Synchroniser 1
- */
-#define ARIZONA_FLL2_SYNC_ENA                    0x0001  /* FLL2_SYNC_ENA */
-#define ARIZONA_FLL2_SYNC_ENA_MASK               0x0001  /* FLL2_SYNC_ENA */
-#define ARIZONA_FLL2_SYNC_ENA_SHIFT                   0  /* FLL2_SYNC_ENA */
-#define ARIZONA_FLL2_SYNC_ENA_WIDTH                   1  /* FLL2_SYNC_ENA */
-
-/*
- * R418 (0x1A2) - FLL2 Synchroniser 2
- */
-#define ARIZONA_FLL2_SYNC_N_MASK                 0x03FF  /* FLL2_SYNC_N - [9:0] */
-#define ARIZONA_FLL2_SYNC_N_SHIFT                     0  /* FLL2_SYNC_N - [9:0] */
-#define ARIZONA_FLL2_SYNC_N_WIDTH                    10  /* FLL2_SYNC_N - [9:0] */
-
-/*
- * R419 (0x1A3) - FLL2 Synchroniser 3
- */
-#define ARIZONA_FLL2_SYNC_THETA_MASK             0xFFFF  /* FLL2_SYNC_THETA - [15:0] */
-#define ARIZONA_FLL2_SYNC_THETA_SHIFT                 0  /* FLL2_SYNC_THETA - [15:0] */
-#define ARIZONA_FLL2_SYNC_THETA_WIDTH                16  /* FLL2_SYNC_THETA - [15:0] */
-
-/*
- * R420 (0x1A4) - FLL2 Synchroniser 4
- */
-#define ARIZONA_FLL2_SYNC_LAMBDA_MASK            0xFFFF  /* FLL2_SYNC_LAMBDA - [15:0] */
-#define ARIZONA_FLL2_SYNC_LAMBDA_SHIFT                0  /* FLL2_SYNC_LAMBDA - [15:0] */
-#define ARIZONA_FLL2_SYNC_LAMBDA_WIDTH               16  /* FLL2_SYNC_LAMBDA - [15:0] */
-
-/*
- * R421 (0x1A5) - FLL2 Synchroniser 5
- */
-#define ARIZONA_FLL2_SYNC_FRATIO_MASK            0x0700  /* FLL2_SYNC_FRATIO - [10:8] */
-#define ARIZONA_FLL2_SYNC_FRATIO_SHIFT                8  /* FLL2_SYNC_FRATIO - [10:8] */
-#define ARIZONA_FLL2_SYNC_FRATIO_WIDTH                3  /* FLL2_SYNC_FRATIO - [10:8] */
-
-/*
- * R422 (0x1A6) - FLL2 Synchroniser 6
- */
-#define ARIZONA_FLL2_CLK_SYNC_DIV_MASK           0x00C0  /* FLL2_CLK_SYNC_DIV - [7:6] */
-#define ARIZONA_FLL2_CLK_SYNC_DIV_SHIFT               6  /* FLL2_CLK_SYNC_DIV - [7:6] */
-#define ARIZONA_FLL2_CLK_SYNC_DIV_WIDTH               2  /* FLL2_CLK_SYNC_DIV - [7:6] */
-#define ARIZONA_FLL2_CLK_SYNC_SRC_MASK           0x000F  /* FLL2_CLK_SYNC_SRC - [3:0] */
-#define ARIZONA_FLL2_CLK_SYNC_SRC_SHIFT               0  /* FLL2_CLK_SYNC_SRC - [3:0] */
-#define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH               4  /* FLL2_CLK_SYNC_SRC - [3:0] */
-
-/*
- * R425 (0x1A9) - FLL2 Spread Spectrum
- */
-#define ARIZONA_FLL2_SS_AMPL_MASK                0x0030  /* FLL2_SS_AMPL - [5:4] */
-#define ARIZONA_FLL2_SS_AMPL_SHIFT                    4  /* FLL2_SS_AMPL - [5:4] */
-#define ARIZONA_FLL2_SS_AMPL_WIDTH                    2  /* FLL2_SS_AMPL - [5:4] */
-#define ARIZONA_FLL2_SS_FREQ_MASK                0x000C  /* FLL2_SS_FREQ - [3:2] */
-#define ARIZONA_FLL2_SS_FREQ_SHIFT                    2  /* FLL2_SS_FREQ - [3:2] */
-#define ARIZONA_FLL2_SS_FREQ_WIDTH                    2  /* FLL2_SS_FREQ - [3:2] */
-#define ARIZONA_FLL2_SS_SEL_MASK                 0x0003  /* FLL2_SS_SEL - [1:0] */
-#define ARIZONA_FLL2_SS_SEL_SHIFT                     0  /* FLL2_SS_SEL - [1:0] */
-#define ARIZONA_FLL2_SS_SEL_WIDTH                     2  /* FLL2_SS_SEL - [1:0] */
-
-/*
- * R426 (0x1AA) - FLL2 GPIO Clock
- */
-#define ARIZONA_FLL2_GPDIV_MASK                  0x00FE  /* FLL2_GPDIV - [7:1] */
-#define ARIZONA_FLL2_GPDIV_SHIFT                      1  /* FLL2_GPDIV - [7:1] */
-#define ARIZONA_FLL2_GPDIV_WIDTH                      7  /* FLL2_GPDIV - [7:1] */
-#define ARIZONA_FLL2_GPDIV_ENA                   0x0001  /* FLL2_GPDIV_ENA */
-#define ARIZONA_FLL2_GPDIV_ENA_MASK              0x0001  /* FLL2_GPDIV_ENA */
-#define ARIZONA_FLL2_GPDIV_ENA_SHIFT                  0  /* FLL2_GPDIV_ENA */
-#define ARIZONA_FLL2_GPDIV_ENA_WIDTH                  1  /* FLL2_GPDIV_ENA */
-
-/*
- * R512 (0x200) - Mic Charge Pump 1
- */
-#define ARIZONA_CPMIC_DISCH                      0x0004  /* CPMIC_DISCH */
-#define ARIZONA_CPMIC_DISCH_MASK                 0x0004  /* CPMIC_DISCH */
-#define ARIZONA_CPMIC_DISCH_SHIFT                     2  /* CPMIC_DISCH */
-#define ARIZONA_CPMIC_DISCH_WIDTH                     1  /* CPMIC_DISCH */
-#define ARIZONA_CPMIC_BYPASS                     0x0002  /* CPMIC_BYPASS */
-#define ARIZONA_CPMIC_BYPASS_MASK                0x0002  /* CPMIC_BYPASS */
-#define ARIZONA_CPMIC_BYPASS_SHIFT                    1  /* CPMIC_BYPASS */
-#define ARIZONA_CPMIC_BYPASS_WIDTH                    1  /* CPMIC_BYPASS */
-#define ARIZONA_CPMIC_ENA                        0x0001  /* CPMIC_ENA */
-#define ARIZONA_CPMIC_ENA_MASK                   0x0001  /* CPMIC_ENA */
-#define ARIZONA_CPMIC_ENA_SHIFT                       0  /* CPMIC_ENA */
-#define ARIZONA_CPMIC_ENA_WIDTH                       1  /* CPMIC_ENA */
-
-/*
- * R528 (0x210) - LDO1 Control 1
- */
-#define ARIZONA_LDO1_VSEL_MASK                   0x07E0  /* LDO1_VSEL - [10:5] */
-#define ARIZONA_LDO1_VSEL_SHIFT                       5  /* LDO1_VSEL - [10:5] */
-#define ARIZONA_LDO1_VSEL_WIDTH                       6  /* LDO1_VSEL - [10:5] */
-#define ARIZONA_LDO1_FAST                        0x0010  /* LDO1_FAST */
-#define ARIZONA_LDO1_FAST_MASK                   0x0010  /* LDO1_FAST */
-#define ARIZONA_LDO1_FAST_SHIFT                       4  /* LDO1_FAST */
-#define ARIZONA_LDO1_FAST_WIDTH                       1  /* LDO1_FAST */
-#define ARIZONA_LDO1_DISCH                       0x0004  /* LDO1_DISCH */
-#define ARIZONA_LDO1_DISCH_MASK                  0x0004  /* LDO1_DISCH */
-#define ARIZONA_LDO1_DISCH_SHIFT                      2  /* LDO1_DISCH */
-#define ARIZONA_LDO1_DISCH_WIDTH                      1  /* LDO1_DISCH */
-#define ARIZONA_LDO1_BYPASS                      0x0002  /* LDO1_BYPASS */
-#define ARIZONA_LDO1_BYPASS_MASK                 0x0002  /* LDO1_BYPASS */
-#define ARIZONA_LDO1_BYPASS_SHIFT                     1  /* LDO1_BYPASS */
-#define ARIZONA_LDO1_BYPASS_WIDTH                     1  /* LDO1_BYPASS */
-#define ARIZONA_LDO1_ENA                         0x0001  /* LDO1_ENA */
-#define ARIZONA_LDO1_ENA_MASK                    0x0001  /* LDO1_ENA */
-#define ARIZONA_LDO1_ENA_SHIFT                        0  /* LDO1_ENA */
-#define ARIZONA_LDO1_ENA_WIDTH                        1  /* LDO1_ENA */
-
-/*
- * R530 (0x212) - LDO1 Control 2
- */
-#define ARIZONA_LDO1_HI_PWR                      0x0001  /* LDO1_HI_PWR */
-#define ARIZONA_LDO1_HI_PWR_SHIFT                     0  /* LDO1_HI_PWR */
-#define ARIZONA_LDO1_HI_PWR_WIDTH                     1  /* LDO1_HI_PWR */
-
-/*
- * R531 (0x213) - LDO2 Control 1
- */
-#define ARIZONA_LDO2_VSEL_MASK                   0x07E0  /* LDO2_VSEL - [10:5] */
-#define ARIZONA_LDO2_VSEL_SHIFT                       5  /* LDO2_VSEL - [10:5] */
-#define ARIZONA_LDO2_VSEL_WIDTH                       6  /* LDO2_VSEL - [10:5] */
-#define ARIZONA_LDO2_FAST                        0x0010  /* LDO2_FAST */
-#define ARIZONA_LDO2_FAST_MASK                   0x0010  /* LDO2_FAST */
-#define ARIZONA_LDO2_FAST_SHIFT                       4  /* LDO2_FAST */
-#define ARIZONA_LDO2_FAST_WIDTH                       1  /* LDO2_FAST */
-#define ARIZONA_LDO2_DISCH                       0x0004  /* LDO2_DISCH */
-#define ARIZONA_LDO2_DISCH_MASK                  0x0004  /* LDO2_DISCH */
-#define ARIZONA_LDO2_DISCH_SHIFT                      2  /* LDO2_DISCH */
-#define ARIZONA_LDO2_DISCH_WIDTH                      1  /* LDO2_DISCH */
-#define ARIZONA_LDO2_BYPASS                      0x0002  /* LDO2_BYPASS */
-#define ARIZONA_LDO2_BYPASS_MASK                 0x0002  /* LDO2_BYPASS */
-#define ARIZONA_LDO2_BYPASS_SHIFT                     1  /* LDO2_BYPASS */
-#define ARIZONA_LDO2_BYPASS_WIDTH                     1  /* LDO2_BYPASS */
-#define ARIZONA_LDO2_ENA                         0x0001  /* LDO2_ENA */
-#define ARIZONA_LDO2_ENA_MASK                    0x0001  /* LDO2_ENA */
-#define ARIZONA_LDO2_ENA_SHIFT                        0  /* LDO2_ENA */
-#define ARIZONA_LDO2_ENA_WIDTH                        1  /* LDO2_ENA */
-
-/*
- * R536 (0x218) - Mic Bias Ctrl 1
- */
-#define ARIZONA_MICB1_EXT_CAP                    0x8000  /* MICB1_EXT_CAP */
-#define ARIZONA_MICB1_EXT_CAP_MASK               0x8000  /* MICB1_EXT_CAP */
-#define ARIZONA_MICB1_EXT_CAP_SHIFT                  15  /* MICB1_EXT_CAP */
-#define ARIZONA_MICB1_EXT_CAP_WIDTH                   1  /* MICB1_EXT_CAP */
-#define ARIZONA_MICB1_LVL_MASK                   0x01E0  /* MICB1_LVL - [8:5] */
-#define ARIZONA_MICB1_LVL_SHIFT                       5  /* MICB1_LVL - [8:5] */
-#define ARIZONA_MICB1_LVL_WIDTH                       4  /* MICB1_LVL - [8:5] */
-#define ARIZONA_MICB1_FAST                       0x0010  /* MICB1_FAST */
-#define ARIZONA_MICB1_FAST_MASK                  0x0010  /* MICB1_FAST */
-#define ARIZONA_MICB1_FAST_SHIFT                      4  /* MICB1_FAST */
-#define ARIZONA_MICB1_FAST_WIDTH                      1  /* MICB1_FAST */
-#define ARIZONA_MICB1_RATE                       0x0008  /* MICB1_RATE */
-#define ARIZONA_MICB1_RATE_MASK                  0x0008  /* MICB1_RATE */
-#define ARIZONA_MICB1_RATE_SHIFT                      3  /* MICB1_RATE */
-#define ARIZONA_MICB1_RATE_WIDTH                      1  /* MICB1_RATE */
-#define ARIZONA_MICB1_DISCH                      0x0004  /* MICB1_DISCH */
-#define ARIZONA_MICB1_DISCH_MASK                 0x0004  /* MICB1_DISCH */
-#define ARIZONA_MICB1_DISCH_SHIFT                     2  /* MICB1_DISCH */
-#define ARIZONA_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
-#define ARIZONA_MICB1_BYPASS                     0x0002  /* MICB1_BYPASS */
-#define ARIZONA_MICB1_BYPASS_MASK                0x0002  /* MICB1_BYPASS */
-#define ARIZONA_MICB1_BYPASS_SHIFT                    1  /* MICB1_BYPASS */
-#define ARIZONA_MICB1_BYPASS_WIDTH                    1  /* MICB1_BYPASS */
-#define ARIZONA_MICB1_ENA                        0x0001  /* MICB1_ENA */
-#define ARIZONA_MICB1_ENA_MASK                   0x0001  /* MICB1_ENA */
-#define ARIZONA_MICB1_ENA_SHIFT                       0  /* MICB1_ENA */
-#define ARIZONA_MICB1_ENA_WIDTH                       1  /* MICB1_ENA */
-
-/*
- * R537 (0x219) - Mic Bias Ctrl 2
- */
-#define ARIZONA_MICB2_EXT_CAP                    0x8000  /* MICB2_EXT_CAP */
-#define ARIZONA_MICB2_EXT_CAP_MASK               0x8000  /* MICB2_EXT_CAP */
-#define ARIZONA_MICB2_EXT_CAP_SHIFT                  15  /* MICB2_EXT_CAP */
-#define ARIZONA_MICB2_EXT_CAP_WIDTH                   1  /* MICB2_EXT_CAP */
-#define ARIZONA_MICB2_LVL_MASK                   0x01E0  /* MICB2_LVL - [8:5] */
-#define ARIZONA_MICB2_LVL_SHIFT                       5  /* MICB2_LVL - [8:5] */
-#define ARIZONA_MICB2_LVL_WIDTH                       4  /* MICB2_LVL - [8:5] */
-#define ARIZONA_MICB2_FAST                       0x0010  /* MICB2_FAST */
-#define ARIZONA_MICB2_FAST_MASK                  0x0010  /* MICB2_FAST */
-#define ARIZONA_MICB2_FAST_SHIFT                      4  /* MICB2_FAST */
-#define ARIZONA_MICB2_FAST_WIDTH                      1  /* MICB2_FAST */
-#define ARIZONA_MICB2_RATE                       0x0008  /* MICB2_RATE */
-#define ARIZONA_MICB2_RATE_MASK                  0x0008  /* MICB2_RATE */
-#define ARIZONA_MICB2_RATE_SHIFT                      3  /* MICB2_RATE */
-#define ARIZONA_MICB2_RATE_WIDTH                      1  /* MICB2_RATE */
-#define ARIZONA_MICB2_DISCH                      0x0004  /* MICB2_DISCH */
-#define ARIZONA_MICB2_DISCH_MASK                 0x0004  /* MICB2_DISCH */
-#define ARIZONA_MICB2_DISCH_SHIFT                     2  /* MICB2_DISCH */
-#define ARIZONA_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
-#define ARIZONA_MICB2_BYPASS                     0x0002  /* MICB2_BYPASS */
-#define ARIZONA_MICB2_BYPASS_MASK                0x0002  /* MICB2_BYPASS */
-#define ARIZONA_MICB2_BYPASS_SHIFT                    1  /* MICB2_BYPASS */
-#define ARIZONA_MICB2_BYPASS_WIDTH                    1  /* MICB2_BYPASS */
-#define ARIZONA_MICB2_ENA                        0x0001  /* MICB2_ENA */
-#define ARIZONA_MICB2_ENA_MASK                   0x0001  /* MICB2_ENA */
-#define ARIZONA_MICB2_ENA_SHIFT                       0  /* MICB2_ENA */
-#define ARIZONA_MICB2_ENA_WIDTH                       1  /* MICB2_ENA */
-
-/*
- * R538 (0x21A) - Mic Bias Ctrl 3
- */
-#define ARIZONA_MICB3_EXT_CAP                    0x8000  /* MICB3_EXT_CAP */
-#define ARIZONA_MICB3_EXT_CAP_MASK               0x8000  /* MICB3_EXT_CAP */
-#define ARIZONA_MICB3_EXT_CAP_SHIFT                  15  /* MICB3_EXT_CAP */
-#define ARIZONA_MICB3_EXT_CAP_WIDTH                   1  /* MICB3_EXT_CAP */
-#define ARIZONA_MICB3_LVL_MASK                   0x01E0  /* MICB3_LVL - [8:5] */
-#define ARIZONA_MICB3_LVL_SHIFT                       5  /* MICB3_LVL - [8:5] */
-#define ARIZONA_MICB3_LVL_WIDTH                       4  /* MICB3_LVL - [8:5] */
-#define ARIZONA_MICB3_FAST                       0x0010  /* MICB3_FAST */
-#define ARIZONA_MICB3_FAST_MASK                  0x0010  /* MICB3_FAST */
-#define ARIZONA_MICB3_FAST_SHIFT                      4  /* MICB3_FAST */
-#define ARIZONA_MICB3_FAST_WIDTH                      1  /* MICB3_FAST */
-#define ARIZONA_MICB3_RATE                       0x0008  /* MICB3_RATE */
-#define ARIZONA_MICB3_RATE_MASK                  0x0008  /* MICB3_RATE */
-#define ARIZONA_MICB3_RATE_SHIFT                      3  /* MICB3_RATE */
-#define ARIZONA_MICB3_RATE_WIDTH                      1  /* MICB3_RATE */
-#define ARIZONA_MICB3_DISCH                      0x0004  /* MICB3_DISCH */
-#define ARIZONA_MICB3_DISCH_MASK                 0x0004  /* MICB3_DISCH */
-#define ARIZONA_MICB3_DISCH_SHIFT                     2  /* MICB3_DISCH */
-#define ARIZONA_MICB3_DISCH_WIDTH                     1  /* MICB3_DISCH */
-#define ARIZONA_MICB3_BYPASS                     0x0002  /* MICB3_BYPASS */
-#define ARIZONA_MICB3_BYPASS_MASK                0x0002  /* MICB3_BYPASS */
-#define ARIZONA_MICB3_BYPASS_SHIFT                    1  /* MICB3_BYPASS */
-#define ARIZONA_MICB3_BYPASS_WIDTH                    1  /* MICB3_BYPASS */
-#define ARIZONA_MICB3_ENA                        0x0001  /* MICB3_ENA */
-#define ARIZONA_MICB3_ENA_MASK                   0x0001  /* MICB3_ENA */
-#define ARIZONA_MICB3_ENA_SHIFT                       0  /* MICB3_ENA */
-#define ARIZONA_MICB3_ENA_WIDTH                       1  /* MICB3_ENA */
-
-/*
- * R659 (0x293) - Accessory Detect Mode 1
- */
-#define ARIZONA_ACCDET_SRC                       0x2000  /* ACCDET_SRC */
-#define ARIZONA_ACCDET_SRC_MASK                  0x2000  /* ACCDET_SRC */
-#define ARIZONA_ACCDET_SRC_SHIFT                     13  /* ACCDET_SRC */
-#define ARIZONA_ACCDET_SRC_WIDTH                      1  /* ACCDET_SRC */
-#define ARIZONA_ACCDET_MODE_MASK                 0x0003  /* ACCDET_MODE - [1:0] */
-#define ARIZONA_ACCDET_MODE_SHIFT                     0  /* ACCDET_MODE - [1:0] */
-#define ARIZONA_ACCDET_MODE_WIDTH                     2  /* ACCDET_MODE - [1:0] */
-
-/*
- * R667 (0x29B) - Headphone Detect 1
- */
-#define ARIZONA_HP_STEP_SIZE                     0x0100  /* HP_STEP_SIZE */
-#define ARIZONA_HP_STEP_SIZE_MASK                0x0100  /* HP_STEP_SIZE */
-#define ARIZONA_HP_STEP_SIZE_SHIFT                    8  /* HP_STEP_SIZE */
-#define ARIZONA_HP_STEP_SIZE_WIDTH                    1  /* HP_STEP_SIZE */
-#define ARIZONA_HP_HOLDTIME_MASK                 0x00E0  /* HP_HOLDTIME - [7:5] */
-#define ARIZONA_HP_HOLDTIME_SHIFT                     5  /* HP_HOLDTIME - [7:5] */
-#define ARIZONA_HP_HOLDTIME_WIDTH                     3  /* HP_HOLDTIME - [7:5] */
-#define ARIZONA_HP_CLK_DIV_MASK                  0x0018  /* HP_CLK_DIV - [4:3] */
-#define ARIZONA_HP_CLK_DIV_SHIFT                      3  /* HP_CLK_DIV - [4:3] */
-#define ARIZONA_HP_CLK_DIV_WIDTH                      2  /* HP_CLK_DIV - [4:3] */
-#define ARIZONA_HP_IDAC_STEER                    0x0004  /* HP_IDAC_STEER */
-#define ARIZONA_HP_IDAC_STEER_MASK               0x0004  /* HP_IDAC_STEER */
-#define ARIZONA_HP_IDAC_STEER_SHIFT                   2  /* HP_IDAC_STEER */
-#define ARIZONA_HP_IDAC_STEER_WIDTH                   1  /* HP_IDAC_STEER */
-#define ARIZONA_HP_RATE                          0x0002  /* HP_RATE */
-#define ARIZONA_HP_RATE_MASK                     0x0002  /* HP_RATE */
-#define ARIZONA_HP_RATE_SHIFT                         1  /* HP_RATE */
-#define ARIZONA_HP_RATE_WIDTH                         1  /* HP_RATE */
-#define ARIZONA_HP_POLL                          0x0001  /* HP_POLL */
-#define ARIZONA_HP_POLL_MASK                     0x0001  /* HP_POLL */
-#define ARIZONA_HP_POLL_SHIFT                         0  /* HP_POLL */
-#define ARIZONA_HP_POLL_WIDTH                         1  /* HP_POLL */
-
-/*
- * R668 (0x29C) - Headphone Detect 2
- */
-#define ARIZONA_HP_DONE                          0x0080  /* HP_DONE */
-#define ARIZONA_HP_DONE_MASK                     0x0080  /* HP_DONE */
-#define ARIZONA_HP_DONE_SHIFT                         7  /* HP_DONE */
-#define ARIZONA_HP_DONE_WIDTH                         1  /* HP_DONE */
-#define ARIZONA_HP_LVL_MASK                      0x007F  /* HP_LVL - [6:0] */
-#define ARIZONA_HP_LVL_SHIFT                          0  /* HP_LVL - [6:0] */
-#define ARIZONA_HP_LVL_WIDTH                          7  /* HP_LVL - [6:0] */
-
-/*
- * R675 (0x2A3) - Mic Detect 1
- */
-#define ARIZONA_MICD_BIAS_STARTTIME_MASK         0xF000  /* MICD_BIAS_STARTTIME - [15:12] */
-#define ARIZONA_MICD_BIAS_STARTTIME_SHIFT            12  /* MICD_BIAS_STARTTIME - [15:12] */
-#define ARIZONA_MICD_BIAS_STARTTIME_WIDTH             4  /* MICD_BIAS_STARTTIME - [15:12] */
-#define ARIZONA_MICD_RATE_MASK                   0x0F00  /* MICD_RATE - [11:8] */
-#define ARIZONA_MICD_RATE_SHIFT                       8  /* MICD_RATE - [11:8] */
-#define ARIZONA_MICD_RATE_WIDTH                       4  /* MICD_RATE - [11:8] */
-#define ARIZONA_MICD_BIAS_SRC_MASK               0x0030  /* MICD_BIAS_SRC - [5:4] */
-#define ARIZONA_MICD_BIAS_SRC_SHIFT                   4  /* MICD_BIAS_SRC - [5:4] */
-#define ARIZONA_MICD_BIAS_SRC_WIDTH                   2  /* MICD_BIAS_SRC - [5:4] */
-#define ARIZONA_MICD_DBTIME                      0x0002  /* MICD_DBTIME */
-#define ARIZONA_MICD_DBTIME_MASK                 0x0002  /* MICD_DBTIME */
-#define ARIZONA_MICD_DBTIME_SHIFT                     1  /* MICD_DBTIME */
-#define ARIZONA_MICD_DBTIME_WIDTH                     1  /* MICD_DBTIME */
-#define ARIZONA_MICD_ENA                         0x0001  /* MICD_ENA */
-#define ARIZONA_MICD_ENA_MASK                    0x0001  /* MICD_ENA */
-#define ARIZONA_MICD_ENA_SHIFT                        0  /* MICD_ENA */
-#define ARIZONA_MICD_ENA_WIDTH                        1  /* MICD_ENA */
-
-/*
- * R676 (0x2A4) - Mic Detect 2
- */
-#define ARIZONA_MICD_LVL_SEL_MASK                0x00FF  /* MICD_LVL_SEL - [7:0] */
-#define ARIZONA_MICD_LVL_SEL_SHIFT                    0  /* MICD_LVL_SEL - [7:0] */
-#define ARIZONA_MICD_LVL_SEL_WIDTH                    8  /* MICD_LVL_SEL - [7:0] */
-
-/*
- * R677 (0x2A5) - Mic Detect 3
- */
-#define ARIZONA_MICD_LVL_MASK                    0x07FC  /* MICD_LVL - [10:2] */
-#define ARIZONA_MICD_LVL_SHIFT                        2  /* MICD_LVL - [10:2] */
-#define ARIZONA_MICD_LVL_WIDTH                        9  /* MICD_LVL - [10:2] */
-#define ARIZONA_MICD_VALID                       0x0002  /* MICD_VALID */
-#define ARIZONA_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
-#define ARIZONA_MICD_VALID_SHIFT                      1  /* MICD_VALID */
-#define ARIZONA_MICD_VALID_WIDTH                      1  /* MICD_VALID */
-#define ARIZONA_MICD_STS                         0x0001  /* MICD_STS */
-#define ARIZONA_MICD_STS_MASK                    0x0001  /* MICD_STS */
-#define ARIZONA_MICD_STS_SHIFT                        0  /* MICD_STS */
-#define ARIZONA_MICD_STS_WIDTH                        1  /* MICD_STS */
-
-/*
- * R707 (0x2C3) - Mic noise mix control 1
- */
-#define ARIZONA_MICMUTE_RATE_MASK                0x7800  /* MICMUTE_RATE - [14:11] */
-#define ARIZONA_MICMUTE_RATE_SHIFT                   11  /* MICMUTE_RATE - [14:11] */
-#define ARIZONA_MICMUTE_RATE_WIDTH                    4  /* MICMUTE_RATE - [14:11] */
-#define ARIZONA_MICMUTE_MIX_ENA                  0x0040  /* MICMUTE_MIX_ENA */
-#define ARIZONA_MICMUTE_MIX_ENA_MASK             0x0040  /* MICMUTE_MIX_ENA */
-#define ARIZONA_MICMUTE_MIX_ENA_SHIFT                 6  /* MICMUTE_MIX_ENA */
-#define ARIZONA_MICMUTE_MIX_ENA_WIDTH                 1  /* MICMUTE_MIX_ENA */
-
-/*
- * R715 (0x2CB) - Isolation control
- */
-#define ARIZONA_ISOLATE_DCVDD1                   0x0001  /* ISOLATE_DCVDD1 */
-#define ARIZONA_ISOLATE_DCVDD1_MASK              0x0001  /* ISOLATE_DCVDD1 */
-#define ARIZONA_ISOLATE_DCVDD1_SHIFT                  0  /* ISOLATE_DCVDD1 */
-#define ARIZONA_ISOLATE_DCVDD1_WIDTH                  1  /* ISOLATE_DCVDD1 */
-
-/*
- * R723 (0x2D3) - Jack detect analogue
- */
-#define ARIZONA_JD2_ENA                          0x0002  /* JD2_ENA */
-#define ARIZONA_JD2_ENA_MASK                     0x0002  /* JD2_ENA */
-#define ARIZONA_JD2_ENA_SHIFT                         1  /* JD2_ENA */
-#define ARIZONA_JD2_ENA_WIDTH                         1  /* JD2_ENA */
-#define ARIZONA_JD1_ENA                          0x0001  /* JD1_ENA */
-#define ARIZONA_JD1_ENA_MASK                     0x0001  /* JD1_ENA */
-#define ARIZONA_JD1_ENA_SHIFT                         0  /* JD1_ENA */
-#define ARIZONA_JD1_ENA_WIDTH                         1  /* JD1_ENA */
-
-/*
- * R768 (0x300) - Input Enables
- */
-#define ARIZONA_IN4L_ENA                         0x0080  /* IN4L_ENA */
-#define ARIZONA_IN4L_ENA_MASK                    0x0080  /* IN4L_ENA */
-#define ARIZONA_IN4L_ENA_SHIFT                        7  /* IN4L_ENA */
-#define ARIZONA_IN4L_ENA_WIDTH                        1  /* IN4L_ENA */
-#define ARIZONA_IN4R_ENA                         0x0040  /* IN4R_ENA */
-#define ARIZONA_IN4R_ENA_MASK                    0x0040  /* IN4R_ENA */
-#define ARIZONA_IN4R_ENA_SHIFT                        6  /* IN4R_ENA */
-#define ARIZONA_IN4R_ENA_WIDTH                        1  /* IN4R_ENA */
-#define ARIZONA_IN3L_ENA                         0x0020  /* IN3L_ENA */
-#define ARIZONA_IN3L_ENA_MASK                    0x0020  /* IN3L_ENA */
-#define ARIZONA_IN3L_ENA_SHIFT                        5  /* IN3L_ENA */
-#define ARIZONA_IN3L_ENA_WIDTH                        1  /* IN3L_ENA */
-#define ARIZONA_IN3R_ENA                         0x0010  /* IN3R_ENA */
-#define ARIZONA_IN3R_ENA_MASK                    0x0010  /* IN3R_ENA */
-#define ARIZONA_IN3R_ENA_SHIFT                        4  /* IN3R_ENA */
-#define ARIZONA_IN3R_ENA_WIDTH                        1  /* IN3R_ENA */
-#define ARIZONA_IN2L_ENA                         0x0008  /* IN2L_ENA */
-#define ARIZONA_IN2L_ENA_MASK                    0x0008  /* IN2L_ENA */
-#define ARIZONA_IN2L_ENA_SHIFT                        3  /* IN2L_ENA */
-#define ARIZONA_IN2L_ENA_WIDTH                        1  /* IN2L_ENA */
-#define ARIZONA_IN2R_ENA                         0x0004  /* IN2R_ENA */
-#define ARIZONA_IN2R_ENA_MASK                    0x0004  /* IN2R_ENA */
-#define ARIZONA_IN2R_ENA_SHIFT                        2  /* IN2R_ENA */
-#define ARIZONA_IN2R_ENA_WIDTH                        1  /* IN2R_ENA */
-#define ARIZONA_IN1L_ENA                         0x0002  /* IN1L_ENA */
-#define ARIZONA_IN1L_ENA_MASK                    0x0002  /* IN1L_ENA */
-#define ARIZONA_IN1L_ENA_SHIFT                        1  /* IN1L_ENA */
-#define ARIZONA_IN1L_ENA_WIDTH                        1  /* IN1L_ENA */
-#define ARIZONA_IN1R_ENA                         0x0001  /* IN1R_ENA */
-#define ARIZONA_IN1R_ENA_MASK                    0x0001  /* IN1R_ENA */
-#define ARIZONA_IN1R_ENA_SHIFT                        0  /* IN1R_ENA */
-#define ARIZONA_IN1R_ENA_WIDTH                        1  /* IN1R_ENA */
-
-/*
- * R776 (0x308) - Input Rate
- */
-#define ARIZONA_IN_RATE_MASK                     0x7800  /* IN_RATE - [14:11] */
-#define ARIZONA_IN_RATE_SHIFT                        11  /* IN_RATE - [14:11] */
-#define ARIZONA_IN_RATE_WIDTH                         4  /* IN_RATE - [14:11] */
-
-/*
- * R777 (0x309) - Input Volume Ramp
- */
-#define ARIZONA_IN_VD_RAMP_MASK                  0x0070  /* IN_VD_RAMP - [6:4] */
-#define ARIZONA_IN_VD_RAMP_SHIFT                      4  /* IN_VD_RAMP - [6:4] */
-#define ARIZONA_IN_VD_RAMP_WIDTH                      3  /* IN_VD_RAMP - [6:4] */
-#define ARIZONA_IN_VI_RAMP_MASK                  0x0007  /* IN_VI_RAMP - [2:0] */
-#define ARIZONA_IN_VI_RAMP_SHIFT                      0  /* IN_VI_RAMP - [2:0] */
-#define ARIZONA_IN_VI_RAMP_WIDTH                      3  /* IN_VI_RAMP - [2:0] */
-
-/*
- * R784 (0x310) - IN1L Control
- */
-#define ARIZONA_IN1_OSR_MASK                     0x6000  /* IN1_OSR - [14:13] */
-#define ARIZONA_IN1_OSR_SHIFT                        13  /* IN1_OSR - [14:13] */
-#define ARIZONA_IN1_OSR_WIDTH                         2  /* IN1_OSR - [14:13] */
-#define ARIZONA_IN1_DMIC_SUP_MASK                0x1800  /* IN1_DMIC_SUP - [12:11] */
-#define ARIZONA_IN1_DMIC_SUP_SHIFT                   11  /* IN1_DMIC_SUP - [12:11] */
-#define ARIZONA_IN1_DMIC_SUP_WIDTH                    2  /* IN1_DMIC_SUP - [12:11] */
-#define ARIZONA_IN1_MODE_MASK                    0x0600  /* IN1_MODE - [10:9] */
-#define ARIZONA_IN1_MODE_SHIFT                        9  /* IN1_MODE - [10:9] */
-#define ARIZONA_IN1_MODE_WIDTH                        2  /* IN1_MODE - [10:9] */
-#define ARIZONA_IN1L_PGA_VOL_MASK                0x00FE  /* IN1L_PGA_VOL - [7:1] */
-#define ARIZONA_IN1L_PGA_VOL_SHIFT                    1  /* IN1L_PGA_VOL - [7:1] */
-#define ARIZONA_IN1L_PGA_VOL_WIDTH                    7  /* IN1L_PGA_VOL - [7:1] */
-
-/*
- * R785 (0x311) - ADC Digital Volume 1L
- */
-#define ARIZONA_IN_VU                            0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_MASK                       0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_SHIFT                           9  /* IN_VU */
-#define ARIZONA_IN_VU_WIDTH                           1  /* IN_VU */
-#define ARIZONA_IN1L_MUTE                        0x0100  /* IN1L_MUTE */
-#define ARIZONA_IN1L_MUTE_MASK                   0x0100  /* IN1L_MUTE */
-#define ARIZONA_IN1L_MUTE_SHIFT                       8  /* IN1L_MUTE */
-#define ARIZONA_IN1L_MUTE_WIDTH                       1  /* IN1L_MUTE */
-#define ARIZONA_IN1L_DIG_VOL_MASK                0x00FF  /* IN1L_DIG_VOL - [7:0] */
-#define ARIZONA_IN1L_DIG_VOL_SHIFT                    0  /* IN1L_DIG_VOL - [7:0] */
-#define ARIZONA_IN1L_DIG_VOL_WIDTH                    8  /* IN1L_DIG_VOL - [7:0] */
-
-/*
- * R786 (0x312) - DMIC1L Control
- */
-#define ARIZONA_IN1_DMICL_DLY_MASK               0x003F  /* IN1_DMICL_DLY - [5:0] */
-#define ARIZONA_IN1_DMICL_DLY_SHIFT                   0  /* IN1_DMICL_DLY - [5:0] */
-#define ARIZONA_IN1_DMICL_DLY_WIDTH                   6  /* IN1_DMICL_DLY - [5:0] */
-
-/*
- * R788 (0x314) - IN1R Control
- */
-#define ARIZONA_IN1R_PGA_VOL_MASK                0x00FE  /* IN1R_PGA_VOL - [7:1] */
-#define ARIZONA_IN1R_PGA_VOL_SHIFT                    1  /* IN1R_PGA_VOL - [7:1] */
-#define ARIZONA_IN1R_PGA_VOL_WIDTH                    7  /* IN1R_PGA_VOL - [7:1] */
-
-/*
- * R789 (0x315) - ADC Digital Volume 1R
- */
-#define ARIZONA_IN_VU                            0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_MASK                       0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_SHIFT                           9  /* IN_VU */
-#define ARIZONA_IN_VU_WIDTH                           1  /* IN_VU */
-#define ARIZONA_IN1R_MUTE                        0x0100  /* IN1R_MUTE */
-#define ARIZONA_IN1R_MUTE_MASK                   0x0100  /* IN1R_MUTE */
-#define ARIZONA_IN1R_MUTE_SHIFT                       8  /* IN1R_MUTE */
-#define ARIZONA_IN1R_MUTE_WIDTH                       1  /* IN1R_MUTE */
-#define ARIZONA_IN1R_DIG_VOL_MASK                0x00FF  /* IN1R_DIG_VOL - [7:0] */
-#define ARIZONA_IN1R_DIG_VOL_SHIFT                    0  /* IN1R_DIG_VOL - [7:0] */
-#define ARIZONA_IN1R_DIG_VOL_WIDTH                    8  /* IN1R_DIG_VOL - [7:0] */
-
-/*
- * R790 (0x316) - DMIC1R Control
- */
-#define ARIZONA_IN1_DMICR_DLY_MASK               0x003F  /* IN1_DMICR_DLY - [5:0] */
-#define ARIZONA_IN1_DMICR_DLY_SHIFT                   0  /* IN1_DMICR_DLY - [5:0] */
-#define ARIZONA_IN1_DMICR_DLY_WIDTH                   6  /* IN1_DMICR_DLY - [5:0] */
-
-/*
- * R792 (0x318) - IN2L Control
- */
-#define ARIZONA_IN2_OSR_MASK                     0x6000  /* IN2_OSR - [14:13] */
-#define ARIZONA_IN2_OSR_SHIFT                        13  /* IN2_OSR - [14:13] */
-#define ARIZONA_IN2_OSR_WIDTH                         2  /* IN2_OSR - [14:13] */
-#define ARIZONA_IN2_DMIC_SUP_MASK                0x1800  /* IN2_DMIC_SUP - [12:11] */
-#define ARIZONA_IN2_DMIC_SUP_SHIFT                   11  /* IN2_DMIC_SUP - [12:11] */
-#define ARIZONA_IN2_DMIC_SUP_WIDTH                    2  /* IN2_DMIC_SUP - [12:11] */
-#define ARIZONA_IN2_MODE_MASK                    0x0600  /* IN2_MODE - [10:9] */
-#define ARIZONA_IN2_MODE_SHIFT                        9  /* IN2_MODE - [10:9] */
-#define ARIZONA_IN2_MODE_WIDTH                        2  /* IN2_MODE - [10:9] */
-#define ARIZONA_IN2L_PGA_VOL_MASK                0x00FE  /* IN2L_PGA_VOL - [7:1] */
-#define ARIZONA_IN2L_PGA_VOL_SHIFT                    1  /* IN2L_PGA_VOL - [7:1] */
-#define ARIZONA_IN2L_PGA_VOL_WIDTH                    7  /* IN2L_PGA_VOL - [7:1] */
-
-/*
- * R793 (0x319) - ADC Digital Volume 2L
- */
-#define ARIZONA_IN_VU                            0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_MASK                       0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_SHIFT                           9  /* IN_VU */
-#define ARIZONA_IN_VU_WIDTH                           1  /* IN_VU */
-#define ARIZONA_IN2L_MUTE                        0x0100  /* IN2L_MUTE */
-#define ARIZONA_IN2L_MUTE_MASK                   0x0100  /* IN2L_MUTE */
-#define ARIZONA_IN2L_MUTE_SHIFT                       8  /* IN2L_MUTE */
-#define ARIZONA_IN2L_MUTE_WIDTH                       1  /* IN2L_MUTE */
-#define ARIZONA_IN2L_DIG_VOL_MASK                0x00FF  /* IN2L_DIG_VOL - [7:0] */
-#define ARIZONA_IN2L_DIG_VOL_SHIFT                    0  /* IN2L_DIG_VOL - [7:0] */
-#define ARIZONA_IN2L_DIG_VOL_WIDTH                    8  /* IN2L_DIG_VOL - [7:0] */
-
-/*
- * R794 (0x31A) - DMIC2L Control
- */
-#define ARIZONA_IN2_DMICL_DLY_MASK               0x003F  /* IN2_DMICL_DLY - [5:0] */
-#define ARIZONA_IN2_DMICL_DLY_SHIFT                   0  /* IN2_DMICL_DLY - [5:0] */
-#define ARIZONA_IN2_DMICL_DLY_WIDTH                   6  /* IN2_DMICL_DLY - [5:0] */
-
-/*
- * R796 (0x31C) - IN2R Control
- */
-#define ARIZONA_IN2R_PGA_VOL_MASK                0x00FE  /* IN2R_PGA_VOL - [7:1] */
-#define ARIZONA_IN2R_PGA_VOL_SHIFT                    1  /* IN2R_PGA_VOL - [7:1] */
-#define ARIZONA_IN2R_PGA_VOL_WIDTH                    7  /* IN2R_PGA_VOL - [7:1] */
-
-/*
- * R797 (0x31D) - ADC Digital Volume 2R
- */
-#define ARIZONA_IN_VU                            0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_MASK                       0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_SHIFT                           9  /* IN_VU */
-#define ARIZONA_IN_VU_WIDTH                           1  /* IN_VU */
-#define ARIZONA_IN2R_MUTE                        0x0100  /* IN2R_MUTE */
-#define ARIZONA_IN2R_MUTE_MASK                   0x0100  /* IN2R_MUTE */
-#define ARIZONA_IN2R_MUTE_SHIFT                       8  /* IN2R_MUTE */
-#define ARIZONA_IN2R_MUTE_WIDTH                       1  /* IN2R_MUTE */
-#define ARIZONA_IN2R_DIG_VOL_MASK                0x00FF  /* IN2R_DIG_VOL - [7:0] */
-#define ARIZONA_IN2R_DIG_VOL_SHIFT                    0  /* IN2R_DIG_VOL - [7:0] */
-#define ARIZONA_IN2R_DIG_VOL_WIDTH                    8  /* IN2R_DIG_VOL - [7:0] */
-
-/*
- * R798 (0x31E) - DMIC2R Control
- */
-#define ARIZONA_IN2_DMICR_DLY_MASK               0x003F  /* IN2_DMICR_DLY - [5:0] */
-#define ARIZONA_IN2_DMICR_DLY_SHIFT                   0  /* IN2_DMICR_DLY - [5:0] */
-#define ARIZONA_IN2_DMICR_DLY_WIDTH                   6  /* IN2_DMICR_DLY - [5:0] */
-
-/*
- * R800 (0x320) - IN3L Control
- */
-#define ARIZONA_IN3_OSR_MASK                     0x6000  /* IN3_OSR - [14:13] */
-#define ARIZONA_IN3_OSR_SHIFT                        13  /* IN3_OSR - [14:13] */
-#define ARIZONA_IN3_OSR_WIDTH                         2  /* IN3_OSR - [14:13] */
-#define ARIZONA_IN3_DMIC_SUP_MASK                0x1800  /* IN3_DMIC_SUP - [12:11] */
-#define ARIZONA_IN3_DMIC_SUP_SHIFT                   11  /* IN3_DMIC_SUP - [12:11] */
-#define ARIZONA_IN3_DMIC_SUP_WIDTH                    2  /* IN3_DMIC_SUP - [12:11] */
-#define ARIZONA_IN3_MODE_MASK                    0x0600  /* IN3_MODE - [10:9] */
-#define ARIZONA_IN3_MODE_SHIFT                        9  /* IN3_MODE - [10:9] */
-#define ARIZONA_IN3_MODE_WIDTH                        2  /* IN3_MODE - [10:9] */
-#define ARIZONA_IN3L_PGA_VOL_MASK                0x00FE  /* IN3L_PGA_VOL - [7:1] */
-#define ARIZONA_IN3L_PGA_VOL_SHIFT                    1  /* IN3L_PGA_VOL - [7:1] */
-#define ARIZONA_IN3L_PGA_VOL_WIDTH                    7  /* IN3L_PGA_VOL - [7:1] */
-
-/*
- * R801 (0x321) - ADC Digital Volume 3L
- */
-#define ARIZONA_IN_VU                            0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_MASK                       0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_SHIFT                           9  /* IN_VU */
-#define ARIZONA_IN_VU_WIDTH                           1  /* IN_VU */
-#define ARIZONA_IN3L_MUTE                        0x0100  /* IN3L_MUTE */
-#define ARIZONA_IN3L_MUTE_MASK                   0x0100  /* IN3L_MUTE */
-#define ARIZONA_IN3L_MUTE_SHIFT                       8  /* IN3L_MUTE */
-#define ARIZONA_IN3L_MUTE_WIDTH                       1  /* IN3L_MUTE */
-#define ARIZONA_IN3L_DIG_VOL_MASK                0x00FF  /* IN3L_DIG_VOL - [7:0] */
-#define ARIZONA_IN3L_DIG_VOL_SHIFT                    0  /* IN3L_DIG_VOL - [7:0] */
-#define ARIZONA_IN3L_DIG_VOL_WIDTH                    8  /* IN3L_DIG_VOL - [7:0] */
-
-/*
- * R802 (0x322) - DMIC3L Control
- */
-#define ARIZONA_IN3_DMICL_DLY_MASK               0x003F  /* IN3_DMICL_DLY - [5:0] */
-#define ARIZONA_IN3_DMICL_DLY_SHIFT                   0  /* IN3_DMICL_DLY - [5:0] */
-#define ARIZONA_IN3_DMICL_DLY_WIDTH                   6  /* IN3_DMICL_DLY - [5:0] */
-
-/*
- * R804 (0x324) - IN3R Control
- */
-#define ARIZONA_IN3R_PGA_VOL_MASK                0x00FE  /* IN3R_PGA_VOL - [7:1] */
-#define ARIZONA_IN3R_PGA_VOL_SHIFT                    1  /* IN3R_PGA_VOL - [7:1] */
-#define ARIZONA_IN3R_PGA_VOL_WIDTH                    7  /* IN3R_PGA_VOL - [7:1] */
-
-/*
- * R805 (0x325) - ADC Digital Volume 3R
- */
-#define ARIZONA_IN_VU                            0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_MASK                       0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_SHIFT                           9  /* IN_VU */
-#define ARIZONA_IN_VU_WIDTH                           1  /* IN_VU */
-#define ARIZONA_IN3R_MUTE                        0x0100  /* IN3R_MUTE */
-#define ARIZONA_IN3R_MUTE_MASK                   0x0100  /* IN3R_MUTE */
-#define ARIZONA_IN3R_MUTE_SHIFT                       8  /* IN3R_MUTE */
-#define ARIZONA_IN3R_MUTE_WIDTH                       1  /* IN3R_MUTE */
-#define ARIZONA_IN3R_DIG_VOL_MASK                0x00FF  /* IN3R_DIG_VOL - [7:0] */
-#define ARIZONA_IN3R_DIG_VOL_SHIFT                    0  /* IN3R_DIG_VOL - [7:0] */
-#define ARIZONA_IN3R_DIG_VOL_WIDTH                    8  /* IN3R_DIG_VOL - [7:0] */
-
-/*
- * R806 (0x326) - DMIC3R Control
- */
-#define ARIZONA_IN3_DMICR_DLY_MASK               0x003F  /* IN3_DMICR_DLY - [5:0] */
-#define ARIZONA_IN3_DMICR_DLY_SHIFT                   0  /* IN3_DMICR_DLY - [5:0] */
-#define ARIZONA_IN3_DMICR_DLY_WIDTH                   6  /* IN3_DMICR_DLY - [5:0] */
-
-/*
- * R808 (0x328) - IN4 Control
- */
-#define ARIZONA_IN4_OSR_MASK                     0x6000  /* IN4_OSR - [14:13] */
-#define ARIZONA_IN4_OSR_SHIFT                        13  /* IN4_OSR - [14:13] */
-#define ARIZONA_IN4_OSR_WIDTH                         2  /* IN4_OSR - [14:13] */
-#define ARIZONA_IN4_DMIC_SUP_MASK                0x1800  /* IN4_DMIC_SUP - [12:11] */
-#define ARIZONA_IN4_DMIC_SUP_SHIFT                   11  /* IN4_DMIC_SUP - [12:11] */
-#define ARIZONA_IN4_DMIC_SUP_WIDTH                    2  /* IN4_DMIC_SUP - [12:11] */
-
-/*
- * R809 (0x329) - ADC Digital Volume 4L
- */
-#define ARIZONA_IN_VU                            0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_MASK                       0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_SHIFT                           9  /* IN_VU */
-#define ARIZONA_IN_VU_WIDTH                           1  /* IN_VU */
-#define ARIZONA_IN4L_MUTE                        0x0100  /* IN4L_MUTE */
-#define ARIZONA_IN4L_MUTE_MASK                   0x0100  /* IN4L_MUTE */
-#define ARIZONA_IN4L_MUTE_SHIFT                       8  /* IN4L_MUTE */
-#define ARIZONA_IN4L_MUTE_WIDTH                       1  /* IN4L_MUTE */
-#define ARIZONA_IN4L_DIG_VOL_MASK                0x00FF  /* IN4L_DIG_VOL - [7:0] */
-#define ARIZONA_IN4L_DIG_VOL_SHIFT                    0  /* IN4L_DIG_VOL - [7:0] */
-#define ARIZONA_IN4L_DIG_VOL_WIDTH                    8  /* IN4L_DIG_VOL - [7:0] */
-
-/*
- * R810 (0x32A) - DMIC4L Control
- */
-#define ARIZONA_IN4L_DMIC_DLY_MASK               0x003F  /* IN4L_DMIC_DLY - [5:0] */
-#define ARIZONA_IN4L_DMIC_DLY_SHIFT                   0  /* IN4L_DMIC_DLY - [5:0] */
-#define ARIZONA_IN4L_DMIC_DLY_WIDTH                   6  /* IN4L_DMIC_DLY - [5:0] */
-
-/*
- * R813 (0x32D) - ADC Digital Volume 4R
- */
-#define ARIZONA_IN_VU                            0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_MASK                       0x0200  /* IN_VU */
-#define ARIZONA_IN_VU_SHIFT                           9  /* IN_VU */
-#define ARIZONA_IN_VU_WIDTH                           1  /* IN_VU */
-#define ARIZONA_IN4R_MUTE                        0x0100  /* IN4R_MUTE */
-#define ARIZONA_IN4R_MUTE_MASK                   0x0100  /* IN4R_MUTE */
-#define ARIZONA_IN4R_MUTE_SHIFT                       8  /* IN4R_MUTE */
-#define ARIZONA_IN4R_MUTE_WIDTH                       1  /* IN4R_MUTE */
-#define ARIZONA_IN4R_DIG_VOL_MASK                0x00FF  /* IN4R_DIG_VOL - [7:0] */
-#define ARIZONA_IN4R_DIG_VOL_SHIFT                    0  /* IN4R_DIG_VOL - [7:0] */
-#define ARIZONA_IN4R_DIG_VOL_WIDTH                    8  /* IN4R_DIG_VOL - [7:0] */
-
-/*
- * R814 (0x32E) - DMIC4R Control
- */
-#define ARIZONA_IN4R_DMIC_DLY_MASK               0x003F  /* IN4R_DMIC_DLY - [5:0] */
-#define ARIZONA_IN4R_DMIC_DLY_SHIFT                   0  /* IN4R_DMIC_DLY - [5:0] */
-#define ARIZONA_IN4R_DMIC_DLY_WIDTH                   6  /* IN4R_DMIC_DLY - [5:0] */
-
-/*
- * R1024 (0x400) - Output Enables 1
- */
-#define ARIZONA_OUT6L_ENA                        0x0800  /* OUT6L_ENA */
-#define ARIZONA_OUT6L_ENA_MASK                   0x0800  /* OUT6L_ENA */
-#define ARIZONA_OUT6L_ENA_SHIFT                      11  /* OUT6L_ENA */
-#define ARIZONA_OUT6L_ENA_WIDTH                       1  /* OUT6L_ENA */
-#define ARIZONA_OUT6R_ENA                        0x0400  /* OUT6R_ENA */
-#define ARIZONA_OUT6R_ENA_MASK                   0x0400  /* OUT6R_ENA */
-#define ARIZONA_OUT6R_ENA_SHIFT                      10  /* OUT6R_ENA */
-#define ARIZONA_OUT6R_ENA_WIDTH                       1  /* OUT6R_ENA */
-#define ARIZONA_OUT5L_ENA                        0x0200  /* OUT5L_ENA */
-#define ARIZONA_OUT5L_ENA_MASK                   0x0200  /* OUT5L_ENA */
-#define ARIZONA_OUT5L_ENA_SHIFT                       9  /* OUT5L_ENA */
-#define ARIZONA_OUT5L_ENA_WIDTH                       1  /* OUT5L_ENA */
-#define ARIZONA_OUT5R_ENA                        0x0100  /* OUT5R_ENA */
-#define ARIZONA_OUT5R_ENA_MASK                   0x0100  /* OUT5R_ENA */
-#define ARIZONA_OUT5R_ENA_SHIFT                       8  /* OUT5R_ENA */
-#define ARIZONA_OUT5R_ENA_WIDTH                       1  /* OUT5R_ENA */
-#define ARIZONA_OUT4L_ENA                        0x0080  /* OUT4L_ENA */
-#define ARIZONA_OUT4L_ENA_MASK                   0x0080  /* OUT4L_ENA */
-#define ARIZONA_OUT4L_ENA_SHIFT                       7  /* OUT4L_ENA */
-#define ARIZONA_OUT4L_ENA_WIDTH                       1  /* OUT4L_ENA */
-#define ARIZONA_OUT4R_ENA                        0x0040  /* OUT4R_ENA */
-#define ARIZONA_OUT4R_ENA_MASK                   0x0040  /* OUT4R_ENA */
-#define ARIZONA_OUT4R_ENA_SHIFT                       6  /* OUT4R_ENA */
-#define ARIZONA_OUT4R_ENA_WIDTH                       1  /* OUT4R_ENA */
-#define ARIZONA_OUT3L_ENA                        0x0020  /* OUT3L_ENA */
-#define ARIZONA_OUT3L_ENA_MASK                   0x0020  /* OUT3L_ENA */
-#define ARIZONA_OUT3L_ENA_SHIFT                       5  /* OUT3L_ENA */
-#define ARIZONA_OUT3L_ENA_WIDTH                       1  /* OUT3L_ENA */
-#define ARIZONA_OUT3R_ENA                        0x0010  /* OUT3R_ENA */
-#define ARIZONA_OUT3R_ENA_MASK                   0x0010  /* OUT3R_ENA */
-#define ARIZONA_OUT3R_ENA_SHIFT                       4  /* OUT3R_ENA */
-#define ARIZONA_OUT3R_ENA_WIDTH                       1  /* OUT3R_ENA */
-#define ARIZONA_OUT2L_ENA                        0x0008  /* OUT2L_ENA */
-#define ARIZONA_OUT2L_ENA_MASK                   0x0008  /* OUT2L_ENA */
-#define ARIZONA_OUT2L_ENA_SHIFT                       3  /* OUT2L_ENA */
-#define ARIZONA_OUT2L_ENA_WIDTH                       1  /* OUT2L_ENA */
-#define ARIZONA_OUT2R_ENA                        0x0004  /* OUT2R_ENA */
-#define ARIZONA_OUT2R_ENA_MASK                   0x0004  /* OUT2R_ENA */
-#define ARIZONA_OUT2R_ENA_SHIFT                       2  /* OUT2R_ENA */
-#define ARIZONA_OUT2R_ENA_WIDTH                       1  /* OUT2R_ENA */
-#define ARIZONA_OUT1L_ENA                        0x0002  /* OUT1L_ENA */
-#define ARIZONA_OUT1L_ENA_MASK                   0x0002  /* OUT1L_ENA */
-#define ARIZONA_OUT1L_ENA_SHIFT                       1  /* OUT1L_ENA */
-#define ARIZONA_OUT1L_ENA_WIDTH                       1  /* OUT1L_ENA */
-#define ARIZONA_OUT1R_ENA                        0x0001  /* OUT1R_ENA */
-#define ARIZONA_OUT1R_ENA_MASK                   0x0001  /* OUT1R_ENA */
-#define ARIZONA_OUT1R_ENA_SHIFT                       0  /* OUT1R_ENA */
-#define ARIZONA_OUT1R_ENA_WIDTH                       1  /* OUT1R_ENA */
-
-/*
- * R1025 (0x401) - Output Status 1
- */
-#define ARIZONA_OUT6L_ENA_STS                    0x0800  /* OUT6L_ENA_STS */
-#define ARIZONA_OUT6L_ENA_STS_MASK               0x0800  /* OUT6L_ENA_STS */
-#define ARIZONA_OUT6L_ENA_STS_SHIFT                  11  /* OUT6L_ENA_STS */
-#define ARIZONA_OUT6L_ENA_STS_WIDTH                   1  /* OUT6L_ENA_STS */
-#define ARIZONA_OUT6R_ENA_STS                    0x0400  /* OUT6R_ENA_STS */
-#define ARIZONA_OUT6R_ENA_STS_MASK               0x0400  /* OUT6R_ENA_STS */
-#define ARIZONA_OUT6R_ENA_STS_SHIFT                  10  /* OUT6R_ENA_STS */
-#define ARIZONA_OUT6R_ENA_STS_WIDTH                   1  /* OUT6R_ENA_STS */
-#define ARIZONA_OUT5L_ENA_STS                    0x0200  /* OUT5L_ENA_STS */
-#define ARIZONA_OUT5L_ENA_STS_MASK               0x0200  /* OUT5L_ENA_STS */
-#define ARIZONA_OUT5L_ENA_STS_SHIFT                   9  /* OUT5L_ENA_STS */
-#define ARIZONA_OUT5L_ENA_STS_WIDTH                   1  /* OUT5L_ENA_STS */
-#define ARIZONA_OUT5R_ENA_STS                    0x0100  /* OUT5R_ENA_STS */
-#define ARIZONA_OUT5R_ENA_STS_MASK               0x0100  /* OUT5R_ENA_STS */
-#define ARIZONA_OUT5R_ENA_STS_SHIFT                   8  /* OUT5R_ENA_STS */
-#define ARIZONA_OUT5R_ENA_STS_WIDTH                   1  /* OUT5R_ENA_STS */
-#define ARIZONA_OUT4L_ENA_STS                    0x0080  /* OUT4L_ENA_STS */
-#define ARIZONA_OUT4L_ENA_STS_MASK               0x0080  /* OUT4L_ENA_STS */
-#define ARIZONA_OUT4L_ENA_STS_SHIFT                   7  /* OUT4L_ENA_STS */
-#define ARIZONA_OUT4L_ENA_STS_WIDTH                   1  /* OUT4L_ENA_STS */
-#define ARIZONA_OUT4R_ENA_STS                    0x0040  /* OUT4R_ENA_STS */
-#define ARIZONA_OUT4R_ENA_STS_MASK               0x0040  /* OUT4R_ENA_STS */
-#define ARIZONA_OUT4R_ENA_STS_SHIFT                   6  /* OUT4R_ENA_STS */
-#define ARIZONA_OUT4R_ENA_STS_WIDTH                   1  /* OUT4R_ENA_STS */
-
-/*
- * R1032 (0x408) - Output Rate 1
- */
-#define ARIZONA_OUT_RATE_MASK                    0x7800  /* OUT_RATE - [14:11] */
-#define ARIZONA_OUT_RATE_SHIFT                       11  /* OUT_RATE - [14:11] */
-#define ARIZONA_OUT_RATE_WIDTH                        4  /* OUT_RATE - [14:11] */
-
-/*
- * R1033 (0x409) - Output Volume Ramp
- */
-#define ARIZONA_OUT_VD_RAMP_MASK                 0x0070  /* OUT_VD_RAMP - [6:4] */
-#define ARIZONA_OUT_VD_RAMP_SHIFT                     4  /* OUT_VD_RAMP - [6:4] */
-#define ARIZONA_OUT_VD_RAMP_WIDTH                     3  /* OUT_VD_RAMP - [6:4] */
-#define ARIZONA_OUT_VI_RAMP_MASK                 0x0007  /* OUT_VI_RAMP - [2:0] */
-#define ARIZONA_OUT_VI_RAMP_SHIFT                     0  /* OUT_VI_RAMP - [2:0] */
-#define ARIZONA_OUT_VI_RAMP_WIDTH                     3  /* OUT_VI_RAMP - [2:0] */
-
-/*
- * R1040 (0x410) - Output Path Config 1L
- */
-#define ARIZONA_OUT1_LP_MODE                     0x8000  /* OUT1_LP_MODE */
-#define ARIZONA_OUT1_LP_MODE_MASK                0x8000  /* OUT1_LP_MODE */
-#define ARIZONA_OUT1_LP_MODE_SHIFT                   15  /* OUT1_LP_MODE */
-#define ARIZONA_OUT1_LP_MODE_WIDTH                    1  /* OUT1_LP_MODE */
-#define ARIZONA_OUT1_OSR                         0x2000  /* OUT1_OSR */
-#define ARIZONA_OUT1_OSR_MASK                    0x2000  /* OUT1_OSR */
-#define ARIZONA_OUT1_OSR_SHIFT                       13  /* OUT1_OSR */
-#define ARIZONA_OUT1_OSR_WIDTH                        1  /* OUT1_OSR */
-#define ARIZONA_OUT1_MONO                        0x1000  /* OUT1_MONO */
-#define ARIZONA_OUT1_MONO_MASK                   0x1000  /* OUT1_MONO */
-#define ARIZONA_OUT1_MONO_SHIFT                      12  /* OUT1_MONO */
-#define ARIZONA_OUT1_MONO_WIDTH                       1  /* OUT1_MONO */
-#define ARIZONA_OUT1L_ANC_SRC_MASK               0x0C00  /* OUT1L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT1L_ANC_SRC_SHIFT                  10  /* OUT1L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT1L_ANC_SRC_WIDTH                   2  /* OUT1L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT1L_PGA_VOL_MASK               0x00FE  /* OUT1L_PGA_VOL - [7:1] */
-#define ARIZONA_OUT1L_PGA_VOL_SHIFT                   1  /* OUT1L_PGA_VOL - [7:1] */
-#define ARIZONA_OUT1L_PGA_VOL_WIDTH                   7  /* OUT1L_PGA_VOL - [7:1] */
-
-/*
- * R1041 (0x411) - DAC Digital Volume 1L
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT1L_MUTE                       0x0100  /* OUT1L_MUTE */
-#define ARIZONA_OUT1L_MUTE_MASK                  0x0100  /* OUT1L_MUTE */
-#define ARIZONA_OUT1L_MUTE_SHIFT                      8  /* OUT1L_MUTE */
-#define ARIZONA_OUT1L_MUTE_WIDTH                      1  /* OUT1L_MUTE */
-#define ARIZONA_OUT1L_VOL_MASK                   0x00FF  /* OUT1L_VOL - [7:0] */
-#define ARIZONA_OUT1L_VOL_SHIFT                       0  /* OUT1L_VOL - [7:0] */
-#define ARIZONA_OUT1L_VOL_WIDTH                       8  /* OUT1L_VOL - [7:0] */
-
-/*
- * R1042 (0x412) - DAC Volume Limit 1L
- */
-#define ARIZONA_OUT1L_VOL_LIM_MASK               0x00FF  /* OUT1L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT1L_VOL_LIM_SHIFT                   0  /* OUT1L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT1L_VOL_LIM_WIDTH                   8  /* OUT1L_VOL_LIM - [7:0] */
-
-/*
- * R1043 (0x413) - Noise Gate Select 1L
- */
-#define ARIZONA_OUT1L_NGATE_SRC_MASK             0x0FFF  /* OUT1L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT1L_NGATE_SRC_SHIFT                 0  /* OUT1L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT1L_NGATE_SRC_WIDTH                12  /* OUT1L_NGATE_SRC - [11:0] */
-
-/*
- * R1044 (0x414) - Output Path Config 1R
- */
-#define ARIZONA_OUT1R_ANC_SRC_MASK               0x0C00  /* OUT1R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT1R_ANC_SRC_SHIFT                  10  /* OUT1R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT1R_ANC_SRC_WIDTH                   2  /* OUT1R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT1R_PGA_VOL_MASK               0x00FE  /* OUT1R_PGA_VOL - [7:1] */
-#define ARIZONA_OUT1R_PGA_VOL_SHIFT                   1  /* OUT1R_PGA_VOL - [7:1] */
-#define ARIZONA_OUT1R_PGA_VOL_WIDTH                   7  /* OUT1R_PGA_VOL - [7:1] */
-
-/*
- * R1045 (0x415) - DAC Digital Volume 1R
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT1R_MUTE                       0x0100  /* OUT1R_MUTE */
-#define ARIZONA_OUT1R_MUTE_MASK                  0x0100  /* OUT1R_MUTE */
-#define ARIZONA_OUT1R_MUTE_SHIFT                      8  /* OUT1R_MUTE */
-#define ARIZONA_OUT1R_MUTE_WIDTH                      1  /* OUT1R_MUTE */
-#define ARIZONA_OUT1R_VOL_MASK                   0x00FF  /* OUT1R_VOL - [7:0] */
-#define ARIZONA_OUT1R_VOL_SHIFT                       0  /* OUT1R_VOL - [7:0] */
-#define ARIZONA_OUT1R_VOL_WIDTH                       8  /* OUT1R_VOL - [7:0] */
-
-/*
- * R1046 (0x416) - DAC Volume Limit 1R
- */
-#define ARIZONA_OUT1R_VOL_LIM_MASK               0x00FF  /* OUT1R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT1R_VOL_LIM_SHIFT                   0  /* OUT1R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT1R_VOL_LIM_WIDTH                   8  /* OUT1R_VOL_LIM - [7:0] */
-
-/*
- * R1047 (0x417) - Noise Gate Select 1R
- */
-#define ARIZONA_OUT1R_NGATE_SRC_MASK             0x0FFF  /* OUT1R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT1R_NGATE_SRC_SHIFT                 0  /* OUT1R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT1R_NGATE_SRC_WIDTH                12  /* OUT1R_NGATE_SRC - [11:0] */
-
-/*
- * R1048 (0x418) - Output Path Config 2L
- */
-#define ARIZONA_OUT2_LP_MODE                     0x8000  /* OUT2_LP_MODE */
-#define ARIZONA_OUT2_LP_MODE_MASK                0x8000  /* OUT2_LP_MODE */
-#define ARIZONA_OUT2_LP_MODE_SHIFT                   15  /* OUT2_LP_MODE */
-#define ARIZONA_OUT2_LP_MODE_WIDTH                    1  /* OUT2_LP_MODE */
-#define ARIZONA_OUT2_OSR                         0x2000  /* OUT2_OSR */
-#define ARIZONA_OUT2_OSR_MASK                    0x2000  /* OUT2_OSR */
-#define ARIZONA_OUT2_OSR_SHIFT                       13  /* OUT2_OSR */
-#define ARIZONA_OUT2_OSR_WIDTH                        1  /* OUT2_OSR */
-#define ARIZONA_OUT2_MONO                        0x1000  /* OUT2_MONO */
-#define ARIZONA_OUT2_MONO_MASK                   0x1000  /* OUT2_MONO */
-#define ARIZONA_OUT2_MONO_SHIFT                      12  /* OUT2_MONO */
-#define ARIZONA_OUT2_MONO_WIDTH                       1  /* OUT2_MONO */
-#define ARIZONA_OUT2L_ANC_SRC_MASK               0x0C00  /* OUT2L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT2L_ANC_SRC_SHIFT                  10  /* OUT2L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT2L_ANC_SRC_WIDTH                   2  /* OUT2L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT2L_PGA_VOL_MASK               0x00FE  /* OUT2L_PGA_VOL - [7:1] */
-#define ARIZONA_OUT2L_PGA_VOL_SHIFT                   1  /* OUT2L_PGA_VOL - [7:1] */
-#define ARIZONA_OUT2L_PGA_VOL_WIDTH                   7  /* OUT2L_PGA_VOL - [7:1] */
-
-/*
- * R1049 (0x419) - DAC Digital Volume 2L
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT2L_MUTE                       0x0100  /* OUT2L_MUTE */
-#define ARIZONA_OUT2L_MUTE_MASK                  0x0100  /* OUT2L_MUTE */
-#define ARIZONA_OUT2L_MUTE_SHIFT                      8  /* OUT2L_MUTE */
-#define ARIZONA_OUT2L_MUTE_WIDTH                      1  /* OUT2L_MUTE */
-#define ARIZONA_OUT2L_VOL_MASK                   0x00FF  /* OUT2L_VOL - [7:0] */
-#define ARIZONA_OUT2L_VOL_SHIFT                       0  /* OUT2L_VOL - [7:0] */
-#define ARIZONA_OUT2L_VOL_WIDTH                       8  /* OUT2L_VOL - [7:0] */
-
-/*
- * R1050 (0x41A) - DAC Volume Limit 2L
- */
-#define ARIZONA_OUT2L_VOL_LIM_MASK               0x00FF  /* OUT2L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT2L_VOL_LIM_SHIFT                   0  /* OUT2L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT2L_VOL_LIM_WIDTH                   8  /* OUT2L_VOL_LIM - [7:0] */
-
-/*
- * R1051 (0x41B) - Noise Gate Select 2L
- */
-#define ARIZONA_OUT2L_NGATE_SRC_MASK             0x0FFF  /* OUT2L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT2L_NGATE_SRC_SHIFT                 0  /* OUT2L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT2L_NGATE_SRC_WIDTH                12  /* OUT2L_NGATE_SRC - [11:0] */
-
-/*
- * R1052 (0x41C) - Output Path Config 2R
- */
-#define ARIZONA_OUT2R_ANC_SRC_MASK               0x0C00  /* OUT2R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT2R_ANC_SRC_SHIFT                  10  /* OUT2R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT2R_ANC_SRC_WIDTH                   2  /* OUT2R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT2R_PGA_VOL_MASK               0x00FE  /* OUT2R_PGA_VOL - [7:1] */
-#define ARIZONA_OUT2R_PGA_VOL_SHIFT                   1  /* OUT2R_PGA_VOL - [7:1] */
-#define ARIZONA_OUT2R_PGA_VOL_WIDTH                   7  /* OUT2R_PGA_VOL - [7:1] */
-
-/*
- * R1053 (0x41D) - DAC Digital Volume 2R
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT2R_MUTE                       0x0100  /* OUT2R_MUTE */
-#define ARIZONA_OUT2R_MUTE_MASK                  0x0100  /* OUT2R_MUTE */
-#define ARIZONA_OUT2R_MUTE_SHIFT                      8  /* OUT2R_MUTE */
-#define ARIZONA_OUT2R_MUTE_WIDTH                      1  /* OUT2R_MUTE */
-#define ARIZONA_OUT2R_VOL_MASK                   0x00FF  /* OUT2R_VOL - [7:0] */
-#define ARIZONA_OUT2R_VOL_SHIFT                       0  /* OUT2R_VOL - [7:0] */
-#define ARIZONA_OUT2R_VOL_WIDTH                       8  /* OUT2R_VOL - [7:0] */
-
-/*
- * R1054 (0x41E) - DAC Volume Limit 2R
- */
-#define ARIZONA_OUT2R_VOL_LIM_MASK               0x00FF  /* OUT2R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT2R_VOL_LIM_SHIFT                   0  /* OUT2R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT2R_VOL_LIM_WIDTH                   8  /* OUT2R_VOL_LIM - [7:0] */
-
-/*
- * R1055 (0x41F) - Noise Gate Select 2R
- */
-#define ARIZONA_OUT2R_NGATE_SRC_MASK             0x0FFF  /* OUT2R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT2R_NGATE_SRC_SHIFT                 0  /* OUT2R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT2R_NGATE_SRC_WIDTH                12  /* OUT2R_NGATE_SRC - [11:0] */
-
-/*
- * R1056 (0x420) - Output Path Config 3L
- */
-#define ARIZONA_OUT3_LP_MODE                     0x8000  /* OUT3_LP_MODE */
-#define ARIZONA_OUT3_LP_MODE_MASK                0x8000  /* OUT3_LP_MODE */
-#define ARIZONA_OUT3_LP_MODE_SHIFT                   15  /* OUT3_LP_MODE */
-#define ARIZONA_OUT3_LP_MODE_WIDTH                    1  /* OUT3_LP_MODE */
-#define ARIZONA_OUT3_OSR                         0x2000  /* OUT3_OSR */
-#define ARIZONA_OUT3_OSR_MASK                    0x2000  /* OUT3_OSR */
-#define ARIZONA_OUT3_OSR_SHIFT                       13  /* OUT3_OSR */
-#define ARIZONA_OUT3_OSR_WIDTH                        1  /* OUT3_OSR */
-#define ARIZONA_OUT3_MONO                        0x1000  /* OUT3_MONO */
-#define ARIZONA_OUT3_MONO_MASK                   0x1000  /* OUT3_MONO */
-#define ARIZONA_OUT3_MONO_SHIFT                      12  /* OUT3_MONO */
-#define ARIZONA_OUT3_MONO_WIDTH                       1  /* OUT3_MONO */
-#define ARIZONA_OUT3L_ANC_SRC_MASK               0x0C00  /* OUT3L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT3L_ANC_SRC_SHIFT                  10  /* OUT3L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT3L_ANC_SRC_WIDTH                   2  /* OUT3L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT3L_PGA_VOL_MASK               0x00FE  /* OUT3L_PGA_VOL - [7:1] */
-#define ARIZONA_OUT3L_PGA_VOL_SHIFT                   1  /* OUT3L_PGA_VOL - [7:1] */
-#define ARIZONA_OUT3L_PGA_VOL_WIDTH                   7  /* OUT3L_PGA_VOL - [7:1] */
-
-/*
- * R1057 (0x421) - DAC Digital Volume 3L
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT3L_MUTE                       0x0100  /* OUT3L_MUTE */
-#define ARIZONA_OUT3L_MUTE_MASK                  0x0100  /* OUT3L_MUTE */
-#define ARIZONA_OUT3L_MUTE_SHIFT                      8  /* OUT3L_MUTE */
-#define ARIZONA_OUT3L_MUTE_WIDTH                      1  /* OUT3L_MUTE */
-#define ARIZONA_OUT3L_VOL_MASK                   0x00FF  /* OUT3L_VOL - [7:0] */
-#define ARIZONA_OUT3L_VOL_SHIFT                       0  /* OUT3L_VOL - [7:0] */
-#define ARIZONA_OUT3L_VOL_WIDTH                       8  /* OUT3L_VOL - [7:0] */
-
-/*
- * R1058 (0x422) - DAC Volume Limit 3L
- */
-#define ARIZONA_OUT3L_VOL_LIM_MASK               0x00FF  /* OUT3L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT3L_VOL_LIM_SHIFT                   0  /* OUT3L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT3L_VOL_LIM_WIDTH                   8  /* OUT3L_VOL_LIM - [7:0] */
-
-/*
- * R1059 (0x423) - Noise Gate Select 3L
- */
-#define ARIZONA_OUT3_NGATE_SRC_MASK              0x0FFF  /* OUT3_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT3_NGATE_SRC_SHIFT                  0  /* OUT3_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT3_NGATE_SRC_WIDTH                 12  /* OUT3_NGATE_SRC - [11:0] */
-
-/*
- * R1060 (0x424) - Output Path Config 3R
- */
-#define ARIZONA_OUT3R_PGA_VOL_MASK               0x00FE  /* OUT3R_PGA_VOL - [7:1] */
-#define ARIZONA_OUT3R_PGA_VOL_SHIFT                   1  /* OUT3R_PGA_VOL - [7:1] */
-#define ARIZONA_OUT3R_PGA_VOL_WIDTH                   7  /* OUT3R_PGA_VOL - [7:1] */
-
-/*
- * R1061 (0x425) - DAC Digital Volume 3R
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT3R_MUTE                       0x0100  /* OUT3R_MUTE */
-#define ARIZONA_OUT3R_MUTE_MASK                  0x0100  /* OUT3R_MUTE */
-#define ARIZONA_OUT3R_MUTE_SHIFT                      8  /* OUT3R_MUTE */
-#define ARIZONA_OUT3R_MUTE_WIDTH                      1  /* OUT3R_MUTE */
-#define ARIZONA_OUT3R_VOL_MASK                   0x00FF  /* OUT3R_VOL - [7:0] */
-#define ARIZONA_OUT3R_VOL_SHIFT                       0  /* OUT3R_VOL - [7:0] */
-#define ARIZONA_OUT3R_VOL_WIDTH                       8  /* OUT3R_VOL - [7:0] */
-
-/*
- * R1062 (0x426) - DAC Volume Limit 3R
- */
-#define ARIZONA_OUT3R_ANC_SRC_MASK               0x0C00  /* OUT3R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT3R_ANC_SRC_SHIFT                  10  /* OUT3R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT3R_ANC_SRC_WIDTH                   2  /* OUT3R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT3R_VOL_LIM_MASK               0x00FF  /* OUT3R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT3R_VOL_LIM_SHIFT                   0  /* OUT3R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT3R_VOL_LIM_WIDTH                   8  /* OUT3R_VOL_LIM - [7:0] */
-
-/*
- * R1064 (0x428) - Output Path Config 4L
- */
-#define ARIZONA_OUT4_OSR                         0x2000  /* OUT4_OSR */
-#define ARIZONA_OUT4_OSR_MASK                    0x2000  /* OUT4_OSR */
-#define ARIZONA_OUT4_OSR_SHIFT                       13  /* OUT4_OSR */
-#define ARIZONA_OUT4_OSR_WIDTH                        1  /* OUT4_OSR */
-#define ARIZONA_OUT4L_ANC_SRC_MASK               0x0C00  /* OUT4L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT4L_ANC_SRC_SHIFT                  10  /* OUT4L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT4L_ANC_SRC_WIDTH                   2  /* OUT4L_ANC_SRC - [11:10] */
-
-/*
- * R1065 (0x429) - DAC Digital Volume 4L
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT4L_MUTE                       0x0100  /* OUT4L_MUTE */
-#define ARIZONA_OUT4L_MUTE_MASK                  0x0100  /* OUT4L_MUTE */
-#define ARIZONA_OUT4L_MUTE_SHIFT                      8  /* OUT4L_MUTE */
-#define ARIZONA_OUT4L_MUTE_WIDTH                      1  /* OUT4L_MUTE */
-#define ARIZONA_OUT4L_VOL_MASK                   0x00FF  /* OUT4L_VOL - [7:0] */
-#define ARIZONA_OUT4L_VOL_SHIFT                       0  /* OUT4L_VOL - [7:0] */
-#define ARIZONA_OUT4L_VOL_WIDTH                       8  /* OUT4L_VOL - [7:0] */
-
-/*
- * R1066 (0x42A) - Out Volume 4L
- */
-#define ARIZONA_OUT4L_VOL_LIM_MASK               0x00FF  /* OUT4L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT4L_VOL_LIM_SHIFT                   0  /* OUT4L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT4L_VOL_LIM_WIDTH                   8  /* OUT4L_VOL_LIM - [7:0] */
-
-/*
- * R1067 (0x42B) - Noise Gate Select 4L
- */
-#define ARIZONA_OUT4L_NGATE_SRC_MASK             0x0FFF  /* OUT4L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT4L_NGATE_SRC_SHIFT                 0  /* OUT4L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT4L_NGATE_SRC_WIDTH                12  /* OUT4L_NGATE_SRC - [11:0] */
-
-/*
- * R1068 (0x42C) - Output Path Config 4R
- */
-#define ARIZONA_OUT4R_ANC_SRC_MASK               0x0C00  /* OUT4R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT4R_ANC_SRC_SHIFT                  10  /* OUT4R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT4R_ANC_SRC_WIDTH                   2  /* OUT4R_ANC_SRC - [11:10] */
-
-/*
- * R1069 (0x42D) - DAC Digital Volume 4R
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT4R_MUTE                       0x0100  /* OUT4R_MUTE */
-#define ARIZONA_OUT4R_MUTE_MASK                  0x0100  /* OUT4R_MUTE */
-#define ARIZONA_OUT4R_MUTE_SHIFT                      8  /* OUT4R_MUTE */
-#define ARIZONA_OUT4R_MUTE_WIDTH                      1  /* OUT4R_MUTE */
-#define ARIZONA_OUT4R_VOL_MASK                   0x00FF  /* OUT4R_VOL - [7:0] */
-#define ARIZONA_OUT4R_VOL_SHIFT                       0  /* OUT4R_VOL - [7:0] */
-#define ARIZONA_OUT4R_VOL_WIDTH                       8  /* OUT4R_VOL - [7:0] */
-
-/*
- * R1070 (0x42E) - Out Volume 4R
- */
-#define ARIZONA_OUT4R_VOL_LIM_MASK               0x00FF  /* OUT4R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT4R_VOL_LIM_SHIFT                   0  /* OUT4R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT4R_VOL_LIM_WIDTH                   8  /* OUT4R_VOL_LIM - [7:0] */
-
-/*
- * R1071 (0x42F) - Noise Gate Select 4R
- */
-#define ARIZONA_OUT4R_NGATE_SRC_MASK             0x0FFF  /* OUT4R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT4R_NGATE_SRC_SHIFT                 0  /* OUT4R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT4R_NGATE_SRC_WIDTH                12  /* OUT4R_NGATE_SRC - [11:0] */
-
-/*
- * R1072 (0x430) - Output Path Config 5L
- */
-#define ARIZONA_OUT5_OSR                         0x2000  /* OUT5_OSR */
-#define ARIZONA_OUT5_OSR_MASK                    0x2000  /* OUT5_OSR */
-#define ARIZONA_OUT5_OSR_SHIFT                       13  /* OUT5_OSR */
-#define ARIZONA_OUT5_OSR_WIDTH                        1  /* OUT5_OSR */
-#define ARIZONA_OUT5L_ANC_SRC_MASK               0x0C00  /* OUT5L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT5L_ANC_SRC_SHIFT                  10  /* OUT5L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT5L_ANC_SRC_WIDTH                   2  /* OUT5L_ANC_SRC - [11:10] */
-
-/*
- * R1073 (0x431) - DAC Digital Volume 5L
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT5L_MUTE                       0x0100  /* OUT5L_MUTE */
-#define ARIZONA_OUT5L_MUTE_MASK                  0x0100  /* OUT5L_MUTE */
-#define ARIZONA_OUT5L_MUTE_SHIFT                      8  /* OUT5L_MUTE */
-#define ARIZONA_OUT5L_MUTE_WIDTH                      1  /* OUT5L_MUTE */
-#define ARIZONA_OUT5L_VOL_MASK                   0x00FF  /* OUT5L_VOL - [7:0] */
-#define ARIZONA_OUT5L_VOL_SHIFT                       0  /* OUT5L_VOL - [7:0] */
-#define ARIZONA_OUT5L_VOL_WIDTH                       8  /* OUT5L_VOL - [7:0] */
-
-/*
- * R1074 (0x432) - DAC Volume Limit 5L
- */
-#define ARIZONA_OUT5L_VOL_LIM_MASK               0x00FF  /* OUT5L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT5L_VOL_LIM_SHIFT                   0  /* OUT5L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT5L_VOL_LIM_WIDTH                   8  /* OUT5L_VOL_LIM - [7:0] */
-
-/*
- * R1075 (0x433) - Noise Gate Select 5L
- */
-#define ARIZONA_OUT5L_NGATE_SRC_MASK             0x0FFF  /* OUT5L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT5L_NGATE_SRC_SHIFT                 0  /* OUT5L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT5L_NGATE_SRC_WIDTH                12  /* OUT5L_NGATE_SRC - [11:0] */
-
-/*
- * R1076 (0x434) - Output Path Config 5R
- */
-#define ARIZONA_OUT5R_ANC_SRC_MASK               0x0C00  /* OUT5R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT5R_ANC_SRC_SHIFT                  10  /* OUT5R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT5R_ANC_SRC_WIDTH                   2  /* OUT5R_ANC_SRC - [11:10] */
-
-/*
- * R1077 (0x435) - DAC Digital Volume 5R
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT5R_MUTE                       0x0100  /* OUT5R_MUTE */
-#define ARIZONA_OUT5R_MUTE_MASK                  0x0100  /* OUT5R_MUTE */
-#define ARIZONA_OUT5R_MUTE_SHIFT                      8  /* OUT5R_MUTE */
-#define ARIZONA_OUT5R_MUTE_WIDTH                      1  /* OUT5R_MUTE */
-#define ARIZONA_OUT5R_VOL_MASK                   0x00FF  /* OUT5R_VOL - [7:0] */
-#define ARIZONA_OUT5R_VOL_SHIFT                       0  /* OUT5R_VOL - [7:0] */
-#define ARIZONA_OUT5R_VOL_WIDTH                       8  /* OUT5R_VOL - [7:0] */
-
-/*
- * R1078 (0x436) - DAC Volume Limit 5R
- */
-#define ARIZONA_OUT5R_VOL_LIM_MASK               0x00FF  /* OUT5R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT5R_VOL_LIM_SHIFT                   0  /* OUT5R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT5R_VOL_LIM_WIDTH                   8  /* OUT5R_VOL_LIM - [7:0] */
-
-/*
- * R1079 (0x437) - Noise Gate Select 5R
- */
-#define ARIZONA_OUT5R_NGATE_SRC_MASK             0x0FFF  /* OUT5R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT5R_NGATE_SRC_SHIFT                 0  /* OUT5R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT5R_NGATE_SRC_WIDTH                12  /* OUT5R_NGATE_SRC - [11:0] */
-
-/*
- * R1080 (0x438) - Output Path Config 6L
- */
-#define ARIZONA_OUT6_OSR                         0x2000  /* OUT6_OSR */
-#define ARIZONA_OUT6_OSR_MASK                    0x2000  /* OUT6_OSR */
-#define ARIZONA_OUT6_OSR_SHIFT                       13  /* OUT6_OSR */
-#define ARIZONA_OUT6_OSR_WIDTH                        1  /* OUT6_OSR */
-#define ARIZONA_OUT6L_ANC_SRC_MASK               0x0C00  /* OUT6L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT6L_ANC_SRC_SHIFT                  10  /* OUT6L_ANC_SRC - [11:10] */
-#define ARIZONA_OUT6L_ANC_SRC_WIDTH                   2  /* OUT6L_ANC_SRC - [11:10] */
-
-/*
- * R1081 (0x439) - DAC Digital Volume 6L
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT6L_MUTE                       0x0100  /* OUT6L_MUTE */
-#define ARIZONA_OUT6L_MUTE_MASK                  0x0100  /* OUT6L_MUTE */
-#define ARIZONA_OUT6L_MUTE_SHIFT                      8  /* OUT6L_MUTE */
-#define ARIZONA_OUT6L_MUTE_WIDTH                      1  /* OUT6L_MUTE */
-#define ARIZONA_OUT6L_VOL_MASK                   0x00FF  /* OUT6L_VOL - [7:0] */
-#define ARIZONA_OUT6L_VOL_SHIFT                       0  /* OUT6L_VOL - [7:0] */
-#define ARIZONA_OUT6L_VOL_WIDTH                       8  /* OUT6L_VOL - [7:0] */
-
-/*
- * R1082 (0x43A) - DAC Volume Limit 6L
- */
-#define ARIZONA_OUT6L_VOL_LIM_MASK               0x00FF  /* OUT6L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT6L_VOL_LIM_SHIFT                   0  /* OUT6L_VOL_LIM - [7:0] */
-#define ARIZONA_OUT6L_VOL_LIM_WIDTH                   8  /* OUT6L_VOL_LIM - [7:0] */
-
-/*
- * R1083 (0x43B) - Noise Gate Select 6L
- */
-#define ARIZONA_OUT6L_NGATE_SRC_MASK             0x0FFF  /* OUT6L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT6L_NGATE_SRC_SHIFT                 0  /* OUT6L_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT6L_NGATE_SRC_WIDTH                12  /* OUT6L_NGATE_SRC - [11:0] */
-
-/*
- * R1084 (0x43C) - Output Path Config 6R
- */
-#define ARIZONA_OUT6R_ANC_SRC_MASK               0x0C00  /* OUT6R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT6R_ANC_SRC_SHIFT                  10  /* OUT6R_ANC_SRC - [11:10] */
-#define ARIZONA_OUT6R_ANC_SRC_WIDTH                   2  /* OUT6R_ANC_SRC - [11:10] */
-
-/*
- * R1085 (0x43D) - DAC Digital Volume 6R
- */
-#define ARIZONA_OUT_VU                           0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_MASK                      0x0200  /* OUT_VU */
-#define ARIZONA_OUT_VU_SHIFT                          9  /* OUT_VU */
-#define ARIZONA_OUT_VU_WIDTH                          1  /* OUT_VU */
-#define ARIZONA_OUT6R_MUTE                       0x0100  /* OUT6R_MUTE */
-#define ARIZONA_OUT6R_MUTE_MASK                  0x0100  /* OUT6R_MUTE */
-#define ARIZONA_OUT6R_MUTE_SHIFT                      8  /* OUT6R_MUTE */
-#define ARIZONA_OUT6R_MUTE_WIDTH                      1  /* OUT6R_MUTE */
-#define ARIZONA_OUT6R_VOL_MASK                   0x00FF  /* OUT6R_VOL - [7:0] */
-#define ARIZONA_OUT6R_VOL_SHIFT                       0  /* OUT6R_VOL - [7:0] */
-#define ARIZONA_OUT6R_VOL_WIDTH                       8  /* OUT6R_VOL - [7:0] */
-
-/*
- * R1086 (0x43E) - DAC Volume Limit 6R
- */
-#define ARIZONA_OUT6R_VOL_LIM_MASK               0x00FF  /* OUT6R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT6R_VOL_LIM_SHIFT                   0  /* OUT6R_VOL_LIM - [7:0] */
-#define ARIZONA_OUT6R_VOL_LIM_WIDTH                   8  /* OUT6R_VOL_LIM - [7:0] */
-
-/*
- * R1087 (0x43F) - Noise Gate Select 6R
- */
-#define ARIZONA_OUT6R_NGATE_SRC_MASK             0x0FFF  /* OUT6R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT6R_NGATE_SRC_SHIFT                 0  /* OUT6R_NGATE_SRC - [11:0] */
-#define ARIZONA_OUT6R_NGATE_SRC_WIDTH                12  /* OUT6R_NGATE_SRC - [11:0] */
-
-/*
- * R1104 (0x450) - DAC AEC Control 1
- */
-#define ARIZONA_AEC_LOOPBACK_SRC_MASK            0x003C  /* AEC_LOOPBACK_SRC - [5:2] */
-#define ARIZONA_AEC_LOOPBACK_SRC_SHIFT                2  /* AEC_LOOPBACK_SRC - [5:2] */
-#define ARIZONA_AEC_LOOPBACK_SRC_WIDTH                4  /* AEC_LOOPBACK_SRC - [5:2] */
-#define ARIZONA_AEC_ENA_STS                      0x0002  /* AEC_ENA_STS */
-#define ARIZONA_AEC_ENA_STS_MASK                 0x0002  /* AEC_ENA_STS */
-#define ARIZONA_AEC_ENA_STS_SHIFT                     1  /* AEC_ENA_STS */
-#define ARIZONA_AEC_ENA_STS_WIDTH                     1  /* AEC_ENA_STS */
-#define ARIZONA_AEC_LOOPBACK_ENA                 0x0001  /* AEC_LOOPBACK_ENA */
-#define ARIZONA_AEC_LOOPBACK_ENA_MASK            0x0001  /* AEC_LOOPBACK_ENA */
-#define ARIZONA_AEC_LOOPBACK_ENA_SHIFT                0  /* AEC_LOOPBACK_ENA */
-#define ARIZONA_AEC_LOOPBACK_ENA_WIDTH                1  /* AEC_LOOPBACK_ENA */
-
-/*
- * R1112 (0x458) - Noise Gate Control
- */
-#define ARIZONA_NGATE_HOLD_MASK                  0x0030  /* NGATE_HOLD - [5:4] */
-#define ARIZONA_NGATE_HOLD_SHIFT                      4  /* NGATE_HOLD - [5:4] */
-#define ARIZONA_NGATE_HOLD_WIDTH                      2  /* NGATE_HOLD - [5:4] */
-#define ARIZONA_NGATE_THR_MASK                   0x000E  /* NGATE_THR - [3:1] */
-#define ARIZONA_NGATE_THR_SHIFT                       1  /* NGATE_THR - [3:1] */
-#define ARIZONA_NGATE_THR_WIDTH                       3  /* NGATE_THR - [3:1] */
-#define ARIZONA_NGATE_ENA                        0x0001  /* NGATE_ENA */
-#define ARIZONA_NGATE_ENA_MASK                   0x0001  /* NGATE_ENA */
-#define ARIZONA_NGATE_ENA_SHIFT                       0  /* NGATE_ENA */
-#define ARIZONA_NGATE_ENA_WIDTH                       1  /* NGATE_ENA */
-
-/*
- * R1168 (0x490) - PDM SPK1 CTRL 1
- */
-#define ARIZONA_SPK1R_MUTE                       0x2000  /* SPK1R_MUTE */
-#define ARIZONA_SPK1R_MUTE_MASK                  0x2000  /* SPK1R_MUTE */
-#define ARIZONA_SPK1R_MUTE_SHIFT                     13  /* SPK1R_MUTE */
-#define ARIZONA_SPK1R_MUTE_WIDTH                      1  /* SPK1R_MUTE */
-#define ARIZONA_SPK1L_MUTE                       0x1000  /* SPK1L_MUTE */
-#define ARIZONA_SPK1L_MUTE_MASK                  0x1000  /* SPK1L_MUTE */
-#define ARIZONA_SPK1L_MUTE_SHIFT                     12  /* SPK1L_MUTE */
-#define ARIZONA_SPK1L_MUTE_WIDTH                      1  /* SPK1L_MUTE */
-#define ARIZONA_SPK1_MUTE_ENDIAN                 0x0100  /* SPK1_MUTE_ENDIAN */
-#define ARIZONA_SPK1_MUTE_ENDIAN_MASK            0x0100  /* SPK1_MUTE_ENDIAN */
-#define ARIZONA_SPK1_MUTE_ENDIAN_SHIFT                8  /* SPK1_MUTE_ENDIAN */
-#define ARIZONA_SPK1_MUTE_ENDIAN_WIDTH                1  /* SPK1_MUTE_ENDIAN */
-#define ARIZONA_SPK1_MUTE_SEQ1_MASK              0x00FF  /* SPK1_MUTE_SEQ1 - [7:0] */
-#define ARIZONA_SPK1_MUTE_SEQ1_SHIFT                  0  /* SPK1_MUTE_SEQ1 - [7:0] */
-#define ARIZONA_SPK1_MUTE_SEQ1_WIDTH                  8  /* SPK1_MUTE_SEQ1 - [7:0] */
-
-/*
- * R1169 (0x491) - PDM SPK1 CTRL 2
- */
-#define ARIZONA_SPK1_FMT                         0x0001  /* SPK1_FMT */
-#define ARIZONA_SPK1_FMT_MASK                    0x0001  /* SPK1_FMT */
-#define ARIZONA_SPK1_FMT_SHIFT                        0  /* SPK1_FMT */
-#define ARIZONA_SPK1_FMT_WIDTH                        1  /* SPK1_FMT */
-
-/*
- * R1170 (0x492) - PDM SPK2 CTRL 1
- */
-#define ARIZONA_SPK2R_MUTE                       0x2000  /* SPK2R_MUTE */
-#define ARIZONA_SPK2R_MUTE_MASK                  0x2000  /* SPK2R_MUTE */
-#define ARIZONA_SPK2R_MUTE_SHIFT                     13  /* SPK2R_MUTE */
-#define ARIZONA_SPK2R_MUTE_WIDTH                      1  /* SPK2R_MUTE */
-#define ARIZONA_SPK2L_MUTE                       0x1000  /* SPK2L_MUTE */
-#define ARIZONA_SPK2L_MUTE_MASK                  0x1000  /* SPK2L_MUTE */
-#define ARIZONA_SPK2L_MUTE_SHIFT                     12  /* SPK2L_MUTE */
-#define ARIZONA_SPK2L_MUTE_WIDTH                      1  /* SPK2L_MUTE */
-#define ARIZONA_SPK2_MUTE_ENDIAN                 0x0100  /* SPK2_MUTE_ENDIAN */
-#define ARIZONA_SPK2_MUTE_ENDIAN_MASK            0x0100  /* SPK2_MUTE_ENDIAN */
-#define ARIZONA_SPK2_MUTE_ENDIAN_SHIFT                8  /* SPK2_MUTE_ENDIAN */
-#define ARIZONA_SPK2_MUTE_ENDIAN_WIDTH                1  /* SPK2_MUTE_ENDIAN */
-#define ARIZONA_SPK2_MUTE_SEQ_MASK               0x00FF  /* SPK2_MUTE_SEQ - [7:0] */
-#define ARIZONA_SPK2_MUTE_SEQ_SHIFT                   0  /* SPK2_MUTE_SEQ - [7:0] */
-#define ARIZONA_SPK2_MUTE_SEQ_WIDTH                   8  /* SPK2_MUTE_SEQ - [7:0] */
-
-/*
- * R1171 (0x493) - PDM SPK2 CTRL 2
- */
-#define ARIZONA_SPK2_FMT                         0x0001  /* SPK2_FMT */
-#define ARIZONA_SPK2_FMT_MASK                    0x0001  /* SPK2_FMT */
-#define ARIZONA_SPK2_FMT_SHIFT                        0  /* SPK2_FMT */
-#define ARIZONA_SPK2_FMT_WIDTH                        1  /* SPK2_FMT */
-
-/*
- * R1244 (0x4DC) - DAC comp 1
- */
-#define ARIZONA_OUT_COMP_COEFF_MASK              0xFFFF  /* OUT_COMP_COEFF - [15:0] */
-#define ARIZONA_OUT_COMP_COEFF_SHIFT                  0  /* OUT_COMP_COEFF - [15:0] */
-#define ARIZONA_OUT_COMP_COEFF_WIDTH                 16  /* OUT_COMP_COEFF - [15:0] */
-
-/*
- * R1245 (0x4DD) - DAC comp 2
- */
-#define ARIZONA_OUT_COMP_COEFF_1                 0x0002  /* OUT_COMP_COEFF */
-#define ARIZONA_OUT_COMP_COEFF_1_MASK            0x0002  /* OUT_COMP_COEFF */
-#define ARIZONA_OUT_COMP_COEFF_1_SHIFT                1  /* OUT_COMP_COEFF */
-#define ARIZONA_OUT_COMP_COEFF_1_WIDTH                1  /* OUT_COMP_COEFF */
-#define ARIZONA_OUT_COMP_COEFF_SEL               0x0001  /* OUT_COMP_COEFF_SEL */
-#define ARIZONA_OUT_COMP_COEFF_SEL_MASK          0x0001  /* OUT_COMP_COEFF_SEL */
-#define ARIZONA_OUT_COMP_COEFF_SEL_SHIFT              0  /* OUT_COMP_COEFF_SEL */
-#define ARIZONA_OUT_COMP_COEFF_SEL_WIDTH              1  /* OUT_COMP_COEFF_SEL */
-
-/*
- * R1246 (0x4DE) - DAC comp 3
- */
-#define ARIZONA_AEC_COMP_COEFF_MASK              0xFFFF  /* AEC_COMP_COEFF - [15:0] */
-#define ARIZONA_AEC_COMP_COEFF_SHIFT                  0  /* AEC_COMP_COEFF - [15:0] */
-#define ARIZONA_AEC_COMP_COEFF_WIDTH                 16  /* AEC_COMP_COEFF - [15:0] */
-
-/*
- * R1247 (0x4DF) - DAC comp 4
- */
-#define ARIZONA_AEC_COMP_COEFF_1                 0x0002  /* AEC_COMP_COEFF */
-#define ARIZONA_AEC_COMP_COEFF_1_MASK            0x0002  /* AEC_COMP_COEFF */
-#define ARIZONA_AEC_COMP_COEFF_1_SHIFT                1  /* AEC_COMP_COEFF */
-#define ARIZONA_AEC_COMP_COEFF_1_WIDTH                1  /* AEC_COMP_COEFF */
-#define ARIZONA_AEC_COMP_COEFF_SEL               0x0001  /* AEC_COMP_COEFF_SEL */
-#define ARIZONA_AEC_COMP_COEFF_SEL_MASK          0x0001  /* AEC_COMP_COEFF_SEL */
-#define ARIZONA_AEC_COMP_COEFF_SEL_SHIFT              0  /* AEC_COMP_COEFF_SEL */
-#define ARIZONA_AEC_COMP_COEFF_SEL_WIDTH              1  /* AEC_COMP_COEFF_SEL */
-
-/*
- * R1280 (0x500) - AIF1 BCLK Ctrl
- */
-#define ARIZONA_AIF1_BCLK_INV                    0x0080  /* AIF1_BCLK_INV */
-#define ARIZONA_AIF1_BCLK_INV_MASK               0x0080  /* AIF1_BCLK_INV */
-#define ARIZONA_AIF1_BCLK_INV_SHIFT                   7  /* AIF1_BCLK_INV */
-#define ARIZONA_AIF1_BCLK_INV_WIDTH                   1  /* AIF1_BCLK_INV */
-#define ARIZONA_AIF1_BCLK_FRC                    0x0040  /* AIF1_BCLK_FRC */
-#define ARIZONA_AIF1_BCLK_FRC_MASK               0x0040  /* AIF1_BCLK_FRC */
-#define ARIZONA_AIF1_BCLK_FRC_SHIFT                   6  /* AIF1_BCLK_FRC */
-#define ARIZONA_AIF1_BCLK_FRC_WIDTH                   1  /* AIF1_BCLK_FRC */
-#define ARIZONA_AIF1_BCLK_MSTR                   0x0020  /* AIF1_BCLK_MSTR */
-#define ARIZONA_AIF1_BCLK_MSTR_MASK              0x0020  /* AIF1_BCLK_MSTR */
-#define ARIZONA_AIF1_BCLK_MSTR_SHIFT                  5  /* AIF1_BCLK_MSTR */
-#define ARIZONA_AIF1_BCLK_MSTR_WIDTH                  1  /* AIF1_BCLK_MSTR */
-#define ARIZONA_AIF1_BCLK_FREQ_MASK              0x001F  /* AIF1_BCLK_FREQ - [4:0] */
-#define ARIZONA_AIF1_BCLK_FREQ_SHIFT                  0  /* AIF1_BCLK_FREQ - [4:0] */
-#define ARIZONA_AIF1_BCLK_FREQ_WIDTH                  5  /* AIF1_BCLK_FREQ - [4:0] */
-
-/*
- * R1281 (0x501) - AIF1 Tx Pin Ctrl
- */
-#define ARIZONA_AIF1TX_DAT_TRI                   0x0020  /* AIF1TX_DAT_TRI */
-#define ARIZONA_AIF1TX_DAT_TRI_MASK              0x0020  /* AIF1TX_DAT_TRI */
-#define ARIZONA_AIF1TX_DAT_TRI_SHIFT                  5  /* AIF1TX_DAT_TRI */
-#define ARIZONA_AIF1TX_DAT_TRI_WIDTH                  1  /* AIF1TX_DAT_TRI */
-#define ARIZONA_AIF1TX_LRCLK_SRC                 0x0008  /* AIF1TX_LRCLK_SRC */
-#define ARIZONA_AIF1TX_LRCLK_SRC_MASK            0x0008  /* AIF1TX_LRCLK_SRC */
-#define ARIZONA_AIF1TX_LRCLK_SRC_SHIFT                3  /* AIF1TX_LRCLK_SRC */
-#define ARIZONA_AIF1TX_LRCLK_SRC_WIDTH                1  /* AIF1TX_LRCLK_SRC */
-#define ARIZONA_AIF1TX_LRCLK_INV                 0x0004  /* AIF1TX_LRCLK_INV */
-#define ARIZONA_AIF1TX_LRCLK_INV_MASK            0x0004  /* AIF1TX_LRCLK_INV */
-#define ARIZONA_AIF1TX_LRCLK_INV_SHIFT                2  /* AIF1TX_LRCLK_INV */
-#define ARIZONA_AIF1TX_LRCLK_INV_WIDTH                1  /* AIF1TX_LRCLK_INV */
-#define ARIZONA_AIF1TX_LRCLK_FRC                 0x0002  /* AIF1TX_LRCLK_FRC */
-#define ARIZONA_AIF1TX_LRCLK_FRC_MASK            0x0002  /* AIF1TX_LRCLK_FRC */
-#define ARIZONA_AIF1TX_LRCLK_FRC_SHIFT                1  /* AIF1TX_LRCLK_FRC */
-#define ARIZONA_AIF1TX_LRCLK_FRC_WIDTH                1  /* AIF1TX_LRCLK_FRC */
-#define ARIZONA_AIF1TX_LRCLK_MSTR                0x0001  /* AIF1TX_LRCLK_MSTR */
-#define ARIZONA_AIF1TX_LRCLK_MSTR_MASK           0x0001  /* AIF1TX_LRCLK_MSTR */
-#define ARIZONA_AIF1TX_LRCLK_MSTR_SHIFT               0  /* AIF1TX_LRCLK_MSTR */
-#define ARIZONA_AIF1TX_LRCLK_MSTR_WIDTH               1  /* AIF1TX_LRCLK_MSTR */
-
-/*
- * R1282 (0x502) - AIF1 Rx Pin Ctrl
- */
-#define ARIZONA_AIF1RX_LRCLK_INV                 0x0004  /* AIF1RX_LRCLK_INV */
-#define ARIZONA_AIF1RX_LRCLK_INV_MASK            0x0004  /* AIF1RX_LRCLK_INV */
-#define ARIZONA_AIF1RX_LRCLK_INV_SHIFT                2  /* AIF1RX_LRCLK_INV */
-#define ARIZONA_AIF1RX_LRCLK_INV_WIDTH                1  /* AIF1RX_LRCLK_INV */
-#define ARIZONA_AIF1RX_LRCLK_FRC                 0x0002  /* AIF1RX_LRCLK_FRC */
-#define ARIZONA_AIF1RX_LRCLK_FRC_MASK            0x0002  /* AIF1RX_LRCLK_FRC */
-#define ARIZONA_AIF1RX_LRCLK_FRC_SHIFT                1  /* AIF1RX_LRCLK_FRC */
-#define ARIZONA_AIF1RX_LRCLK_FRC_WIDTH                1  /* AIF1RX_LRCLK_FRC */
-#define ARIZONA_AIF1RX_LRCLK_MSTR                0x0001  /* AIF1RX_LRCLK_MSTR */
-#define ARIZONA_AIF1RX_LRCLK_MSTR_MASK           0x0001  /* AIF1RX_LRCLK_MSTR */
-#define ARIZONA_AIF1RX_LRCLK_MSTR_SHIFT               0  /* AIF1RX_LRCLK_MSTR */
-#define ARIZONA_AIF1RX_LRCLK_MSTR_WIDTH               1  /* AIF1RX_LRCLK_MSTR */
-
-/*
- * R1283 (0x503) - AIF1 Rate Ctrl
- */
-#define ARIZONA_AIF1_RATE_MASK                   0x7800  /* AIF1_RATE - [14:11] */
-#define ARIZONA_AIF1_RATE_SHIFT                      11  /* AIF1_RATE - [14:11] */
-#define ARIZONA_AIF1_RATE_WIDTH                       4  /* AIF1_RATE - [14:11] */
-#define ARIZONA_AIF1_TRI                         0x0040  /* AIF1_TRI */
-#define ARIZONA_AIF1_TRI_MASK                    0x0040  /* AIF1_TRI */
-#define ARIZONA_AIF1_TRI_SHIFT                        6  /* AIF1_TRI */
-#define ARIZONA_AIF1_TRI_WIDTH                        1  /* AIF1_TRI */
-
-/*
- * R1284 (0x504) - AIF1 Format
- */
-#define ARIZONA_AIF1_FMT_MASK                    0x0007  /* AIF1_FMT - [2:0] */
-#define ARIZONA_AIF1_FMT_SHIFT                        0  /* AIF1_FMT - [2:0] */
-#define ARIZONA_AIF1_FMT_WIDTH                        3  /* AIF1_FMT - [2:0] */
-
-/*
- * R1285 (0x505) - AIF1 Tx BCLK Rate
- */
-#define ARIZONA_AIF1TX_BCPF_MASK                 0x1FFF  /* AIF1TX_BCPF - [12:0] */
-#define ARIZONA_AIF1TX_BCPF_SHIFT                     0  /* AIF1TX_BCPF - [12:0] */
-#define ARIZONA_AIF1TX_BCPF_WIDTH                    13  /* AIF1TX_BCPF - [12:0] */
-
-/*
- * R1286 (0x506) - AIF1 Rx BCLK Rate
- */
-#define ARIZONA_AIF1RX_BCPF_MASK                 0x1FFF  /* AIF1RX_BCPF - [12:0] */
-#define ARIZONA_AIF1RX_BCPF_SHIFT                     0  /* AIF1RX_BCPF - [12:0] */
-#define ARIZONA_AIF1RX_BCPF_WIDTH                    13  /* AIF1RX_BCPF - [12:0] */
-
-/*
- * R1287 (0x507) - AIF1 Frame Ctrl 1
- */
-#define ARIZONA_AIF1TX_WL_MASK                   0x3F00  /* AIF1TX_WL - [13:8] */
-#define ARIZONA_AIF1TX_WL_SHIFT                       8  /* AIF1TX_WL - [13:8] */
-#define ARIZONA_AIF1TX_WL_WIDTH                       6  /* AIF1TX_WL - [13:8] */
-#define ARIZONA_AIF1TX_SLOT_LEN_MASK             0x00FF  /* AIF1TX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF1TX_SLOT_LEN_SHIFT                 0  /* AIF1TX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF1TX_SLOT_LEN_WIDTH                 8  /* AIF1TX_SLOT_LEN - [7:0] */
-
-/*
- * R1288 (0x508) - AIF1 Frame Ctrl 2
- */
-#define ARIZONA_AIF1RX_WL_MASK                   0x3F00  /* AIF1RX_WL - [13:8] */
-#define ARIZONA_AIF1RX_WL_SHIFT                       8  /* AIF1RX_WL - [13:8] */
-#define ARIZONA_AIF1RX_WL_WIDTH                       6  /* AIF1RX_WL - [13:8] */
-#define ARIZONA_AIF1RX_SLOT_LEN_MASK             0x00FF  /* AIF1RX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF1RX_SLOT_LEN_SHIFT                 0  /* AIF1RX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF1RX_SLOT_LEN_WIDTH                 8  /* AIF1RX_SLOT_LEN - [7:0] */
-
-/*
- * R1289 (0x509) - AIF1 Frame Ctrl 3
- */
-#define ARIZONA_AIF1TX1_SLOT_MASK                0x003F  /* AIF1TX1_SLOT - [5:0] */
-#define ARIZONA_AIF1TX1_SLOT_SHIFT                    0  /* AIF1TX1_SLOT - [5:0] */
-#define ARIZONA_AIF1TX1_SLOT_WIDTH                    6  /* AIF1TX1_SLOT - [5:0] */
-
-/*
- * R1290 (0x50A) - AIF1 Frame Ctrl 4
- */
-#define ARIZONA_AIF1TX2_SLOT_MASK                0x003F  /* AIF1TX2_SLOT - [5:0] */
-#define ARIZONA_AIF1TX2_SLOT_SHIFT                    0  /* AIF1TX2_SLOT - [5:0] */
-#define ARIZONA_AIF1TX2_SLOT_WIDTH                    6  /* AIF1TX2_SLOT - [5:0] */
-
-/*
- * R1291 (0x50B) - AIF1 Frame Ctrl 5
- */
-#define ARIZONA_AIF1TX3_SLOT_MASK                0x003F  /* AIF1TX3_SLOT - [5:0] */
-#define ARIZONA_AIF1TX3_SLOT_SHIFT                    0  /* AIF1TX3_SLOT - [5:0] */
-#define ARIZONA_AIF1TX3_SLOT_WIDTH                    6  /* AIF1TX3_SLOT - [5:0] */
-
-/*
- * R1292 (0x50C) - AIF1 Frame Ctrl 6
- */
-#define ARIZONA_AIF1TX4_SLOT_MASK                0x003F  /* AIF1TX4_SLOT - [5:0] */
-#define ARIZONA_AIF1TX4_SLOT_SHIFT                    0  /* AIF1TX4_SLOT - [5:0] */
-#define ARIZONA_AIF1TX4_SLOT_WIDTH                    6  /* AIF1TX4_SLOT - [5:0] */
-
-/*
- * R1293 (0x50D) - AIF1 Frame Ctrl 7
- */
-#define ARIZONA_AIF1TX5_SLOT_MASK                0x003F  /* AIF1TX5_SLOT - [5:0] */
-#define ARIZONA_AIF1TX5_SLOT_SHIFT                    0  /* AIF1TX5_SLOT - [5:0] */
-#define ARIZONA_AIF1TX5_SLOT_WIDTH                    6  /* AIF1TX5_SLOT - [5:0] */
-
-/*
- * R1294 (0x50E) - AIF1 Frame Ctrl 8
- */
-#define ARIZONA_AIF1TX6_SLOT_MASK                0x003F  /* AIF1TX6_SLOT - [5:0] */
-#define ARIZONA_AIF1TX6_SLOT_SHIFT                    0  /* AIF1TX6_SLOT - [5:0] */
-#define ARIZONA_AIF1TX6_SLOT_WIDTH                    6  /* AIF1TX6_SLOT - [5:0] */
-
-/*
- * R1295 (0x50F) - AIF1 Frame Ctrl 9
- */
-#define ARIZONA_AIF1TX7_SLOT_MASK                0x003F  /* AIF1TX7_SLOT - [5:0] */
-#define ARIZONA_AIF1TX7_SLOT_SHIFT                    0  /* AIF1TX7_SLOT - [5:0] */
-#define ARIZONA_AIF1TX7_SLOT_WIDTH                    6  /* AIF1TX7_SLOT - [5:0] */
-
-/*
- * R1296 (0x510) - AIF1 Frame Ctrl 10
- */
-#define ARIZONA_AIF1TX8_SLOT_MASK                0x003F  /* AIF1TX8_SLOT - [5:0] */
-#define ARIZONA_AIF1TX8_SLOT_SHIFT                    0  /* AIF1TX8_SLOT - [5:0] */
-#define ARIZONA_AIF1TX8_SLOT_WIDTH                    6  /* AIF1TX8_SLOT - [5:0] */
-
-/*
- * R1297 (0x511) - AIF1 Frame Ctrl 11
- */
-#define ARIZONA_AIF1RX1_SLOT_MASK                0x003F  /* AIF1RX1_SLOT - [5:0] */
-#define ARIZONA_AIF1RX1_SLOT_SHIFT                    0  /* AIF1RX1_SLOT - [5:0] */
-#define ARIZONA_AIF1RX1_SLOT_WIDTH                    6  /* AIF1RX1_SLOT - [5:0] */
-
-/*
- * R1298 (0x512) - AIF1 Frame Ctrl 12
- */
-#define ARIZONA_AIF1RX2_SLOT_MASK                0x003F  /* AIF1RX2_SLOT - [5:0] */
-#define ARIZONA_AIF1RX2_SLOT_SHIFT                    0  /* AIF1RX2_SLOT - [5:0] */
-#define ARIZONA_AIF1RX2_SLOT_WIDTH                    6  /* AIF1RX2_SLOT - [5:0] */
-
-/*
- * R1299 (0x513) - AIF1 Frame Ctrl 13
- */
-#define ARIZONA_AIF1RX3_SLOT_MASK                0x003F  /* AIF1RX3_SLOT - [5:0] */
-#define ARIZONA_AIF1RX3_SLOT_SHIFT                    0  /* AIF1RX3_SLOT - [5:0] */
-#define ARIZONA_AIF1RX3_SLOT_WIDTH                    6  /* AIF1RX3_SLOT - [5:0] */
-
-/*
- * R1300 (0x514) - AIF1 Frame Ctrl 14
- */
-#define ARIZONA_AIF1RX4_SLOT_MASK                0x003F  /* AIF1RX4_SLOT - [5:0] */
-#define ARIZONA_AIF1RX4_SLOT_SHIFT                    0  /* AIF1RX4_SLOT - [5:0] */
-#define ARIZONA_AIF1RX4_SLOT_WIDTH                    6  /* AIF1RX4_SLOT - [5:0] */
-
-/*
- * R1301 (0x515) - AIF1 Frame Ctrl 15
- */
-#define ARIZONA_AIF1RX5_SLOT_MASK                0x003F  /* AIF1RX5_SLOT - [5:0] */
-#define ARIZONA_AIF1RX5_SLOT_SHIFT                    0  /* AIF1RX5_SLOT - [5:0] */
-#define ARIZONA_AIF1RX5_SLOT_WIDTH                    6  /* AIF1RX5_SLOT - [5:0] */
-
-/*
- * R1302 (0x516) - AIF1 Frame Ctrl 16
- */
-#define ARIZONA_AIF1RX6_SLOT_MASK                0x003F  /* AIF1RX6_SLOT - [5:0] */
-#define ARIZONA_AIF1RX6_SLOT_SHIFT                    0  /* AIF1RX6_SLOT - [5:0] */
-#define ARIZONA_AIF1RX6_SLOT_WIDTH                    6  /* AIF1RX6_SLOT - [5:0] */
-
-/*
- * R1303 (0x517) - AIF1 Frame Ctrl 17
- */
-#define ARIZONA_AIF1RX7_SLOT_MASK                0x003F  /* AIF1RX7_SLOT - [5:0] */
-#define ARIZONA_AIF1RX7_SLOT_SHIFT                    0  /* AIF1RX7_SLOT - [5:0] */
-#define ARIZONA_AIF1RX7_SLOT_WIDTH                    6  /* AIF1RX7_SLOT - [5:0] */
-
-/*
- * R1304 (0x518) - AIF1 Frame Ctrl 18
- */
-#define ARIZONA_AIF1RX8_SLOT_MASK                0x003F  /* AIF1RX8_SLOT - [5:0] */
-#define ARIZONA_AIF1RX8_SLOT_SHIFT                    0  /* AIF1RX8_SLOT - [5:0] */
-#define ARIZONA_AIF1RX8_SLOT_WIDTH                    6  /* AIF1RX8_SLOT - [5:0] */
-
-/*
- * R1305 (0x519) - AIF1 Tx Enables
- */
-#define ARIZONA_AIF1TX8_ENA                      0x0080  /* AIF1TX8_ENA */
-#define ARIZONA_AIF1TX8_ENA_MASK                 0x0080  /* AIF1TX8_ENA */
-#define ARIZONA_AIF1TX8_ENA_SHIFT                     7  /* AIF1TX8_ENA */
-#define ARIZONA_AIF1TX8_ENA_WIDTH                     1  /* AIF1TX8_ENA */
-#define ARIZONA_AIF1TX7_ENA                      0x0040  /* AIF1TX7_ENA */
-#define ARIZONA_AIF1TX7_ENA_MASK                 0x0040  /* AIF1TX7_ENA */
-#define ARIZONA_AIF1TX7_ENA_SHIFT                     6  /* AIF1TX7_ENA */
-#define ARIZONA_AIF1TX7_ENA_WIDTH                     1  /* AIF1TX7_ENA */
-#define ARIZONA_AIF1TX6_ENA                      0x0020  /* AIF1TX6_ENA */
-#define ARIZONA_AIF1TX6_ENA_MASK                 0x0020  /* AIF1TX6_ENA */
-#define ARIZONA_AIF1TX6_ENA_SHIFT                     5  /* AIF1TX6_ENA */
-#define ARIZONA_AIF1TX6_ENA_WIDTH                     1  /* AIF1TX6_ENA */
-#define ARIZONA_AIF1TX5_ENA                      0x0010  /* AIF1TX5_ENA */
-#define ARIZONA_AIF1TX5_ENA_MASK                 0x0010  /* AIF1TX5_ENA */
-#define ARIZONA_AIF1TX5_ENA_SHIFT                     4  /* AIF1TX5_ENA */
-#define ARIZONA_AIF1TX5_ENA_WIDTH                     1  /* AIF1TX5_ENA */
-#define ARIZONA_AIF1TX4_ENA                      0x0008  /* AIF1TX4_ENA */
-#define ARIZONA_AIF1TX4_ENA_MASK                 0x0008  /* AIF1TX4_ENA */
-#define ARIZONA_AIF1TX4_ENA_SHIFT                     3  /* AIF1TX4_ENA */
-#define ARIZONA_AIF1TX4_ENA_WIDTH                     1  /* AIF1TX4_ENA */
-#define ARIZONA_AIF1TX3_ENA                      0x0004  /* AIF1TX3_ENA */
-#define ARIZONA_AIF1TX3_ENA_MASK                 0x0004  /* AIF1TX3_ENA */
-#define ARIZONA_AIF1TX3_ENA_SHIFT                     2  /* AIF1TX3_ENA */
-#define ARIZONA_AIF1TX3_ENA_WIDTH                     1  /* AIF1TX3_ENA */
-#define ARIZONA_AIF1TX2_ENA                      0x0002  /* AIF1TX2_ENA */
-#define ARIZONA_AIF1TX2_ENA_MASK                 0x0002  /* AIF1TX2_ENA */
-#define ARIZONA_AIF1TX2_ENA_SHIFT                     1  /* AIF1TX2_ENA */
-#define ARIZONA_AIF1TX2_ENA_WIDTH                     1  /* AIF1TX2_ENA */
-#define ARIZONA_AIF1TX1_ENA                      0x0001  /* AIF1TX1_ENA */
-#define ARIZONA_AIF1TX1_ENA_MASK                 0x0001  /* AIF1TX1_ENA */
-#define ARIZONA_AIF1TX1_ENA_SHIFT                     0  /* AIF1TX1_ENA */
-#define ARIZONA_AIF1TX1_ENA_WIDTH                     1  /* AIF1TX1_ENA */
-
-/*
- * R1306 (0x51A) - AIF1 Rx Enables
- */
-#define ARIZONA_AIF1RX8_ENA                      0x0080  /* AIF1RX8_ENA */
-#define ARIZONA_AIF1RX8_ENA_MASK                 0x0080  /* AIF1RX8_ENA */
-#define ARIZONA_AIF1RX8_ENA_SHIFT                     7  /* AIF1RX8_ENA */
-#define ARIZONA_AIF1RX8_ENA_WIDTH                     1  /* AIF1RX8_ENA */
-#define ARIZONA_AIF1RX7_ENA                      0x0040  /* AIF1RX7_ENA */
-#define ARIZONA_AIF1RX7_ENA_MASK                 0x0040  /* AIF1RX7_ENA */
-#define ARIZONA_AIF1RX7_ENA_SHIFT                     6  /* AIF1RX7_ENA */
-#define ARIZONA_AIF1RX7_ENA_WIDTH                     1  /* AIF1RX7_ENA */
-#define ARIZONA_AIF1RX6_ENA                      0x0020  /* AIF1RX6_ENA */
-#define ARIZONA_AIF1RX6_ENA_MASK                 0x0020  /* AIF1RX6_ENA */
-#define ARIZONA_AIF1RX6_ENA_SHIFT                     5  /* AIF1RX6_ENA */
-#define ARIZONA_AIF1RX6_ENA_WIDTH                     1  /* AIF1RX6_ENA */
-#define ARIZONA_AIF1RX5_ENA                      0x0010  /* AIF1RX5_ENA */
-#define ARIZONA_AIF1RX5_ENA_MASK                 0x0010  /* AIF1RX5_ENA */
-#define ARIZONA_AIF1RX5_ENA_SHIFT                     4  /* AIF1RX5_ENA */
-#define ARIZONA_AIF1RX5_ENA_WIDTH                     1  /* AIF1RX5_ENA */
-#define ARIZONA_AIF1RX4_ENA                      0x0008  /* AIF1RX4_ENA */
-#define ARIZONA_AIF1RX4_ENA_MASK                 0x0008  /* AIF1RX4_ENA */
-#define ARIZONA_AIF1RX4_ENA_SHIFT                     3  /* AIF1RX4_ENA */
-#define ARIZONA_AIF1RX4_ENA_WIDTH                     1  /* AIF1RX4_ENA */
-#define ARIZONA_AIF1RX3_ENA                      0x0004  /* AIF1RX3_ENA */
-#define ARIZONA_AIF1RX3_ENA_MASK                 0x0004  /* AIF1RX3_ENA */
-#define ARIZONA_AIF1RX3_ENA_SHIFT                     2  /* AIF1RX3_ENA */
-#define ARIZONA_AIF1RX3_ENA_WIDTH                     1  /* AIF1RX3_ENA */
-#define ARIZONA_AIF1RX2_ENA                      0x0002  /* AIF1RX2_ENA */
-#define ARIZONA_AIF1RX2_ENA_MASK                 0x0002  /* AIF1RX2_ENA */
-#define ARIZONA_AIF1RX2_ENA_SHIFT                     1  /* AIF1RX2_ENA */
-#define ARIZONA_AIF1RX2_ENA_WIDTH                     1  /* AIF1RX2_ENA */
-#define ARIZONA_AIF1RX1_ENA                      0x0001  /* AIF1RX1_ENA */
-#define ARIZONA_AIF1RX1_ENA_MASK                 0x0001  /* AIF1RX1_ENA */
-#define ARIZONA_AIF1RX1_ENA_SHIFT                     0  /* AIF1RX1_ENA */
-#define ARIZONA_AIF1RX1_ENA_WIDTH                     1  /* AIF1RX1_ENA */
-
-/*
- * R1307 (0x51B) - AIF1 Force Write
- */
-#define ARIZONA_AIF1_FRC_WR                      0x0001  /* AIF1_FRC_WR */
-#define ARIZONA_AIF1_FRC_WR_MASK                 0x0001  /* AIF1_FRC_WR */
-#define ARIZONA_AIF1_FRC_WR_SHIFT                     0  /* AIF1_FRC_WR */
-#define ARIZONA_AIF1_FRC_WR_WIDTH                     1  /* AIF1_FRC_WR */
-
-/*
- * R1344 (0x540) - AIF2 BCLK Ctrl
- */
-#define ARIZONA_AIF2_BCLK_INV                    0x0080  /* AIF2_BCLK_INV */
-#define ARIZONA_AIF2_BCLK_INV_MASK               0x0080  /* AIF2_BCLK_INV */
-#define ARIZONA_AIF2_BCLK_INV_SHIFT                   7  /* AIF2_BCLK_INV */
-#define ARIZONA_AIF2_BCLK_INV_WIDTH                   1  /* AIF2_BCLK_INV */
-#define ARIZONA_AIF2_BCLK_FRC                    0x0040  /* AIF2_BCLK_FRC */
-#define ARIZONA_AIF2_BCLK_FRC_MASK               0x0040  /* AIF2_BCLK_FRC */
-#define ARIZONA_AIF2_BCLK_FRC_SHIFT                   6  /* AIF2_BCLK_FRC */
-#define ARIZONA_AIF2_BCLK_FRC_WIDTH                   1  /* AIF2_BCLK_FRC */
-#define ARIZONA_AIF2_BCLK_MSTR                   0x0020  /* AIF2_BCLK_MSTR */
-#define ARIZONA_AIF2_BCLK_MSTR_MASK              0x0020  /* AIF2_BCLK_MSTR */
-#define ARIZONA_AIF2_BCLK_MSTR_SHIFT                  5  /* AIF2_BCLK_MSTR */
-#define ARIZONA_AIF2_BCLK_MSTR_WIDTH                  1  /* AIF2_BCLK_MSTR */
-#define ARIZONA_AIF2_BCLK_FREQ_MASK              0x001F  /* AIF2_BCLK_FREQ - [4:0] */
-#define ARIZONA_AIF2_BCLK_FREQ_SHIFT                  0  /* AIF2_BCLK_FREQ - [4:0] */
-#define ARIZONA_AIF2_BCLK_FREQ_WIDTH                  5  /* AIF2_BCLK_FREQ - [4:0] */
-
-/*
- * R1345 (0x541) - AIF2 Tx Pin Ctrl
- */
-#define ARIZONA_AIF2TX_DAT_TRI                   0x0020  /* AIF2TX_DAT_TRI */
-#define ARIZONA_AIF2TX_DAT_TRI_MASK              0x0020  /* AIF2TX_DAT_TRI */
-#define ARIZONA_AIF2TX_DAT_TRI_SHIFT                  5  /* AIF2TX_DAT_TRI */
-#define ARIZONA_AIF2TX_DAT_TRI_WIDTH                  1  /* AIF2TX_DAT_TRI */
-#define ARIZONA_AIF2TX_LRCLK_SRC                 0x0008  /* AIF2TX_LRCLK_SRC */
-#define ARIZONA_AIF2TX_LRCLK_SRC_MASK            0x0008  /* AIF2TX_LRCLK_SRC */
-#define ARIZONA_AIF2TX_LRCLK_SRC_SHIFT                3  /* AIF2TX_LRCLK_SRC */
-#define ARIZONA_AIF2TX_LRCLK_SRC_WIDTH                1  /* AIF2TX_LRCLK_SRC */
-#define ARIZONA_AIF2TX_LRCLK_INV                 0x0004  /* AIF2TX_LRCLK_INV */
-#define ARIZONA_AIF2TX_LRCLK_INV_MASK            0x0004  /* AIF2TX_LRCLK_INV */
-#define ARIZONA_AIF2TX_LRCLK_INV_SHIFT                2  /* AIF2TX_LRCLK_INV */
-#define ARIZONA_AIF2TX_LRCLK_INV_WIDTH                1  /* AIF2TX_LRCLK_INV */
-#define ARIZONA_AIF2TX_LRCLK_FRC                 0x0002  /* AIF2TX_LRCLK_FRC */
-#define ARIZONA_AIF2TX_LRCLK_FRC_MASK            0x0002  /* AIF2TX_LRCLK_FRC */
-#define ARIZONA_AIF2TX_LRCLK_FRC_SHIFT                1  /* AIF2TX_LRCLK_FRC */
-#define ARIZONA_AIF2TX_LRCLK_FRC_WIDTH                1  /* AIF2TX_LRCLK_FRC */
-#define ARIZONA_AIF2TX_LRCLK_MSTR                0x0001  /* AIF2TX_LRCLK_MSTR */
-#define ARIZONA_AIF2TX_LRCLK_MSTR_MASK           0x0001  /* AIF2TX_LRCLK_MSTR */
-#define ARIZONA_AIF2TX_LRCLK_MSTR_SHIFT               0  /* AIF2TX_LRCLK_MSTR */
-#define ARIZONA_AIF2TX_LRCLK_MSTR_WIDTH               1  /* AIF2TX_LRCLK_MSTR */
-
-/*
- * R1346 (0x542) - AIF2 Rx Pin Ctrl
- */
-#define ARIZONA_AIF2RX_LRCLK_INV                 0x0004  /* AIF2RX_LRCLK_INV */
-#define ARIZONA_AIF2RX_LRCLK_INV_MASK            0x0004  /* AIF2RX_LRCLK_INV */
-#define ARIZONA_AIF2RX_LRCLK_INV_SHIFT                2  /* AIF2RX_LRCLK_INV */
-#define ARIZONA_AIF2RX_LRCLK_INV_WIDTH                1  /* AIF2RX_LRCLK_INV */
-#define ARIZONA_AIF2RX_LRCLK_FRC                 0x0002  /* AIF2RX_LRCLK_FRC */
-#define ARIZONA_AIF2RX_LRCLK_FRC_MASK            0x0002  /* AIF2RX_LRCLK_FRC */
-#define ARIZONA_AIF2RX_LRCLK_FRC_SHIFT                1  /* AIF2RX_LRCLK_FRC */
-#define ARIZONA_AIF2RX_LRCLK_FRC_WIDTH                1  /* AIF2RX_LRCLK_FRC */
-#define ARIZONA_AIF2RX_LRCLK_MSTR                0x0001  /* AIF2RX_LRCLK_MSTR */
-#define ARIZONA_AIF2RX_LRCLK_MSTR_MASK           0x0001  /* AIF2RX_LRCLK_MSTR */
-#define ARIZONA_AIF2RX_LRCLK_MSTR_SHIFT               0  /* AIF2RX_LRCLK_MSTR */
-#define ARIZONA_AIF2RX_LRCLK_MSTR_WIDTH               1  /* AIF2RX_LRCLK_MSTR */
-
-/*
- * R1347 (0x543) - AIF2 Rate Ctrl
- */
-#define ARIZONA_AIF2_RATE_MASK                   0x7800  /* AIF2_RATE - [14:11] */
-#define ARIZONA_AIF2_RATE_SHIFT                      11  /* AIF2_RATE - [14:11] */
-#define ARIZONA_AIF2_RATE_WIDTH                       4  /* AIF2_RATE - [14:11] */
-#define ARIZONA_AIF2_TRI                         0x0040  /* AIF2_TRI */
-#define ARIZONA_AIF2_TRI_MASK                    0x0040  /* AIF2_TRI */
-#define ARIZONA_AIF2_TRI_SHIFT                        6  /* AIF2_TRI */
-#define ARIZONA_AIF2_TRI_WIDTH                        1  /* AIF2_TRI */
-
-/*
- * R1348 (0x544) - AIF2 Format
- */
-#define ARIZONA_AIF2_FMT_MASK                    0x0007  /* AIF2_FMT - [2:0] */
-#define ARIZONA_AIF2_FMT_SHIFT                        0  /* AIF2_FMT - [2:0] */
-#define ARIZONA_AIF2_FMT_WIDTH                        3  /* AIF2_FMT - [2:0] */
-
-/*
- * R1349 (0x545) - AIF2 Tx BCLK Rate
- */
-#define ARIZONA_AIF2TX_BCPF_MASK                 0x1FFF  /* AIF2TX_BCPF - [12:0] */
-#define ARIZONA_AIF2TX_BCPF_SHIFT                     0  /* AIF2TX_BCPF - [12:0] */
-#define ARIZONA_AIF2TX_BCPF_WIDTH                    13  /* AIF2TX_BCPF - [12:0] */
-
-/*
- * R1350 (0x546) - AIF2 Rx BCLK Rate
- */
-#define ARIZONA_AIF2RX_BCPF_MASK                 0x1FFF  /* AIF2RX_BCPF - [12:0] */
-#define ARIZONA_AIF2RX_BCPF_SHIFT                     0  /* AIF2RX_BCPF - [12:0] */
-#define ARIZONA_AIF2RX_BCPF_WIDTH                    13  /* AIF2RX_BCPF - [12:0] */
-
-/*
- * R1351 (0x547) - AIF2 Frame Ctrl 1
- */
-#define ARIZONA_AIF2TX_WL_MASK                   0x3F00  /* AIF2TX_WL - [13:8] */
-#define ARIZONA_AIF2TX_WL_SHIFT                       8  /* AIF2TX_WL - [13:8] */
-#define ARIZONA_AIF2TX_WL_WIDTH                       6  /* AIF2TX_WL - [13:8] */
-#define ARIZONA_AIF2TX_SLOT_LEN_MASK             0x00FF  /* AIF2TX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF2TX_SLOT_LEN_SHIFT                 0  /* AIF2TX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF2TX_SLOT_LEN_WIDTH                 8  /* AIF2TX_SLOT_LEN - [7:0] */
-
-/*
- * R1352 (0x548) - AIF2 Frame Ctrl 2
- */
-#define ARIZONA_AIF2RX_WL_MASK                   0x3F00  /* AIF2RX_WL - [13:8] */
-#define ARIZONA_AIF2RX_WL_SHIFT                       8  /* AIF2RX_WL - [13:8] */
-#define ARIZONA_AIF2RX_WL_WIDTH                       6  /* AIF2RX_WL - [13:8] */
-#define ARIZONA_AIF2RX_SLOT_LEN_MASK             0x00FF  /* AIF2RX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF2RX_SLOT_LEN_SHIFT                 0  /* AIF2RX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF2RX_SLOT_LEN_WIDTH                 8  /* AIF2RX_SLOT_LEN - [7:0] */
-
-/*
- * R1353 (0x549) - AIF2 Frame Ctrl 3
- */
-#define ARIZONA_AIF2TX1_SLOT_MASK                0x003F  /* AIF2TX1_SLOT - [5:0] */
-#define ARIZONA_AIF2TX1_SLOT_SHIFT                    0  /* AIF2TX1_SLOT - [5:0] */
-#define ARIZONA_AIF2TX1_SLOT_WIDTH                    6  /* AIF2TX1_SLOT - [5:0] */
-
-/*
- * R1354 (0x54A) - AIF2 Frame Ctrl 4
- */
-#define ARIZONA_AIF2TX2_SLOT_MASK                0x003F  /* AIF2TX2_SLOT - [5:0] */
-#define ARIZONA_AIF2TX2_SLOT_SHIFT                    0  /* AIF2TX2_SLOT - [5:0] */
-#define ARIZONA_AIF2TX2_SLOT_WIDTH                    6  /* AIF2TX2_SLOT - [5:0] */
-
-/*
- * R1361 (0x551) - AIF2 Frame Ctrl 11
- */
-#define ARIZONA_AIF2RX1_SLOT_MASK                0x003F  /* AIF2RX1_SLOT - [5:0] */
-#define ARIZONA_AIF2RX1_SLOT_SHIFT                    0  /* AIF2RX1_SLOT - [5:0] */
-#define ARIZONA_AIF2RX1_SLOT_WIDTH                    6  /* AIF2RX1_SLOT - [5:0] */
-
-/*
- * R1362 (0x552) - AIF2 Frame Ctrl 12
- */
-#define ARIZONA_AIF2RX2_SLOT_MASK                0x003F  /* AIF2RX2_SLOT - [5:0] */
-#define ARIZONA_AIF2RX2_SLOT_SHIFT                    0  /* AIF2RX2_SLOT - [5:0] */
-#define ARIZONA_AIF2RX2_SLOT_WIDTH                    6  /* AIF2RX2_SLOT - [5:0] */
-
-/*
- * R1369 (0x559) - AIF2 Tx Enables
- */
-#define ARIZONA_AIF2TX2_ENA                      0x0002  /* AIF2TX2_ENA */
-#define ARIZONA_AIF2TX2_ENA_MASK                 0x0002  /* AIF2TX2_ENA */
-#define ARIZONA_AIF2TX2_ENA_SHIFT                     1  /* AIF2TX2_ENA */
-#define ARIZONA_AIF2TX2_ENA_WIDTH                     1  /* AIF2TX2_ENA */
-#define ARIZONA_AIF2TX1_ENA                      0x0001  /* AIF2TX1_ENA */
-#define ARIZONA_AIF2TX1_ENA_MASK                 0x0001  /* AIF2TX1_ENA */
-#define ARIZONA_AIF2TX1_ENA_SHIFT                     0  /* AIF2TX1_ENA */
-#define ARIZONA_AIF2TX1_ENA_WIDTH                     1  /* AIF2TX1_ENA */
-
-/*
- * R1370 (0x55A) - AIF2 Rx Enables
- */
-#define ARIZONA_AIF2RX2_ENA                      0x0002  /* AIF2RX2_ENA */
-#define ARIZONA_AIF2RX2_ENA_MASK                 0x0002  /* AIF2RX2_ENA */
-#define ARIZONA_AIF2RX2_ENA_SHIFT                     1  /* AIF2RX2_ENA */
-#define ARIZONA_AIF2RX2_ENA_WIDTH                     1  /* AIF2RX2_ENA */
-#define ARIZONA_AIF2RX1_ENA                      0x0001  /* AIF2RX1_ENA */
-#define ARIZONA_AIF2RX1_ENA_MASK                 0x0001  /* AIF2RX1_ENA */
-#define ARIZONA_AIF2RX1_ENA_SHIFT                     0  /* AIF2RX1_ENA */
-#define ARIZONA_AIF2RX1_ENA_WIDTH                     1  /* AIF2RX1_ENA */
-
-/*
- * R1371 (0x55B) - AIF2 Force Write
- */
-#define ARIZONA_AIF2_FRC_WR                      0x0001  /* AIF2_FRC_WR */
-#define ARIZONA_AIF2_FRC_WR_MASK                 0x0001  /* AIF2_FRC_WR */
-#define ARIZONA_AIF2_FRC_WR_SHIFT                     0  /* AIF2_FRC_WR */
-#define ARIZONA_AIF2_FRC_WR_WIDTH                     1  /* AIF2_FRC_WR */
-
-/*
- * R1408 (0x580) - AIF3 BCLK Ctrl
- */
-#define ARIZONA_AIF3_BCLK_INV                    0x0080  /* AIF3_BCLK_INV */
-#define ARIZONA_AIF3_BCLK_INV_MASK               0x0080  /* AIF3_BCLK_INV */
-#define ARIZONA_AIF3_BCLK_INV_SHIFT                   7  /* AIF3_BCLK_INV */
-#define ARIZONA_AIF3_BCLK_INV_WIDTH                   1  /* AIF3_BCLK_INV */
-#define ARIZONA_AIF3_BCLK_FRC                    0x0040  /* AIF3_BCLK_FRC */
-#define ARIZONA_AIF3_BCLK_FRC_MASK               0x0040  /* AIF3_BCLK_FRC */
-#define ARIZONA_AIF3_BCLK_FRC_SHIFT                   6  /* AIF3_BCLK_FRC */
-#define ARIZONA_AIF3_BCLK_FRC_WIDTH                   1  /* AIF3_BCLK_FRC */
-#define ARIZONA_AIF3_BCLK_MSTR                   0x0020  /* AIF3_BCLK_MSTR */
-#define ARIZONA_AIF3_BCLK_MSTR_MASK              0x0020  /* AIF3_BCLK_MSTR */
-#define ARIZONA_AIF3_BCLK_MSTR_SHIFT                  5  /* AIF3_BCLK_MSTR */
-#define ARIZONA_AIF3_BCLK_MSTR_WIDTH                  1  /* AIF3_BCLK_MSTR */
-#define ARIZONA_AIF3_BCLK_FREQ_MASK              0x001F  /* AIF3_BCLK_FREQ - [4:0] */
-#define ARIZONA_AIF3_BCLK_FREQ_SHIFT                  0  /* AIF3_BCLK_FREQ - [4:0] */
-#define ARIZONA_AIF3_BCLK_FREQ_WIDTH                  5  /* AIF3_BCLK_FREQ - [4:0] */
-
-/*
- * R1409 (0x581) - AIF3 Tx Pin Ctrl
- */
-#define ARIZONA_AIF3TX_DAT_TRI                   0x0020  /* AIF3TX_DAT_TRI */
-#define ARIZONA_AIF3TX_DAT_TRI_MASK              0x0020  /* AIF3TX_DAT_TRI */
-#define ARIZONA_AIF3TX_DAT_TRI_SHIFT                  5  /* AIF3TX_DAT_TRI */
-#define ARIZONA_AIF3TX_DAT_TRI_WIDTH                  1  /* AIF3TX_DAT_TRI */
-#define ARIZONA_AIF3TX_LRCLK_SRC                 0x0008  /* AIF3TX_LRCLK_SRC */
-#define ARIZONA_AIF3TX_LRCLK_SRC_MASK            0x0008  /* AIF3TX_LRCLK_SRC */
-#define ARIZONA_AIF3TX_LRCLK_SRC_SHIFT                3  /* AIF3TX_LRCLK_SRC */
-#define ARIZONA_AIF3TX_LRCLK_SRC_WIDTH                1  /* AIF3TX_LRCLK_SRC */
-#define ARIZONA_AIF3TX_LRCLK_INV                 0x0004  /* AIF3TX_LRCLK_INV */
-#define ARIZONA_AIF3TX_LRCLK_INV_MASK            0x0004  /* AIF3TX_LRCLK_INV */
-#define ARIZONA_AIF3TX_LRCLK_INV_SHIFT                2  /* AIF3TX_LRCLK_INV */
-#define ARIZONA_AIF3TX_LRCLK_INV_WIDTH                1  /* AIF3TX_LRCLK_INV */
-#define ARIZONA_AIF3TX_LRCLK_FRC                 0x0002  /* AIF3TX_LRCLK_FRC */
-#define ARIZONA_AIF3TX_LRCLK_FRC_MASK            0x0002  /* AIF3TX_LRCLK_FRC */
-#define ARIZONA_AIF3TX_LRCLK_FRC_SHIFT                1  /* AIF3TX_LRCLK_FRC */
-#define ARIZONA_AIF3TX_LRCLK_FRC_WIDTH                1  /* AIF3TX_LRCLK_FRC */
-#define ARIZONA_AIF3TX_LRCLK_MSTR                0x0001  /* AIF3TX_LRCLK_MSTR */
-#define ARIZONA_AIF3TX_LRCLK_MSTR_MASK           0x0001  /* AIF3TX_LRCLK_MSTR */
-#define ARIZONA_AIF3TX_LRCLK_MSTR_SHIFT               0  /* AIF3TX_LRCLK_MSTR */
-#define ARIZONA_AIF3TX_LRCLK_MSTR_WIDTH               1  /* AIF3TX_LRCLK_MSTR */
-
-/*
- * R1410 (0x582) - AIF3 Rx Pin Ctrl
- */
-#define ARIZONA_AIF3RX_LRCLK_INV                 0x0004  /* AIF3RX_LRCLK_INV */
-#define ARIZONA_AIF3RX_LRCLK_INV_MASK            0x0004  /* AIF3RX_LRCLK_INV */
-#define ARIZONA_AIF3RX_LRCLK_INV_SHIFT                2  /* AIF3RX_LRCLK_INV */
-#define ARIZONA_AIF3RX_LRCLK_INV_WIDTH                1  /* AIF3RX_LRCLK_INV */
-#define ARIZONA_AIF3RX_LRCLK_FRC                 0x0002  /* AIF3RX_LRCLK_FRC */
-#define ARIZONA_AIF3RX_LRCLK_FRC_MASK            0x0002  /* AIF3RX_LRCLK_FRC */
-#define ARIZONA_AIF3RX_LRCLK_FRC_SHIFT                1  /* AIF3RX_LRCLK_FRC */
-#define ARIZONA_AIF3RX_LRCLK_FRC_WIDTH                1  /* AIF3RX_LRCLK_FRC */
-#define ARIZONA_AIF3RX_LRCLK_MSTR                0x0001  /* AIF3RX_LRCLK_MSTR */
-#define ARIZONA_AIF3RX_LRCLK_MSTR_MASK           0x0001  /* AIF3RX_LRCLK_MSTR */
-#define ARIZONA_AIF3RX_LRCLK_MSTR_SHIFT               0  /* AIF3RX_LRCLK_MSTR */
-#define ARIZONA_AIF3RX_LRCLK_MSTR_WIDTH               1  /* AIF3RX_LRCLK_MSTR */
-
-/*
- * R1411 (0x583) - AIF3 Rate Ctrl
- */
-#define ARIZONA_AIF3_RATE_MASK                   0x7800  /* AIF3_RATE - [14:11] */
-#define ARIZONA_AIF3_RATE_SHIFT                      11  /* AIF3_RATE - [14:11] */
-#define ARIZONA_AIF3_RATE_WIDTH                       4  /* AIF3_RATE - [14:11] */
-#define ARIZONA_AIF3_TRI                         0x0040  /* AIF3_TRI */
-#define ARIZONA_AIF3_TRI_MASK                    0x0040  /* AIF3_TRI */
-#define ARIZONA_AIF3_TRI_SHIFT                        6  /* AIF3_TRI */
-#define ARIZONA_AIF3_TRI_WIDTH                        1  /* AIF3_TRI */
-
-/*
- * R1412 (0x584) - AIF3 Format
- */
-#define ARIZONA_AIF3_FMT_MASK                    0x0007  /* AIF3_FMT - [2:0] */
-#define ARIZONA_AIF3_FMT_SHIFT                        0  /* AIF3_FMT - [2:0] */
-#define ARIZONA_AIF3_FMT_WIDTH                        3  /* AIF3_FMT - [2:0] */
-
-/*
- * R1413 (0x585) - AIF3 Tx BCLK Rate
- */
-#define ARIZONA_AIF3TX_BCPF_MASK                 0x1FFF  /* AIF3TX_BCPF - [12:0] */
-#define ARIZONA_AIF3TX_BCPF_SHIFT                     0  /* AIF3TX_BCPF - [12:0] */
-#define ARIZONA_AIF3TX_BCPF_WIDTH                    13  /* AIF3TX_BCPF - [12:0] */
-
-/*
- * R1414 (0x586) - AIF3 Rx BCLK Rate
- */
-#define ARIZONA_AIF3RX_BCPF_MASK                 0x1FFF  /* AIF3RX_BCPF - [12:0] */
-#define ARIZONA_AIF3RX_BCPF_SHIFT                     0  /* AIF3RX_BCPF - [12:0] */
-#define ARIZONA_AIF3RX_BCPF_WIDTH                    13  /* AIF3RX_BCPF - [12:0] */
-
-/*
- * R1415 (0x587) - AIF3 Frame Ctrl 1
- */
-#define ARIZONA_AIF3TX_WL_MASK                   0x3F00  /* AIF3TX_WL - [13:8] */
-#define ARIZONA_AIF3TX_WL_SHIFT                       8  /* AIF3TX_WL - [13:8] */
-#define ARIZONA_AIF3TX_WL_WIDTH                       6  /* AIF3TX_WL - [13:8] */
-#define ARIZONA_AIF3TX_SLOT_LEN_MASK             0x00FF  /* AIF3TX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF3TX_SLOT_LEN_SHIFT                 0  /* AIF3TX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF3TX_SLOT_LEN_WIDTH                 8  /* AIF3TX_SLOT_LEN - [7:0] */
-
-/*
- * R1416 (0x588) - AIF3 Frame Ctrl 2
- */
-#define ARIZONA_AIF3RX_WL_MASK                   0x3F00  /* AIF3RX_WL - [13:8] */
-#define ARIZONA_AIF3RX_WL_SHIFT                       8  /* AIF3RX_WL - [13:8] */
-#define ARIZONA_AIF3RX_WL_WIDTH                       6  /* AIF3RX_WL - [13:8] */
-#define ARIZONA_AIF3RX_SLOT_LEN_MASK             0x00FF  /* AIF3RX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF3RX_SLOT_LEN_SHIFT                 0  /* AIF3RX_SLOT_LEN - [7:0] */
-#define ARIZONA_AIF3RX_SLOT_LEN_WIDTH                 8  /* AIF3RX_SLOT_LEN - [7:0] */
-
-/*
- * R1417 (0x589) - AIF3 Frame Ctrl 3
- */
-#define ARIZONA_AIF3TX1_SLOT_MASK                0x003F  /* AIF3TX1_SLOT - [5:0] */
-#define ARIZONA_AIF3TX1_SLOT_SHIFT                    0  /* AIF3TX1_SLOT - [5:0] */
-#define ARIZONA_AIF3TX1_SLOT_WIDTH                    6  /* AIF3TX1_SLOT - [5:0] */
-
-/*
- * R1418 (0x58A) - AIF3 Frame Ctrl 4
- */
-#define ARIZONA_AIF3TX2_SLOT_MASK                0x003F  /* AIF3TX2_SLOT - [5:0] */
-#define ARIZONA_AIF3TX2_SLOT_SHIFT                    0  /* AIF3TX2_SLOT - [5:0] */
-#define ARIZONA_AIF3TX2_SLOT_WIDTH                    6  /* AIF3TX2_SLOT - [5:0] */
-
-/*
- * R1425 (0x591) - AIF3 Frame Ctrl 11
- */
-#define ARIZONA_AIF3RX1_SLOT_MASK                0x003F  /* AIF3RX1_SLOT - [5:0] */
-#define ARIZONA_AIF3RX1_SLOT_SHIFT                    0  /* AIF3RX1_SLOT - [5:0] */
-#define ARIZONA_AIF3RX1_SLOT_WIDTH                    6  /* AIF3RX1_SLOT - [5:0] */
-
-/*
- * R1426 (0x592) - AIF3 Frame Ctrl 12
- */
-#define ARIZONA_AIF3RX2_SLOT_MASK                0x003F  /* AIF3RX2_SLOT - [5:0] */
-#define ARIZONA_AIF3RX2_SLOT_SHIFT                    0  /* AIF3RX2_SLOT - [5:0] */
-#define ARIZONA_AIF3RX2_SLOT_WIDTH                    6  /* AIF3RX2_SLOT - [5:0] */
-
-/*
- * R1433 (0x599) - AIF3 Tx Enables
- */
-#define ARIZONA_AIF3TX2_ENA                      0x0002  /* AIF3TX2_ENA */
-#define ARIZONA_AIF3TX2_ENA_MASK                 0x0002  /* AIF3TX2_ENA */
-#define ARIZONA_AIF3TX2_ENA_SHIFT                     1  /* AIF3TX2_ENA */
-#define ARIZONA_AIF3TX2_ENA_WIDTH                     1  /* AIF3TX2_ENA */
-#define ARIZONA_AIF3TX1_ENA                      0x0001  /* AIF3TX1_ENA */
-#define ARIZONA_AIF3TX1_ENA_MASK                 0x0001  /* AIF3TX1_ENA */
-#define ARIZONA_AIF3TX1_ENA_SHIFT                     0  /* AIF3TX1_ENA */
-#define ARIZONA_AIF3TX1_ENA_WIDTH                     1  /* AIF3TX1_ENA */
-
-/*
- * R1434 (0x59A) - AIF3 Rx Enables
- */
-#define ARIZONA_AIF3RX2_ENA                      0x0002  /* AIF3RX2_ENA */
-#define ARIZONA_AIF3RX2_ENA_MASK                 0x0002  /* AIF3RX2_ENA */
-#define ARIZONA_AIF3RX2_ENA_SHIFT                     1  /* AIF3RX2_ENA */
-#define ARIZONA_AIF3RX2_ENA_WIDTH                     1  /* AIF3RX2_ENA */
-#define ARIZONA_AIF3RX1_ENA                      0x0001  /* AIF3RX1_ENA */
-#define ARIZONA_AIF3RX1_ENA_MASK                 0x0001  /* AIF3RX1_ENA */
-#define ARIZONA_AIF3RX1_ENA_SHIFT                     0  /* AIF3RX1_ENA */
-#define ARIZONA_AIF3RX1_ENA_WIDTH                     1  /* AIF3RX1_ENA */
-
-/*
- * R1435 (0x59B) - AIF3 Force Write
- */
-#define ARIZONA_AIF3_FRC_WR                      0x0001  /* AIF3_FRC_WR */
-#define ARIZONA_AIF3_FRC_WR_MASK                 0x0001  /* AIF3_FRC_WR */
-#define ARIZONA_AIF3_FRC_WR_SHIFT                     0  /* AIF3_FRC_WR */
-#define ARIZONA_AIF3_FRC_WR_WIDTH                     1  /* AIF3_FRC_WR */
-
-/*
- * R1507 (0x5E3) - SLIMbus Framer Ref Gear
- */
-#define ARIZONA_SLIMCLK_SRC                      0x0010  /* SLIMCLK_SRC */
-#define ARIZONA_SLIMCLK_SRC_MASK                 0x0010  /* SLIMCLK_SRC */
-#define ARIZONA_SLIMCLK_SRC_SHIFT                     4  /* SLIMCLK_SRC */
-#define ARIZONA_SLIMCLK_SRC_WIDTH                     1  /* SLIMCLK_SRC */
-#define ARIZONA_FRAMER_REF_GEAR_MASK             0x000F  /* FRAMER_REF_GEAR - [3:0] */
-#define ARIZONA_FRAMER_REF_GEAR_SHIFT                 0  /* FRAMER_REF_GEAR - [3:0] */
-#define ARIZONA_FRAMER_REF_GEAR_WIDTH                 4  /* FRAMER_REF_GEAR - [3:0] */
-
-/*
- * R1509 (0x5E5) - SLIMbus Rates 1
- */
-#define ARIZONA_SLIMRX2_RATE_MASK                0x7800  /* SLIMRX2_RATE - [14:11] */
-#define ARIZONA_SLIMRX2_RATE_SHIFT                   11  /* SLIMRX2_RATE - [14:11] */
-#define ARIZONA_SLIMRX2_RATE_WIDTH                    4  /* SLIMRX2_RATE - [14:11] */
-#define ARIZONA_SLIMRX1_RATE_MASK                0x0078  /* SLIMRX1_RATE - [6:3] */
-#define ARIZONA_SLIMRX1_RATE_SHIFT                    3  /* SLIMRX1_RATE - [6:3] */
-#define ARIZONA_SLIMRX1_RATE_WIDTH                    4  /* SLIMRX1_RATE - [6:3] */
-
-/*
- * R1510 (0x5E6) - SLIMbus Rates 2
- */
-#define ARIZONA_SLIMRX4_RATE_MASK                0x7800  /* SLIMRX4_RATE - [14:11] */
-#define ARIZONA_SLIMRX4_RATE_SHIFT                   11  /* SLIMRX4_RATE - [14:11] */
-#define ARIZONA_SLIMRX4_RATE_WIDTH                    4  /* SLIMRX4_RATE - [14:11] */
-#define ARIZONA_SLIMRX3_RATE_MASK                0x0078  /* SLIMRX3_RATE - [6:3] */
-#define ARIZONA_SLIMRX3_RATE_SHIFT                    3  /* SLIMRX3_RATE - [6:3] */
-#define ARIZONA_SLIMRX3_RATE_WIDTH                    4  /* SLIMRX3_RATE - [6:3] */
-
-/*
- * R1511 (0x5E7) - SLIMbus Rates 3
- */
-#define ARIZONA_SLIMRX6_RATE_MASK                0x7800  /* SLIMRX6_RATE - [14:11] */
-#define ARIZONA_SLIMRX6_RATE_SHIFT                   11  /* SLIMRX6_RATE - [14:11] */
-#define ARIZONA_SLIMRX6_RATE_WIDTH                    4  /* SLIMRX6_RATE - [14:11] */
-#define ARIZONA_SLIMRX5_RATE_MASK                0x0078  /* SLIMRX5_RATE - [6:3] */
-#define ARIZONA_SLIMRX5_RATE_SHIFT                    3  /* SLIMRX5_RATE - [6:3] */
-#define ARIZONA_SLIMRX5_RATE_WIDTH                    4  /* SLIMRX5_RATE - [6:3] */
-
-/*
- * R1512 (0x5E8) - SLIMbus Rates 4
- */
-#define ARIZONA_SLIMRX8_RATE_MASK                0x7800  /* SLIMRX8_RATE - [14:11] */
-#define ARIZONA_SLIMRX8_RATE_SHIFT                   11  /* SLIMRX8_RATE - [14:11] */
-#define ARIZONA_SLIMRX8_RATE_WIDTH                    4  /* SLIMRX8_RATE - [14:11] */
-#define ARIZONA_SLIMRX7_RATE_MASK                0x0078  /* SLIMRX7_RATE - [6:3] */
-#define ARIZONA_SLIMRX7_RATE_SHIFT                    3  /* SLIMRX7_RATE - [6:3] */
-#define ARIZONA_SLIMRX7_RATE_WIDTH                    4  /* SLIMRX7_RATE - [6:3] */
-
-/*
- * R1513 (0x5E9) - SLIMbus Rates 5
- */
-#define ARIZONA_SLIMTX2_RATE_MASK                0x7800  /* SLIMTX2_RATE - [14:11] */
-#define ARIZONA_SLIMTX2_RATE_SHIFT                   11  /* SLIMTX2_RATE - [14:11] */
-#define ARIZONA_SLIMTX2_RATE_WIDTH                    4  /* SLIMTX2_RATE - [14:11] */
-#define ARIZONA_SLIMTX1_RATE_MASK                0x0078  /* SLIMTX1_RATE - [6:3] */
-#define ARIZONA_SLIMTX1_RATE_SHIFT                    3  /* SLIMTX1_RATE - [6:3] */
-#define ARIZONA_SLIMTX1_RATE_WIDTH                    4  /* SLIMTX1_RATE - [6:3] */
-
-/*
- * R1514 (0x5EA) - SLIMbus Rates 6
- */
-#define ARIZONA_SLIMTX4_RATE_MASK                0x7800  /* SLIMTX4_RATE - [14:11] */
-#define ARIZONA_SLIMTX4_RATE_SHIFT                   11  /* SLIMTX4_RATE - [14:11] */
-#define ARIZONA_SLIMTX4_RATE_WIDTH                    4  /* SLIMTX4_RATE - [14:11] */
-#define ARIZONA_SLIMTX3_RATE_MASK                0x0078  /* SLIMTX3_RATE - [6:3] */
-#define ARIZONA_SLIMTX3_RATE_SHIFT                    3  /* SLIMTX3_RATE - [6:3] */
-#define ARIZONA_SLIMTX3_RATE_WIDTH                    4  /* SLIMTX3_RATE - [6:3] */
-
-/*
- * R1515 (0x5EB) - SLIMbus Rates 7
- */
-#define ARIZONA_SLIMTX6_RATE_MASK                0x7800  /* SLIMTX6_RATE - [14:11] */
-#define ARIZONA_SLIMTX6_RATE_SHIFT                   11  /* SLIMTX6_RATE - [14:11] */
-#define ARIZONA_SLIMTX6_RATE_WIDTH                    4  /* SLIMTX6_RATE - [14:11] */
-#define ARIZONA_SLIMTX5_RATE_MASK                0x0078  /* SLIMTX5_RATE - [6:3] */
-#define ARIZONA_SLIMTX5_RATE_SHIFT                    3  /* SLIMTX5_RATE - [6:3] */
-#define ARIZONA_SLIMTX5_RATE_WIDTH                    4  /* SLIMTX5_RATE - [6:3] */
-
-/*
- * R1516 (0x5EC) - SLIMbus Rates 8
- */
-#define ARIZONA_SLIMTX8_RATE_MASK                0x7800  /* SLIMTX8_RATE - [14:11] */
-#define ARIZONA_SLIMTX8_RATE_SHIFT                   11  /* SLIMTX8_RATE - [14:11] */
-#define ARIZONA_SLIMTX8_RATE_WIDTH                    4  /* SLIMTX8_RATE - [14:11] */
-#define ARIZONA_SLIMTX7_RATE_MASK                0x0078  /* SLIMTX7_RATE - [6:3] */
-#define ARIZONA_SLIMTX7_RATE_SHIFT                    3  /* SLIMTX7_RATE - [6:3] */
-#define ARIZONA_SLIMTX7_RATE_WIDTH                    4  /* SLIMTX7_RATE - [6:3] */
-
-/*
- * R1525 (0x5F5) - SLIMbus RX Channel Enable
- */
-#define ARIZONA_SLIMRX8_ENA                      0x0080  /* SLIMRX8_ENA */
-#define ARIZONA_SLIMRX8_ENA_MASK                 0x0080  /* SLIMRX8_ENA */
-#define ARIZONA_SLIMRX8_ENA_SHIFT                     7  /* SLIMRX8_ENA */
-#define ARIZONA_SLIMRX8_ENA_WIDTH                     1  /* SLIMRX8_ENA */
-#define ARIZONA_SLIMRX7_ENA                      0x0040  /* SLIMRX7_ENA */
-#define ARIZONA_SLIMRX7_ENA_MASK                 0x0040  /* SLIMRX7_ENA */
-#define ARIZONA_SLIMRX7_ENA_SHIFT                     6  /* SLIMRX7_ENA */
-#define ARIZONA_SLIMRX7_ENA_WIDTH                     1  /* SLIMRX7_ENA */
-#define ARIZONA_SLIMRX6_ENA                      0x0020  /* SLIMRX6_ENA */
-#define ARIZONA_SLIMRX6_ENA_MASK                 0x0020  /* SLIMRX6_ENA */
-#define ARIZONA_SLIMRX6_ENA_SHIFT                     5  /* SLIMRX6_ENA */
-#define ARIZONA_SLIMRX6_ENA_WIDTH                     1  /* SLIMRX6_ENA */
-#define ARIZONA_SLIMRX5_ENA                      0x0010  /* SLIMRX5_ENA */
-#define ARIZONA_SLIMRX5_ENA_MASK                 0x0010  /* SLIMRX5_ENA */
-#define ARIZONA_SLIMRX5_ENA_SHIFT                     4  /* SLIMRX5_ENA */
-#define ARIZONA_SLIMRX5_ENA_WIDTH                     1  /* SLIMRX5_ENA */
-#define ARIZONA_SLIMRX4_ENA                      0x0008  /* SLIMRX4_ENA */
-#define ARIZONA_SLIMRX4_ENA_MASK                 0x0008  /* SLIMRX4_ENA */
-#define ARIZONA_SLIMRX4_ENA_SHIFT                     3  /* SLIMRX4_ENA */
-#define ARIZONA_SLIMRX4_ENA_WIDTH                     1  /* SLIMRX4_ENA */
-#define ARIZONA_SLIMRX3_ENA                      0x0004  /* SLIMRX3_ENA */
-#define ARIZONA_SLIMRX3_ENA_MASK                 0x0004  /* SLIMRX3_ENA */
-#define ARIZONA_SLIMRX3_ENA_SHIFT                     2  /* SLIMRX3_ENA */
-#define ARIZONA_SLIMRX3_ENA_WIDTH                     1  /* SLIMRX3_ENA */
-#define ARIZONA_SLIMRX2_ENA                      0x0002  /* SLIMRX2_ENA */
-#define ARIZONA_SLIMRX2_ENA_MASK                 0x0002  /* SLIMRX2_ENA */
-#define ARIZONA_SLIMRX2_ENA_SHIFT                     1  /* SLIMRX2_ENA */
-#define ARIZONA_SLIMRX2_ENA_WIDTH                     1  /* SLIMRX2_ENA */
-#define ARIZONA_SLIMRX1_ENA                      0x0001  /* SLIMRX1_ENA */
-#define ARIZONA_SLIMRX1_ENA_MASK                 0x0001  /* SLIMRX1_ENA */
-#define ARIZONA_SLIMRX1_ENA_SHIFT                     0  /* SLIMRX1_ENA */
-#define ARIZONA_SLIMRX1_ENA_WIDTH                     1  /* SLIMRX1_ENA */
-
-/*
- * R1526 (0x5F6) - SLIMbus TX Channel Enable
- */
-#define ARIZONA_SLIMTX8_ENA                      0x0080  /* SLIMTX8_ENA */
-#define ARIZONA_SLIMTX8_ENA_MASK                 0x0080  /* SLIMTX8_ENA */
-#define ARIZONA_SLIMTX8_ENA_SHIFT                     7  /* SLIMTX8_ENA */
-#define ARIZONA_SLIMTX8_ENA_WIDTH                     1  /* SLIMTX8_ENA */
-#define ARIZONA_SLIMTX7_ENA                      0x0040  /* SLIMTX7_ENA */
-#define ARIZONA_SLIMTX7_ENA_MASK                 0x0040  /* SLIMTX7_ENA */
-#define ARIZONA_SLIMTX7_ENA_SHIFT                     6  /* SLIMTX7_ENA */
-#define ARIZONA_SLIMTX7_ENA_WIDTH                     1  /* SLIMTX7_ENA */
-#define ARIZONA_SLIMTX6_ENA                      0x0020  /* SLIMTX6_ENA */
-#define ARIZONA_SLIMTX6_ENA_MASK                 0x0020  /* SLIMTX6_ENA */
-#define ARIZONA_SLIMTX6_ENA_SHIFT                     5  /* SLIMTX6_ENA */
-#define ARIZONA_SLIMTX6_ENA_WIDTH                     1  /* SLIMTX6_ENA */
-#define ARIZONA_SLIMTX5_ENA                      0x0010  /* SLIMTX5_ENA */
-#define ARIZONA_SLIMTX5_ENA_MASK                 0x0010  /* SLIMTX5_ENA */
-#define ARIZONA_SLIMTX5_ENA_SHIFT                     4  /* SLIMTX5_ENA */
-#define ARIZONA_SLIMTX5_ENA_WIDTH                     1  /* SLIMTX5_ENA */
-#define ARIZONA_SLIMTX4_ENA                      0x0008  /* SLIMTX4_ENA */
-#define ARIZONA_SLIMTX4_ENA_MASK                 0x0008  /* SLIMTX4_ENA */
-#define ARIZONA_SLIMTX4_ENA_SHIFT                     3  /* SLIMTX4_ENA */
-#define ARIZONA_SLIMTX4_ENA_WIDTH                     1  /* SLIMTX4_ENA */
-#define ARIZONA_SLIMTX3_ENA                      0x0004  /* SLIMTX3_ENA */
-#define ARIZONA_SLIMTX3_ENA_MASK                 0x0004  /* SLIMTX3_ENA */
-#define ARIZONA_SLIMTX3_ENA_SHIFT                     2  /* SLIMTX3_ENA */
-#define ARIZONA_SLIMTX3_ENA_WIDTH                     1  /* SLIMTX3_ENA */
-#define ARIZONA_SLIMTX2_ENA                      0x0002  /* SLIMTX2_ENA */
-#define ARIZONA_SLIMTX2_ENA_MASK                 0x0002  /* SLIMTX2_ENA */
-#define ARIZONA_SLIMTX2_ENA_SHIFT                     1  /* SLIMTX2_ENA */
-#define ARIZONA_SLIMTX2_ENA_WIDTH                     1  /* SLIMTX2_ENA */
-#define ARIZONA_SLIMTX1_ENA                      0x0001  /* SLIMTX1_ENA */
-#define ARIZONA_SLIMTX1_ENA_MASK                 0x0001  /* SLIMTX1_ENA */
-#define ARIZONA_SLIMTX1_ENA_SHIFT                     0  /* SLIMTX1_ENA */
-#define ARIZONA_SLIMTX1_ENA_WIDTH                     1  /* SLIMTX1_ENA */
-
-/*
- * R1527 (0x5F7) - SLIMbus RX Port Status
- */
-#define ARIZONA_SLIMRX8_PORT_STS                 0x0080  /* SLIMRX8_PORT_STS */
-#define ARIZONA_SLIMRX8_PORT_STS_MASK            0x0080  /* SLIMRX8_PORT_STS */
-#define ARIZONA_SLIMRX8_PORT_STS_SHIFT                7  /* SLIMRX8_PORT_STS */
-#define ARIZONA_SLIMRX8_PORT_STS_WIDTH                1  /* SLIMRX8_PORT_STS */
-#define ARIZONA_SLIMRX7_PORT_STS                 0x0040  /* SLIMRX7_PORT_STS */
-#define ARIZONA_SLIMRX7_PORT_STS_MASK            0x0040  /* SLIMRX7_PORT_STS */
-#define ARIZONA_SLIMRX7_PORT_STS_SHIFT                6  /* SLIMRX7_PORT_STS */
-#define ARIZONA_SLIMRX7_PORT_STS_WIDTH                1  /* SLIMRX7_PORT_STS */
-#define ARIZONA_SLIMRX6_PORT_STS                 0x0020  /* SLIMRX6_PORT_STS */
-#define ARIZONA_SLIMRX6_PORT_STS_MASK            0x0020  /* SLIMRX6_PORT_STS */
-#define ARIZONA_SLIMRX6_PORT_STS_SHIFT                5  /* SLIMRX6_PORT_STS */
-#define ARIZONA_SLIMRX6_PORT_STS_WIDTH                1  /* SLIMRX6_PORT_STS */
-#define ARIZONA_SLIMRX5_PORT_STS                 0x0010  /* SLIMRX5_PORT_STS */
-#define ARIZONA_SLIMRX5_PORT_STS_MASK            0x0010  /* SLIMRX5_PORT_STS */
-#define ARIZONA_SLIMRX5_PORT_STS_SHIFT                4  /* SLIMRX5_PORT_STS */
-#define ARIZONA_SLIMRX5_PORT_STS_WIDTH                1  /* SLIMRX5_PORT_STS */
-#define ARIZONA_SLIMRX4_PORT_STS                 0x0008  /* SLIMRX4_PORT_STS */
-#define ARIZONA_SLIMRX4_PORT_STS_MASK            0x0008  /* SLIMRX4_PORT_STS */
-#define ARIZONA_SLIMRX4_PORT_STS_SHIFT                3  /* SLIMRX4_PORT_STS */
-#define ARIZONA_SLIMRX4_PORT_STS_WIDTH                1  /* SLIMRX4_PORT_STS */
-#define ARIZONA_SLIMRX3_PORT_STS                 0x0004  /* SLIMRX3_PORT_STS */
-#define ARIZONA_SLIMRX3_PORT_STS_MASK            0x0004  /* SLIMRX3_PORT_STS */
-#define ARIZONA_SLIMRX3_PORT_STS_SHIFT                2  /* SLIMRX3_PORT_STS */
-#define ARIZONA_SLIMRX3_PORT_STS_WIDTH                1  /* SLIMRX3_PORT_STS */
-#define ARIZONA_SLIMRX2_PORT_STS                 0x0002  /* SLIMRX2_PORT_STS */
-#define ARIZONA_SLIMRX2_PORT_STS_MASK            0x0002  /* SLIMRX2_PORT_STS */
-#define ARIZONA_SLIMRX2_PORT_STS_SHIFT                1  /* SLIMRX2_PORT_STS */
-#define ARIZONA_SLIMRX2_PORT_STS_WIDTH                1  /* SLIMRX2_PORT_STS */
-#define ARIZONA_SLIMRX1_PORT_STS                 0x0001  /* SLIMRX1_PORT_STS */
-#define ARIZONA_SLIMRX1_PORT_STS_MASK            0x0001  /* SLIMRX1_PORT_STS */
-#define ARIZONA_SLIMRX1_PORT_STS_SHIFT                0  /* SLIMRX1_PORT_STS */
-#define ARIZONA_SLIMRX1_PORT_STS_WIDTH                1  /* SLIMRX1_PORT_STS */
-
-/*
- * R1528 (0x5F8) - SLIMbus TX Port Status
- */
-#define ARIZONA_SLIMTX8_PORT_STS                 0x0080  /* SLIMTX8_PORT_STS */
-#define ARIZONA_SLIMTX8_PORT_STS_MASK            0x0080  /* SLIMTX8_PORT_STS */
-#define ARIZONA_SLIMTX8_PORT_STS_SHIFT                7  /* SLIMTX8_PORT_STS */
-#define ARIZONA_SLIMTX8_PORT_STS_WIDTH                1  /* SLIMTX8_PORT_STS */
-#define ARIZONA_SLIMTX7_PORT_STS                 0x0040  /* SLIMTX7_PORT_STS */
-#define ARIZONA_SLIMTX7_PORT_STS_MASK            0x0040  /* SLIMTX7_PORT_STS */
-#define ARIZONA_SLIMTX7_PORT_STS_SHIFT                6  /* SLIMTX7_PORT_STS */
-#define ARIZONA_SLIMTX7_PORT_STS_WIDTH                1  /* SLIMTX7_PORT_STS */
-#define ARIZONA_SLIMTX6_PORT_STS                 0x0020  /* SLIMTX6_PORT_STS */
-#define ARIZONA_SLIMTX6_PORT_STS_MASK            0x0020  /* SLIMTX6_PORT_STS */
-#define ARIZONA_SLIMTX6_PORT_STS_SHIFT                5  /* SLIMTX6_PORT_STS */
-#define ARIZONA_SLIMTX6_PORT_STS_WIDTH                1  /* SLIMTX6_PORT_STS */
-#define ARIZONA_SLIMTX5_PORT_STS                 0x0010  /* SLIMTX5_PORT_STS */
-#define ARIZONA_SLIMTX5_PORT_STS_MASK            0x0010  /* SLIMTX5_PORT_STS */
-#define ARIZONA_SLIMTX5_PORT_STS_SHIFT                4  /* SLIMTX5_PORT_STS */
-#define ARIZONA_SLIMTX5_PORT_STS_WIDTH                1  /* SLIMTX5_PORT_STS */
-#define ARIZONA_SLIMTX4_PORT_STS                 0x0008  /* SLIMTX4_PORT_STS */
-#define ARIZONA_SLIMTX4_PORT_STS_MASK            0x0008  /* SLIMTX4_PORT_STS */
-#define ARIZONA_SLIMTX4_PORT_STS_SHIFT                3  /* SLIMTX4_PORT_STS */
-#define ARIZONA_SLIMTX4_PORT_STS_WIDTH                1  /* SLIMTX4_PORT_STS */
-#define ARIZONA_SLIMTX3_PORT_STS                 0x0004  /* SLIMTX3_PORT_STS */
-#define ARIZONA_SLIMTX3_PORT_STS_MASK            0x0004  /* SLIMTX3_PORT_STS */
-#define ARIZONA_SLIMTX3_PORT_STS_SHIFT                2  /* SLIMTX3_PORT_STS */
-#define ARIZONA_SLIMTX3_PORT_STS_WIDTH                1  /* SLIMTX3_PORT_STS */
-#define ARIZONA_SLIMTX2_PORT_STS                 0x0002  /* SLIMTX2_PORT_STS */
-#define ARIZONA_SLIMTX2_PORT_STS_MASK            0x0002  /* SLIMTX2_PORT_STS */
-#define ARIZONA_SLIMTX2_PORT_STS_SHIFT                1  /* SLIMTX2_PORT_STS */
-#define ARIZONA_SLIMTX2_PORT_STS_WIDTH                1  /* SLIMTX2_PORT_STS */
-#define ARIZONA_SLIMTX1_PORT_STS                 0x0001  /* SLIMTX1_PORT_STS */
-#define ARIZONA_SLIMTX1_PORT_STS_MASK            0x0001  /* SLIMTX1_PORT_STS */
-#define ARIZONA_SLIMTX1_PORT_STS_SHIFT                0  /* SLIMTX1_PORT_STS */
-#define ARIZONA_SLIMTX1_PORT_STS_WIDTH                1  /* SLIMTX1_PORT_STS */
-
-/*
- * R3087 (0xC0F) - IRQ CTRL 1
- */
-#define ARIZONA_IRQ_POL                          0x0400  /* IRQ_POL */
-#define ARIZONA_IRQ_POL_MASK                     0x0400  /* IRQ_POL */
-#define ARIZONA_IRQ_POL_SHIFT                        10  /* IRQ_POL */
-#define ARIZONA_IRQ_POL_WIDTH                         1  /* IRQ_POL */
-#define ARIZONA_IRQ_OP_CFG                       0x0200  /* IRQ_OP_CFG */
-#define ARIZONA_IRQ_OP_CFG_MASK                  0x0200  /* IRQ_OP_CFG */
-#define ARIZONA_IRQ_OP_CFG_SHIFT                      9  /* IRQ_OP_CFG */
-#define ARIZONA_IRQ_OP_CFG_WIDTH                      1  /* IRQ_OP_CFG */
-
-/*
- * R3088 (0xC10) - GPIO Debounce Config
- */
-#define ARIZONA_GP_DBTIME_MASK                   0xF000  /* GP_DBTIME - [15:12] */
-#define ARIZONA_GP_DBTIME_SHIFT                      12  /* GP_DBTIME - [15:12] */
-#define ARIZONA_GP_DBTIME_WIDTH                       4  /* GP_DBTIME - [15:12] */
-
-/*
- * R3104 (0xC20) - Misc Pad Ctrl 1
- */
-#define ARIZONA_LDO1ENA_PD                       0x8000  /* LDO1ENA_PD */
-#define ARIZONA_LDO1ENA_PD_MASK                  0x8000  /* LDO1ENA_PD */
-#define ARIZONA_LDO1ENA_PD_SHIFT                     15  /* LDO1ENA_PD */
-#define ARIZONA_LDO1ENA_PD_WIDTH                      1  /* LDO1ENA_PD */
-#define ARIZONA_MCLK2_PD                         0x2000  /* MCLK2_PD */
-#define ARIZONA_MCLK2_PD_MASK                    0x2000  /* MCLK2_PD */
-#define ARIZONA_MCLK2_PD_SHIFT                       13  /* MCLK2_PD */
-#define ARIZONA_MCLK2_PD_WIDTH                        1  /* MCLK2_PD */
-#define ARIZONA_RSTB_PU                          0x0002  /* RSTB_PU */
-#define ARIZONA_RSTB_PU_MASK                     0x0002  /* RSTB_PU */
-#define ARIZONA_RSTB_PU_SHIFT                         1  /* RSTB_PU */
-#define ARIZONA_RSTB_PU_WIDTH                         1  /* RSTB_PU */
-
-/*
- * R3105 (0xC21) - Misc Pad Ctrl 2
- */
-#define ARIZONA_MCLK1_PD                         0x1000  /* MCLK1_PD */
-#define ARIZONA_MCLK1_PD_MASK                    0x1000  /* MCLK1_PD */
-#define ARIZONA_MCLK1_PD_SHIFT                       12  /* MCLK1_PD */
-#define ARIZONA_MCLK1_PD_WIDTH                        1  /* MCLK1_PD */
-#define ARIZONA_MICD_PD                          0x0100  /* MICD_PD */
-#define ARIZONA_MICD_PD_MASK                     0x0100  /* MICD_PD */
-#define ARIZONA_MICD_PD_SHIFT                         8  /* MICD_PD */
-#define ARIZONA_MICD_PD_WIDTH                         1  /* MICD_PD */
-#define ARIZONA_ADDR_PD                          0x0001  /* ADDR_PD */
-#define ARIZONA_ADDR_PD_MASK                     0x0001  /* ADDR_PD */
-#define ARIZONA_ADDR_PD_SHIFT                         0  /* ADDR_PD */
-#define ARIZONA_ADDR_PD_WIDTH                         1  /* ADDR_PD */
-
-/*
- * R3106 (0xC22) - Misc Pad Ctrl 3
- */
-#define ARIZONA_DMICDAT4_PD                      0x0008  /* DMICDAT4_PD */
-#define ARIZONA_DMICDAT4_PD_MASK                 0x0008  /* DMICDAT4_PD */
-#define ARIZONA_DMICDAT4_PD_SHIFT                     3  /* DMICDAT4_PD */
-#define ARIZONA_DMICDAT4_PD_WIDTH                     1  /* DMICDAT4_PD */
-#define ARIZONA_DMICDAT3_PD                      0x0004  /* DMICDAT3_PD */
-#define ARIZONA_DMICDAT3_PD_MASK                 0x0004  /* DMICDAT3_PD */
-#define ARIZONA_DMICDAT3_PD_SHIFT                     2  /* DMICDAT3_PD */
-#define ARIZONA_DMICDAT3_PD_WIDTH                     1  /* DMICDAT3_PD */
-#define ARIZONA_DMICDAT2_PD                      0x0002  /* DMICDAT2_PD */
-#define ARIZONA_DMICDAT2_PD_MASK                 0x0002  /* DMICDAT2_PD */
-#define ARIZONA_DMICDAT2_PD_SHIFT                     1  /* DMICDAT2_PD */
-#define ARIZONA_DMICDAT2_PD_WIDTH                     1  /* DMICDAT2_PD */
-#define ARIZONA_DMICDAT1_PD                      0x0001  /* DMICDAT1_PD */
-#define ARIZONA_DMICDAT1_PD_MASK                 0x0001  /* DMICDAT1_PD */
-#define ARIZONA_DMICDAT1_PD_SHIFT                     0  /* DMICDAT1_PD */
-#define ARIZONA_DMICDAT1_PD_WIDTH                     1  /* DMICDAT1_PD */
-
-/*
- * R3107 (0xC23) - Misc Pad Ctrl 4
- */
-#define ARIZONA_AIF1RXLRCLK_PU                   0x0020  /* AIF1RXLRCLK_PU */
-#define ARIZONA_AIF1RXLRCLK_PU_MASK              0x0020  /* AIF1RXLRCLK_PU */
-#define ARIZONA_AIF1RXLRCLK_PU_SHIFT                  5  /* AIF1RXLRCLK_PU */
-#define ARIZONA_AIF1RXLRCLK_PU_WIDTH                  1  /* AIF1RXLRCLK_PU */
-#define ARIZONA_AIF1RXLRCLK_PD                   0x0010  /* AIF1RXLRCLK_PD */
-#define ARIZONA_AIF1RXLRCLK_PD_MASK              0x0010  /* AIF1RXLRCLK_PD */
-#define ARIZONA_AIF1RXLRCLK_PD_SHIFT                  4  /* AIF1RXLRCLK_PD */
-#define ARIZONA_AIF1RXLRCLK_PD_WIDTH                  1  /* AIF1RXLRCLK_PD */
-#define ARIZONA_AIF1BCLK_PU                      0x0008  /* AIF1BCLK_PU */
-#define ARIZONA_AIF1BCLK_PU_MASK                 0x0008  /* AIF1BCLK_PU */
-#define ARIZONA_AIF1BCLK_PU_SHIFT                     3  /* AIF1BCLK_PU */
-#define ARIZONA_AIF1BCLK_PU_WIDTH                     1  /* AIF1BCLK_PU */
-#define ARIZONA_AIF1BCLK_PD                      0x0004  /* AIF1BCLK_PD */
-#define ARIZONA_AIF1BCLK_PD_MASK                 0x0004  /* AIF1BCLK_PD */
-#define ARIZONA_AIF1BCLK_PD_SHIFT                     2  /* AIF1BCLK_PD */
-#define ARIZONA_AIF1BCLK_PD_WIDTH                     1  /* AIF1BCLK_PD */
-#define ARIZONA_AIF1RXDAT_PU                     0x0002  /* AIF1RXDAT_PU */
-#define ARIZONA_AIF1RXDAT_PU_MASK                0x0002  /* AIF1RXDAT_PU */
-#define ARIZONA_AIF1RXDAT_PU_SHIFT                    1  /* AIF1RXDAT_PU */
-#define ARIZONA_AIF1RXDAT_PU_WIDTH                    1  /* AIF1RXDAT_PU */
-#define ARIZONA_AIF1RXDAT_PD                     0x0001  /* AIF1RXDAT_PD */
-#define ARIZONA_AIF1RXDAT_PD_MASK                0x0001  /* AIF1RXDAT_PD */
-#define ARIZONA_AIF1RXDAT_PD_SHIFT                    0  /* AIF1RXDAT_PD */
-#define ARIZONA_AIF1RXDAT_PD_WIDTH                    1  /* AIF1RXDAT_PD */
-
-/*
- * R3108 (0xC24) - Misc Pad Ctrl 5
- */
-#define ARIZONA_AIF2RXLRCLK_PU                   0x0020  /* AIF2RXLRCLK_PU */
-#define ARIZONA_AIF2RXLRCLK_PU_MASK              0x0020  /* AIF2RXLRCLK_PU */
-#define ARIZONA_AIF2RXLRCLK_PU_SHIFT                  5  /* AIF2RXLRCLK_PU */
-#define ARIZONA_AIF2RXLRCLK_PU_WIDTH                  1  /* AIF2RXLRCLK_PU */
-#define ARIZONA_AIF2RXLRCLK_PD                   0x0010  /* AIF2RXLRCLK_PD */
-#define ARIZONA_AIF2RXLRCLK_PD_MASK              0x0010  /* AIF2RXLRCLK_PD */
-#define ARIZONA_AIF2RXLRCLK_PD_SHIFT                  4  /* AIF2RXLRCLK_PD */
-#define ARIZONA_AIF2RXLRCLK_PD_WIDTH                  1  /* AIF2RXLRCLK_PD */
-#define ARIZONA_AIF2BCLK_PU                      0x0008  /* AIF2BCLK_PU */
-#define ARIZONA_AIF2BCLK_PU_MASK                 0x0008  /* AIF2BCLK_PU */
-#define ARIZONA_AIF2BCLK_PU_SHIFT                     3  /* AIF2BCLK_PU */
-#define ARIZONA_AIF2BCLK_PU_WIDTH                     1  /* AIF2BCLK_PU */
-#define ARIZONA_AIF2BCLK_PD                      0x0004  /* AIF2BCLK_PD */
-#define ARIZONA_AIF2BCLK_PD_MASK                 0x0004  /* AIF2BCLK_PD */
-#define ARIZONA_AIF2BCLK_PD_SHIFT                     2  /* AIF2BCLK_PD */
-#define ARIZONA_AIF2BCLK_PD_WIDTH                     1  /* AIF2BCLK_PD */
-#define ARIZONA_AIF2RXDAT_PU                     0x0002  /* AIF2RXDAT_PU */
-#define ARIZONA_AIF2RXDAT_PU_MASK                0x0002  /* AIF2RXDAT_PU */
-#define ARIZONA_AIF2RXDAT_PU_SHIFT                    1  /* AIF2RXDAT_PU */
-#define ARIZONA_AIF2RXDAT_PU_WIDTH                    1  /* AIF2RXDAT_PU */
-#define ARIZONA_AIF2RXDAT_PD                     0x0001  /* AIF2RXDAT_PD */
-#define ARIZONA_AIF2RXDAT_PD_MASK                0x0001  /* AIF2RXDAT_PD */
-#define ARIZONA_AIF2RXDAT_PD_SHIFT                    0  /* AIF2RXDAT_PD */
-#define ARIZONA_AIF2RXDAT_PD_WIDTH                    1  /* AIF2RXDAT_PD */
-
-/*
- * R3109 (0xC25) - Misc Pad Ctrl 6
- */
-#define ARIZONA_AIF3RXLRCLK_PU                   0x0020  /* AIF3RXLRCLK_PU */
-#define ARIZONA_AIF3RXLRCLK_PU_MASK              0x0020  /* AIF3RXLRCLK_PU */
-#define ARIZONA_AIF3RXLRCLK_PU_SHIFT                  5  /* AIF3RXLRCLK_PU */
-#define ARIZONA_AIF3RXLRCLK_PU_WIDTH                  1  /* AIF3RXLRCLK_PU */
-#define ARIZONA_AIF3RXLRCLK_PD                   0x0010  /* AIF3RXLRCLK_PD */
-#define ARIZONA_AIF3RXLRCLK_PD_MASK              0x0010  /* AIF3RXLRCLK_PD */
-#define ARIZONA_AIF3RXLRCLK_PD_SHIFT                  4  /* AIF3RXLRCLK_PD */
-#define ARIZONA_AIF3RXLRCLK_PD_WIDTH                  1  /* AIF3RXLRCLK_PD */
-#define ARIZONA_AIF3BCLK_PU                      0x0008  /* AIF3BCLK_PU */
-#define ARIZONA_AIF3BCLK_PU_MASK                 0x0008  /* AIF3BCLK_PU */
-#define ARIZONA_AIF3BCLK_PU_SHIFT                     3  /* AIF3BCLK_PU */
-#define ARIZONA_AIF3BCLK_PU_WIDTH                     1  /* AIF3BCLK_PU */
-#define ARIZONA_AIF3BCLK_PD                      0x0004  /* AIF3BCLK_PD */
-#define ARIZONA_AIF3BCLK_PD_MASK                 0x0004  /* AIF3BCLK_PD */
-#define ARIZONA_AIF3BCLK_PD_SHIFT                     2  /* AIF3BCLK_PD */
-#define ARIZONA_AIF3BCLK_PD_WIDTH                     1  /* AIF3BCLK_PD */
-#define ARIZONA_AIF3RXDAT_PU                     0x0002  /* AIF3RXDAT_PU */
-#define ARIZONA_AIF3RXDAT_PU_MASK                0x0002  /* AIF3RXDAT_PU */
-#define ARIZONA_AIF3RXDAT_PU_SHIFT                    1  /* AIF3RXDAT_PU */
-#define ARIZONA_AIF3RXDAT_PU_WIDTH                    1  /* AIF3RXDAT_PU */
-#define ARIZONA_AIF3RXDAT_PD                     0x0001  /* AIF3RXDAT_PD */
-#define ARIZONA_AIF3RXDAT_PD_MASK                0x0001  /* AIF3RXDAT_PD */
-#define ARIZONA_AIF3RXDAT_PD_SHIFT                    0  /* AIF3RXDAT_PD */
-#define ARIZONA_AIF3RXDAT_PD_WIDTH                    1  /* AIF3RXDAT_PD */
-
-/*
- * R3328 (0xD00) - Interrupt Status 1
- */
-#define ARIZONA_GP4_EINT1                        0x0008  /* GP4_EINT1 */
-#define ARIZONA_GP4_EINT1_MASK                   0x0008  /* GP4_EINT1 */
-#define ARIZONA_GP4_EINT1_SHIFT                       3  /* GP4_EINT1 */
-#define ARIZONA_GP4_EINT1_WIDTH                       1  /* GP4_EINT1 */
-#define ARIZONA_GP3_EINT1                        0x0004  /* GP3_EINT1 */
-#define ARIZONA_GP3_EINT1_MASK                   0x0004  /* GP3_EINT1 */
-#define ARIZONA_GP3_EINT1_SHIFT                       2  /* GP3_EINT1 */
-#define ARIZONA_GP3_EINT1_WIDTH                       1  /* GP3_EINT1 */
-#define ARIZONA_GP2_EINT1                        0x0002  /* GP2_EINT1 */
-#define ARIZONA_GP2_EINT1_MASK                   0x0002  /* GP2_EINT1 */
-#define ARIZONA_GP2_EINT1_SHIFT                       1  /* GP2_EINT1 */
-#define ARIZONA_GP2_EINT1_WIDTH                       1  /* GP2_EINT1 */
-#define ARIZONA_GP1_EINT1                        0x0001  /* GP1_EINT1 */
-#define ARIZONA_GP1_EINT1_MASK                   0x0001  /* GP1_EINT1 */
-#define ARIZONA_GP1_EINT1_SHIFT                       0  /* GP1_EINT1 */
-#define ARIZONA_GP1_EINT1_WIDTH                       1  /* GP1_EINT1 */
-
-/*
- * R3329 (0xD01) - Interrupt Status 2
- */
-#define ARIZONA_DSP4_RAM_RDY_EINT1               0x0800  /* DSP4_RAM_RDY_EINT1 */
-#define ARIZONA_DSP4_RAM_RDY_EINT1_MASK          0x0800  /* DSP4_RAM_RDY_EINT1 */
-#define ARIZONA_DSP4_RAM_RDY_EINT1_SHIFT             11  /* DSP4_RAM_RDY_EINT1 */
-#define ARIZONA_DSP4_RAM_RDY_EINT1_WIDTH              1  /* DSP4_RAM_RDY_EINT1 */
-#define ARIZONA_DSP3_RAM_RDY_EINT1               0x0400  /* DSP3_RAM_RDY_EINT1 */
-#define ARIZONA_DSP3_RAM_RDY_EINT1_MASK          0x0400  /* DSP3_RAM_RDY_EINT1 */
-#define ARIZONA_DSP3_RAM_RDY_EINT1_SHIFT             10  /* DSP3_RAM_RDY_EINT1 */
-#define ARIZONA_DSP3_RAM_RDY_EINT1_WIDTH              1  /* DSP3_RAM_RDY_EINT1 */
-#define ARIZONA_DSP2_RAM_RDY_EINT1               0x0200  /* DSP2_RAM_RDY_EINT1 */
-#define ARIZONA_DSP2_RAM_RDY_EINT1_MASK          0x0200  /* DSP2_RAM_RDY_EINT1 */
-#define ARIZONA_DSP2_RAM_RDY_EINT1_SHIFT              9  /* DSP2_RAM_RDY_EINT1 */
-#define ARIZONA_DSP2_RAM_RDY_EINT1_WIDTH              1  /* DSP2_RAM_RDY_EINT1 */
-#define ARIZONA_DSP1_RAM_RDY_EINT1               0x0100  /* DSP1_RAM_RDY_EINT1 */
-#define ARIZONA_DSP1_RAM_RDY_EINT1_MASK          0x0100  /* DSP1_RAM_RDY_EINT1 */
-#define ARIZONA_DSP1_RAM_RDY_EINT1_SHIFT              8  /* DSP1_RAM_RDY_EINT1 */
-#define ARIZONA_DSP1_RAM_RDY_EINT1_WIDTH              1  /* DSP1_RAM_RDY_EINT1 */
-#define ARIZONA_DSP_IRQ8_EINT1                   0x0080  /* DSP_IRQ8_EINT1 */
-#define ARIZONA_DSP_IRQ8_EINT1_MASK              0x0080  /* DSP_IRQ8_EINT1 */
-#define ARIZONA_DSP_IRQ8_EINT1_SHIFT                  7  /* DSP_IRQ8_EINT1 */
-#define ARIZONA_DSP_IRQ8_EINT1_WIDTH                  1  /* DSP_IRQ8_EINT1 */
-#define ARIZONA_DSP_IRQ7_EINT1                   0x0040  /* DSP_IRQ7_EINT1 */
-#define ARIZONA_DSP_IRQ7_EINT1_MASK              0x0040  /* DSP_IRQ7_EINT1 */
-#define ARIZONA_DSP_IRQ7_EINT1_SHIFT                  6  /* DSP_IRQ7_EINT1 */
-#define ARIZONA_DSP_IRQ7_EINT1_WIDTH                  1  /* DSP_IRQ7_EINT1 */
-#define ARIZONA_DSP_IRQ6_EINT1                   0x0020  /* DSP_IRQ6_EINT1 */
-#define ARIZONA_DSP_IRQ6_EINT1_MASK              0x0020  /* DSP_IRQ6_EINT1 */
-#define ARIZONA_DSP_IRQ6_EINT1_SHIFT                  5  /* DSP_IRQ6_EINT1 */
-#define ARIZONA_DSP_IRQ6_EINT1_WIDTH                  1  /* DSP_IRQ6_EINT1 */
-#define ARIZONA_DSP_IRQ5_EINT1                   0x0010  /* DSP_IRQ5_EINT1 */
-#define ARIZONA_DSP_IRQ5_EINT1_MASK              0x0010  /* DSP_IRQ5_EINT1 */
-#define ARIZONA_DSP_IRQ5_EINT1_SHIFT                  4  /* DSP_IRQ5_EINT1 */
-#define ARIZONA_DSP_IRQ5_EINT1_WIDTH                  1  /* DSP_IRQ5_EINT1 */
-#define ARIZONA_DSP_IRQ4_EINT1                   0x0008  /* DSP_IRQ4_EINT1 */
-#define ARIZONA_DSP_IRQ4_EINT1_MASK              0x0008  /* DSP_IRQ4_EINT1 */
-#define ARIZONA_DSP_IRQ4_EINT1_SHIFT                  3  /* DSP_IRQ4_EINT1 */
-#define ARIZONA_DSP_IRQ4_EINT1_WIDTH                  1  /* DSP_IRQ4_EINT1 */
-#define ARIZONA_DSP_IRQ3_EINT1                   0x0004  /* DSP_IRQ3_EINT1 */
-#define ARIZONA_DSP_IRQ3_EINT1_MASK              0x0004  /* DSP_IRQ3_EINT1 */
-#define ARIZONA_DSP_IRQ3_EINT1_SHIFT                  2  /* DSP_IRQ3_EINT1 */
-#define ARIZONA_DSP_IRQ3_EINT1_WIDTH                  1  /* DSP_IRQ3_EINT1 */
-#define ARIZONA_DSP_IRQ2_EINT1                   0x0002  /* DSP_IRQ2_EINT1 */
-#define ARIZONA_DSP_IRQ2_EINT1_MASK              0x0002  /* DSP_IRQ2_EINT1 */
-#define ARIZONA_DSP_IRQ2_EINT1_SHIFT                  1  /* DSP_IRQ2_EINT1 */
-#define ARIZONA_DSP_IRQ2_EINT1_WIDTH                  1  /* DSP_IRQ2_EINT1 */
-#define ARIZONA_DSP_IRQ1_EINT1                   0x0001  /* DSP_IRQ1_EINT1 */
-#define ARIZONA_DSP_IRQ1_EINT1_MASK              0x0001  /* DSP_IRQ1_EINT1 */
-#define ARIZONA_DSP_IRQ1_EINT1_SHIFT                  0  /* DSP_IRQ1_EINT1 */
-#define ARIZONA_DSP_IRQ1_EINT1_WIDTH                  1  /* DSP_IRQ1_EINT1 */
-
-/*
- * R3330 (0xD02) - Interrupt Status 3
- */
-#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1          0x8000  /* SPK_SHUTDOWN_WARN_EINT1 */
-#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_MASK     0x8000  /* SPK_SHUTDOWN_WARN_EINT1 */
-#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_SHIFT        15  /* SPK_SHUTDOWN_WARN_EINT1 */
-#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_WIDTH         1  /* SPK_SHUTDOWN_WARN_EINT1 */
-#define ARIZONA_SPK_SHUTDOWN_EINT1               0x4000  /* SPK_SHUTDOWN_EINT1 */
-#define ARIZONA_SPK_SHUTDOWN_EINT1_MASK          0x4000  /* SPK_SHUTDOWN_EINT1 */
-#define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT             14  /* SPK_SHUTDOWN_EINT1 */
-#define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH              1  /* SPK_SHUTDOWN_EINT1 */
-#define ARIZONA_HPDET_EINT1                      0x2000  /* HPDET_EINT1 */
-#define ARIZONA_HPDET_EINT1_MASK                 0x2000  /* HPDET_EINT1 */
-#define ARIZONA_HPDET_EINT1_SHIFT                    13  /* HPDET_EINT1 */
-#define ARIZONA_HPDET_EINT1_WIDTH                     1  /* HPDET_EINT1 */
-#define ARIZONA_MICDET_EINT1                     0x1000  /* MICDET_EINT1 */
-#define ARIZONA_MICDET_EINT1_MASK                0x1000  /* MICDET_EINT1 */
-#define ARIZONA_MICDET_EINT1_SHIFT                   12  /* MICDET_EINT1 */
-#define ARIZONA_MICDET_EINT1_WIDTH                    1  /* MICDET_EINT1 */
-#define ARIZONA_WSEQ_DONE_EINT1                  0x0800  /* WSEQ_DONE_EINT1 */
-#define ARIZONA_WSEQ_DONE_EINT1_MASK             0x0800  /* WSEQ_DONE_EINT1 */
-#define ARIZONA_WSEQ_DONE_EINT1_SHIFT                11  /* WSEQ_DONE_EINT1 */
-#define ARIZONA_WSEQ_DONE_EINT1_WIDTH                 1  /* WSEQ_DONE_EINT1 */
-#define ARIZONA_DRC2_SIG_DET_EINT1               0x0400  /* DRC2_SIG_DET_EINT1 */
-#define ARIZONA_DRC2_SIG_DET_EINT1_MASK          0x0400  /* DRC2_SIG_DET_EINT1 */
-#define ARIZONA_DRC2_SIG_DET_EINT1_SHIFT             10  /* DRC2_SIG_DET_EINT1 */
-#define ARIZONA_DRC2_SIG_DET_EINT1_WIDTH              1  /* DRC2_SIG_DET_EINT1 */
-#define ARIZONA_DRC1_SIG_DET_EINT1               0x0200  /* DRC1_SIG_DET_EINT1 */
-#define ARIZONA_DRC1_SIG_DET_EINT1_MASK          0x0200  /* DRC1_SIG_DET_EINT1 */
-#define ARIZONA_DRC1_SIG_DET_EINT1_SHIFT              9  /* DRC1_SIG_DET_EINT1 */
-#define ARIZONA_DRC1_SIG_DET_EINT1_WIDTH              1  /* DRC1_SIG_DET_EINT1 */
-#define ARIZONA_ASRC2_LOCK_EINT1                 0x0100  /* ASRC2_LOCK_EINT1 */
-#define ARIZONA_ASRC2_LOCK_EINT1_MASK            0x0100  /* ASRC2_LOCK_EINT1 */
-#define ARIZONA_ASRC2_LOCK_EINT1_SHIFT                8  /* ASRC2_LOCK_EINT1 */
-#define ARIZONA_ASRC2_LOCK_EINT1_WIDTH                1  /* ASRC2_LOCK_EINT1 */
-#define ARIZONA_ASRC1_LOCK_EINT1                 0x0080  /* ASRC1_LOCK_EINT1 */
-#define ARIZONA_ASRC1_LOCK_EINT1_MASK            0x0080  /* ASRC1_LOCK_EINT1 */
-#define ARIZONA_ASRC1_LOCK_EINT1_SHIFT                7  /* ASRC1_LOCK_EINT1 */
-#define ARIZONA_ASRC1_LOCK_EINT1_WIDTH                1  /* ASRC1_LOCK_EINT1 */
-#define ARIZONA_UNDERCLOCKED_EINT1               0x0040  /* UNDERCLOCKED_EINT1 */
-#define ARIZONA_UNDERCLOCKED_EINT1_MASK          0x0040  /* UNDERCLOCKED_EINT1 */
-#define ARIZONA_UNDERCLOCKED_EINT1_SHIFT              6  /* UNDERCLOCKED_EINT1 */
-#define ARIZONA_UNDERCLOCKED_EINT1_WIDTH              1  /* UNDERCLOCKED_EINT1 */
-#define ARIZONA_OVERCLOCKED_EINT1                0x0020  /* OVERCLOCKED_EINT1 */
-#define ARIZONA_OVERCLOCKED_EINT1_MASK           0x0020  /* OVERCLOCKED_EINT1 */
-#define ARIZONA_OVERCLOCKED_EINT1_SHIFT               5  /* OVERCLOCKED_EINT1 */
-#define ARIZONA_OVERCLOCKED_EINT1_WIDTH               1  /* OVERCLOCKED_EINT1 */
-#define ARIZONA_FLL2_LOCK_EINT1                  0x0008  /* FLL2_LOCK_EINT1 */
-#define ARIZONA_FLL2_LOCK_EINT1_MASK             0x0008  /* FLL2_LOCK_EINT1 */
-#define ARIZONA_FLL2_LOCK_EINT1_SHIFT                 3  /* FLL2_LOCK_EINT1 */
-#define ARIZONA_FLL2_LOCK_EINT1_WIDTH                 1  /* FLL2_LOCK_EINT1 */
-#define ARIZONA_FLL1_LOCK_EINT1                  0x0004  /* FLL1_LOCK_EINT1 */
-#define ARIZONA_FLL1_LOCK_EINT1_MASK             0x0004  /* FLL1_LOCK_EINT1 */
-#define ARIZONA_FLL1_LOCK_EINT1_SHIFT                 2  /* FLL1_LOCK_EINT1 */
-#define ARIZONA_FLL1_LOCK_EINT1_WIDTH                 1  /* FLL1_LOCK_EINT1 */
-#define ARIZONA_CLKGEN_ERR_EINT1                 0x0002  /* CLKGEN_ERR_EINT1 */
-#define ARIZONA_CLKGEN_ERR_EINT1_MASK            0x0002  /* CLKGEN_ERR_EINT1 */
-#define ARIZONA_CLKGEN_ERR_EINT1_SHIFT                1  /* CLKGEN_ERR_EINT1 */
-#define ARIZONA_CLKGEN_ERR_EINT1_WIDTH                1  /* CLKGEN_ERR_EINT1 */
-#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1           0x0001  /* CLKGEN_ERR_ASYNC_EINT1 */
-#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_MASK      0x0001  /* CLKGEN_ERR_ASYNC_EINT1 */
-#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_SHIFT          0  /* CLKGEN_ERR_ASYNC_EINT1 */
-#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_WIDTH          1  /* CLKGEN_ERR_ASYNC_EINT1 */
-
-/*
- * R3331 (0xD03) - Interrupt Status 4
- */
-#define ARIZONA_ASRC_CFG_ERR_EINT1               0x8000  /* ASRC_CFG_ERR_EINT1 */
-#define ARIZONA_ASRC_CFG_ERR_EINT1_MASK          0x8000  /* ASRC_CFG_ERR_EINT1 */
-#define ARIZONA_ASRC_CFG_ERR_EINT1_SHIFT             15  /* ASRC_CFG_ERR_EINT1 */
-#define ARIZONA_ASRC_CFG_ERR_EINT1_WIDTH              1  /* ASRC_CFG_ERR_EINT1 */
-#define ARIZONA_AIF3_ERR_EINT1                   0x4000  /* AIF3_ERR_EINT1 */
-#define ARIZONA_AIF3_ERR_EINT1_MASK              0x4000  /* AIF3_ERR_EINT1 */
-#define ARIZONA_AIF3_ERR_EINT1_SHIFT                 14  /* AIF3_ERR_EINT1 */
-#define ARIZONA_AIF3_ERR_EINT1_WIDTH                  1  /* AIF3_ERR_EINT1 */
-#define ARIZONA_AIF2_ERR_EINT1                   0x2000  /* AIF2_ERR_EINT1 */
-#define ARIZONA_AIF2_ERR_EINT1_MASK              0x2000  /* AIF2_ERR_EINT1 */
-#define ARIZONA_AIF2_ERR_EINT1_SHIFT                 13  /* AIF2_ERR_EINT1 */
-#define ARIZONA_AIF2_ERR_EINT1_WIDTH                  1  /* AIF2_ERR_EINT1 */
-#define ARIZONA_AIF1_ERR_EINT1                   0x1000  /* AIF1_ERR_EINT1 */
-#define ARIZONA_AIF1_ERR_EINT1_MASK              0x1000  /* AIF1_ERR_EINT1 */
-#define ARIZONA_AIF1_ERR_EINT1_SHIFT                 12  /* AIF1_ERR_EINT1 */
-#define ARIZONA_AIF1_ERR_EINT1_WIDTH                  1  /* AIF1_ERR_EINT1 */
-#define ARIZONA_CTRLIF_ERR_EINT1                 0x0800  /* CTRLIF_ERR_EINT1 */
-#define ARIZONA_CTRLIF_ERR_EINT1_MASK            0x0800  /* CTRLIF_ERR_EINT1 */
-#define ARIZONA_CTRLIF_ERR_EINT1_SHIFT               11  /* CTRLIF_ERR_EINT1 */
-#define ARIZONA_CTRLIF_ERR_EINT1_WIDTH                1  /* CTRLIF_ERR_EINT1 */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1       0x0400  /* MIXER_DROPPED_SAMPLE_EINT1 */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_MASK  0x0400  /* MIXER_DROPPED_SAMPLE_EINT1 */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_SHIFT     10  /* MIXER_DROPPED_SAMPLE_EINT1 */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_WIDTH      1  /* MIXER_DROPPED_SAMPLE_EINT1 */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1          0x0200  /* ASYNC_CLK_ENA_LOW_EINT1 */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_MASK     0x0200  /* ASYNC_CLK_ENA_LOW_EINT1 */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_SHIFT         9  /* ASYNC_CLK_ENA_LOW_EINT1 */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_WIDTH         1  /* ASYNC_CLK_ENA_LOW_EINT1 */
-#define ARIZONA_SYSCLK_ENA_LOW_EINT1             0x0100  /* SYSCLK_ENA_LOW_EINT1 */
-#define ARIZONA_SYSCLK_ENA_LOW_EINT1_MASK        0x0100  /* SYSCLK_ENA_LOW_EINT1 */
-#define ARIZONA_SYSCLK_ENA_LOW_EINT1_SHIFT            8  /* SYSCLK_ENA_LOW_EINT1 */
-#define ARIZONA_SYSCLK_ENA_LOW_EINT1_WIDTH            1  /* SYSCLK_ENA_LOW_EINT1 */
-#define ARIZONA_ISRC1_CFG_ERR_EINT1              0x0080  /* ISRC1_CFG_ERR_EINT1 */
-#define ARIZONA_ISRC1_CFG_ERR_EINT1_MASK         0x0080  /* ISRC1_CFG_ERR_EINT1 */
-#define ARIZONA_ISRC1_CFG_ERR_EINT1_SHIFT             7  /* ISRC1_CFG_ERR_EINT1 */
-#define ARIZONA_ISRC1_CFG_ERR_EINT1_WIDTH             1  /* ISRC1_CFG_ERR_EINT1 */
-#define ARIZONA_ISRC2_CFG_ERR_EINT1              0x0040  /* ISRC2_CFG_ERR_EINT1 */
-#define ARIZONA_ISRC2_CFG_ERR_EINT1_MASK         0x0040  /* ISRC2_CFG_ERR_EINT1 */
-#define ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT             6  /* ISRC2_CFG_ERR_EINT1 */
-#define ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH             1  /* ISRC2_CFG_ERR_EINT1 */
-
-/*
- * R3332 (0xD04) - Interrupt Status 5
- */
-#define ARIZONA_BOOT_DONE_EINT1                  0x0100  /* BOOT_DONE_EINT1 */
-#define ARIZONA_BOOT_DONE_EINT1_MASK             0x0100  /* BOOT_DONE_EINT1 */
-#define ARIZONA_BOOT_DONE_EINT1_SHIFT                 8  /* BOOT_DONE_EINT1 */
-#define ARIZONA_BOOT_DONE_EINT1_WIDTH                 1  /* BOOT_DONE_EINT1 */
-#define ARIZONA_DCS_DAC_DONE_EINT1               0x0080  /* DCS_DAC_DONE_EINT1 */
-#define ARIZONA_DCS_DAC_DONE_EINT1_MASK          0x0080  /* DCS_DAC_DONE_EINT1 */
-#define ARIZONA_DCS_DAC_DONE_EINT1_SHIFT              7  /* DCS_DAC_DONE_EINT1 */
-#define ARIZONA_DCS_DAC_DONE_EINT1_WIDTH              1  /* DCS_DAC_DONE_EINT1 */
-#define ARIZONA_DCS_HP_DONE_EINT1                0x0040  /* DCS_HP_DONE_EINT1 */
-#define ARIZONA_DCS_HP_DONE_EINT1_MASK           0x0040  /* DCS_HP_DONE_EINT1 */
-#define ARIZONA_DCS_HP_DONE_EINT1_SHIFT               6  /* DCS_HP_DONE_EINT1 */
-#define ARIZONA_DCS_HP_DONE_EINT1_WIDTH               1  /* DCS_HP_DONE_EINT1 */
-#define ARIZONA_FLL2_CLOCK_OK_EINT1              0x0002  /* FLL2_CLOCK_OK_EINT1 */
-#define ARIZONA_FLL2_CLOCK_OK_EINT1_MASK         0x0002  /* FLL2_CLOCK_OK_EINT1 */
-#define ARIZONA_FLL2_CLOCK_OK_EINT1_SHIFT             1  /* FLL2_CLOCK_OK_EINT1 */
-#define ARIZONA_FLL2_CLOCK_OK_EINT1_WIDTH             1  /* FLL2_CLOCK_OK_EINT1 */
-#define ARIZONA_FLL1_CLOCK_OK_EINT1              0x0001  /* FLL1_CLOCK_OK_EINT1 */
-#define ARIZONA_FLL1_CLOCK_OK_EINT1_MASK         0x0001  /* FLL1_CLOCK_OK_EINT1 */
-#define ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT             0  /* FLL1_CLOCK_OK_EINT1 */
-#define ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH             1  /* FLL1_CLOCK_OK_EINT1 */
-
-/*
- * R3336 (0xD08) - Interrupt Status 1 Mask
- */
-#define ARIZONA_IM_GP4_EINT1                     0x0008  /* IM_GP4_EINT1 */
-#define ARIZONA_IM_GP4_EINT1_MASK                0x0008  /* IM_GP4_EINT1 */
-#define ARIZONA_IM_GP4_EINT1_SHIFT                    3  /* IM_GP4_EINT1 */
-#define ARIZONA_IM_GP4_EINT1_WIDTH                    1  /* IM_GP4_EINT1 */
-#define ARIZONA_IM_GP3_EINT1                     0x0004  /* IM_GP3_EINT1 */
-#define ARIZONA_IM_GP3_EINT1_MASK                0x0004  /* IM_GP3_EINT1 */
-#define ARIZONA_IM_GP3_EINT1_SHIFT                    2  /* IM_GP3_EINT1 */
-#define ARIZONA_IM_GP3_EINT1_WIDTH                    1  /* IM_GP3_EINT1 */
-#define ARIZONA_IM_GP2_EINT1                     0x0002  /* IM_GP2_EINT1 */
-#define ARIZONA_IM_GP2_EINT1_MASK                0x0002  /* IM_GP2_EINT1 */
-#define ARIZONA_IM_GP2_EINT1_SHIFT                    1  /* IM_GP2_EINT1 */
-#define ARIZONA_IM_GP2_EINT1_WIDTH                    1  /* IM_GP2_EINT1 */
-#define ARIZONA_IM_GP1_EINT1                     0x0001  /* IM_GP1_EINT1 */
-#define ARIZONA_IM_GP1_EINT1_MASK                0x0001  /* IM_GP1_EINT1 */
-#define ARIZONA_IM_GP1_EINT1_SHIFT                    0  /* IM_GP1_EINT1 */
-#define ARIZONA_IM_GP1_EINT1_WIDTH                    1  /* IM_GP1_EINT1 */
-
-/*
- * R3337 (0xD09) - Interrupt Status 2 Mask
- */
-#define ARIZONA_IM_DSP1_RAM_RDY_EINT1            0x0100  /* IM_DSP1_RAM_RDY_EINT1 */
-#define ARIZONA_IM_DSP1_RAM_RDY_EINT1_MASK       0x0100  /* IM_DSP1_RAM_RDY_EINT1 */
-#define ARIZONA_IM_DSP1_RAM_RDY_EINT1_SHIFT           8  /* IM_DSP1_RAM_RDY_EINT1 */
-#define ARIZONA_IM_DSP1_RAM_RDY_EINT1_WIDTH           1  /* IM_DSP1_RAM_RDY_EINT1 */
-#define ARIZONA_IM_DSP_IRQ2_EINT1                0x0002  /* IM_DSP_IRQ2_EINT1 */
-#define ARIZONA_IM_DSP_IRQ2_EINT1_MASK           0x0002  /* IM_DSP_IRQ2_EINT1 */
-#define ARIZONA_IM_DSP_IRQ2_EINT1_SHIFT               1  /* IM_DSP_IRQ2_EINT1 */
-#define ARIZONA_IM_DSP_IRQ2_EINT1_WIDTH               1  /* IM_DSP_IRQ2_EINT1 */
-#define ARIZONA_IM_DSP_IRQ1_EINT1                0x0001  /* IM_DSP_IRQ1_EINT1 */
-#define ARIZONA_IM_DSP_IRQ1_EINT1_MASK           0x0001  /* IM_DSP_IRQ1_EINT1 */
-#define ARIZONA_IM_DSP_IRQ1_EINT1_SHIFT               0  /* IM_DSP_IRQ1_EINT1 */
-#define ARIZONA_IM_DSP_IRQ1_EINT1_WIDTH               1  /* IM_DSP_IRQ1_EINT1 */
-
-/*
- * R3338 (0xD0A) - Interrupt Status 3 Mask
- */
-#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1       0x8000  /* IM_SPK_SHUTDOWN_WARN_EINT1 */
-#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_MASK  0x8000  /* IM_SPK_SHUTDOWN_WARN_EINT1 */
-#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_SHIFT     15  /* IM_SPK_SHUTDOWN_WARN_EINT1 */
-#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_WIDTH      1  /* IM_SPK_SHUTDOWN_WARN_EINT1 */
-#define ARIZONA_IM_SPK_SHUTDOWN_EINT1            0x4000  /* IM_SPK_SHUTDOWN_EINT1 */
-#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK       0x4000  /* IM_SPK_SHUTDOWN_EINT1 */
-#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT          14  /* IM_SPK_SHUTDOWN_EINT1 */
-#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH           1  /* IM_SPK_SHUTDOWN_EINT1 */
-#define ARIZONA_IM_HPDET_EINT1                   0x2000  /* IM_HPDET_EINT1 */
-#define ARIZONA_IM_HPDET_EINT1_MASK              0x2000  /* IM_HPDET_EINT1 */
-#define ARIZONA_IM_HPDET_EINT1_SHIFT                 13  /* IM_HPDET_EINT1 */
-#define ARIZONA_IM_HPDET_EINT1_WIDTH                  1  /* IM_HPDET_EINT1 */
-#define ARIZONA_IM_MICDET_EINT1                  0x1000  /* IM_MICDET_EINT1 */
-#define ARIZONA_IM_MICDET_EINT1_MASK             0x1000  /* IM_MICDET_EINT1 */
-#define ARIZONA_IM_MICDET_EINT1_SHIFT                12  /* IM_MICDET_EINT1 */
-#define ARIZONA_IM_MICDET_EINT1_WIDTH                 1  /* IM_MICDET_EINT1 */
-#define ARIZONA_IM_WSEQ_DONE_EINT1               0x0800  /* IM_WSEQ_DONE_EINT1 */
-#define ARIZONA_IM_WSEQ_DONE_EINT1_MASK          0x0800  /* IM_WSEQ_DONE_EINT1 */
-#define ARIZONA_IM_WSEQ_DONE_EINT1_SHIFT             11  /* IM_WSEQ_DONE_EINT1 */
-#define ARIZONA_IM_WSEQ_DONE_EINT1_WIDTH              1  /* IM_WSEQ_DONE_EINT1 */
-#define ARIZONA_IM_DRC2_SIG_DET_EINT1            0x0400  /* IM_DRC2_SIG_DET_EINT1 */
-#define ARIZONA_IM_DRC2_SIG_DET_EINT1_MASK       0x0400  /* IM_DRC2_SIG_DET_EINT1 */
-#define ARIZONA_IM_DRC2_SIG_DET_EINT1_SHIFT          10  /* IM_DRC2_SIG_DET_EINT1 */
-#define ARIZONA_IM_DRC2_SIG_DET_EINT1_WIDTH           1  /* IM_DRC2_SIG_DET_EINT1 */
-#define ARIZONA_IM_DRC1_SIG_DET_EINT1            0x0200  /* IM_DRC1_SIG_DET_EINT1 */
-#define ARIZONA_IM_DRC1_SIG_DET_EINT1_MASK       0x0200  /* IM_DRC1_SIG_DET_EINT1 */
-#define ARIZONA_IM_DRC1_SIG_DET_EINT1_SHIFT           9  /* IM_DRC1_SIG_DET_EINT1 */
-#define ARIZONA_IM_DRC1_SIG_DET_EINT1_WIDTH           1  /* IM_DRC1_SIG_DET_EINT1 */
-#define ARIZONA_IM_ASRC2_LOCK_EINT1              0x0100  /* IM_ASRC2_LOCK_EINT1 */
-#define ARIZONA_IM_ASRC2_LOCK_EINT1_MASK         0x0100  /* IM_ASRC2_LOCK_EINT1 */
-#define ARIZONA_IM_ASRC2_LOCK_EINT1_SHIFT             8  /* IM_ASRC2_LOCK_EINT1 */
-#define ARIZONA_IM_ASRC2_LOCK_EINT1_WIDTH             1  /* IM_ASRC2_LOCK_EINT1 */
-#define ARIZONA_IM_ASRC1_LOCK_EINT1              0x0080  /* IM_ASRC1_LOCK_EINT1 */
-#define ARIZONA_IM_ASRC1_LOCK_EINT1_MASK         0x0080  /* IM_ASRC1_LOCK_EINT1 */
-#define ARIZONA_IM_ASRC1_LOCK_EINT1_SHIFT             7  /* IM_ASRC1_LOCK_EINT1 */
-#define ARIZONA_IM_ASRC1_LOCK_EINT1_WIDTH             1  /* IM_ASRC1_LOCK_EINT1 */
-#define ARIZONA_IM_UNDERCLOCKED_EINT1            0x0040  /* IM_UNDERCLOCKED_EINT1 */
-#define ARIZONA_IM_UNDERCLOCKED_EINT1_MASK       0x0040  /* IM_UNDERCLOCKED_EINT1 */
-#define ARIZONA_IM_UNDERCLOCKED_EINT1_SHIFT           6  /* IM_UNDERCLOCKED_EINT1 */
-#define ARIZONA_IM_UNDERCLOCKED_EINT1_WIDTH           1  /* IM_UNDERCLOCKED_EINT1 */
-#define ARIZONA_IM_OVERCLOCKED_EINT1             0x0020  /* IM_OVERCLOCKED_EINT1 */
-#define ARIZONA_IM_OVERCLOCKED_EINT1_MASK        0x0020  /* IM_OVERCLOCKED_EINT1 */
-#define ARIZONA_IM_OVERCLOCKED_EINT1_SHIFT            5  /* IM_OVERCLOCKED_EINT1 */
-#define ARIZONA_IM_OVERCLOCKED_EINT1_WIDTH            1  /* IM_OVERCLOCKED_EINT1 */
-#define ARIZONA_IM_FLL2_LOCK_EINT1               0x0008  /* IM_FLL2_LOCK_EINT1 */
-#define ARIZONA_IM_FLL2_LOCK_EINT1_MASK          0x0008  /* IM_FLL2_LOCK_EINT1 */
-#define ARIZONA_IM_FLL2_LOCK_EINT1_SHIFT              3  /* IM_FLL2_LOCK_EINT1 */
-#define ARIZONA_IM_FLL2_LOCK_EINT1_WIDTH              1  /* IM_FLL2_LOCK_EINT1 */
-#define ARIZONA_IM_FLL1_LOCK_EINT1               0x0004  /* IM_FLL1_LOCK_EINT1 */
-#define ARIZONA_IM_FLL1_LOCK_EINT1_MASK          0x0004  /* IM_FLL1_LOCK_EINT1 */
-#define ARIZONA_IM_FLL1_LOCK_EINT1_SHIFT              2  /* IM_FLL1_LOCK_EINT1 */
-#define ARIZONA_IM_FLL1_LOCK_EINT1_WIDTH              1  /* IM_FLL1_LOCK_EINT1 */
-#define ARIZONA_IM_CLKGEN_ERR_EINT1              0x0002  /* IM_CLKGEN_ERR_EINT1 */
-#define ARIZONA_IM_CLKGEN_ERR_EINT1_MASK         0x0002  /* IM_CLKGEN_ERR_EINT1 */
-#define ARIZONA_IM_CLKGEN_ERR_EINT1_SHIFT             1  /* IM_CLKGEN_ERR_EINT1 */
-#define ARIZONA_IM_CLKGEN_ERR_EINT1_WIDTH             1  /* IM_CLKGEN_ERR_EINT1 */
-#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1        0x0001  /* IM_CLKGEN_ERR_ASYNC_EINT1 */
-#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_MASK   0x0001  /* IM_CLKGEN_ERR_ASYNC_EINT1 */
-#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_SHIFT       0  /* IM_CLKGEN_ERR_ASYNC_EINT1 */
-#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_WIDTH       1  /* IM_CLKGEN_ERR_ASYNC_EINT1 */
-
-/*
- * R3339 (0xD0B) - Interrupt Status 4 Mask
- */
-#define ARIZONA_IM_ASRC_CFG_ERR_EINT1            0x8000  /* IM_ASRC_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK       0x8000  /* IM_ASRC_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT          15  /* IM_ASRC_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH           1  /* IM_ASRC_CFG_ERR_EINT1 */
-#define ARIZONA_IM_AIF3_ERR_EINT1                0x4000  /* IM_AIF3_ERR_EINT1 */
-#define ARIZONA_IM_AIF3_ERR_EINT1_MASK           0x4000  /* IM_AIF3_ERR_EINT1 */
-#define ARIZONA_IM_AIF3_ERR_EINT1_SHIFT              14  /* IM_AIF3_ERR_EINT1 */
-#define ARIZONA_IM_AIF3_ERR_EINT1_WIDTH               1  /* IM_AIF3_ERR_EINT1 */
-#define ARIZONA_IM_AIF2_ERR_EINT1                0x2000  /* IM_AIF2_ERR_EINT1 */
-#define ARIZONA_IM_AIF2_ERR_EINT1_MASK           0x2000  /* IM_AIF2_ERR_EINT1 */
-#define ARIZONA_IM_AIF2_ERR_EINT1_SHIFT              13  /* IM_AIF2_ERR_EINT1 */
-#define ARIZONA_IM_AIF2_ERR_EINT1_WIDTH               1  /* IM_AIF2_ERR_EINT1 */
-#define ARIZONA_IM_AIF1_ERR_EINT1                0x1000  /* IM_AIF1_ERR_EINT1 */
-#define ARIZONA_IM_AIF1_ERR_EINT1_MASK           0x1000  /* IM_AIF1_ERR_EINT1 */
-#define ARIZONA_IM_AIF1_ERR_EINT1_SHIFT              12  /* IM_AIF1_ERR_EINT1 */
-#define ARIZONA_IM_AIF1_ERR_EINT1_WIDTH               1  /* IM_AIF1_ERR_EINT1 */
-#define ARIZONA_IM_CTRLIF_ERR_EINT1              0x0800  /* IM_CTRLIF_ERR_EINT1 */
-#define ARIZONA_IM_CTRLIF_ERR_EINT1_MASK         0x0800  /* IM_CTRLIF_ERR_EINT1 */
-#define ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT            11  /* IM_CTRLIF_ERR_EINT1 */
-#define ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH             1  /* IM_CTRLIF_ERR_EINT1 */
-#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1    0x0400  /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
-#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400  /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
-#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT     10  /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
-#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH      1  /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
-#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1       0x0200  /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
-#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK  0x0200  /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
-#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT      9  /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
-#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH      1  /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
-#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1          0x0100  /* IM_SYSCLK_ENA_LOW_EINT1 */
-#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK     0x0100  /* IM_SYSCLK_ENA_LOW_EINT1 */
-#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT         8  /* IM_SYSCLK_ENA_LOW_EINT1 */
-#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH         1  /* IM_SYSCLK_ENA_LOW_EINT1 */
-#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1           0x0080  /* IM_ISRC1_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK      0x0080  /* IM_ISRC1_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT          7  /* IM_ISRC1_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH          1  /* IM_ISRC1_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1           0x0040  /* IM_ISRC2_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK      0x0040  /* IM_ISRC2_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT          6  /* IM_ISRC2_CFG_ERR_EINT1 */
-#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH          1  /* IM_ISRC2_CFG_ERR_EINT1 */
-
-/*
- * R3340 (0xD0C) - Interrupt Status 5 Mask
- */
-#define ARIZONA_IM_BOOT_DONE_EINT1               0x0100  /* IM_BOOT_DONE_EINT1 */
-#define ARIZONA_IM_BOOT_DONE_EINT1_MASK          0x0100  /* IM_BOOT_DONE_EINT1 */
-#define ARIZONA_IM_BOOT_DONE_EINT1_SHIFT              8  /* IM_BOOT_DONE_EINT1 */
-#define ARIZONA_IM_BOOT_DONE_EINT1_WIDTH              1  /* IM_BOOT_DONE_EINT1 */
-#define ARIZONA_IM_DCS_DAC_DONE_EINT1            0x0080  /* IM_DCS_DAC_DONE_EINT1 */
-#define ARIZONA_IM_DCS_DAC_DONE_EINT1_MASK       0x0080  /* IM_DCS_DAC_DONE_EINT1 */
-#define ARIZONA_IM_DCS_DAC_DONE_EINT1_SHIFT           7  /* IM_DCS_DAC_DONE_EINT1 */
-#define ARIZONA_IM_DCS_DAC_DONE_EINT1_WIDTH           1  /* IM_DCS_DAC_DONE_EINT1 */
-#define ARIZONA_IM_DCS_HP_DONE_EINT1             0x0040  /* IM_DCS_HP_DONE_EINT1 */
-#define ARIZONA_IM_DCS_HP_DONE_EINT1_MASK        0x0040  /* IM_DCS_HP_DONE_EINT1 */
-#define ARIZONA_IM_DCS_HP_DONE_EINT1_SHIFT            6  /* IM_DCS_HP_DONE_EINT1 */
-#define ARIZONA_IM_DCS_HP_DONE_EINT1_WIDTH            1  /* IM_DCS_HP_DONE_EINT1 */
-#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1           0x0002  /* IM_FLL2_CLOCK_OK_EINT1 */
-#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_MASK      0x0002  /* IM_FLL2_CLOCK_OK_EINT1 */
-#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_SHIFT          1  /* IM_FLL2_CLOCK_OK_EINT1 */
-#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_WIDTH          1  /* IM_FLL2_CLOCK_OK_EINT1 */
-#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1           0x0001  /* IM_FLL1_CLOCK_OK_EINT1 */
-#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_MASK      0x0001  /* IM_FLL1_CLOCK_OK_EINT1 */
-#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT          0  /* IM_FLL1_CLOCK_OK_EINT1 */
-#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH          1  /* IM_FLL1_CLOCK_OK_EINT1 */
-
-/*
- * R3343 (0xD0F) - Interrupt Control
- */
-#define ARIZONA_IM_IRQ1                          0x0001  /* IM_IRQ1 */
-#define ARIZONA_IM_IRQ1_MASK                     0x0001  /* IM_IRQ1 */
-#define ARIZONA_IM_IRQ1_SHIFT                         0  /* IM_IRQ1 */
-#define ARIZONA_IM_IRQ1_WIDTH                         1  /* IM_IRQ1 */
-
-/*
- * R3344 (0xD10) - IRQ2 Status 1
- */
-#define ARIZONA_GP4_EINT2                        0x0008  /* GP4_EINT2 */
-#define ARIZONA_GP4_EINT2_MASK                   0x0008  /* GP4_EINT2 */
-#define ARIZONA_GP4_EINT2_SHIFT                       3  /* GP4_EINT2 */
-#define ARIZONA_GP4_EINT2_WIDTH                       1  /* GP4_EINT2 */
-#define ARIZONA_GP3_EINT2                        0x0004  /* GP3_EINT2 */
-#define ARIZONA_GP3_EINT2_MASK                   0x0004  /* GP3_EINT2 */
-#define ARIZONA_GP3_EINT2_SHIFT                       2  /* GP3_EINT2 */
-#define ARIZONA_GP3_EINT2_WIDTH                       1  /* GP3_EINT2 */
-#define ARIZONA_GP2_EINT2                        0x0002  /* GP2_EINT2 */
-#define ARIZONA_GP2_EINT2_MASK                   0x0002  /* GP2_EINT2 */
-#define ARIZONA_GP2_EINT2_SHIFT                       1  /* GP2_EINT2 */
-#define ARIZONA_GP2_EINT2_WIDTH                       1  /* GP2_EINT2 */
-#define ARIZONA_GP1_EINT2                        0x0001  /* GP1_EINT2 */
-#define ARIZONA_GP1_EINT2_MASK                   0x0001  /* GP1_EINT2 */
-#define ARIZONA_GP1_EINT2_SHIFT                       0  /* GP1_EINT2 */
-#define ARIZONA_GP1_EINT2_WIDTH                       1  /* GP1_EINT2 */
-
-/*
- * R3345 (0xD11) - IRQ2 Status 2
- */
-#define ARIZONA_DSP1_RAM_RDY_EINT2               0x0100  /* DSP1_RAM_RDY_EINT2 */
-#define ARIZONA_DSP1_RAM_RDY_EINT2_MASK          0x0100  /* DSP1_RAM_RDY_EINT2 */
-#define ARIZONA_DSP1_RAM_RDY_EINT2_SHIFT              8  /* DSP1_RAM_RDY_EINT2 */
-#define ARIZONA_DSP1_RAM_RDY_EINT2_WIDTH              1  /* DSP1_RAM_RDY_EINT2 */
-#define ARIZONA_DSP_IRQ2_EINT2                   0x0002  /* DSP_IRQ2_EINT2 */
-#define ARIZONA_DSP_IRQ2_EINT2_MASK              0x0002  /* DSP_IRQ2_EINT2 */
-#define ARIZONA_DSP_IRQ2_EINT2_SHIFT                  1  /* DSP_IRQ2_EINT2 */
-#define ARIZONA_DSP_IRQ2_EINT2_WIDTH                  1  /* DSP_IRQ2_EINT2 */
-#define ARIZONA_DSP_IRQ1_EINT2                   0x0001  /* DSP_IRQ1_EINT2 */
-#define ARIZONA_DSP_IRQ1_EINT2_MASK              0x0001  /* DSP_IRQ1_EINT2 */
-#define ARIZONA_DSP_IRQ1_EINT2_SHIFT                  0  /* DSP_IRQ1_EINT2 */
-#define ARIZONA_DSP_IRQ1_EINT2_WIDTH                  1  /* DSP_IRQ1_EINT2 */
-
-/*
- * R3346 (0xD12) - IRQ2 Status 3
- */
-#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2          0x8000  /* SPK_SHUTDOWN_WARN_EINT2 */
-#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_MASK     0x8000  /* SPK_SHUTDOWN_WARN_EINT2 */
-#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_SHIFT        15  /* SPK_SHUTDOWN_WARN_EINT2 */
-#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_WIDTH         1  /* SPK_SHUTDOWN_WARN_EINT2 */
-#define ARIZONA_SPK_SHUTDOWN_EINT2               0x4000  /* SPK_SHUTDOWN_EINT2 */
-#define ARIZONA_SPK_SHUTDOWN_EINT2_MASK          0x4000  /* SPK_SHUTDOWN_EINT2 */
-#define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT             14  /* SPK_SHUTDOWN_EINT2 */
-#define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH              1  /* SPK_SHUTDOWN_EINT2 */
-#define ARIZONA_HPDET_EINT2                      0x2000  /* HPDET_EINT2 */
-#define ARIZONA_HPDET_EINT2_MASK                 0x2000  /* HPDET_EINT2 */
-#define ARIZONA_HPDET_EINT2_SHIFT                    13  /* HPDET_EINT2 */
-#define ARIZONA_HPDET_EINT2_WIDTH                     1  /* HPDET_EINT2 */
-#define ARIZONA_MICDET_EINT2                     0x1000  /* MICDET_EINT2 */
-#define ARIZONA_MICDET_EINT2_MASK                0x1000  /* MICDET_EINT2 */
-#define ARIZONA_MICDET_EINT2_SHIFT                   12  /* MICDET_EINT2 */
-#define ARIZONA_MICDET_EINT2_WIDTH                    1  /* MICDET_EINT2 */
-#define ARIZONA_WSEQ_DONE_EINT2                  0x0800  /* WSEQ_DONE_EINT2 */
-#define ARIZONA_WSEQ_DONE_EINT2_MASK             0x0800  /* WSEQ_DONE_EINT2 */
-#define ARIZONA_WSEQ_DONE_EINT2_SHIFT                11  /* WSEQ_DONE_EINT2 */
-#define ARIZONA_WSEQ_DONE_EINT2_WIDTH                 1  /* WSEQ_DONE_EINT2 */
-#define ARIZONA_DRC2_SIG_DET_EINT2               0x0400  /* DRC2_SIG_DET_EINT2 */
-#define ARIZONA_DRC2_SIG_DET_EINT2_MASK          0x0400  /* DRC2_SIG_DET_EINT2 */
-#define ARIZONA_DRC2_SIG_DET_EINT2_SHIFT             10  /* DRC2_SIG_DET_EINT2 */
-#define ARIZONA_DRC2_SIG_DET_EINT2_WIDTH              1  /* DRC2_SIG_DET_EINT2 */
-#define ARIZONA_DRC1_SIG_DET_EINT2               0x0200  /* DRC1_SIG_DET_EINT2 */
-#define ARIZONA_DRC1_SIG_DET_EINT2_MASK          0x0200  /* DRC1_SIG_DET_EINT2 */
-#define ARIZONA_DRC1_SIG_DET_EINT2_SHIFT              9  /* DRC1_SIG_DET_EINT2 */
-#define ARIZONA_DRC1_SIG_DET_EINT2_WIDTH              1  /* DRC1_SIG_DET_EINT2 */
-#define ARIZONA_ASRC2_LOCK_EINT2                 0x0100  /* ASRC2_LOCK_EINT2 */
-#define ARIZONA_ASRC2_LOCK_EINT2_MASK            0x0100  /* ASRC2_LOCK_EINT2 */
-#define ARIZONA_ASRC2_LOCK_EINT2_SHIFT                8  /* ASRC2_LOCK_EINT2 */
-#define ARIZONA_ASRC2_LOCK_EINT2_WIDTH                1  /* ASRC2_LOCK_EINT2 */
-#define ARIZONA_ASRC1_LOCK_EINT2                 0x0080  /* ASRC1_LOCK_EINT2 */
-#define ARIZONA_ASRC1_LOCK_EINT2_MASK            0x0080  /* ASRC1_LOCK_EINT2 */
-#define ARIZONA_ASRC1_LOCK_EINT2_SHIFT                7  /* ASRC1_LOCK_EINT2 */
-#define ARIZONA_ASRC1_LOCK_EINT2_WIDTH                1  /* ASRC1_LOCK_EINT2 */
-#define ARIZONA_UNDERCLOCKED_EINT2               0x0040  /* UNDERCLOCKED_EINT2 */
-#define ARIZONA_UNDERCLOCKED_EINT2_MASK          0x0040  /* UNDERCLOCKED_EINT2 */
-#define ARIZONA_UNDERCLOCKED_EINT2_SHIFT              6  /* UNDERCLOCKED_EINT2 */
-#define ARIZONA_UNDERCLOCKED_EINT2_WIDTH              1  /* UNDERCLOCKED_EINT2 */
-#define ARIZONA_OVERCLOCKED_EINT2                0x0020  /* OVERCLOCKED_EINT2 */
-#define ARIZONA_OVERCLOCKED_EINT2_MASK           0x0020  /* OVERCLOCKED_EINT2 */
-#define ARIZONA_OVERCLOCKED_EINT2_SHIFT               5  /* OVERCLOCKED_EINT2 */
-#define ARIZONA_OVERCLOCKED_EINT2_WIDTH               1  /* OVERCLOCKED_EINT2 */
-#define ARIZONA_FLL2_LOCK_EINT2                  0x0008  /* FLL2_LOCK_EINT2 */
-#define ARIZONA_FLL2_LOCK_EINT2_MASK             0x0008  /* FLL2_LOCK_EINT2 */
-#define ARIZONA_FLL2_LOCK_EINT2_SHIFT                 3  /* FLL2_LOCK_EINT2 */
-#define ARIZONA_FLL2_LOCK_EINT2_WIDTH                 1  /* FLL2_LOCK_EINT2 */
-#define ARIZONA_FLL1_LOCK_EINT2                  0x0004  /* FLL1_LOCK_EINT2 */
-#define ARIZONA_FLL1_LOCK_EINT2_MASK             0x0004  /* FLL1_LOCK_EINT2 */
-#define ARIZONA_FLL1_LOCK_EINT2_SHIFT                 2  /* FLL1_LOCK_EINT2 */
-#define ARIZONA_FLL1_LOCK_EINT2_WIDTH                 1  /* FLL1_LOCK_EINT2 */
-#define ARIZONA_CLKGEN_ERR_EINT2                 0x0002  /* CLKGEN_ERR_EINT2 */
-#define ARIZONA_CLKGEN_ERR_EINT2_MASK            0x0002  /* CLKGEN_ERR_EINT2 */
-#define ARIZONA_CLKGEN_ERR_EINT2_SHIFT                1  /* CLKGEN_ERR_EINT2 */
-#define ARIZONA_CLKGEN_ERR_EINT2_WIDTH                1  /* CLKGEN_ERR_EINT2 */
-#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2           0x0001  /* CLKGEN_ERR_ASYNC_EINT2 */
-#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_MASK      0x0001  /* CLKGEN_ERR_ASYNC_EINT2 */
-#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_SHIFT          0  /* CLKGEN_ERR_ASYNC_EINT2 */
-#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_WIDTH          1  /* CLKGEN_ERR_ASYNC_EINT2 */
-
-/*
- * R3347 (0xD13) - IRQ2 Status 4
- */
-#define ARIZONA_ASRC_CFG_ERR_EINT2               0x8000  /* ASRC_CFG_ERR_EINT2 */
-#define ARIZONA_ASRC_CFG_ERR_EINT2_MASK          0x8000  /* ASRC_CFG_ERR_EINT2 */
-#define ARIZONA_ASRC_CFG_ERR_EINT2_SHIFT             15  /* ASRC_CFG_ERR_EINT2 */
-#define ARIZONA_ASRC_CFG_ERR_EINT2_WIDTH              1  /* ASRC_CFG_ERR_EINT2 */
-#define ARIZONA_AIF3_ERR_EINT2                   0x4000  /* AIF3_ERR_EINT2 */
-#define ARIZONA_AIF3_ERR_EINT2_MASK              0x4000  /* AIF3_ERR_EINT2 */
-#define ARIZONA_AIF3_ERR_EINT2_SHIFT                 14  /* AIF3_ERR_EINT2 */
-#define ARIZONA_AIF3_ERR_EINT2_WIDTH                  1  /* AIF3_ERR_EINT2 */
-#define ARIZONA_AIF2_ERR_EINT2                   0x2000  /* AIF2_ERR_EINT2 */
-#define ARIZONA_AIF2_ERR_EINT2_MASK              0x2000  /* AIF2_ERR_EINT2 */
-#define ARIZONA_AIF2_ERR_EINT2_SHIFT                 13  /* AIF2_ERR_EINT2 */
-#define ARIZONA_AIF2_ERR_EINT2_WIDTH                  1  /* AIF2_ERR_EINT2 */
-#define ARIZONA_AIF1_ERR_EINT2                   0x1000  /* AIF1_ERR_EINT2 */
-#define ARIZONA_AIF1_ERR_EINT2_MASK              0x1000  /* AIF1_ERR_EINT2 */
-#define ARIZONA_AIF1_ERR_EINT2_SHIFT                 12  /* AIF1_ERR_EINT2 */
-#define ARIZONA_AIF1_ERR_EINT2_WIDTH                  1  /* AIF1_ERR_EINT2 */
-#define ARIZONA_CTRLIF_ERR_EINT2                 0x0800  /* CTRLIF_ERR_EINT2 */
-#define ARIZONA_CTRLIF_ERR_EINT2_MASK            0x0800  /* CTRLIF_ERR_EINT2 */
-#define ARIZONA_CTRLIF_ERR_EINT2_SHIFT               11  /* CTRLIF_ERR_EINT2 */
-#define ARIZONA_CTRLIF_ERR_EINT2_WIDTH                1  /* CTRLIF_ERR_EINT2 */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2       0x0400  /* MIXER_DROPPED_SAMPLE_EINT2 */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_MASK  0x0400  /* MIXER_DROPPED_SAMPLE_EINT2 */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_SHIFT     10  /* MIXER_DROPPED_SAMPLE_EINT2 */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_WIDTH      1  /* MIXER_DROPPED_SAMPLE_EINT2 */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2          0x0200  /* ASYNC_CLK_ENA_LOW_EINT2 */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_MASK     0x0200  /* ASYNC_CLK_ENA_LOW_EINT2 */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_SHIFT         9  /* ASYNC_CLK_ENA_LOW_EINT2 */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_WIDTH         1  /* ASYNC_CLK_ENA_LOW_EINT2 */
-#define ARIZONA_SYSCLK_ENA_LOW_EINT2             0x0100  /* SYSCLK_ENA_LOW_EINT2 */
-#define ARIZONA_SYSCLK_ENA_LOW_EINT2_MASK        0x0100  /* SYSCLK_ENA_LOW_EINT2 */
-#define ARIZONA_SYSCLK_ENA_LOW_EINT2_SHIFT            8  /* SYSCLK_ENA_LOW_EINT2 */
-#define ARIZONA_SYSCLK_ENA_LOW_EINT2_WIDTH            1  /* SYSCLK_ENA_LOW_EINT2 */
-#define ARIZONA_ISRC1_CFG_ERR_EINT2              0x0080  /* ISRC1_CFG_ERR_EINT2 */
-#define ARIZONA_ISRC1_CFG_ERR_EINT2_MASK         0x0080  /* ISRC1_CFG_ERR_EINT2 */
-#define ARIZONA_ISRC1_CFG_ERR_EINT2_SHIFT             7  /* ISRC1_CFG_ERR_EINT2 */
-#define ARIZONA_ISRC1_CFG_ERR_EINT2_WIDTH             1  /* ISRC1_CFG_ERR_EINT2 */
-#define ARIZONA_ISRC2_CFG_ERR_EINT2              0x0040  /* ISRC2_CFG_ERR_EINT2 */
-#define ARIZONA_ISRC2_CFG_ERR_EINT2_MASK         0x0040  /* ISRC2_CFG_ERR_EINT2 */
-#define ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT             6  /* ISRC2_CFG_ERR_EINT2 */
-#define ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH             1  /* ISRC2_CFG_ERR_EINT2 */
-
-/*
- * R3348 (0xD14) - IRQ2 Status 5
- */
-#define ARIZONA_BOOT_DONE_EINT2                  0x0100  /* BOOT_DONE_EINT2 */
-#define ARIZONA_BOOT_DONE_EINT2_MASK             0x0100  /* BOOT_DONE_EINT2 */
-#define ARIZONA_BOOT_DONE_EINT2_SHIFT                 8  /* BOOT_DONE_EINT2 */
-#define ARIZONA_BOOT_DONE_EINT2_WIDTH                 1  /* BOOT_DONE_EINT2 */
-#define ARIZONA_DCS_DAC_DONE_EINT2               0x0080  /* DCS_DAC_DONE_EINT2 */
-#define ARIZONA_DCS_DAC_DONE_EINT2_MASK          0x0080  /* DCS_DAC_DONE_EINT2 */
-#define ARIZONA_DCS_DAC_DONE_EINT2_SHIFT              7  /* DCS_DAC_DONE_EINT2 */
-#define ARIZONA_DCS_DAC_DONE_EINT2_WIDTH              1  /* DCS_DAC_DONE_EINT2 */
-#define ARIZONA_DCS_HP_DONE_EINT2                0x0040  /* DCS_HP_DONE_EINT2 */
-#define ARIZONA_DCS_HP_DONE_EINT2_MASK           0x0040  /* DCS_HP_DONE_EINT2 */
-#define ARIZONA_DCS_HP_DONE_EINT2_SHIFT               6  /* DCS_HP_DONE_EINT2 */
-#define ARIZONA_DCS_HP_DONE_EINT2_WIDTH               1  /* DCS_HP_DONE_EINT2 */
-#define ARIZONA_FLL2_CLOCK_OK_EINT2              0x0002  /* FLL2_CLOCK_OK_EINT2 */
-#define ARIZONA_FLL2_CLOCK_OK_EINT2_MASK         0x0002  /* FLL2_CLOCK_OK_EINT2 */
-#define ARIZONA_FLL2_CLOCK_OK_EINT2_SHIFT             1  /* FLL2_CLOCK_OK_EINT2 */
-#define ARIZONA_FLL2_CLOCK_OK_EINT2_WIDTH             1  /* FLL2_CLOCK_OK_EINT2 */
-#define ARIZONA_FLL1_CLOCK_OK_EINT2              0x0001  /* FLL1_CLOCK_OK_EINT2 */
-#define ARIZONA_FLL1_CLOCK_OK_EINT2_MASK         0x0001  /* FLL1_CLOCK_OK_EINT2 */
-#define ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT             0  /* FLL1_CLOCK_OK_EINT2 */
-#define ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH             1  /* FLL1_CLOCK_OK_EINT2 */
-
-/*
- * R3352 (0xD18) - IRQ2 Status 1 Mask
- */
-#define ARIZONA_IM_GP4_EINT2                     0x0008  /* IM_GP4_EINT2 */
-#define ARIZONA_IM_GP4_EINT2_MASK                0x0008  /* IM_GP4_EINT2 */
-#define ARIZONA_IM_GP4_EINT2_SHIFT                    3  /* IM_GP4_EINT2 */
-#define ARIZONA_IM_GP4_EINT2_WIDTH                    1  /* IM_GP4_EINT2 */
-#define ARIZONA_IM_GP3_EINT2                     0x0004  /* IM_GP3_EINT2 */
-#define ARIZONA_IM_GP3_EINT2_MASK                0x0004  /* IM_GP3_EINT2 */
-#define ARIZONA_IM_GP3_EINT2_SHIFT                    2  /* IM_GP3_EINT2 */
-#define ARIZONA_IM_GP3_EINT2_WIDTH                    1  /* IM_GP3_EINT2 */
-#define ARIZONA_IM_GP2_EINT2                     0x0002  /* IM_GP2_EINT2 */
-#define ARIZONA_IM_GP2_EINT2_MASK                0x0002  /* IM_GP2_EINT2 */
-#define ARIZONA_IM_GP2_EINT2_SHIFT                    1  /* IM_GP2_EINT2 */
-#define ARIZONA_IM_GP2_EINT2_WIDTH                    1  /* IM_GP2_EINT2 */
-#define ARIZONA_IM_GP1_EINT2                     0x0001  /* IM_GP1_EINT2 */
-#define ARIZONA_IM_GP1_EINT2_MASK                0x0001  /* IM_GP1_EINT2 */
-#define ARIZONA_IM_GP1_EINT2_SHIFT                    0  /* IM_GP1_EINT2 */
-#define ARIZONA_IM_GP1_EINT2_WIDTH                    1  /* IM_GP1_EINT2 */
-
-/*
- * R3353 (0xD19) - IRQ2 Status 2 Mask
- */
-#define ARIZONA_IM_DSP1_RAM_RDY_EINT2            0x0100  /* IM_DSP1_RAM_RDY_EINT2 */
-#define ARIZONA_IM_DSP1_RAM_RDY_EINT2_MASK       0x0100  /* IM_DSP1_RAM_RDY_EINT2 */
-#define ARIZONA_IM_DSP1_RAM_RDY_EINT2_SHIFT           8  /* IM_DSP1_RAM_RDY_EINT2 */
-#define ARIZONA_IM_DSP1_RAM_RDY_EINT2_WIDTH           1  /* IM_DSP1_RAM_RDY_EINT2 */
-#define ARIZONA_IM_DSP_IRQ2_EINT2                0x0002  /* IM_DSP_IRQ2_EINT2 */
-#define ARIZONA_IM_DSP_IRQ2_EINT2_MASK           0x0002  /* IM_DSP_IRQ2_EINT2 */
-#define ARIZONA_IM_DSP_IRQ2_EINT2_SHIFT               1  /* IM_DSP_IRQ2_EINT2 */
-#define ARIZONA_IM_DSP_IRQ2_EINT2_WIDTH               1  /* IM_DSP_IRQ2_EINT2 */
-#define ARIZONA_IM_DSP_IRQ1_EINT2                0x0001  /* IM_DSP_IRQ1_EINT2 */
-#define ARIZONA_IM_DSP_IRQ1_EINT2_MASK           0x0001  /* IM_DSP_IRQ1_EINT2 */
-#define ARIZONA_IM_DSP_IRQ1_EINT2_SHIFT               0  /* IM_DSP_IRQ1_EINT2 */
-#define ARIZONA_IM_DSP_IRQ1_EINT2_WIDTH               1  /* IM_DSP_IRQ1_EINT2 */
-
-/*
- * R3354 (0xD1A) - IRQ2 Status 3 Mask
- */
-#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2       0x8000  /* IM_SPK_SHUTDOWN_WARN_EINT2 */
-#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_MASK  0x8000  /* IM_SPK_SHUTDOWN_WARN_EINT2 */
-#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_SHIFT     15  /* IM_SPK_SHUTDOWN_WARN_EINT2 */
-#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_WIDTH      1  /* IM_SPK_SHUTDOWN_WARN_EINT2 */
-#define ARIZONA_IM_SPK_SHUTDOWN_EINT2            0x4000  /* IM_SPK_SHUTDOWN_EINT2 */
-#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK       0x4000  /* IM_SPK_SHUTDOWN_EINT2 */
-#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT          14  /* IM_SPK_SHUTDOWN_EINT2 */
-#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH           1  /* IM_SPK_SHUTDOWN_EINT2 */
-#define ARIZONA_IM_HPDET_EINT2                   0x2000  /* IM_HPDET_EINT2 */
-#define ARIZONA_IM_HPDET_EINT2_MASK              0x2000  /* IM_HPDET_EINT2 */
-#define ARIZONA_IM_HPDET_EINT2_SHIFT                 13  /* IM_HPDET_EINT2 */
-#define ARIZONA_IM_HPDET_EINT2_WIDTH                  1  /* IM_HPDET_EINT2 */
-#define ARIZONA_IM_MICDET_EINT2                  0x1000  /* IM_MICDET_EINT2 */
-#define ARIZONA_IM_MICDET_EINT2_MASK             0x1000  /* IM_MICDET_EINT2 */
-#define ARIZONA_IM_MICDET_EINT2_SHIFT                12  /* IM_MICDET_EINT2 */
-#define ARIZONA_IM_MICDET_EINT2_WIDTH                 1  /* IM_MICDET_EINT2 */
-#define ARIZONA_IM_WSEQ_DONE_EINT2               0x0800  /* IM_WSEQ_DONE_EINT2 */
-#define ARIZONA_IM_WSEQ_DONE_EINT2_MASK          0x0800  /* IM_WSEQ_DONE_EINT2 */
-#define ARIZONA_IM_WSEQ_DONE_EINT2_SHIFT             11  /* IM_WSEQ_DONE_EINT2 */
-#define ARIZONA_IM_WSEQ_DONE_EINT2_WIDTH              1  /* IM_WSEQ_DONE_EINT2 */
-#define ARIZONA_IM_DRC2_SIG_DET_EINT2            0x0400  /* IM_DRC2_SIG_DET_EINT2 */
-#define ARIZONA_IM_DRC2_SIG_DET_EINT2_MASK       0x0400  /* IM_DRC2_SIG_DET_EINT2 */
-#define ARIZONA_IM_DRC2_SIG_DET_EINT2_SHIFT          10  /* IM_DRC2_SIG_DET_EINT2 */
-#define ARIZONA_IM_DRC2_SIG_DET_EINT2_WIDTH           1  /* IM_DRC2_SIG_DET_EINT2 */
-#define ARIZONA_IM_DRC1_SIG_DET_EINT2            0x0200  /* IM_DRC1_SIG_DET_EINT2 */
-#define ARIZONA_IM_DRC1_SIG_DET_EINT2_MASK       0x0200  /* IM_DRC1_SIG_DET_EINT2 */
-#define ARIZONA_IM_DRC1_SIG_DET_EINT2_SHIFT           9  /* IM_DRC1_SIG_DET_EINT2 */
-#define ARIZONA_IM_DRC1_SIG_DET_EINT2_WIDTH           1  /* IM_DRC1_SIG_DET_EINT2 */
-#define ARIZONA_IM_ASRC2_LOCK_EINT2              0x0100  /* IM_ASRC2_LOCK_EINT2 */
-#define ARIZONA_IM_ASRC2_LOCK_EINT2_MASK         0x0100  /* IM_ASRC2_LOCK_EINT2 */
-#define ARIZONA_IM_ASRC2_LOCK_EINT2_SHIFT             8  /* IM_ASRC2_LOCK_EINT2 */
-#define ARIZONA_IM_ASRC2_LOCK_EINT2_WIDTH             1  /* IM_ASRC2_LOCK_EINT2 */
-#define ARIZONA_IM_ASRC1_LOCK_EINT2              0x0080  /* IM_ASRC1_LOCK_EINT2 */
-#define ARIZONA_IM_ASRC1_LOCK_EINT2_MASK         0x0080  /* IM_ASRC1_LOCK_EINT2 */
-#define ARIZONA_IM_ASRC1_LOCK_EINT2_SHIFT             7  /* IM_ASRC1_LOCK_EINT2 */
-#define ARIZONA_IM_ASRC1_LOCK_EINT2_WIDTH             1  /* IM_ASRC1_LOCK_EINT2 */
-#define ARIZONA_IM_UNDERCLOCKED_EINT2            0x0040  /* IM_UNDERCLOCKED_EINT2 */
-#define ARIZONA_IM_UNDERCLOCKED_EINT2_MASK       0x0040  /* IM_UNDERCLOCKED_EINT2 */
-#define ARIZONA_IM_UNDERCLOCKED_EINT2_SHIFT           6  /* IM_UNDERCLOCKED_EINT2 */
-#define ARIZONA_IM_UNDERCLOCKED_EINT2_WIDTH           1  /* IM_UNDERCLOCKED_EINT2 */
-#define ARIZONA_IM_OVERCLOCKED_EINT2             0x0020  /* IM_OVERCLOCKED_EINT2 */
-#define ARIZONA_IM_OVERCLOCKED_EINT2_MASK        0x0020  /* IM_OVERCLOCKED_EINT2 */
-#define ARIZONA_IM_OVERCLOCKED_EINT2_SHIFT            5  /* IM_OVERCLOCKED_EINT2 */
-#define ARIZONA_IM_OVERCLOCKED_EINT2_WIDTH            1  /* IM_OVERCLOCKED_EINT2 */
-#define ARIZONA_IM_FLL2_LOCK_EINT2               0x0008  /* IM_FLL2_LOCK_EINT2 */
-#define ARIZONA_IM_FLL2_LOCK_EINT2_MASK          0x0008  /* IM_FLL2_LOCK_EINT2 */
-#define ARIZONA_IM_FLL2_LOCK_EINT2_SHIFT              3  /* IM_FLL2_LOCK_EINT2 */
-#define ARIZONA_IM_FLL2_LOCK_EINT2_WIDTH              1  /* IM_FLL2_LOCK_EINT2 */
-#define ARIZONA_IM_FLL1_LOCK_EINT2               0x0004  /* IM_FLL1_LOCK_EINT2 */
-#define ARIZONA_IM_FLL1_LOCK_EINT2_MASK          0x0004  /* IM_FLL1_LOCK_EINT2 */
-#define ARIZONA_IM_FLL1_LOCK_EINT2_SHIFT              2  /* IM_FLL1_LOCK_EINT2 */
-#define ARIZONA_IM_FLL1_LOCK_EINT2_WIDTH              1  /* IM_FLL1_LOCK_EINT2 */
-#define ARIZONA_IM_CLKGEN_ERR_EINT2              0x0002  /* IM_CLKGEN_ERR_EINT2 */
-#define ARIZONA_IM_CLKGEN_ERR_EINT2_MASK         0x0002  /* IM_CLKGEN_ERR_EINT2 */
-#define ARIZONA_IM_CLKGEN_ERR_EINT2_SHIFT             1  /* IM_CLKGEN_ERR_EINT2 */
-#define ARIZONA_IM_CLKGEN_ERR_EINT2_WIDTH             1  /* IM_CLKGEN_ERR_EINT2 */
-#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2        0x0001  /* IM_CLKGEN_ERR_ASYNC_EINT2 */
-#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_MASK   0x0001  /* IM_CLKGEN_ERR_ASYNC_EINT2 */
-#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_SHIFT       0  /* IM_CLKGEN_ERR_ASYNC_EINT2 */
-#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_WIDTH       1  /* IM_CLKGEN_ERR_ASYNC_EINT2 */
-
-/*
- * R3355 (0xD1B) - IRQ2 Status 4 Mask
- */
-#define ARIZONA_IM_ASRC_CFG_ERR_EINT2            0x8000  /* IM_ASRC_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK       0x8000  /* IM_ASRC_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT          15  /* IM_ASRC_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH           1  /* IM_ASRC_CFG_ERR_EINT2 */
-#define ARIZONA_IM_AIF3_ERR_EINT2                0x4000  /* IM_AIF3_ERR_EINT2 */
-#define ARIZONA_IM_AIF3_ERR_EINT2_MASK           0x4000  /* IM_AIF3_ERR_EINT2 */
-#define ARIZONA_IM_AIF3_ERR_EINT2_SHIFT              14  /* IM_AIF3_ERR_EINT2 */
-#define ARIZONA_IM_AIF3_ERR_EINT2_WIDTH               1  /* IM_AIF3_ERR_EINT2 */
-#define ARIZONA_IM_AIF2_ERR_EINT2                0x2000  /* IM_AIF2_ERR_EINT2 */
-#define ARIZONA_IM_AIF2_ERR_EINT2_MASK           0x2000  /* IM_AIF2_ERR_EINT2 */
-#define ARIZONA_IM_AIF2_ERR_EINT2_SHIFT              13  /* IM_AIF2_ERR_EINT2 */
-#define ARIZONA_IM_AIF2_ERR_EINT2_WIDTH               1  /* IM_AIF2_ERR_EINT2 */
-#define ARIZONA_IM_AIF1_ERR_EINT2                0x1000  /* IM_AIF1_ERR_EINT2 */
-#define ARIZONA_IM_AIF1_ERR_EINT2_MASK           0x1000  /* IM_AIF1_ERR_EINT2 */
-#define ARIZONA_IM_AIF1_ERR_EINT2_SHIFT              12  /* IM_AIF1_ERR_EINT2 */
-#define ARIZONA_IM_AIF1_ERR_EINT2_WIDTH               1  /* IM_AIF1_ERR_EINT2 */
-#define ARIZONA_IM_CTRLIF_ERR_EINT2              0x0800  /* IM_CTRLIF_ERR_EINT2 */
-#define ARIZONA_IM_CTRLIF_ERR_EINT2_MASK         0x0800  /* IM_CTRLIF_ERR_EINT2 */
-#define ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT            11  /* IM_CTRLIF_ERR_EINT2 */
-#define ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH             1  /* IM_CTRLIF_ERR_EINT2 */
-#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2    0x0400  /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
-#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400  /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
-#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT     10  /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
-#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH      1  /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
-#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2       0x0200  /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
-#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK  0x0200  /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
-#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT      9  /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
-#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH      1  /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
-#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2          0x0100  /* IM_SYSCLK_ENA_LOW_EINT2 */
-#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK     0x0100  /* IM_SYSCLK_ENA_LOW_EINT2 */
-#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT         8  /* IM_SYSCLK_ENA_LOW_EINT2 */
-#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH         1  /* IM_SYSCLK_ENA_LOW_EINT2 */
-#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2           0x0080  /* IM_ISRC1_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK      0x0080  /* IM_ISRC1_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT          7  /* IM_ISRC1_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH          1  /* IM_ISRC1_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2           0x0040  /* IM_ISRC2_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK      0x0040  /* IM_ISRC2_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT          6  /* IM_ISRC2_CFG_ERR_EINT2 */
-#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH          1  /* IM_ISRC2_CFG_ERR_EINT2 */
-
-/*
- * R3356 (0xD1C) - IRQ2 Status 5 Mask
- */
-
-#define ARIZONA_IM_BOOT_DONE_EINT2               0x0100  /* IM_BOOT_DONE_EINT2 */
-#define ARIZONA_IM_BOOT_DONE_EINT2_MASK          0x0100  /* IM_BOOT_DONE_EINT2 */
-#define ARIZONA_IM_BOOT_DONE_EINT2_SHIFT              8  /* IM_BOOT_DONE_EINT2 */
-#define ARIZONA_IM_BOOT_DONE_EINT2_WIDTH              1  /* IM_BOOT_DONE_EINT2 */
-#define ARIZONA_IM_DCS_DAC_DONE_EINT2            0x0080  /* IM_DCS_DAC_DONE_EINT2 */
-#define ARIZONA_IM_DCS_DAC_DONE_EINT2_MASK       0x0080  /* IM_DCS_DAC_DONE_EINT2 */
-#define ARIZONA_IM_DCS_DAC_DONE_EINT2_SHIFT           7  /* IM_DCS_DAC_DONE_EINT2 */
-#define ARIZONA_IM_DCS_DAC_DONE_EINT2_WIDTH           1  /* IM_DCS_DAC_DONE_EINT2 */
-#define ARIZONA_IM_DCS_HP_DONE_EINT2             0x0040  /* IM_DCS_HP_DONE_EINT2 */
-#define ARIZONA_IM_DCS_HP_DONE_EINT2_MASK        0x0040  /* IM_DCS_HP_DONE_EINT2 */
-#define ARIZONA_IM_DCS_HP_DONE_EINT2_SHIFT            6  /* IM_DCS_HP_DONE_EINT2 */
-#define ARIZONA_IM_DCS_HP_DONE_EINT2_WIDTH            1  /* IM_DCS_HP_DONE_EINT2 */
-#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2           0x0002  /* IM_FLL2_CLOCK_OK_EINT2 */
-#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_MASK      0x0002  /* IM_FLL2_CLOCK_OK_EINT2 */
-#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_SHIFT          1  /* IM_FLL2_CLOCK_OK_EINT2 */
-#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_WIDTH          1  /* IM_FLL2_CLOCK_OK_EINT2 */
-#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2           0x0001  /* IM_FLL1_CLOCK_OK_EINT2 */
-#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_MASK      0x0001  /* IM_FLL1_CLOCK_OK_EINT2 */
-#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT          0  /* IM_FLL1_CLOCK_OK_EINT2 */
-#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH          1  /* IM_FLL1_CLOCK_OK_EINT2 */
-
-/*
- * R3359 (0xD1F) - IRQ2 Control
- */
-#define ARIZONA_IM_IRQ2                          0x0001  /* IM_IRQ2 */
-#define ARIZONA_IM_IRQ2_MASK                     0x0001  /* IM_IRQ2 */
-#define ARIZONA_IM_IRQ2_SHIFT                         0  /* IM_IRQ2 */
-#define ARIZONA_IM_IRQ2_WIDTH                         1  /* IM_IRQ2 */
-
-/*
- * R3360 (0xD20) - Interrupt Raw Status 2
- */
-#define ARIZONA_DSP1_RAM_RDY_STS                 0x0100  /* DSP1_RAM_RDY_STS */
-#define ARIZONA_DSP1_RAM_RDY_STS_MASK            0x0100  /* DSP1_RAM_RDY_STS */
-#define ARIZONA_DSP1_RAM_RDY_STS_SHIFT                8  /* DSP1_RAM_RDY_STS */
-#define ARIZONA_DSP1_RAM_RDY_STS_WIDTH                1  /* DSP1_RAM_RDY_STS */
-#define ARIZONA_DSP_IRQ2_STS                     0x0002  /* DSP_IRQ2_STS */
-#define ARIZONA_DSP_IRQ2_STS_MASK                0x0002  /* DSP_IRQ2_STS */
-#define ARIZONA_DSP_IRQ2_STS_SHIFT                    1  /* DSP_IRQ2_STS */
-#define ARIZONA_DSP_IRQ2_STS_WIDTH                    1  /* DSP_IRQ2_STS */
-#define ARIZONA_DSP_IRQ1_STS                     0x0001  /* DSP_IRQ1_STS */
-#define ARIZONA_DSP_IRQ1_STS_MASK                0x0001  /* DSP_IRQ1_STS */
-#define ARIZONA_DSP_IRQ1_STS_SHIFT                    0  /* DSP_IRQ1_STS */
-#define ARIZONA_DSP_IRQ1_STS_WIDTH                    1  /* DSP_IRQ1_STS */
-
-/*
- * R3361 (0xD21) - Interrupt Raw Status 3
- */
-#define ARIZONA_SPK_SHUTDOWN_WARN_STS            0x8000  /* SPK_SHUTDOWN_WARN_STS */
-#define ARIZONA_SPK_SHUTDOWN_WARN_STS_MASK       0x8000  /* SPK_SHUTDOWN_WARN_STS */
-#define ARIZONA_SPK_SHUTDOWN_WARN_STS_SHIFT          15  /* SPK_SHUTDOWN_WARN_STS */
-#define ARIZONA_SPK_SHUTDOWN_WARN_STS_WIDTH           1  /* SPK_SHUTDOWN_WARN_STS */
-#define ARIZONA_SPK_SHUTDOWN_STS                 0x4000  /* SPK_SHUTDOWN_STS */
-#define ARIZONA_SPK_SHUTDOWN_STS_MASK            0x4000  /* SPK_SHUTDOWN_STS */
-#define ARIZONA_SPK_SHUTDOWN_STS_SHIFT               14  /* SPK_SHUTDOWN_STS */
-#define ARIZONA_SPK_SHUTDOWN_STS_WIDTH                1  /* SPK_SHUTDOWN_STS */
-#define ARIZONA_HPDET_STS                        0x2000  /* HPDET_STS */
-#define ARIZONA_HPDET_STS_MASK                   0x2000  /* HPDET_STS */
-#define ARIZONA_HPDET_STS_SHIFT                      13  /* HPDET_STS */
-#define ARIZONA_HPDET_STS_WIDTH                       1  /* HPDET_STS */
-#define ARIZONA_MICDET_STS                       0x1000  /* MICDET_STS */
-#define ARIZONA_MICDET_STS_MASK                  0x1000  /* MICDET_STS */
-#define ARIZONA_MICDET_STS_SHIFT                     12  /* MICDET_STS */
-#define ARIZONA_MICDET_STS_WIDTH                      1  /* MICDET_STS */
-#define ARIZONA_WSEQ_DONE_STS                    0x0800  /* WSEQ_DONE_STS */
-#define ARIZONA_WSEQ_DONE_STS_MASK               0x0800  /* WSEQ_DONE_STS */
-#define ARIZONA_WSEQ_DONE_STS_SHIFT                  11  /* WSEQ_DONE_STS */
-#define ARIZONA_WSEQ_DONE_STS_WIDTH                   1  /* WSEQ_DONE_STS */
-#define ARIZONA_DRC2_SIG_DET_STS                 0x0400  /* DRC2_SIG_DET_STS */
-#define ARIZONA_DRC2_SIG_DET_STS_MASK            0x0400  /* DRC2_SIG_DET_STS */
-#define ARIZONA_DRC2_SIG_DET_STS_SHIFT               10  /* DRC2_SIG_DET_STS */
-#define ARIZONA_DRC2_SIG_DET_STS_WIDTH                1  /* DRC2_SIG_DET_STS */
-#define ARIZONA_DRC1_SIG_DET_STS                 0x0200  /* DRC1_SIG_DET_STS */
-#define ARIZONA_DRC1_SIG_DET_STS_MASK            0x0200  /* DRC1_SIG_DET_STS */
-#define ARIZONA_DRC1_SIG_DET_STS_SHIFT                9  /* DRC1_SIG_DET_STS */
-#define ARIZONA_DRC1_SIG_DET_STS_WIDTH                1  /* DRC1_SIG_DET_STS */
-#define ARIZONA_ASRC2_LOCK_STS                   0x0100  /* ASRC2_LOCK_STS */
-#define ARIZONA_ASRC2_LOCK_STS_MASK              0x0100  /* ASRC2_LOCK_STS */
-#define ARIZONA_ASRC2_LOCK_STS_SHIFT                  8  /* ASRC2_LOCK_STS */
-#define ARIZONA_ASRC2_LOCK_STS_WIDTH                  1  /* ASRC2_LOCK_STS */
-#define ARIZONA_ASRC1_LOCK_STS                   0x0080  /* ASRC1_LOCK_STS */
-#define ARIZONA_ASRC1_LOCK_STS_MASK              0x0080  /* ASRC1_LOCK_STS */
-#define ARIZONA_ASRC1_LOCK_STS_SHIFT                  7  /* ASRC1_LOCK_STS */
-#define ARIZONA_ASRC1_LOCK_STS_WIDTH                  1  /* ASRC1_LOCK_STS */
-#define ARIZONA_UNDERCLOCKED_STS                 0x0040  /* UNDERCLOCKED_STS */
-#define ARIZONA_UNDERCLOCKED_STS_MASK            0x0040  /* UNDERCLOCKED_STS */
-#define ARIZONA_UNDERCLOCKED_STS_SHIFT                6  /* UNDERCLOCKED_STS */
-#define ARIZONA_UNDERCLOCKED_STS_WIDTH                1  /* UNDERCLOCKED_STS */
-#define ARIZONA_OVERCLOCKED_STS                  0x0020  /* OVERCLOCKED_STS */
-#define ARIZONA_OVERCLOCKED_STS_MASK             0x0020  /* OVERCLOCKED_STS */
-#define ARIZONA_OVERCLOCKED_STS_SHIFT                 5  /* OVERCLOCKED_STS */
-#define ARIZONA_OVERCLOCKED_STS_WIDTH                 1  /* OVERCLOCKED_STS */
-#define ARIZONA_FLL2_LOCK_STS                    0x0008  /* FLL2_LOCK_STS */
-#define ARIZONA_FLL2_LOCK_STS_MASK               0x0008  /* FLL2_LOCK_STS */
-#define ARIZONA_FLL2_LOCK_STS_SHIFT                   3  /* FLL2_LOCK_STS */
-#define ARIZONA_FLL2_LOCK_STS_WIDTH                   1  /* FLL2_LOCK_STS */
-#define ARIZONA_FLL1_LOCK_STS                    0x0004  /* FLL1_LOCK_STS */
-#define ARIZONA_FLL1_LOCK_STS_MASK               0x0004  /* FLL1_LOCK_STS */
-#define ARIZONA_FLL1_LOCK_STS_SHIFT                   2  /* FLL1_LOCK_STS */
-#define ARIZONA_FLL1_LOCK_STS_WIDTH                   1  /* FLL1_LOCK_STS */
-#define ARIZONA_CLKGEN_ERR_STS                   0x0002  /* CLKGEN_ERR_STS */
-#define ARIZONA_CLKGEN_ERR_STS_MASK              0x0002  /* CLKGEN_ERR_STS */
-#define ARIZONA_CLKGEN_ERR_STS_SHIFT                  1  /* CLKGEN_ERR_STS */
-#define ARIZONA_CLKGEN_ERR_STS_WIDTH                  1  /* CLKGEN_ERR_STS */
-#define ARIZONA_CLKGEN_ERR_ASYNC_STS             0x0001  /* CLKGEN_ERR_ASYNC_STS */
-#define ARIZONA_CLKGEN_ERR_ASYNC_STS_MASK        0x0001  /* CLKGEN_ERR_ASYNC_STS */
-#define ARIZONA_CLKGEN_ERR_ASYNC_STS_SHIFT            0  /* CLKGEN_ERR_ASYNC_STS */
-#define ARIZONA_CLKGEN_ERR_ASYNC_STS_WIDTH            1  /* CLKGEN_ERR_ASYNC_STS */
-
-/*
- * R3362 (0xD22) - Interrupt Raw Status 4
- */
-#define ARIZONA_ASRC_CFG_ERR_STS                 0x8000  /* ASRC_CFG_ERR_STS */
-#define ARIZONA_ASRC_CFG_ERR_STS_MASK            0x8000  /* ASRC_CFG_ERR_STS */
-#define ARIZONA_ASRC_CFG_ERR_STS_SHIFT               15  /* ASRC_CFG_ERR_STS */
-#define ARIZONA_ASRC_CFG_ERR_STS_WIDTH                1  /* ASRC_CFG_ERR_STS */
-#define ARIZONA_AIF3_ERR_STS                     0x4000  /* AIF3_ERR_STS */
-#define ARIZONA_AIF3_ERR_STS_MASK                0x4000  /* AIF3_ERR_STS */
-#define ARIZONA_AIF3_ERR_STS_SHIFT                   14  /* AIF3_ERR_STS */
-#define ARIZONA_AIF3_ERR_STS_WIDTH                    1  /* AIF3_ERR_STS */
-#define ARIZONA_AIF2_ERR_STS                     0x2000  /* AIF2_ERR_STS */
-#define ARIZONA_AIF2_ERR_STS_MASK                0x2000  /* AIF2_ERR_STS */
-#define ARIZONA_AIF2_ERR_STS_SHIFT                   13  /* AIF2_ERR_STS */
-#define ARIZONA_AIF2_ERR_STS_WIDTH                    1  /* AIF2_ERR_STS */
-#define ARIZONA_AIF1_ERR_STS                     0x1000  /* AIF1_ERR_STS */
-#define ARIZONA_AIF1_ERR_STS_MASK                0x1000  /* AIF1_ERR_STS */
-#define ARIZONA_AIF1_ERR_STS_SHIFT                   12  /* AIF1_ERR_STS */
-#define ARIZONA_AIF1_ERR_STS_WIDTH                    1  /* AIF1_ERR_STS */
-#define ARIZONA_CTRLIF_ERR_STS                   0x0800  /* CTRLIF_ERR_STS */
-#define ARIZONA_CTRLIF_ERR_STS_MASK              0x0800  /* CTRLIF_ERR_STS */
-#define ARIZONA_CTRLIF_ERR_STS_SHIFT                 11  /* CTRLIF_ERR_STS */
-#define ARIZONA_CTRLIF_ERR_STS_WIDTH                  1  /* CTRLIF_ERR_STS */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_STS         0x0400  /* MIXER_DROPPED_SAMPLE_STS */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_STS_MASK    0x0400  /* MIXER_DROPPED_SAMPLE_STS */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_STS_SHIFT       10  /* MIXER_DROPPED_SAMPLE_STS */
-#define ARIZONA_MIXER_DROPPED_SAMPLE_STS_WIDTH        1  /* MIXER_DROPPED_SAMPLE_STS */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_STS            0x0200  /* ASYNC_CLK_ENA_LOW_STS */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_STS_MASK       0x0200  /* ASYNC_CLK_ENA_LOW_STS */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_STS_SHIFT           9  /* ASYNC_CLK_ENA_LOW_STS */
-#define ARIZONA_ASYNC_CLK_ENA_LOW_STS_WIDTH           1  /* ASYNC_CLK_ENA_LOW_STS */
-#define ARIZONA_SYSCLK_ENA_LOW_STS               0x0100  /* SYSCLK_ENA_LOW_STS */
-#define ARIZONA_SYSCLK_ENA_LOW_STS_MASK          0x0100  /* SYSCLK_ENA_LOW_STS */
-#define ARIZONA_SYSCLK_ENA_LOW_STS_SHIFT              8  /* SYSCLK_ENA_LOW_STS */
-#define ARIZONA_SYSCLK_ENA_LOW_STS_WIDTH              1  /* SYSCLK_ENA_LOW_STS */
-#define ARIZONA_ISRC1_CFG_ERR_STS                0x0080  /* ISRC1_CFG_ERR_STS */
-#define ARIZONA_ISRC1_CFG_ERR_STS_MASK           0x0080  /* ISRC1_CFG_ERR_STS */
-#define ARIZONA_ISRC1_CFG_ERR_STS_SHIFT               7  /* ISRC1_CFG_ERR_STS */
-#define ARIZONA_ISRC1_CFG_ERR_STS_WIDTH               1  /* ISRC1_CFG_ERR_STS */
-#define ARIZONA_ISRC2_CFG_ERR_STS                0x0040  /* ISRC2_CFG_ERR_STS */
-#define ARIZONA_ISRC2_CFG_ERR_STS_MASK           0x0040  /* ISRC2_CFG_ERR_STS */
-#define ARIZONA_ISRC2_CFG_ERR_STS_SHIFT               6  /* ISRC2_CFG_ERR_STS */
-#define ARIZONA_ISRC2_CFG_ERR_STS_WIDTH               1  /* ISRC2_CFG_ERR_STS */
-
-/*
- * R3363 (0xD23) - Interrupt Raw Status 5
- */
-#define ARIZONA_BOOT_DONE_STS                    0x0100  /* BOOT_DONE_STS */
-#define ARIZONA_BOOT_DONE_STS_MASK               0x0100  /* BOOT_DONE_STS */
-#define ARIZONA_BOOT_DONE_STS_SHIFT                   8  /* BOOT_DONE_STS */
-#define ARIZONA_BOOT_DONE_STS_WIDTH                   1  /* BOOT_DONE_STS */
-#define ARIZONA_DCS_DAC_DONE_STS                 0x0080  /* DCS_DAC_DONE_STS */
-#define ARIZONA_DCS_DAC_DONE_STS_MASK            0x0080  /* DCS_DAC_DONE_STS */
-#define ARIZONA_DCS_DAC_DONE_STS_SHIFT                7  /* DCS_DAC_DONE_STS */
-#define ARIZONA_DCS_DAC_DONE_STS_WIDTH                1  /* DCS_DAC_DONE_STS */
-#define ARIZONA_DCS_HP_DONE_STS                  0x0040  /* DCS_HP_DONE_STS */
-#define ARIZONA_DCS_HP_DONE_STS_MASK             0x0040  /* DCS_HP_DONE_STS */
-#define ARIZONA_DCS_HP_DONE_STS_SHIFT                 6  /* DCS_HP_DONE_STS */
-#define ARIZONA_DCS_HP_DONE_STS_WIDTH                 1  /* DCS_HP_DONE_STS */
-#define ARIZONA_FLL2_CLOCK_OK_STS                0x0002  /* FLL2_CLOCK_OK_STS */
-#define ARIZONA_FLL2_CLOCK_OK_STS_MASK           0x0002  /* FLL2_CLOCK_OK_STS */
-#define ARIZONA_FLL2_CLOCK_OK_STS_SHIFT               1  /* FLL2_CLOCK_OK_STS */
-#define ARIZONA_FLL2_CLOCK_OK_STS_WIDTH               1  /* FLL2_CLOCK_OK_STS */
-#define ARIZONA_FLL1_CLOCK_OK_STS                0x0001  /* FLL1_CLOCK_OK_STS */
-#define ARIZONA_FLL1_CLOCK_OK_STS_MASK           0x0001  /* FLL1_CLOCK_OK_STS */
-#define ARIZONA_FLL1_CLOCK_OK_STS_SHIFT               0  /* FLL1_CLOCK_OK_STS */
-#define ARIZONA_FLL1_CLOCK_OK_STS_WIDTH               1  /* FLL1_CLOCK_OK_STS */
-
-/*
- * R3364 (0xD24) - Interrupt Raw Status 6
- */
-#define ARIZONA_PWM_OVERCLOCKED_STS              0x2000  /* PWM_OVERCLOCKED_STS */
-#define ARIZONA_PWM_OVERCLOCKED_STS_MASK         0x2000  /* PWM_OVERCLOCKED_STS */
-#define ARIZONA_PWM_OVERCLOCKED_STS_SHIFT            13  /* PWM_OVERCLOCKED_STS */
-#define ARIZONA_PWM_OVERCLOCKED_STS_WIDTH             1  /* PWM_OVERCLOCKED_STS */
-#define ARIZONA_FX_CORE_OVERCLOCKED_STS          0x1000  /* FX_CORE_OVERCLOCKED_STS */
-#define ARIZONA_FX_CORE_OVERCLOCKED_STS_MASK     0x1000  /* FX_CORE_OVERCLOCKED_STS */
-#define ARIZONA_FX_CORE_OVERCLOCKED_STS_SHIFT        12  /* FX_CORE_OVERCLOCKED_STS */
-#define ARIZONA_FX_CORE_OVERCLOCKED_STS_WIDTH         1  /* FX_CORE_OVERCLOCKED_STS */
-#define ARIZONA_DAC_SYS_OVERCLOCKED_STS          0x0400  /* DAC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_DAC_SYS_OVERCLOCKED_STS_MASK     0x0400  /* DAC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_DAC_SYS_OVERCLOCKED_STS_SHIFT        10  /* DAC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_DAC_SYS_OVERCLOCKED_STS_WIDTH         1  /* DAC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_DAC_WARP_OVERCLOCKED_STS         0x0200  /* DAC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_DAC_WARP_OVERCLOCKED_STS_MASK    0x0200  /* DAC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_DAC_WARP_OVERCLOCKED_STS_SHIFT        9  /* DAC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_DAC_WARP_OVERCLOCKED_STS_WIDTH        1  /* DAC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_ADC_OVERCLOCKED_STS              0x0100  /* ADC_OVERCLOCKED_STS */
-#define ARIZONA_ADC_OVERCLOCKED_STS_MASK         0x0100  /* ADC_OVERCLOCKED_STS */
-#define ARIZONA_ADC_OVERCLOCKED_STS_SHIFT             8  /* ADC_OVERCLOCKED_STS */
-#define ARIZONA_ADC_OVERCLOCKED_STS_WIDTH             1  /* ADC_OVERCLOCKED_STS */
-#define ARIZONA_MIXER_OVERCLOCKED_STS            0x0080  /* MIXER_OVERCLOCKED_STS */
-#define ARIZONA_MIXER_OVERCLOCKED_STS_MASK       0x0080  /* MIXER_OVERCLOCKED_STS */
-#define ARIZONA_MIXER_OVERCLOCKED_STS_SHIFT           7  /* MIXER_OVERCLOCKED_STS */
-#define ARIZONA_MIXER_OVERCLOCKED_STS_WIDTH           1  /* MIXER_OVERCLOCKED_STS */
-#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS       0x0040  /* AIF3_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_MASK  0x0040  /* AIF3_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_SHIFT      6  /* AIF3_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_WIDTH      1  /* AIF3_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS       0x0020  /* AIF2_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_MASK  0x0020  /* AIF2_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_SHIFT      5  /* AIF2_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_WIDTH      1  /* AIF2_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS       0x0010  /* AIF1_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_MASK  0x0010  /* AIF1_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_SHIFT      4  /* AIF1_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_WIDTH      1  /* AIF1_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS        0x0008  /* AIF3_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_MASK   0x0008  /* AIF3_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_SHIFT       3  /* AIF3_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_WIDTH       1  /* AIF3_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS        0x0004  /* AIF2_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_MASK   0x0004  /* AIF2_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_SHIFT       2  /* AIF2_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_WIDTH       1  /* AIF2_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS        0x0002  /* AIF1_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_MASK   0x0002  /* AIF1_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_SHIFT       1  /* AIF1_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_WIDTH       1  /* AIF1_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS         0x0001  /* PAD_CTRL_OVERCLOCKED_STS */
-#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_MASK    0x0001  /* PAD_CTRL_OVERCLOCKED_STS */
-#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_SHIFT        0  /* PAD_CTRL_OVERCLOCKED_STS */
-#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_WIDTH        1  /* PAD_CTRL_OVERCLOCKED_STS */
-
-/*
- * R3365 (0xD25) - Interrupt Raw Status 7
- */
-#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS   0x8000  /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK 0x8000  /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_SHIFT     15  /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_WIDTH      1  /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS    0x4000  /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK 0x4000  /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT     14  /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH      1  /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS     0x2000  /* SLIMBUS_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK 0x2000  /* SLIMBUS_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT     13  /* SLIMBUS_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH      1  /* SLIMBUS_SYNC_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS   0x1000  /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK 0x1000  /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_SHIFT     12  /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_WIDTH      1  /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS  0x0800  /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_MASK 0x0800  /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT     11  /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH      1  /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS    0x0400  /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK 0x0400  /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT     10  /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH      1  /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS   0x0200  /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK 0x0200  /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_SHIFT      9  /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_WIDTH      1  /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
-#define ARIZONA_ADSP2_1_OVERCLOCKED_STS          0x0008  /* ADSP2_1_OVERCLOCKED_STS */
-#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK     0x0008  /* ADSP2_1_OVERCLOCKED_STS */
-#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT         3  /* ADSP2_1_OVERCLOCKED_STS */
-#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH         1  /* ADSP2_1_OVERCLOCKED_STS */
-#define ARIZONA_ISRC2_OVERCLOCKED_STS            0x0002  /* ISRC2_OVERCLOCKED_STS */
-#define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK       0x0002  /* ISRC2_OVERCLOCKED_STS */
-#define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT           1  /* ISRC2_OVERCLOCKED_STS */
-#define ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH           1  /* ISRC2_OVERCLOCKED_STS */
-#define ARIZONA_ISRC1_OVERCLOCKED_STS            0x0001  /* ISRC1_OVERCLOCKED_STS */
-#define ARIZONA_ISRC1_OVERCLOCKED_STS_MASK       0x0001  /* ISRC1_OVERCLOCKED_STS */
-#define ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT           0  /* ISRC1_OVERCLOCKED_STS */
-#define ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH           1  /* ISRC1_OVERCLOCKED_STS */
-
-/*
- * R3366 (0xD26) - Interrupt Raw Status 8
- */
-#define ARIZONA_AIF3_UNDERCLOCKED_STS            0x0400  /* AIF3_UNDERCLOCKED_STS */
-#define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK       0x0400  /* AIF3_UNDERCLOCKED_STS */
-#define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT          10  /* AIF3_UNDERCLOCKED_STS */
-#define ARIZONA_AIF3_UNDERCLOCKED_STS_WIDTH           1  /* AIF3_UNDERCLOCKED_STS */
-#define ARIZONA_AIF2_UNDERCLOCKED_STS            0x0200  /* AIF2_UNDERCLOCKED_STS */
-#define ARIZONA_AIF2_UNDERCLOCKED_STS_MASK       0x0200  /* AIF2_UNDERCLOCKED_STS */
-#define ARIZONA_AIF2_UNDERCLOCKED_STS_SHIFT           9  /* AIF2_UNDERCLOCKED_STS */
-#define ARIZONA_AIF2_UNDERCLOCKED_STS_WIDTH           1  /* AIF2_UNDERCLOCKED_STS */
-#define ARIZONA_AIF1_UNDERCLOCKED_STS            0x0100  /* AIF1_UNDERCLOCKED_STS */
-#define ARIZONA_AIF1_UNDERCLOCKED_STS_MASK       0x0100  /* AIF1_UNDERCLOCKED_STS */
-#define ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT           8  /* AIF1_UNDERCLOCKED_STS */
-#define ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH           1  /* AIF1_UNDERCLOCKED_STS */
-#define ARIZONA_ISRC2_UNDERCLOCKED_STS           0x0040  /* ISRC2_UNDERCLOCKED_STS */
-#define ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK      0x0040  /* ISRC2_UNDERCLOCKED_STS */
-#define ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT          6  /* ISRC2_UNDERCLOCKED_STS */
-#define ARIZONA_ISRC2_UNDERCLOCKED_STS_WIDTH          1  /* ISRC2_UNDERCLOCKED_STS */
-#define ARIZONA_ISRC1_UNDERCLOCKED_STS           0x0020  /* ISRC1_UNDERCLOCKED_STS */
-#define ARIZONA_ISRC1_UNDERCLOCKED_STS_MASK      0x0020  /* ISRC1_UNDERCLOCKED_STS */
-#define ARIZONA_ISRC1_UNDERCLOCKED_STS_SHIFT          5  /* ISRC1_UNDERCLOCKED_STS */
-#define ARIZONA_ISRC1_UNDERCLOCKED_STS_WIDTH          1  /* ISRC1_UNDERCLOCKED_STS */
-#define ARIZONA_FX_UNDERCLOCKED_STS              0x0010  /* FX_UNDERCLOCKED_STS */
-#define ARIZONA_FX_UNDERCLOCKED_STS_MASK         0x0010  /* FX_UNDERCLOCKED_STS */
-#define ARIZONA_FX_UNDERCLOCKED_STS_SHIFT             4  /* FX_UNDERCLOCKED_STS */
-#define ARIZONA_FX_UNDERCLOCKED_STS_WIDTH             1  /* FX_UNDERCLOCKED_STS */
-#define ARIZONA_ASRC_UNDERCLOCKED_STS            0x0008  /* ASRC_UNDERCLOCKED_STS */
-#define ARIZONA_ASRC_UNDERCLOCKED_STS_MASK       0x0008  /* ASRC_UNDERCLOCKED_STS */
-#define ARIZONA_ASRC_UNDERCLOCKED_STS_SHIFT           3  /* ASRC_UNDERCLOCKED_STS */
-#define ARIZONA_ASRC_UNDERCLOCKED_STS_WIDTH           1  /* ASRC_UNDERCLOCKED_STS */
-#define ARIZONA_DAC_UNDERCLOCKED_STS             0x0004  /* DAC_UNDERCLOCKED_STS */
-#define ARIZONA_DAC_UNDERCLOCKED_STS_MASK        0x0004  /* DAC_UNDERCLOCKED_STS */
-#define ARIZONA_DAC_UNDERCLOCKED_STS_SHIFT            2  /* DAC_UNDERCLOCKED_STS */
-#define ARIZONA_DAC_UNDERCLOCKED_STS_WIDTH            1  /* DAC_UNDERCLOCKED_STS */
-#define ARIZONA_ADC_UNDERCLOCKED_STS             0x0002  /* ADC_UNDERCLOCKED_STS */
-#define ARIZONA_ADC_UNDERCLOCKED_STS_MASK        0x0002  /* ADC_UNDERCLOCKED_STS */
-#define ARIZONA_ADC_UNDERCLOCKED_STS_SHIFT            1  /* ADC_UNDERCLOCKED_STS */
-#define ARIZONA_ADC_UNDERCLOCKED_STS_WIDTH            1  /* ADC_UNDERCLOCKED_STS */
-#define ARIZONA_MIXER_UNDERCLOCKED_STS           0x0001  /* MIXER_UNDERCLOCKED_STS */
-#define ARIZONA_MIXER_UNDERCLOCKED_STS_MASK      0x0001  /* MIXER_UNDERCLOCKED_STS */
-#define ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT          0  /* MIXER_UNDERCLOCKED_STS */
-#define ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH          1  /* MIXER_UNDERCLOCKED_STS */
-
-/*
- * R3392 (0xD40) - IRQ Pin Status
- */
-#define ARIZONA_IRQ2_STS                         0x0002  /* IRQ2_STS */
-#define ARIZONA_IRQ2_STS_MASK                    0x0002  /* IRQ2_STS */
-#define ARIZONA_IRQ2_STS_SHIFT                        1  /* IRQ2_STS */
-#define ARIZONA_IRQ2_STS_WIDTH                        1  /* IRQ2_STS */
-#define ARIZONA_IRQ1_STS                         0x0001  /* IRQ1_STS */
-#define ARIZONA_IRQ1_STS_MASK                    0x0001  /* IRQ1_STS */
-#define ARIZONA_IRQ1_STS_SHIFT                        0  /* IRQ1_STS */
-#define ARIZONA_IRQ1_STS_WIDTH                        1  /* IRQ1_STS */
-
-/*
- * R3393 (0xD41) - ADSP2 IRQ0
- */
-#define ARIZONA_DSP_IRQ2                         0x0002  /* DSP_IRQ2 */
-#define ARIZONA_DSP_IRQ2_MASK                    0x0002  /* DSP_IRQ2 */
-#define ARIZONA_DSP_IRQ2_SHIFT                        1  /* DSP_IRQ2 */
-#define ARIZONA_DSP_IRQ2_WIDTH                        1  /* DSP_IRQ2 */
-#define ARIZONA_DSP_IRQ1                         0x0001  /* DSP_IRQ1 */
-#define ARIZONA_DSP_IRQ1_MASK                    0x0001  /* DSP_IRQ1 */
-#define ARIZONA_DSP_IRQ1_SHIFT                        0  /* DSP_IRQ1 */
-#define ARIZONA_DSP_IRQ1_WIDTH                        1  /* DSP_IRQ1 */
-
-/*
- * R3408 (0xD50) - AOD wkup and trig
- */
-#define ARIZONA_GP5_FALL_TRIG_STS                0x0020  /* GP5_FALL_TRIG_STS */
-#define ARIZONA_GP5_FALL_TRIG_STS_MASK           0x0020  /* GP5_FALL_TRIG_STS */
-#define ARIZONA_GP5_FALL_TRIG_STS_SHIFT               5  /* GP5_FALL_TRIG_STS */
-#define ARIZONA_GP5_FALL_TRIG_STS_WIDTH               1  /* GP5_FALL_TRIG_STS */
-#define ARIZONA_GP5_RISE_TRIG_STS                0x0010  /* GP5_RISE_TRIG_STS */
-#define ARIZONA_GP5_RISE_TRIG_STS_MASK           0x0010  /* GP5_RISE_TRIG_STS */
-#define ARIZONA_GP5_RISE_TRIG_STS_SHIFT               4  /* GP5_RISE_TRIG_STS */
-#define ARIZONA_GP5_RISE_TRIG_STS_WIDTH               1  /* GP5_RISE_TRIG_STS */
-#define ARIZONA_JD1_FALL_TRIG_STS                0x0008  /* JD1_FALL_TRIG_STS */
-#define ARIZONA_JD1_FALL_TRIG_STS_MASK           0x0008  /* JD1_FALL_TRIG_STS */
-#define ARIZONA_JD1_FALL_TRIG_STS_SHIFT               3  /* JD1_FALL_TRIG_STS */
-#define ARIZONA_JD1_FALL_TRIG_STS_WIDTH               1  /* JD1_FALL_TRIG_STS */
-#define ARIZONA_JD1_RISE_TRIG_STS                0x0004  /* JD1_RISE_TRIG_STS */
-#define ARIZONA_JD1_RISE_TRIG_STS_MASK           0x0004  /* JD1_RISE_TRIG_STS */
-#define ARIZONA_JD1_RISE_TRIG_STS_SHIFT               2  /* JD1_RISE_TRIG_STS */
-#define ARIZONA_JD1_RISE_TRIG_STS_WIDTH               1  /* JD1_RISE_TRIG_STS */
-#define ARIZONA_JD2_FALL_TRIG_STS                0x0002  /* JD2_FALL_TRIG_STS */
-#define ARIZONA_JD2_FALL_TRIG_STS_MASK           0x0002  /* JD2_FALL_TRIG_STS */
-#define ARIZONA_JD2_FALL_TRIG_STS_SHIFT               1  /* JD2_FALL_TRIG_STS */
-#define ARIZONA_JD2_FALL_TRIG_STS_WIDTH               1  /* JD2_FALL_TRIG_STS */
-#define ARIZONA_JD2_RISE_TRIG_STS                0x0001  /* JD2_RISE_TRIG_STS */
-#define ARIZONA_JD2_RISE_TRIG_STS_MASK           0x0001  /* JD2_RISE_TRIG_STS */
-#define ARIZONA_JD2_RISE_TRIG_STS_SHIFT               0  /* JD2_RISE_TRIG_STS */
-#define ARIZONA_JD2_RISE_TRIG_STS_WIDTH               1  /* JD2_RISE_TRIG_STS */
-
-/*
- * R3409 (0xD51) - AOD IRQ1
- */
-#define ARIZONA_GP5_FALL_EINT1                   0x0020  /* GP5_FALL_EINT1 */
-#define ARIZONA_GP5_FALL_EINT1_MASK              0x0020  /* GP5_FALL_EINT1 */
-#define ARIZONA_GP5_FALL_EINT1_SHIFT                  5  /* GP5_FALL_EINT1 */
-#define ARIZONA_GP5_FALL_EINT1_WIDTH                  1  /* GP5_FALL_EINT1 */
-#define ARIZONA_GP5_RISE_EINT1                   0x0010  /* GP5_RISE_EINT1 */
-#define ARIZONA_GP5_RISE_EINT1_MASK              0x0010  /* GP5_RISE_EINT1 */
-#define ARIZONA_GP5_RISE_EINT1_SHIFT                  4  /* GP5_RISE_EINT1 */
-#define ARIZONA_GP5_RISE_EINT1_WIDTH                  1  /* GP5_RISE_EINT1 */
-#define ARIZONA_JD1_FALL_EINT1                   0x0008  /* JD1_FALL_EINT1 */
-#define ARIZONA_JD1_FALL_EINT1_MASK              0x0008  /* JD1_FALL_EINT1 */
-#define ARIZONA_JD1_FALL_EINT1_SHIFT                  3  /* JD1_FALL_EINT1 */
-#define ARIZONA_JD1_FALL_EINT1_WIDTH                  1  /* JD1_FALL_EINT1 */
-#define ARIZONA_JD1_RISE_EINT1                   0x0004  /* JD1_RISE_EINT1 */
-#define ARIZONA_JD1_RISE_EINT1_MASK              0x0004  /* JD1_RISE_EINT1 */
-#define ARIZONA_JD1_RISE_EINT1_SHIFT                  2  /* JD1_RISE_EINT1 */
-#define ARIZONA_JD1_RISE_EINT1_WIDTH                  1  /* JD1_RISE_EINT1 */
-#define ARIZONA_JD2_FALL_EINT1                   0x0002  /* JD2_FALL_EINT1 */
-#define ARIZONA_JD2_FALL_EINT1_MASK              0x0002  /* JD2_FALL_EINT1 */
-#define ARIZONA_JD2_FALL_EINT1_SHIFT                  1  /* JD2_FALL_EINT1 */
-#define ARIZONA_JD2_FALL_EINT1_WIDTH                  1  /* JD2_FALL_EINT1 */
-#define ARIZONA_JD2_RISE_EINT1                   0x0001  /* JD2_RISE_EINT1 */
-#define ARIZONA_JD2_RISE_EINT1_MASK              0x0001  /* JD2_RISE_EINT1 */
-#define ARIZONA_JD2_RISE_EINT1_SHIFT                  0  /* JD2_RISE_EINT1 */
-#define ARIZONA_JD2_RISE_EINT1_WIDTH                  1  /* JD2_RISE_EINT1 */
-
-/*
- * R3410 (0xD52) - AOD IRQ2
- */
-#define ARIZONA_GP5_FALL_EINT2                   0x0020  /* GP5_FALL_EINT2 */
-#define ARIZONA_GP5_FALL_EINT2_MASK              0x0020  /* GP5_FALL_EINT2 */
-#define ARIZONA_GP5_FALL_EINT2_SHIFT                  5  /* GP5_FALL_EINT2 */
-#define ARIZONA_GP5_FALL_EINT2_WIDTH                  1  /* GP5_FALL_EINT2 */
-#define ARIZONA_GP5_RISE_EINT2                   0x0010  /* GP5_RISE_EINT2 */
-#define ARIZONA_GP5_RISE_EINT2_MASK              0x0010  /* GP5_RISE_EINT2 */
-#define ARIZONA_GP5_RISE_EINT2_SHIFT                  4  /* GP5_RISE_EINT2 */
-#define ARIZONA_GP5_RISE_EINT2_WIDTH                  1  /* GP5_RISE_EINT2 */
-#define ARIZONA_JD1_FALL_EINT2                   0x0008  /* JD1_FALL_EINT2 */
-#define ARIZONA_JD1_FALL_EINT2_MASK              0x0008  /* JD1_FALL_EINT2 */
-#define ARIZONA_JD1_FALL_EINT2_SHIFT                  3  /* JD1_FALL_EINT2 */
-#define ARIZONA_JD1_FALL_EINT2_WIDTH                  1  /* JD1_FALL_EINT2 */
-#define ARIZONA_JD1_RISE_EINT2                   0x0004  /* JD1_RISE_EINT2 */
-#define ARIZONA_JD1_RISE_EINT2_MASK              0x0004  /* JD1_RISE_EINT2 */
-#define ARIZONA_JD1_RISE_EINT2_SHIFT                  2  /* JD1_RISE_EINT2 */
-#define ARIZONA_JD1_RISE_EINT2_WIDTH                  1  /* JD1_RISE_EINT2 */
-#define ARIZONA_JD2_FALL_EINT2                   0x0002  /* JD2_FALL_EINT2 */
-#define ARIZONA_JD2_FALL_EINT2_MASK              0x0002  /* JD2_FALL_EINT2 */
-#define ARIZONA_JD2_FALL_EINT2_SHIFT                  1  /* JD2_FALL_EINT2 */
-#define ARIZONA_JD2_FALL_EINT2_WIDTH                  1  /* JD2_FALL_EINT2 */
-#define ARIZONA_JD2_RISE_EINT2                   0x0001  /* JD2_RISE_EINT2 */
-#define ARIZONA_JD2_RISE_EINT2_MASK              0x0001  /* JD2_RISE_EINT2 */
-#define ARIZONA_JD2_RISE_EINT2_SHIFT                  0  /* JD2_RISE_EINT2 */
-#define ARIZONA_JD2_RISE_EINT2_WIDTH                  1  /* JD2_RISE_EINT2 */
-
-/*
- * R3411 (0xD53) - AOD IRQ Mask IRQ1
- */
-#define ARIZONA_IM_GP5_FALL_EINT1                0x0020  /* IM_GP5_FALL_EINT1 */
-#define ARIZONA_IM_GP5_FALL_EINT1_MASK           0x0020  /* IM_GP5_FALL_EINT1 */
-#define ARIZONA_IM_GP5_FALL_EINT1_SHIFT               5  /* IM_GP5_FALL_EINT1 */
-#define ARIZONA_IM_GP5_FALL_EINT1_WIDTH               1  /* IM_GP5_FALL_EINT1 */
-#define ARIZONA_IM_GP5_RISE_EINT1                0x0010  /* IM_GP5_RISE_EINT1 */
-#define ARIZONA_IM_GP5_RISE_EINT1_MASK           0x0010  /* IM_GP5_RISE_EINT1 */
-#define ARIZONA_IM_GP5_RISE_EINT1_SHIFT               4  /* IM_GP5_RISE_EINT1 */
-#define ARIZONA_IM_GP5_RISE_EINT1_WIDTH               1  /* IM_GP5_RISE_EINT1 */
-#define ARIZONA_IM_JD1_FALL_EINT1                0x0008  /* IM_JD1_FALL_EINT1 */
-#define ARIZONA_IM_JD1_FALL_EINT1_MASK           0x0008  /* IM_JD1_FALL_EINT1 */
-#define ARIZONA_IM_JD1_FALL_EINT1_SHIFT               3  /* IM_JD1_FALL_EINT1 */
-#define ARIZONA_IM_JD1_FALL_EINT1_WIDTH               1  /* IM_JD1_FALL_EINT1 */
-#define ARIZONA_IM_JD1_RISE_EINT1                0x0004  /* IM_JD1_RISE_EINT1 */
-#define ARIZONA_IM_JD1_RISE_EINT1_MASK           0x0004  /* IM_JD1_RISE_EINT1 */
-#define ARIZONA_IM_JD1_RISE_EINT1_SHIFT               2  /* IM_JD1_RISE_EINT1 */
-#define ARIZONA_IM_JD1_RISE_EINT1_WIDTH               1  /* IM_JD1_RISE_EINT1 */
-#define ARIZONA_IM_JD2_FALL_EINT1                0x0002  /* IM_JD2_FALL_EINT1 */
-#define ARIZONA_IM_JD2_FALL_EINT1_MASK           0x0002  /* IM_JD2_FALL_EINT1 */
-#define ARIZONA_IM_JD2_FALL_EINT1_SHIFT               1  /* IM_JD2_FALL_EINT1 */
-#define ARIZONA_IM_JD2_FALL_EINT1_WIDTH               1  /* IM_JD2_FALL_EINT1 */
-#define ARIZONA_IM_JD2_RISE_EINT1                0x0001  /* IM_JD2_RISE_EINT1 */
-#define ARIZONA_IM_JD2_RISE_EINT1_MASK           0x0001  /* IM_JD2_RISE_EINT1 */
-#define ARIZONA_IM_JD2_RISE_EINT1_SHIFT               0  /* IM_JD2_RISE_EINT1 */
-#define ARIZONA_IM_JD2_RISE_EINT1_WIDTH               1  /* IM_JD2_RISE_EINT1 */
-
-/*
- * R3412 (0xD54) - AOD IRQ Mask IRQ2
- */
-#define ARIZONA_IM_GP5_FALL_EINT2                0x0020  /* IM_GP5_FALL_EINT2 */
-#define ARIZONA_IM_GP5_FALL_EINT2_MASK           0x0020  /* IM_GP5_FALL_EINT2 */
-#define ARIZONA_IM_GP5_FALL_EINT2_SHIFT               5  /* IM_GP5_FALL_EINT2 */
-#define ARIZONA_IM_GP5_FALL_EINT2_WIDTH               1  /* IM_GP5_FALL_EINT2 */
-#define ARIZONA_IM_GP5_RISE_EINT2                0x0010  /* IM_GP5_RISE_EINT2 */
-#define ARIZONA_IM_GP5_RISE_EINT2_MASK           0x0010  /* IM_GP5_RISE_EINT2 */
-#define ARIZONA_IM_GP5_RISE_EINT2_SHIFT               4  /* IM_GP5_RISE_EINT2 */
-#define ARIZONA_IM_GP5_RISE_EINT2_WIDTH               1  /* IM_GP5_RISE_EINT2 */
-#define ARIZONA_IM_JD1_FALL_EINT2                0x0008  /* IM_JD1_FALL_EINT2 */
-#define ARIZONA_IM_JD1_FALL_EINT2_MASK           0x0008  /* IM_JD1_FALL_EINT2 */
-#define ARIZONA_IM_JD1_FALL_EINT2_SHIFT               3  /* IM_JD1_FALL_EINT2 */
-#define ARIZONA_IM_JD1_FALL_EINT2_WIDTH               1  /* IM_JD1_FALL_EINT2 */
-#define ARIZONA_IM_JD1_RISE_EINT2                0x0004  /* IM_JD1_RISE_EINT2 */
-#define ARIZONA_IM_JD1_RISE_EINT2_MASK           0x0004  /* IM_JD1_RISE_EINT2 */
-#define ARIZONA_IM_JD1_RISE_EINT2_SHIFT               2  /* IM_JD1_RISE_EINT2 */
-#define ARIZONA_IM_JD1_RISE_EINT2_WIDTH               1  /* IM_JD1_RISE_EINT2 */
-#define ARIZONA_IM_JD2_FALL_EINT2                0x0002  /* IM_JD2_FALL_EINT2 */
-#define ARIZONA_IM_JD2_FALL_EINT2_MASK           0x0002  /* IM_JD2_FALL_EINT2 */
-#define ARIZONA_IM_JD2_FALL_EINT2_SHIFT               1  /* IM_JD2_FALL_EINT2 */
-#define ARIZONA_IM_JD2_FALL_EINT2_WIDTH               1  /* IM_JD2_FALL_EINT2 */
-#define ARIZONA_IM_JD2_RISE_EINT2                0x0001  /* IM_JD2_RISE_EINT2 */
-#define ARIZONA_IM_JD2_RISE_EINT2_MASK           0x0001  /* IM_JD2_RISE_EINT2 */
-#define ARIZONA_IM_JD2_RISE_EINT2_SHIFT               0  /* IM_JD2_RISE_EINT2 */
-#define ARIZONA_IM_JD2_RISE_EINT2_WIDTH               1  /* IM_JD2_RISE_EINT2 */
-
-/*
- * R3413 (0xD55) - AOD IRQ Raw Status
- */
-#define ARIZONA_GP5_STS                          0x0004  /* GP5_STS */
-#define ARIZONA_GP5_STS_MASK                     0x0004  /* GP5_STS */
-#define ARIZONA_GP5_STS_SHIFT                         2  /* GP5_STS */
-#define ARIZONA_GP5_STS_WIDTH                         1  /* GP5_STS */
-#define ARIZONA_JD2_STS                          0x0002  /* JD2_STS */
-#define ARIZONA_JD2_STS_MASK                     0x0002  /* JD2_STS */
-#define ARIZONA_JD2_STS_SHIFT                         1  /* JD2_STS */
-#define ARIZONA_JD2_STS_WIDTH                         1  /* JD2_STS */
-#define ARIZONA_JD1_STS                          0x0001  /* JD1_STS */
-#define ARIZONA_JD1_STS_MASK                     0x0001  /* JD1_STS */
-#define ARIZONA_JD1_STS_SHIFT                         0  /* JD1_STS */
-#define ARIZONA_JD1_STS_WIDTH                         1  /* JD1_STS */
-
-/*
- * R3414 (0xD56) - Jack detect debounce
- */
-#define ARIZONA_JD2_DB                           0x0002  /* JD2_DB */
-#define ARIZONA_JD2_DB_MASK                      0x0002  /* JD2_DB */
-#define ARIZONA_JD2_DB_SHIFT                          1  /* JD2_DB */
-#define ARIZONA_JD2_DB_WIDTH                          1  /* JD2_DB */
-#define ARIZONA_JD1_DB                           0x0001  /* JD1_DB */
-#define ARIZONA_JD1_DB_MASK                      0x0001  /* JD1_DB */
-#define ARIZONA_JD1_DB_SHIFT                          0  /* JD1_DB */
-#define ARIZONA_JD1_DB_WIDTH                          1  /* JD1_DB */
-
-/*
- * R3584 (0xE00) - FX_Ctrl1
- */
-#define ARIZONA_FX_RATE_MASK                     0x7800  /* FX_RATE - [14:11] */
-#define ARIZONA_FX_RATE_SHIFT                        11  /* FX_RATE - [14:11] */
-#define ARIZONA_FX_RATE_WIDTH                         4  /* FX_RATE - [14:11] */
-
-/*
- * R3585 (0xE01) - FX_Ctrl2
- */
-#define ARIZONA_FX_STS_MASK                      0xFFF0  /* FX_STS - [15:4] */
-#define ARIZONA_FX_STS_SHIFT                          4  /* FX_STS - [15:4] */
-#define ARIZONA_FX_STS_WIDTH                         12  /* FX_STS - [15:4] */
-
-/*
- * R3600 (0xE10) - EQ1_1
- */
-#define ARIZONA_EQ1_B1_GAIN_MASK                 0xF800  /* EQ1_B1_GAIN - [15:11] */
-#define ARIZONA_EQ1_B1_GAIN_SHIFT                    11  /* EQ1_B1_GAIN - [15:11] */
-#define ARIZONA_EQ1_B1_GAIN_WIDTH                     5  /* EQ1_B1_GAIN - [15:11] */
-#define ARIZONA_EQ1_B2_GAIN_MASK                 0x07C0  /* EQ1_B2_GAIN - [10:6] */
-#define ARIZONA_EQ1_B2_GAIN_SHIFT                     6  /* EQ1_B2_GAIN - [10:6] */
-#define ARIZONA_EQ1_B2_GAIN_WIDTH                     5  /* EQ1_B2_GAIN - [10:6] */
-#define ARIZONA_EQ1_B3_GAIN_MASK                 0x003E  /* EQ1_B3_GAIN - [5:1] */
-#define ARIZONA_EQ1_B3_GAIN_SHIFT                     1  /* EQ1_B3_GAIN - [5:1] */
-#define ARIZONA_EQ1_B3_GAIN_WIDTH                     5  /* EQ1_B3_GAIN - [5:1] */
-#define ARIZONA_EQ1_ENA                          0x0001  /* EQ1_ENA */
-#define ARIZONA_EQ1_ENA_MASK                     0x0001  /* EQ1_ENA */
-#define ARIZONA_EQ1_ENA_SHIFT                         0  /* EQ1_ENA */
-#define ARIZONA_EQ1_ENA_WIDTH                         1  /* EQ1_ENA */
-
-/*
- * R3601 (0xE11) - EQ1_2
- */
-#define ARIZONA_EQ1_B4_GAIN_MASK                 0xF800  /* EQ1_B4_GAIN - [15:11] */
-#define ARIZONA_EQ1_B4_GAIN_SHIFT                    11  /* EQ1_B4_GAIN - [15:11] */
-#define ARIZONA_EQ1_B4_GAIN_WIDTH                     5  /* EQ1_B4_GAIN - [15:11] */
-#define ARIZONA_EQ1_B5_GAIN_MASK                 0x07C0  /* EQ1_B5_GAIN - [10:6] */
-#define ARIZONA_EQ1_B5_GAIN_SHIFT                     6  /* EQ1_B5_GAIN - [10:6] */
-#define ARIZONA_EQ1_B5_GAIN_WIDTH                     5  /* EQ1_B5_GAIN - [10:6] */
-#define ARIZONA_EQ1_B1_MODE                      0x0001  /* EQ1_B1_MODE */
-#define ARIZONA_EQ1_B1_MODE_MASK                 0x0001  /* EQ1_B1_MODE */
-#define ARIZONA_EQ1_B1_MODE_SHIFT                     0  /* EQ1_B1_MODE */
-#define ARIZONA_EQ1_B1_MODE_WIDTH                     1  /* EQ1_B1_MODE */
-
-/*
- * R3602 (0xE12) - EQ1_3
- */
-#define ARIZONA_EQ1_B1_A_MASK                    0xFFFF  /* EQ1_B1_A - [15:0] */
-#define ARIZONA_EQ1_B1_A_SHIFT                        0  /* EQ1_B1_A - [15:0] */
-#define ARIZONA_EQ1_B1_A_WIDTH                       16  /* EQ1_B1_A - [15:0] */
-
-/*
- * R3603 (0xE13) - EQ1_4
- */
-#define ARIZONA_EQ1_B1_B_MASK                    0xFFFF  /* EQ1_B1_B - [15:0] */
-#define ARIZONA_EQ1_B1_B_SHIFT                        0  /* EQ1_B1_B - [15:0] */
-#define ARIZONA_EQ1_B1_B_WIDTH                       16  /* EQ1_B1_B - [15:0] */
-
-/*
- * R3604 (0xE14) - EQ1_5
- */
-#define ARIZONA_EQ1_B1_PG_MASK                   0xFFFF  /* EQ1_B1_PG - [15:0] */
-#define ARIZONA_EQ1_B1_PG_SHIFT                       0  /* EQ1_B1_PG - [15:0] */
-#define ARIZONA_EQ1_B1_PG_WIDTH                      16  /* EQ1_B1_PG - [15:0] */
-
-/*
- * R3605 (0xE15) - EQ1_6
- */
-#define ARIZONA_EQ1_B2_A_MASK                    0xFFFF  /* EQ1_B2_A - [15:0] */
-#define ARIZONA_EQ1_B2_A_SHIFT                        0  /* EQ1_B2_A - [15:0] */
-#define ARIZONA_EQ1_B2_A_WIDTH                       16  /* EQ1_B2_A - [15:0] */
-
-/*
- * R3606 (0xE16) - EQ1_7
- */
-#define ARIZONA_EQ1_B2_B_MASK                    0xFFFF  /* EQ1_B2_B - [15:0] */
-#define ARIZONA_EQ1_B2_B_SHIFT                        0  /* EQ1_B2_B - [15:0] */
-#define ARIZONA_EQ1_B2_B_WIDTH                       16  /* EQ1_B2_B - [15:0] */
-
-/*
- * R3607 (0xE17) - EQ1_8
- */
-#define ARIZONA_EQ1_B2_C_MASK                    0xFFFF  /* EQ1_B2_C - [15:0] */
-#define ARIZONA_EQ1_B2_C_SHIFT                        0  /* EQ1_B2_C - [15:0] */
-#define ARIZONA_EQ1_B2_C_WIDTH                       16  /* EQ1_B2_C - [15:0] */
-
-/*
- * R3608 (0xE18) - EQ1_9
- */
-#define ARIZONA_EQ1_B2_PG_MASK                   0xFFFF  /* EQ1_B2_PG - [15:0] */
-#define ARIZONA_EQ1_B2_PG_SHIFT                       0  /* EQ1_B2_PG - [15:0] */
-#define ARIZONA_EQ1_B2_PG_WIDTH                      16  /* EQ1_B2_PG - [15:0] */
-
-/*
- * R3609 (0xE19) - EQ1_10
- */
-#define ARIZONA_EQ1_B3_A_MASK                    0xFFFF  /* EQ1_B3_A - [15:0] */
-#define ARIZONA_EQ1_B3_A_SHIFT                        0  /* EQ1_B3_A - [15:0] */
-#define ARIZONA_EQ1_B3_A_WIDTH                       16  /* EQ1_B3_A - [15:0] */
-
-/*
- * R3610 (0xE1A) - EQ1_11
- */
-#define ARIZONA_EQ1_B3_B_MASK                    0xFFFF  /* EQ1_B3_B - [15:0] */
-#define ARIZONA_EQ1_B3_B_SHIFT                        0  /* EQ1_B3_B - [15:0] */
-#define ARIZONA_EQ1_B3_B_WIDTH                       16  /* EQ1_B3_B - [15:0] */
-
-/*
- * R3611 (0xE1B) - EQ1_12
- */
-#define ARIZONA_EQ1_B3_C_MASK                    0xFFFF  /* EQ1_B3_C - [15:0] */
-#define ARIZONA_EQ1_B3_C_SHIFT                        0  /* EQ1_B3_C - [15:0] */
-#define ARIZONA_EQ1_B3_C_WIDTH                       16  /* EQ1_B3_C - [15:0] */
-
-/*
- * R3612 (0xE1C) - EQ1_13
- */
-#define ARIZONA_EQ1_B3_PG_MASK                   0xFFFF  /* EQ1_B3_PG - [15:0] */
-#define ARIZONA_EQ1_B3_PG_SHIFT                       0  /* EQ1_B3_PG - [15:0] */
-#define ARIZONA_EQ1_B3_PG_WIDTH                      16  /* EQ1_B3_PG - [15:0] */
-
-/*
- * R3613 (0xE1D) - EQ1_14
- */
-#define ARIZONA_EQ1_B4_A_MASK                    0xFFFF  /* EQ1_B4_A - [15:0] */
-#define ARIZONA_EQ1_B4_A_SHIFT                        0  /* EQ1_B4_A - [15:0] */
-#define ARIZONA_EQ1_B4_A_WIDTH                       16  /* EQ1_B4_A - [15:0] */
-
-/*
- * R3614 (0xE1E) - EQ1_15
- */
-#define ARIZONA_EQ1_B4_B_MASK                    0xFFFF  /* EQ1_B4_B - [15:0] */
-#define ARIZONA_EQ1_B4_B_SHIFT                        0  /* EQ1_B4_B - [15:0] */
-#define ARIZONA_EQ1_B4_B_WIDTH                       16  /* EQ1_B4_B - [15:0] */
-
-/*
- * R3615 (0xE1F) - EQ1_16
- */
-#define ARIZONA_EQ1_B4_C_MASK                    0xFFFF  /* EQ1_B4_C - [15:0] */
-#define ARIZONA_EQ1_B4_C_SHIFT                        0  /* EQ1_B4_C - [15:0] */
-#define ARIZONA_EQ1_B4_C_WIDTH                       16  /* EQ1_B4_C - [15:0] */
-
-/*
- * R3616 (0xE20) - EQ1_17
- */
-#define ARIZONA_EQ1_B4_PG_MASK                   0xFFFF  /* EQ1_B4_PG - [15:0] */
-#define ARIZONA_EQ1_B4_PG_SHIFT                       0  /* EQ1_B4_PG - [15:0] */
-#define ARIZONA_EQ1_B4_PG_WIDTH                      16  /* EQ1_B4_PG - [15:0] */
-
-/*
- * R3617 (0xE21) - EQ1_18
- */
-#define ARIZONA_EQ1_B5_A_MASK                    0xFFFF  /* EQ1_B5_A - [15:0] */
-#define ARIZONA_EQ1_B5_A_SHIFT                        0  /* EQ1_B5_A - [15:0] */
-#define ARIZONA_EQ1_B5_A_WIDTH                       16  /* EQ1_B5_A - [15:0] */
-
-/*
- * R3618 (0xE22) - EQ1_19
- */
-#define ARIZONA_EQ1_B5_B_MASK                    0xFFFF  /* EQ1_B5_B - [15:0] */
-#define ARIZONA_EQ1_B5_B_SHIFT                        0  /* EQ1_B5_B - [15:0] */
-#define ARIZONA_EQ1_B5_B_WIDTH                       16  /* EQ1_B5_B - [15:0] */
-
-/*
- * R3619 (0xE23) - EQ1_20
- */
-#define ARIZONA_EQ1_B5_PG_MASK                   0xFFFF  /* EQ1_B5_PG - [15:0] */
-#define ARIZONA_EQ1_B5_PG_SHIFT                       0  /* EQ1_B5_PG - [15:0] */
-#define ARIZONA_EQ1_B5_PG_WIDTH                      16  /* EQ1_B5_PG - [15:0] */
-
-/*
- * R3620 (0xE24) - EQ1_21
- */
-#define ARIZONA_EQ1_B1_C_MASK                    0xFFFF  /* EQ1_B1_C - [15:0] */
-#define ARIZONA_EQ1_B1_C_SHIFT                        0  /* EQ1_B1_C - [15:0] */
-#define ARIZONA_EQ1_B1_C_WIDTH                       16  /* EQ1_B1_C - [15:0] */
-
-/*
- * R3622 (0xE26) - EQ2_1
- */
-#define ARIZONA_EQ2_B1_GAIN_MASK                 0xF800  /* EQ2_B1_GAIN - [15:11] */
-#define ARIZONA_EQ2_B1_GAIN_SHIFT                    11  /* EQ2_B1_GAIN - [15:11] */
-#define ARIZONA_EQ2_B1_GAIN_WIDTH                     5  /* EQ2_B1_GAIN - [15:11] */
-#define ARIZONA_EQ2_B2_GAIN_MASK                 0x07C0  /* EQ2_B2_GAIN - [10:6] */
-#define ARIZONA_EQ2_B2_GAIN_SHIFT                     6  /* EQ2_B2_GAIN - [10:6] */
-#define ARIZONA_EQ2_B2_GAIN_WIDTH                     5  /* EQ2_B2_GAIN - [10:6] */
-#define ARIZONA_EQ2_B3_GAIN_MASK                 0x003E  /* EQ2_B3_GAIN - [5:1] */
-#define ARIZONA_EQ2_B3_GAIN_SHIFT                     1  /* EQ2_B3_GAIN - [5:1] */
-#define ARIZONA_EQ2_B3_GAIN_WIDTH                     5  /* EQ2_B3_GAIN - [5:1] */
-#define ARIZONA_EQ2_ENA                          0x0001  /* EQ2_ENA */
-#define ARIZONA_EQ2_ENA_MASK                     0x0001  /* EQ2_ENA */
-#define ARIZONA_EQ2_ENA_SHIFT                         0  /* EQ2_ENA */
-#define ARIZONA_EQ2_ENA_WIDTH                         1  /* EQ2_ENA */
-
-/*
- * R3623 (0xE27) - EQ2_2
- */
-#define ARIZONA_EQ2_B4_GAIN_MASK                 0xF800  /* EQ2_B4_GAIN - [15:11] */
-#define ARIZONA_EQ2_B4_GAIN_SHIFT                    11  /* EQ2_B4_GAIN - [15:11] */
-#define ARIZONA_EQ2_B4_GAIN_WIDTH                     5  /* EQ2_B4_GAIN - [15:11] */
-#define ARIZONA_EQ2_B5_GAIN_MASK                 0x07C0  /* EQ2_B5_GAIN - [10:6] */
-#define ARIZONA_EQ2_B5_GAIN_SHIFT                     6  /* EQ2_B5_GAIN - [10:6] */
-#define ARIZONA_EQ2_B5_GAIN_WIDTH                     5  /* EQ2_B5_GAIN - [10:6] */
-#define ARIZONA_EQ2_B1_MODE                      0x0001  /* EQ2_B1_MODE */
-#define ARIZONA_EQ2_B1_MODE_MASK                 0x0001  /* EQ2_B1_MODE */
-#define ARIZONA_EQ2_B1_MODE_SHIFT                     0  /* EQ2_B1_MODE */
-#define ARIZONA_EQ2_B1_MODE_WIDTH                     1  /* EQ2_B1_MODE */
-
-/*
- * R3624 (0xE28) - EQ2_3
- */
-#define ARIZONA_EQ2_B1_A_MASK                    0xFFFF  /* EQ2_B1_A - [15:0] */
-#define ARIZONA_EQ2_B1_A_SHIFT                        0  /* EQ2_B1_A - [15:0] */
-#define ARIZONA_EQ2_B1_A_WIDTH                       16  /* EQ2_B1_A - [15:0] */
-
-/*
- * R3625 (0xE29) - EQ2_4
- */
-#define ARIZONA_EQ2_B1_B_MASK                    0xFFFF  /* EQ2_B1_B - [15:0] */
-#define ARIZONA_EQ2_B1_B_SHIFT                        0  /* EQ2_B1_B - [15:0] */
-#define ARIZONA_EQ2_B1_B_WIDTH                       16  /* EQ2_B1_B - [15:0] */
-
-/*
- * R3626 (0xE2A) - EQ2_5
- */
-#define ARIZONA_EQ2_B1_PG_MASK                   0xFFFF  /* EQ2_B1_PG - [15:0] */
-#define ARIZONA_EQ2_B1_PG_SHIFT                       0  /* EQ2_B1_PG - [15:0] */
-#define ARIZONA_EQ2_B1_PG_WIDTH                      16  /* EQ2_B1_PG - [15:0] */
-
-/*
- * R3627 (0xE2B) - EQ2_6
- */
-#define ARIZONA_EQ2_B2_A_MASK                    0xFFFF  /* EQ2_B2_A - [15:0] */
-#define ARIZONA_EQ2_B2_A_SHIFT                        0  /* EQ2_B2_A - [15:0] */
-#define ARIZONA_EQ2_B2_A_WIDTH                       16  /* EQ2_B2_A - [15:0] */
-
-/*
- * R3628 (0xE2C) - EQ2_7
- */
-#define ARIZONA_EQ2_B2_B_MASK                    0xFFFF  /* EQ2_B2_B - [15:0] */
-#define ARIZONA_EQ2_B2_B_SHIFT                        0  /* EQ2_B2_B - [15:0] */
-#define ARIZONA_EQ2_B2_B_WIDTH                       16  /* EQ2_B2_B - [15:0] */
-
-/*
- * R3629 (0xE2D) - EQ2_8
- */
-#define ARIZONA_EQ2_B2_C_MASK                    0xFFFF  /* EQ2_B2_C - [15:0] */
-#define ARIZONA_EQ2_B2_C_SHIFT                        0  /* EQ2_B2_C - [15:0] */
-#define ARIZONA_EQ2_B2_C_WIDTH                       16  /* EQ2_B2_C - [15:0] */
-
-/*
- * R3630 (0xE2E) - EQ2_9
- */
-#define ARIZONA_EQ2_B2_PG_MASK                   0xFFFF  /* EQ2_B2_PG - [15:0] */
-#define ARIZONA_EQ2_B2_PG_SHIFT                       0  /* EQ2_B2_PG - [15:0] */
-#define ARIZONA_EQ2_B2_PG_WIDTH                      16  /* EQ2_B2_PG - [15:0] */
-
-/*
- * R3631 (0xE2F) - EQ2_10
- */
-#define ARIZONA_EQ2_B3_A_MASK                    0xFFFF  /* EQ2_B3_A - [15:0] */
-#define ARIZONA_EQ2_B3_A_SHIFT                        0  /* EQ2_B3_A - [15:0] */
-#define ARIZONA_EQ2_B3_A_WIDTH                       16  /* EQ2_B3_A - [15:0] */
-
-/*
- * R3632 (0xE30) - EQ2_11
- */
-#define ARIZONA_EQ2_B3_B_MASK                    0xFFFF  /* EQ2_B3_B - [15:0] */
-#define ARIZONA_EQ2_B3_B_SHIFT                        0  /* EQ2_B3_B - [15:0] */
-#define ARIZONA_EQ2_B3_B_WIDTH                       16  /* EQ2_B3_B - [15:0] */
-
-/*
- * R3633 (0xE31) - EQ2_12
- */
-#define ARIZONA_EQ2_B3_C_MASK                    0xFFFF  /* EQ2_B3_C - [15:0] */
-#define ARIZONA_EQ2_B3_C_SHIFT                        0  /* EQ2_B3_C - [15:0] */
-#define ARIZONA_EQ2_B3_C_WIDTH                       16  /* EQ2_B3_C - [15:0] */
-
-/*
- * R3634 (0xE32) - EQ2_13
- */
-#define ARIZONA_EQ2_B3_PG_MASK                   0xFFFF  /* EQ2_B3_PG - [15:0] */
-#define ARIZONA_EQ2_B3_PG_SHIFT                       0  /* EQ2_B3_PG - [15:0] */
-#define ARIZONA_EQ2_B3_PG_WIDTH                      16  /* EQ2_B3_PG - [15:0] */
-
-/*
- * R3635 (0xE33) - EQ2_14
- */
-#define ARIZONA_EQ2_B4_A_MASK                    0xFFFF  /* EQ2_B4_A - [15:0] */
-#define ARIZONA_EQ2_B4_A_SHIFT                        0  /* EQ2_B4_A - [15:0] */
-#define ARIZONA_EQ2_B4_A_WIDTH                       16  /* EQ2_B4_A - [15:0] */
-
-/*
- * R3636 (0xE34) - EQ2_15
- */
-#define ARIZONA_EQ2_B4_B_MASK                    0xFFFF  /* EQ2_B4_B - [15:0] */
-#define ARIZONA_EQ2_B4_B_SHIFT                        0  /* EQ2_B4_B - [15:0] */
-#define ARIZONA_EQ2_B4_B_WIDTH                       16  /* EQ2_B4_B - [15:0] */
-
-/*
- * R3637 (0xE35) - EQ2_16
- */
-#define ARIZONA_EQ2_B4_C_MASK                    0xFFFF  /* EQ2_B4_C - [15:0] */
-#define ARIZONA_EQ2_B4_C_SHIFT                        0  /* EQ2_B4_C - [15:0] */
-#define ARIZONA_EQ2_B4_C_WIDTH                       16  /* EQ2_B4_C - [15:0] */
-
-/*
- * R3638 (0xE36) - EQ2_17
- */
-#define ARIZONA_EQ2_B4_PG_MASK                   0xFFFF  /* EQ2_B4_PG - [15:0] */
-#define ARIZONA_EQ2_B4_PG_SHIFT                       0  /* EQ2_B4_PG - [15:0] */
-#define ARIZONA_EQ2_B4_PG_WIDTH                      16  /* EQ2_B4_PG - [15:0] */
-
-/*
- * R3639 (0xE37) - EQ2_18
- */
-#define ARIZONA_EQ2_B5_A_MASK                    0xFFFF  /* EQ2_B5_A - [15:0] */
-#define ARIZONA_EQ2_B5_A_SHIFT                        0  /* EQ2_B5_A - [15:0] */
-#define ARIZONA_EQ2_B5_A_WIDTH                       16  /* EQ2_B5_A - [15:0] */
-
-/*
- * R3640 (0xE38) - EQ2_19
- */
-#define ARIZONA_EQ2_B5_B_MASK                    0xFFFF  /* EQ2_B5_B - [15:0] */
-#define ARIZONA_EQ2_B5_B_SHIFT                        0  /* EQ2_B5_B - [15:0] */
-#define ARIZONA_EQ2_B5_B_WIDTH                       16  /* EQ2_B5_B - [15:0] */
-
-/*
- * R3641 (0xE39) - EQ2_20
- */
-#define ARIZONA_EQ2_B5_PG_MASK                   0xFFFF  /* EQ2_B5_PG - [15:0] */
-#define ARIZONA_EQ2_B5_PG_SHIFT                       0  /* EQ2_B5_PG - [15:0] */
-#define ARIZONA_EQ2_B5_PG_WIDTH                      16  /* EQ2_B5_PG - [15:0] */
-
-/*
- * R3642 (0xE3A) - EQ2_21
- */
-#define ARIZONA_EQ2_B1_C_MASK                    0xFFFF  /* EQ2_B1_C - [15:0] */
-#define ARIZONA_EQ2_B1_C_SHIFT                        0  /* EQ2_B1_C - [15:0] */
-#define ARIZONA_EQ2_B1_C_WIDTH                       16  /* EQ2_B1_C - [15:0] */
-
-/*
- * R3644 (0xE3C) - EQ3_1
- */
-#define ARIZONA_EQ3_B1_GAIN_MASK                 0xF800  /* EQ3_B1_GAIN - [15:11] */
-#define ARIZONA_EQ3_B1_GAIN_SHIFT                    11  /* EQ3_B1_GAIN - [15:11] */
-#define ARIZONA_EQ3_B1_GAIN_WIDTH                     5  /* EQ3_B1_GAIN - [15:11] */
-#define ARIZONA_EQ3_B2_GAIN_MASK                 0x07C0  /* EQ3_B2_GAIN - [10:6] */
-#define ARIZONA_EQ3_B2_GAIN_SHIFT                     6  /* EQ3_B2_GAIN - [10:6] */
-#define ARIZONA_EQ3_B2_GAIN_WIDTH                     5  /* EQ3_B2_GAIN - [10:6] */
-#define ARIZONA_EQ3_B3_GAIN_MASK                 0x003E  /* EQ3_B3_GAIN - [5:1] */
-#define ARIZONA_EQ3_B3_GAIN_SHIFT                     1  /* EQ3_B3_GAIN - [5:1] */
-#define ARIZONA_EQ3_B3_GAIN_WIDTH                     5  /* EQ3_B3_GAIN - [5:1] */
-#define ARIZONA_EQ3_ENA                          0x0001  /* EQ3_ENA */
-#define ARIZONA_EQ3_ENA_MASK                     0x0001  /* EQ3_ENA */
-#define ARIZONA_EQ3_ENA_SHIFT                         0  /* EQ3_ENA */
-#define ARIZONA_EQ3_ENA_WIDTH                         1  /* EQ3_ENA */
-
-/*
- * R3645 (0xE3D) - EQ3_2
- */
-#define ARIZONA_EQ3_B4_GAIN_MASK                 0xF800  /* EQ3_B4_GAIN - [15:11] */
-#define ARIZONA_EQ3_B4_GAIN_SHIFT                    11  /* EQ3_B4_GAIN - [15:11] */
-#define ARIZONA_EQ3_B4_GAIN_WIDTH                     5  /* EQ3_B4_GAIN - [15:11] */
-#define ARIZONA_EQ3_B5_GAIN_MASK                 0x07C0  /* EQ3_B5_GAIN - [10:6] */
-#define ARIZONA_EQ3_B5_GAIN_SHIFT                     6  /* EQ3_B5_GAIN - [10:6] */
-#define ARIZONA_EQ3_B5_GAIN_WIDTH                     5  /* EQ3_B5_GAIN - [10:6] */
-#define ARIZONA_EQ3_B1_MODE                      0x0001  /* EQ3_B1_MODE */
-#define ARIZONA_EQ3_B1_MODE_MASK                 0x0001  /* EQ3_B1_MODE */
-#define ARIZONA_EQ3_B1_MODE_SHIFT                     0  /* EQ3_B1_MODE */
-#define ARIZONA_EQ3_B1_MODE_WIDTH                     1  /* EQ3_B1_MODE */
-
-/*
- * R3646 (0xE3E) - EQ3_3
- */
-#define ARIZONA_EQ3_B1_A_MASK                    0xFFFF  /* EQ3_B1_A - [15:0] */
-#define ARIZONA_EQ3_B1_A_SHIFT                        0  /* EQ3_B1_A - [15:0] */
-#define ARIZONA_EQ3_B1_A_WIDTH                       16  /* EQ3_B1_A - [15:0] */
-
-/*
- * R3647 (0xE3F) - EQ3_4
- */
-#define ARIZONA_EQ3_B1_B_MASK                    0xFFFF  /* EQ3_B1_B - [15:0] */
-#define ARIZONA_EQ3_B1_B_SHIFT                        0  /* EQ3_B1_B - [15:0] */
-#define ARIZONA_EQ3_B1_B_WIDTH                       16  /* EQ3_B1_B - [15:0] */
-
-/*
- * R3648 (0xE40) - EQ3_5
- */
-#define ARIZONA_EQ3_B1_PG_MASK                   0xFFFF  /* EQ3_B1_PG - [15:0] */
-#define ARIZONA_EQ3_B1_PG_SHIFT                       0  /* EQ3_B1_PG - [15:0] */
-#define ARIZONA_EQ3_B1_PG_WIDTH                      16  /* EQ3_B1_PG - [15:0] */
-
-/*
- * R3649 (0xE41) - EQ3_6
- */
-#define ARIZONA_EQ3_B2_A_MASK                    0xFFFF  /* EQ3_B2_A - [15:0] */
-#define ARIZONA_EQ3_B2_A_SHIFT                        0  /* EQ3_B2_A - [15:0] */
-#define ARIZONA_EQ3_B2_A_WIDTH                       16  /* EQ3_B2_A - [15:0] */
-
-/*
- * R3650 (0xE42) - EQ3_7
- */
-#define ARIZONA_EQ3_B2_B_MASK                    0xFFFF  /* EQ3_B2_B - [15:0] */
-#define ARIZONA_EQ3_B2_B_SHIFT                        0  /* EQ3_B2_B - [15:0] */
-#define ARIZONA_EQ3_B2_B_WIDTH                       16  /* EQ3_B2_B - [15:0] */
-
-/*
- * R3651 (0xE43) - EQ3_8
- */
-#define ARIZONA_EQ3_B2_C_MASK                    0xFFFF  /* EQ3_B2_C - [15:0] */
-#define ARIZONA_EQ3_B2_C_SHIFT                        0  /* EQ3_B2_C - [15:0] */
-#define ARIZONA_EQ3_B2_C_WIDTH                       16  /* EQ3_B2_C - [15:0] */
-
-/*
- * R3652 (0xE44) - EQ3_9
- */
-#define ARIZONA_EQ3_B2_PG_MASK                   0xFFFF  /* EQ3_B2_PG - [15:0] */
-#define ARIZONA_EQ3_B2_PG_SHIFT                       0  /* EQ3_B2_PG - [15:0] */
-#define ARIZONA_EQ3_B2_PG_WIDTH                      16  /* EQ3_B2_PG - [15:0] */
-
-/*
- * R3653 (0xE45) - EQ3_10
- */
-#define ARIZONA_EQ3_B3_A_MASK                    0xFFFF  /* EQ3_B3_A - [15:0] */
-#define ARIZONA_EQ3_B3_A_SHIFT                        0  /* EQ3_B3_A - [15:0] */
-#define ARIZONA_EQ3_B3_A_WIDTH                       16  /* EQ3_B3_A - [15:0] */
-
-/*
- * R3654 (0xE46) - EQ3_11
- */
-#define ARIZONA_EQ3_B3_B_MASK                    0xFFFF  /* EQ3_B3_B - [15:0] */
-#define ARIZONA_EQ3_B3_B_SHIFT                        0  /* EQ3_B3_B - [15:0] */
-#define ARIZONA_EQ3_B3_B_WIDTH                       16  /* EQ3_B3_B - [15:0] */
-
-/*
- * R3655 (0xE47) - EQ3_12
- */
-#define ARIZONA_EQ3_B3_C_MASK                    0xFFFF  /* EQ3_B3_C - [15:0] */
-#define ARIZONA_EQ3_B3_C_SHIFT                        0  /* EQ3_B3_C - [15:0] */
-#define ARIZONA_EQ3_B3_C_WIDTH                       16  /* EQ3_B3_C - [15:0] */
-
-/*
- * R3656 (0xE48) - EQ3_13
- */
-#define ARIZONA_EQ3_B3_PG_MASK                   0xFFFF  /* EQ3_B3_PG - [15:0] */
-#define ARIZONA_EQ3_B3_PG_SHIFT                       0  /* EQ3_B3_PG - [15:0] */
-#define ARIZONA_EQ3_B3_PG_WIDTH                      16  /* EQ3_B3_PG - [15:0] */
-
-/*
- * R3657 (0xE49) - EQ3_14
- */
-#define ARIZONA_EQ3_B4_A_MASK                    0xFFFF  /* EQ3_B4_A - [15:0] */
-#define ARIZONA_EQ3_B4_A_SHIFT                        0  /* EQ3_B4_A - [15:0] */
-#define ARIZONA_EQ3_B4_A_WIDTH                       16  /* EQ3_B4_A - [15:0] */
-
-/*
- * R3658 (0xE4A) - EQ3_15
- */
-#define ARIZONA_EQ3_B4_B_MASK                    0xFFFF  /* EQ3_B4_B - [15:0] */
-#define ARIZONA_EQ3_B4_B_SHIFT                        0  /* EQ3_B4_B - [15:0] */
-#define ARIZONA_EQ3_B4_B_WIDTH                       16  /* EQ3_B4_B - [15:0] */
-
-/*
- * R3659 (0xE4B) - EQ3_16
- */
-#define ARIZONA_EQ3_B4_C_MASK                    0xFFFF  /* EQ3_B4_C - [15:0] */
-#define ARIZONA_EQ3_B4_C_SHIFT                        0  /* EQ3_B4_C - [15:0] */
-#define ARIZONA_EQ3_B4_C_WIDTH                       16  /* EQ3_B4_C - [15:0] */
-
-/*
- * R3660 (0xE4C) - EQ3_17
- */
-#define ARIZONA_EQ3_B4_PG_MASK                   0xFFFF  /* EQ3_B4_PG - [15:0] */
-#define ARIZONA_EQ3_B4_PG_SHIFT                       0  /* EQ3_B4_PG - [15:0] */
-#define ARIZONA_EQ3_B4_PG_WIDTH                      16  /* EQ3_B4_PG - [15:0] */
-
-/*
- * R3661 (0xE4D) - EQ3_18
- */
-#define ARIZONA_EQ3_B5_A_MASK                    0xFFFF  /* EQ3_B5_A - [15:0] */
-#define ARIZONA_EQ3_B5_A_SHIFT                        0  /* EQ3_B5_A - [15:0] */
-#define ARIZONA_EQ3_B5_A_WIDTH                       16  /* EQ3_B5_A - [15:0] */
-
-/*
- * R3662 (0xE4E) - EQ3_19
- */
-#define ARIZONA_EQ3_B5_B_MASK                    0xFFFF  /* EQ3_B5_B - [15:0] */
-#define ARIZONA_EQ3_B5_B_SHIFT                        0  /* EQ3_B5_B - [15:0] */
-#define ARIZONA_EQ3_B5_B_WIDTH                       16  /* EQ3_B5_B - [15:0] */
-
-/*
- * R3663 (0xE4F) - EQ3_20
- */
-#define ARIZONA_EQ3_B5_PG_MASK                   0xFFFF  /* EQ3_B5_PG - [15:0] */
-#define ARIZONA_EQ3_B5_PG_SHIFT                       0  /* EQ3_B5_PG - [15:0] */
-#define ARIZONA_EQ3_B5_PG_WIDTH                      16  /* EQ3_B5_PG - [15:0] */
-
-/*
- * R3664 (0xE50) - EQ3_21
- */
-#define ARIZONA_EQ3_B1_C_MASK                    0xFFFF  /* EQ3_B1_C - [15:0] */
-#define ARIZONA_EQ3_B1_C_SHIFT                        0  /* EQ3_B1_C - [15:0] */
-#define ARIZONA_EQ3_B1_C_WIDTH                       16  /* EQ3_B1_C - [15:0] */
-
-/*
- * R3666 (0xE52) - EQ4_1
- */
-#define ARIZONA_EQ4_B1_GAIN_MASK                 0xF800  /* EQ4_B1_GAIN - [15:11] */
-#define ARIZONA_EQ4_B1_GAIN_SHIFT                    11  /* EQ4_B1_GAIN - [15:11] */
-#define ARIZONA_EQ4_B1_GAIN_WIDTH                     5  /* EQ4_B1_GAIN - [15:11] */
-#define ARIZONA_EQ4_B2_GAIN_MASK                 0x07C0  /* EQ4_B2_GAIN - [10:6] */
-#define ARIZONA_EQ4_B2_GAIN_SHIFT                     6  /* EQ4_B2_GAIN - [10:6] */
-#define ARIZONA_EQ4_B2_GAIN_WIDTH                     5  /* EQ4_B2_GAIN - [10:6] */
-#define ARIZONA_EQ4_B3_GAIN_MASK                 0x003E  /* EQ4_B3_GAIN - [5:1] */
-#define ARIZONA_EQ4_B3_GAIN_SHIFT                     1  /* EQ4_B3_GAIN - [5:1] */
-#define ARIZONA_EQ4_B3_GAIN_WIDTH                     5  /* EQ4_B3_GAIN - [5:1] */
-#define ARIZONA_EQ4_ENA                          0x0001  /* EQ4_ENA */
-#define ARIZONA_EQ4_ENA_MASK                     0x0001  /* EQ4_ENA */
-#define ARIZONA_EQ4_ENA_SHIFT                         0  /* EQ4_ENA */
-#define ARIZONA_EQ4_ENA_WIDTH                         1  /* EQ4_ENA */
-
-/*
- * R3667 (0xE53) - EQ4_2
- */
-#define ARIZONA_EQ4_B4_GAIN_MASK                 0xF800  /* EQ4_B4_GAIN - [15:11] */
-#define ARIZONA_EQ4_B4_GAIN_SHIFT                    11  /* EQ4_B4_GAIN - [15:11] */
-#define ARIZONA_EQ4_B4_GAIN_WIDTH                     5  /* EQ4_B4_GAIN - [15:11] */
-#define ARIZONA_EQ4_B5_GAIN_MASK                 0x07C0  /* EQ4_B5_GAIN - [10:6] */
-#define ARIZONA_EQ4_B5_GAIN_SHIFT                     6  /* EQ4_B5_GAIN - [10:6] */
-#define ARIZONA_EQ4_B5_GAIN_WIDTH                     5  /* EQ4_B5_GAIN - [10:6] */
-#define ARIZONA_EQ4_B1_MODE                      0x0001  /* EQ4_B1_MODE */
-#define ARIZONA_EQ4_B1_MODE_MASK                 0x0001  /* EQ4_B1_MODE */
-#define ARIZONA_EQ4_B1_MODE_SHIFT                     0  /* EQ4_B1_MODE */
-#define ARIZONA_EQ4_B1_MODE_WIDTH                     1  /* EQ4_B1_MODE */
-
-/*
- * R3668 (0xE54) - EQ4_3
- */
-#define ARIZONA_EQ4_B1_A_MASK                    0xFFFF  /* EQ4_B1_A - [15:0] */
-#define ARIZONA_EQ4_B1_A_SHIFT                        0  /* EQ4_B1_A - [15:0] */
-#define ARIZONA_EQ4_B1_A_WIDTH                       16  /* EQ4_B1_A - [15:0] */
-
-/*
- * R3669 (0xE55) - EQ4_4
- */
-#define ARIZONA_EQ4_B1_B_MASK                    0xFFFF  /* EQ4_B1_B - [15:0] */
-#define ARIZONA_EQ4_B1_B_SHIFT                        0  /* EQ4_B1_B - [15:0] */
-#define ARIZONA_EQ4_B1_B_WIDTH                       16  /* EQ4_B1_B - [15:0] */
-
-/*
- * R3670 (0xE56) - EQ4_5
- */
-#define ARIZONA_EQ4_B1_PG_MASK                   0xFFFF  /* EQ4_B1_PG - [15:0] */
-#define ARIZONA_EQ4_B1_PG_SHIFT                       0  /* EQ4_B1_PG - [15:0] */
-#define ARIZONA_EQ4_B1_PG_WIDTH                      16  /* EQ4_B1_PG - [15:0] */
-
-/*
- * R3671 (0xE57) - EQ4_6
- */
-#define ARIZONA_EQ4_B2_A_MASK                    0xFFFF  /* EQ4_B2_A - [15:0] */
-#define ARIZONA_EQ4_B2_A_SHIFT                        0  /* EQ4_B2_A - [15:0] */
-#define ARIZONA_EQ4_B2_A_WIDTH                       16  /* EQ4_B2_A - [15:0] */
-
-/*
- * R3672 (0xE58) - EQ4_7
- */
-#define ARIZONA_EQ4_B2_B_MASK                    0xFFFF  /* EQ4_B2_B - [15:0] */
-#define ARIZONA_EQ4_B2_B_SHIFT                        0  /* EQ4_B2_B - [15:0] */
-#define ARIZONA_EQ4_B2_B_WIDTH                       16  /* EQ4_B2_B - [15:0] */
-
-/*
- * R3673 (0xE59) - EQ4_8
- */
-#define ARIZONA_EQ4_B2_C_MASK                    0xFFFF  /* EQ4_B2_C - [15:0] */
-#define ARIZONA_EQ4_B2_C_SHIFT                        0  /* EQ4_B2_C - [15:0] */
-#define ARIZONA_EQ4_B2_C_WIDTH                       16  /* EQ4_B2_C - [15:0] */
-
-/*
- * R3674 (0xE5A) - EQ4_9
- */
-#define ARIZONA_EQ4_B2_PG_MASK                   0xFFFF  /* EQ4_B2_PG - [15:0] */
-#define ARIZONA_EQ4_B2_PG_SHIFT                       0  /* EQ4_B2_PG - [15:0] */
-#define ARIZONA_EQ4_B2_PG_WIDTH                      16  /* EQ4_B2_PG - [15:0] */
-
-/*
- * R3675 (0xE5B) - EQ4_10
- */
-#define ARIZONA_EQ4_B3_A_MASK                    0xFFFF  /* EQ4_B3_A - [15:0] */
-#define ARIZONA_EQ4_B3_A_SHIFT                        0  /* EQ4_B3_A - [15:0] */
-#define ARIZONA_EQ4_B3_A_WIDTH                       16  /* EQ4_B3_A - [15:0] */
-
-/*
- * R3676 (0xE5C) - EQ4_11
- */
-#define ARIZONA_EQ4_B3_B_MASK                    0xFFFF  /* EQ4_B3_B - [15:0] */
-#define ARIZONA_EQ4_B3_B_SHIFT                        0  /* EQ4_B3_B - [15:0] */
-#define ARIZONA_EQ4_B3_B_WIDTH                       16  /* EQ4_B3_B - [15:0] */
-
-/*
- * R3677 (0xE5D) - EQ4_12
- */
-#define ARIZONA_EQ4_B3_C_MASK                    0xFFFF  /* EQ4_B3_C - [15:0] */
-#define ARIZONA_EQ4_B3_C_SHIFT                        0  /* EQ4_B3_C - [15:0] */
-#define ARIZONA_EQ4_B3_C_WIDTH                       16  /* EQ4_B3_C - [15:0] */
-
-/*
- * R3678 (0xE5E) - EQ4_13
- */
-#define ARIZONA_EQ4_B3_PG_MASK                   0xFFFF  /* EQ4_B3_PG - [15:0] */
-#define ARIZONA_EQ4_B3_PG_SHIFT                       0  /* EQ4_B3_PG - [15:0] */
-#define ARIZONA_EQ4_B3_PG_WIDTH                      16  /* EQ4_B3_PG - [15:0] */
-
-/*
- * R3679 (0xE5F) - EQ4_14
- */
-#define ARIZONA_EQ4_B4_A_MASK                    0xFFFF  /* EQ4_B4_A - [15:0] */
-#define ARIZONA_EQ4_B4_A_SHIFT                        0  /* EQ4_B4_A - [15:0] */
-#define ARIZONA_EQ4_B4_A_WIDTH                       16  /* EQ4_B4_A - [15:0] */
-
-/*
- * R3680 (0xE60) - EQ4_15
- */
-#define ARIZONA_EQ4_B4_B_MASK                    0xFFFF  /* EQ4_B4_B - [15:0] */
-#define ARIZONA_EQ4_B4_B_SHIFT                        0  /* EQ4_B4_B - [15:0] */
-#define ARIZONA_EQ4_B4_B_WIDTH                       16  /* EQ4_B4_B - [15:0] */
-
-/*
- * R3681 (0xE61) - EQ4_16
- */
-#define ARIZONA_EQ4_B4_C_MASK                    0xFFFF  /* EQ4_B4_C - [15:0] */
-#define ARIZONA_EQ4_B4_C_SHIFT                        0  /* EQ4_B4_C - [15:0] */
-#define ARIZONA_EQ4_B4_C_WIDTH                       16  /* EQ4_B4_C - [15:0] */
-
-/*
- * R3682 (0xE62) - EQ4_17
- */
-#define ARIZONA_EQ4_B4_PG_MASK                   0xFFFF  /* EQ4_B4_PG - [15:0] */
-#define ARIZONA_EQ4_B4_PG_SHIFT                       0  /* EQ4_B4_PG - [15:0] */
-#define ARIZONA_EQ4_B4_PG_WIDTH                      16  /* EQ4_B4_PG - [15:0] */
-
-/*
- * R3683 (0xE63) - EQ4_18
- */
-#define ARIZONA_EQ4_B5_A_MASK                    0xFFFF  /* EQ4_B5_A - [15:0] */
-#define ARIZONA_EQ4_B5_A_SHIFT                        0  /* EQ4_B5_A - [15:0] */
-#define ARIZONA_EQ4_B5_A_WIDTH                       16  /* EQ4_B5_A - [15:0] */
-
-/*
- * R3684 (0xE64) - EQ4_19
- */
-#define ARIZONA_EQ4_B5_B_MASK                    0xFFFF  /* EQ4_B5_B - [15:0] */
-#define ARIZONA_EQ4_B5_B_SHIFT                        0  /* EQ4_B5_B - [15:0] */
-#define ARIZONA_EQ4_B5_B_WIDTH                       16  /* EQ4_B5_B - [15:0] */
-
-/*
- * R3685 (0xE65) - EQ4_20
- */
-#define ARIZONA_EQ4_B5_PG_MASK                   0xFFFF  /* EQ4_B5_PG - [15:0] */
-#define ARIZONA_EQ4_B5_PG_SHIFT                       0  /* EQ4_B5_PG - [15:0] */
-#define ARIZONA_EQ4_B5_PG_WIDTH                      16  /* EQ4_B5_PG - [15:0] */
-
-/*
- * R3686 (0xE66) - EQ4_21
- */
-#define ARIZONA_EQ4_B1_C_MASK                    0xFFFF  /* EQ4_B1_C - [15:0] */
-#define ARIZONA_EQ4_B1_C_SHIFT                        0  /* EQ4_B1_C - [15:0] */
-#define ARIZONA_EQ4_B1_C_WIDTH                       16  /* EQ4_B1_C - [15:0] */
-
-/*
- * R3712 (0xE80) - DRC1 ctrl1
- */
-#define ARIZONA_DRC1_SIG_DET_RMS_MASK            0xF800  /* DRC1_SIG_DET_RMS - [15:11] */
-#define ARIZONA_DRC1_SIG_DET_RMS_SHIFT               11  /* DRC1_SIG_DET_RMS - [15:11] */
-#define ARIZONA_DRC1_SIG_DET_RMS_WIDTH                5  /* DRC1_SIG_DET_RMS - [15:11] */
-#define ARIZONA_DRC1_SIG_DET_PK_MASK             0x0600  /* DRC1_SIG_DET_PK - [10:9] */
-#define ARIZONA_DRC1_SIG_DET_PK_SHIFT                 9  /* DRC1_SIG_DET_PK - [10:9] */
-#define ARIZONA_DRC1_SIG_DET_PK_WIDTH                 2  /* DRC1_SIG_DET_PK - [10:9] */
-#define ARIZONA_DRC1_NG_ENA                      0x0100  /* DRC1_NG_ENA */
-#define ARIZONA_DRC1_NG_ENA_MASK                 0x0100  /* DRC1_NG_ENA */
-#define ARIZONA_DRC1_NG_ENA_SHIFT                     8  /* DRC1_NG_ENA */
-#define ARIZONA_DRC1_NG_ENA_WIDTH                     1  /* DRC1_NG_ENA */
-#define ARIZONA_DRC1_SIG_DET_MODE                0x0080  /* DRC1_SIG_DET_MODE */
-#define ARIZONA_DRC1_SIG_DET_MODE_MASK           0x0080  /* DRC1_SIG_DET_MODE */
-#define ARIZONA_DRC1_SIG_DET_MODE_SHIFT               7  /* DRC1_SIG_DET_MODE */
-#define ARIZONA_DRC1_SIG_DET_MODE_WIDTH               1  /* DRC1_SIG_DET_MODE */
-#define ARIZONA_DRC1_SIG_DET                     0x0040  /* DRC1_SIG_DET */
-#define ARIZONA_DRC1_SIG_DET_MASK                0x0040  /* DRC1_SIG_DET */
-#define ARIZONA_DRC1_SIG_DET_SHIFT                    6  /* DRC1_SIG_DET */
-#define ARIZONA_DRC1_SIG_DET_WIDTH                    1  /* DRC1_SIG_DET */
-#define ARIZONA_DRC1_KNEE2_OP_ENA                0x0020  /* DRC1_KNEE2_OP_ENA */
-#define ARIZONA_DRC1_KNEE2_OP_ENA_MASK           0x0020  /* DRC1_KNEE2_OP_ENA */
-#define ARIZONA_DRC1_KNEE2_OP_ENA_SHIFT               5  /* DRC1_KNEE2_OP_ENA */
-#define ARIZONA_DRC1_KNEE2_OP_ENA_WIDTH               1  /* DRC1_KNEE2_OP_ENA */
-#define ARIZONA_DRC1_QR                          0x0010  /* DRC1_QR */
-#define ARIZONA_DRC1_QR_MASK                     0x0010  /* DRC1_QR */
-#define ARIZONA_DRC1_QR_SHIFT                         4  /* DRC1_QR */
-#define ARIZONA_DRC1_QR_WIDTH                         1  /* DRC1_QR */
-#define ARIZONA_DRC1_ANTICLIP                    0x0008  /* DRC1_ANTICLIP */
-#define ARIZONA_DRC1_ANTICLIP_MASK               0x0008  /* DRC1_ANTICLIP */
-#define ARIZONA_DRC1_ANTICLIP_SHIFT                   3  /* DRC1_ANTICLIP */
-#define ARIZONA_DRC1_ANTICLIP_WIDTH                   1  /* DRC1_ANTICLIP */
-#define ARIZONA_DRC1L_ENA                        0x0002  /* DRC1L_ENA */
-#define ARIZONA_DRC1L_ENA_MASK                   0x0002  /* DRC1L_ENA */
-#define ARIZONA_DRC1L_ENA_SHIFT                       1  /* DRC1L_ENA */
-#define ARIZONA_DRC1L_ENA_WIDTH                       1  /* DRC1L_ENA */
-#define ARIZONA_DRC1R_ENA                        0x0001  /* DRC1R_ENA */
-#define ARIZONA_DRC1R_ENA_MASK                   0x0001  /* DRC1R_ENA */
-#define ARIZONA_DRC1R_ENA_SHIFT                       0  /* DRC1R_ENA */
-#define ARIZONA_DRC1R_ENA_WIDTH                       1  /* DRC1R_ENA */
-
-/*
- * R3713 (0xE81) - DRC1 ctrl2
- */
-#define ARIZONA_DRC1_ATK_MASK                    0x1E00  /* DRC1_ATK - [12:9] */
-#define ARIZONA_DRC1_ATK_SHIFT                        9  /* DRC1_ATK - [12:9] */
-#define ARIZONA_DRC1_ATK_WIDTH                        4  /* DRC1_ATK - [12:9] */
-#define ARIZONA_DRC1_DCY_MASK                    0x01E0  /* DRC1_DCY - [8:5] */
-#define ARIZONA_DRC1_DCY_SHIFT                        5  /* DRC1_DCY - [8:5] */
-#define ARIZONA_DRC1_DCY_WIDTH                        4  /* DRC1_DCY - [8:5] */
-#define ARIZONA_DRC1_MINGAIN_MASK                0x001C  /* DRC1_MINGAIN - [4:2] */
-#define ARIZONA_DRC1_MINGAIN_SHIFT                    2  /* DRC1_MINGAIN - [4:2] */
-#define ARIZONA_DRC1_MINGAIN_WIDTH                    3  /* DRC1_MINGAIN - [4:2] */
-#define ARIZONA_DRC1_MAXGAIN_MASK                0x0003  /* DRC1_MAXGAIN - [1:0] */
-#define ARIZONA_DRC1_MAXGAIN_SHIFT                    0  /* DRC1_MAXGAIN - [1:0] */
-#define ARIZONA_DRC1_MAXGAIN_WIDTH                    2  /* DRC1_MAXGAIN - [1:0] */
-
-/*
- * R3714 (0xE82) - DRC1 ctrl3
- */
-#define ARIZONA_DRC1_NG_MINGAIN_MASK             0xF000  /* DRC1_NG_MINGAIN - [15:12] */
-#define ARIZONA_DRC1_NG_MINGAIN_SHIFT                12  /* DRC1_NG_MINGAIN - [15:12] */
-#define ARIZONA_DRC1_NG_MINGAIN_WIDTH                 4  /* DRC1_NG_MINGAIN - [15:12] */
-#define ARIZONA_DRC1_NG_EXP_MASK                 0x0C00  /* DRC1_NG_EXP - [11:10] */
-#define ARIZONA_DRC1_NG_EXP_SHIFT                    10  /* DRC1_NG_EXP - [11:10] */
-#define ARIZONA_DRC1_NG_EXP_WIDTH                     2  /* DRC1_NG_EXP - [11:10] */
-#define ARIZONA_DRC1_QR_THR_MASK                 0x0300  /* DRC1_QR_THR - [9:8] */
-#define ARIZONA_DRC1_QR_THR_SHIFT                     8  /* DRC1_QR_THR - [9:8] */
-#define ARIZONA_DRC1_QR_THR_WIDTH                     2  /* DRC1_QR_THR - [9:8] */
-#define ARIZONA_DRC1_QR_DCY_MASK                 0x00C0  /* DRC1_QR_DCY - [7:6] */
-#define ARIZONA_DRC1_QR_DCY_SHIFT                     6  /* DRC1_QR_DCY - [7:6] */
-#define ARIZONA_DRC1_QR_DCY_WIDTH                     2  /* DRC1_QR_DCY - [7:6] */
-#define ARIZONA_DRC1_HI_COMP_MASK                0x0038  /* DRC1_HI_COMP - [5:3] */
-#define ARIZONA_DRC1_HI_COMP_SHIFT                    3  /* DRC1_HI_COMP - [5:3] */
-#define ARIZONA_DRC1_HI_COMP_WIDTH                    3  /* DRC1_HI_COMP - [5:3] */
-#define ARIZONA_DRC1_LO_COMP_MASK                0x0007  /* DRC1_LO_COMP - [2:0] */
-#define ARIZONA_DRC1_LO_COMP_SHIFT                    0  /* DRC1_LO_COMP - [2:0] */
-#define ARIZONA_DRC1_LO_COMP_WIDTH                    3  /* DRC1_LO_COMP - [2:0] */
-
-/*
- * R3715 (0xE83) - DRC1 ctrl4
- */
-#define ARIZONA_DRC1_KNEE_IP_MASK                0x07E0  /* DRC1_KNEE_IP - [10:5] */
-#define ARIZONA_DRC1_KNEE_IP_SHIFT                    5  /* DRC1_KNEE_IP - [10:5] */
-#define ARIZONA_DRC1_KNEE_IP_WIDTH                    6  /* DRC1_KNEE_IP - [10:5] */
-#define ARIZONA_DRC1_KNEE_OP_MASK                0x001F  /* DRC1_KNEE_OP - [4:0] */
-#define ARIZONA_DRC1_KNEE_OP_SHIFT                    0  /* DRC1_KNEE_OP - [4:0] */
-#define ARIZONA_DRC1_KNEE_OP_WIDTH                    5  /* DRC1_KNEE_OP - [4:0] */
-
-/*
- * R3716 (0xE84) - DRC1 ctrl5
- */
-#define ARIZONA_DRC1_KNEE2_IP_MASK               0x03E0  /* DRC1_KNEE2_IP - [9:5] */
-#define ARIZONA_DRC1_KNEE2_IP_SHIFT                   5  /* DRC1_KNEE2_IP - [9:5] */
-#define ARIZONA_DRC1_KNEE2_IP_WIDTH                   5  /* DRC1_KNEE2_IP - [9:5] */
-#define ARIZONA_DRC1_KNEE2_OP_MASK               0x001F  /* DRC1_KNEE2_OP - [4:0] */
-#define ARIZONA_DRC1_KNEE2_OP_SHIFT                   0  /* DRC1_KNEE2_OP - [4:0] */
-#define ARIZONA_DRC1_KNEE2_OP_WIDTH                   5  /* DRC1_KNEE2_OP - [4:0] */
-
-/*
- * R3721 (0xE89) - DRC2 ctrl1
- */
-#define ARIZONA_DRC2_SIG_DET_RMS_MASK            0xF800  /* DRC2_SIG_DET_RMS - [15:11] */
-#define ARIZONA_DRC2_SIG_DET_RMS_SHIFT               11  /* DRC2_SIG_DET_RMS - [15:11] */
-#define ARIZONA_DRC2_SIG_DET_RMS_WIDTH                5  /* DRC2_SIG_DET_RMS - [15:11] */
-#define ARIZONA_DRC2_SIG_DET_PK_MASK             0x0600  /* DRC2_SIG_DET_PK - [10:9] */
-#define ARIZONA_DRC2_SIG_DET_PK_SHIFT                 9  /* DRC2_SIG_DET_PK - [10:9] */
-#define ARIZONA_DRC2_SIG_DET_PK_WIDTH                 2  /* DRC2_SIG_DET_PK - [10:9] */
-#define ARIZONA_DRC2_NG_ENA                      0x0100  /* DRC2_NG_ENA */
-#define ARIZONA_DRC2_NG_ENA_MASK                 0x0100  /* DRC2_NG_ENA */
-#define ARIZONA_DRC2_NG_ENA_SHIFT                     8  /* DRC2_NG_ENA */
-#define ARIZONA_DRC2_NG_ENA_WIDTH                     1  /* DRC2_NG_ENA */
-#define ARIZONA_DRC2_SIG_DET_MODE                0x0080  /* DRC2_SIG_DET_MODE */
-#define ARIZONA_DRC2_SIG_DET_MODE_MASK           0x0080  /* DRC2_SIG_DET_MODE */
-#define ARIZONA_DRC2_SIG_DET_MODE_SHIFT               7  /* DRC2_SIG_DET_MODE */
-#define ARIZONA_DRC2_SIG_DET_MODE_WIDTH               1  /* DRC2_SIG_DET_MODE */
-#define ARIZONA_DRC2_SIG_DET                     0x0040  /* DRC2_SIG_DET */
-#define ARIZONA_DRC2_SIG_DET_MASK                0x0040  /* DRC2_SIG_DET */
-#define ARIZONA_DRC2_SIG_DET_SHIFT                    6  /* DRC2_SIG_DET */
-#define ARIZONA_DRC2_SIG_DET_WIDTH                    1  /* DRC2_SIG_DET */
-#define ARIZONA_DRC2_KNEE2_OP_ENA                0x0020  /* DRC2_KNEE2_OP_ENA */
-#define ARIZONA_DRC2_KNEE2_OP_ENA_MASK           0x0020  /* DRC2_KNEE2_OP_ENA */
-#define ARIZONA_DRC2_KNEE2_OP_ENA_SHIFT               5  /* DRC2_KNEE2_OP_ENA */
-#define ARIZONA_DRC2_KNEE2_OP_ENA_WIDTH               1  /* DRC2_KNEE2_OP_ENA */
-#define ARIZONA_DRC2_QR                          0x0010  /* DRC2_QR */
-#define ARIZONA_DRC2_QR_MASK                     0x0010  /* DRC2_QR */
-#define ARIZONA_DRC2_QR_SHIFT                         4  /* DRC2_QR */
-#define ARIZONA_DRC2_QR_WIDTH                         1  /* DRC2_QR */
-#define ARIZONA_DRC2_ANTICLIP                    0x0008  /* DRC2_ANTICLIP */
-#define ARIZONA_DRC2_ANTICLIP_MASK               0x0008  /* DRC2_ANTICLIP */
-#define ARIZONA_DRC2_ANTICLIP_SHIFT                   3  /* DRC2_ANTICLIP */
-#define ARIZONA_DRC2_ANTICLIP_WIDTH                   1  /* DRC2_ANTICLIP */
-#define ARIZONA_DRC2L_ENA                        0x0002  /* DRC2L_ENA */
-#define ARIZONA_DRC2L_ENA_MASK                   0x0002  /* DRC2L_ENA */
-#define ARIZONA_DRC2L_ENA_SHIFT                       1  /* DRC2L_ENA */
-#define ARIZONA_DRC2L_ENA_WIDTH                       1  /* DRC2L_ENA */
-#define ARIZONA_DRC2R_ENA                        0x0001  /* DRC2R_ENA */
-#define ARIZONA_DRC2R_ENA_MASK                   0x0001  /* DRC2R_ENA */
-#define ARIZONA_DRC2R_ENA_SHIFT                       0  /* DRC2R_ENA */
-#define ARIZONA_DRC2R_ENA_WIDTH                       1  /* DRC2R_ENA */
-
-/*
- * R3722 (0xE8A) - DRC2 ctrl2
- */
-#define ARIZONA_DRC2_ATK_MASK                    0x1E00  /* DRC2_ATK - [12:9] */
-#define ARIZONA_DRC2_ATK_SHIFT                        9  /* DRC2_ATK - [12:9] */
-#define ARIZONA_DRC2_ATK_WIDTH                        4  /* DRC2_ATK - [12:9] */
-#define ARIZONA_DRC2_DCY_MASK                    0x01E0  /* DRC2_DCY - [8:5] */
-#define ARIZONA_DRC2_DCY_SHIFT                        5  /* DRC2_DCY - [8:5] */
-#define ARIZONA_DRC2_DCY_WIDTH                        4  /* DRC2_DCY - [8:5] */
-#define ARIZONA_DRC2_MINGAIN_MASK                0x001C  /* DRC2_MINGAIN - [4:2] */
-#define ARIZONA_DRC2_MINGAIN_SHIFT                    2  /* DRC2_MINGAIN - [4:2] */
-#define ARIZONA_DRC2_MINGAIN_WIDTH                    3  /* DRC2_MINGAIN - [4:2] */
-#define ARIZONA_DRC2_MAXGAIN_MASK                0x0003  /* DRC2_MAXGAIN - [1:0] */
-#define ARIZONA_DRC2_MAXGAIN_SHIFT                    0  /* DRC2_MAXGAIN - [1:0] */
-#define ARIZONA_DRC2_MAXGAIN_WIDTH                    2  /* DRC2_MAXGAIN - [1:0] */
-
-/*
- * R3723 (0xE8B) - DRC2 ctrl3
- */
-#define ARIZONA_DRC2_NG_MINGAIN_MASK             0xF000  /* DRC2_NG_MINGAIN - [15:12] */
-#define ARIZONA_DRC2_NG_MINGAIN_SHIFT                12  /* DRC2_NG_MINGAIN - [15:12] */
-#define ARIZONA_DRC2_NG_MINGAIN_WIDTH                 4  /* DRC2_NG_MINGAIN - [15:12] */
-#define ARIZONA_DRC2_NG_EXP_MASK                 0x0C00  /* DRC2_NG_EXP - [11:10] */
-#define ARIZONA_DRC2_NG_EXP_SHIFT                    10  /* DRC2_NG_EXP - [11:10] */
-#define ARIZONA_DRC2_NG_EXP_WIDTH                     2  /* DRC2_NG_EXP - [11:10] */
-#define ARIZONA_DRC2_QR_THR_MASK                 0x0300  /* DRC2_QR_THR - [9:8] */
-#define ARIZONA_DRC2_QR_THR_SHIFT                     8  /* DRC2_QR_THR - [9:8] */
-#define ARIZONA_DRC2_QR_THR_WIDTH                     2  /* DRC2_QR_THR - [9:8] */
-#define ARIZONA_DRC2_QR_DCY_MASK                 0x00C0  /* DRC2_QR_DCY - [7:6] */
-#define ARIZONA_DRC2_QR_DCY_SHIFT                     6  /* DRC2_QR_DCY - [7:6] */
-#define ARIZONA_DRC2_QR_DCY_WIDTH                     2  /* DRC2_QR_DCY - [7:6] */
-#define ARIZONA_DRC2_HI_COMP_MASK                0x0038  /* DRC2_HI_COMP - [5:3] */
-#define ARIZONA_DRC2_HI_COMP_SHIFT                    3  /* DRC2_HI_COMP - [5:3] */
-#define ARIZONA_DRC2_HI_COMP_WIDTH                    3  /* DRC2_HI_COMP - [5:3] */
-#define ARIZONA_DRC2_LO_COMP_MASK                0x0007  /* DRC2_LO_COMP - [2:0] */
-#define ARIZONA_DRC2_LO_COMP_SHIFT                    0  /* DRC2_LO_COMP - [2:0] */
-#define ARIZONA_DRC2_LO_COMP_WIDTH                    3  /* DRC2_LO_COMP - [2:0] */
-
-/*
- * R3724 (0xE8C) - DRC2 ctrl4
- */
-#define ARIZONA_DRC2_KNEE_IP_MASK                0x07E0  /* DRC2_KNEE_IP - [10:5] */
-#define ARIZONA_DRC2_KNEE_IP_SHIFT                    5  /* DRC2_KNEE_IP - [10:5] */
-#define ARIZONA_DRC2_KNEE_IP_WIDTH                    6  /* DRC2_KNEE_IP - [10:5] */
-#define ARIZONA_DRC2_KNEE_OP_MASK                0x001F  /* DRC2_KNEE_OP - [4:0] */
-#define ARIZONA_DRC2_KNEE_OP_SHIFT                    0  /* DRC2_KNEE_OP - [4:0] */
-#define ARIZONA_DRC2_KNEE_OP_WIDTH                    5  /* DRC2_KNEE_OP - [4:0] */
-
-/*
- * R3725 (0xE8D) - DRC2 ctrl5
- */
-#define ARIZONA_DRC2_KNEE2_IP_MASK               0x03E0  /* DRC2_KNEE2_IP - [9:5] */
-#define ARIZONA_DRC2_KNEE2_IP_SHIFT                   5  /* DRC2_KNEE2_IP - [9:5] */
-#define ARIZONA_DRC2_KNEE2_IP_WIDTH                   5  /* DRC2_KNEE2_IP - [9:5] */
-#define ARIZONA_DRC2_KNEE2_OP_MASK               0x001F  /* DRC2_KNEE2_OP - [4:0] */
-#define ARIZONA_DRC2_KNEE2_OP_SHIFT                   0  /* DRC2_KNEE2_OP - [4:0] */
-#define ARIZONA_DRC2_KNEE2_OP_WIDTH                   5  /* DRC2_KNEE2_OP - [4:0] */
-
-/*
- * R3776 (0xEC0) - HPLPF1_1
- */
-#define ARIZONA_LHPF1_MODE                       0x0002  /* LHPF1_MODE */
-#define ARIZONA_LHPF1_MODE_MASK                  0x0002  /* LHPF1_MODE */
-#define ARIZONA_LHPF1_MODE_SHIFT                      1  /* LHPF1_MODE */
-#define ARIZONA_LHPF1_MODE_WIDTH                      1  /* LHPF1_MODE */
-#define ARIZONA_LHPF1_ENA                        0x0001  /* LHPF1_ENA */
-#define ARIZONA_LHPF1_ENA_MASK                   0x0001  /* LHPF1_ENA */
-#define ARIZONA_LHPF1_ENA_SHIFT                       0  /* LHPF1_ENA */
-#define ARIZONA_LHPF1_ENA_WIDTH                       1  /* LHPF1_ENA */
-
-/*
- * R3777 (0xEC1) - HPLPF1_2
- */
-#define ARIZONA_LHPF1_COEFF_MASK                 0xFFFF  /* LHPF1_COEFF - [15:0] */
-#define ARIZONA_LHPF1_COEFF_SHIFT                     0  /* LHPF1_COEFF - [15:0] */
-#define ARIZONA_LHPF1_COEFF_WIDTH                    16  /* LHPF1_COEFF - [15:0] */
-
-/*
- * R3780 (0xEC4) - HPLPF2_1
- */
-#define ARIZONA_LHPF2_MODE                       0x0002  /* LHPF2_MODE */
-#define ARIZONA_LHPF2_MODE_MASK                  0x0002  /* LHPF2_MODE */
-#define ARIZONA_LHPF2_MODE_SHIFT                      1  /* LHPF2_MODE */
-#define ARIZONA_LHPF2_MODE_WIDTH                      1  /* LHPF2_MODE */
-#define ARIZONA_LHPF2_ENA                        0x0001  /* LHPF2_ENA */
-#define ARIZONA_LHPF2_ENA_MASK                   0x0001  /* LHPF2_ENA */
-#define ARIZONA_LHPF2_ENA_SHIFT                       0  /* LHPF2_ENA */
-#define ARIZONA_LHPF2_ENA_WIDTH                       1  /* LHPF2_ENA */
-
-/*
- * R3781 (0xEC5) - HPLPF2_2
- */
-#define ARIZONA_LHPF2_COEFF_MASK                 0xFFFF  /* LHPF2_COEFF - [15:0] */
-#define ARIZONA_LHPF2_COEFF_SHIFT                     0  /* LHPF2_COEFF - [15:0] */
-#define ARIZONA_LHPF2_COEFF_WIDTH                    16  /* LHPF2_COEFF - [15:0] */
-
-/*
- * R3784 (0xEC8) - HPLPF3_1
- */
-#define ARIZONA_LHPF3_MODE                       0x0002  /* LHPF3_MODE */
-#define ARIZONA_LHPF3_MODE_MASK                  0x0002  /* LHPF3_MODE */
-#define ARIZONA_LHPF3_MODE_SHIFT                      1  /* LHPF3_MODE */
-#define ARIZONA_LHPF3_MODE_WIDTH                      1  /* LHPF3_MODE */
-#define ARIZONA_LHPF3_ENA                        0x0001  /* LHPF3_ENA */
-#define ARIZONA_LHPF3_ENA_MASK                   0x0001  /* LHPF3_ENA */
-#define ARIZONA_LHPF3_ENA_SHIFT                       0  /* LHPF3_ENA */
-#define ARIZONA_LHPF3_ENA_WIDTH                       1  /* LHPF3_ENA */
-
-/*
- * R3785 (0xEC9) - HPLPF3_2
- */
-#define ARIZONA_LHPF3_COEFF_MASK                 0xFFFF  /* LHPF3_COEFF - [15:0] */
-#define ARIZONA_LHPF3_COEFF_SHIFT                     0  /* LHPF3_COEFF - [15:0] */
-#define ARIZONA_LHPF3_COEFF_WIDTH                    16  /* LHPF3_COEFF - [15:0] */
-
-/*
- * R3788 (0xECC) - HPLPF4_1
- */
-#define ARIZONA_LHPF4_MODE                       0x0002  /* LHPF4_MODE */
-#define ARIZONA_LHPF4_MODE_MASK                  0x0002  /* LHPF4_MODE */
-#define ARIZONA_LHPF4_MODE_SHIFT                      1  /* LHPF4_MODE */
-#define ARIZONA_LHPF4_MODE_WIDTH                      1  /* LHPF4_MODE */
-#define ARIZONA_LHPF4_ENA                        0x0001  /* LHPF4_ENA */
-#define ARIZONA_LHPF4_ENA_MASK                   0x0001  /* LHPF4_ENA */
-#define ARIZONA_LHPF4_ENA_SHIFT                       0  /* LHPF4_ENA */
-#define ARIZONA_LHPF4_ENA_WIDTH                       1  /* LHPF4_ENA */
-
-/*
- * R3789 (0xECD) - HPLPF4_2
- */
-#define ARIZONA_LHPF4_COEFF_MASK                 0xFFFF  /* LHPF4_COEFF - [15:0] */
-#define ARIZONA_LHPF4_COEFF_SHIFT                     0  /* LHPF4_COEFF - [15:0] */
-#define ARIZONA_LHPF4_COEFF_WIDTH                    16  /* LHPF4_COEFF - [15:0] */
-
-/*
- * R3808 (0xEE0) - ASRC_ENABLE
- */
-#define ARIZONA_ASRC2L_ENA                       0x0008  /* ASRC2L_ENA */
-#define ARIZONA_ASRC2L_ENA_MASK                  0x0008  /* ASRC2L_ENA */
-#define ARIZONA_ASRC2L_ENA_SHIFT                      3  /* ASRC2L_ENA */
-#define ARIZONA_ASRC2L_ENA_WIDTH                      1  /* ASRC2L_ENA */
-#define ARIZONA_ASRC2R_ENA                       0x0004  /* ASRC2R_ENA */
-#define ARIZONA_ASRC2R_ENA_MASK                  0x0004  /* ASRC2R_ENA */
-#define ARIZONA_ASRC2R_ENA_SHIFT                      2  /* ASRC2R_ENA */
-#define ARIZONA_ASRC2R_ENA_WIDTH                      1  /* ASRC2R_ENA */
-#define ARIZONA_ASRC1L_ENA                       0x0002  /* ASRC1L_ENA */
-#define ARIZONA_ASRC1L_ENA_MASK                  0x0002  /* ASRC1L_ENA */
-#define ARIZONA_ASRC1L_ENA_SHIFT                      1  /* ASRC1L_ENA */
-#define ARIZONA_ASRC1L_ENA_WIDTH                      1  /* ASRC1L_ENA */
-#define ARIZONA_ASRC1R_ENA                       0x0001  /* ASRC1R_ENA */
-#define ARIZONA_ASRC1R_ENA_MASK                  0x0001  /* ASRC1R_ENA */
-#define ARIZONA_ASRC1R_ENA_SHIFT                      0  /* ASRC1R_ENA */
-#define ARIZONA_ASRC1R_ENA_WIDTH                      1  /* ASRC1R_ENA */
-
-/*
- * R3810 (0xEE2) - ASRC_RATE1
- */
-#define ARIZONA_ASRC_RATE1_MASK                  0x7800  /* ASRC_RATE1 - [14:11] */
-#define ARIZONA_ASRC_RATE1_SHIFT                     11  /* ASRC_RATE1 - [14:11] */
-#define ARIZONA_ASRC_RATE1_WIDTH                      4  /* ASRC_RATE1 - [14:11] */
-
-/*
- * R3811 (0xEE3) - ASRC_RATE2
- */
-#define ARIZONA_ASRC_RATE2_MASK                  0x7800  /* ASRC_RATE2 - [14:11] */
-#define ARIZONA_ASRC_RATE2_SHIFT                     11  /* ASRC_RATE2 - [14:11] */
-#define ARIZONA_ASRC_RATE2_WIDTH                      4  /* ASRC_RATE2 - [14:11] */
-
-/*
- * R3824 (0xEF0) - ISRC 1 CTRL 1
- */
-#define ARIZONA_ISRC1_FSH_MASK                   0x7800  /* ISRC1_FSH - [14:11] */
-#define ARIZONA_ISRC1_FSH_SHIFT                      11  /* ISRC1_FSH - [14:11] */
-#define ARIZONA_ISRC1_FSH_WIDTH                       4  /* ISRC1_FSH - [14:11] */
-#define ARIZONA_ISRC1_CLK_SEL_MASK               0x0700  /* ISRC1_CLK_SEL - [10:8] */
-#define ARIZONA_ISRC1_CLK_SEL_SHIFT                   8  /* ISRC1_CLK_SEL - [10:8] */
-#define ARIZONA_ISRC1_CLK_SEL_WIDTH                   3  /* ISRC1_CLK_SEL - [10:8] */
-
-/*
- * R3825 (0xEF1) - ISRC 1 CTRL 2
- */
-#define ARIZONA_ISRC1_FSL_MASK                   0x7800  /* ISRC1_FSL - [14:11] */
-#define ARIZONA_ISRC1_FSL_SHIFT                      11  /* ISRC1_FSL - [14:11] */
-#define ARIZONA_ISRC1_FSL_WIDTH                       4  /* ISRC1_FSL - [14:11] */
-
-/*
- * R3826 (0xEF2) - ISRC 1 CTRL 3
- */
-#define ARIZONA_ISRC1_INT0_ENA                   0x8000  /* ISRC1_INT0_ENA */
-#define ARIZONA_ISRC1_INT0_ENA_MASK              0x8000  /* ISRC1_INT0_ENA */
-#define ARIZONA_ISRC1_INT0_ENA_SHIFT                 15  /* ISRC1_INT0_ENA */
-#define ARIZONA_ISRC1_INT0_ENA_WIDTH                  1  /* ISRC1_INT0_ENA */
-#define ARIZONA_ISRC1_INT1_ENA                   0x4000  /* ISRC1_INT1_ENA */
-#define ARIZONA_ISRC1_INT1_ENA_MASK              0x4000  /* ISRC1_INT1_ENA */
-#define ARIZONA_ISRC1_INT1_ENA_SHIFT                 14  /* ISRC1_INT1_ENA */
-#define ARIZONA_ISRC1_INT1_ENA_WIDTH                  1  /* ISRC1_INT1_ENA */
-#define ARIZONA_ISRC1_INT2_ENA                   0x2000  /* ISRC1_INT2_ENA */
-#define ARIZONA_ISRC1_INT2_ENA_MASK              0x2000  /* ISRC1_INT2_ENA */
-#define ARIZONA_ISRC1_INT2_ENA_SHIFT                 13  /* ISRC1_INT2_ENA */
-#define ARIZONA_ISRC1_INT2_ENA_WIDTH                  1  /* ISRC1_INT2_ENA */
-#define ARIZONA_ISRC1_INT3_ENA                   0x1000  /* ISRC1_INT3_ENA */
-#define ARIZONA_ISRC1_INT3_ENA_MASK              0x1000  /* ISRC1_INT3_ENA */
-#define ARIZONA_ISRC1_INT3_ENA_SHIFT                 12  /* ISRC1_INT3_ENA */
-#define ARIZONA_ISRC1_INT3_ENA_WIDTH                  1  /* ISRC1_INT3_ENA */
-#define ARIZONA_ISRC1_DEC0_ENA                   0x0200  /* ISRC1_DEC0_ENA */
-#define ARIZONA_ISRC1_DEC0_ENA_MASK              0x0200  /* ISRC1_DEC0_ENA */
-#define ARIZONA_ISRC1_DEC0_ENA_SHIFT                  9  /* ISRC1_DEC0_ENA */
-#define ARIZONA_ISRC1_DEC0_ENA_WIDTH                  1  /* ISRC1_DEC0_ENA */
-#define ARIZONA_ISRC1_DEC1_ENA                   0x0100  /* ISRC1_DEC1_ENA */
-#define ARIZONA_ISRC1_DEC1_ENA_MASK              0x0100  /* ISRC1_DEC1_ENA */
-#define ARIZONA_ISRC1_DEC1_ENA_SHIFT                  8  /* ISRC1_DEC1_ENA */
-#define ARIZONA_ISRC1_DEC1_ENA_WIDTH                  1  /* ISRC1_DEC1_ENA */
-#define ARIZONA_ISRC1_DEC2_ENA                   0x0080  /* ISRC1_DEC2_ENA */
-#define ARIZONA_ISRC1_DEC2_ENA_MASK              0x0080  /* ISRC1_DEC2_ENA */
-#define ARIZONA_ISRC1_DEC2_ENA_SHIFT                  7  /* ISRC1_DEC2_ENA */
-#define ARIZONA_ISRC1_DEC2_ENA_WIDTH                  1  /* ISRC1_DEC2_ENA */
-#define ARIZONA_ISRC1_DEC3_ENA                   0x0040  /* ISRC1_DEC3_ENA */
-#define ARIZONA_ISRC1_DEC3_ENA_MASK              0x0040  /* ISRC1_DEC3_ENA */
-#define ARIZONA_ISRC1_DEC3_ENA_SHIFT                  6  /* ISRC1_DEC3_ENA */
-#define ARIZONA_ISRC1_DEC3_ENA_WIDTH                  1  /* ISRC1_DEC3_ENA */
-#define ARIZONA_ISRC1_NOTCH_ENA                  0x0001  /* ISRC1_NOTCH_ENA */
-#define ARIZONA_ISRC1_NOTCH_ENA_MASK             0x0001  /* ISRC1_NOTCH_ENA */
-#define ARIZONA_ISRC1_NOTCH_ENA_SHIFT                 0  /* ISRC1_NOTCH_ENA */
-#define ARIZONA_ISRC1_NOTCH_ENA_WIDTH                 1  /* ISRC1_NOTCH_ENA */
-
-/*
- * R3827 (0xEF3) - ISRC 2 CTRL 1
- */
-#define ARIZONA_ISRC2_FSH_MASK                   0x7800  /* ISRC2_FSH - [14:11] */
-#define ARIZONA_ISRC2_FSH_SHIFT                      11  /* ISRC2_FSH - [14:11] */
-#define ARIZONA_ISRC2_FSH_WIDTH                       4  /* ISRC2_FSH - [14:11] */
-#define ARIZONA_ISRC2_CLK_SEL_MASK               0x0700  /* ISRC2_CLK_SEL - [10:8] */
-#define ARIZONA_ISRC2_CLK_SEL_SHIFT                   8  /* ISRC2_CLK_SEL - [10:8] */
-#define ARIZONA_ISRC2_CLK_SEL_WIDTH                   3  /* ISRC2_CLK_SEL - [10:8] */
-
-/*
- * R3828 (0xEF4) - ISRC 2 CTRL 2
- */
-#define ARIZONA_ISRC2_FSL_MASK                   0x7800  /* ISRC2_FSL - [14:11] */
-#define ARIZONA_ISRC2_FSL_SHIFT                      11  /* ISRC2_FSL - [14:11] */
-#define ARIZONA_ISRC2_FSL_WIDTH                       4  /* ISRC2_FSL - [14:11] */
-
-/*
- * R3829 (0xEF5) - ISRC 2 CTRL 3
- */
-#define ARIZONA_ISRC2_INT0_ENA                   0x8000  /* ISRC2_INT0_ENA */
-#define ARIZONA_ISRC2_INT0_ENA_MASK              0x8000  /* ISRC2_INT0_ENA */
-#define ARIZONA_ISRC2_INT0_ENA_SHIFT                 15  /* ISRC2_INT0_ENA */
-#define ARIZONA_ISRC2_INT0_ENA_WIDTH                  1  /* ISRC2_INT0_ENA */
-#define ARIZONA_ISRC2_INT1_ENA                   0x4000  /* ISRC2_INT1_ENA */
-#define ARIZONA_ISRC2_INT1_ENA_MASK              0x4000  /* ISRC2_INT1_ENA */
-#define ARIZONA_ISRC2_INT1_ENA_SHIFT                 14  /* ISRC2_INT1_ENA */
-#define ARIZONA_ISRC2_INT1_ENA_WIDTH                  1  /* ISRC2_INT1_ENA */
-#define ARIZONA_ISRC2_INT2_ENA                   0x2000  /* ISRC2_INT2_ENA */
-#define ARIZONA_ISRC2_INT2_ENA_MASK              0x2000  /* ISRC2_INT2_ENA */
-#define ARIZONA_ISRC2_INT2_ENA_SHIFT                 13  /* ISRC2_INT2_ENA */
-#define ARIZONA_ISRC2_INT2_ENA_WIDTH                  1  /* ISRC2_INT2_ENA */
-#define ARIZONA_ISRC2_INT3_ENA                   0x1000  /* ISRC2_INT3_ENA */
-#define ARIZONA_ISRC2_INT3_ENA_MASK              0x1000  /* ISRC2_INT3_ENA */
-#define ARIZONA_ISRC2_INT3_ENA_SHIFT                 12  /* ISRC2_INT3_ENA */
-#define ARIZONA_ISRC2_INT3_ENA_WIDTH                  1  /* ISRC2_INT3_ENA */
-#define ARIZONA_ISRC2_DEC0_ENA                   0x0200  /* ISRC2_DEC0_ENA */
-#define ARIZONA_ISRC2_DEC0_ENA_MASK              0x0200  /* ISRC2_DEC0_ENA */
-#define ARIZONA_ISRC2_DEC0_ENA_SHIFT                  9  /* ISRC2_DEC0_ENA */
-#define ARIZONA_ISRC2_DEC0_ENA_WIDTH                  1  /* ISRC2_DEC0_ENA */
-#define ARIZONA_ISRC2_DEC1_ENA                   0x0100  /* ISRC2_DEC1_ENA */
-#define ARIZONA_ISRC2_DEC1_ENA_MASK              0x0100  /* ISRC2_DEC1_ENA */
-#define ARIZONA_ISRC2_DEC1_ENA_SHIFT                  8  /* ISRC2_DEC1_ENA */
-#define ARIZONA_ISRC2_DEC1_ENA_WIDTH                  1  /* ISRC2_DEC1_ENA */
-#define ARIZONA_ISRC2_DEC2_ENA                   0x0080  /* ISRC2_DEC2_ENA */
-#define ARIZONA_ISRC2_DEC2_ENA_MASK              0x0080  /* ISRC2_DEC2_ENA */
-#define ARIZONA_ISRC2_DEC2_ENA_SHIFT                  7  /* ISRC2_DEC2_ENA */
-#define ARIZONA_ISRC2_DEC2_ENA_WIDTH                  1  /* ISRC2_DEC2_ENA */
-#define ARIZONA_ISRC2_DEC3_ENA                   0x0040  /* ISRC2_DEC3_ENA */
-#define ARIZONA_ISRC2_DEC3_ENA_MASK              0x0040  /* ISRC2_DEC3_ENA */
-#define ARIZONA_ISRC2_DEC3_ENA_SHIFT                  6  /* ISRC2_DEC3_ENA */
-#define ARIZONA_ISRC2_DEC3_ENA_WIDTH                  1  /* ISRC2_DEC3_ENA */
-#define ARIZONA_ISRC2_NOTCH_ENA                  0x0001  /* ISRC2_NOTCH_ENA */
-#define ARIZONA_ISRC2_NOTCH_ENA_MASK             0x0001  /* ISRC2_NOTCH_ENA */
-#define ARIZONA_ISRC2_NOTCH_ENA_SHIFT                 0  /* ISRC2_NOTCH_ENA */
-#define ARIZONA_ISRC2_NOTCH_ENA_WIDTH                 1  /* ISRC2_NOTCH_ENA */
-
-/*
- * R3830 (0xEF6) - ISRC 3 CTRL 1
- */
-#define ARIZONA_ISRC3_FSH_MASK                   0x7800  /* ISRC3_FSH - [14:11] */
-#define ARIZONA_ISRC3_FSH_SHIFT                      11  /* ISRC3_FSH - [14:11] */
-#define ARIZONA_ISRC3_FSH_WIDTH                       4  /* ISRC3_FSH - [14:11] */
-#define ARIZONA_ISRC3_CLK_SEL_MASK               0x0700  /* ISRC3_CLK_SEL - [10:8] */
-#define ARIZONA_ISRC3_CLK_SEL_SHIFT                   8  /* ISRC3_CLK_SEL - [10:8] */
-#define ARIZONA_ISRC3_CLK_SEL_WIDTH                   3  /* ISRC3_CLK_SEL - [10:8] */
-
-/*
- * R3831 (0xEF7) - ISRC 3 CTRL 2
- */
-#define ARIZONA_ISRC3_FSL_MASK                   0x7800  /* ISRC3_FSL - [14:11] */
-#define ARIZONA_ISRC3_FSL_SHIFT                      11  /* ISRC3_FSL - [14:11] */
-#define ARIZONA_ISRC3_FSL_WIDTH                       4  /* ISRC3_FSL - [14:11] */
-
-/*
- * R3832 (0xEF8) - ISRC 3 CTRL 3
- */
-#define ARIZONA_ISRC3_INT0_ENA                   0x8000  /* ISRC3_INT0_ENA */
-#define ARIZONA_ISRC3_INT0_ENA_MASK              0x8000  /* ISRC3_INT0_ENA */
-#define ARIZONA_ISRC3_INT0_ENA_SHIFT                 15  /* ISRC3_INT0_ENA */
-#define ARIZONA_ISRC3_INT0_ENA_WIDTH                  1  /* ISRC3_INT0_ENA */
-#define ARIZONA_ISRC3_INT1_ENA                   0x4000  /* ISRC3_INT1_ENA */
-#define ARIZONA_ISRC3_INT1_ENA_MASK              0x4000  /* ISRC3_INT1_ENA */
-#define ARIZONA_ISRC3_INT1_ENA_SHIFT                 14  /* ISRC3_INT1_ENA */
-#define ARIZONA_ISRC3_INT1_ENA_WIDTH                  1  /* ISRC3_INT1_ENA */
-#define ARIZONA_ISRC3_INT2_ENA                   0x2000  /* ISRC3_INT2_ENA */
-#define ARIZONA_ISRC3_INT2_ENA_MASK              0x2000  /* ISRC3_INT2_ENA */
-#define ARIZONA_ISRC3_INT2_ENA_SHIFT                 13  /* ISRC3_INT2_ENA */
-#define ARIZONA_ISRC3_INT2_ENA_WIDTH                  1  /* ISRC3_INT2_ENA */
-#define ARIZONA_ISRC3_INT3_ENA                   0x1000  /* ISRC3_INT3_ENA */
-#define ARIZONA_ISRC3_INT3_ENA_MASK              0x1000  /* ISRC3_INT3_ENA */
-#define ARIZONA_ISRC3_INT3_ENA_SHIFT                 12  /* ISRC3_INT3_ENA */
-#define ARIZONA_ISRC3_INT3_ENA_WIDTH                  1  /* ISRC3_INT3_ENA */
-#define ARIZONA_ISRC3_DEC0_ENA                   0x0200  /* ISRC3_DEC0_ENA */
-#define ARIZONA_ISRC3_DEC0_ENA_MASK              0x0200  /* ISRC3_DEC0_ENA */
-#define ARIZONA_ISRC3_DEC0_ENA_SHIFT                  9  /* ISRC3_DEC0_ENA */
-#define ARIZONA_ISRC3_DEC0_ENA_WIDTH                  1  /* ISRC3_DEC0_ENA */
-#define ARIZONA_ISRC3_DEC1_ENA                   0x0100  /* ISRC3_DEC1_ENA */
-#define ARIZONA_ISRC3_DEC1_ENA_MASK              0x0100  /* ISRC3_DEC1_ENA */
-#define ARIZONA_ISRC3_DEC1_ENA_SHIFT                  8  /* ISRC3_DEC1_ENA */
-#define ARIZONA_ISRC3_DEC1_ENA_WIDTH                  1  /* ISRC3_DEC1_ENA */
-#define ARIZONA_ISRC3_DEC2_ENA                   0x0080  /* ISRC3_DEC2_ENA */
-#define ARIZONA_ISRC3_DEC2_ENA_MASK              0x0080  /* ISRC3_DEC2_ENA */
-#define ARIZONA_ISRC3_DEC2_ENA_SHIFT                  7  /* ISRC3_DEC2_ENA */
-#define ARIZONA_ISRC3_DEC2_ENA_WIDTH                  1  /* ISRC3_DEC2_ENA */
-#define ARIZONA_ISRC3_DEC3_ENA                   0x0040  /* ISRC3_DEC3_ENA */
-#define ARIZONA_ISRC3_DEC3_ENA_MASK              0x0040  /* ISRC3_DEC3_ENA */
-#define ARIZONA_ISRC3_DEC3_ENA_SHIFT                  6  /* ISRC3_DEC3_ENA */
-#define ARIZONA_ISRC3_DEC3_ENA_WIDTH                  1  /* ISRC3_DEC3_ENA */
-#define ARIZONA_ISRC3_NOTCH_ENA                  0x0001  /* ISRC3_NOTCH_ENA */
-#define ARIZONA_ISRC3_NOTCH_ENA_MASK             0x0001  /* ISRC3_NOTCH_ENA */
-#define ARIZONA_ISRC3_NOTCH_ENA_SHIFT                 0  /* ISRC3_NOTCH_ENA */
-#define ARIZONA_ISRC3_NOTCH_ENA_WIDTH                 1  /* ISRC3_NOTCH_ENA */
-
-/*
- * R4352 (0x1100) - DSP1 Control 1
- */
-#define ARIZONA_DSP1_RATE_MASK                   0x7800  /* DSP1_RATE - [14:11] */
-#define ARIZONA_DSP1_RATE_SHIFT                      11  /* DSP1_RATE - [14:11] */
-#define ARIZONA_DSP1_RATE_WIDTH                       4  /* DSP1_RATE - [14:11] */
-#define ARIZONA_DSP1_MEM_ENA                     0x0010  /* DSP1_MEM_ENA */
-#define ARIZONA_DSP1_MEM_ENA_MASK                0x0010  /* DSP1_MEM_ENA */
-#define ARIZONA_DSP1_MEM_ENA_SHIFT                    4  /* DSP1_MEM_ENA */
-#define ARIZONA_DSP1_MEM_ENA_WIDTH                    1  /* DSP1_MEM_ENA */
-#define ARIZONA_DSP1_SYS_ENA                     0x0004  /* DSP1_SYS_ENA */
-#define ARIZONA_DSP1_SYS_ENA_MASK                0x0004  /* DSP1_SYS_ENA */
-#define ARIZONA_DSP1_SYS_ENA_SHIFT                    2  /* DSP1_SYS_ENA */
-#define ARIZONA_DSP1_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
-#define ARIZONA_DSP1_CORE_ENA                    0x0002  /* DSP1_CORE_ENA */
-#define ARIZONA_DSP1_CORE_ENA_MASK               0x0002  /* DSP1_CORE_ENA */
-#define ARIZONA_DSP1_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
-#define ARIZONA_DSP1_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
-#define ARIZONA_DSP1_START                       0x0001  /* DSP1_START */
-#define ARIZONA_DSP1_START_MASK                  0x0001  /* DSP1_START */
-#define ARIZONA_DSP1_START_SHIFT                      0  /* DSP1_START */
-#define ARIZONA_DSP1_START_WIDTH                      1  /* DSP1_START */
-
-/*
- * R4353 (0x1101) - DSP1 Clocking 1
- */
-#define ARIZONA_DSP1_CLK_SEL_MASK                0x0007  /* DSP1_CLK_SEL - [2:0] */
-#define ARIZONA_DSP1_CLK_SEL_SHIFT                    0  /* DSP1_CLK_SEL - [2:0] */
-#define ARIZONA_DSP1_CLK_SEL_WIDTH                    3  /* DSP1_CLK_SEL - [2:0] */
-
-/*
- * R4356 (0x1104) - DSP1 Status 1
- */
-#define ARIZONA_DSP1_RAM_RDY                     0x0001  /* DSP1_RAM_RDY */
-#define ARIZONA_DSP1_RAM_RDY_MASK                0x0001  /* DSP1_RAM_RDY */
-#define ARIZONA_DSP1_RAM_RDY_SHIFT                    0  /* DSP1_RAM_RDY */
-#define ARIZONA_DSP1_RAM_RDY_WIDTH                    1  /* DSP1_RAM_RDY */
-
-/*
- * R4357 (0x1105) - DSP1 Status 2
- */
-#define ARIZONA_DSP1_PING_FULL                   0x8000  /* DSP1_PING_FULL */
-#define ARIZONA_DSP1_PING_FULL_MASK              0x8000  /* DSP1_PING_FULL */
-#define ARIZONA_DSP1_PING_FULL_SHIFT                 15  /* DSP1_PING_FULL */
-#define ARIZONA_DSP1_PING_FULL_WIDTH                  1  /* DSP1_PING_FULL */
-#define ARIZONA_DSP1_PONG_FULL                   0x4000  /* DSP1_PONG_FULL */
-#define ARIZONA_DSP1_PONG_FULL_MASK              0x4000  /* DSP1_PONG_FULL */
-#define ARIZONA_DSP1_PONG_FULL_SHIFT                 14  /* DSP1_PONG_FULL */
-#define ARIZONA_DSP1_PONG_FULL_WIDTH                  1  /* DSP1_PONG_FULL */
-#define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_MASK   0x00FF  /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
-#define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT       0  /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
-#define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH       8  /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
-
-#endif
diff --git a/include/linux/mfd/as3711.h b/include/linux/mfd/as3711.h
deleted file mode 100644
index 38452ce1e89..00000000000
--- a/include/linux/mfd/as3711.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * AS3711 PMIC MFC driver header
- *
- * Copyright (C) 2012 Renesas Electronics Corporation
- * Author: Guennadi Liakhovetski, <g.liakhovetski@gmx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the version 2 of the GNU General Public License as
- * published by the Free Software Foundation
- */
-
-#ifndef MFD_AS3711_H
-#define MFD_AS3711_H
-
-/*
- * Client data
- */
-
-/* Register addresses */
-#define AS3711_SD_1_VOLTAGE             0       /* Digital Step-Down */
-#define AS3711_SD_2_VOLTAGE             1
-#define AS3711_SD_3_VOLTAGE             2
-#define AS3711_SD_4_VOLTAGE             3
-#define AS3711_LDO_1_VOLTAGE            4       /* Analog LDO */
-#define AS3711_LDO_2_VOLTAGE            5
-#define AS3711_LDO_3_VOLTAGE            6       /* Digital LDO */
-#define AS3711_LDO_4_VOLTAGE            7
-#define AS3711_LDO_5_VOLTAGE            8
-#define AS3711_LDO_6_VOLTAGE            9
-#define AS3711_LDO_7_VOLTAGE            0xa
-#define AS3711_LDO_8_VOLTAGE            0xb
-#define AS3711_SD_CONTROL               0x10
-#define AS3711_GPIO_SIGNAL_OUT          0x20
-#define AS3711_GPIO_SIGNAL_IN           0x21
-#define AS3711_SD_CONTROL_1             0x30
-#define AS3711_SD_CONTROL_2             0x31
-#define AS3711_CURR_CONTROL             0x40
-#define AS3711_CURR1_VALUE              0x43
-#define AS3711_CURR2_VALUE              0x44
-#define AS3711_CURR3_VALUE              0x45
-#define AS3711_STEPUP_CONTROL_1         0x50
-#define AS3711_STEPUP_CONTROL_2         0x51
-#define AS3711_STEPUP_CONTROL_4         0x53
-#define AS3711_STEPUP_CONTROL_5         0x54
-#define AS3711_REG_STATUS               0x73
-#define AS3711_INTERRUPT_STATUS_1       0x77
-#define AS3711_INTERRUPT_STATUS_2       0x78
-#define AS3711_INTERRUPT_STATUS_3       0x79
-#define AS3711_CHARGER_STATUS_1         0x86
-#define AS3711_CHARGER_STATUS_2         0x87
-#define AS3711_ASIC_ID_1                0x90
-#define AS3711_ASIC_ID_2                0x91
-
-#define AS3711_MAX_REGS                 0x92
-
-/* Regulators */
-enum {
-        AS3711_REGULATOR_SD_1,
-        AS3711_REGULATOR_SD_2,
-        AS3711_REGULATOR_SD_3,
-        AS3711_REGULATOR_SD_4,
-        AS3711_REGULATOR_LDO_1,
-        AS3711_REGULATOR_LDO_2,
-        AS3711_REGULATOR_LDO_3,
-        AS3711_REGULATOR_LDO_4,
-        AS3711_REGULATOR_LDO_5,
-        AS3711_REGULATOR_LDO_6,
-        AS3711_REGULATOR_LDO_7,
-        AS3711_REGULATOR_LDO_8,
-
-        AS3711_REGULATOR_MAX,
-};
-
-struct device;
-struct regmap;
-
-struct as3711 {
-        struct device *dev;
-        struct regmap *regmap;
-};
-
-#define AS3711_MAX_STEPDOWN 4
-#define AS3711_MAX_STEPUP 2
-#define AS3711_MAX_LDO 8
-
-enum as3711_su2_feedback {
-        AS3711_SU2_VOLTAGE,
-        AS3711_SU2_CURR1,
-        AS3711_SU2_CURR2,
-        AS3711_SU2_CURR3,
-        AS3711_SU2_CURR_AUTO,
-};
-
-enum as3711_su2_fbprot {
-        AS3711_SU2_LX_SD4,
-        AS3711_SU2_GPIO2,
-        AS3711_SU2_GPIO3,
-        AS3711_SU2_GPIO4,
-};
-
-/*
- * Platform data
- */
-
-struct as3711_regulator_pdata {
-        struct regulator_init_data *init_data[AS3711_REGULATOR_MAX];
-};
-
-struct as3711_bl_pdata {
-        const char *su1_fb;
-        int su1_max_uA;
-        const char *su2_fb;
-        int su2_max_uA;
-        enum as3711_su2_feedback su2_feedback;
-        enum as3711_su2_fbprot su2_fbprot;
-        bool su2_auto_curr1;
-        bool su2_auto_curr2;
-        bool su2_auto_curr3;
-};
-
-struct as3711_platform_data {
-        struct as3711_regulator_pdata regulator;
-        struct as3711_bl_pdata backlight;
-};
-
-#endif
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index e1148d037e7..ed793b77a1c 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -31,8 +31,6 @@ struct asic3_platform_data {
 
         unsigned int gpio_base;
 
-        unsigned int clock_rate;
-
         struct asic3_led *leds;
 };
 
@@ -140,7 +138,6 @@ struct asic3_platform_data {
 #define ASIC3_GPIOC13_nPWAIT            ASIC3_CONFIG_GPIO(45, 1, 1, 0)
 #define ASIC3_GPIOC14_nPIOIS16          ASIC3_CONFIG_GPIO(46, 1, 1, 0)
 #define ASIC3_GPIOC15_nPIOR             ASIC3_CONFIG_GPIO(47, 1, 0, 0)
-#define ASIC3_GPIOD4_CF_nCD             ASIC3_CONFIG_GPIO(52, 1, 0, 0)
 #define ASIC3_GPIOD11_nCIOIS16          ASIC3_CONFIG_GPIO(59, 1, 0, 0)
 #define ASIC3_GPIOD12_nCWAIT            ASIC3_CONFIG_GPIO(60, 1, 0, 0)
 #define ASIC3_GPIOD15_nPIOW             ASIC3_CONFIG_GPIO(63, 1, 0, 0)
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index cebe97ee98b..4e76163dd86 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -16,8 +16,6 @@
 
 #include <linux/platform_device.h>
 
-struct irq_domain;
-
 /*
  * This struct describes the MFD part ("cell").
  * After registration the copy of this structure will become the platform data
@@ -38,11 +36,6 @@ struct mfd_cell {
         /* platform data passed to the sub devices drivers */
         void                    *platform_data;
         size_t                  pdata_size;
-        /*
-         * Device Tree compatible string
-         * See: Documentation/devicetree/usage-model.txt Chapter 2.2 for details
-         */
-        const char              *of_compatible;
 
         /*
          * These resources can be specified relative to the parent device.
@@ -100,7 +93,7 @@ static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev)
 extern int mfd_add_devices(struct device *parent, int id,
                            struct mfd_cell *cells, int n_devs,
                            struct resource *mem_base,
-                           int irq_base, struct irq_domain *irq_domain);
+                           int irq_base);
 
 extern void mfd_remove_devices(struct device *parent);
 
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
deleted file mode 100644
index 86dd93de6ff..00000000000
--- a/include/linux/mfd/da9052/da9052.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * da9052 declarations for DA9052 PMICs.
- *
- * Copyright(c) 2011 Dialog Semiconductor Ltd.
- *
- * Author: David Dajun Chen <dchen@diasemi.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __MFD_DA9052_DA9052_H
-#define __MFD_DA9052_DA9052_H
-
-#include <linux/interrupt.h>
-#include <linux/regmap.h>
-#include <linux/slab.h>
-#include <linux/completion.h>
-#include <linux/list.h>
-#include <linux/mfd/core.h>
-
-#include <linux/mfd/da9052/reg.h>
-
-/* Common - HWMON Channel Definations */
-#define DA9052_ADC_VDDOUT       0
-#define DA9052_ADC_ICH          1
-#define DA9052_ADC_TBAT 2
-#define DA9052_ADC_VBAT 3
-#define DA9052_ADC_IN4          4
-#define DA9052_ADC_IN5          5
-#define DA9052_ADC_IN6          6
-#define DA9052_ADC_TSI          7
-#define DA9052_ADC_TJUNC        8
-#define DA9052_ADC_VBBAT        9
-
-#define DA9052_IRQ_DCIN 0
-#define DA9052_IRQ_VBUS 1
-#define DA9052_IRQ_DCINREM      2
-#define DA9052_IRQ_VBUSREM      3
-#define DA9052_IRQ_VDDLOW       4
-#define DA9052_IRQ_ALARM        5
-#define DA9052_IRQ_SEQRDY       6
-#define DA9052_IRQ_COMP1V2      7
-#define DA9052_IRQ_NONKEY       8
-#define DA9052_IRQ_IDFLOAT      9
-#define DA9052_IRQ_IDGND        10
-#define DA9052_IRQ_CHGEND       11
-#define DA9052_IRQ_TBAT 12
-#define DA9052_IRQ_ADC_EOM      13
-#define DA9052_IRQ_PENDOWN      14
-#define DA9052_IRQ_TSIREADY     15
-#define DA9052_IRQ_GPI0 16
-#define DA9052_IRQ_GPI1 17
-#define DA9052_IRQ_GPI2 18
-#define DA9052_IRQ_GPI3 19
-#define DA9052_IRQ_GPI4 20
-#define DA9052_IRQ_GPI5 21
-#define DA9052_IRQ_GPI6 22
-#define DA9052_IRQ_GPI7 23
-#define DA9052_IRQ_GPI8 24
-#define DA9052_IRQ_GPI9 25
-#define DA9052_IRQ_GPI10        26
-#define DA9052_IRQ_GPI11        27
-#define DA9052_IRQ_GPI12        28
-#define DA9052_IRQ_GPI13        29
-#define DA9052_IRQ_GPI14        30
-#define DA9052_IRQ_GPI15        31
-
-enum da9052_chip_id {
-        DA9052,
-        DA9053_AA,
-        DA9053_BA,
-        DA9053_BB,
-};
-
-struct da9052_pdata;
-
-struct da9052 {
-        struct device *dev;
-        struct regmap *regmap;
-
-        struct mutex auxadc_lock;
-        struct completion done;
-
-        int irq_base;
-        struct regmap_irq_chip_data *irq_data;
-        u8 chip_id;
-
-        int chip_irq;
-};
-
-/* ADC API */
-int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel);
-int da9052_adc_read_temp(struct da9052 *da9052);
-
-/* Device I/O API */
-static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg)
-{
-        int val, ret;
-
-        ret = regmap_read(da9052->regmap, reg, &val);
-        if (ret < 0)
-                return ret;
-        return val;
-}
-
-static inline int da9052_reg_write(struct da9052 *da9052, unsigned char reg,
-                                    unsigned char val)
-{
-        return regmap_write(da9052->regmap, reg, val);
-}
-
-static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg,
-                                     unsigned reg_cnt, unsigned char *val)
-{
-        return regmap_bulk_read(da9052->regmap, reg, val, reg_cnt);
-}
-
-static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,
-                                      unsigned reg_cnt, unsigned char *val)
-{
-        return regmap_raw_write(da9052->regmap, reg, val, reg_cnt);
-}
-
-static inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg,
-                                     unsigned char bit_mask,
-                                     unsigned char reg_val)
-{
-        return regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val);
-}
-
-int da9052_device_init(struct da9052 *da9052, u8 chip_id);
-void da9052_device_exit(struct da9052 *da9052);
-
-extern struct regmap_config da9052_regmap_config;
-
-int da9052_irq_init(struct da9052 *da9052);
-int da9052_irq_exit(struct da9052 *da9052);
-int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
-                           irq_handler_t handler, void *data);
-void da9052_free_irq(struct da9052 *da9052, int irq, void *data);
-
-int da9052_enable_irq(struct da9052 *da9052, int irq);
-int da9052_disable_irq(struct da9052 *da9052, int irq);
-int da9052_disable_irq_nosync(struct da9052 *da9052, int irq);
-
-#endif /* __MFD_DA9052_DA9052_H */
diff --git a/include/linux/mfd/da9052/pdata.h b/include/linux/mfd/da9052/pdata.h
deleted file mode 100644
index 62c5c3c2992..00000000000
--- a/include/linux/mfd/da9052/pdata.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Platform data declarations for DA9052 PMICs.
- *
- * Copyright(c) 2011 Dialog Semiconductor Ltd.
- *
- * Author: David Dajun Chen <dchen@diasemi.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __MFD_DA9052_PDATA_H__
-#define __MFD_DA9052_PDATA_H__
-
-#define DA9052_MAX_REGULATORS   14
-
-struct da9052;
-
-struct da9052_pdata {
-        struct led_platform_data *pled;
-        int (*init) (struct da9052 *da9052);
-        int irq_base;
-        int gpio_base;
-        int use_for_apm;
-        struct regulator_init_data *regulators[DA9052_MAX_REGULATORS];
-};
-
-#endif
diff --git a/include/linux/mfd/da9052/reg.h b/include/linux/mfd/da9052/reg.h
deleted file mode 100644
index b97f7309d7f..00000000000
--- a/include/linux/mfd/da9052/reg.h
+++ /dev/null
@@ -1,749 +0,0 @@
-/*
- * Register declarations for DA9052 PMICs.
- *
- * Copyright(c) 2011 Dialog Semiconductor Ltd.
- *
- * Author: David Dajun Chen <dchen@diasemi.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __LINUX_MFD_DA9052_REG_H
-#define __LINUX_MFD_DA9052_REG_H
-
-/* PAGE REGISTERS */
-#define DA9052_PAGE0_CON_REG            0
-#define DA9052_PAGE1_CON_REG            128
-
-/* STATUS REGISTERS */
-#define DA9052_STATUS_A_REG             1
-#define DA9052_STATUS_B_REG             2
-#define DA9052_STATUS_C_REG             3
-#define DA9052_STATUS_D_REG             4
-
-/* EVENT REGISTERS */
-#define DA9052_EVENT_A_REG              5
-#define DA9052_EVENT_B_REG              6
-#define DA9052_EVENT_C_REG              7
-#define DA9052_EVENT_D_REG              8
-#define DA9052_FAULTLOG_REG             9
-
-/* IRQ REGISTERS */
-#define DA9052_IRQ_MASK_A_REG           10
-#define DA9052_IRQ_MASK_B_REG           11
-#define DA9052_IRQ_MASK_C_REG           12
-#define DA9052_IRQ_MASK_D_REG           13
-
-/* CONTROL REGISTERS */
-#define DA9052_CONTROL_A_REG            14
-#define DA9052_CONTROL_B_REG            15
-#define DA9052_CONTROL_C_REG            16
-#define DA9052_CONTROL_D_REG            17
-
-#define DA9052_PDDIS_REG                18
-#define DA9052_INTERFACE_REG            19
-#define DA9052_RESET_REG                20
-
-/* GPIO REGISTERS */
-#define DA9052_GPIO_0_1_REG             21
-#define DA9052_GPIO_2_3_REG             22
-#define DA9052_GPIO_4_5_REG             23
-#define DA9052_GPIO_6_7_REG             24
-#define DA9052_GPIO_14_15_REG           28
-
-/* POWER SEQUENCER CONTROL REGISTERS */
-#define DA9052_ID_0_1_REG               29
-#define DA9052_ID_2_3_REG               30
-#define DA9052_ID_4_5_REG               31
-#define DA9052_ID_6_7_REG               32
-#define DA9052_ID_8_9_REG               33
-#define DA9052_ID_10_11_REG             34
-#define DA9052_ID_12_13_REG             35
-#define DA9052_ID_14_15_REG             36
-#define DA9052_ID_16_17_REG             37
-#define DA9052_ID_18_19_REG             38
-#define DA9052_ID_20_21_REG             39
-#define DA9052_SEQ_STATUS_REG           40
-#define DA9052_SEQ_A_REG                41
-#define DA9052_SEQ_B_REG                42
-#define DA9052_SEQ_TIMER_REG            43
-
-/* LDO AND BUCK REGISTERS */
-#define DA9052_BUCKA_REG                44
-#define DA9052_BUCKB_REG                45
-#define DA9052_BUCKCORE_REG             46
-#define DA9052_BUCKPRO_REG              47
-#define DA9052_BUCKMEM_REG              48
-#define DA9052_BUCKPERI_REG             49
-#define DA9052_LDO1_REG         50
-#define DA9052_LDO2_REG         51
-#define DA9052_LDO3_REG         52
-#define DA9052_LDO4_REG         53
-#define DA9052_LDO5_REG         54
-#define DA9052_LDO6_REG         55
-#define DA9052_LDO7_REG         56
-#define DA9052_LDO8_REG         57
-#define DA9052_LDO9_REG         58
-#define DA9052_LDO10_REG                59
-#define DA9052_SUPPLY_REG               60
-#define DA9052_PULLDOWN_REG             61
-#define DA9052_CHGBUCK_REG              62
-#define DA9052_WAITCONT_REG             63
-#define DA9052_ISET_REG         64
-#define DA9052_BATCHG_REG               65
-
-/* BATTERY CONTROL REGISTRS */
-#define DA9052_CHG_CONT_REG             66
-#define DA9052_INPUT_CONT_REG           67
-#define DA9052_CHG_TIME_REG             68
-#define DA9052_BBAT_CONT_REG            69
-
-/* LED CONTROL REGISTERS */
-#define DA9052_BOOST_REG                70
-#define DA9052_LED_CONT_REG             71
-#define DA9052_LEDMIN123_REG            72
-#define DA9052_LED1_CONF_REG            73
-#define DA9052_LED2_CONF_REG            74
-#define DA9052_LED3_CONF_REG            75
-#define DA9052_LED1CONT_REG             76
-#define DA9052_LED2CONT_REG             77
-#define DA9052_LED3CONT_REG             78
-#define DA9052_LED_CONT_4_REG           79
-#define DA9052_LED_CONT_5_REG           80
-
-/* ADC CONTROL REGISTERS */
-#define DA9052_ADC_MAN_REG              81
-#define DA9052_ADC_CONT_REG             82
-#define DA9052_ADC_RES_L_REG            83
-#define DA9052_ADC_RES_H_REG            84
-#define DA9052_VDD_RES_REG              85
-#define DA9052_VDD_MON_REG              86
-
-#define DA9052_ICHG_AV_REG              87
-#define DA9052_ICHG_THD_REG             88
-#define DA9052_ICHG_END_REG             89
-#define DA9052_TBAT_RES_REG             90
-#define DA9052_TBAT_HIGHP_REG           91
-#define DA9052_TBAT_HIGHN_REG           92
-#define DA9052_TBAT_LOW_REG             93
-#define DA9052_T_OFFSET_REG             94
-
-#define DA9052_ADCIN4_RES_REG           95
-#define DA9052_AUTO4_HIGH_REG           96
-#define DA9052_AUTO4_LOW_REG            97
-#define DA9052_ADCIN5_RES_REG           98
-#define DA9052_AUTO5_HIGH_REG           99
-#define DA9052_AUTO5_LOW_REG            100
-#define DA9052_ADCIN6_RES_REG           101
-#define DA9052_AUTO6_HIGH_REG           102
-#define DA9052_AUTO6_LOW_REG            103
-
-#define DA9052_TJUNC_RES_REG            104
-
-/* TSI CONTROL REGISTERS */
-#define DA9052_TSI_CONT_A_REG           105
-#define DA9052_TSI_CONT_B_REG           106
-#define DA9052_TSI_X_MSB_REG            107
-#define DA9052_TSI_Y_MSB_REG            108
-#define DA9052_TSI_LSB_REG              109
-#define DA9052_TSI_Z_MSB_REG            110
-
-/* RTC COUNT REGISTERS */
-#define DA9052_COUNT_S_REG              111
-#define DA9052_COUNT_MI_REG             112
-#define DA9052_COUNT_H_REG              113
-#define DA9052_COUNT_D_REG              114
-#define DA9052_COUNT_MO_REG             115
-#define DA9052_COUNT_Y_REG              116
-
-/* RTC CONTROL REGISTERS */
-#define DA9052_ALARM_MI_REG             117
-#define DA9052_ALARM_H_REG              118
-#define DA9052_ALARM_D_REG              119
-#define DA9052_ALARM_MO_REG             120
-#define DA9052_ALARM_Y_REG              121
-#define DA9052_SECOND_A_REG             122
-#define DA9052_SECOND_B_REG             123
-#define DA9052_SECOND_C_REG             124
-#define DA9052_SECOND_D_REG             125
-
-/* PAGE CONFIGURATION BIT */
-#define DA9052_PAGE_CONF                0X80
-
-/* STATUS REGISTER A BITS */
-#define DA9052_STATUSA_VDATDET          0X80
-#define DA9052_STATUSA_VBUSSEL          0X40
-#define DA9052_STATUSA_DCINSEL          0X20
-#define DA9052_STATUSA_VBUSDET          0X10
-#define DA9052_STATUSA_DCINDET          0X08
-#define DA9052_STATUSA_IDGND            0X04
-#define DA9052_STATUSA_IDFLOAT          0X02
-#define DA9052_STATUSA_NONKEY           0X01
-
-/* STATUS REGISTER B BITS */
-#define DA9052_STATUSB_COMPDET          0X80
-#define DA9052_STATUSB_SEQUENCING       0X40
-#define DA9052_STATUSB_GPFB2            0X20
-#define DA9052_STATUSB_CHGTO            0X10
-#define DA9052_STATUSB_CHGEND           0X08
-#define DA9052_STATUSB_CHGLIM           0X04
-#define DA9052_STATUSB_CHGPRE           0X02
-#define DA9052_STATUSB_CHGATT           0X01
-
-/* STATUS REGISTER C BITS */
-#define DA9052_STATUSC_GPI7             0X80
-#define DA9052_STATUSC_GPI6             0X40
-#define DA9052_STATUSC_GPI5             0X20
-#define DA9052_STATUSC_GPI4             0X10
-#define DA9052_STATUSC_GPI3             0X08
-#define DA9052_STATUSC_GPI2             0X04
-#define DA9052_STATUSC_GPI1             0X02
-#define DA9052_STATUSC_GPI0             0X01
-
-/* STATUS REGISTER D BITS */
-#define DA9052_STATUSD_GPI15            0X80
-#define DA9052_STATUSD_GPI14            0X40
-#define DA9052_STATUSD_GPI13            0X20
-#define DA9052_STATUSD_GPI12            0X10
-#define DA9052_STATUSD_GPI11            0X08
-#define DA9052_STATUSD_GPI10            0X04
-#define DA9052_STATUSD_GPI9             0X02
-#define DA9052_STATUSD_GPI8             0X01
-
-/* EVENT REGISTER A BITS */
-#define DA9052_EVENTA_ECOMP1V2          0X80
-#define DA9052_EVENTA_ESEQRDY           0X40
-#define DA9052_EVENTA_EALRAM            0X20
-#define DA9052_EVENTA_EVDDLOW           0X10
-#define DA9052_EVENTA_EVBUSREM          0X08
-#define DA9052_EVENTA_EDCINREM          0X04
-#define DA9052_EVENTA_EVBUSDET          0X02
-#define DA9052_EVENTA_EDCINDET          0X01
-
-/* EVENT REGISTER B BITS */
-#define DA9052_EVENTB_ETSIREADY 0X80
-#define DA9052_EVENTB_EPENDOWN          0X40
-#define DA9052_EVENTB_EADCEOM           0X20
-#define DA9052_EVENTB_ETBAT             0X10
-#define DA9052_EVENTB_ECHGEND           0X08
-#define DA9052_EVENTB_EIDGND            0X04
-#define DA9052_EVENTB_EIDFLOAT          0X02
-#define DA9052_EVENTB_ENONKEY           0X01
-
-/* EVENT REGISTER C BITS */
-#define DA9052_EVENTC_EGPI7             0X80
-#define DA9052_EVENTC_EGPI6             0X40
-#define DA9052_EVENTC_EGPI5             0X20
-#define DA9052_EVENTC_EGPI4             0X10
-#define DA9052_EVENTC_EGPI3             0X08
-#define DA9052_EVENTC_EGPI2             0X04
-#define DA9052_EVENTC_EGPI1             0X02
-#define DA9052_EVENTC_EGPI0             0X01
-
-/* EVENT REGISTER D BITS */
-#define DA9052_EVENTD_EGPI15            0X80
-#define DA9052_EVENTD_EGPI14            0X40
-#define DA9052_EVENTD_EGPI13            0X20
-#define DA9052_EVENTD_EGPI12            0X10
-#define DA9052_EVENTD_EGPI11            0X08
-#define DA9052_EVENTD_EGPI10            0X04
-#define DA9052_EVENTD_EGPI9             0X02
-#define DA9052_EVENTD_EGPI8             0X01
-
-/* IRQ MASK REGISTERS BITS */
-#define DA9052_M_NONKEY         0X0100
-
-/* TSI EVENT REGISTERS BITS */
-#define DA9052_E_PEN_DOWN               0X4000
-#define DA9052_E_TSI_READY              0X8000
-
-/* FAULT LOG REGISTER BITS */
-#define DA9052_FAULTLOG_WAITSET 0X80
-#define DA9052_FAULTLOG_NSDSET          0X40
-#define DA9052_FAULTLOG_KEYSHUT 0X20
-#define DA9052_FAULTLOG_TEMPOVER        0X08
-#define DA9052_FAULTLOG_VDDSTART        0X04
-#define DA9052_FAULTLOG_VDDFAULT        0X02
-#define DA9052_FAULTLOG_TWDERROR        0X01
-
-/* CONTROL REGISTER A BITS */
-#define DA9052_CONTROLA_GPIV            0X80
-#define DA9052_CONTROLA_PMOTYPE 0X20
-#define DA9052_CONTROLA_PMOV            0X10
-#define DA9052_CONTROLA_PMIV            0X08
-#define DA9052_CONTROLA_PMIFV           0X08
-#define DA9052_CONTROLA_PWR1EN          0X04
-#define DA9052_CONTROLA_PWREN           0X02
-#define DA9052_CONTROLA_SYSEN           0X01
-
-/* CONTROL REGISTER B BITS */
-#define DA9052_CONTROLB_SHUTDOWN        0X80
-#define DA9052_CONTROLB_DEEPSLEEP       0X40
-#define DA9052_CONTROL_B_WRITEMODE      0X20
-#define DA9052_CONTROLB_BBATEN          0X10
-#define DA9052_CONTROLB_OTPREADEN       0X08
-#define DA9052_CONTROLB_AUTOBOOT        0X04
-#define DA9052_CONTROLB_ACTDIODE        0X02
-#define DA9052_CONTROLB_BUCKMERGE       0X01
-
-/* CONTROL REGISTER C BITS */
-#define DA9052_CONTROLC_BLINKDUR        0X80
-#define DA9052_CONTROLC_BLINKFRQ        0X60
-#define DA9052_CONTROLC_DEBOUNCING      0X1C
-#define DA9052_CONTROLC_PMFB2PIN        0X02
-#define DA9052_CONTROLC_PMFB1PIN        0X01
-
-/* CONTROL REGISTER D BITS */
-#define DA9052_CONTROLD_WATCHDOG        0X80
-#define DA9052_CONTROLD_ACCDETEN        0X40
-#define DA9052_CONTROLD_GPI1415SD       0X20
-#define DA9052_CONTROLD_NONKEYSD        0X10
-#define DA9052_CONTROLD_KEEPACTEN       0X08
-#define DA9052_CONTROLD_TWDSCALE        0X07
-
-/* POWER DOWN DISABLE REGISTER BITS */
-#define DA9052_PDDIS_PMCONTPD           0X80
-#define DA9052_PDDIS_OUT32KPD           0X40
-#define DA9052_PDDIS_CHGBBATPD          0X20
-#define DA9052_PDDIS_CHGPD              0X10
-#define DA9052_PDDIS_HS2WIREPD          0X08
-#define DA9052_PDDIS_PMIFPD             0X04
-#define DA9052_PDDIS_GPADCPD            0X02
-#define DA9052_PDDIS_GPIOPD             0X01
-
-/* CONTROL REGISTER D BITS */
-#define DA9052_INTERFACE_IFBASEADDR     0XE0
-#define DA9052_INTERFACE_NCSPOL 0X10
-#define DA9052_INTERFACE_RWPOL          0X08
-#define DA9052_INTERFACE_CPHA           0X04
-#define DA9052_INTERFACE_CPOL           0X02
-#define DA9052_INTERFACE_IFTYPE 0X01
-
-/* CONTROL REGISTER D BITS */
-#define DA9052_RESET_RESETEVENT 0XC0
-#define DA9052_RESET_RESETTIMER 0X3F
-
-/* GPIO REGISTERS */
-/* GPIO CONTROL REGISTER BITS */
-#define DA9052_GPIO_EVEN_PORT_PIN       0X03
-#define DA9052_GPIO_EVEN_PORT_TYPE      0X04
-#define DA9052_GPIO_EVEN_PORT_MODE      0X08
-
-#define DA9052_GPIO_ODD_PORT_PIN        0X30
-#define DA9052_GPIO_ODD_PORT_TYPE       0X40
-#define DA9052_GPIO_ODD_PORT_MODE       0X80
-
-/*POWER SEQUENCER REGISTER BITS */
-/* SEQ CONTROL REGISTER BITS FOR ID 0 AND 1 */
-#define DA9052_ID01_LDO1STEP            0XF0
-#define DA9052_ID01_SYSPRE              0X04
-#define DA9052_ID01_DEFSUPPLY           0X02
-#define DA9052_ID01_NRESMODE            0X01
-
-/* SEQ CONTROL REGISTER BITS FOR ID 2 AND 3 */
-#define DA9052_ID23_LDO3STEP            0XF0
-#define DA9052_ID23_LDO2STEP            0X0F
-
-/* SEQ CONTROL REGISTER BITS FOR ID 4 AND 5 */
-#define DA9052_ID45_LDO5STEP            0XF0
-#define DA9052_ID45_LDO4STEP            0X0F
-
-/* SEQ CONTROL REGISTER BITS FOR ID 6 AND 7 */
-#define DA9052_ID67_LDO7STEP            0XF0
-#define DA9052_ID67_LDO6STEP            0X0F
-
-/* SEQ CONTROL REGISTER BITS FOR ID 8 AND 9 */
-#define DA9052_ID89_LDO9STEP            0XF0
-#define DA9052_ID89_LDO8STEP            0X0F
-
-/* SEQ CONTROL REGISTER BITS FOR ID 10 AND 11 */
-#define DA9052_ID1011_PDDISSTEP 0XF0
-#define DA9052_ID1011_LDO10STEP 0X0F
-
-/* SEQ CONTROL REGISTER BITS FOR ID 12 AND 13 */
-#define DA9052_ID1213_VMEMSWSTEP        0XF0
-#define DA9052_ID1213_VPERISWSTEP       0X0F
-
-/* SEQ CONTROL REGISTER BITS FOR ID 14 AND 15 */
-#define DA9052_ID1415_BUCKPROSTEP       0XF0
-#define DA9052_ID1415_BUCKCORESTEP      0X0F
-
-/* SEQ CONTROL REGISTER BITS FOR ID 16 AND 17 */
-#define DA9052_ID1617_BUCKPERISTEP      0XF0
-#define DA9052_ID1617_BUCKMEMSTEP       0X0F
-
-/* SEQ CONTROL REGISTER BITS FOR ID 18 AND 19 */
-#define DA9052_ID1819_GPRISE2STEP       0XF0
-#define DA9052_ID1819_GPRISE1STEP       0X0F
-
-/* SEQ CONTROL REGISTER BITS FOR ID 20 AND 21 */
-#define DA9052_ID2021_GPFALL2STEP       0XF0
-#define DA9052_ID2021_GPFALL1STEP       0X0F
-
-/* POWER SEQ STATUS REGISTER BITS */
-#define DA9052_SEQSTATUS_SEQPOINTER     0XF0
-#define DA9052_SEQSTATUS_WAITSTEP       0X0F
-
-/* POWER SEQ A REGISTER BITS */
-#define DA9052_SEQA_POWEREND            0XF0
-#define DA9052_SEQA_SYSTEMEND           0X0F
-
-/* POWER SEQ B REGISTER BITS */
-#define DA9052_SEQB_PARTDOWN            0XF0
-#define DA9052_SEQB_MAXCOUNT            0X0F
-
-/* POWER SEQ TIMER REGISTER BITS */
-#define DA9052_SEQTIMER_SEQDUMMY        0XF0
-#define DA9052_SEQTIMER_SEQTIME 0X0F
-
-/*POWER SUPPLY CONTROL REGISTER BITS */
-/* BUCK REGISTER A BITS */
-#define DA9052_BUCKA_BPROILIM           0XC0
-#define DA9052_BUCKA_BPROMODE           0X30
-#define DA9052_BUCKA_BCOREILIM          0X0C
-#define DA9052_BUCKA_BCOREMODE          0X03
-
-/* BUCK REGISTER B BITS */
-#define DA9052_BUCKB_BERIILIM           0XC0
-#define DA9052_BUCKB_BPERIMODE          0X30
-#define DA9052_BUCKB_BMEMILIM           0X0C
-#define DA9052_BUCKB_BMEMMODE           0X03
-
-/* BUCKCORE REGISTER BITS */
-#define DA9052_BUCKCORE_BCORECONF       0X80
-#define DA9052_BUCKCORE_BCOREEN 0X40
-#define DA9052_BUCKCORE_VBCORE          0X3F
-
-/* BUCKPRO REGISTER BITS */
-#define DA9052_BUCKPRO_BPROCONF 0X80
-#define DA9052_BUCKPRO_BPROEN           0X40
-#define DA9052_BUCKPRO_VBPRO            0X3F
-
-/* BUCKMEM REGISTER BITS */
-#define DA9052_BUCKMEM_BMEMCONF 0X80
-#define DA9052_BUCKMEM_BMEMEN           0X40
-#define DA9052_BUCKMEM_VBMEM            0X3F
-
-/* BUCKPERI REGISTER BITS */
-#define DA9052_BUCKPERI_BPERICONF       0X80
-#define DA9052_BUCKPERI_BPERIEN 0X40
-#define DA9052_BUCKPERI_BPERIHS 0X20
-#define DA9052_BUCKPERI_VBPERI          0X1F
-
-/* LDO1 REGISTER BITS */
-#define DA9052_LDO1_LDO1CONF            0X80
-#define DA9052_LDO1_LDO1EN              0X40
-#define DA9052_LDO1_VLDO1               0X1F
-
-/* LDO2 REGISTER BITS */
-#define DA9052_LDO2_LDO2CONF            0X80
-#define DA9052_LDO2_LDO2EN              0X40
-#define DA9052_LDO2_VLDO2               0X3F
-
-/* LDO3 REGISTER BITS */
-#define DA9052_LDO3_LDO3CONF            0X80
-#define DA9052_LDO3_LDO3EN              0X40
-#define DA9052_LDO3_VLDO3               0X3F
-
-/* LDO4 REGISTER BITS */
-#define DA9052_LDO4_LDO4CONF            0X80
-#define DA9052_LDO4_LDO4EN              0X40
-#define DA9052_LDO4_VLDO4               0X3F
-
-/* LDO5 REGISTER BITS */
-#define DA9052_LDO5_LDO5CONF            0X80
-#define DA9052_LDO5_LDO5EN              0X40
-#define DA9052_LDO5_VLDO5               0X3F
-
-/* LDO6 REGISTER BITS */
-#define DA9052_LDO6_LDO6CONF            0X80
-#define DA9052_LDO6_LDO6EN              0X40
-#define DA9052_LDO6_VLDO6               0X3F
-
-/* LDO7 REGISTER BITS */
-#define DA9052_LDO7_LDO7CONF            0X80
-#define DA9052_LDO7_LDO7EN              0X40
-#define DA9052_LDO7_VLDO7               0X3F
-
-/* LDO8 REGISTER BITS */
-#define DA9052_LDO8_LDO8CONF            0X80
-#define DA9052_LDO8_LDO8EN              0X40
-#define DA9052_LDO8_VLDO8               0X3F
-
-/* LDO9 REGISTER BITS */
-#define DA9052_LDO9_LDO9CONF            0X80
-#define DA9052_LDO9_LDO9EN              0X40
-#define DA9052_LDO9_VLDO9               0X3F
-
-/* LDO10 REGISTER BITS */
-#define DA9052_LDO10_LDO10CONF          0X80
-#define DA9052_LDO10_LDO10EN            0X40
-#define DA9052_LDO10_VLDO10             0X3F
-
-/* SUPPLY REGISTER BITS */
-#define DA9052_SUPPLY_VLOCK             0X80
-#define DA9052_SUPPLY_VMEMSWEN          0X40
-#define DA9052_SUPPLY_VPERISWEN 0X20
-#define DA9052_SUPPLY_VLDO3GO           0X10
-#define DA9052_SUPPLY_VLDO2GO           0X08
-#define DA9052_SUPPLY_VBMEMGO           0X04
-#define DA9052_SUPPLY_VBPROGO           0X02
-#define DA9052_SUPPLY_VBCOREGO          0X01
-
-/* PULLDOWN REGISTER BITS */
-#define DA9052_PULLDOWN_LDO5PDDIS       0X20
-#define DA9052_PULLDOWN_LDO2PDDIS       0X10
-#define DA9052_PULLDOWN_LDO1PDDIS       0X08
-#define DA9052_PULLDOWN_MEMPDDIS        0X04
-#define DA9052_PULLDOWN_PROPDDIS        0X02
-#define DA9052_PULLDOWN_COREPDDIS       0X01
-
-/* BAT CHARGER REGISTER BITS */
-/* CHARGER BUCK REGISTER BITS */
-#define DA9052_CHGBUCK_CHGTEMP          0X80
-#define DA9052_CHGBUCK_CHGUSBILIM       0X40
-#define DA9052_CHGBUCK_CHGBUCKLP        0X20
-#define DA9052_CHGBUCK_CHGBUCKEN        0X10
-#define DA9052_CHGBUCK_ISETBUCK 0X0F
-
-/* WAIT COUNTER REGISTER BITS */
-#define DA9052_WAITCONT_WAITDIR 0X80
-#define DA9052_WAITCONT_RTCCLOCK        0X40
-#define DA9052_WAITCONT_WAITMODE        0X20
-#define DA9052_WAITCONT_EN32KOUT        0X10
-#define DA9052_WAITCONT_DELAYTIME       0X0F
-
-/* ISET CONTROL REGISTER BITS */
-#define DA9052_ISET_ISETDCIN            0XF0
-#define DA9052_ISET_ISETVBUS            0X0F
-
-/* BATTERY CHARGER CONTROL REGISTER BITS */
-#define DA9052_BATCHG_ICHGPRE           0XC0
-#define DA9052_BATCHG_ICHGBAT           0X3F
-
-/* CHARGER COUNTER REGISTER BITS */
-#define DA9052_CHG_CONT_VCHG_BAT        0XF8
-#define DA9052_CHG_CONT_TCTR            0X07
-
-/* INPUT CONTROL REGISTER BITS */
-#define DA9052_INPUT_CONT_TCTR_MODE     0X80
-#define DA9052_INPUT_CONT_VBUS_SUSP     0X10
-#define DA9052_INPUT_CONT_DCIN_SUSP     0X08
-
-/* CHARGING TIME REGISTER BITS */
-#define DA9052_CHGTIME_CHGTIME          0XFF
-
-/* BACKUP BATTERY CONTROL REGISTER BITS */
-#define DA9052_BBATCONT_BCHARGERISET    0XF0
-#define DA9052_BBATCONT_BCHARGERVSET    0X0F
-
-/* LED REGISTERS BITS */
-/* LED BOOST REGISTER BITS */
-#define DA9052_BOOST_EBFAULT            0X80
-#define DA9052_BOOST_MBFAULT            0X40
-#define DA9052_BOOST_BOOSTFRQ           0X20
-#define DA9052_BOOST_BOOSTILIM          0X10
-#define DA9052_BOOST_LED3INEN           0X08
-#define DA9052_BOOST_LED2INEN           0X04
-#define DA9052_BOOST_LED1INEN           0X02
-#define DA9052_BOOST_BOOSTEN            0X01
-
-/* LED CONTROL REGISTER BITS */
-#define DA9052_LEDCONT_SELLEDMODE       0X80
-#define DA9052_LEDCONT_LED3ICONT        0X40
-#define DA9052_LEDCONT_LED3RAMP 0X20
-#define DA9052_LEDCONT_LED3EN           0X10
-#define DA9052_LEDCONT_LED2RAMP 0X08
-#define DA9052_LEDCONT_LED2EN           0X04
-#define DA9052_LEDCONT_LED1RAMP 0X02
-#define DA9052_LEDCONT_LED1EN           0X01
-
-/* LEDMIN123 REGISTER BIT */
-#define DA9052_LEDMIN123_LEDMINCURRENT  0XFF
-
-/* LED1CONF REGISTER BIT */
-#define DA9052_LED1CONF_LED1CURRENT     0XFF
-
-/* LED2CONF REGISTER BIT */
-#define DA9052_LED2CONF_LED2CURRENT     0XFF
-
-/* LED3CONF REGISTER BIT */
-#define DA9052_LED3CONF_LED3CURRENT     0XFF
-
-/* LED COUNT REGISTER BIT */
-#define DA9052_LED_CONT_DIM             0X80
-
-/* ADC MAN REGISTERS BITS */
-#define DA9052_ADC_MAN_MAN_CONV 0X10
-#define DA9052_ADC_MAN_MUXSEL_VDDOUT    0X00
-#define DA9052_ADC_MAN_MUXSEL_ICH       0X01
-#define DA9052_ADC_MAN_MUXSEL_TBAT      0X02
-#define DA9052_ADC_MAN_MUXSEL_VBAT      0X03
-#define DA9052_ADC_MAN_MUXSEL_AD4       0X04
-#define DA9052_ADC_MAN_MUXSEL_AD5       0X05
-#define DA9052_ADC_MAN_MUXSEL_AD6       0X06
-#define DA9052_ADC_MAN_MUXSEL_VBBAT     0X09
-
-/* ADC CONTROL REGSISTERS BITS */
-#define DA9052_ADCCONT_COMP1V2EN        0X80
-#define DA9052_ADCCONT_ADCMODE          0X40
-#define DA9052_ADCCONT_TBATISRCEN       0X20
-#define DA9052_ADCCONT_AD4ISRCEN        0X10
-#define DA9052_ADCCONT_AUTOAD6EN        0X08
-#define DA9052_ADCCONT_AUTOAD5EN        0X04
-#define DA9052_ADCCONT_AUTOAD4EN        0X02
-#define DA9052_ADCCONT_AUTOVDDEN        0X01
-
-/* ADC 10 BIT MANUAL CONVERSION RESULT LOW REGISTER */
-#define DA9052_ADC_RES_LSB              0X03
-
-/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH REGISTER */
-#define DA9052_ADCRESH_ADCRESMSB        0XFF
-
-/* VDD RES REGSISTER BIT*/
-#define DA9052_VDDRES_VDDOUTRES 0XFF
-
-/* VDD MON REGSISTER BIT */
-#define DA9052_VDDMON_VDDOUTMON 0XFF
-
-/* ICHG_AV REGSISTER BIT */
-#define DA9052_ICHGAV_ICHGAV            0XFF
-
-/* ICHG_THD REGSISTER BIT */
-#define DA9052_ICHGTHD_ICHGTHD          0XFF
-
-/* ICHG_END REGSISTER BIT */
-#define DA9052_ICHGEND_ICHGEND          0XFF
-
-/* TBAT_RES REGSISTER BIT */
-#define DA9052_TBATRES_TBATRES          0XFF
-
-/* TBAT_HIGHP REGSISTER BIT */
-#define DA9052_TBATHIGHP_TBATHIGHP      0XFF
-
-/* TBAT_HIGHN REGSISTER BIT */
-#define DA9052_TBATHIGHN_TBATHIGHN      0XFF
-
-/* TBAT_LOW REGSISTER BIT */
-#define DA9052_TBATLOW_TBATLOW          0XFF
-
-/* T_OFFSET REGSISTER BIT */
-#define DA9052_TOFFSET_TOFFSET          0XFF
-
-/* ADCIN4_RES REGSISTER BIT */
-#define DA9052_ADCIN4RES_ADCIN4RES      0XFF
-
-/* ADCIN4_HIGH REGSISTER BIT */
-#define DA9052_AUTO4HIGH_AUTO4HIGH      0XFF
-
-/* ADCIN4_LOW REGSISTER BIT */
-#define DA9052_AUTO4LOW_AUTO4LOW        0XFF
-
-/* ADCIN5_RES REGSISTER BIT */
-#define DA9052_ADCIN5RES_ADCIN5RES      0XFF
-
-/* ADCIN5_HIGH REGSISTER BIT */
-#define DA9052_AUTO5HIGH_AUTOHIGH       0XFF
-
-/* ADCIN5_LOW REGSISTER BIT */
-#define DA9052_AUTO5LOW_AUTO5LOW        0XFF
-
-/* ADCIN6_RES REGSISTER BIT */
-#define DA9052_ADCIN6RES_ADCIN6RES      0XFF
-
-/* ADCIN6_HIGH REGSISTER BIT */
-#define DA9052_AUTO6HIGH_AUTO6HIGH      0XFF
-
-/* ADCIN6_LOW REGSISTER BIT */
-#define DA9052_AUTO6LOW_AUTO6LOW        0XFF
-
-/* TJUNC_RES REGSISTER BIT*/
-#define DA9052_TJUNCRES_TJUNCRES        0XFF
-
-/* TSI REGISTER */
-/* TSI CONTROL REGISTER A BITS */
-#define DA9052_TSICONTA_TSIDELAY        0XC0
-#define DA9052_TSICONTA_TSISKIP 0X38
-#define DA9052_TSICONTA_TSIMODE 0X04
-#define DA9052_TSICONTA_PENDETEN        0X02
-#define DA9052_TSICONTA_AUTOTSIEN       0X01
-
-/* TSI CONTROL REGISTER B BITS */
-#define DA9052_TSICONTB_ADCREF          0X80
-#define DA9052_TSICONTB_TSIMAN          0X40
-#define DA9052_TSICONTB_TSIMUX          0X30
-#define DA9052_TSICONTB_TSISEL3 0X08
-#define DA9052_TSICONTB_TSISEL2 0X04
-#define DA9052_TSICONTB_TSISEL1 0X02
-#define DA9052_TSICONTB_TSISEL0 0X01
-
-/* TSI X CO-ORDINATE MSB RESULT REGISTER BITS */
-#define DA9052_TSIXMSB_TSIXM            0XFF
-
-/* TSI Y CO-ORDINATE MSB RESULT REGISTER BITS */
-#define DA9052_TSIYMSB_TSIYM            0XFF
-
-/* TSI CO-ORDINATE LSB RESULT REGISTER BITS */
-#define DA9052_TSILSB_PENDOWN           0X40
-#define DA9052_TSILSB_TSIZL             0X30
-#define DA9052_TSILSB_TSIYL             0X0C
-#define DA9052_TSILSB_TSIXL             0X03
-
-/* TSI Z MEASUREMENT MSB RESULT REGISTER BIT */
-#define DA9052_TSIZMSB_TSIZM            0XFF
-
-/* RTC REGISTER */
-/* RTC TIMER SECONDS REGISTER BITS */
-#define DA9052_COUNTS_MONITOR           0X40
-#define DA9052_RTC_SEC                  0X3F
-
-/* RTC TIMER MINUTES REGISTER BIT */
-#define DA9052_RTC_MIN                  0X3F
-
-/* RTC TIMER HOUR REGISTER BIT */
-#define DA9052_RTC_HOUR         0X1F
-
-/* RTC TIMER DAYS REGISTER BIT */
-#define DA9052_RTC_DAY                  0X1F
-
-/* RTC TIMER MONTHS REGISTER BIT */
-#define DA9052_RTC_MONTH                0X0F
-
-/* RTC TIMER YEARS REGISTER BIT */
-#define DA9052_RTC_YEAR         0X3F
-
-/* RTC ALARM MINUTES REGISTER BITS */
-#define DA9052_ALARMM_I_TICK_TYPE       0X80
-#define DA9052_ALARMMI_ALARMTYPE        0X40
-
-/* RTC ALARM YEARS REGISTER BITS */
-#define DA9052_ALARM_Y_TICK_ON          0X80
-#define DA9052_ALARM_Y_ALARM_ON 0X40
-
-/* RTC SECONDS REGISTER A BITS */
-#define DA9052_SECONDA_SECONDSA 0XFF
-
-/* RTC SECONDS REGISTER B BITS */
-#define DA9052_SECONDB_SECONDSB 0XFF
-
-/* RTC SECONDS REGISTER C BITS */
-#define DA9052_SECONDC_SECONDSC 0XFF
-
-/* RTC SECONDS REGISTER D BITS */
-#define DA9052_SECONDD_SECONDSD 0XFF
-
-#endif
-/* __LINUX_MFD_DA9052_REG_H */
diff --git a/include/linux/mfd/da9055/core.h b/include/linux/mfd/da9055/core.h
deleted file mode 100644
index 956afa44599..00000000000
--- a/include/linux/mfd/da9055/core.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * da9055 declarations for DA9055 PMICs.
- *
- * Copyright(c) 2012 Dialog Semiconductor Ltd.
- *
- * Author: David Dajun Chen <dchen@diasemi.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __DA9055_CORE_H
-#define __DA9055_CORE_H
-
-#include <linux/interrupt.h>
-#include <linux/regmap.h>
-
-/*
- * PMIC IRQ
- */
-#define DA9055_IRQ_ALARM        0x01
-#define DA9055_IRQ_TICK         0x02
-#define DA9055_IRQ_NONKEY       0x00
-#define DA9055_IRQ_REGULATOR    0x0B
-#define DA9055_IRQ_HWMON        0x03
-
-struct da9055_pdata;
-
-struct da9055 {
-        struct regmap *regmap;
-        struct regmap_irq_chip_data *irq_data;
-        struct device *dev;
-        struct i2c_client *i2c_client;
-
-        int irq_base;
-        int chip_irq;
-};
-
-/* Device I/O */
-static inline int da9055_reg_read(struct da9055 *da9055, unsigned char reg)
-{
-        int val, ret;
-
-        ret = regmap_read(da9055->regmap, reg, &val);
-        if (ret < 0)
-                return ret;
-
-        return val;
-}
-
-static inline int da9055_reg_write(struct da9055 *da9055, unsigned char reg,
-                                    unsigned char val)
-{
-        return regmap_write(da9055->regmap, reg, val);
-}
-
-static inline int da9055_group_read(struct da9055 *da9055, unsigned char reg,
-                                     unsigned reg_cnt, unsigned char *val)
-{
-        return regmap_bulk_read(da9055->regmap, reg, val, reg_cnt);
-}
-
-static inline int da9055_group_write(struct da9055 *da9055, unsigned char reg,
-                                      unsigned reg_cnt, unsigned char *val)
-{
-        return regmap_raw_write(da9055->regmap, reg, val, reg_cnt);
-}
-
-static inline int da9055_reg_update(struct da9055 *da9055, unsigned char reg,
-                                     unsigned char bit_mask,
-                                     unsigned char reg_val)
-{
-        return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val);
-}
-
-/* Generic Device API */
-int da9055_device_init(struct da9055 *da9055);
-void da9055_device_exit(struct da9055 *da9055);
-
-extern struct regmap_config da9055_regmap_config;
-
-#endif /* __DA9055_CORE_H */
diff --git a/include/linux/mfd/da9055/pdata.h b/include/linux/mfd/da9055/pdata.h
deleted file mode 100644
index 04e092be4b0..00000000000
--- a/include/linux/mfd/da9055/pdata.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright (C) 2012 Dialog Semiconductor Ltd.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- */
-#ifndef __DA9055_PDATA_H
-#define __DA9055_PDATA_H
-
-#define DA9055_MAX_REGULATORS   8
-
-struct da9055;
-
-enum gpio_select {
-        NO_GPIO = 0,
-        GPIO_1,
-        GPIO_2
-};
-
-struct da9055_pdata {
-        int (*init) (struct da9055 *da9055);
-        int irq_base;
-        int gpio_base;
-
-        struct regulator_init_data *regulators[DA9055_MAX_REGULATORS];
-        /* Enable RTC in RESET Mode */
-        bool reset_enable;
-        /*
-         * GPI muxed pin to control
-         * regulator state A/B, 0 if not available.
-         */
-        int *gpio_ren;
-        /*
-         * GPI muxed pin to control
-         * regulator set, 0 if not available.
-         */
-        int *gpio_rsel;
-        /*
-         * Regulator mode control bits value (GPI offset) that
-         * that controls the regulator state, 0 if not available.
-         */
-        enum gpio_select *reg_ren;
-        /*
-         * Regulator mode control bits value (GPI offset) that
-         * controls the regulator set A/B, 0 if  not available.
-         */
-        enum gpio_select *reg_rsel;
-        /* GPIOs to enable regulator, 0 if not available */
-        int *ena_gpio;
-};
-#endif /* __DA9055_PDATA_H */
diff --git a/include/linux/mfd/da9055/reg.h b/include/linux/mfd/da9055/reg.h
deleted file mode 100644
index 2b592e072db..00000000000
--- a/include/linux/mfd/da9055/reg.h
+++ /dev/null
@@ -1,699 +0,0 @@
-/*
- * DA9055 declarations for DA9055 PMICs.
- *
- * Copyright(c) 2012 Dialog Semiconductor Ltd.
- *
- * Author: David Dajun Chen <dchen@diasemi.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __DA9055_REG_H
-#define __DA9055_REG_H
-
-/*
- * PMIC registers
- */
- /* PAGE0 */
-#define DA9055_REG_PAGE_CON             0x00
-
-/* System Control and Event Registers */
-#define DA9055_REG_STATUS_A             0x01
-#define DA9055_REG_STATUS_B             0x02
-#define DA9055_REG_FAULT_LOG            0x03
-#define DA9055_REG_EVENT_A              0x04
-#define DA9055_REG_EVENT_B              0x05
-#define DA9055_REG_EVENT_C              0x06
-#define DA9055_REG_IRQ_MASK_A           0x07
-#define DA9055_REG_IRQ_MASK_B           0x08
-#define DA9055_REG_IRQ_MASK_C           0x09
-#define DA9055_REG_CONTROL_A            0x0A
-#define DA9055_REG_CONTROL_B            0x0B
-#define DA9055_REG_CONTROL_C            0x0C
-#define DA9055_REG_CONTROL_D            0x0D
-#define DA9055_REG_CONTROL_E            0x0E
-#define DA9055_REG_PD_DIS               0x0F
-
-/* GPIO Control Registers */
-#define DA9055_REG_GPIO0_1              0x10
-#define DA9055_REG_GPIO2                0x11
-#define DA9055_REG_GPIO_MODE0_2         0x12
-
-/* Regulator Control Registers */
-#define DA9055_REG_BCORE_CONT           0x13
-#define DA9055_REG_BMEM_CONT            0x14
-#define DA9055_REG_LDO1_CONT            0x15
-#define DA9055_REG_LDO2_CONT            0x16
-#define DA9055_REG_LDO3_CONT            0x17
-#define DA9055_REG_LDO4_CONT            0x18
-#define DA9055_REG_LDO5_CONT            0x19
-#define DA9055_REG_LDO6_CONT            0x1A
-
-/* GP-ADC Control Registers */
-#define DA9055_REG_ADC_MAN              0x1B
-#define DA9055_REG_ADC_CONT             0x1C
-#define DA9055_REG_VSYS_MON             0x1D
-#define DA9055_REG_ADC_RES_L            0x1E
-#define DA9055_REG_ADC_RES_H            0x1F
-#define DA9055_REG_VSYS_RES             0x20
-#define DA9055_REG_ADCIN1_RES           0x21
-#define DA9055_REG_ADCIN2_RES           0x22
-#define DA9055_REG_ADCIN3_RES           0x23
-
-/* Sequencer Control Registers */
-#define DA9055_REG_EN_32K               0x35
-
-/* Regulator Setting Registers */
-#define DA9055_REG_BUCK_LIM             0x37
-#define DA9055_REG_BCORE_MODE           0x38
-#define DA9055_REG_VBCORE_A             0x39
-#define DA9055_REG_VBMEM_A              0x3A
-#define DA9055_REG_VLDO1_A              0x3B
-#define DA9055_REG_VLDO2_A              0x3C
-#define DA9055_REG_VLDO3_A              0x3D
-#define DA9055_REG_VLDO4_A              0x3E
-#define DA9055_REG_VLDO5_A              0x3F
-#define DA9055_REG_VLDO6_A              0x40
-#define DA9055_REG_VBCORE_B             0x41
-#define DA9055_REG_VBMEM_B              0x42
-#define DA9055_REG_VLDO1_B              0x43
-#define DA9055_REG_VLDO2_B              0x44
-#define DA9055_REG_VLDO3_B              0x45
-#define DA9055_REG_VLDO4_B              0x46
-#define DA9055_REG_VLDO5_B              0x47
-#define DA9055_REG_VLDO6_B              0x48
-
-/* GP-ADC Threshold Registers */
-#define DA9055_REG_AUTO1_HIGH           0x49
-#define DA9055_REG_AUTO1_LOW            0x4A
-#define DA9055_REG_AUTO2_HIGH           0x4B
-#define DA9055_REG_AUTO2_LOW            0x4C
-#define DA9055_REG_AUTO3_HIGH           0x4D
-#define DA9055_REG_AUTO3_LOW            0x4E
-
-/* OTP */
-#define DA9055_REG_OPT_COUNT            0x50
-#define DA9055_REG_OPT_ADDR             0x51
-#define DA9055_REG_OPT_DATA             0x52
-
-/* RTC Calendar and Alarm Registers */
-#define DA9055_REG_COUNT_S              0x53
-#define DA9055_REG_COUNT_MI             0x54
-#define DA9055_REG_COUNT_H              0x55
-#define DA9055_REG_COUNT_D              0x56
-#define DA9055_REG_COUNT_MO             0x57
-#define DA9055_REG_COUNT_Y              0x58
-#define DA9055_REG_ALARM_MI             0x59
-#define DA9055_REG_ALARM_H              0x5A
-#define DA9055_REG_ALARM_D              0x5B
-#define DA9055_REG_ALARM_MO             0x5C
-#define DA9055_REG_ALARM_Y              0x5D
-#define DA9055_REG_SECOND_A             0x5E
-#define DA9055_REG_SECOND_B             0x5F
-#define DA9055_REG_SECOND_C             0x60
-#define DA9055_REG_SECOND_D             0x61
-
-/* Customer Trim and Configuration */
-#define DA9055_REG_T_OFFSET             0x63
-#define DA9055_REG_INTERFACE            0x64
-#define DA9055_REG_CONFIG_A             0x65
-#define DA9055_REG_CONFIG_B             0x66
-#define DA9055_REG_CONFIG_C             0x67
-#define DA9055_REG_CONFIG_D             0x68
-#define DA9055_REG_CONFIG_E             0x69
-#define DA9055_REG_TRIM_CLDR            0x6F
-
-/* General Purpose Registers */
-#define DA9055_REG_GP_ID_0              0x70
-#define DA9055_REG_GP_ID_1              0x71
-#define DA9055_REG_GP_ID_2              0x72
-#define DA9055_REG_GP_ID_3              0x73
-#define DA9055_REG_GP_ID_4              0x74
-#define DA9055_REG_GP_ID_5              0x75
-#define DA9055_REG_GP_ID_6              0x76
-#define DA9055_REG_GP_ID_7              0x77
-#define DA9055_REG_GP_ID_8              0x78
-#define DA9055_REG_GP_ID_9              0x79
-#define DA9055_REG_GP_ID_10             0x7A
-#define DA9055_REG_GP_ID_11             0x7B
-#define DA9055_REG_GP_ID_12             0x7C
-#define DA9055_REG_GP_ID_13             0x7D
-#define DA9055_REG_GP_ID_14             0x7E
-#define DA9055_REG_GP_ID_15             0x7F
-#define DA9055_REG_GP_ID_16             0x80
-#define DA9055_REG_GP_ID_17             0x81
-#define DA9055_REG_GP_ID_18             0x82
-#define DA9055_REG_GP_ID_19             0x83
-
-#define DA9055_MAX_REGISTER_CNT         DA9055_REG_GP_ID_19
-
-/*
- * PMIC registers bits
- */
-
-/* DA9055_REG_PAGE_CON (addr=0x00) */
-#define DA9055_PAGE_WRITE_MODE          (0<<6)
-#define DA9055_REPEAT_WRITE_MODE        (1<<6)
-
-/* DA9055_REG_STATUS_A (addr=0x01) */
-#define DA9055_NOKEY_STS                0x01
-#define DA9055_WAKE_STS                 0x02
-#define DA9055_DVC_BUSY_STS             0x04
-#define DA9055_COMP1V2_STS              0x08
-#define DA9055_NJIG_STS                 0x10
-#define DA9055_LDO5_LIM_STS             0x20
-#define DA9055_LDO6_LIM_STS             0x40
-
-/* DA9055_REG_STATUS_B (addr=0x02) */
-#define DA9055_GPI0_STS                 0x01
-#define DA9055_GPI1_STS                 0x02
-#define DA9055_GPI2_STS                 0x04
-
-/* DA9055_REG_FAULT_LOG (addr=0x03) */
-#define DA9055_TWD_ERROR_FLG            0x01
-#define DA9055_POR_FLG                  0x02
-#define DA9055_VDD_FAULT_FLG            0x04
-#define DA9055_VDD_START_FLG            0x08
-#define DA9055_TEMP_CRIT_FLG            0x10
-#define DA9055_KEY_RESET_FLG            0x20
-#define DA9055_WAIT_SHUT_FLG            0x80
-
-/* DA9055_REG_EVENT_A (addr=0x04) */
-#define DA9055_NOKEY_EINT               0x01
-#define DA9055_ALARM_EINT               0x02
-#define DA9055_TICK_EINT                0x04
-#define DA9055_ADC_RDY_EINT             0x08
-#define DA9055_SEQ_RDY_EINT             0x10
-#define DA9055_EVENTS_B_EINT            0x20
-#define DA9055_EVENTS_C_EINT            0x40
-
-/* DA9055_REG_EVENT_B (addr=0x05) */
-#define DA9055_E_WAKE_EINT              0x01
-#define DA9055_E_TEMP_EINT              0x02
-#define DA9055_E_COMP1V2_EINT           0x04
-#define DA9055_E_LDO_LIM_EINT           0x08
-#define DA9055_E_NJIG_EINT              0x20
-#define DA9055_E_VDD_MON_EINT           0x40
-#define DA9055_E_VDD_WARN_EINT          0x80
-
-/* DA9055_REG_EVENT_C (addr=0x06) */
-#define DA9055_E_GPI0_EINT              0x01
-#define DA9055_E_GPI1_EINT              0x02
-#define DA9055_E_GPI2_EINT              0x04
-
-/* DA9055_REG_IRQ_MASK_A (addr=0x07) */
-#define DA9055_M_NONKEY_EINT            0x01
-#define DA9055_M_ALARM_EINT             0x02
-#define DA9055_M_TICK_EINT              0x04
-#define DA9055_M_ADC_RDY_EINT           0x08
-#define DA9055_M_SEQ_RDY_EINT           0x10
-
-/* DA9055_REG_IRQ_MASK_B (addr=0x08) */
-#define DA9055_M_WAKE_EINT              0x01
-#define DA9055_M_TEMP_EINT              0x02
-#define DA9055_M_COMP_1V2_EINT          0x04
-#define DA9055_M_LDO_LIM_EINT           0x08
-#define DA9055_M_NJIG_EINT              0x20
-#define DA9055_M_VDD_MON_EINT           0x40
-#define DA9055_M_VDD_WARN_EINT          0x80
-
-/* DA9055_REG_IRQ_MASK_C (addr=0x09) */
-#define DA9055_M_GPI0_EINT              0x01
-#define DA9055_M_GPI1_EINT              0x02
-#define DA9055_M_GPI2_EINT              0x04
-
-/* DA9055_REG_CONTROL_A (addr=0xA) */
-#define DA9055_DEBOUNCING_SHIFT         0x00
-#define DA9055_DEBOUNCING_MASK          0x07
-#define DA9055_NRES_MODE_SHIFT          0x03
-#define DA9055_NRES_MODE_MASK           0x08
-#define DA9055_SLEW_RATE_SHIFT          0x04
-#define DA9055_SLEW_RATE_MASK           0x30
-#define DA9055_NOKEY_LOCK_SHIFT         0x06
-#define DA9055_NOKEY_LOCK_MASK          0x40
-
-/* DA9055_REG_CONTROL_B (addr=0xB) */
-#define DA9055_RTC_MODE_PD              0x01
-#define DA9055_RTC_MODE_SD_SHIFT        0x01
-#define DA9055_RTC_MODE_SD              0x02
-#define DA9055_RTC_EN                   0x04
-#define DA9055_ECO_MODE_SHIFT           0x03
-#define DA9055_ECO_MODE_MASK            0x08
-#define DA9055_TWDSCALE_SHIFT           4
-#define DA9055_TWDSCALE_MASK            0x70
-#define DA9055_V_LOCK_SHIFT             0x07
-#define DA9055_V_LOCK_MASK              0x80
-
-/* DA9055_REG_CONTROL_C (addr=0xC) */
-#define DA9055_SYSTEM_EN_SHIFT          0x00
-#define DA9055_SYSTEM_EN_MASK           0x01
-#define DA9055_POWERN_EN_SHIFT          0x01
-#define DA9055_POWERN_EN_MASK           0x02
-#define DA9055_POWER1_EN_SHIFT          0x02
-#define DA9055_POWER1_EN_MASK           0x04
-
-/* DA9055_REG_CONTROL_D (addr=0xD) */
-#define DA9055_STANDBY_SHIFT            0x02
-#define DA9055_STANDBY_MASK             0x08
-#define DA9055_AUTO_BOOT_SHIFT          0x03
-#define DA9055_AUTO_BOOT_MASK           0x04
-
-/* DA9055_REG_CONTROL_E (addr=0xE) */
-#define DA9055_WATCHDOG_SHIFT           0x00
-#define DA9055_WATCHDOG_MASK            0x01
-#define DA9055_SHUTDOWN_SHIFT           0x01
-#define DA9055_SHUTDOWN_MASK            0x02
-#define DA9055_WAKE_UP_SHIFT            0x02
-#define DA9055_WAKE_UP_MASK             0x04
-
-/* DA9055_REG_GPIO (addr=0x10/0x11) */
-#define DA9055_GPIO0_PIN_SHIFT          0x00
-#define DA9055_GPIO0_PIN_MASK           0x03
-#define DA9055_GPIO0_TYPE_SHIFT         0x02
-#define DA9055_GPIO0_TYPE_MASK          0x04
-#define DA9055_GPIO0_WEN_SHIFT          0x03
-#define DA9055_GPIO0_WEN_MASK           0x08
-#define DA9055_GPIO1_PIN_SHIFT          0x04
-#define DA9055_GPIO1_PIN_MASK           0x30
-#define DA9055_GPIO1_TYPE_SHIFT         0x06
-#define DA9055_GPIO1_TYPE_MASK          0x40
-#define DA9055_GPIO1_WEN_SHIFT          0x07
-#define DA9055_GPIO1_WEN_MASK           0x80
-#define DA9055_GPIO2_PIN_SHIFT          0x00
-#define DA9055_GPIO2_PIN_MASK           0x30
-#define DA9055_GPIO2_TYPE_SHIFT         0x02
-#define DA9055_GPIO2_TYPE_MASK          0x04
-#define DA9055_GPIO2_WEN_SHIFT          0x03
-#define DA9055_GPIO2_WEN_MASK           0x08
-
-/* DA9055_REG_GPIO_MODE (addr=0x12) */
-#define DA9055_GPIO0_MODE_SHIFT         0x00
-#define DA9055_GPIO0_MODE_MASK          0x01
-#define DA9055_GPIO1_MODE_SHIFT         0x01
-#define DA9055_GPIO1_MODE_MASK          0x02
-#define DA9055_GPIO2_MODE_SHIFT         0x02
-#define DA9055_GPIO2_MODE_MASK          0x04
-
-/* DA9055_REG_BCORE_CONT (addr=0x13) */
-#define DA9055_BCORE_EN_SHIFT           0x00
-#define DA9055_BCORE_EN_MASK            0x01
-#define DA9055_BCORE_GPI_SHIFT          0x01
-#define DA9055_BCORE_GPI_MASK           0x02
-#define DA9055_BCORE_PD_DIS_SHIFT       0x03
-#define DA9055_BCORE_PD_DIS_MASK        0x04
-#define DA9055_VBCORE_SEL_SHIFT         0x04
-#define DA9055_SEL_REG_A                0x0
-#define DA9055_SEL_REG_B                0x10
-#define DA9055_VBCORE_SEL_MASK          0x10
-#define DA9055_V_GPI_MASK               0x60
-#define DA9055_V_GPI_SHIFT              0x05
-#define DA9055_E_GPI_MASK               0x06
-#define DA9055_E_GPI_SHIFT              0x01
-#define DA9055_VBCORE_GPI_SHIFT         0x05
-#define DA9055_VBCORE_GPI_MASK          0x60
-#define DA9055_BCORE_CONF_SHIFT         0x07
-#define DA9055_BCORE_CONF_MASK          0x80
-
-/* DA9055_REG_BMEM_CONT (addr=0x14) */
-#define DA9055_BMEM_EN_SHIFT            0x00
-#define DA9055_BMEM_EN_MASK             0x01
-#define DA9055_BMEM_GPI_SHIFT           0x01
-#define DA9055_BMEM_GPI_MASK            0x06
-#define DA9055_BMEM_PD_DIS_SHIFT        0x03
-#define DA9055_BMEM_PD_DIS_MASK         0x08
-#define DA9055_VBMEM_SEL_SHIT           0x04
-#define DA9055_VBMEM_SEL_VBMEM_A        (0<<4)
-#define DA9055_VBMEM_SEL_VBMEM_B        (1<<4)
-#define DA9055_VBMEM_SEL_MASK           0x10
-#define DA9055_VBMEM_GPI_SHIFT          0x05
-#define DA9055_VBMEM_GPI_MASK           0x60
-#define DA9055_BMEM_CONF_SHIFT          0x07
-#define DA9055_BMEM_CONF_MASK           0x80
-
-/* DA9055_REG_LDO_CONT (addr=0x15-0x1A) */
-#define DA9055_LDO_EN_SHIFT             0x00
-#define DA9055_LDO_EN_MASK              0x01
-#define DA9055_LDO_GPI_SHIFT            0x01
-#define DA9055_LDO_GPI_MASK             0x06
-#define DA9055_LDO_PD_DIS_SHIFT         0x03
-#define DA9055_LDO_PD_DIS_MASK          0x08
-#define DA9055_VLDO_SEL_SHIFT           0x04
-#define DA9055_VLDO_SEL_MASK            0x10
-#define DA9055_VLDO_SEL_VLDO_A          0x00
-#define DA9055_VLDO_SEL_VLDO_B          0x01
-#define DA9055_VLDO_GPI_SHIFT           0x05
-#define DA9055_VLDO_GPI_MASK            0x60
-#define DA9055_LDO_CONF_SHIFT           0x07
-#define DA9055_LDO_CONF_MASK            0x80
-#define DA9055_REGUALTOR_SET_A          0x00
-#define DA9055_REGUALTOR_SET_B          0x10
-
-/* DA9055_REG_ADC_MAN (addr=0x1B) */
-#define DA9055_ADC_MUX_SHIFT            0
-#define DA9055_ADC_MUX_MASK             0xF
-#define DA9055_ADC_MUX_VSYS             0x0
-#define DA9055_ADC_MUX_ADCIN1           0x01
-#define DA9055_ADC_MUX_ADCIN2           0x02
-#define DA9055_ADC_MUX_ADCIN3           0x03
-#define DA9055_ADC_MUX_T_SENSE          0x04
-#define DA9055_ADC_MAN_SHIFT            0x04
-#define DA9055_ADC_MAN_CONV             0x10
-#define DA9055_ADC_LSB_MASK             0X03
-#define DA9055_ADC_MODE_MASK            0x20
-#define DA9055_ADC_MODE_SHIFT           5
-#define DA9055_ADC_MODE_1MS             (1<<5)
-#define DA9055_COMP1V2_EN_SHIFT         7
-
-/* DA9055_REG_ADC_CONT (addr=0x1C) */
-#define DA9055_ADC_AUTO_VSYS_EN_SHIFT   0
-#define DA9055_ADC_AUTO_AD1_EN_SHIFT    1
-#define DA9055_ADC_AUTO_AD2_EN_SHIFT    2
-#define DA9055_ADC_AUTO_AD3_EN_SHIFT    3
-#define DA9055_ADC_ISRC_EN_SHIFT        4
-#define DA9055_ADC_ADCIN1_DEB_SHIFT     5
-#define DA9055_ADC_ADCIN2_DEB_SHIFT     6
-#define DA9055_ADC_ADCIN3_DEB_SHIFT     7
-#define DA9055_AD1_ISRC_MASK            0x10
-#define DA9055_AD1_ISRC_SHIFT           4
-
-/* DA9055_REG_VSYS_MON (addr=0x1D) */
-#define DA9055_VSYS_VAL_SHIFT           0
-#define DA9055_VSYS_VAL_MASK            0xFF
-#define DA9055_VSYS_VAL_BASE            0x00
-#define DA9055_VSYS_VAL_MAX             DA9055_VSYS_VAL_MASK
-#define DA9055_VSYS_VOLT_BASE           2500
-#define DA9055_VSYS_VOLT_INC            10
-#define DA9055_VSYS_STEPS               255
-#define DA9055_VSYS_VOLT_MIN            2500
-
-/* DA9044_REG_XXX_RES (addr=0x20-0x23) */
-#define DA9055_ADC_VAL_SHIFT            0
-#define DA9055_ADC_VAL_MASK             0xFF
-#define DA9055_ADC_VAL_BASE             0x00
-#define DA9055_ADC_VAL_MAX              DA9055_ADC_VAL_MASK
-#define DA9055_ADC_VOLT_BASE            0
-#define DA9055_ADC_VSYS_VOLT_BASE       2500
-#define DA9055_ADC_VOLT_INC             10
-#define DA9055_ADC_VSYS_VOLT_INC        12
-#define DA9055_ADC_STEPS                255
-
-/* DA9055_REG_EN_32K  (addr=0x35)*/
-#define DA9055_STARTUP_TIME_MASK        0x07
-#define DA9055_STARTUP_TIME_0S          0x0
-#define DA9055_STARTUP_TIME_0_52S       0x1
-#define DA9055_STARTUP_TIME_1S          0x2
-#define DA9055_CRYSTAL_EN               0x08
-#define DA9055_DELAY_MODE_EN            0x10
-#define DA9055_OUT_CLCK_GATED           0x20
-#define DA9055_RTC_CLOCK_GATED          0x40
-#define DA9055_EN_32KOUT_BUF            0x80
-
-/* DA9055_REG_RESET (addr=0x36) */
-/* Timer up to 31.744 ms */
-#define DA9055_RESET_TIMER_VAL_SHIFT    0
-#define DA9055_RESET_LOW_VAL_MASK       0x3F
-#define DA9055_RESET_LOW_VAL_BASE       0
-#define DA9055_RESET_LOW_VAL_MAX        DA9055_RESET_LOW_VAL_MASK
-#define DA9055_RESET_US_LOW_BASE        1024 /* min val in units of us */
-#define DA9055_RESET_US_LOW_INC         1024 /* inc val in units of us */
-#define DA9055_RESET_US_LOW_STEP        30
-
-/* Timer up to 1048.576ms */
-#define DA9055_RESET_HIGH_VAL_MASK      0x3F
-#define DA9055_RESET_HIGH_VAL_BASE      0
-#define DA9055_RESET_HIGH_VAL_MAX       DA9055_RESET_HIGH_VAL_MASK
-#define DA9055_RESET_US_HIGH_BASE       32768 /* min val in units of us */
-#define DA9055_RESET_US_HIGH_INC        32768 /* inv val in units of us */
-#define DA9055_RESET_US_HIGH_STEP       31
-
-/* DA9055_REG_BUCK_ILIM (addr=0x37)*/
-#define DA9055_BMEM_ILIM_SHIFT          0
-#define DA9055_ILIM_MASK                0x3
-#define DA9055_ILIM_500MA               0x0
-#define DA9055_ILIM_600MA               0x1
-#define DA9055_ILIM_700MA               0x2
-#define DA9055_ILIM_800MA               0x3
-#define DA9055_BCORE_ILIM_SHIFT         2
-
-/* DA9055_REG_BCORE_MODE (addr=0x38) */
-#define DA9055_BMEM_MODE_SHIFT          0
-#define DA9055_MODE_MASK                0x3
-#define DA9055_MODE_AB                  0x0
-#define DA9055_MODE_SLEEP               0x1
-#define DA9055_MODE_SYNCHRO             0x2
-#define DA9055_MODE_AUTO                0x3
-#define DA9055_BCORE_MODE_SHIFT         2
-
-/* DA9055_REG_VBCORE_A/B (addr=0x39/0x41)*/
-#define DA9055_VBCORE_VAL_SHIFT         0
-#define DA9055_VBCORE_VAL_MASK          0x3F
-#define DA9055_VBCORE_VAL_BASE          0x09
-#define DA9055_VBCORE_VAL_MAX           DA9055_VBCORE_VAL_MASK
-#define DA9055_VBCORE_VOLT_BASE         750
-#define DA9055_VBCORE_VOLT_INC          25
-#define DA9055_VBCORE_STEPS             53
-#define DA9055_VBCORE_VOLT_MIN          DA9055_VBCORE_VOLT_BASE
-#define DA9055_BCORE_SL_SYNCHRO         (0<<7)
-#define DA9055_BCORE_SL_SLEEP           (1<<7)
-
-/* DA9055_REG_VBMEM_A/B (addr=0x3A/0x42)*/
-#define DA9055_VBMEM_VAL_SHIFT          0
-#define DA9055_VBMEM_VAL_MASK           0x3F
-#define DA9055_VBMEM_VAL_BASE           0x00
-#define DA9055_VBMEM_VAL_MAX            DA9055_VBMEM_VAL_MASK
-#define DA9055_VBMEM_VOLT_BASE          925
-#define DA9055_VBMEM_VOLT_INC           25
-#define DA9055_VBMEM_STEPS              63
-#define DA9055_VBMEM_VOLT_MIN           DA9055_VBMEM_VOLT_BASE
-#define DA9055_BCMEM_SL_SYNCHRO         (0<<7)
-#define DA9055_BCMEM_SL_SLEEP           (1<<7)
-
-
-/* DA9055_REG_VLDO (addr=0x3B-0x40/0x43-0x48)*/
-#define DA9055_VLDO_VAL_SHIFT           0
-#define DA9055_VLDO_VAL_MASK            0x3F
-#define DA9055_VLDO6_VAL_MASK           0x7F
-#define DA9055_VLDO_VAL_BASE            0x02
-#define DA9055_VLDO2_VAL_BASE           0x03
-#define DA9055_VLDO6_VAL_BASE           0x00
-#define DA9055_VLDO_VAL_MAX             DA9055_VLDO_VAL_MASK
-#define DA9055_VLDO6_VAL_MAX            DA9055_VLDO6_VAL_MASK
-#define DA9055_VLDO_VOLT_BASE           900
-#define DA9055_VLDO_VOLT_INC            50
-#define DA9055_VLDO6_VOLT_INC           20
-#define DA9055_VLDO_STEPS               48
-#define DA9055_VLDO5_STEPS              37
-#define DA9055_VLDO6_STEPS              120
-#define DA9055_VLDO_VOLT_MIN            DA9055_VLDO_VOLT_BASE
-#define DA9055_LDO_MODE_SHIFT           7
-#define DA9055_LDO_SL_NORMAL            0
-#define DA9055_LDO_SL_SLEEP             1
-
-/* DA9055_REG_OTP_CONT (addr=0x50) */
-#define DA9055_OTP_TIM_NORMAL           (0<<0)
-#define DA9055_OTP_TIM_MARGINAL         (1<<0)
-#define DA9055_OTP_GP_RD_SHIFT          1
-#define DA9055_OTP_APPS_RD_SHIFT        2
-#define DA9055_PC_DONE_SHIFT            3
-#define DA9055_OTP_GP_LOCK_SHIFT        4
-#define DA9055_OTP_APPS_LOCK_SHIFT      5
-#define DA9055_OTP_CONF_LOCK_SHIFT      6
-#define DA9055_OTP_WRITE_DIS_SHIFT      7
-
-/* DA9055_REG_COUNT_S (addr=0x53) */
-#define DA9055_RTC_SEC                  0x3F
-#define DA9055_RTC_MONITOR_EN           0x40
-#define DA9055_RTC_READ                 0x80
-
-/* DA9055_REG_COUNT_MI (addr=0x54) */
-#define DA9055_RTC_MIN                  0x3F
-
-/* DA9055_REG_COUNT_H (addr=0x55) */
-#define DA9055_RTC_HOUR                 0x1F
-
-/* DA9055_REG_COUNT_D (addr=0x56) */
-#define DA9055_RTC_DAY                  0x1F
-
-/* DA9055_REG_COUNT_MO (addr=0x57) */
-#define DA9055_RTC_MONTH                0x0F
-
-/* DA9055_REG_COUNT_Y (addr=0x58) */
-#define DA9055_RTC_YEAR                 0x3F
-#define DA9055_RTC_YEAR_BASE            2000
-
-/* DA9055_REG_ALARM_MI (addr=0x59) */
-#define DA9055_RTC_ALM_MIN              0x3F
-#define DA9055_ALARM_STATUS_SHIFT       6
-#define DA9055_ALARM_STATUS_MASK        0x3
-#define DA9055_ALARM_STATUS_NO_ALARM    0x0
-#define DA9055_ALARM_STATUS_TICK        0x1
-#define DA9055_ALARM_STATUS_TIMER_ALARM 0x2
-#define DA9055_ALARM_STATUS_BOTH        0x3
-
-/* DA9055_REG_ALARM_H (addr=0x5A) */
-#define DA9055_RTC_ALM_HOUR             0x1F
-
-/* DA9055_REG_ALARM_D (addr=0x5B) */
-#define DA9055_RTC_ALM_DAY              0x1F
-
-/* DA9055_REG_ALARM_MO (addr=0x5C) */
-#define DA9055_RTC_ALM_MONTH            0x0F
-#define DA9055_RTC_TICK_WAKE_MASK       0x20
-#define DA9055_RTC_TICK_WAKE_SHIFT      5
-#define DA9055_RTC_TICK_TYPE            0x10
-#define DA9055_RTC_TICK_TYPE_SHIFT      0x4
-#define DA9055_RTC_TICK_SEC             0x0
-#define DA9055_RTC_TICK_MIN             0x1
-#define DA9055_ALARAM_TICK_WAKE         0x20
-
-/* DA9055_REG_ALARM_Y (addr=0x5D) */
-#define DA9055_RTC_TICK_EN              0x80
-#define DA9055_RTC_ALM_EN               0x40
-#define DA9055_RTC_TICK_ALM_MASK        0xC0
-#define DA9055_RTC_ALM_YEAR             0x3F
-
-/* DA9055_REG_TRIM_CLDR (addr=0x62) */
-#define DA9055_TRIM_32K_SHIFT           0
-#define DA9055_TRIM_32K_MASK            0x7F
-#define DA9055_TRIM_DECREMENT           (1<<7)
-#define DA9055_TRIM_INCREMENT           (0<<7)
-#define DA9055_TRIM_VAL_BASE            0x0
-#define DA9055_TRIM_PPM_BASE            0x0 /* min val in units of 0.1PPM */
-#define DA9055_TRIM_PPM_INC             19 /* min inc in units of 0.1PPM */
-#define DA9055_TRIM_STEPS               127
-
-/* DA9055_REG_CONFIG_A (addr=0x65) */
-#define DA9055_PM_I_V_VDDCORE           (0<<0)
-#define DA9055_PM_I_V_VDD_IO            (1<<0)
-#define DA9055_VDD_FAULT_TYPE_ACT_LOW   (0<<1)
-#define DA9055_VDD_FAULT_TYPE_ACT_HIGH  (1<<1)
-#define DA9055_PM_O_TYPE_PUSH_PULL      (0<<2)
-#define DA9055_PM_O_TYPE_OPEN_DRAIN     (1<<2)
-#define DA9055_IRQ_TYPE_ACT_LOW         (0<<3)
-#define DA9055_IRQ_TYPE_ACT_HIGH        (1<<3)
-#define DA9055_NIRQ_MODE_IMM            (0<<4)
-#define DA9055_NIRQ_MODE_ACTIVE         (1<<4)
-#define DA9055_GPI_V_VDDCORE            (0<<5)
-#define DA9055_GPI_V_VDD_IO             (1<<5)
-#define DA9055_PM_IF_V_VDDCORE          (0<<6)
-#define DA9055_PM_IF_V_VDD_IO           (1<<6)
-
-/* DA9055_REG_CONFIG_B (addr=0x66) */
-#define DA9055_VDD_FAULT_VAL_SHIFT      0
-#define DA9055_VDD_FAULT_VAL_MASK       0xF
-#define DA9055_VDD_FAULT_VAL_BASE       0x0
-#define DA9055_VDD_FAULT_VAL_MAX        DA9055_VDD_FAULT_VAL_MASK
-#define DA9055_VDD_FAULT_VOLT_BASE      2500
-#define DA9055_VDD_FAULT_VOLT_INC       50
-#define DA9055_VDD_FAULT_STEPS          15
-
-#define DA9055_VDD_HYST_VAL_SHIFT       4
-#define DA9055_VDD_HYST_VAL_MASK        0x7
-#define DA9055_VDD_HYST_VAL_BASE        0x0
-#define DA9055_VDD_HYST_VAL_MAX         DA9055_VDD_HYST_VAL_MASK
-#define DA9055_VDD_HYST_VOLT_BASE       100
-#define DA9055_VDD_HYST_VOLT_INC        50
-#define DA9055_VDD_HYST_STEPS           7
-#define DA9055_VDD_HYST_VOLT_MIN        DA9055_VDD_HYST_VOLT_BASE
-
-#define DA9055_VDD_FAULT_EN_SHIFT       7
-
-/* DA9055_REG_CONFIG_C (addr=0x67) */
-#define DA9055_BCORE_CLK_INV_SHIFT      0
-#define DA9055_BMEM_CLK_INV_SHIFT       1
-#define DA9055_NFAULT_CONF_SHIFT        2
-#define DA9055_LDO_SD_SHIFT             4
-#define DA9055_LDO5_BYP_SHIFT           6
-#define DA9055_LDO6_BYP_SHIFT           7
-
-/* DA9055_REG_CONFIG_D (addr=0x68) */
-#define DA9055_NONKEY_PIN_SHIFT         0
-#define DA9055_NONKEY_PIN_MASK          0x3
-#define DA9055_NONKEY_PIN_PORT_MODE     0x0
-#define DA9055_NONKEY_PIN_KEY_MODE      0x1
-#define DA9055_NONKEY_PIN_MULTI_FUNC    0x2
-#define DA9055_NONKEY_PIN_DEDICT        0x3
-#define DA9055_NONKEY_SD_SHIFT          2
-#define DA9055_KEY_DELAY_SHIFT          3
-#define DA9055_KEY_DELAY_MASK           0x3
-#define DA9055_KEY_DELAY_4S             0x0
-#define DA9055_KEY_DELAY_6S             0x1
-#define DA9055_KEY_DELAY_8S             0x2
-#define DA9055_KEY_DELAY_10S            0x3
-
-/* DA9055_REG_CONFIG_E (addr=0x69) */
-#define DA9055_GPIO_PUPD_PULL_UP        0x0
-#define DA9055_GPIO_PUPD_OPEN_DRAIN     0x1
-#define DA9055_GPIO0_PUPD_SHIFT         0
-#define DA9055_GPIO1_PUPD_SHIFT         1
-#define DA9055_GPIO2_PUPD_SHIFT         2
-#define DA9055_UVOV_DELAY_SHIFT         4
-#define DA9055_UVOV_DELAY_MASK          0x3
-#define DA9055_RESET_DURATION_SHIFT     6
-#define DA9055_RESET_DURATION_MASK      0x3
-#define DA9055_RESET_DURATION_0MS       0x0
-#define DA9055_RESET_DURATION_100MS     0x1
-#define DA9055_RESET_DURATION_500MS     0x2
-#define DA9055_RESET_DURATION_1000MS    0x3
-
-/* DA9055_REG_MON_REG_1 (addr=0x6A) */
-#define DA9055_MON_THRES_SHIFT          0
-#define DA9055_MON_THRES_MASK           0x3
-#define DA9055_MON_RES_SHIFT            2
-#define DA9055_MON_DEB_SHIFT            3
-#define DA9055_MON_MODE_SHIFT           4
-#define DA9055_MON_MODE_MASK            0x3
-#define DA9055_START_MAX_SHIFT          6
-#define DA9055_START_MAX_MASK           0x3
-
-/* DA9055_REG_MON_REG_2 (addr=0x6B) */
-#define DA9055_LDO1_MON_EN_SHIFT        0
-#define DA9055_LDO2_MON_EN_SHIFT        1
-#define DA9055_LDO3_MON_EN_SHIFT        2
-#define DA9055_LDO4_MON_EN_SHIFT        3
-#define DA9055_LDO5_MON_EN_SHIFT        4
-#define DA9055_LDO6_MON_EN_SHIFT        5
-#define DA9055_BCORE_MON_EN_SHIFT       6
-#define DA9055_BMEM_MON_EN_SHIFT        7
-
-/* DA9055_REG_CONFIG_F (addr=0x6C) */
-#define DA9055_LDO1_DEF_SHIFT           0
-#define DA9055_LDO2_DEF_SHIFT           1
-#define DA9055_LDO3_DEF_SHIFT           2
-#define DA9055_LDO4_DEF_SHIFT           3
-#define DA9055_LDO5_DEF_SHIFT           4
-#define DA9055_LDO6_DEF_SHIFT           5
-#define DA9055_BCORE_DEF_SHIFT          6
-#define DA9055_BMEM_DEF_SHIFT           7
-
-/* DA9055_REG_MON_REG_4 (addr=0x6D) */
-#define DA9055_MON_A8_IDX_SHIFT         0
-#define DA9055_MON_A89_IDX_MASK         0x3
-#define DA9055_MON_A89_IDX_NONE         0x0
-#define DA9055_MON_A89_IDX_BUCKCORE     0x1
-#define DA9055_MON_A89_IDX_LDO3         0x2
-#define DA9055_MON_A9_IDX_SHIFT         5
-
-/* DA9055_REG_MON_REG_5 (addr=0x6E) */
-#define DA9055_MON_A10_IDX_SHIFT        0
-#define DA9055_MON_A10_IDX_MASK         0x3
-#define DA9055_MON_A10_IDX_NONE         0x0
-#define DA9055_MON_A10_IDX_LDO1         0x1
-#define DA9055_MON_A10_IDX_LDO2         0x2
-#define DA9055_MON_A10_IDX_LDO5         0x3
-#define DA9055_MON_A10_IDX_LDO6         0x4
-
-#endif /* __DA9055_REG_H */
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index 6ee4247df11..917dbcab701 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -11,24 +11,7 @@
 #define __MFD_DB8500_PRCMU_H
 
 #include <linux/interrupt.h>
-#include <linux/bitops.h>
-
-/*
- * Registers
- */
-#define DB8500_PRCM_GPIOCR 0x138
-#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0     BIT(0)
-#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD      BIT(9)
-#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1     BIT(11)
-#define DB8500_PRCM_GPIOCR_SPI2_SELECT          BIT(23)
-
-#define DB8500_PRCM_LINE_VALUE 0x170
-#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0      BIT(3)
-
-#define DB8500_PRCM_DSI_SW_RESET 0x324
-#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
-#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
-#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
+#include <linux/notifier.h>
 
 /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
 
@@ -150,7 +133,7 @@ enum ap_pwrst {
  * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
  */
 enum ap_pwrst_trans {
-        PRCMU_AP_NO_CHANGE              = 0x00,
+        NO_TRANSITION                   = 0x00,
         APEXECUTE_TO_APSLEEP            = 0x01,
         APIDLE_TO_APSLEEP               = 0x02, /* To be removed */
         PRCMU_AP_SLEEP                  = 0x01,
@@ -163,6 +146,54 @@ enum ap_pwrst_trans {
 };
 
 /**
+ * enum ddr_pwrst - DDR power states definition
+ * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
+ * @DDR_PWR_STATE_ON:
+ * @DDR_PWR_STATE_OFFLOWLAT:
+ * @DDR_PWR_STATE_OFFHIGHLAT:
+ */
+enum ddr_pwrst {
+        DDR_PWR_STATE_UNCHANGED     = 0x00,
+        DDR_PWR_STATE_ON            = 0x01,
+        DDR_PWR_STATE_OFFLOWLAT     = 0x02,
+        DDR_PWR_STATE_OFFHIGHLAT    = 0x03
+};
+
+/**
+ * enum arm_opp - ARM OPP states definition
+ * @ARM_OPP_INIT:
+ * @ARM_NO_CHANGE: The ARM operating point is unchanged
+ * @ARM_100_OPP: The new ARM operating point is arm100opp
+ * @ARM_50_OPP: The new ARM operating point is arm50opp
+ * @ARM_MAX_OPP: Operating point is "max" (more than 100)
+ * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
+ * @ARM_EXTCLK: The new ARM operating point is armExtClk
+ */
+enum arm_opp {
+        ARM_OPP_INIT = 0x00,
+        ARM_NO_CHANGE = 0x01,
+        ARM_100_OPP = 0x02,
+        ARM_50_OPP = 0x03,
+        ARM_MAX_OPP = 0x04,
+        ARM_MAX_FREQ100OPP = 0x05,
+        ARM_EXTCLK = 0x07
+};
+
+/**
+ * enum ape_opp - APE OPP states definition
+ * @APE_OPP_INIT:
+ * @APE_NO_CHANGE: The APE operating point is unchanged
+ * @APE_100_OPP: The new APE operating point is ape100opp
+ * @APE_50_OPP: 50%
+ */
+enum ape_opp {
+        APE_OPP_INIT = 0x00,
+        APE_NO_CHANGE = 0x01,
+        APE_100_OPP = 0x02,
+        APE_50_OPP = 0x03
+};
+
+/**
  * enum hw_acc_state - State definition for hardware accelerator
  * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
  * @HW_OFF: The hardware accelerator must be switched off
@@ -438,26 +469,122 @@ enum auto_enable {
 
 /* End of file previously known as prcmu-fw-defs_v1.h */
 
+/* PRCMU Wakeup defines */
+enum prcmu_wakeup_index {
+        PRCMU_WAKEUP_INDEX_RTC,
+        PRCMU_WAKEUP_INDEX_RTT0,
+        PRCMU_WAKEUP_INDEX_RTT1,
+        PRCMU_WAKEUP_INDEX_HSI0,
+        PRCMU_WAKEUP_INDEX_HSI1,
+        PRCMU_WAKEUP_INDEX_USB,
+        PRCMU_WAKEUP_INDEX_ABB,
+        PRCMU_WAKEUP_INDEX_ABB_FIFO,
+        PRCMU_WAKEUP_INDEX_ARM,
+        NUM_PRCMU_WAKEUP_INDICES
+};
+#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
+
+/* PRCMU QoS APE OPP class */
+#define PRCMU_QOS_APE_OPP 1
+#define PRCMU_QOS_DDR_OPP 2
+#define PRCMU_QOS_DEFAULT_VALUE -1
+
 /**
- * enum prcmu_power_status - results from set_power_state
- * @PRCMU_SLEEP_OK: Sleep went ok
- * @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
- * @PRCMU_IDLE_OK: Idle went ok
- * @PRCMU_DEEPIDLE_OK: DeepIdle went ok
- * @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
- * @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
+ * enum hw_acc_dev - enum for hw accelerators
+ * @HW_ACC_SVAMMDSP: for SVAMMDSP
+ * @HW_ACC_SVAPIPE:  for SVAPIPE
+ * @HW_ACC_SIAMMDSP: for SIAMMDSP
+ * @HW_ACC_SIAPIPE: for SIAPIPE
+ * @HW_ACC_SGA: for SGA
+ * @HW_ACC_B2R2: for B2R2
+ * @HW_ACC_MCDE: for MCDE
+ * @HW_ACC_ESRAM1: for ESRAM1
+ * @HW_ACC_ESRAM2: for ESRAM2
+ * @HW_ACC_ESRAM3: for ESRAM3
+ * @HW_ACC_ESRAM4: for ESRAM4
+ * @NUM_HW_ACC: number of hardware accelerators
+ *
+ * Different hw accelerators which can be turned ON/
+ * OFF or put into retention (MMDSPs and ESRAMs).
+ * Used with EPOD API.
  *
+ * NOTE! Deprecated, to be removed when all users switched over to use the
+ * regulator API.
  */
-enum prcmu_power_status {
-        PRCMU_SLEEP_OK                  = 0xf3,
-        PRCMU_DEEP_SLEEP_OK             = 0xf6,
-        PRCMU_IDLE_OK                   = 0xf0,
-        PRCMU_DEEPIDLE_OK               = 0xe3,
-        PRCMU_PRCMU2ARMPENDINGIT_ER     = 0x91,
-        PRCMU_ARMPENDINGIT_ER           = 0x93,
+enum hw_acc_dev {
+        HW_ACC_SVAMMDSP,
+        HW_ACC_SVAPIPE,
+        HW_ACC_SIAMMDSP,
+        HW_ACC_SIAPIPE,
+        HW_ACC_SGA,
+        HW_ACC_B2R2,
+        HW_ACC_MCDE,
+        HW_ACC_ESRAM1,
+        HW_ACC_ESRAM2,
+        HW_ACC_ESRAM3,
+        HW_ACC_ESRAM4,
+        NUM_HW_ACC
 };
 
 /*
+ * Ids for all EPODs (power domains)
+ * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
+ * - EPOD_ID_SVAPIPE: power domain for SVA pipe
+ * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
+ * - EPOD_ID_SIAPIPE: power domain for SIA pipe
+ * - EPOD_ID_SGA: power domain for SGA
+ * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
+ * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
+ * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
+ * - NUM_EPOD_ID: number of power domains
+ */
+#define EPOD_ID_SVAMMDSP        0
+#define EPOD_ID_SVAPIPE         1
+#define EPOD_ID_SIAMMDSP        2
+#define EPOD_ID_SIAPIPE         3
+#define EPOD_ID_SGA             4
+#define EPOD_ID_B2R2_MCDE       5
+#define EPOD_ID_ESRAM12         6
+#define EPOD_ID_ESRAM34         7
+#define NUM_EPOD_ID             8
+
+/*
+ * state definition for EPOD (power domain)
+ * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
+ * - EPOD_STATE_OFF: The EPOD is switched off
+ * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
+ *                         retention
+ * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
+ * - EPOD_STATE_ON: Same as above, but with clock enabled
+ */
+#define EPOD_STATE_NO_CHANGE    0x00
+#define EPOD_STATE_OFF          0x01
+#define EPOD_STATE_RAMRET       0x02
+#define EPOD_STATE_ON_CLK_OFF   0x03
+#define EPOD_STATE_ON           0x04
+
+/*
+ * CLKOUT sources
+ */
+#define PRCMU_CLKSRC_CLK38M             0x00
+#define PRCMU_CLKSRC_ACLK               0x01
+#define PRCMU_CLKSRC_SYSCLK             0x02
+#define PRCMU_CLKSRC_LCDCLK             0x03
+#define PRCMU_CLKSRC_SDMMCCLK           0x04
+#define PRCMU_CLKSRC_TVCLK              0x05
+#define PRCMU_CLKSRC_TIMCLK             0x06
+#define PRCMU_CLKSRC_CLK009             0x07
+/* These are only valid for CLKOUT1: */
+#define PRCMU_CLKSRC_SIAMMDSPCLK        0x40
+#define PRCMU_CLKSRC_I2CCLK             0x41
+#define PRCMU_CLKSRC_MSP02CLK           0x42
+#define PRCMU_CLKSRC_ARMPLL_OBSCLK      0x43
+#define PRCMU_CLKSRC_HSIRXCLK           0x44
+#define PRCMU_CLKSRC_HSITXCLK           0x45
+#define PRCMU_CLKSRC_ARMCLKFIX          0x46
+#define PRCMU_CLKSRC_HDMICLK            0x47
+
+/*
  * Definitions for autonomous power management configuration.
  */
 
@@ -493,88 +620,126 @@ struct prcmu_auto_pm_config {
         u8 sva_policy;
 };
 
-#define PRCMU_FW_PROJECT_U8500          2
-#define PRCMU_FW_PROJECT_U9500          4
-#define PRCMU_FW_PROJECT_U8500_C2       7
-#define PRCMU_FW_PROJECT_U9500_C2       11
-#define PRCMU_FW_PROJECT_U8520          13
-#define PRCMU_FW_PROJECT_U8420          14
-
-struct prcmu_fw_version {
-        u8 project;
-        u8 api_version;
-        u8 func_version;
-        u8 errata;
+/**
+ * enum ddr_opp - DDR OPP states definition
+ * @DDR_100_OPP: The new DDR operating point is ddr100opp
+ * @DDR_50_OPP: The new DDR operating point is ddr50opp
+ * @DDR_25_OPP: The new DDR operating point is ddr25opp
+ */
+enum ddr_opp {
+        DDR_100_OPP = 0x00,
+        DDR_50_OPP = 0x01,
+        DDR_25_OPP = 0x02,
+};
+
+/*
+ * Clock identifiers.
+ */
+enum prcmu_clock {
+        PRCMU_SGACLK,
+        PRCMU_UARTCLK,
+        PRCMU_MSP02CLK,
+        PRCMU_MSP1CLK,
+        PRCMU_I2CCLK,
+        PRCMU_SDMMCCLK,
+        PRCMU_SLIMCLK,
+        PRCMU_PER1CLK,
+        PRCMU_PER2CLK,
+        PRCMU_PER3CLK,
+        PRCMU_PER5CLK,
+        PRCMU_PER6CLK,
+        PRCMU_PER7CLK,
+        PRCMU_LCDCLK,
+        PRCMU_BMLCLK,
+        PRCMU_HSITXCLK,
+        PRCMU_HSIRXCLK,
+        PRCMU_HDMICLK,
+        PRCMU_APEATCLK,
+        PRCMU_APETRACECLK,
+        PRCMU_MCDECLK,
+        PRCMU_IPI2CCLK,
+        PRCMU_DSIALTCLK,
+        PRCMU_DMACLK,
+        PRCMU_B2R2CLK,
+        PRCMU_TVCLK,
+        PRCMU_SSPCLK,
+        PRCMU_RNGCLK,
+        PRCMU_UICCCLK,
+        PRCMU_NUM_REG_CLOCKS,
+        PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
+        PRCMU_TIMCLK,
 };
 
+/*
+ * Definitions for controlling ESRAM0 in deep sleep.
+ */
+#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
+#define ESRAM0_DEEP_SLEEP_STATE_RET 2
+
+#ifdef CONFIG_MFD_DB8500_PRCMU
+void __init prcmu_early_init(void);
+int prcmu_set_display_clocks(void);
+int prcmu_disable_dsipll(void);
+int prcmu_enable_dsipll(void);
+#else
+static inline void __init prcmu_early_init(void) {}
+#endif
+
 #ifdef CONFIG_MFD_DB8500_PRCMU
 
-void db8500_prcmu_early_init(void);
 int prcmu_set_rc_a2p(enum romcode_write);
 enum romcode_read prcmu_get_rc_p2a(void);
 enum ap_pwrst prcmu_get_xp70_current_state(void);
+int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
+
+void prcmu_enable_wakeups(u32 wakeups);
+static inline void prcmu_disable_wakeups(void)
+{
+        prcmu_enable_wakeups(0);
+}
+
+void prcmu_config_abb_event_readout(u32 abb_events);
+void prcmu_get_abb_event_buffer(void __iomem **buf);
+int prcmu_set_arm_opp(u8 opp);
+int prcmu_get_arm_opp(void);
 bool prcmu_has_arm_maxopp(void);
-struct prcmu_fw_version *prcmu_get_fw_version(void);
+bool prcmu_is_u8400(void);
+int prcmu_set_ape_opp(u8 opp);
+int prcmu_get_ape_opp(void);
+int prcmu_request_ape_opp_100_voltage(bool enable);
 int prcmu_release_usb_wakeup_state(void);
+int prcmu_set_ddr_opp(u8 opp);
+int prcmu_get_ddr_opp(void);
+unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
+void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
+/* NOTE! Use regulator framework instead */
+int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
+int prcmu_set_epod(u16 epod_id, u8 epod_state);
 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
         struct prcmu_auto_pm_config *idle);
 bool prcmu_is_auto_pm_enabled(void);
 
 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
+int prcmu_request_clock(u8 clock, bool enable);
 int prcmu_set_clock_divider(u8 clock, u8 divider);
-int db8500_prcmu_config_hotdog(u8 threshold);
-int db8500_prcmu_config_hotmon(u8 low, u8 high);
-int db8500_prcmu_start_temp_sense(u16 cycles32k);
-int db8500_prcmu_stop_temp_sense(void);
+int prcmu_config_esram0_deep_sleep(u8 state);
+int prcmu_config_hotdog(u8 threshold);
+int prcmu_config_hotmon(u8 low, u8 high);
+int prcmu_start_temp_sense(u16 cycles32k);
+int prcmu_stop_temp_sense(void);
 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
 
-int prcmu_ac_wake_req(void);
+void prcmu_ac_wake_req(void);
 void prcmu_ac_sleep_req(void);
-void db8500_prcmu_modem_reset(void);
-
-int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
-int db8500_prcmu_enable_a9wdog(u8 id);
-int db8500_prcmu_disable_a9wdog(u8 id);
-int db8500_prcmu_kick_a9wdog(u8 id);
-int db8500_prcmu_load_a9wdog(u8 id, u32 val);
-
-void db8500_prcmu_system_reset(u16 reset_code);
-int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
-u8 db8500_prcmu_get_power_state_result(void);
-int db8500_prcmu_gic_decouple(void);
-int db8500_prcmu_gic_recouple(void);
-int db8500_prcmu_copy_gic_settings(void);
-bool db8500_prcmu_gic_pending_irq(void);
-bool db8500_prcmu_pending_irq(void);
-bool db8500_prcmu_is_cpu_in_wfi(int cpu);
-void db8500_prcmu_enable_wakeups(u32 wakeups);
-int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
-int db8500_prcmu_request_clock(u8 clock, bool enable);
-int db8500_prcmu_set_display_clocks(void);
-int db8500_prcmu_disable_dsipll(void);
-int db8500_prcmu_enable_dsipll(void);
-void db8500_prcmu_config_abb_event_readout(u32 abb_events);
-void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
-int db8500_prcmu_config_esram0_deep_sleep(u8 state);
-u16 db8500_prcmu_get_reset_code(void);
-bool db8500_prcmu_is_ac_wake_requested(void);
-int db8500_prcmu_set_arm_opp(u8 opp);
-int db8500_prcmu_get_arm_opp(void);
-int db8500_prcmu_set_ape_opp(u8 opp);
-int db8500_prcmu_get_ape_opp(void);
-int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
-int db8500_prcmu_set_ddr_opp(u8 opp);
-int db8500_prcmu_get_ddr_opp(void);
-
-u32 db8500_prcmu_read(unsigned int reg);
-void db8500_prcmu_write(unsigned int reg, u32 value);
-void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
+void prcmu_system_reset(u16 reset_code);
+void prcmu_modem_reset(void);
+bool prcmu_is_ac_wake_requested(void);
+void prcmu_enable_spi2(void);
+void prcmu_disable_spi2(void);
 
 #else /* !CONFIG_MFD_DB8500_PRCMU */
 
-static inline void db8500_prcmu_early_init(void) {}
-
 static inline int prcmu_set_rc_a2p(enum romcode_write code)
 {
         return 0;
@@ -590,209 +755,224 @@ static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
         return AP_EXECUTE;
 }
 
-static inline bool prcmu_has_arm_maxopp(void)
+static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+        bool keep_ap_pll)
 {
-        return false;
+        return 0;
 }
 
-static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
-{
-        return NULL;
-}
+static inline void prcmu_enable_wakeups(u32 wakeups) {}
 
-static inline int db8500_prcmu_set_ape_opp(u8 opp)
-{
-        return 0;
-}
+static inline void prcmu_disable_wakeups(void) {}
 
-static inline int db8500_prcmu_get_ape_opp(void)
-{
-        return APE_100_OPP;
-}
+static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
 
-static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
+static inline int prcmu_set_arm_opp(u8 opp)
 {
         return 0;
 }
 
-static inline int prcmu_release_usb_wakeup_state(void)
+static inline int prcmu_get_arm_opp(void)
 {
-        return 0;
+        return ARM_100_OPP;
 }
 
-static inline int db8500_prcmu_set_ddr_opp(u8 opp)
+static bool prcmu_has_arm_maxopp(void)
 {
-        return 0;
+        return false;
 }
 
-static inline int db8500_prcmu_get_ddr_opp(void)
+static bool prcmu_is_u8400(void)
 {
-        return DDR_100_OPP;
+        return false;
 }
 
-static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
-        struct prcmu_auto_pm_config *idle)
+static inline int prcmu_set_ape_opp(u8 opp)
 {
+        return 0;
 }
 
-static inline bool prcmu_is_auto_pm_enabled(void)
+static inline int prcmu_get_ape_opp(void)
 {
-        return false;
+        return APE_100_OPP;
 }
 
-static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
+static inline int prcmu_request_ape_opp_100_voltage(bool enable)
 {
         return 0;
 }
 
-static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
+static inline int prcmu_release_usb_wakeup_state(void)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_config_hotdog(u8 threshold)
+static inline int prcmu_set_ddr_opp(u8 opp)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
+static inline int prcmu_get_ddr_opp(void)
 {
-        return 0;
+        return DDR_100_OPP;
 }
 
-static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
+static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_stop_temp_sense(void)
+static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
+
+static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
 {
         return 0;
 }
 
-static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+        struct prcmu_auto_pm_config *idle)
 {
-        return -ENOSYS;
 }
 
-static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+static inline bool prcmu_is_auto_pm_enabled(void)
 {
-        return -ENOSYS;
+        return false;
 }
 
-static inline int prcmu_ac_wake_req(void)
+static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 {
         return 0;
 }
 
-static inline void prcmu_ac_sleep_req(void) {}
-
-static inline void db8500_prcmu_modem_reset(void) {}
-
-static inline void db8500_prcmu_system_reset(u16 reset_code) {}
-
-static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
-        bool keep_ap_pll)
+static inline int prcmu_request_clock(u8 clock, bool enable)
 {
         return 0;
 }
 
-static inline u8 db8500_prcmu_get_power_state_result(void)
+static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
 {
         return 0;
 }
 
-static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
-
-static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
+int prcmu_config_esram0_deep_sleep(u8 state)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
+static inline int prcmu_config_hotdog(u8 threshold)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_set_display_clocks(void)
+static inline int prcmu_config_hotmon(u8 low, u8 high)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_disable_dsipll(void)
+static inline int prcmu_start_temp_sense(u16 cycles32k)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_enable_dsipll(void)
+static inline int prcmu_stop_temp_sense(void)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
+static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
 {
-        return 0;
+        return -ENOSYS;
 }
 
-static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
+static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        return -ENOSYS;
+}
+
+static inline void prcmu_ac_wake_req(void) {}
+
+static inline void prcmu_ac_sleep_req(void) {}
 
-static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
+static inline void prcmu_system_reset(u16 reset_code) {}
 
-static inline u16 db8500_prcmu_get_reset_code(void)
+static inline void prcmu_modem_reset(void) {}
+
+static inline bool prcmu_is_ac_wake_requested(void)
 {
-        return 0;
+        return false;
 }
 
-static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
+#ifndef CONFIG_UX500_SOC_DB5500
+static inline int prcmu_set_display_clocks(void)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_enable_a9wdog(u8 id)
+static inline int prcmu_disable_dsipll(void)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_disable_a9wdog(u8 id)
+static inline int prcmu_enable_dsipll(void)
 {
         return 0;
 }
+#endif
 
-static inline int db8500_prcmu_kick_a9wdog(u8 id)
+static inline int prcmu_enable_spi2(void)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
+static inline int prcmu_disable_spi2(void)
 {
         return 0;
 }
 
-static inline bool db8500_prcmu_is_ac_wake_requested(void)
+#endif /* !CONFIG_MFD_DB8500_PRCMU */
+
+#ifdef CONFIG_UX500_PRCMU_QOS_POWER
+int prcmu_qos_requirement(int pm_qos_class);
+int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
+int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
+void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
+int prcmu_qos_add_notifier(int prcmu_qos_class,
+                           struct notifier_block *notifier);
+int prcmu_qos_remove_notifier(int prcmu_qos_class,
+                              struct notifier_block *notifier);
+#else
+static inline int prcmu_qos_requirement(int prcmu_qos_class)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_set_arm_opp(u8 opp)
+static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
+                                            char *name, s32 value)
 {
         return 0;
 }
 
-static inline int db8500_prcmu_get_arm_opp(void)
+static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
+                                               char *name, s32 new_value)
 {
         return 0;
 }
 
-static inline u32 db8500_prcmu_read(unsigned int reg)
+static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
 {
-        return 0;
 }
 
-static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
-
-static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
-        u32 value) {}
+static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
+                                         struct notifier_block *notifier)
+{
+        return 0;
+}
+static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
+                                            struct notifier_block *notifier)
+{
+        return 0;
+}
 
-#endif /* !CONFIG_MFD_DB8500_PRCMU */
+#endif
 
 #endif /* __MFD_DB8500_PRCMU_H */
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
deleted file mode 100644
index c202d6c4d87..00000000000
--- a/include/linux/mfd/dbx500-prcmu.h
+++ /dev/null
@@ -1,773 +0,0 @@
-/*
- * Copyright (C) ST Ericsson SA 2011
- *
- * License Terms: GNU General Public License v2
- *
- * STE Ux500 PRCMU API
- */
-#ifndef __MACH_PRCMU_H
-#define __MACH_PRCMU_H
-
-#include <linux/interrupt.h>
-#include <linux/notifier.h>
-#include <linux/err.h>
-
-/* PRCMU Wakeup defines */
-enum prcmu_wakeup_index {
-        PRCMU_WAKEUP_INDEX_RTC,
-        PRCMU_WAKEUP_INDEX_RTT0,
-        PRCMU_WAKEUP_INDEX_RTT1,
-        PRCMU_WAKEUP_INDEX_HSI0,
-        PRCMU_WAKEUP_INDEX_HSI1,
-        PRCMU_WAKEUP_INDEX_USB,
-        PRCMU_WAKEUP_INDEX_ABB,
-        PRCMU_WAKEUP_INDEX_ABB_FIFO,
-        PRCMU_WAKEUP_INDEX_ARM,
-        PRCMU_WAKEUP_INDEX_CD_IRQ,
-        NUM_PRCMU_WAKEUP_INDICES
-};
-#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
-
-/* EPOD (power domain) IDs */
-
-/*
- * DB8500 EPODs
- * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
- * - EPOD_ID_SVAPIPE: power domain for SVA pipe
- * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
- * - EPOD_ID_SIAPIPE: power domain for SIA pipe
- * - EPOD_ID_SGA: power domain for SGA
- * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
- * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
- * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
- * - NUM_EPOD_ID: number of power domains
- *
- * TODO: These should be prefixed.
- */
-#define EPOD_ID_SVAMMDSP        0
-#define EPOD_ID_SVAPIPE         1
-#define EPOD_ID_SIAMMDSP        2
-#define EPOD_ID_SIAPIPE         3
-#define EPOD_ID_SGA             4
-#define EPOD_ID_B2R2_MCDE       5
-#define EPOD_ID_ESRAM12         6
-#define EPOD_ID_ESRAM34         7
-#define NUM_EPOD_ID             8
-
-/*
- * state definition for EPOD (power domain)
- * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
- * - EPOD_STATE_OFF: The EPOD is switched off
- * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
- *                         retention
- * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
- * - EPOD_STATE_ON: Same as above, but with clock enabled
- */
-#define EPOD_STATE_NO_CHANGE    0x00
-#define EPOD_STATE_OFF          0x01
-#define EPOD_STATE_RAMRET       0x02
-#define EPOD_STATE_ON_CLK_OFF   0x03
-#define EPOD_STATE_ON           0x04
-
-/*
- * CLKOUT sources
- */
-#define PRCMU_CLKSRC_CLK38M             0x00
-#define PRCMU_CLKSRC_ACLK               0x01
-#define PRCMU_CLKSRC_SYSCLK             0x02
-#define PRCMU_CLKSRC_LCDCLK             0x03
-#define PRCMU_CLKSRC_SDMMCCLK           0x04
-#define PRCMU_CLKSRC_TVCLK              0x05
-#define PRCMU_CLKSRC_TIMCLK             0x06
-#define PRCMU_CLKSRC_CLK009             0x07
-/* These are only valid for CLKOUT1: */
-#define PRCMU_CLKSRC_SIAMMDSPCLK        0x40
-#define PRCMU_CLKSRC_I2CCLK             0x41
-#define PRCMU_CLKSRC_MSP02CLK           0x42
-#define PRCMU_CLKSRC_ARMPLL_OBSCLK      0x43
-#define PRCMU_CLKSRC_HSIRXCLK           0x44
-#define PRCMU_CLKSRC_HSITXCLK           0x45
-#define PRCMU_CLKSRC_ARMCLKFIX          0x46
-#define PRCMU_CLKSRC_HDMICLK            0x47
-
-/*
- * Clock identifiers.
- */
-enum prcmu_clock {
-        PRCMU_SGACLK,
-        PRCMU_UARTCLK,
-        PRCMU_MSP02CLK,
-        PRCMU_MSP1CLK,
-        PRCMU_I2CCLK,
-        PRCMU_SDMMCCLK,
-        PRCMU_SPARE1CLK,
-        PRCMU_SLIMCLK,
-        PRCMU_PER1CLK,
-        PRCMU_PER2CLK,
-        PRCMU_PER3CLK,
-        PRCMU_PER5CLK,
-        PRCMU_PER6CLK,
-        PRCMU_PER7CLK,
-        PRCMU_LCDCLK,
-        PRCMU_BMLCLK,
-        PRCMU_HSITXCLK,
-        PRCMU_HSIRXCLK,
-        PRCMU_HDMICLK,
-        PRCMU_APEATCLK,
-        PRCMU_APETRACECLK,
-        PRCMU_MCDECLK,
-        PRCMU_IPI2CCLK,
-        PRCMU_DSIALTCLK,
-        PRCMU_DMACLK,
-        PRCMU_B2R2CLK,
-        PRCMU_TVCLK,
-        PRCMU_SSPCLK,
-        PRCMU_RNGCLK,
-        PRCMU_UICCCLK,
-        PRCMU_PWMCLK,
-        PRCMU_IRDACLK,
-        PRCMU_IRRCCLK,
-        PRCMU_SIACLK,
-        PRCMU_SVACLK,
-        PRCMU_ACLK,
-        PRCMU_NUM_REG_CLOCKS,
-        PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
-        PRCMU_CDCLK,
-        PRCMU_TIMCLK,
-        PRCMU_PLLSOC0,
-        PRCMU_PLLSOC1,
-        PRCMU_ARMSS,
-        PRCMU_PLLDDR,
-        PRCMU_PLLDSI,
-        PRCMU_DSI0CLK,
-        PRCMU_DSI1CLK,
-        PRCMU_DSI0ESCCLK,
-        PRCMU_DSI1ESCCLK,
-        PRCMU_DSI2ESCCLK,
-};
-
-/**
- * enum ape_opp - APE OPP states definition
- * @APE_OPP_INIT:
- * @APE_NO_CHANGE: The APE operating point is unchanged
- * @APE_100_OPP: The new APE operating point is ape100opp
- * @APE_50_OPP: 50%
- * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
- */
-enum ape_opp {
-        APE_OPP_INIT = 0x00,
-        APE_NO_CHANGE = 0x01,
-        APE_100_OPP = 0x02,
-        APE_50_OPP = 0x03,
-        APE_50_PARTLY_25_OPP = 0xFF,
-};
-
-/**
- * enum arm_opp - ARM OPP states definition
- * @ARM_OPP_INIT:
- * @ARM_NO_CHANGE: The ARM operating point is unchanged
- * @ARM_100_OPP: The new ARM operating point is arm100opp
- * @ARM_50_OPP: The new ARM operating point is arm50opp
- * @ARM_MAX_OPP: Operating point is "max" (more than 100)
- * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
- * @ARM_EXTCLK: The new ARM operating point is armExtClk
- */
-enum arm_opp {
-        ARM_OPP_INIT = 0x00,
-        ARM_NO_CHANGE = 0x01,
-        ARM_100_OPP = 0x02,
-        ARM_50_OPP = 0x03,
-        ARM_MAX_OPP = 0x04,
-        ARM_MAX_FREQ100OPP = 0x05,
-        ARM_EXTCLK = 0x07
-};
-
-/**
- * enum ddr_opp - DDR OPP states definition
- * @DDR_100_OPP: The new DDR operating point is ddr100opp
- * @DDR_50_OPP: The new DDR operating point is ddr50opp
- * @DDR_25_OPP: The new DDR operating point is ddr25opp
- */
-enum ddr_opp {
-        DDR_100_OPP = 0x00,
-        DDR_50_OPP = 0x01,
-        DDR_25_OPP = 0x02,
-};
-
-/*
- * Definitions for controlling ESRAM0 in deep sleep.
- */
-#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
-#define ESRAM0_DEEP_SLEEP_STATE_RET 2
-
-/**
- * enum ddr_pwrst - DDR power states definition
- * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
- * @DDR_PWR_STATE_ON:
- * @DDR_PWR_STATE_OFFLOWLAT:
- * @DDR_PWR_STATE_OFFHIGHLAT:
- */
-enum ddr_pwrst {
-        DDR_PWR_STATE_UNCHANGED     = 0x00,
-        DDR_PWR_STATE_ON            = 0x01,
-        DDR_PWR_STATE_OFFLOWLAT     = 0x02,
-        DDR_PWR_STATE_OFFHIGHLAT    = 0x03
-};
-
-#include <linux/mfd/db8500-prcmu.h>
-
-#if defined(CONFIG_UX500_SOC_DB8500)
-
-#include <mach/id.h>
-
-static inline void __init prcmu_early_init(void)
-{
-        return db8500_prcmu_early_init();
-}
-
-static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
-                bool keep_ap_pll)
-{
-        return db8500_prcmu_set_power_state(state, keep_ulp_clk,
-                keep_ap_pll);
-}
-
-static inline u8 prcmu_get_power_state_result(void)
-{
-        return db8500_prcmu_get_power_state_result();
-}
-
-static inline int prcmu_gic_decouple(void)
-{
-        return db8500_prcmu_gic_decouple();
-}
-
-static inline int prcmu_gic_recouple(void)
-{
-        return db8500_prcmu_gic_recouple();
-}
-
-static inline bool prcmu_gic_pending_irq(void)
-{
-        return db8500_prcmu_gic_pending_irq();
-}
-
-static inline bool prcmu_is_cpu_in_wfi(int cpu)
-{
-        return db8500_prcmu_is_cpu_in_wfi(cpu);
-}
-
-static inline int prcmu_copy_gic_settings(void)
-{
-        return db8500_prcmu_copy_gic_settings();
-}
-
-static inline bool prcmu_pending_irq(void)
-{
-        return db8500_prcmu_pending_irq();
-}
-
-static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
-{
-        return db8500_prcmu_set_epod(epod_id, epod_state);
-}
-
-static inline void prcmu_enable_wakeups(u32 wakeups)
-{
-        db8500_prcmu_enable_wakeups(wakeups);
-}
-
-static inline void prcmu_disable_wakeups(void)
-{
-        prcmu_enable_wakeups(0);
-}
-
-static inline void prcmu_config_abb_event_readout(u32 abb_events)
-{
-        db8500_prcmu_config_abb_event_readout(abb_events);
-}
-
-static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
-{
-        db8500_prcmu_get_abb_event_buffer(buf);
-}
-
-int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
-int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
-int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
-
-int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
-
-static inline int prcmu_request_clock(u8 clock, bool enable)
-{
-        return db8500_prcmu_request_clock(clock, enable);
-}
-
-unsigned long prcmu_clock_rate(u8 clock);
-long prcmu_round_clock_rate(u8 clock, unsigned long rate);
-int prcmu_set_clock_rate(u8 clock, unsigned long rate);
-
-static inline int prcmu_set_ddr_opp(u8 opp)
-{
-        return db8500_prcmu_set_ddr_opp(opp);
-}
-static inline int prcmu_get_ddr_opp(void)
-{
-        return db8500_prcmu_get_ddr_opp();
-}
-
-static inline int prcmu_set_arm_opp(u8 opp)
-{
-        return db8500_prcmu_set_arm_opp(opp);
-}
-
-static inline int prcmu_get_arm_opp(void)
-{
-        return db8500_prcmu_get_arm_opp();
-}
-
-static inline int prcmu_set_ape_opp(u8 opp)
-{
-        return db8500_prcmu_set_ape_opp(opp);
-}
-
-static inline int prcmu_get_ape_opp(void)
-{
-        return db8500_prcmu_get_ape_opp();
-}
-
-static inline int prcmu_request_ape_opp_100_voltage(bool enable)
-{
-        return db8500_prcmu_request_ape_opp_100_voltage(enable);
-}
-
-static inline void prcmu_system_reset(u16 reset_code)
-{
-        return db8500_prcmu_system_reset(reset_code);
-}
-
-static inline u16 prcmu_get_reset_code(void)
-{
-        return db8500_prcmu_get_reset_code();
-}
-
-int prcmu_ac_wake_req(void);
-void prcmu_ac_sleep_req(void);
-static inline void prcmu_modem_reset(void)
-{
-        return db8500_prcmu_modem_reset();
-}
-
-static inline bool prcmu_is_ac_wake_requested(void)
-{
-        return db8500_prcmu_is_ac_wake_requested();
-}
-
-static inline int prcmu_set_display_clocks(void)
-{
-        return db8500_prcmu_set_display_clocks();
-}
-
-static inline int prcmu_disable_dsipll(void)
-{
-        return db8500_prcmu_disable_dsipll();
-}
-
-static inline int prcmu_enable_dsipll(void)
-{
-        return db8500_prcmu_enable_dsipll();
-}
-
-static inline int prcmu_config_esram0_deep_sleep(u8 state)
-{
-        return db8500_prcmu_config_esram0_deep_sleep(state);
-}
-
-static inline int prcmu_config_hotdog(u8 threshold)
-{
-        return db8500_prcmu_config_hotdog(threshold);
-}
-
-static inline int prcmu_config_hotmon(u8 low, u8 high)
-{
-        return db8500_prcmu_config_hotmon(low, high);
-}
-
-static inline int prcmu_start_temp_sense(u16 cycles32k)
-{
-        return  db8500_prcmu_start_temp_sense(cycles32k);
-}
-
-static inline int prcmu_stop_temp_sense(void)
-{
-        return  db8500_prcmu_stop_temp_sense();
-}
-
-static inline u32 prcmu_read(unsigned int reg)
-{
-        return db8500_prcmu_read(reg);
-}
-
-static inline void prcmu_write(unsigned int reg, u32 value)
-{
-        db8500_prcmu_write(reg, value);
-}
-
-static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
-{
-        db8500_prcmu_write_masked(reg, mask, value);
-}
-
-static inline int prcmu_enable_a9wdog(u8 id)
-{
-        return db8500_prcmu_enable_a9wdog(id);
-}
-
-static inline int prcmu_disable_a9wdog(u8 id)
-{
-        return db8500_prcmu_disable_a9wdog(id);
-}
-
-static inline int prcmu_kick_a9wdog(u8 id)
-{
-        return db8500_prcmu_kick_a9wdog(id);
-}
-
-static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
-{
-        return db8500_prcmu_load_a9wdog(id, timeout);
-}
-
-static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
-{
-        return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
-}
-#else
-
-static inline void __init prcmu_early_init(void) {}
-
-static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
-        bool keep_ap_pll)
-{
-        return 0;
-}
-
-static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
-{
-        return 0;
-}
-
-static inline void prcmu_enable_wakeups(u32 wakeups) {}
-
-static inline void prcmu_disable_wakeups(void) {}
-
-static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
-{
-        return -ENOSYS;
-}
-
-static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
-{
-        return -ENOSYS;
-}
-
-static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
-        u8 size)
-{
-        return -ENOSYS;
-}
-
-static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
-{
-        return 0;
-}
-
-static inline int prcmu_request_clock(u8 clock, bool enable)
-{
-        return 0;
-}
-
-static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
-{
-        return 0;
-}
-
-static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
-{
-        return 0;
-}
-
-static inline unsigned long prcmu_clock_rate(u8 clock)
-{
-        return 0;
-}
-
-static inline int prcmu_set_ape_opp(u8 opp)
-{
-        return 0;
-}
-
-static inline int prcmu_get_ape_opp(void)
-{
-        return APE_100_OPP;
-}
-
-static inline int prcmu_request_ape_opp_100_voltage(bool enable)
-{
-        return 0;
-}
-
-static inline int prcmu_set_arm_opp(u8 opp)
-{
-        return 0;
-}
-
-static inline int prcmu_get_arm_opp(void)
-{
-        return ARM_100_OPP;
-}
-
-static inline int prcmu_set_ddr_opp(u8 opp)
-{
-        return 0;
-}
-
-static inline int prcmu_get_ddr_opp(void)
-{
-        return DDR_100_OPP;
-}
-
-static inline void prcmu_system_reset(u16 reset_code) {}
-
-static inline u16 prcmu_get_reset_code(void)
-{
-        return 0;
-}
-
-static inline int prcmu_ac_wake_req(void)
-{
-        return 0;
-}
-
-static inline void prcmu_ac_sleep_req(void) {}
-
-static inline void prcmu_modem_reset(void) {}
-
-static inline bool prcmu_is_ac_wake_requested(void)
-{
-        return false;
-}
-
-static inline int prcmu_set_display_clocks(void)
-{
-        return 0;
-}
-
-static inline int prcmu_disable_dsipll(void)
-{
-        return 0;
-}
-
-static inline int prcmu_enable_dsipll(void)
-{
-        return 0;
-}
-
-static inline int prcmu_config_esram0_deep_sleep(u8 state)
-{
-        return 0;
-}
-
-static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
-
-static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
-{
-        *buf = NULL;
-}
-
-static inline int prcmu_config_hotdog(u8 threshold)
-{
-        return 0;
-}
-
-static inline int prcmu_config_hotmon(u8 low, u8 high)
-{
-        return 0;
-}
-
-static inline int prcmu_start_temp_sense(u16 cycles32k)
-{
-        return 0;
-}
-
-static inline int prcmu_stop_temp_sense(void)
-{
-        return 0;
-}
-
-static inline u32 prcmu_read(unsigned int reg)
-{
-        return 0;
-}
-
-static inline void prcmu_write(unsigned int reg, u32 value) {}
-
-static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
-
-#endif
-
-static inline void prcmu_set(unsigned int reg, u32 bits)
-{
-        prcmu_write_masked(reg, bits, bits);
-}
-
-static inline void prcmu_clear(unsigned int reg, u32 bits)
-{
-        prcmu_write_masked(reg, bits, 0);
-}
-
-#if defined(CONFIG_UX500_SOC_DB8500)
-
-/**
- * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
- */
-static inline void prcmu_enable_spi2(void)
-{
-        if (cpu_is_u8500())
-                prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
-}
-
-/**
- * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
- */
-static inline void prcmu_disable_spi2(void)
-{
-        if (cpu_is_u8500())
-                prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
-}
-
-/**
- * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
- * and UARTMOD on OtherAlternateC3.
- */
-static inline void prcmu_enable_stm_mod_uart(void)
-{
-        if (cpu_is_u8500()) {
-                prcmu_set(DB8500_PRCM_GPIOCR,
-                        (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
-                         DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
-        }
-}
-
-/**
- * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
- * and UARTMOD on OtherAlternateC3.
- */
-static inline void prcmu_disable_stm_mod_uart(void)
-{
-        if (cpu_is_u8500()) {
-                prcmu_clear(DB8500_PRCM_GPIOCR,
-                        (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
-                         DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
-        }
-}
-
-/**
- * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
- */
-static inline void prcmu_enable_stm_ape(void)
-{
-        if (cpu_is_u8500()) {
-                prcmu_set(DB8500_PRCM_GPIOCR,
-                        DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
-        }
-}
-
-/**
- * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
- */
-static inline void prcmu_disable_stm_ape(void)
-{
-        if (cpu_is_u8500()) {
-                prcmu_clear(DB8500_PRCM_GPIOCR,
-                        DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
-        }
-}
-
-#else
-
-static inline void prcmu_enable_spi2(void) {}
-static inline void prcmu_disable_spi2(void) {}
-static inline void prcmu_enable_stm_mod_uart(void) {}
-static inline void prcmu_disable_stm_mod_uart(void) {}
-static inline void prcmu_enable_stm_ape(void) {}
-static inline void prcmu_disable_stm_ape(void) {}
-
-#endif
-
-/* PRCMU QoS APE OPP class */
-#define PRCMU_QOS_APE_OPP 1
-#define PRCMU_QOS_DDR_OPP 2
-#define PRCMU_QOS_ARM_OPP 3
-#define PRCMU_QOS_DEFAULT_VALUE -1
-
-#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
-
-unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
-void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
-void prcmu_qos_force_opp(int, s32);
-int prcmu_qos_requirement(int pm_qos_class);
-int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
-int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
-void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
-int prcmu_qos_add_notifier(int prcmu_qos_class,
-                           struct notifier_block *notifier);
-int prcmu_qos_remove_notifier(int prcmu_qos_class,
-                              struct notifier_block *notifier);
-
-#else
-
-static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
-{
-        return 0;
-}
-
-static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
-
-static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
-
-static inline int prcmu_qos_requirement(int prcmu_qos_class)
-{
-        return 0;
-}
-
-static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
-                                            char *name, s32 value)
-{
-        return 0;
-}
-
-static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
-                                               char *name, s32 new_value)
-{
-        return 0;
-}
-
-static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
-{
-}
-
-static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
-                                         struct notifier_block *notifier)
-{
-        return 0;
-}
-static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
-                                            struct notifier_block *notifier)
-{
-        return 0;
-}
-
-#endif
-
-#endif /* __MACH_PRCMU_H */
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h
index 32a1b5cfeba..40c372165f3 100644
--- a/include/linux/mfd/ezx-pcap.h
+++ b/include/linux/mfd/ezx-pcap.h
@@ -16,7 +16,6 @@ struct pcap_subdev {
 struct pcap_platform_data {
         unsigned int irq_base;
         unsigned int config;
-        int gpio;
         void (*init) (void *);  /* board specific init */
         int num_subdevs;
         struct pcap_subdev *subdevs;
diff --git a/include/linux/mfd/intel_msic.h b/include/linux/mfd/intel_msic.h
deleted file mode 100644
index 439a7a617bc..00000000000
--- a/include/linux/mfd/intel_msic.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * include/linux/mfd/intel_msic.h - Core interface for Intel MSIC
- *
- * Copyright (C) 2011, Intel Corporation
- * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __LINUX_MFD_INTEL_MSIC_H__
-#define __LINUX_MFD_INTEL_MSIC_H__
-
-/* ID */
-#define INTEL_MSIC_ID0                  0x000   /* RO */
-#define INTEL_MSIC_ID1                  0x001   /* RO */
-
-/* IRQ */
-#define INTEL_MSIC_IRQLVL1              0x002
-#define INTEL_MSIC_ADC1INT              0x003
-#define INTEL_MSIC_CCINT                0x004
-#define INTEL_MSIC_PWRSRCINT            0x005
-#define INTEL_MSIC_PWRSRCINT1           0x006
-#define INTEL_MSIC_CHRINT               0x007
-#define INTEL_MSIC_CHRINT1              0x008
-#define INTEL_MSIC_RTCIRQ               0x009
-#define INTEL_MSIC_GPIO0LVIRQ           0x00a
-#define INTEL_MSIC_GPIO1LVIRQ           0x00b
-#define INTEL_MSIC_GPIOHVIRQ            0x00c
-#define INTEL_MSIC_VRINT                0x00d
-#define INTEL_MSIC_OCAUDIO              0x00e
-#define INTEL_MSIC_ACCDET               0x00f
-#define INTEL_MSIC_RESETIRQ1            0x010
-#define INTEL_MSIC_RESETIRQ2            0x011
-#define INTEL_MSIC_MADC1INT             0x012
-#define INTEL_MSIC_MCCINT               0x013
-#define INTEL_MSIC_MPWRSRCINT           0x014
-#define INTEL_MSIC_MPWRSRCINT1          0x015
-#define INTEL_MSIC_MCHRINT              0x016
-#define INTEL_MSIC_MCHRINT1             0x017
-#define INTEL_MSIC_RTCIRQMASK           0x018
-#define INTEL_MSIC_GPIO0LVIRQMASK       0x019
-#define INTEL_MSIC_GPIO1LVIRQMASK       0x01a
-#define INTEL_MSIC_GPIOHVIRQMASK        0x01b
-#define INTEL_MSIC_VRINTMASK            0x01c
-#define INTEL_MSIC_OCAUDIOMASK          0x01d
-#define INTEL_MSIC_ACCDETMASK           0x01e
-#define INTEL_MSIC_RESETIRQ1MASK        0x01f
-#define INTEL_MSIC_RESETIRQ2MASK        0x020
-#define INTEL_MSIC_IRQLVL1MSK           0x021
-#define INTEL_MSIC_PBCONFIG             0x03e
-#define INTEL_MSIC_PBSTATUS             0x03f   /* RO */
-
-/* GPIO */
-#define INTEL_MSIC_GPIO0LV7CTLO         0x040
-#define INTEL_MSIC_GPIO0LV6CTLO         0x041
-#define INTEL_MSIC_GPIO0LV5CTLO         0x042
-#define INTEL_MSIC_GPIO0LV4CTLO         0x043
-#define INTEL_MSIC_GPIO0LV3CTLO         0x044
-#define INTEL_MSIC_GPIO0LV2CTLO         0x045
-#define INTEL_MSIC_GPIO0LV1CTLO         0x046
-#define INTEL_MSIC_GPIO0LV0CTLO         0x047
-#define INTEL_MSIC_GPIO1LV7CTLOS        0x048
-#define INTEL_MSIC_GPIO1LV6CTLO         0x049
-#define INTEL_MSIC_GPIO1LV5CTLO         0x04a
-#define INTEL_MSIC_GPIO1LV4CTLO         0x04b
-#define INTEL_MSIC_GPIO1LV3CTLO         0x04c
-#define INTEL_MSIC_GPIO1LV2CTLO         0x04d
-#define INTEL_MSIC_GPIO1LV1CTLO         0x04e
-#define INTEL_MSIC_GPIO1LV0CTLO         0x04f
-#define INTEL_MSIC_GPIO0LV7CTLI         0x050
-#define INTEL_MSIC_GPIO0LV6CTLI         0x051
-#define INTEL_MSIC_GPIO0LV5CTLI         0x052
-#define INTEL_MSIC_GPIO0LV4CTLI         0x053
-#define INTEL_MSIC_GPIO0LV3CTLI         0x054
-#define INTEL_MSIC_GPIO0LV2CTLI         0x055
-#define INTEL_MSIC_GPIO0LV1CTLI         0x056
-#define INTEL_MSIC_GPIO0LV0CTLI         0x057
-#define INTEL_MSIC_GPIO1LV7CTLIS        0x058
-#define INTEL_MSIC_GPIO1LV6CTLI         0x059
-#define INTEL_MSIC_GPIO1LV5CTLI         0x05a
-#define INTEL_MSIC_GPIO1LV4CTLI         0x05b
-#define INTEL_MSIC_GPIO1LV3CTLI         0x05c
-#define INTEL_MSIC_GPIO1LV2CTLI         0x05d
-#define INTEL_MSIC_GPIO1LV1CTLI         0x05e
-#define INTEL_MSIC_GPIO1LV0CTLI         0x05f
-#define INTEL_MSIC_PWM0CLKDIV1          0x061
-#define INTEL_MSIC_PWM0CLKDIV0          0x062
-#define INTEL_MSIC_PWM1CLKDIV1          0x063
-#define INTEL_MSIC_PWM1CLKDIV0          0x064
-#define INTEL_MSIC_PWM2CLKDIV1          0x065
-#define INTEL_MSIC_PWM2CLKDIV0          0x066
-#define INTEL_MSIC_PWM0DUTYCYCLE        0x067
-#define INTEL_MSIC_PWM1DUTYCYCLE        0x068
-#define INTEL_MSIC_PWM2DUTYCYCLE        0x069
-#define INTEL_MSIC_GPIO0HV3CTLO         0x06d
-#define INTEL_MSIC_GPIO0HV2CTLO         0x06e
-#define INTEL_MSIC_GPIO0HV1CTLO         0x06f
-#define INTEL_MSIC_GPIO0HV0CTLO         0x070
-#define INTEL_MSIC_GPIO1HV3CTLO         0x071
-#define INTEL_MSIC_GPIO1HV2CTLO         0x072
-#define INTEL_MSIC_GPIO1HV1CTLO         0x073
-#define INTEL_MSIC_GPIO1HV0CTLO         0x074
-#define INTEL_MSIC_GPIO0HV3CTLI         0x075
-#define INTEL_MSIC_GPIO0HV2CTLI         0x076
-#define INTEL_MSIC_GPIO0HV1CTLI         0x077
-#define INTEL_MSIC_GPIO0HV0CTLI         0x078
-#define INTEL_MSIC_GPIO1HV3CTLI         0x079
-#define INTEL_MSIC_GPIO1HV2CTLI         0x07a
-#define INTEL_MSIC_GPIO1HV1CTLI         0x07b
-#define INTEL_MSIC_GPIO1HV0CTLI         0x07c
-
-/* SVID */
-#define INTEL_MSIC_SVIDCTRL0            0x080
-#define INTEL_MSIC_SVIDCTRL1            0x081
-#define INTEL_MSIC_SVIDCTRL2            0x082
-#define INTEL_MSIC_SVIDTXLASTPKT3       0x083   /* RO */
-#define INTEL_MSIC_SVIDTXLASTPKT2       0x084   /* RO */
-#define INTEL_MSIC_SVIDTXLASTPKT1       0x085   /* RO */
-#define INTEL_MSIC_SVIDTXLASTPKT0       0x086   /* RO */
-#define INTEL_MSIC_SVIDPKTOUTBYTE3      0x087
-#define INTEL_MSIC_SVIDPKTOUTBYTE2      0x088
-#define INTEL_MSIC_SVIDPKTOUTBYTE1      0x089
-#define INTEL_MSIC_SVIDPKTOUTBYTE0      0x08a
-#define INTEL_MSIC_SVIDRXVPDEBUG1       0x08b
-#define INTEL_MSIC_SVIDRXVPDEBUG0       0x08c
-#define INTEL_MSIC_SVIDRXLASTPKT3       0x08d   /* RO */
-#define INTEL_MSIC_SVIDRXLASTPKT2       0x08e   /* RO */
-#define INTEL_MSIC_SVIDRXLASTPKT1       0x08f   /* RO */
-#define INTEL_MSIC_SVIDRXLASTPKT0       0x090   /* RO */
-#define INTEL_MSIC_SVIDRXCHKSTATUS3     0x091   /* RO */
-#define INTEL_MSIC_SVIDRXCHKSTATUS2     0x092   /* RO */
-#define INTEL_MSIC_SVIDRXCHKSTATUS1     0x093   /* RO */
-#define INTEL_MSIC_SVIDRXCHKSTATUS0     0x094   /* RO */
-
-/* VREG */
-#define INTEL_MSIC_VCCLATCH             0x0c0
-#define INTEL_MSIC_VNNLATCH             0x0c1
-#define INTEL_MSIC_VCCCNT               0x0c2
-#define INTEL_MSIC_SMPSRAMP             0x0c3
-#define INTEL_MSIC_VNNCNT               0x0c4
-#define INTEL_MSIC_VNNAONCNT            0x0c5
-#define INTEL_MSIC_VCC122AONCNT         0x0c6
-#define INTEL_MSIC_V180AONCNT           0x0c7
-#define INTEL_MSIC_V500CNT              0x0c8
-#define INTEL_MSIC_VIHFCNT              0x0c9
-#define INTEL_MSIC_LDORAMP1             0x0ca
-#define INTEL_MSIC_LDORAMP2             0x0cb
-#define INTEL_MSIC_VCC108AONCNT         0x0cc
-#define INTEL_MSIC_VCC108ASCNT          0x0cd
-#define INTEL_MSIC_VCC108CNT            0x0ce
-#define INTEL_MSIC_VCCA100ASCNT         0x0cf
-#define INTEL_MSIC_VCCA100CNT           0x0d0
-#define INTEL_MSIC_VCC180AONCNT         0x0d1
-#define INTEL_MSIC_VCC180CNT            0x0d2
-#define INTEL_MSIC_VCC330CNT            0x0d3
-#define INTEL_MSIC_VUSB330CNT           0x0d4
-#define INTEL_MSIC_VCCSDIOCNT           0x0d5
-#define INTEL_MSIC_VPROG1CNT            0x0d6
-#define INTEL_MSIC_VPROG2CNT            0x0d7
-#define INTEL_MSIC_VEMMCSCNT            0x0d8
-#define INTEL_MSIC_VEMMC1CNT            0x0d9
-#define INTEL_MSIC_VEMMC2CNT            0x0da
-#define INTEL_MSIC_VAUDACNT             0x0db
-#define INTEL_MSIC_VHSPCNT              0x0dc
-#define INTEL_MSIC_VHSNCNT              0x0dd
-#define INTEL_MSIC_VHDMICNT             0x0de
-#define INTEL_MSIC_VOTGCNT              0x0df
-#define INTEL_MSIC_V1P35CNT             0x0e0
-#define INTEL_MSIC_V330AONCNT           0x0e1
-
-/* RESET */
-#define INTEL_MSIC_CHIPCNTRL            0x100   /* WO */
-#define INTEL_MSIC_ERCONFIG             0x101
-
-/* BURST */
-#define INTEL_MSIC_BATCURRENTLIMIT12    0x102
-#define INTEL_MSIC_BATTIMELIMIT12       0x103
-#define INTEL_MSIC_BATTIMELIMIT3        0x104
-#define INTEL_MSIC_BATTIMEDB            0x105
-#define INTEL_MSIC_BRSTCONFIGOUTPUTS    0x106
-#define INTEL_MSIC_BRSTCONFIGACTIONS    0x107
-#define INTEL_MSIC_BURSTCONTROLSTATUS   0x108
-
-/* RTC */
-#define INTEL_MSIC_RTCB1                0x140   /* RO */
-#define INTEL_MSIC_RTCB2                0x141   /* RO */
-#define INTEL_MSIC_RTCB3                0x142   /* RO */
-#define INTEL_MSIC_RTCB4                0x143   /* RO */
-#define INTEL_MSIC_RTCOB1               0x144
-#define INTEL_MSIC_RTCOB2               0x145
-#define INTEL_MSIC_RTCOB3               0x146
-#define INTEL_MSIC_RTCOB4               0x147
-#define INTEL_MSIC_RTCAB1               0x148
-#define INTEL_MSIC_RTCAB2               0x149
-#define INTEL_MSIC_RTCAB3               0x14a
-#define INTEL_MSIC_RTCAB4               0x14b
-#define INTEL_MSIC_RTCWAB1              0x14c
-#define INTEL_MSIC_RTCWAB2              0x14d
-#define INTEL_MSIC_RTCWAB3              0x14e
-#define INTEL_MSIC_RTCWAB4              0x14f
-#define INTEL_MSIC_RTCSC1               0x150
-#define INTEL_MSIC_RTCSC2               0x151
-#define INTEL_MSIC_RTCSC3               0x152
-#define INTEL_MSIC_RTCSC4               0x153
-#define INTEL_MSIC_RTCSTATUS            0x154   /* RO */
-#define INTEL_MSIC_RTCCONFIG1           0x155
-#define INTEL_MSIC_RTCCONFIG2           0x156
-
-/* CHARGER */
-#define INTEL_MSIC_BDTIMER              0x180
-#define INTEL_MSIC_BATTRMV              0x181
-#define INTEL_MSIC_VBUSDET              0x182
-#define INTEL_MSIC_VBUSDET1             0x183
-#define INTEL_MSIC_ADPHVDET             0x184
-#define INTEL_MSIC_ADPLVDET             0x185
-#define INTEL_MSIC_ADPDETDBDM           0x186
-#define INTEL_MSIC_LOWBATTDET           0x187
-#define INTEL_MSIC_CHRCTRL              0x188
-#define INTEL_MSIC_CHRCVOLTAGE          0x189
-#define INTEL_MSIC_CHRCCURRENT          0x18a
-#define INTEL_MSIC_SPCHARGER            0x18b
-#define INTEL_MSIC_CHRTTIME             0x18c
-#define INTEL_MSIC_CHRCTRL1             0x18d
-#define INTEL_MSIC_PWRSRCLMT            0x18e
-#define INTEL_MSIC_CHRSTWDT             0x18f
-#define INTEL_MSIC_WDTWRITE             0x190   /* WO */
-#define INTEL_MSIC_CHRSAFELMT           0x191
-#define INTEL_MSIC_SPWRSRCINT           0x192   /* RO */
-#define INTEL_MSIC_SPWRSRCINT1          0x193   /* RO */
-#define INTEL_MSIC_CHRLEDPWM            0x194
-#define INTEL_MSIC_CHRLEDCTRL           0x195
-
-/* ADC */
-#define INTEL_MSIC_ADC1CNTL1            0x1c0
-#define INTEL_MSIC_ADC1CNTL2            0x1c1
-#define INTEL_MSIC_ADC1CNTL3            0x1c2
-#define INTEL_MSIC_ADC1OFFSETH          0x1c3   /* RO */
-#define INTEL_MSIC_ADC1OFFSETL          0x1c4   /* RO */
-#define INTEL_MSIC_ADC1ADDR0            0x1c5
-#define INTEL_MSIC_ADC1ADDR1            0x1c6
-#define INTEL_MSIC_ADC1ADDR2            0x1c7
-#define INTEL_MSIC_ADC1ADDR3            0x1c8
-#define INTEL_MSIC_ADC1ADDR4            0x1c9
-#define INTEL_MSIC_ADC1ADDR5            0x1ca
-#define INTEL_MSIC_ADC1ADDR6            0x1cb
-#define INTEL_MSIC_ADC1ADDR7            0x1cc
-#define INTEL_MSIC_ADC1ADDR8            0x1cd
-#define INTEL_MSIC_ADC1ADDR9            0x1ce
-#define INTEL_MSIC_ADC1ADDR10           0x1cf
-#define INTEL_MSIC_ADC1ADDR11           0x1d0
-#define INTEL_MSIC_ADC1ADDR12           0x1d1
-#define INTEL_MSIC_ADC1ADDR13           0x1d2
-#define INTEL_MSIC_ADC1ADDR14           0x1d3
-#define INTEL_MSIC_ADC1SNS0H            0x1d4   /* RO */
-#define INTEL_MSIC_ADC1SNS0L            0x1d5   /* RO */
-#define INTEL_MSIC_ADC1SNS1H            0x1d6   /* RO */
-#define INTEL_MSIC_ADC1SNS1L            0x1d7   /* RO */
-#define INTEL_MSIC_ADC1SNS2H            0x1d8   /* RO */
-#define INTEL_MSIC_ADC1SNS2L            0x1d9   /* RO */
-#define INTEL_MSIC_ADC1SNS3H            0x1da   /* RO */
-#define INTEL_MSIC_ADC1SNS3L            0x1db   /* RO */
-#define INTEL_MSIC_ADC1SNS4H            0x1dc   /* RO */
-#define INTEL_MSIC_ADC1SNS4L            0x1dd   /* RO */
-#define INTEL_MSIC_ADC1SNS5H            0x1de   /* RO */
-#define INTEL_MSIC_ADC1SNS5L            0x1df   /* RO */
-#define INTEL_MSIC_ADC1SNS6H            0x1e0   /* RO */
-#define INTEL_MSIC_ADC1SNS6L            0x1e1   /* RO */
-#define INTEL_MSIC_ADC1SNS7H            0x1e2   /* RO */
-#define INTEL_MSIC_ADC1SNS7L            0x1e3   /* RO */
-#define INTEL_MSIC_ADC1SNS8H            0x1e4   /* RO */
-#define INTEL_MSIC_ADC1SNS8L            0x1e5   /* RO */
-#define INTEL_MSIC_ADC1SNS9H            0x1e6   /* RO */
-#define INTEL_MSIC_ADC1SNS9L            0x1e7   /* RO */
-#define INTEL_MSIC_ADC1SNS10H           0x1e8   /* RO */
-#define INTEL_MSIC_ADC1SNS10L           0x1e9   /* RO */
-#define INTEL_MSIC_ADC1SNS11H           0x1ea   /* RO */
-#define INTEL_MSIC_ADC1SNS11L           0x1eb   /* RO */
-#define INTEL_MSIC_ADC1SNS12H           0x1ec   /* RO */
-#define INTEL_MSIC_ADC1SNS12L           0x1ed   /* RO */
-#define INTEL_MSIC_ADC1SNS13H           0x1ee   /* RO */
-#define INTEL_MSIC_ADC1SNS13L           0x1ef   /* RO */
-#define INTEL_MSIC_ADC1SNS14H           0x1f0   /* RO */
-#define INTEL_MSIC_ADC1SNS14L           0x1f1   /* RO */
-#define INTEL_MSIC_ADC1BV0H             0x1f2   /* RO */
-#define INTEL_MSIC_ADC1BV0L             0x1f3   /* RO */
-#define INTEL_MSIC_ADC1BV1H             0x1f4   /* RO */
-#define INTEL_MSIC_ADC1BV1L             0x1f5   /* RO */
-#define INTEL_MSIC_ADC1BV2H             0x1f6   /* RO */
-#define INTEL_MSIC_ADC1BV2L             0x1f7   /* RO */
-#define INTEL_MSIC_ADC1BV3H             0x1f8   /* RO */
-#define INTEL_MSIC_ADC1BV3L             0x1f9   /* RO */
-#define INTEL_MSIC_ADC1BI0H             0x1fa   /* RO */
-#define INTEL_MSIC_ADC1BI0L             0x1fb   /* RO */
-#define INTEL_MSIC_ADC1BI1H             0x1fc   /* RO */
-#define INTEL_MSIC_ADC1BI1L             0x1fd   /* RO */
-#define INTEL_MSIC_ADC1BI2H             0x1fe   /* RO */
-#define INTEL_MSIC_ADC1BI2L             0x1ff   /* RO */
-#define INTEL_MSIC_ADC1BI3H             0x200   /* RO */
-#define INTEL_MSIC_ADC1BI3L             0x201   /* RO */
-#define INTEL_MSIC_CCCNTL               0x202
-#define INTEL_MSIC_CCOFFSETH            0x203   /* RO */
-#define INTEL_MSIC_CCOFFSETL            0x204   /* RO */
-#define INTEL_MSIC_CCADCHA              0x205   /* RO */
-#define INTEL_MSIC_CCADCLA              0x206   /* RO */
-
-/* AUDIO */
-#define INTEL_MSIC_AUDPLLCTRL           0x240
-#define INTEL_MSIC_DMICBUF0123          0x241
-#define INTEL_MSIC_DMICBUF45            0x242
-#define INTEL_MSIC_DMICGPO              0x244
-#define INTEL_MSIC_DMICMUX              0x245
-#define INTEL_MSIC_DMICCLK              0x246
-#define INTEL_MSIC_MICBIAS              0x247
-#define INTEL_MSIC_ADCCONFIG            0x248
-#define INTEL_MSIC_MICAMP1              0x249
-#define INTEL_MSIC_MICAMP2              0x24a
-#define INTEL_MSIC_NOISEMUX             0x24b
-#define INTEL_MSIC_AUDIOMUX12           0x24c
-#define INTEL_MSIC_AUDIOMUX34           0x24d
-#define INTEL_MSIC_AUDIOSINC            0x24e
-#define INTEL_MSIC_AUDIOTXEN            0x24f
-#define INTEL_MSIC_HSEPRXCTRL           0x250
-#define INTEL_MSIC_IHFRXCTRL            0x251
-#define INTEL_MSIC_VOICETXVOL           0x252
-#define INTEL_MSIC_SIDETONEVOL          0x253
-#define INTEL_MSIC_MUSICSHARVOL         0x254
-#define INTEL_MSIC_VOICETXCTRL          0x255
-#define INTEL_MSIC_HSMIXER              0x256
-#define INTEL_MSIC_DACCONFIG            0x257
-#define INTEL_MSIC_SOFTMUTE             0x258
-#define INTEL_MSIC_HSLVOLCTRL           0x259
-#define INTEL_MSIC_HSRVOLCTRL           0x25a
-#define INTEL_MSIC_IHFLVOLCTRL          0x25b
-#define INTEL_MSIC_IHFRVOLCTRL          0x25c
-#define INTEL_MSIC_DRIVEREN             0x25d
-#define INTEL_MSIC_LINEOUTCTRL          0x25e
-#define INTEL_MSIC_VIB1CTRL1            0x25f
-#define INTEL_MSIC_VIB1CTRL2            0x260
-#define INTEL_MSIC_VIB1CTRL3            0x261
-#define INTEL_MSIC_VIB1SPIPCM_1         0x262
-#define INTEL_MSIC_VIB1SPIPCM_2         0x263
-#define INTEL_MSIC_VIB1CTRL5            0x264
-#define INTEL_MSIC_VIB2CTRL1            0x265
-#define INTEL_MSIC_VIB2CTRL2            0x266
-#define INTEL_MSIC_VIB2CTRL3            0x267
-#define INTEL_MSIC_VIB2SPIPCM_1         0x268
-#define INTEL_MSIC_VIB2SPIPCM_2         0x269
-#define INTEL_MSIC_VIB2CTRL5            0x26a
-#define INTEL_MSIC_BTNCTRL1             0x26b
-#define INTEL_MSIC_BTNCTRL2             0x26c
-#define INTEL_MSIC_PCM1TXSLOT01         0x26d
-#define INTEL_MSIC_PCM1TXSLOT23         0x26e
-#define INTEL_MSIC_PCM1TXSLOT45         0x26f
-#define INTEL_MSIC_PCM1RXSLOT0123       0x270
-#define INTEL_MSIC_PCM1RXSLOT045        0x271
-#define INTEL_MSIC_PCM2TXSLOT01         0x272
-#define INTEL_MSIC_PCM2TXSLOT23         0x273
-#define INTEL_MSIC_PCM2TXSLOT45         0x274
-#define INTEL_MSIC_PCM2RXSLOT01         0x275
-#define INTEL_MSIC_PCM2RXSLOT23         0x276
-#define INTEL_MSIC_PCM2RXSLOT45         0x277
-#define INTEL_MSIC_PCM1CTRL1            0x278
-#define INTEL_MSIC_PCM1CTRL2            0x279
-#define INTEL_MSIC_PCM1CTRL3            0x27a
-#define INTEL_MSIC_PCM2CTRL1            0x27b
-#define INTEL_MSIC_PCM2CTRL2            0x27c
-
-/* HDMI */
-#define INTEL_MSIC_HDMIPUEN             0x280
-#define INTEL_MSIC_HDMISTATUS           0x281   /* RO */
-
-/* Physical address of the start of the MSIC interrupt tree in SRAM */
-#define INTEL_MSIC_IRQ_PHYS_BASE        0xffff7fc0
-
-/**
- * struct intel_msic_gpio_pdata - platform data for the MSIC GPIO driver
- * @gpio_base: base number for the GPIOs
- */
-struct intel_msic_gpio_pdata {
-        unsigned        gpio_base;
-};
-
-/**
- * struct intel_msic_ocd_pdata - platform data for the MSIC OCD driver
- * @gpio: GPIO number used for OCD interrupts
- *
- * The MSIC MFD driver converts @gpio into an IRQ number and passes it to
- * the OCD driver as %IORESOURCE_IRQ.
- */
-struct intel_msic_ocd_pdata {
-        unsigned        gpio;
-};
-
-/* MSIC embedded blocks (subdevices) */
-enum intel_msic_block {
-        INTEL_MSIC_BLOCK_TOUCH,
-        INTEL_MSIC_BLOCK_ADC,
-        INTEL_MSIC_BLOCK_BATTERY,
-        INTEL_MSIC_BLOCK_GPIO,
-        INTEL_MSIC_BLOCK_AUDIO,
-        INTEL_MSIC_BLOCK_HDMI,
-        INTEL_MSIC_BLOCK_THERMAL,
-        INTEL_MSIC_BLOCK_POWER_BTN,
-        INTEL_MSIC_BLOCK_OCD,
-
-        INTEL_MSIC_BLOCK_LAST,
-};
-
-/**
- * struct intel_msic_platform_data - platform data for the MSIC driver
- * @irq: array of interrupt numbers, one per device. If @irq is set to %0
- *       for a given block, the corresponding platform device is not
- *       created. For devices which don't have an interrupt, use %0xff
- *       (this is same as in SFI spec).
- * @gpio: platform data for the MSIC GPIO driver
- * @ocd: platform data for the MSIC OCD driver
- *
- * Once the MSIC driver is initialized, the register interface is ready to
- * use. All the platform devices for subdevices are created after the
- * register interface is ready so that we can guarantee its availability to
- * the subdevice drivers.
- *
- * Interrupt numbers are passed to the subdevices via %IORESOURCE_IRQ
- * resources of the created platform device.
- */
-struct intel_msic_platform_data {
-        int                             irq[INTEL_MSIC_BLOCK_LAST];
-        struct intel_msic_gpio_pdata    *gpio;
-        struct intel_msic_ocd_pdata     *ocd;
-};
-
-struct intel_msic;
-
-extern int intel_msic_reg_read(unsigned short reg, u8 *val);
-extern int intel_msic_reg_write(unsigned short reg, u8 val);
-extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask);
-extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count);
-extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count);
-
-/*
- * pdev_to_intel_msic - gets an MSIC instance from the platform device
- * @pdev: platform device pointer
- *
- * The client drivers need to have pointer to the MSIC instance if they
- * want to call intel_msic_irq_read(). This macro can be used for
- * convenience to get the MSIC pointer from @pdev where needed. This is
- * _only_ valid for devices which are managed by the MSIC.
- */
-#define pdev_to_intel_msic(pdev)        (dev_get_drvdata(pdev->dev.parent))
-
-extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg,
-                               u8 *val);
-
-#endif /* __LINUX_MFD_INTEL_MSIC_H__ */
diff --git a/include/linux/mfd/lm3533.h b/include/linux/mfd/lm3533.h
deleted file mode 100644
index 594bc591f25..00000000000
--- a/include/linux/mfd/lm3533.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * lm3533.h -- LM3533 interface
- *
- * Copyright (C) 2011-2012 Texas Instruments
- *
- * Author: Johan Hovold <jhovold@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under  the terms of the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef __LINUX_MFD_LM3533_H
-#define __LINUX_MFD_LM3533_H
-
-#define LM3533_ATTR_RO(_name) \
-        DEVICE_ATTR(_name, S_IRUGO, show_##_name, NULL)
-#define LM3533_ATTR_RW(_name) \
-        DEVICE_ATTR(_name, S_IRUGO | S_IWUSR , show_##_name, store_##_name)
-
-struct device;
-struct regmap;
-
-struct lm3533 {
-        struct device *dev;
-
-        struct regmap *regmap;
-
-        int gpio_hwen;
-        int irq;
-
-        unsigned have_als:1;
-        unsigned have_backlights:1;
-        unsigned have_leds:1;
-};
-
-struct lm3533_ctrlbank {
-        struct lm3533 *lm3533;
-        struct device *dev;
-        int id;
-};
-
-struct lm3533_als_platform_data {
-        unsigned pwm_mode:1;            /* PWM input mode (default analog) */
-        u8 r_select;                    /* 1 - 127 (ignored in PWM-mode) */
-};
-
-struct lm3533_bl_platform_data {
-        char *name;
-        u16 max_current;                /* 5000 - 29800 uA (800 uA step) */
-        u8 default_brightness;          /* 0 - 255 */
-        u8 pwm;                         /* 0 - 0x3f */
-};
-
-struct lm3533_led_platform_data {
-        char *name;
-        const char *default_trigger;
-        u16 max_current;                /* 5000 - 29800 uA (800 uA step) */
-        u8 pwm;                         /* 0 - 0x3f */
-};
-
-enum lm3533_boost_freq {
-        LM3533_BOOST_FREQ_500KHZ,
-        LM3533_BOOST_FREQ_1000KHZ,
-};
-
-enum lm3533_boost_ovp {
-        LM3533_BOOST_OVP_16V,
-        LM3533_BOOST_OVP_24V,
-        LM3533_BOOST_OVP_32V,
-        LM3533_BOOST_OVP_40V,
-};
-
-struct lm3533_platform_data {
-        int gpio_hwen;
-
-        enum lm3533_boost_ovp boost_ovp;
-        enum lm3533_boost_freq boost_freq;
-
-        struct lm3533_als_platform_data *als;
-
-        struct lm3533_bl_platform_data *backlights;
-        int num_backlights;
-
-        struct lm3533_led_platform_data *leds;
-        int num_leds;
-};
-
-extern int lm3533_ctrlbank_enable(struct lm3533_ctrlbank *cb);
-extern int lm3533_ctrlbank_disable(struct lm3533_ctrlbank *cb);
-
-extern int lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank *cb, u8 val);
-extern int lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank *cb, u8 *val);
-extern int lm3533_ctrlbank_set_max_current(struct lm3533_ctrlbank *cb,
-                                                                u16 imax);
-extern int lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank *cb, u8 val);
-extern int lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank *cb, u8 *val);
-
-extern int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val);
-extern int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val);
-extern int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask);
-
-#endif  /* __LINUX_MFD_LM3533_H */
diff --git a/include/linux/mfd/lp8788-isink.h b/include/linux/mfd/lp8788-isink.h
deleted file mode 100644
index f38262d21ff..00000000000
--- a/include/linux/mfd/lp8788-isink.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * TI LP8788 MFD - common definitions for current sinks
- *
- * Copyright 2012 Texas Instruments
- *
- * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ISINK_LP8788_H__
-#define __ISINK_LP8788_H__
-
-/* register address */
-#define LP8788_ISINK_CTRL               0x99
-#define LP8788_ISINK12_IOUT             0x9A
-#define LP8788_ISINK3_IOUT              0x9B
-#define LP8788_ISINK1_PWM               0x9C
-#define LP8788_ISINK2_PWM               0x9D
-#define LP8788_ISINK3_PWM               0x9E
-
-/* mask bits */
-#define LP8788_ISINK1_IOUT_M            0x0F    /* Addr 9Ah */
-#define LP8788_ISINK2_IOUT_M            0xF0
-#define LP8788_ISINK3_IOUT_M            0x0F    /* Addr 9Bh */
-
-/* 6 bits used for PWM code : Addr 9C ~ 9Eh */
-#define LP8788_ISINK_MAX_PWM            63
-#define LP8788_ISINK_SCALE_OFFSET       3
-
-static const u8 lp8788_iout_addr[] = {
-        LP8788_ISINK12_IOUT,
-        LP8788_ISINK12_IOUT,
-        LP8788_ISINK3_IOUT,
-};
-
-static const u8 lp8788_iout_mask[] = {
-        LP8788_ISINK1_IOUT_M,
-        LP8788_ISINK2_IOUT_M,
-        LP8788_ISINK3_IOUT_M,
-};
-
-static const u8 lp8788_pwm_addr[] = {
-        LP8788_ISINK1_PWM,
-        LP8788_ISINK2_PWM,
-        LP8788_ISINK3_PWM,
-};
-
-#endif
diff --git a/include/linux/mfd/lp8788.h b/include/linux/mfd/lp8788.h
deleted file mode 100644
index 2a32b16f79c..00000000000
--- a/include/linux/mfd/lp8788.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- * TI LP8788 MFD Device
- *
- * Copyright 2012 Texas Instruments
- *
- * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __MFD_LP8788_H__
-#define __MFD_LP8788_H__
-
-#include <linux/gpio.h>
-#include <linux/irqdomain.h>
-#include <linux/regmap.h>
-
-#define LP8788_DEV_BUCK         "lp8788-buck"
-#define LP8788_DEV_DLDO         "lp8788-dldo"
-#define LP8788_DEV_ALDO         "lp8788-aldo"
-#define LP8788_DEV_CHARGER      "lp8788-charger"
-#define LP8788_DEV_RTC          "lp8788-rtc"
-#define LP8788_DEV_BACKLIGHT    "lp8788-backlight"
-#define LP8788_DEV_VIBRATOR     "lp8788-vibrator"
-#define LP8788_DEV_KEYLED       "lp8788-keyled"
-#define LP8788_DEV_ADC          "lp8788-adc"
-
-#define LP8788_NUM_BUCKS        4
-#define LP8788_NUM_DLDOS        12
-#define LP8788_NUM_ALDOS        10
-#define LP8788_NUM_BUCK2_DVS    2
-
-#define LP8788_CHG_IRQ          "CHG_IRQ"
-#define LP8788_PRSW_IRQ         "PRSW_IRQ"
-#define LP8788_BATT_IRQ         "BATT_IRQ"
-#define LP8788_ALM_IRQ          "ALARM_IRQ"
-
-enum lp8788_int_id {
-        /* interrup register 1 : Addr 00h */
-        LP8788_INT_TSDL,
-        LP8788_INT_TSDH,
-        LP8788_INT_UVLO,
-        LP8788_INT_FLAGMON,
-        LP8788_INT_PWRON_TIME,
-        LP8788_INT_PWRON,
-        LP8788_INT_COMP1,
-        LP8788_INT_COMP2,
-
-        /* interrupt register 2 : Addr 01h */
-        LP8788_INT_CHG_INPUT_STATE,
-        LP8788_INT_CHG_STATE,
-        LP8788_INT_EOC,
-        LP8788_INT_CHG_RESTART,
-        LP8788_INT_RESTART_TIMEOUT,
-        LP8788_INT_FULLCHG_TIMEOUT,
-        LP8788_INT_PRECHG_TIMEOUT,
-
-        /* interrupt register 3 : Addr 02h */
-        LP8788_INT_RTC_ALARM1 = 17,
-        LP8788_INT_RTC_ALARM2,
-        LP8788_INT_ENTER_SYS_SUPPORT,
-        LP8788_INT_EXIT_SYS_SUPPORT,
-        LP8788_INT_BATT_LOW,
-        LP8788_INT_NO_BATT,
-
-        LP8788_INT_MAX = 24,
-};
-
-enum lp8788_dvs_sel {
-        DVS_SEL_V0,
-        DVS_SEL_V1,
-        DVS_SEL_V2,
-        DVS_SEL_V3,
-};
-
-enum lp8788_ext_ldo_en_id {
-        EN_ALDO1,
-        EN_ALDO234,
-        EN_ALDO5,
-        EN_ALDO7,
-        EN_DLDO7,
-        EN_DLDO911,
-        EN_LDOS_MAX,
-};
-
-enum lp8788_charger_event {
-        NO_CHARGER,
-        CHARGER_DETECTED,
-};
-
-enum lp8788_bl_ctrl_mode {
-        LP8788_BL_REGISTER_ONLY,
-        LP8788_BL_COMB_PWM_BASED,       /* PWM + I2C, changed by PWM input */
-        LP8788_BL_COMB_REGISTER_BASED,  /* PWM + I2C, changed by I2C */
-};
-
-enum lp8788_bl_dim_mode {
-        LP8788_DIM_EXPONENTIAL,
-        LP8788_DIM_LINEAR,
-};
-
-enum lp8788_bl_full_scale_current {
-        LP8788_FULLSCALE_5000uA,
-        LP8788_FULLSCALE_8500uA,
-        LP8788_FULLSCALE_1200uA,
-        LP8788_FULLSCALE_1550uA,
-        LP8788_FULLSCALE_1900uA,
-        LP8788_FULLSCALE_2250uA,
-        LP8788_FULLSCALE_2600uA,
-        LP8788_FULLSCALE_2950uA,
-};
-
-enum lp8788_bl_ramp_step {
-        LP8788_RAMP_8us,
-        LP8788_RAMP_1024us,
-        LP8788_RAMP_2048us,
-        LP8788_RAMP_4096us,
-        LP8788_RAMP_8192us,
-        LP8788_RAMP_16384us,
-        LP8788_RAMP_32768us,
-        LP8788_RAMP_65538us,
-};
-
-enum lp8788_bl_pwm_polarity {
-        LP8788_PWM_ACTIVE_HIGH,
-        LP8788_PWM_ACTIVE_LOW,
-};
-
-enum lp8788_isink_scale {
-        LP8788_ISINK_SCALE_100mA,
-        LP8788_ISINK_SCALE_120mA,
-};
-
-enum lp8788_isink_number {
-        LP8788_ISINK_1,
-        LP8788_ISINK_2,
-        LP8788_ISINK_3,
-};
-
-enum lp8788_alarm_sel {
-        LP8788_ALARM_1,
-        LP8788_ALARM_2,
-        LP8788_ALARM_MAX,
-};
-
-enum lp8788_adc_id {
-        LPADC_VBATT_5P5,
-        LPADC_VIN_CHG,
-        LPADC_IBATT,
-        LPADC_IC_TEMP,
-        LPADC_VBATT_6P0,
-        LPADC_VBATT_5P0,
-        LPADC_ADC1,
-        LPADC_ADC2,
-        LPADC_VDD,
-        LPADC_VCOIN,
-        LPADC_VDD_LDO,
-        LPADC_ADC3,
-        LPADC_ADC4,
-        LPADC_MAX,
-};
-
-struct lp8788;
-
-/*
- * lp8788_buck1_dvs
- * @gpio         : gpio pin number for dvs control
- * @vsel         : dvs selector for buck v1 register
- */
-struct lp8788_buck1_dvs {
-        int gpio;
-        enum lp8788_dvs_sel vsel;
-};
-
-/*
- * lp8788_buck2_dvs
- * @gpio         : two gpio pin numbers are used for dvs
- * @vsel         : dvs selector for buck v2 register
- */
-struct lp8788_buck2_dvs {
-        int gpio[LP8788_NUM_BUCK2_DVS];
-        enum lp8788_dvs_sel vsel;
-};
-
-/*
- * struct lp8788_ldo_enable_pin
- *
- *   Basically, all LDOs are enabled through the I2C commands.
- *   But ALDO 1 ~ 5, 7, DLDO 7, 9, 11 can be enabled by external gpio pins.
- *
- * @gpio         : gpio number which is used for enabling ldos
- * @init_state   : initial gpio state (ex. GPIOF_OUT_INIT_LOW)
- */
-struct lp8788_ldo_enable_pin {
-        int gpio;
-        int init_state;
-};
-
-/*
- * struct lp8788_chg_param
- * @addr         : charging control register address (range : 0x11 ~ 0x1C)
- * @val          : charging parameter value
- */
-struct lp8788_chg_param {
-        u8 addr;
-        u8 val;
-};
-
-/*
- * struct lp8788_charger_platform_data
- * @adc_vbatt         : adc channel name for battery voltage
- * @adc_batt_temp     : adc channel name for battery temperature
- * @max_vbatt_mv      : used for calculating battery capacity
- * @chg_params        : initial charging parameters
- * @num_chg_params    : numbers of charging parameters
- * @charger_event     : the charger event can be reported to the platform side
- */
-struct lp8788_charger_platform_data {
-        const char *adc_vbatt;
-        const char *adc_batt_temp;
-        unsigned int max_vbatt_mv;
-        struct lp8788_chg_param *chg_params;
-        int num_chg_params;
-        void (*charger_event) (struct lp8788 *lp,
-                                enum lp8788_charger_event event);
-};
-
-/*
- * struct lp8788_bl_pwm_data
- * @pwm_set_intensity     : set duty of pwm
- * @pwm_get_intensity     : get current duty of pwm
- */
-struct lp8788_bl_pwm_data {
-        void (*pwm_set_intensity) (int brightness, int max_brightness);
-        int (*pwm_get_intensity) (int max_brightness);
-};
-
-/*
- * struct lp8788_backlight_platform_data
- * @name                  : backlight driver name. (default: "lcd-backlight")
- * @initial_brightness    : initial value of backlight brightness
- * @bl_mode               : brightness control by pwm or lp8788 register
- * @dim_mode              : dimming mode selection
- * @full_scale            : full scale current setting
- * @rise_time             : brightness ramp up step time
- * @fall_time             : brightness ramp down step time
- * @pwm_pol               : pwm polarity setting when bl_mode is pwm based
- * @pwm_data              : platform specific pwm generation functions
- *                          only valid when bl_mode is pwm based
- */
-struct lp8788_backlight_platform_data {
-        char *name;
-        int initial_brightness;
-        enum lp8788_bl_ctrl_mode bl_mode;
-        enum lp8788_bl_dim_mode dim_mode;
-        enum lp8788_bl_full_scale_current full_scale;
-        enum lp8788_bl_ramp_step rise_time;
-        enum lp8788_bl_ramp_step fall_time;
-        enum lp8788_bl_pwm_polarity pwm_pol;
-        struct lp8788_bl_pwm_data pwm_data;
-};
-
-/*
- * struct lp8788_led_platform_data
- * @name         : led driver name. (default: "keyboard-backlight")
- * @scale        : current scale
- * @num          : current sink number
- * @iout_code    : current output value (Addr 9Ah ~ 9Bh)
- */
-struct lp8788_led_platform_data {
-        char *name;
-        enum lp8788_isink_scale scale;
-        enum lp8788_isink_number num;
-        int iout_code;
-};
-
-/*
- * struct lp8788_vib_platform_data
- * @name         : vibrator driver name
- * @scale        : current scale
- * @num          : current sink number
- * @iout_code    : current output value (Addr 9Ah ~ 9Bh)
- * @pwm_code     : PWM code value (Addr 9Ch ~ 9Eh)
- */
-struct lp8788_vib_platform_data {
-        char *name;
-        enum lp8788_isink_scale scale;
-        enum lp8788_isink_number num;
-        int iout_code;
-        int pwm_code;
-};
-
-/*
- * struct lp8788_platform_data
- * @init_func    : used for initializing registers
- *                 before mfd driver is registered
- * @buck_data    : regulator initial data for buck
- * @dldo_data    : regulator initial data for digital ldo
- * @aldo_data    : regulator initial data for analog ldo
- * @buck1_dvs    : gpio configurations for buck1 dvs
- * @buck2_dvs    : gpio configurations for buck2 dvs
- * @ldo_pin      : gpio configurations for enabling LDOs
- * @chg_pdata    : platform data for charger driver
- * @alarm_sel    : rtc alarm selection (1 or 2)
- * @bl_pdata     : configurable data for backlight driver
- * @led_pdata    : configurable data for led driver
- * @vib_pdata    : configurable data for vibrator driver
- * @adc_pdata    : iio map data for adc driver
- */
-struct lp8788_platform_data {
-        /* general system information */
-        int (*init_func) (struct lp8788 *lp);
-
-        /* regulators */
-        struct regulator_init_data *buck_data[LP8788_NUM_BUCKS];
-        struct regulator_init_data *dldo_data[LP8788_NUM_DLDOS];
-        struct regulator_init_data *aldo_data[LP8788_NUM_ALDOS];
-        struct lp8788_buck1_dvs *buck1_dvs;
-        struct lp8788_buck2_dvs *buck2_dvs;
-        struct lp8788_ldo_enable_pin *ldo_pin[EN_LDOS_MAX];
-
-        /* charger */
-        struct lp8788_charger_platform_data *chg_pdata;
-
-        /* rtc alarm */
-        enum lp8788_alarm_sel alarm_sel;
-
-        /* backlight */
-        struct lp8788_backlight_platform_data *bl_pdata;
-
-        /* current sinks */
-        struct lp8788_led_platform_data *led_pdata;
-        struct lp8788_vib_platform_data *vib_pdata;
-
-        /* adc iio map data */
-        struct iio_map *adc_pdata;
-};
-
-/*
- * struct lp8788
- * @dev          : parent device pointer
- * @regmap       : used for i2c communcation on accessing registers
- * @irqdm        : interrupt domain for handling nested interrupt
- * @irq          : pin number of IRQ_N
- * @pdata        : lp8788 platform specific data
- */
-struct lp8788 {
-        struct device *dev;
-        struct regmap *regmap;
-        struct irq_domain *irqdm;
-        int irq;
-        struct lp8788_platform_data *pdata;
-};
-
-int lp8788_irq_init(struct lp8788 *lp, int chip_irq);
-void lp8788_irq_exit(struct lp8788 *lp);
-int lp8788_read_byte(struct lp8788 *lp, u8 reg, u8 *data);
-int lp8788_read_multi_bytes(struct lp8788 *lp, u8 reg, u8 *data, size_t count);
-int lp8788_write_byte(struct lp8788 *lp, u8 reg, u8 data);
-int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data);
-#endif
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
deleted file mode 100644
index 3e1df644c40..00000000000
--- a/include/linux/mfd/lpc_ich.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *  linux/drivers/mfd/lpc_ich.h
- *
- *  Copyright (c) 2012 Extreme Engineering Solution, Inc.
- *  Author: Aaron Sierra <asierra@xes-inc.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License 2 as published
- *  by the Free Software Foundation.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; see the file COPYING.  If not, write to
- *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef LPC_ICH_H
-#define LPC_ICH_H
-
-/* Watchdog resources */
-#define ICH_RES_IO_TCO  0
-#define ICH_RES_IO_SMI  1
-#define ICH_RES_MEM_OFF 2
-#define ICH_RES_MEM_GCS 0
-
-/* GPIO resources */
-#define ICH_RES_GPIO    0
-#define ICH_RES_GPE0    1
-
-/* GPIO compatibility */
-#define ICH_I3100_GPIO          0x401
-#define ICH_V5_GPIO             0x501
-#define ICH_V6_GPIO             0x601
-#define ICH_V7_GPIO             0x701
-#define ICH_V9_GPIO             0x801
-#define ICH_V10CORP_GPIO        0xa01
-#define ICH_V10CONS_GPIO        0xa11
-
-struct lpc_ich_info {
-        char name[32];
-        unsigned int iTCO_version;
-        unsigned int gpio_version;
-        u8 use_gpio;
-};
-
-#endif
diff --git a/include/linux/mfd/max77686-private.h b/include/linux/mfd/max77686-private.h
deleted file mode 100644
index d327d4971e4..00000000000
--- a/include/linux/mfd/max77686-private.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * max77686.h - Voltage regulator driver for the Maxim 77686
- *
- *  Copyright (C) 2012 Samsung Electrnoics
- *  Chiwoong Byun <woong.byun@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __LINUX_MFD_MAX77686_PRIV_H
-#define __LINUX_MFD_MAX77686_PRIV_H
-
-#include <linux/i2c.h>
-#include <linux/regmap.h>
-#include <linux/module.h>
-
-#define MAX77686_REG_INVALID            (0xff)
-
-enum max77686_pmic_reg {
-        MAX77686_REG_DEVICE_ID          = 0x00,
-        MAX77686_REG_INTSRC             = 0x01,
-        MAX77686_REG_INT1               = 0x02,
-        MAX77686_REG_INT2               = 0x03,
-
-        MAX77686_REG_INT1MSK            = 0x04,
-        MAX77686_REG_INT2MSK            = 0x05,
-
-        MAX77686_REG_STATUS1            = 0x06,
-        MAX77686_REG_STATUS2            = 0x07,
-
-        MAX77686_REG_PWRON              = 0x08,
-        MAX77686_REG_ONOFF_DELAY        = 0x09,
-        MAX77686_REG_MRSTB              = 0x0A,
-        /* Reserved: 0x0B-0x0F */
-
-        MAX77686_REG_BUCK1CTRL          = 0x10,
-        MAX77686_REG_BUCK1OUT           = 0x11,
-        MAX77686_REG_BUCK2CTRL1         = 0x12,
-        MAX77686_REG_BUCK234FREQ        = 0x13,
-        MAX77686_REG_BUCK2DVS1          = 0x14,
-        MAX77686_REG_BUCK2DVS2          = 0x15,
-        MAX77686_REG_BUCK2DVS3          = 0x16,
-        MAX77686_REG_BUCK2DVS4          = 0x17,
-        MAX77686_REG_BUCK2DVS5          = 0x18,
-        MAX77686_REG_BUCK2DVS6          = 0x19,
-        MAX77686_REG_BUCK2DVS7          = 0x1A,
-        MAX77686_REG_BUCK2DVS8          = 0x1B,
-        MAX77686_REG_BUCK3CTRL1         = 0x1C,
-        /* Reserved: 0x1D */
-        MAX77686_REG_BUCK3DVS1          = 0x1E,
-        MAX77686_REG_BUCK3DVS2          = 0x1F,
-        MAX77686_REG_BUCK3DVS3          = 0x20,
-        MAX77686_REG_BUCK3DVS4          = 0x21,
-        MAX77686_REG_BUCK3DVS5          = 0x22,
-        MAX77686_REG_BUCK3DVS6          = 0x23,
-        MAX77686_REG_BUCK3DVS7          = 0x24,
-        MAX77686_REG_BUCK3DVS8          = 0x25,
-        MAX77686_REG_BUCK4CTRL1         = 0x26,
-        /* Reserved: 0x27 */
-        MAX77686_REG_BUCK4DVS1          = 0x28,
-        MAX77686_REG_BUCK4DVS2          = 0x29,
-        MAX77686_REG_BUCK4DVS3          = 0x2A,
-        MAX77686_REG_BUCK4DVS4          = 0x2B,
-        MAX77686_REG_BUCK4DVS5          = 0x2C,
-        MAX77686_REG_BUCK4DVS6          = 0x2D,
-        MAX77686_REG_BUCK4DVS7          = 0x2E,
-        MAX77686_REG_BUCK4DVS8          = 0x2F,
-        MAX77686_REG_BUCK5CTRL          = 0x30,
-        MAX77686_REG_BUCK5OUT           = 0x31,
-        MAX77686_REG_BUCK6CTRL          = 0x32,
-        MAX77686_REG_BUCK6OUT           = 0x33,
-        MAX77686_REG_BUCK7CTRL          = 0x34,
-        MAX77686_REG_BUCK7OUT           = 0x35,
-        MAX77686_REG_BUCK8CTRL          = 0x36,
-        MAX77686_REG_BUCK8OUT           = 0x37,
-        MAX77686_REG_BUCK9CTRL          = 0x38,
-        MAX77686_REG_BUCK9OUT           = 0x39,
-        /* Reserved: 0x3A-0x3F */
-
-        MAX77686_REG_LDO1CTRL1          = 0x40,
-        MAX77686_REG_LDO2CTRL1          = 0x41,
-        MAX77686_REG_LDO3CTRL1          = 0x42,
-        MAX77686_REG_LDO4CTRL1          = 0x43,
-        MAX77686_REG_LDO5CTRL1          = 0x44,
-        MAX77686_REG_LDO6CTRL1          = 0x45,
-        MAX77686_REG_LDO7CTRL1          = 0x46,
-        MAX77686_REG_LDO8CTRL1          = 0x47,
-        MAX77686_REG_LDO9CTRL1          = 0x48,
-        MAX77686_REG_LDO10CTRL1         = 0x49,
-        MAX77686_REG_LDO11CTRL1         = 0x4A,
-        MAX77686_REG_LDO12CTRL1         = 0x4B,
-        MAX77686_REG_LDO13CTRL1         = 0x4C,
-        MAX77686_REG_LDO14CTRL1         = 0x4D,
-        MAX77686_REG_LDO15CTRL1         = 0x4E,
-        MAX77686_REG_LDO16CTRL1         = 0x4F,
-        MAX77686_REG_LDO17CTRL1         = 0x50,
-        MAX77686_REG_LDO18CTRL1         = 0x51,
-        MAX77686_REG_LDO19CTRL1         = 0x52,
-        MAX77686_REG_LDO20CTRL1         = 0x53,
-        MAX77686_REG_LDO21CTRL1         = 0x54,
-        MAX77686_REG_LDO22CTRL1         = 0x55,
-        MAX77686_REG_LDO23CTRL1         = 0x56,
-        MAX77686_REG_LDO24CTRL1         = 0x57,
-        MAX77686_REG_LDO25CTRL1         = 0x58,
-        MAX77686_REG_LDO26CTRL1         = 0x59,
-        /* Reserved: 0x5A-0x5F */
-        MAX77686_REG_LDO1CTRL2          = 0x60,
-        MAX77686_REG_LDO2CTRL2          = 0x61,
-        MAX77686_REG_LDO3CTRL2          = 0x62,
-        MAX77686_REG_LDO4CTRL2          = 0x63,
-        MAX77686_REG_LDO5CTRL2          = 0x64,
-        MAX77686_REG_LDO6CTRL2          = 0x65,
-        MAX77686_REG_LDO7CTRL2          = 0x66,
-        MAX77686_REG_LDO8CTRL2          = 0x67,
-        MAX77686_REG_LDO9CTRL2          = 0x68,
-        MAX77686_REG_LDO10CTRL2         = 0x69,
-        MAX77686_REG_LDO11CTRL2         = 0x6A,
-        MAX77686_REG_LDO12CTRL2         = 0x6B,
-        MAX77686_REG_LDO13CTRL2         = 0x6C,
-        MAX77686_REG_LDO14CTRL2         = 0x6D,
-        MAX77686_REG_LDO15CTRL2         = 0x6E,
-        MAX77686_REG_LDO16CTRL2         = 0x6F,
-        MAX77686_REG_LDO17CTRL2         = 0x70,
-        MAX77686_REG_LDO18CTRL2         = 0x71,
-        MAX77686_REG_LDO19CTRL2         = 0x72,
-        MAX77686_REG_LDO20CTRL2         = 0x73,
-        MAX77686_REG_LDO21CTRL2         = 0x74,
-        MAX77686_REG_LDO22CTRL2         = 0x75,
-        MAX77686_REG_LDO23CTRL2         = 0x76,
-        MAX77686_REG_LDO24CTRL2         = 0x77,
-        MAX77686_REG_LDO25CTRL2         = 0x78,
-        MAX77686_REG_LDO26CTRL2         = 0x79,
-        /* Reserved: 0x7A-0x7D */
-
-        MAX77686_REG_BBAT_CHG           = 0x7E,
-        MAX77686_REG_32KHZ                      = 0x7F,
-
-        MAX77686_REG_PMIC_END           = 0x80,
-};
-
-enum max77686_rtc_reg {
-        MAX77686_RTC_INT                        = 0x00,
-        MAX77686_RTC_INTM                       = 0x01,
-        MAX77686_RTC_CONTROLM           = 0x02,
-        MAX77686_RTC_CONTROL            = 0x03,
-        MAX77686_RTC_UPDATE0            = 0x04,
-        /* Reserved: 0x5 */
-        MAX77686_WTSR_SMPL_CNTL         = 0x06,
-        MAX77686_RTC_SEC                        = 0x07,
-        MAX77686_RTC_MIN                        = 0x08,
-        MAX77686_RTC_HOUR                       = 0x09,
-        MAX77686_RTC_WEEKDAY            = 0x0A,
-        MAX77686_RTC_MONTH                      = 0x0B,
-        MAX77686_RTC_YEAR                       = 0x0C,
-        MAX77686_RTC_DATE                       = 0x0D,
-        MAX77686_ALARM1_SEC                     = 0x0E,
-        MAX77686_ALARM1_MIN                     = 0x0F,
-        MAX77686_ALARM1_HOUR            = 0x10,
-        MAX77686_ALARM1_WEEKDAY         = 0x11,
-        MAX77686_ALARM1_MONTH           = 0x12,
-        MAX77686_ALARM1_YEAR            = 0x13,
-        MAX77686_ALARM1_DATE            = 0x14,
-        MAX77686_ALARM2_SEC                     = 0x15,
-        MAX77686_ALARM2_MIN                     = 0x16,
-        MAX77686_ALARM2_HOUR            = 0x17,
-        MAX77686_ALARM2_WEEKDAY         = 0x18,
-        MAX77686_ALARM2_MONTH           = 0x19,
-        MAX77686_ALARM2_YEAR            = 0x1A,
-        MAX77686_ALARM2_DATE            = 0x1B,
-};
-
-#define MAX77686_IRQSRC_PMIC    (0)
-#define MAX77686_IRQSRC_RTC             (1 << 0)
-
-enum max77686_irq_source {
-        PMIC_INT1 = 0,
-        PMIC_INT2,
-        RTC_INT,
-
-        MAX77686_IRQ_GROUP_NR,
-};
-
-enum max77686_irq {
-        MAX77686_PMICIRQ_PWRONF,
-        MAX77686_PMICIRQ_PWRONR,
-        MAX77686_PMICIRQ_JIGONBF,
-        MAX77686_PMICIRQ_JIGONBR,
-        MAX77686_PMICIRQ_ACOKBF,
-        MAX77686_PMICIRQ_ACOKBR,
-        MAX77686_PMICIRQ_ONKEY1S,
-        MAX77686_PMICIRQ_MRSTB,
-
-        MAX77686_PMICIRQ_140C,
-        MAX77686_PMICIRQ_120C,
-
-        MAX77686_RTCIRQ_RTC60S,
-        MAX77686_RTCIRQ_RTCA1,
-        MAX77686_RTCIRQ_RTCA2,
-        MAX77686_RTCIRQ_SMPL,
-        MAX77686_RTCIRQ_RTC1S,
-        MAX77686_RTCIRQ_WTSR,
-
-        MAX77686_IRQ_NR,
-};
-
-struct max77686_dev {
-        struct device *dev;
-        struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
-        struct i2c_client *rtc; /* slave addr 0x0c */
-
-        int type;
-
-        struct regmap *regmap;          /* regmap for mfd */
-        struct regmap *rtc_regmap;      /* regmap for rtc */
-
-        struct irq_domain *irq_domain;
-
-        int irq;
-        int irq_gpio;
-        bool wakeup;
-        struct mutex irqlock;
-        int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
-        int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
-};
-
-enum max77686_types {
-        TYPE_MAX77686,
-};
-
-extern int max77686_irq_init(struct max77686_dev *max77686);
-extern void max77686_irq_exit(struct max77686_dev *max77686);
-extern int max77686_irq_resume(struct max77686_dev *max77686);
-
-#endif /*  __LINUX_MFD_MAX77686_PRIV_H */
diff --git a/include/linux/mfd/max77686.h b/include/linux/mfd/max77686.h
deleted file mode 100644
index 46c0f320ed7..00000000000
--- a/include/linux/mfd/max77686.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * max77686.h - Driver for the Maxim 77686
- *
- *  Copyright (C) 2012 Samsung Electrnoics
- *  Chiwoong Byun <woong.byun@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * This driver is based on max8997.h
- *
- * MAX77686 has PMIC, RTC devices.
- * The devices share the same I2C bus and included in
- * this mfd driver.
- */
-
-#ifndef __LINUX_MFD_MAX77686_H
-#define __LINUX_MFD_MAX77686_H
-
-#include <linux/regulator/consumer.h>
-
-/* MAX77686 regulator IDs */
-enum max77686_regulators {
-        MAX77686_LDO1 = 0,
-        MAX77686_LDO2,
-        MAX77686_LDO3,
-        MAX77686_LDO4,
-        MAX77686_LDO5,
-        MAX77686_LDO6,
-        MAX77686_LDO7,
-        MAX77686_LDO8,
-        MAX77686_LDO9,
-        MAX77686_LDO10,
-        MAX77686_LDO11,
-        MAX77686_LDO12,
-        MAX77686_LDO13,
-        MAX77686_LDO14,
-        MAX77686_LDO15,
-        MAX77686_LDO16,
-        MAX77686_LDO17,
-        MAX77686_LDO18,
-        MAX77686_LDO19,
-        MAX77686_LDO20,
-        MAX77686_LDO21,
-        MAX77686_LDO22,
-        MAX77686_LDO23,
-        MAX77686_LDO24,
-        MAX77686_LDO25,
-        MAX77686_LDO26,
-        MAX77686_BUCK1,
-        MAX77686_BUCK2,
-        MAX77686_BUCK3,
-        MAX77686_BUCK4,
-        MAX77686_BUCK5,
-        MAX77686_BUCK6,
-        MAX77686_BUCK7,
-        MAX77686_BUCK8,
-        MAX77686_BUCK9,
-
-        MAX77686_REG_MAX,
-};
-
-struct max77686_regulator_data {
-        int id;
-        struct regulator_init_data *initdata;
-        struct device_node *of_node;
-};
-
-enum max77686_opmode {
-        MAX77686_OPMODE_NORMAL,
-        MAX77686_OPMODE_LP,
-        MAX77686_OPMODE_STANDBY,
-};
-
-struct max77686_opmode_data {
-        int id;
-        int mode;
-};
-
-struct max77686_platform_data {
-        /* IRQ */
-        int irq_gpio;
-        int ono;
-        int wakeup;
-
-        /* ---- PMIC ---- */
-        struct max77686_regulator_data *regulators;
-        int num_regulators;
-
-        struct max77686_opmode_data *opmode_data;
-
-        /*
-         * GPIO-DVS feature is not enabled with the current version of
-         * MAX77686 driver. Buck2/3/4_voltages[0] is used as the default
-         * voltage at probe. DVS/SELB gpios are set as OUTPUT-LOW.
-         */
-        int buck234_gpio_dvs[3]; /* GPIO of [0]DVS1, [1]DVS2, [2]DVS3 */
-        int buck234_gpio_selb[3]; /* [0]SELB2, [1]SELB3, [2]SELB4 */
-        unsigned int buck2_voltage[8]; /* buckx_voltage in uV */
-        unsigned int buck3_voltage[8];
-        unsigned int buck4_voltage[8];
-};
-
-#endif /* __LINUX_MFD_MAX77686_H */
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
deleted file mode 100644
index 1eeae5c0791..00000000000
--- a/include/linux/mfd/max77693-private.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * max77693-private.h - Voltage regulator driver for the Maxim 77693
- *
- *  Copyright (C) 2012 Samsung Electrnoics
- *  SangYoung Son <hello.son@samsung.com>
- *
- * This program is not provided / owned by Maxim Integrated Products.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __LINUX_MFD_MAX77693_PRIV_H
-#define __LINUX_MFD_MAX77693_PRIV_H
-
-#include <linux/i2c.h>
-
-#define MAX77693_NUM_IRQ_MUIC_REGS      3
-#define MAX77693_REG_INVALID            (0xff)
-
-/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
-enum max77693_pmic_reg {
-        MAX77693_LED_REG_IFLASH1                        = 0x00,
-        MAX77693_LED_REG_IFLASH2                        = 0x01,
-        MAX77693_LED_REG_ITORCH                         = 0x02,
-        MAX77693_LED_REG_ITORCHTIMER                    = 0x03,
-        MAX77693_LED_REG_FLASH_TIMER                    = 0x04,
-        MAX77693_LED_REG_FLASH_EN                       = 0x05,
-        MAX77693_LED_REG_MAX_FLASH1                     = 0x06,
-        MAX77693_LED_REG_MAX_FLASH2                     = 0x07,
-        MAX77693_LED_REG_MAX_FLASH3                     = 0x08,
-        MAX77693_LED_REG_MAX_FLASH4                     = 0x09,
-        MAX77693_LED_REG_VOUT_CNTL                      = 0x0A,
-        MAX77693_LED_REG_VOUT_FLASH1                    = 0x0B,
-        MAX77693_LED_REG_VOUT_FLASH2                    = 0x0C,
-        MAX77693_LED_REG_FLASH_INT                      = 0x0E,
-        MAX77693_LED_REG_FLASH_INT_MASK                 = 0x0F,
-        MAX77693_LED_REG_FLASH_INT_STATUS               = 0x10,
-
-        MAX77693_PMIC_REG_PMIC_ID1                      = 0x20,
-        MAX77693_PMIC_REG_PMIC_ID2                      = 0x21,
-        MAX77693_PMIC_REG_INTSRC                        = 0x22,
-        MAX77693_PMIC_REG_INTSRC_MASK                   = 0x23,
-        MAX77693_PMIC_REG_TOPSYS_INT                    = 0x24,
-        MAX77693_PMIC_REG_TOPSYS_INT_MASK               = 0x26,
-        MAX77693_PMIC_REG_TOPSYS_STAT                   = 0x28,
-        MAX77693_PMIC_REG_MAINCTRL1                     = 0x2A,
-        MAX77693_PMIC_REG_LSCNFG                        = 0x2B,
-
-        MAX77693_CHG_REG_CHG_INT                        = 0xB0,
-        MAX77693_CHG_REG_CHG_INT_MASK                   = 0xB1,
-        MAX77693_CHG_REG_CHG_INT_OK                     = 0xB2,
-        MAX77693_CHG_REG_CHG_DETAILS_00                 = 0xB3,
-        MAX77693_CHG_REG_CHG_DETAILS_01                 = 0xB4,
-        MAX77693_CHG_REG_CHG_DETAILS_02                 = 0xB5,
-        MAX77693_CHG_REG_CHG_DETAILS_03                 = 0xB6,
-        MAX77693_CHG_REG_CHG_CNFG_00                    = 0xB7,
-        MAX77693_CHG_REG_CHG_CNFG_01                    = 0xB8,
-        MAX77693_CHG_REG_CHG_CNFG_02                    = 0xB9,
-        MAX77693_CHG_REG_CHG_CNFG_03                    = 0xBA,
-        MAX77693_CHG_REG_CHG_CNFG_04                    = 0xBB,
-        MAX77693_CHG_REG_CHG_CNFG_05                    = 0xBC,
-        MAX77693_CHG_REG_CHG_CNFG_06                    = 0xBD,
-        MAX77693_CHG_REG_CHG_CNFG_07                    = 0xBE,
-        MAX77693_CHG_REG_CHG_CNFG_08                    = 0xBF,
-        MAX77693_CHG_REG_CHG_CNFG_09                    = 0xC0,
-        MAX77693_CHG_REG_CHG_CNFG_10                    = 0xC1,
-        MAX77693_CHG_REG_CHG_CNFG_11                    = 0xC2,
-        MAX77693_CHG_REG_CHG_CNFG_12                    = 0xC3,
-        MAX77693_CHG_REG_CHG_CNFG_13                    = 0xC4,
-        MAX77693_CHG_REG_CHG_CNFG_14                    = 0xC5,
-        MAX77693_CHG_REG_SAFEOUT_CTRL                   = 0xC6,
-
-        MAX77693_PMIC_REG_END,
-};
-
-/* Slave addr = 0x4A: MUIC */
-enum max77693_muic_reg {
-        MAX77693_MUIC_REG_ID            = 0x00,
-        MAX77693_MUIC_REG_INT1          = 0x01,
-        MAX77693_MUIC_REG_INT2          = 0x02,
-        MAX77693_MUIC_REG_INT3          = 0x03,
-        MAX77693_MUIC_REG_STATUS1       = 0x04,
-        MAX77693_MUIC_REG_STATUS2       = 0x05,
-        MAX77693_MUIC_REG_STATUS3       = 0x06,
-        MAX77693_MUIC_REG_INTMASK1      = 0x07,
-        MAX77693_MUIC_REG_INTMASK2      = 0x08,
-        MAX77693_MUIC_REG_INTMASK3      = 0x09,
-        MAX77693_MUIC_REG_CDETCTRL1     = 0x0A,
-        MAX77693_MUIC_REG_CDETCTRL2     = 0x0B,
-        MAX77693_MUIC_REG_CTRL1         = 0x0C,
-        MAX77693_MUIC_REG_CTRL2         = 0x0D,
-        MAX77693_MUIC_REG_CTRL3         = 0x0E,
-
-        MAX77693_MUIC_REG_END,
-};
-
-/* Slave addr = 0x90: Haptic */
-enum max77693_haptic_reg {
-        MAX77693_HAPTIC_REG_STATUS              = 0x00,
-        MAX77693_HAPTIC_REG_CONFIG1             = 0x01,
-        MAX77693_HAPTIC_REG_CONFIG2             = 0x02,
-        MAX77693_HAPTIC_REG_CONFIG_CHNL         = 0x03,
-        MAX77693_HAPTIC_REG_CONFG_CYC1          = 0x04,
-        MAX77693_HAPTIC_REG_CONFG_CYC2          = 0x05,
-        MAX77693_HAPTIC_REG_CONFIG_PER1         = 0x06,
-        MAX77693_HAPTIC_REG_CONFIG_PER2         = 0x07,
-        MAX77693_HAPTIC_REG_CONFIG_PER3         = 0x08,
-        MAX77693_HAPTIC_REG_CONFIG_PER4         = 0x09,
-        MAX77693_HAPTIC_REG_CONFIG_DUTY1        = 0x0A,
-        MAX77693_HAPTIC_REG_CONFIG_DUTY2        = 0x0B,
-        MAX77693_HAPTIC_REG_CONFIG_PWM1         = 0x0C,
-        MAX77693_HAPTIC_REG_CONFIG_PWM2         = 0x0D,
-        MAX77693_HAPTIC_REG_CONFIG_PWM3         = 0x0E,
-        MAX77693_HAPTIC_REG_CONFIG_PWM4         = 0x0F,
-        MAX77693_HAPTIC_REG_REV                 = 0x10,
-
-        MAX77693_HAPTIC_REG_END,
-};
-
-enum max77693_irq_source {
-        LED_INT = 0,
-        TOPSYS_INT,
-        CHG_INT,
-        MUIC_INT1,
-        MUIC_INT2,
-        MUIC_INT3,
-
-        MAX77693_IRQ_GROUP_NR,
-};
-
-enum max77693_irq {
-        /* PMIC - FLASH */
-        MAX77693_LED_IRQ_FLED2_OPEN,
-        MAX77693_LED_IRQ_FLED2_SHORT,
-        MAX77693_LED_IRQ_FLED1_OPEN,
-        MAX77693_LED_IRQ_FLED1_SHORT,
-        MAX77693_LED_IRQ_MAX_FLASH,
-
-        /* PMIC - TOPSYS */
-        MAX77693_TOPSYS_IRQ_T120C_INT,
-        MAX77693_TOPSYS_IRQ_T140C_INT,
-        MAX77693_TOPSYS_IRQ_LOWSYS_INT,
-
-        /* PMIC - Charger */
-        MAX77693_CHG_IRQ_BYP_I,
-        MAX77693_CHG_IRQ_THM_I,
-        MAX77693_CHG_IRQ_BAT_I,
-        MAX77693_CHG_IRQ_CHG_I,
-        MAX77693_CHG_IRQ_CHGIN_I,
-
-        /* MUIC INT1 */
-        MAX77693_MUIC_IRQ_INT1_ADC,
-        MAX77693_MUIC_IRQ_INT1_ADC_LOW,
-        MAX77693_MUIC_IRQ_INT1_ADC_ERR,
-        MAX77693_MUIC_IRQ_INT1_ADC1K,
-
-        /* MUIC INT2 */
-        MAX77693_MUIC_IRQ_INT2_CHGTYP,
-        MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
-        MAX77693_MUIC_IRQ_INT2_DCDTMR,
-        MAX77693_MUIC_IRQ_INT2_DXOVP,
-        MAX77693_MUIC_IRQ_INT2_VBVOLT,
-        MAX77693_MUIC_IRQ_INT2_VIDRM,
-
-        /* MUIC INT3 */
-        MAX77693_MUIC_IRQ_INT3_EOC,
-        MAX77693_MUIC_IRQ_INT3_CGMBC,
-        MAX77693_MUIC_IRQ_INT3_OVP,
-        MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
-        MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
-        MAX77693_MUIC_IRQ_INT3_BAT_DET,
-
-        MAX77693_IRQ_NR,
-};
-
-struct max77693_dev {
-        struct device *dev;
-        struct i2c_client *i2c;         /* 0xCC , PMIC, Charger, Flash LED */
-        struct i2c_client *muic;        /* 0x4A , MUIC */
-        struct i2c_client *haptic;      /* 0x90 , Haptic */
-
-        int type;
-
-        struct regmap *regmap;
-        struct regmap *regmap_muic;
-        struct regmap *regmap_haptic;
-
-        struct irq_domain *irq_domain;
-
-        int irq;
-        int irq_gpio;
-        bool wakeup;
-        struct mutex irqlock;
-        int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
-        int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
-};
-
-enum max77693_types {
-        TYPE_MAX77693,
-};
-
-extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest);
-extern int max77693_bulk_read(struct regmap *map, u8 reg, int count,
-                                u8 *buf);
-extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value);
-extern int max77693_bulk_write(struct regmap *map, u8 reg, int count,
-                                u8 *buf);
-extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask);
-
-extern int max77693_irq_init(struct max77693_dev *max77686);
-extern void max77693_irq_exit(struct max77693_dev *max77686);
-extern int max77693_irq_resume(struct max77693_dev *max77686);
-
-#endif /*  __LINUX_MFD_MAX77693_PRIV_H */
diff --git a/include/linux/mfd/max77693.h b/include/linux/mfd/max77693.h
deleted file mode 100644
index fe03b2d35d4..00000000000
--- a/include/linux/mfd/max77693.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * max77693.h - Driver for the Maxim 77693
- *
- *  Copyright (C) 2012 Samsung Electrnoics
- *  SangYoung Son <hello.son@samsung.com>
- *
- * This program is not provided / owned by Maxim Integrated Products.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * This driver is based on max8997.h
- *
- * MAX77693 has PMIC, Charger, Flash LED, Haptic, MUIC devices.
- * The devices share the same I2C bus and included in
- * this mfd driver.
- */
-
-#ifndef __LINUX_MFD_MAX77693_H
-#define __LINUX_MFD_MAX77693_H
-
-struct max77693_reg_data {
-        u8 addr;
-        u8 data;
-};
-
-struct max77693_muic_platform_data {
-        struct max77693_reg_data *init_data;
-        int num_init_data;
-};
-
-struct max77693_platform_data {
-        int wakeup;
-
-        /* muic data */
-        struct max77693_muic_platform_data *muic_data;
-};
-#endif  /* __LINUX_MFD_MAX77693_H */
diff --git a/include/linux/mfd/max8907.h b/include/linux/mfd/max8907.h
deleted file mode 100644
index b06f7a6a1e8..00000000000
--- a/include/linux/mfd/max8907.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * Functions to access MAX8907 power management chip.
- *
- * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
- * Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __LINUX_MFD_MAX8907_H
-#define __LINUX_MFD_MAX8907_H
-
-#include <linux/mutex.h>
-#include <linux/pm.h>
-
-#define MAX8907_GEN_I2C_ADDR            (0x78 >> 1)
-#define MAX8907_ADC_I2C_ADDR            (0x8e >> 1)
-#define MAX8907_RTC_I2C_ADDR            (0xd0 >> 1)
-
-/* MAX8907 register map */
-#define MAX8907_REG_SYSENSEL            0x00
-#define MAX8907_REG_ON_OFF_IRQ1         0x01
-#define MAX8907_REG_ON_OFF_IRQ1_MASK    0x02
-#define MAX8907_REG_ON_OFF_STAT         0x03
-#define MAX8907_REG_SDCTL1              0x04
-#define MAX8907_REG_SDSEQCNT1           0x05
-#define MAX8907_REG_SDV1                0x06
-#define MAX8907_REG_SDCTL2              0x07
-#define MAX8907_REG_SDSEQCNT2           0x08
-#define MAX8907_REG_SDV2                0x09
-#define MAX8907_REG_SDCTL3              0x0A
-#define MAX8907_REG_SDSEQCNT3           0x0B
-#define MAX8907_REG_SDV3                0x0C
-#define MAX8907_REG_ON_OFF_IRQ2         0x0D
-#define MAX8907_REG_ON_OFF_IRQ2_MASK    0x0E
-#define MAX8907_REG_RESET_CNFG          0x0F
-#define MAX8907_REG_LDOCTL16            0x10
-#define MAX8907_REG_LDOSEQCNT16         0x11
-#define MAX8907_REG_LDO16VOUT           0x12
-#define MAX8907_REG_SDBYSEQCNT          0x13
-#define MAX8907_REG_LDOCTL17            0x14
-#define MAX8907_REG_LDOSEQCNT17         0x15
-#define MAX8907_REG_LDO17VOUT           0x16
-#define MAX8907_REG_LDOCTL1             0x18
-#define MAX8907_REG_LDOSEQCNT1          0x19
-#define MAX8907_REG_LDO1VOUT            0x1A
-#define MAX8907_REG_LDOCTL2             0x1C
-#define MAX8907_REG_LDOSEQCNT2          0x1D
-#define MAX8907_REG_LDO2VOUT            0x1E
-#define MAX8907_REG_LDOCTL3             0x20
-#define MAX8907_REG_LDOSEQCNT3          0x21
-#define MAX8907_REG_LDO3VOUT            0x22
-#define MAX8907_REG_LDOCTL4             0x24
-#define MAX8907_REG_LDOSEQCNT4          0x25
-#define MAX8907_REG_LDO4VOUT            0x26
-#define MAX8907_REG_LDOCTL5             0x28
-#define MAX8907_REG_LDOSEQCNT5          0x29
-#define MAX8907_REG_LDO5VOUT            0x2A
-#define MAX8907_REG_LDOCTL6             0x2C
-#define MAX8907_REG_LDOSEQCNT6          0x2D
-#define MAX8907_REG_LDO6VOUT            0x2E
-#define MAX8907_REG_LDOCTL7             0x30
-#define MAX8907_REG_LDOSEQCNT7          0x31
-#define MAX8907_REG_LDO7VOUT            0x32
-#define MAX8907_REG_LDOCTL8             0x34
-#define MAX8907_REG_LDOSEQCNT8          0x35
-#define MAX8907_REG_LDO8VOUT            0x36
-#define MAX8907_REG_LDOCTL9             0x38
-#define MAX8907_REG_LDOSEQCNT9          0x39
-#define MAX8907_REG_LDO9VOUT            0x3A
-#define MAX8907_REG_LDOCTL10            0x3C
-#define MAX8907_REG_LDOSEQCNT10         0x3D
-#define MAX8907_REG_LDO10VOUT           0x3E
-#define MAX8907_REG_LDOCTL11            0x40
-#define MAX8907_REG_LDOSEQCNT11         0x41
-#define MAX8907_REG_LDO11VOUT           0x42
-#define MAX8907_REG_LDOCTL12            0x44
-#define MAX8907_REG_LDOSEQCNT12         0x45
-#define MAX8907_REG_LDO12VOUT           0x46
-#define MAX8907_REG_LDOCTL13            0x48
-#define MAX8907_REG_LDOSEQCNT13         0x49
-#define MAX8907_REG_LDO13VOUT           0x4A
-#define MAX8907_REG_LDOCTL14            0x4C
-#define MAX8907_REG_LDOSEQCNT14         0x4D
-#define MAX8907_REG_LDO14VOUT           0x4E
-#define MAX8907_REG_LDOCTL15            0x50
-#define MAX8907_REG_LDOSEQCNT15         0x51
-#define MAX8907_REG_LDO15VOUT           0x52
-#define MAX8907_REG_OUT5VEN             0x54
-#define MAX8907_REG_OUT5VSEQ            0x55
-#define MAX8907_REG_OUT33VEN            0x58
-#define MAX8907_REG_OUT33VSEQ           0x59
-#define MAX8907_REG_LDOCTL19            0x5C
-#define MAX8907_REG_LDOSEQCNT19         0x5D
-#define MAX8907_REG_LDO19VOUT           0x5E
-#define MAX8907_REG_LBCNFG              0x60
-#define MAX8907_REG_SEQ1CNFG            0x64
-#define MAX8907_REG_SEQ2CNFG            0x65
-#define MAX8907_REG_SEQ3CNFG            0x66
-#define MAX8907_REG_SEQ4CNFG            0x67
-#define MAX8907_REG_SEQ5CNFG            0x68
-#define MAX8907_REG_SEQ6CNFG            0x69
-#define MAX8907_REG_SEQ7CNFG            0x6A
-#define MAX8907_REG_LDOCTL18            0x72
-#define MAX8907_REG_LDOSEQCNT18         0x73
-#define MAX8907_REG_LDO18VOUT           0x74
-#define MAX8907_REG_BBAT_CNFG           0x78
-#define MAX8907_REG_CHG_CNTL1           0x7C
-#define MAX8907_REG_CHG_CNTL2           0x7D
-#define MAX8907_REG_CHG_IRQ1            0x7E
-#define MAX8907_REG_CHG_IRQ2            0x7F
-#define MAX8907_REG_CHG_IRQ1_MASK       0x80
-#define MAX8907_REG_CHG_IRQ2_MASK       0x81
-#define MAX8907_REG_CHG_STAT            0x82
-#define MAX8907_REG_WLED_MODE_CNTL      0x84
-#define MAX8907_REG_ILED_CNTL           0x84
-#define MAX8907_REG_II1RR               0x8E
-#define MAX8907_REG_II2RR               0x8F
-#define MAX8907_REG_LDOCTL20            0x9C
-#define MAX8907_REG_LDOSEQCNT20         0x9D
-#define MAX8907_REG_LDO20VOUT           0x9E
-
-/* RTC register map */
-#define MAX8907_REG_RTC_SEC             0x00
-#define MAX8907_REG_RTC_MIN             0x01
-#define MAX8907_REG_RTC_HOURS           0x02
-#define MAX8907_REG_RTC_WEEKDAY         0x03
-#define MAX8907_REG_RTC_DATE            0x04
-#define MAX8907_REG_RTC_MONTH           0x05
-#define MAX8907_REG_RTC_YEAR1           0x06
-#define MAX8907_REG_RTC_YEAR2           0x07
-#define MAX8907_REG_ALARM0_SEC          0x08
-#define MAX8907_REG_ALARM0_MIN          0x09
-#define MAX8907_REG_ALARM0_HOURS        0x0A
-#define MAX8907_REG_ALARM0_WEEKDAY      0x0B
-#define MAX8907_REG_ALARM0_DATE         0x0C
-#define MAX8907_REG_ALARM0_MONTH        0x0D
-#define MAX8907_REG_ALARM0_YEAR1        0x0E
-#define MAX8907_REG_ALARM0_YEAR2        0x0F
-#define MAX8907_REG_ALARM1_SEC          0x10
-#define MAX8907_REG_ALARM1_MIN          0x11
-#define MAX8907_REG_ALARM1_HOURS        0x12
-#define MAX8907_REG_ALARM1_WEEKDAY      0x13
-#define MAX8907_REG_ALARM1_DATE         0x14
-#define MAX8907_REG_ALARM1_MONTH        0x15
-#define MAX8907_REG_ALARM1_YEAR1        0x16
-#define MAX8907_REG_ALARM1_YEAR2        0x17
-#define MAX8907_REG_ALARM0_CNTL         0x18
-#define MAX8907_REG_ALARM1_CNTL         0x19
-#define MAX8907_REG_RTC_STATUS          0x1A
-#define MAX8907_REG_RTC_CNTL            0x1B
-#define MAX8907_REG_RTC_IRQ             0x1C
-#define MAX8907_REG_RTC_IRQ_MASK        0x1D
-#define MAX8907_REG_MPL_CNTL            0x1E
-
-/* ADC and Touch Screen Controller register map */
-#define MAX8907_CTL                     0
-#define MAX8907_SEQCNT                  1
-#define MAX8907_VOUT                    2
-
-/* mask bit fields */
-#define MAX8907_MASK_LDO_SEQ            0x1C
-#define MAX8907_MASK_LDO_EN             0x01
-#define MAX8907_MASK_VBBATTCV           0x03
-#define MAX8907_MASK_OUT5V_VINEN        0x10
-#define MAX8907_MASK_OUT5V_ENSRC        0x0E
-#define MAX8907_MASK_OUT5V_EN           0x01
-#define MAX8907_MASK_POWER_OFF          0x40
-
-/* Regulator IDs */
-#define MAX8907_MBATT   0
-#define MAX8907_SD1     1
-#define MAX8907_SD2     2
-#define MAX8907_SD3     3
-#define MAX8907_LDO1    4
-#define MAX8907_LDO2    5
-#define MAX8907_LDO3    6
-#define MAX8907_LDO4    7
-#define MAX8907_LDO5    8
-#define MAX8907_LDO6    9
-#define MAX8907_LDO7    10
-#define MAX8907_LDO8    11
-#define MAX8907_LDO9    12
-#define MAX8907_LDO10   13
-#define MAX8907_LDO11   14
-#define MAX8907_LDO12   15
-#define MAX8907_LDO13   16
-#define MAX8907_LDO14   17
-#define MAX8907_LDO15   18
-#define MAX8907_LDO16   19
-#define MAX8907_LDO17   20
-#define MAX8907_LDO18   21
-#define MAX8907_LDO19   22
-#define MAX8907_LDO20   23
-#define MAX8907_OUT5V   24
-#define MAX8907_OUT33V  25
-#define MAX8907_BBAT    26
-#define MAX8907_SDBY    27
-#define MAX8907_VRTC    28
-#define MAX8907_NUM_REGULATORS (MAX8907_VRTC + 1)
-
-/* IRQ definitions */
-enum {
-        MAX8907_IRQ_VCHG_DC_OVP = 0,
-        MAX8907_IRQ_VCHG_DC_F,
-        MAX8907_IRQ_VCHG_DC_R,
-        MAX8907_IRQ_VCHG_THM_OK_R,
-        MAX8907_IRQ_VCHG_THM_OK_F,
-        MAX8907_IRQ_VCHG_MBATTLOW_F,
-        MAX8907_IRQ_VCHG_MBATTLOW_R,
-        MAX8907_IRQ_VCHG_RST,
-        MAX8907_IRQ_VCHG_DONE,
-        MAX8907_IRQ_VCHG_TOPOFF,
-        MAX8907_IRQ_VCHG_TMR_FAULT,
-
-        MAX8907_IRQ_GPM_RSTIN = 0,
-        MAX8907_IRQ_GPM_MPL,
-        MAX8907_IRQ_GPM_SW_3SEC,
-        MAX8907_IRQ_GPM_EXTON_F,
-        MAX8907_IRQ_GPM_EXTON_R,
-        MAX8907_IRQ_GPM_SW_1SEC,
-        MAX8907_IRQ_GPM_SW_F,
-        MAX8907_IRQ_GPM_SW_R,
-        MAX8907_IRQ_GPM_SYSCKEN_F,
-        MAX8907_IRQ_GPM_SYSCKEN_R,
-
-        MAX8907_IRQ_RTC_ALARM1 = 0,
-        MAX8907_IRQ_RTC_ALARM0,
-};
-
-struct max8907_platform_data {
-        struct regulator_init_data *init_data[MAX8907_NUM_REGULATORS];
-        bool pm_off;
-};
-
-struct regmap_irq_chips_data;
-
-struct max8907 {
-        struct device                   *dev;
-        struct mutex                    irq_lock;
-        struct i2c_client               *i2c_gen;
-        struct i2c_client               *i2c_rtc;
-        struct regmap                   *regmap_gen;
-        struct regmap                   *regmap_rtc;
-        struct regmap_irq_chip_data     *irqc_chg;
-        struct regmap_irq_chip_data     *irqc_on_off;
-        struct regmap_irq_chip_data     *irqc_rtc;
-};
-
-#endif
diff --git a/include/linux/mfd/max8925.h b/include/linux/mfd/max8925.h
index 74d8e296963..5259dfe8c58 100644
--- a/include/linux/mfd/max8925.h
+++ b/include/linux/mfd/max8925.h
@@ -158,6 +158,8 @@ enum {
 #define TSC_IRQ_MASK                    (0x03)
 #define RTC_IRQ_MASK                    (0x0c)
 
+#define MAX8925_MAX_REGULATOR           (23)
+
 #define MAX8925_NAME_SIZE               (32)
 
 /* IRQ definitions */
@@ -165,6 +167,9 @@ enum {
         MAX8925_IRQ_VCHG_DC_OVP,
         MAX8925_IRQ_VCHG_DC_F,
         MAX8925_IRQ_VCHG_DC_R,
+        MAX8925_IRQ_VCHG_USB_OVP,
+        MAX8925_IRQ_VCHG_USB_F,
+        MAX8925_IRQ_VCHG_USB_R,
         MAX8925_IRQ_VCHG_THM_OK_R,
         MAX8925_IRQ_VCHG_THM_OK_F,
         MAX8925_IRQ_VCHG_SYSLOW_F,
@@ -201,8 +206,6 @@ struct max8925_chip {
         int                     irq_base;
         int                     core_irq;
         int                     tsc_irq;
-
-        unsigned int            wakeup_flag;
 };
 
 struct max8925_backlight_pdata {
@@ -220,10 +223,6 @@ struct max8925_power_pdata {
         unsigned        batt_detect:1;
         unsigned        topoff_threshold:2;
         unsigned        fast_charge:3;  /* charge current */
-        unsigned        no_temp_support:1; /* set if no temperature detect */
-        unsigned        no_insert_detect:1; /* set if no ac insert detect */
-        char            **supplied_to;
-        int             num_supplicants;
 };
 
 /*
@@ -234,29 +233,7 @@ struct max8925_platform_data {
         struct max8925_backlight_pdata  *backlight;
         struct max8925_touch_pdata      *touch;
         struct max8925_power_pdata      *power;
-        struct regulator_init_data      *sd1;
-        struct regulator_init_data      *sd2;
-        struct regulator_init_data      *sd3;
-        struct regulator_init_data      *ldo1;
-        struct regulator_init_data      *ldo2;
-        struct regulator_init_data      *ldo3;
-        struct regulator_init_data      *ldo4;
-        struct regulator_init_data      *ldo5;
-        struct regulator_init_data      *ldo6;
-        struct regulator_init_data      *ldo7;
-        struct regulator_init_data      *ldo8;
-        struct regulator_init_data      *ldo9;
-        struct regulator_init_data      *ldo10;
-        struct regulator_init_data      *ldo11;
-        struct regulator_init_data      *ldo12;
-        struct regulator_init_data      *ldo13;
-        struct regulator_init_data      *ldo14;
-        struct regulator_init_data      *ldo15;
-        struct regulator_init_data      *ldo16;
-        struct regulator_init_data      *ldo17;
-        struct regulator_init_data      *ldo18;
-        struct regulator_init_data      *ldo19;
-        struct regulator_init_data      *ldo20;
+        struct regulator_init_data      *regulator[MAX8925_MAX_REGULATOR];
 
         int             irq_base;
         int             tsc_irq;
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
index 6ae21bf47d6..5ff2400ad46 100644
--- a/include/linux/mfd/max8997-private.h
+++ b/include/linux/mfd/max8997-private.h
@@ -23,8 +23,6 @@
 #define __LINUX_MFD_MAX8997_PRIV_H
 
 #include <linux/i2c.h>
-#include <linux/export.h>
-#include <linux/irqdomain.h>
 
 #define MAX8997_REG_INVALID     (0xff)
 
@@ -316,7 +314,6 @@ enum max8997_irq {
 #define MAX8997_NUM_GPIO        12
 struct max8997_dev {
         struct device *dev;
-        struct max8997_platform_data *pdata;
         struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
         struct i2c_client *rtc; /* slave addr 0x0c */
         struct i2c_client *haptic; /* slave addr 0x90 */
@@ -328,7 +325,8 @@ struct max8997_dev {
 
         int irq;
         int ono;
-        struct irq_domain *irq_domain;
+        int irq_base;
+        bool wakeup;
         struct mutex irqlock;
         int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
         int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index 1d4a4fe6ac3..0bbd13dbe33 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -75,113 +75,11 @@ enum max8998_regulators {
 struct max8997_regulator_data {
         int id;
         struct regulator_init_data *initdata;
-        struct device_node *reg_node;
-};
-
-enum max8997_muic_usb_type {
-        MAX8997_USB_HOST,
-        MAX8997_USB_DEVICE,
-};
-
-enum max8997_muic_charger_type {
-        MAX8997_CHARGER_TYPE_NONE = 0,
-        MAX8997_CHARGER_TYPE_USB,
-        MAX8997_CHARGER_TYPE_DOWNSTREAM_PORT,
-        MAX8997_CHARGER_TYPE_DEDICATED_CHG,
-        MAX8997_CHARGER_TYPE_500MA,
-        MAX8997_CHARGER_TYPE_1A,
-        MAX8997_CHARGER_TYPE_DEAD_BATTERY = 7,
-};
-
-struct max8997_muic_reg_data {
-        u8 addr;
-        u8 data;
-};
-
-/**
- * struct max8997_muic_platform_data
- * @init_data: array of max8997_muic_reg_data
- *             used for initializing registers of MAX8997 MUIC device
- * @num_init_data: array size of init_data
- */
-struct max8997_muic_platform_data {
-        struct max8997_muic_reg_data *init_data;
-        int num_init_data;
-};
-
-enum max8997_haptic_motor_type {
-        MAX8997_HAPTIC_ERM,
-        MAX8997_HAPTIC_LRA,
-};
-
-enum max8997_haptic_pulse_mode {
-        MAX8997_EXTERNAL_MODE,
-        MAX8997_INTERNAL_MODE,
-};
-
-enum max8997_haptic_pwm_divisor {
-        MAX8997_PWM_DIVISOR_32,
-        MAX8997_PWM_DIVISOR_64,
-        MAX8997_PWM_DIVISOR_128,
-        MAX8997_PWM_DIVISOR_256,
-};
-
-/**
- * max8997_haptic_platform_data
- * @pwm_channel_id: channel number of PWM device
- *                  valid for MAX8997_EXTERNAL_MODE
- * @pwm_period: period in nano second for PWM device
- *              valid for MAX8997_EXTERNAL_MODE
- * @type: motor type
- * @mode: pulse mode
- *     MAX8997_EXTERNAL_MODE: external PWM device is used to control motor
- *     MAX8997_INTERNAL_MODE: internal pulse generator is used to control motor
- * @pwm_divisor: divisor for external PWM device
- * @internal_mode_pattern: internal mode pattern for internal mode
- *     [0 - 3]: valid pattern number
- * @pattern_cycle: the number of cycles of the waveform
- *                 for the internal mode pattern
- *     [0 - 15]: available cycles
- * @pattern_signal_period: period of the waveform for the internal mode pattern
- *     [0 - 255]: available period
- */
-struct max8997_haptic_platform_data {
-        unsigned int pwm_channel_id;
-        unsigned int pwm_period;
-
-        enum max8997_haptic_motor_type type;
-        enum max8997_haptic_pulse_mode mode;
-        enum max8997_haptic_pwm_divisor pwm_divisor;
-
-        unsigned int internal_mode_pattern;
-        unsigned int pattern_cycle;
-        unsigned int pattern_signal_period;
-};
-
-enum max8997_led_mode {
-        MAX8997_NONE,
-        MAX8997_FLASH_MODE,
-        MAX8997_MOVIE_MODE,
-        MAX8997_FLASH_PIN_CONTROL_MODE,
-        MAX8997_MOVIE_PIN_CONTROL_MODE,
-};
-
-/**
- *  struct max8997_led_platform_data
- *  The number of LED devices for MAX8997 is two
- *  @mode: LED mode for each LED device
- *  @brightness: initial brightness for each LED device
- *      range:
- *      [0 - 31]: MAX8997_FLASH_MODE and MAX8997_FLASH_PIN_CONTROL_MODE
- *      [0 - 15]: MAX8997_MOVIE_MODE and MAX8997_MOVIE_PIN_CONTROL_MODE
- */
-struct max8997_led_platform_data {
-        enum max8997_led_mode mode[2];
-        u8 brightness[2];
 };
 
 struct max8997_platform_data {
         /* IRQ */
+        int irq_base;
         int ono;
         int wakeup;
 
@@ -215,15 +113,10 @@ struct max8997_platform_data {
         /* charge Full Timeout */
         int timeout; /* 0 (no timeout), 5, 6, 7 hours */
 
-        /* ---- MUIC ---- */
-        struct max8997_muic_platform_data *muic_pdata;
-
-        /* ---- HAPTIC ---- */
-        struct max8997_haptic_platform_data *haptic_pdata;
-
+        /* MUIC: Not implemented */
+        /* HAPTIC: Not implemented */
         /* RTC: Not implemented */
-        /* ---- LED ---- */
-        struct max8997_led_platform_data *led_pdata;
+        /* Flash: Not implemented */
 };
 
 #endif /* __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/max8998.h b/include/linux/mfd/max8998.h
index 6823548d0c0..f4f0dfa4698 100644
--- a/include/linux/mfd/max8998.h
+++ b/include/linux/mfd/max8998.h
@@ -67,7 +67,7 @@ struct max8998_regulator_data {
 /**
  * struct max8998_board - packages regulator init data
  * @regulators: array of defined regulators
- * @num_regulators: number of regulators used
+ * @num_regulators: number of regultors used
  * @irq_base: base IRQ number for max8998, required for IRQs
  * @ono: power onoff IRQ number for max8998
  * @buck_voltage_lock: Do NOT change the values of the following six
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
index a8eeda773a7..7d0f3d6a000 100644
--- a/include/linux/mfd/mc13783.h
+++ b/include/linux/mfd/mc13783.h
@@ -12,6 +12,117 @@
 
 #include <linux/mfd/mc13xxx.h>
 
+struct mc13783;
+
+struct mc13xxx *mc13783_to_mc13xxx(struct mc13783 *mc13783);
+
+static inline void mc13783_lock(struct mc13783 *mc13783)
+{
+        mc13xxx_lock(mc13783_to_mc13xxx(mc13783));
+}
+
+static inline void mc13783_unlock(struct mc13783 *mc13783)
+{
+        mc13xxx_unlock(mc13783_to_mc13xxx(mc13783));
+}
+
+static inline int mc13783_reg_read(struct mc13783 *mc13783,
+                unsigned int offset, u32 *val)
+{
+        return mc13xxx_reg_read(mc13783_to_mc13xxx(mc13783), offset, val);
+}
+
+static inline int mc13783_reg_write(struct mc13783 *mc13783,
+                unsigned int offset, u32 val)
+{
+        return mc13xxx_reg_write(mc13783_to_mc13xxx(mc13783), offset, val);
+}
+
+static inline int mc13783_reg_rmw(struct mc13783 *mc13783,
+                unsigned int offset, u32 mask, u32 val)
+{
+        return mc13xxx_reg_rmw(mc13783_to_mc13xxx(mc13783), offset, mask, val);
+}
+
+static inline int mc13783_get_flags(struct mc13783 *mc13783)
+{
+        return mc13xxx_get_flags(mc13783_to_mc13xxx(mc13783));
+}
+
+static inline int mc13783_irq_request(struct mc13783 *mc13783, int irq,
+                irq_handler_t handler, const char *name, void *dev)
+{
+        return mc13xxx_irq_request(mc13783_to_mc13xxx(mc13783), irq,
+                        handler, name, dev);
+}
+
+static inline int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
+                irq_handler_t handler, const char *name, void *dev)
+{
+        return mc13xxx_irq_request_nounmask(mc13783_to_mc13xxx(mc13783), irq,
+                        handler, name, dev);
+}
+
+static inline int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
+{
+        return mc13xxx_irq_free(mc13783_to_mc13xxx(mc13783), irq, dev);
+}
+
+static inline int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
+{
+        return mc13xxx_irq_mask(mc13783_to_mc13xxx(mc13783), irq);
+}
+
+static inline int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
+{
+        return mc13xxx_irq_unmask(mc13783_to_mc13xxx(mc13783), irq);
+}
+static inline int mc13783_irq_status(struct mc13783 *mc13783, int irq,
+                int *enabled, int *pending)
+{
+        return mc13xxx_irq_status(mc13783_to_mc13xxx(mc13783),
+                        irq, enabled, pending);
+}
+
+static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
+{
+        return mc13xxx_irq_ack(mc13783_to_mc13xxx(mc13783), irq);
+}
+
+#define MC13783_ADC0            43
+#define MC13783_ADC0_ADREFEN            (1 << 10)
+#define MC13783_ADC0_ADREFMODE          (1 << 11)
+#define MC13783_ADC0_TSMOD0             (1 << 12)
+#define MC13783_ADC0_TSMOD1             (1 << 13)
+#define MC13783_ADC0_TSMOD2             (1 << 14)
+#define MC13783_ADC0_ADINC1             (1 << 16)
+#define MC13783_ADC0_ADINC2             (1 << 17)
+
+#define MC13783_ADC0_TSMOD_MASK         (MC13783_ADC0_TSMOD0 | \
+                                        MC13783_ADC0_TSMOD1 | \
+                                        MC13783_ADC0_TSMOD2)
+
+#define mc13783_regulator_init_data mc13xxx_regulator_init_data
+#define mc13783_regulator_platform_data mc13xxx_regulator_platform_data
+#define mc13783_led_platform_data mc13xxx_led_platform_data
+#define mc13783_leds_platform_data mc13xxx_leds_platform_data
+
+#define mc13783_platform_data mc13xxx_platform_data
+#define MC13783_USE_TOUCHSCREEN MC13XXX_USE_TOUCHSCREEN
+#define MC13783_USE_CODEC       MC13XXX_USE_CODEC
+#define MC13783_USE_ADC         MC13XXX_USE_ADC
+#define MC13783_USE_RTC         MC13XXX_USE_RTC
+#define MC13783_USE_REGULATOR   MC13XXX_USE_REGULATOR
+#define MC13783_USE_LED         MC13XXX_USE_LED
+
+#define MC13783_ADC_MODE_TS             1
+#define MC13783_ADC_MODE_SINGLE_CHAN    2
+#define MC13783_ADC_MODE_MULT_CHAN      3
+
+int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
+                unsigned int channel, unsigned int *sample);
+
+
 #define MC13783_REG_SW1A                0
 #define MC13783_REG_SW1B                1
 #define MC13783_REG_SW2A                2
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
index bf070755982..c064beaaccb 100644
--- a/include/linux/mfd/mc13xxx.h
+++ b/include/linux/mfd/mc13xxx.h
@@ -37,10 +37,6 @@ int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq);
 
 int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
 
-int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
-                unsigned int mode, unsigned int channel,
-                u8 ato, bool atox, unsigned int *sample);
-
 #define MC13XXX_IRQ_ADCDONE     0
 #define MC13XXX_IRQ_ADCBISDONE  1
 #define MC13XXX_IRQ_TS          2
@@ -70,7 +66,6 @@ struct regulator_init_data;
 struct mc13xxx_regulator_init_data {
         int id;
         struct regulator_init_data *init_data;
-        struct device_node *node;
 };
 
 struct mc13xxx_regulator_platform_data {
@@ -142,80 +137,17 @@ struct mc13xxx_leds_platform_data {
         char tc3_period;
 };
 
-struct mc13xxx_buttons_platform_data {
-#define MC13783_BUTTON_DBNC_0MS         0
-#define MC13783_BUTTON_DBNC_30MS        1
-#define MC13783_BUTTON_DBNC_150MS       2
-#define MC13783_BUTTON_DBNC_750MS       3
-#define MC13783_BUTTON_ENABLE           (1 << 2)
-#define MC13783_BUTTON_POL_INVERT       (1 << 3)
-#define MC13783_BUTTON_RESET_EN         (1 << 4)
-        int b1on_flags;
-        unsigned short b1on_key;
-        int b2on_flags;
-        unsigned short b2on_key;
-        int b3on_flags;
-        unsigned short b3on_key;
-};
-
-struct mc13xxx_ts_platform_data {
-        /* Delay between Touchscreen polarization and ADC Conversion.
-         * Given in clock ticks of a 32 kHz clock which gives a granularity of
-         * about 30.5ms */
-        u8 ato;
-
-#define MC13783_TS_ATO_FIRST false
-#define MC13783_TS_ATO_EACH  true
-        /* Use the ATO delay only for the first conversion or for each one */
-        bool atox;
-};
-
-enum mc13783_ssi_port {
-        MC13783_SSI1_PORT,
-        MC13783_SSI2_PORT,
-};
-
-struct mc13xxx_codec_platform_data {
-        enum mc13783_ssi_port adc_ssi_port;
-        enum mc13783_ssi_port dac_ssi_port;
-};
-
 struct mc13xxx_platform_data {
 #define MC13XXX_USE_TOUCHSCREEN (1 << 0)
 #define MC13XXX_USE_CODEC       (1 << 1)
 #define MC13XXX_USE_ADC         (1 << 2)
 #define MC13XXX_USE_RTC         (1 << 3)
+#define MC13XXX_USE_REGULATOR   (1 << 4)
+#define MC13XXX_USE_LED         (1 << 5)
         unsigned int flags;
 
         struct mc13xxx_regulator_platform_data regulators;
         struct mc13xxx_leds_platform_data *leds;
-        struct mc13xxx_buttons_platform_data *buttons;
-        struct mc13xxx_ts_platform_data touch;
-        struct mc13xxx_codec_platform_data *codec;
 };
 
-#define MC13XXX_ADC_MODE_TS             1
-#define MC13XXX_ADC_MODE_SINGLE_CHAN    2
-#define MC13XXX_ADC_MODE_MULT_CHAN      3
-
-#define MC13XXX_ADC0            43
-#define MC13XXX_ADC0_LICELLCON          (1 << 0)
-#define MC13XXX_ADC0_CHRGICON           (1 << 1)
-#define MC13XXX_ADC0_BATICON            (1 << 2)
-#define MC13XXX_ADC0_ADREFEN            (1 << 10)
-#define MC13XXX_ADC0_TSMOD0             (1 << 12)
-#define MC13XXX_ADC0_TSMOD1             (1 << 13)
-#define MC13XXX_ADC0_TSMOD2             (1 << 14)
-#define MC13XXX_ADC0_ADINC1             (1 << 16)
-#define MC13XXX_ADC0_ADINC2             (1 << 17)
-
-#define MC13XXX_ADC0_TSMOD_MASK         (MC13XXX_ADC0_TSMOD0 | \
-                                        MC13XXX_ADC0_TSMOD1 | \
-                                        MC13XXX_ADC0_TSMOD2)
-
-#define MC13XXX_ADC0_CONFIG_MASK        (MC13XXX_ADC0_TSMOD_MASK | \
-                                        MC13XXX_ADC0_LICELLCON | \
-                                        MC13XXX_ADC0_CHRGICON | \
-                                        MC13XXX_ADC0_BATICON)
-
 #endif /* ifndef __LINUX_MFD_MC13XXX_H */
diff --git a/include/linux/mfd/mcp.h b/include/linux/mfd/mcp.h
index a9e8bd15767..ee496708e38 100644
--- a/include/linux/mfd/mcp.h
+++ b/include/linux/mfd/mcp.h
@@ -10,6 +10,8 @@
 #ifndef MCP_H
 #define MCP_H
 
+#include <mach/dma.h>
+
 struct mcp_ops;
 
 struct mcp {
@@ -19,7 +21,12 @@ struct mcp {
         int             use_count;
         unsigned int    sclk_rate;
         unsigned int    rw_timeout;
+        dma_device_t    dma_audio_rd;
+        dma_device_t    dma_audio_wr;
+        dma_device_t    dma_telco_rd;
+        dma_device_t    dma_telco_wr;
         struct device   attached_device;
+        int             gpio_base;
 };
 
 struct mcp_ops {
@@ -40,14 +47,15 @@ void mcp_disable(struct mcp *);
 #define mcp_get_sclk_rate(mcp)  ((mcp)->sclk_rate)
 
 struct mcp *mcp_host_alloc(struct device *, size_t);
-int mcp_host_add(struct mcp *, void *);
-void mcp_host_del(struct mcp *);
-void mcp_host_free(struct mcp *);
+int mcp_host_register(struct mcp *);
+void mcp_host_unregister(struct mcp *);
 
 struct mcp_driver {
         struct device_driver drv;
         int (*probe)(struct mcp *);
         void (*remove)(struct mcp *);
+        int (*suspend)(struct mcp *, pm_message_t);
+        int (*resume)(struct mcp *);
 };
 
 int mcp_driver_register(struct mcp_driver *);
@@ -56,9 +64,6 @@ void mcp_driver_unregister(struct mcp_driver *);
 #define mcp_get_drvdata(mcp)    dev_get_drvdata(&(mcp)->attached_device)
 #define mcp_set_drvdata(mcp,d)  dev_set_drvdata(&(mcp)->attached_device, d)
 
-static inline void *mcp_priv(struct mcp *mcp)
-{
-        return mcp + 1;
-}
+#define mcp_priv(mcp)           ((void *)((mcp)+1))
 
 #endif
diff --git a/include/linux/mfd/menelaus.h b/include/linux/mfd/menelaus.h
deleted file mode 100644
index f097e89134c..00000000000
--- a/include/linux/mfd/menelaus.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Functions to access Menelaus power management chip
- */
-
-#ifndef __ASM_ARCH_MENELAUS_H
-#define __ASM_ARCH_MENELAUS_H
-
-struct device;
-
-struct menelaus_platform_data {
-        int (* late_init)(struct device *dev);
-};
-
-extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
-                                          void *data);
-extern void menelaus_unregister_mmc_callback(void);
-extern int menelaus_set_mmc_opendrain(int slot, int enable);
-extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
-
-extern int menelaus_set_vmem(unsigned int mV);
-extern int menelaus_set_vio(unsigned int mV);
-extern int menelaus_set_vmmc(unsigned int mV);
-extern int menelaus_set_vaux(unsigned int mV);
-extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
-extern int menelaus_set_slot_sel(int enable);
-extern int menelaus_get_slot_pin_states(void);
-extern int menelaus_set_vcore_sw(unsigned int mV);
-extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
-
-#define EN_VPLL_SLEEP   (1 << 7)
-#define EN_VMMC_SLEEP   (1 << 6)
-#define EN_VAUX_SLEEP   (1 << 5)
-#define EN_VIO_SLEEP    (1 << 4)
-#define EN_VMEM_SLEEP   (1 << 3)
-#define EN_DC3_SLEEP    (1 << 2)
-#define EN_DC2_SLEEP    (1 << 1)
-#define EN_VC_SLEEP     (1 << 0)
-
-extern int menelaus_set_regulator_sleep(int enable, u32 val);
-
-#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
-#define omap_has_menelaus()     1
-#else
-#define omap_has_menelaus()     0
-#endif
-
-#endif
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
deleted file mode 100644
index 29f6616e12f..00000000000
--- a/include/linux/mfd/palmas.h
+++ /dev/null
@@ -1,2792 +0,0 @@
-/*
- * TI Palmas
- *
- * Copyright 2011 Texas Instruments Inc.
- *
- * Author: Graeme Gregory <gg@slimlogic.co.uk>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under  the terms of the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __LINUX_MFD_PALMAS_H
-#define __LINUX_MFD_PALMAS_H
-
-#include <linux/usb/otg.h>
-#include <linux/leds.h>
-#include <linux/regmap.h>
-#include <linux/regulator/driver.h>
-
-#define PALMAS_NUM_CLIENTS              3
-
-struct palmas_pmic;
-struct palmas_gpadc;
-struct palmas_resource;
-struct palmas_usb;
-
-struct palmas {
-        struct device *dev;
-
-        struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
-        struct regmap *regmap[PALMAS_NUM_CLIENTS];
-
-        /* Stored chip id */
-        int id;
-
-        /* IRQ Data */
-        int irq;
-        u32 irq_mask;
-        struct mutex irq_lock;
-        struct regmap_irq_chip_data *irq_data;
-
-        /* Child Devices */
-        struct palmas_pmic *pmic;
-        struct palmas_gpadc *gpadc;
-        struct palmas_resource *resource;
-        struct palmas_usb *usb;
-
-        /* GPIO MUXing */
-        u8 gpio_muxed;
-        u8 led_muxed;
-        u8 pwm_muxed;
-};
-
-struct palmas_gpadc_platform_data {
-        /* Channel 3 current source is only enabled during conversion */
-        int ch3_current;
-
-        /* Channel 0 current source can be used for battery detection.
-         * If used for battery detection this will cause a permanent current
-         * consumption depending on current level set here.
-         */
-        int ch0_current;
-
-        /* default BAT_REMOVAL_DAT setting on device probe */
-        int bat_removal;
-
-        /* Sets the START_POLARITY bit in the RT_CTRL register */
-        int start_polarity;
-};
-
-struct palmas_reg_init {
-        /* warm_rest controls the voltage levels after a warm reset
-         *
-         * 0: reload default values from OTP on warm reset
-         * 1: maintain voltage from VSEL on warm reset
-         */
-        int warm_reset;
-
-        /* roof_floor controls whether the regulator uses the i2c style
-         * of DVS or uses the method where a GPIO or other control method is
-         * attached to the NSLEEP/ENABLE1/ENABLE2 pins
-         *
-         * For SMPS
-         *
-         * 0: i2c selection of voltage
-         * 1: pin selection of voltage.
-         *
-         * For LDO unused
-         */
-        int roof_floor;
-
-        /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
-         * the data sheet.
-         *
-         * For SMPS
-         *
-         * 0: Off
-         * 1: AUTO
-         * 2: ECO
-         * 3: Forced PWM
-         *
-         * For LDO
-         *
-         * 0: Off
-         * 1: On
-         */
-        int mode_sleep;
-
-        /* tstep is the timestep loaded to the TSTEP register
-         *
-         * For SMPS
-         *
-         * 0: Jump (no slope control)
-         * 1: 10mV/us
-         * 2: 5mV/us
-         * 3: 2.5mV/us
-         *
-         * For LDO unused
-         */
-        int tstep;
-
-        /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
-         * register. Set this is the default voltage set in OTP needs
-         * to be overridden.
-         */
-        u8 vsel;
-
-};
-
-enum palmas_regulators {
-        /* SMPS regulators */
-        PALMAS_REG_SMPS12,
-        PALMAS_REG_SMPS123,
-        PALMAS_REG_SMPS3,
-        PALMAS_REG_SMPS45,
-        PALMAS_REG_SMPS457,
-        PALMAS_REG_SMPS6,
-        PALMAS_REG_SMPS7,
-        PALMAS_REG_SMPS8,
-        PALMAS_REG_SMPS9,
-        PALMAS_REG_SMPS10,
-        /* LDO regulators */
-        PALMAS_REG_LDO1,
-        PALMAS_REG_LDO2,
-        PALMAS_REG_LDO3,
-        PALMAS_REG_LDO4,
-        PALMAS_REG_LDO5,
-        PALMAS_REG_LDO6,
-        PALMAS_REG_LDO7,
-        PALMAS_REG_LDO8,
-        PALMAS_REG_LDO9,
-        PALMAS_REG_LDOLN,
-        PALMAS_REG_LDOUSB,
-        /* Total number of regulators */
-        PALMAS_NUM_REGS,
-};
-
-struct palmas_pmic_platform_data {
-        /* An array of pointers to regulator init data indexed by regulator
-         * ID
-         */
-        struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
-
-        /* An array of pointers to structures containing sleep mode and DVS
-         * configuration for regulators indexed by ID
-         */
-        struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
-
-        /* use LDO6 for vibrator control */
-        int ldo6_vibrator;
-};
-
-struct palmas_usb_platform_data {
-        /* Set this if platform wishes its own vbus control */
-        int no_control_vbus;
-
-        /* Do we enable the wakeup comparator on probe */
-        int wakeup;
-};
-
-struct palmas_resource_platform_data {
-        int regen1_mode_sleep;
-        int regen2_mode_sleep;
-        int sysen1_mode_sleep;
-        int sysen2_mode_sleep;
-
-        /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
-        u8 nsleep_res;
-        /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
-        u8 nsleep_smps;
-        /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
-        u8 nsleep_ldo1;
-        /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
-        u8 nsleep_ldo2;
-
-        /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
-        u8 enable1_res;
-        /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
-        u8 enable1_smps;
-        /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
-        u8 enable1_ldo1;
-        /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
-        u8 enable1_ldo2;
-
-        /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
-        u8 enable2_res;
-        /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
-        u8 enable2_smps;
-        /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
-        u8 enable2_ldo1;
-        /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
-        u8 enable2_ldo2;
-};
-
-struct palmas_clk_platform_data {
-        int clk32kg_mode_sleep;
-        int clk32kgaudio_mode_sleep;
-};
-
-struct palmas_platform_data {
-        int gpio_base;
-
-        /* bit value to be loaded to the POWER_CTRL register */
-        u8 power_ctrl;
-
-        /*
-         * boolean to select if we want to configure muxing here
-         * then the two value to load into the registers if true
-         */
-        int mux_from_pdata;
-        u8 pad1, pad2;
-
-        struct palmas_pmic_platform_data *pmic_pdata;
-        struct palmas_gpadc_platform_data *gpadc_pdata;
-        struct palmas_usb_platform_data *usb_pdata;
-        struct palmas_resource_platform_data *resource_pdata;
-        struct palmas_clk_platform_data *clk_pdata;
-};
-
-struct palmas_gpadc_calibration {
-        s32 gain;
-        s32 gain_error;
-        s32 offset_error;
-};
-
-struct palmas_gpadc {
-        struct device *dev;
-        struct palmas *palmas;
-
-        int ch3_current;
-        int ch0_current;
-
-        int gpadc_force;
-
-        int bat_removal;
-
-        struct mutex reading_lock;
-        struct completion irq_complete;
-
-        int eoc_sw_irq;
-
-        struct palmas_gpadc_calibration *palmas_cal_tbl;
-
-        int conv0_channel;
-        int conv1_channel;
-        int rt_channel;
-};
-
-struct palmas_gpadc_result {
-        s32 raw_code;
-        s32 corrected_code;
-        s32 result;
-};
-
-#define PALMAS_MAX_CHANNELS 16
-
-/* Define the palmas IRQ numbers */
-enum palmas_irqs {
-        /* INT1 registers */
-        PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
-        PALMAS_PWRON_IRQ,
-        PALMAS_LONG_PRESS_KEY_IRQ,
-        PALMAS_RPWRON_IRQ,
-        PALMAS_PWRDOWN_IRQ,
-        PALMAS_HOTDIE_IRQ,
-        PALMAS_VSYS_MON_IRQ,
-        PALMAS_VBAT_MON_IRQ,
-        /* INT2 registers */
-        PALMAS_RTC_ALARM_IRQ,
-        PALMAS_RTC_TIMER_IRQ,
-        PALMAS_WDT_IRQ,
-        PALMAS_BATREMOVAL_IRQ,
-        PALMAS_RESET_IN_IRQ,
-        PALMAS_FBI_BB_IRQ,
-        PALMAS_SHORT_IRQ,
-        PALMAS_VAC_ACOK_IRQ,
-        /* INT3 registers */
-        PALMAS_GPADC_AUTO_0_IRQ,
-        PALMAS_GPADC_AUTO_1_IRQ,
-        PALMAS_GPADC_EOC_SW_IRQ,
-        PALMAS_GPADC_EOC_RT_IRQ,
-        PALMAS_ID_OTG_IRQ,
-        PALMAS_ID_IRQ,
-        PALMAS_VBUS_OTG_IRQ,
-        PALMAS_VBUS_IRQ,
-        /* INT4 registers */
-        PALMAS_GPIO_0_IRQ,
-        PALMAS_GPIO_1_IRQ,
-        PALMAS_GPIO_2_IRQ,
-        PALMAS_GPIO_3_IRQ,
-        PALMAS_GPIO_4_IRQ,
-        PALMAS_GPIO_5_IRQ,
-        PALMAS_GPIO_6_IRQ,
-        PALMAS_GPIO_7_IRQ,
-        /* Total Number IRQs */
-        PALMAS_NUM_IRQ,
-};
-
-struct palmas_pmic {
-        struct palmas *palmas;
-        struct device *dev;
-        struct regulator_desc desc[PALMAS_NUM_REGS];
-        struct regulator_dev *rdev[PALMAS_NUM_REGS];
-        struct mutex mutex;
-
-        int smps123;
-        int smps457;
-
-        int range[PALMAS_REG_SMPS10];
-};
-
-struct palmas_resource {
-        struct palmas *palmas;
-        struct device *dev;
-};
-
-struct palmas_usb {
-        struct palmas *palmas;
-        struct device *dev;
-
-        /* for vbus reporting with irqs disabled */
-        spinlock_t lock;
-
-        struct regulator *vbus_reg;
-
-        /* used to set vbus, in atomic path */
-        struct work_struct set_vbus_work;
-
-        int irq1;
-        int irq2;
-        int irq3;
-        int irq4;
-
-        int vbus_enable;
-
-        u8 linkstat;
-};
-
-#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
-
-enum usb_irq_events {
-        /* Wakeup events from INT3 */
-        PALMAS_USB_ID_WAKEPUP,
-        PALMAS_USB_VBUS_WAKEUP,
-
-        /* ID_OTG_EVENTS */
-        PALMAS_USB_ID_GND,
-        N_PALMAS_USB_ID_GND,
-        PALMAS_USB_ID_C,
-        N_PALMAS_USB_ID_C,
-        PALMAS_USB_ID_B,
-        N_PALMAS_USB_ID_B,
-        PALMAS_USB_ID_A,
-        N_PALMAS_USB_ID_A,
-        PALMAS_USB_ID_FLOAT,
-        N_PALMAS_USB_ID_FLOAT,
-
-        /* VBUS_OTG_EVENTS */
-        PALMAS_USB_VB_SESS_END,
-        N_PALMAS_USB_VB_SESS_END,
-        PALMAS_USB_VB_SESS_VLD,
-        N_PALMAS_USB_VB_SESS_VLD,
-        PALMAS_USB_VA_SESS_VLD,
-        N_PALMAS_USB_VA_SESS_VLD,
-        PALMAS_USB_VA_VBUS_VLD,
-        N_PALMAS_USB_VA_VBUS_VLD,
-        PALMAS_USB_VADP_SNS,
-        N_PALMAS_USB_VADP_SNS,
-        PALMAS_USB_VADP_PRB,
-        N_PALMAS_USB_VADP_PRB,
-        PALMAS_USB_VOTG_SESS_VLD,
-        N_PALMAS_USB_VOTG_SESS_VLD,
-};
-
-/* defines so we can store the mux settings */
-#define PALMAS_GPIO_0_MUXED                                     (1 << 0)
-#define PALMAS_GPIO_1_MUXED                                     (1 << 1)
-#define PALMAS_GPIO_2_MUXED                                     (1 << 2)
-#define PALMAS_GPIO_3_MUXED                                     (1 << 3)
-#define PALMAS_GPIO_4_MUXED                                     (1 << 4)
-#define PALMAS_GPIO_5_MUXED                                     (1 << 5)
-#define PALMAS_GPIO_6_MUXED                                     (1 << 6)
-#define PALMAS_GPIO_7_MUXED                                     (1 << 7)
-
-#define PALMAS_LED1_MUXED                                       (1 << 0)
-#define PALMAS_LED2_MUXED                                       (1 << 1)
-
-#define PALMAS_PWM1_MUXED                                       (1 << 0)
-#define PALMAS_PWM2_MUXED                                       (1 << 1)
-
-/* helper macro to get correct slave number */
-#define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
-#define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
-
-/* Base addresses of IP blocks in Palmas */
-#define PALMAS_SMPS_DVS_BASE                                    0x20
-#define PALMAS_RTC_BASE                                         0x100
-#define PALMAS_VALIDITY_BASE                                    0x118
-#define PALMAS_SMPS_BASE                                        0x120
-#define PALMAS_LDO_BASE                                         0x150
-#define PALMAS_DVFS_BASE                                        0x180
-#define PALMAS_PMU_CONTROL_BASE                                 0x1A0
-#define PALMAS_RESOURCE_BASE                                    0x1D4
-#define PALMAS_PU_PD_OD_BASE                                    0x1F4
-#define PALMAS_LED_BASE                                         0x200
-#define PALMAS_INTERRUPT_BASE                                   0x210
-#define PALMAS_USB_OTG_BASE                                     0x250
-#define PALMAS_VIBRATOR_BASE                                    0x270
-#define PALMAS_GPIO_BASE                                        0x280
-#define PALMAS_USB_BASE                                         0x290
-#define PALMAS_GPADC_BASE                                       0x2C0
-#define PALMAS_TRIM_GPADC_BASE                                  0x3CD
-
-/* Registers for function RTC */
-#define PALMAS_SECONDS_REG                                      0x0
-#define PALMAS_MINUTES_REG                                      0x1
-#define PALMAS_HOURS_REG                                        0x2
-#define PALMAS_DAYS_REG                                         0x3
-#define PALMAS_MONTHS_REG                                       0x4
-#define PALMAS_YEARS_REG                                        0x5
-#define PALMAS_WEEKS_REG                                        0x6
-#define PALMAS_ALARM_SECONDS_REG                                0x8
-#define PALMAS_ALARM_MINUTES_REG                                0x9
-#define PALMAS_ALARM_HOURS_REG                                  0xA
-#define PALMAS_ALARM_DAYS_REG                                   0xB
-#define PALMAS_ALARM_MONTHS_REG                                 0xC
-#define PALMAS_ALARM_YEARS_REG                                  0xD
-#define PALMAS_RTC_CTRL_REG                                     0x10
-#define PALMAS_RTC_STATUS_REG                                   0x11
-#define PALMAS_RTC_INTERRUPTS_REG                               0x12
-#define PALMAS_RTC_COMP_LSB_REG                                 0x13
-#define PALMAS_RTC_COMP_MSB_REG                                 0x14
-#define PALMAS_RTC_RES_PROG_REG                                 0x15
-#define PALMAS_RTC_RESET_STATUS_REG                             0x16
-
-/* Bit definitions for SECONDS_REG */
-#define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
-#define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
-#define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
-#define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
-
-/* Bit definitions for MINUTES_REG */
-#define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
-#define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
-#define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
-#define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
-
-/* Bit definitions for HOURS_REG */
-#define PALMAS_HOURS_REG_PM_NAM                                 0x80
-#define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
-#define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
-#define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
-#define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
-#define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
-
-/* Bit definitions for DAYS_REG */
-#define PALMAS_DAYS_REG_DAY1_MASK                               0x30
-#define PALMAS_DAYS_REG_DAY1_SHIFT                              4
-#define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
-#define PALMAS_DAYS_REG_DAY0_SHIFT                              0
-
-/* Bit definitions for MONTHS_REG */
-#define PALMAS_MONTHS_REG_MONTH1                                0x10
-#define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
-#define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
-#define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
-
-/* Bit definitions for YEARS_REG */
-#define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
-#define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
-#define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
-#define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
-
-/* Bit definitions for WEEKS_REG */
-#define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
-#define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
-
-/* Bit definitions for ALARM_SECONDS_REG */
-#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
-#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
-#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
-#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
-
-/* Bit definitions for ALARM_MINUTES_REG */
-#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
-#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
-#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
-#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
-
-/* Bit definitions for ALARM_HOURS_REG */
-#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
-#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
-#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
-#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
-#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
-#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
-
-/* Bit definitions for ALARM_DAYS_REG */
-#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
-#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
-#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
-#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
-
-/* Bit definitions for ALARM_MONTHS_REG */
-#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
-#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
-#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
-#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
-
-/* Bit definitions for ALARM_YEARS_REG */
-#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
-#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
-#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
-#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
-
-/* Bit definitions for RTC_CTRL_REG */
-#define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
-#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
-#define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
-#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
-#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
-#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
-#define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
-#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
-#define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
-#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
-#define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
-#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
-#define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
-#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
-#define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
-#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
-
-/* Bit definitions for RTC_STATUS_REG */
-#define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
-#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
-#define PALMAS_RTC_STATUS_REG_ALARM                             0x40
-#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
-#define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
-#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
-#define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
-#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
-#define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
-#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
-#define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
-#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
-#define PALMAS_RTC_STATUS_REG_RUN                               0x02
-#define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
-
-/* Bit definitions for RTC_INTERRUPTS_REG */
-#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
-#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
-#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
-#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
-#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
-#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
-#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
-#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
-
-/* Bit definitions for RTC_COMP_LSB_REG */
-#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
-#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
-
-/* Bit definitions for RTC_COMP_MSB_REG */
-#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
-#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
-
-/* Bit definitions for RTC_RES_PROG_REG */
-#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
-#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
-
-/* Bit definitions for RTC_RESET_STATUS_REG */
-#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
-#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
-
-/* Registers for function BACKUP */
-#define PALMAS_BACKUP0                                          0x0
-#define PALMAS_BACKUP1                                          0x1
-#define PALMAS_BACKUP2                                          0x2
-#define PALMAS_BACKUP3                                          0x3
-#define PALMAS_BACKUP4                                          0x4
-#define PALMAS_BACKUP5                                          0x5
-#define PALMAS_BACKUP6                                          0x6
-#define PALMAS_BACKUP7                                          0x7
-
-/* Bit definitions for BACKUP0 */
-#define PALMAS_BACKUP0_BACKUP_MASK                              0xff
-#define PALMAS_BACKUP0_BACKUP_SHIFT                             0
-
-/* Bit definitions for BACKUP1 */
-#define PALMAS_BACKUP1_BACKUP_MASK                              0xff
-#define PALMAS_BACKUP1_BACKUP_SHIFT                             0
-
-/* Bit definitions for BACKUP2 */
-#define PALMAS_BACKUP2_BACKUP_MASK                              0xff
-#define PALMAS_BACKUP2_BACKUP_SHIFT                             0
-
-/* Bit definitions for BACKUP3 */
-#define PALMAS_BACKUP3_BACKUP_MASK                              0xff
-#define PALMAS_BACKUP3_BACKUP_SHIFT                             0
-
-/* Bit definitions for BACKUP4 */
-#define PALMAS_BACKUP4_BACKUP_MASK                              0xff
-#define PALMAS_BACKUP4_BACKUP_SHIFT                             0
-
-/* Bit definitions for BACKUP5 */
-#define PALMAS_BACKUP5_BACKUP_MASK                              0xff
-#define PALMAS_BACKUP5_BACKUP_SHIFT                             0
-
-/* Bit definitions for BACKUP6 */
-#define PALMAS_BACKUP6_BACKUP_MASK                              0xff
-#define PALMAS_BACKUP6_BACKUP_SHIFT                             0
-
-/* Bit definitions for BACKUP7 */
-#define PALMAS_BACKUP7_BACKUP_MASK                              0xff
-#define PALMAS_BACKUP7_BACKUP_SHIFT                             0
-
-/* Registers for function SMPS */
-#define PALMAS_SMPS12_CTRL                                      0x0
-#define PALMAS_SMPS12_TSTEP                                     0x1
-#define PALMAS_SMPS12_FORCE                                     0x2
-#define PALMAS_SMPS12_VOLTAGE                                   0x3
-#define PALMAS_SMPS3_CTRL                                       0x4
-#define PALMAS_SMPS3_VOLTAGE                                    0x7
-#define PALMAS_SMPS45_CTRL                                      0x8
-#define PALMAS_SMPS45_TSTEP                                     0x9
-#define PALMAS_SMPS45_FORCE                                     0xA
-#define PALMAS_SMPS45_VOLTAGE                                   0xB
-#define PALMAS_SMPS6_CTRL                                       0xC
-#define PALMAS_SMPS6_TSTEP                                      0xD
-#define PALMAS_SMPS6_FORCE                                      0xE
-#define PALMAS_SMPS6_VOLTAGE                                    0xF
-#define PALMAS_SMPS7_CTRL                                       0x10
-#define PALMAS_SMPS7_VOLTAGE                                    0x13
-#define PALMAS_SMPS8_CTRL                                       0x14
-#define PALMAS_SMPS8_TSTEP                                      0x15
-#define PALMAS_SMPS8_FORCE                                      0x16
-#define PALMAS_SMPS8_VOLTAGE                                    0x17
-#define PALMAS_SMPS9_CTRL                                       0x18
-#define PALMAS_SMPS9_VOLTAGE                                    0x1B
-#define PALMAS_SMPS10_CTRL                                      0x1C
-#define PALMAS_SMPS10_STATUS                                    0x1F
-#define PALMAS_SMPS_CTRL                                        0x24
-#define PALMAS_SMPS_PD_CTRL                                     0x25
-#define PALMAS_SMPS_DITHER_EN                                   0x26
-#define PALMAS_SMPS_THERMAL_EN                                  0x27
-#define PALMAS_SMPS_THERMAL_STATUS                              0x28
-#define PALMAS_SMPS_SHORT_STATUS                                0x29
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
-#define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
-#define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
-
-/* Bit definitions for SMPS12_CTRL */
-#define PALMAS_SMPS12_CTRL_WR_S                                 0x80
-#define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
-#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
-#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
-#define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
-#define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
-#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
-#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
-#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
-#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
-
-/* Bit definitions for SMPS12_TSTEP */
-#define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
-#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
-
-/* Bit definitions for SMPS12_FORCE */
-#define PALMAS_SMPS12_FORCE_CMD                                 0x80
-#define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
-#define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
-#define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
-
-/* Bit definitions for SMPS12_VOLTAGE */
-#define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
-#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
-#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
-#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
-
-/* Bit definitions for SMPS3_CTRL */
-#define PALMAS_SMPS3_CTRL_WR_S                                  0x80
-#define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
-#define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
-#define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
-#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
-#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
-#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
-#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
-
-/* Bit definitions for SMPS3_VOLTAGE */
-#define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
-#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
-#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
-#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
-
-/* Bit definitions for SMPS45_CTRL */
-#define PALMAS_SMPS45_CTRL_WR_S                                 0x80
-#define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
-#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
-#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
-#define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
-#define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
-#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
-#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
-#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
-#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
-
-/* Bit definitions for SMPS45_TSTEP */
-#define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
-#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
-
-/* Bit definitions for SMPS45_FORCE */
-#define PALMAS_SMPS45_FORCE_CMD                                 0x80
-#define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
-#define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
-#define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
-
-/* Bit definitions for SMPS45_VOLTAGE */
-#define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
-#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
-#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
-#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
-
-/* Bit definitions for SMPS6_CTRL */
-#define PALMAS_SMPS6_CTRL_WR_S                                  0x80
-#define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
-#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
-#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
-#define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
-#define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
-#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
-#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
-#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
-#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
-
-/* Bit definitions for SMPS6_TSTEP */
-#define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
-#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
-
-/* Bit definitions for SMPS6_FORCE */
-#define PALMAS_SMPS6_FORCE_CMD                                  0x80
-#define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
-#define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
-#define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
-
-/* Bit definitions for SMPS6_VOLTAGE */
-#define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
-#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
-#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
-#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
-
-/* Bit definitions for SMPS7_CTRL */
-#define PALMAS_SMPS7_CTRL_WR_S                                  0x80
-#define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
-#define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
-#define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
-#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
-#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
-#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
-#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
-
-/* Bit definitions for SMPS7_VOLTAGE */
-#define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
-#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
-#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
-#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
-
-/* Bit definitions for SMPS8_CTRL */
-#define PALMAS_SMPS8_CTRL_WR_S                                  0x80
-#define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
-#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
-#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
-#define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
-#define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
-#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
-#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
-#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
-#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
-
-/* Bit definitions for SMPS8_TSTEP */
-#define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
-#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
-
-/* Bit definitions for SMPS8_FORCE */
-#define PALMAS_SMPS8_FORCE_CMD                                  0x80
-#define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
-#define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
-#define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
-
-/* Bit definitions for SMPS8_VOLTAGE */
-#define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
-#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
-#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
-#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
-
-/* Bit definitions for SMPS9_CTRL */
-#define PALMAS_SMPS9_CTRL_WR_S                                  0x80
-#define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
-#define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
-#define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
-#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
-#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
-#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
-#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
-
-/* Bit definitions for SMPS9_VOLTAGE */
-#define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
-#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
-#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
-#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
-
-/* Bit definitions for SMPS10_CTRL */
-#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
-#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
-#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
-#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
-
-/* Bit definitions for SMPS10_STATUS */
-#define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
-#define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
-
-/* Bit definitions for SMPS_CTRL */
-#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
-#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
-#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
-#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
-#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
-#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
-#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
-#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
-
-/* Bit definitions for SMPS_PD_CTRL */
-#define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
-#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
-#define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
-#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
-#define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
-#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
-#define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
-#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
-#define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
-#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
-#define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
-#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
-#define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
-#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
-
-/* Bit definitions for SMPS_THERMAL_EN */
-#define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
-#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
-#define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
-#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
-#define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
-#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
-#define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
-#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
-#define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
-#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
-
-/* Bit definitions for SMPS_THERMAL_STATUS */
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
-#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
-
-/* Bit definitions for SMPS_SHORT_STATUS */
-#define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
-#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
-#define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
-#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
-#define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
-#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
-#define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
-#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
-#define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
-#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
-#define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
-#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
-#define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
-#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
-#define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
-#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
-
-/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
-#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
-
-/* Bit definitions for SMPS_POWERGOOD_MASK1 */
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
-#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
-
-/* Bit definitions for SMPS_POWERGOOD_MASK2 */
-#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
-#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
-#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
-#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
-#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
-#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
-#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
-#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
-
-/* Registers for function LDO */
-#define PALMAS_LDO1_CTRL                                        0x0
-#define PALMAS_LDO1_VOLTAGE                                     0x1
-#define PALMAS_LDO2_CTRL                                        0x2
-#define PALMAS_LDO2_VOLTAGE                                     0x3
-#define PALMAS_LDO3_CTRL                                        0x4
-#define PALMAS_LDO3_VOLTAGE                                     0x5
-#define PALMAS_LDO4_CTRL                                        0x6
-#define PALMAS_LDO4_VOLTAGE                                     0x7
-#define PALMAS_LDO5_CTRL                                        0x8
-#define PALMAS_LDO5_VOLTAGE                                     0x9
-#define PALMAS_LDO6_CTRL                                        0xA
-#define PALMAS_LDO6_VOLTAGE                                     0xB
-#define PALMAS_LDO7_CTRL                                        0xC
-#define PALMAS_LDO7_VOLTAGE                                     0xD
-#define PALMAS_LDO8_CTRL                                        0xE
-#define PALMAS_LDO8_VOLTAGE                                     0xF
-#define PALMAS_LDO9_CTRL                                        0x10
-#define PALMAS_LDO9_VOLTAGE                                     0x11
-#define PALMAS_LDOLN_CTRL                                       0x12
-#define PALMAS_LDOLN_VOLTAGE                                    0x13
-#define PALMAS_LDOUSB_CTRL                                      0x14
-#define PALMAS_LDOUSB_VOLTAGE                                   0x15
-#define PALMAS_LDO_CTRL                                         0x1A
-#define PALMAS_LDO_PD_CTRL1                                     0x1B
-#define PALMAS_LDO_PD_CTRL2                                     0x1C
-#define PALMAS_LDO_SHORT_STATUS1                                0x1D
-#define PALMAS_LDO_SHORT_STATUS2                                0x1E
-
-/* Bit definitions for LDO1_CTRL */
-#define PALMAS_LDO1_CTRL_WR_S                                   0x80
-#define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
-#define PALMAS_LDO1_CTRL_STATUS                                 0x10
-#define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
-#define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
-#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
-#define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
-#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
-
-/* Bit definitions for LDO1_VOLTAGE */
-#define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
-#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
-
-/* Bit definitions for LDO2_CTRL */
-#define PALMAS_LDO2_CTRL_WR_S                                   0x80
-#define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
-#define PALMAS_LDO2_CTRL_STATUS                                 0x10
-#define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
-#define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
-#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
-#define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
-#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
-
-/* Bit definitions for LDO2_VOLTAGE */
-#define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
-#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
-
-/* Bit definitions for LDO3_CTRL */
-#define PALMAS_LDO3_CTRL_WR_S                                   0x80
-#define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
-#define PALMAS_LDO3_CTRL_STATUS                                 0x10
-#define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
-#define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
-#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
-#define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
-#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
-
-/* Bit definitions for LDO3_VOLTAGE */
-#define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
-#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
-
-/* Bit definitions for LDO4_CTRL */
-#define PALMAS_LDO4_CTRL_WR_S                                   0x80
-#define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
-#define PALMAS_LDO4_CTRL_STATUS                                 0x10
-#define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
-#define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
-#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
-#define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
-#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
-
-/* Bit definitions for LDO4_VOLTAGE */
-#define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
-#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
-
-/* Bit definitions for LDO5_CTRL */
-#define PALMAS_LDO5_CTRL_WR_S                                   0x80
-#define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
-#define PALMAS_LDO5_CTRL_STATUS                                 0x10
-#define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
-#define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
-#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
-#define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
-#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
-
-/* Bit definitions for LDO5_VOLTAGE */
-#define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
-#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
-
-/* Bit definitions for LDO6_CTRL */
-#define PALMAS_LDO6_CTRL_WR_S                                   0x80
-#define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
-#define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
-#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
-#define PALMAS_LDO6_CTRL_STATUS                                 0x10
-#define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
-#define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
-#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
-#define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
-#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
-
-/* Bit definitions for LDO6_VOLTAGE */
-#define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
-#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
-
-/* Bit definitions for LDO7_CTRL */
-#define PALMAS_LDO7_CTRL_WR_S                                   0x80
-#define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
-#define PALMAS_LDO7_CTRL_STATUS                                 0x10
-#define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
-#define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
-#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
-#define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
-#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
-
-/* Bit definitions for LDO7_VOLTAGE */
-#define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
-#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
-
-/* Bit definitions for LDO8_CTRL */
-#define PALMAS_LDO8_CTRL_WR_S                                   0x80
-#define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
-#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
-#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
-#define PALMAS_LDO8_CTRL_STATUS                                 0x10
-#define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
-#define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
-#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
-#define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
-#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
-
-/* Bit definitions for LDO8_VOLTAGE */
-#define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
-#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
-
-/* Bit definitions for LDO9_CTRL */
-#define PALMAS_LDO9_CTRL_WR_S                                   0x80
-#define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
-#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
-#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
-#define PALMAS_LDO9_CTRL_STATUS                                 0x10
-#define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
-#define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
-#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
-#define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
-#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
-
-/* Bit definitions for LDO9_VOLTAGE */
-#define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
-#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
-
-/* Bit definitions for LDOLN_CTRL */
-#define PALMAS_LDOLN_CTRL_WR_S                                  0x80
-#define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
-#define PALMAS_LDOLN_CTRL_STATUS                                0x10
-#define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
-#define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
-#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
-#define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
-#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
-
-/* Bit definitions for LDOLN_VOLTAGE */
-#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
-#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
-
-/* Bit definitions for LDOUSB_CTRL */
-#define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
-#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
-#define PALMAS_LDOUSB_CTRL_STATUS                               0x10
-#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
-#define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
-#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
-#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
-#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
-
-/* Bit definitions for LDOUSB_VOLTAGE */
-#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
-#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
-
-/* Bit definitions for LDO_CTRL */
-#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
-#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
-
-/* Bit definitions for LDO_PD_CTRL1 */
-#define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
-#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
-#define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
-#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
-#define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
-#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
-#define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
-#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
-#define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
-#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
-#define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
-#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
-#define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
-#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
-#define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
-#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
-
-/* Bit definitions for LDO_PD_CTRL2 */
-#define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
-#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
-#define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
-#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
-#define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
-#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
-
-/* Bit definitions for LDO_SHORT_STATUS1 */
-#define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
-#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
-#define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
-#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
-#define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
-#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
-#define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
-#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
-#define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
-#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
-#define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
-#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
-#define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
-#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
-#define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
-#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
-
-/* Bit definitions for LDO_SHORT_STATUS2 */
-#define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
-#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
-#define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
-#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
-#define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
-#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
-#define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
-#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
-
-/* Registers for function PMU_CONTROL */
-#define PALMAS_DEV_CTRL                                         0x0
-#define PALMAS_POWER_CTRL                                       0x1
-#define PALMAS_VSYS_LO                                          0x2
-#define PALMAS_VSYS_MON                                         0x3
-#define PALMAS_VBAT_MON                                         0x4
-#define PALMAS_WATCHDOG                                         0x5
-#define PALMAS_BOOT_STATUS                                      0x6
-#define PALMAS_BATTERY_BOUNCE                                   0x7
-#define PALMAS_BACKUP_BATTERY_CTRL                              0x8
-#define PALMAS_LONG_PRESS_KEY                                   0x9
-#define PALMAS_OSC_THERM_CTRL                                   0xA
-#define PALMAS_BATDEBOUNCING                                    0xB
-#define PALMAS_SWOFF_HWRST                                      0xF
-#define PALMAS_SWOFF_COLDRST                                    0x10
-#define PALMAS_SWOFF_STATUS                                     0x11
-#define PALMAS_PMU_CONFIG                                       0x12
-#define PALMAS_SPARE                                            0x14
-#define PALMAS_PMU_SECONDARY_INT                                0x15
-#define PALMAS_SW_REVISION                                      0x17
-#define PALMAS_EXT_CHRG_CTRL                                    0x18
-#define PALMAS_PMU_SECONDARY_INT2                               0x19
-
-/* Bit definitions for DEV_CTRL */
-#define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
-#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
-#define PALMAS_DEV_CTRL_SW_RST                                  0x02
-#define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
-#define PALMAS_DEV_CTRL_DEV_ON                                  0x01
-#define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
-
-/* Bit definitions for POWER_CTRL */
-#define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
-#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
-#define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
-#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
-#define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
-#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
-
-/* Bit definitions for VSYS_LO */
-#define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
-#define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
-
-/* Bit definitions for VSYS_MON */
-#define PALMAS_VSYS_MON_ENABLE                                  0x80
-#define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
-#define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
-#define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
-
-/* Bit definitions for VBAT_MON */
-#define PALMAS_VBAT_MON_ENABLE                                  0x80
-#define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
-#define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
-#define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
-
-/* Bit definitions for WATCHDOG */
-#define PALMAS_WATCHDOG_LOCK                                    0x20
-#define PALMAS_WATCHDOG_LOCK_SHIFT                              5
-#define PALMAS_WATCHDOG_ENABLE                                  0x10
-#define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
-#define PALMAS_WATCHDOG_MODE                                    0x08
-#define PALMAS_WATCHDOG_MODE_SHIFT                              3
-#define PALMAS_WATCHDOG_TIMER_MASK                              0x07
-#define PALMAS_WATCHDOG_TIMER_SHIFT                             0
-
-/* Bit definitions for BOOT_STATUS */
-#define PALMAS_BOOT_STATUS_BOOT1                                0x02
-#define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
-#define PALMAS_BOOT_STATUS_BOOT0                                0x01
-#define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
-
-/* Bit definitions for BATTERY_BOUNCE */
-#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
-#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
-
-/* Bit definitions for BACKUP_BATTERY_CTRL */
-#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
-#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
-#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
-#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
-#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
-#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
-#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
-#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
-#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
-#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
-#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
-#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
-#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
-#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
-
-/* Bit definitions for LONG_PRESS_KEY */
-#define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
-#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
-#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
-#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
-#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
-#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
-#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
-#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
-
-/* Bit definitions for OSC_THERM_CTRL */
-#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
-#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
-#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
-#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
-#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
-#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
-#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
-#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
-#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
-#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
-#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
-#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
-#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
-#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
-
-/* Bit definitions for BATDEBOUNCING */
-#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
-#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
-#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
-#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
-#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
-#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
-
-/* Bit definitions for SWOFF_HWRST */
-#define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
-#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
-#define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
-#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
-#define PALMAS_SWOFF_HWRST_WTD                                  0x20
-#define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
-#define PALMAS_SWOFF_HWRST_TSHUT                                0x10
-#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
-#define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
-#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
-#define PALMAS_SWOFF_HWRST_SW_RST                               0x04
-#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
-#define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
-#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
-#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
-#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
-
-/* Bit definitions for SWOFF_COLDRST */
-#define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
-#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
-#define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
-#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
-#define PALMAS_SWOFF_COLDRST_WTD                                0x20
-#define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
-#define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
-#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
-#define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
-#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
-#define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
-#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
-#define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
-#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
-#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
-#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
-
-/* Bit definitions for SWOFF_STATUS */
-#define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
-#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
-#define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
-#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
-#define PALMAS_SWOFF_STATUS_WTD                                 0x20
-#define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
-#define PALMAS_SWOFF_STATUS_TSHUT                               0x10
-#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
-#define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
-#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
-#define PALMAS_SWOFF_STATUS_SW_RST                              0x04
-#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
-#define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
-#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
-#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
-#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
-
-/* Bit definitions for PMU_CONFIG */
-#define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
-#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
-#define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
-#define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
-#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
-#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
-#define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
-#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
-#define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
-#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
-
-/* Bit definitions for SPARE */
-#define PALMAS_SPARE_SPARE_MASK                                 0xf8
-#define PALMAS_SPARE_SPARE_SHIFT                                3
-#define PALMAS_SPARE_REGEN3_OD                                  0x04
-#define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
-#define PALMAS_SPARE_REGEN2_OD                                  0x02
-#define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
-#define PALMAS_SPARE_REGEN1_OD                                  0x01
-#define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
-
-/* Bit definitions for PMU_SECONDARY_INT */
-#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
-#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
-#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
-#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
-#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
-#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
-#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
-#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
-#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
-#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
-#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
-#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
-#define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
-#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
-#define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
-#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
-
-/* Bit definitions for SW_REVISION */
-#define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
-#define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
-
-/* Bit definitions for EXT_CHRG_CTRL */
-#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
-#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
-#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
-#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
-#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
-#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
-#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
-#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
-#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
-#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
-#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
-#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
-
-/* Bit definitions for PMU_SECONDARY_INT2 */
-#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
-#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
-#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
-#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
-#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
-#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
-#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
-#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
-
-/* Registers for function RESOURCE */
-#define PALMAS_CLK32KG_CTRL                                     0x0
-#define PALMAS_CLK32KGAUDIO_CTRL                                0x1
-#define PALMAS_REGEN1_CTRL                                      0x2
-#define PALMAS_REGEN2_CTRL                                      0x3
-#define PALMAS_SYSEN1_CTRL                                      0x4
-#define PALMAS_SYSEN2_CTRL                                      0x5
-#define PALMAS_NSLEEP_RES_ASSIGN                                0x6
-#define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
-#define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
-#define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
-#define PALMAS_ENABLE1_RES_ASSIGN                               0xA
-#define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
-#define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
-#define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
-#define PALMAS_ENABLE2_RES_ASSIGN                               0xE
-#define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
-#define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
-#define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
-#define PALMAS_REGEN3_CTRL                                      0x12
-
-/* Bit definitions for CLK32KG_CTRL */
-#define PALMAS_CLK32KG_CTRL_STATUS                              0x10
-#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
-#define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
-#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
-#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
-#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
-
-/* Bit definitions for CLK32KGAUDIO_CTRL */
-#define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
-#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
-#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
-#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
-#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
-#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
-#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
-#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
-
-/* Bit definitions for REGEN1_CTRL */
-#define PALMAS_REGEN1_CTRL_STATUS                               0x10
-#define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
-#define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
-#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
-#define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
-#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
-
-/* Bit definitions for REGEN2_CTRL */
-#define PALMAS_REGEN2_CTRL_STATUS                               0x10
-#define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
-#define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
-#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
-#define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
-#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
-
-/* Bit definitions for SYSEN1_CTRL */
-#define PALMAS_SYSEN1_CTRL_STATUS                               0x10
-#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
-#define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
-#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
-#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
-#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
-
-/* Bit definitions for SYSEN2_CTRL */
-#define PALMAS_SYSEN2_CTRL_STATUS                               0x10
-#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
-#define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
-#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
-#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
-#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
-
-/* Bit definitions for NSLEEP_RES_ASSIGN */
-#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
-#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
-#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
-#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
-#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
-#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
-#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
-#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
-#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
-#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
-#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
-#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
-#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
-#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
-
-/* Bit definitions for NSLEEP_SMPS_ASSIGN */
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
-#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
-
-/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
-#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
-
-/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
-#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
-#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
-#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
-#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
-#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
-#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
-
-/* Bit definitions for ENABLE1_RES_ASSIGN */
-#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
-#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
-#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
-#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
-#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
-#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
-#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
-#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
-#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
-#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
-#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
-#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
-#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
-#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
-
-/* Bit definitions for ENABLE1_SMPS_ASSIGN */
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
-#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
-
-/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
-#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
-
-/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
-#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
-#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
-#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
-#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
-#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
-#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
-
-/* Bit definitions for ENABLE2_RES_ASSIGN */
-#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
-#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
-#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
-#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
-#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
-#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
-#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
-#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
-#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
-#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
-#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
-#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
-#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
-#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
-
-/* Bit definitions for ENABLE2_SMPS_ASSIGN */
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
-#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
-
-/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
-#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
-
-/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
-#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
-#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
-#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
-#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
-#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
-#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
-
-/* Bit definitions for REGEN3_CTRL */
-#define PALMAS_REGEN3_CTRL_STATUS                               0x10
-#define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
-#define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
-#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
-#define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
-#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
-
-/* Registers for function PAD_CONTROL */
-#define PALMAS_PU_PD_INPUT_CTRL1                                0x0
-#define PALMAS_PU_PD_INPUT_CTRL2                                0x1
-#define PALMAS_PU_PD_INPUT_CTRL3                                0x2
-#define PALMAS_OD_OUTPUT_CTRL                                   0x4
-#define PALMAS_POLARITY_CTRL                                    0x5
-#define PALMAS_PRIMARY_SECONDARY_PAD1                           0x6
-#define PALMAS_PRIMARY_SECONDARY_PAD2                           0x7
-#define PALMAS_I2C_SPI                                          0x8
-#define PALMAS_PU_PD_INPUT_CTRL4                                0x9
-#define PALMAS_PRIMARY_SECONDARY_PAD3                           0xA
-
-/* Bit definitions for PU_PD_INPUT_CTRL1 */
-#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
-#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
-#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
-#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
-#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
-#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
-#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
-#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
-#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
-#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
-
-/* Bit definitions for PU_PD_INPUT_CTRL2 */
-#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
-#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
-#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
-#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
-#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
-#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
-#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
-#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
-#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
-#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
-#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
-#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
-
-/* Bit definitions for PU_PD_INPUT_CTRL3 */
-#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
-#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
-#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
-#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
-#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
-#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
-#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
-#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
-
-/* Bit definitions for OD_OUTPUT_CTRL */
-#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
-#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
-#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
-#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
-#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
-#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
-#define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
-#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
-
-/* Bit definitions for POLARITY_CTRL */
-#define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
-#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
-#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
-#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
-#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
-#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
-#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
-#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
-#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
-#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
-#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
-#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
-#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
-#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
-#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
-#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
-
-/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
-#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
-#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
-#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
-#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
-#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
-#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
-#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
-#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
-#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
-#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
-#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
-#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
-
-/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
-#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
-#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
-#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
-#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
-#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
-#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
-#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
-#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
-
-/* Bit definitions for I2C_SPI */
-#define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
-#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
-#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
-#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
-#define PALMAS_I2C_SPI_ID_I2C2                                  0x20
-#define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
-#define PALMAS_I2C_SPI_I2C_SPI                                  0x10
-#define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
-#define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
-#define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
-
-/* Bit definitions for PU_PD_INPUT_CTRL4 */
-#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
-#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
-#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
-#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
-#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
-#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
-#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
-#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
-
-/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
-#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
-#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
-#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
-#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
-
-/* Registers for function LED_PWM */
-#define PALMAS_LED_PERIOD_CTRL                                  0x0
-#define PALMAS_LED_CTRL                                         0x1
-#define PALMAS_PWM_CTRL1                                        0x2
-#define PALMAS_PWM_CTRL2                                        0x3
-
-/* Bit definitions for LED_PERIOD_CTRL */
-#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
-#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
-#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
-#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
-
-/* Bit definitions for LED_CTRL */
-#define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
-#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
-#define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
-#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
-#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
-#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
-#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
-#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
-
-/* Bit definitions for PWM_CTRL1 */
-#define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
-#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
-#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
-#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
-
-/* Bit definitions for PWM_CTRL2 */
-#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
-#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
-
-/* Registers for function INTERRUPT */
-#define PALMAS_INT1_STATUS                                      0x0
-#define PALMAS_INT1_MASK                                        0x1
-#define PALMAS_INT1_LINE_STATE                                  0x2
-#define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
-#define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
-#define PALMAS_INT2_STATUS                                      0x5
-#define PALMAS_INT2_MASK                                        0x6
-#define PALMAS_INT2_LINE_STATE                                  0x7
-#define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
-#define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
-#define PALMAS_INT3_STATUS                                      0xA
-#define PALMAS_INT3_MASK                                        0xB
-#define PALMAS_INT3_LINE_STATE                                  0xC
-#define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
-#define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
-#define PALMAS_INT4_STATUS                                      0xF
-#define PALMAS_INT4_MASK                                        0x10
-#define PALMAS_INT4_LINE_STATE                                  0x11
-#define PALMAS_INT4_EDGE_DETECT1                                0x12
-#define PALMAS_INT4_EDGE_DETECT2                                0x13
-#define PALMAS_INT_CTRL                                         0x14
-
-/* Bit definitions for INT1_STATUS */
-#define PALMAS_INT1_STATUS_VBAT_MON                             0x80
-#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
-#define PALMAS_INT1_STATUS_VSYS_MON                             0x40
-#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
-#define PALMAS_INT1_STATUS_HOTDIE                               0x20
-#define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
-#define PALMAS_INT1_STATUS_PWRDOWN                              0x10
-#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
-#define PALMAS_INT1_STATUS_RPWRON                               0x08
-#define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
-#define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
-#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
-#define PALMAS_INT1_STATUS_PWRON                                0x02
-#define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
-#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
-#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
-
-/* Bit definitions for INT1_MASK */
-#define PALMAS_INT1_MASK_VBAT_MON                               0x80
-#define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
-#define PALMAS_INT1_MASK_VSYS_MON                               0x40
-#define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
-#define PALMAS_INT1_MASK_HOTDIE                                 0x20
-#define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
-#define PALMAS_INT1_MASK_PWRDOWN                                0x10
-#define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
-#define PALMAS_INT1_MASK_RPWRON                                 0x08
-#define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
-#define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
-#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
-#define PALMAS_INT1_MASK_PWRON                                  0x02
-#define PALMAS_INT1_MASK_PWRON_SHIFT                            1
-#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
-#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
-
-/* Bit definitions for INT1_LINE_STATE */
-#define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
-#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
-#define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
-#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
-#define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
-#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
-#define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
-#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
-#define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
-#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
-#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
-#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
-#define PALMAS_INT1_LINE_STATE_PWRON                            0x02
-#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
-#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
-#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
-
-/* Bit definitions for INT2_STATUS */
-#define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
-#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
-#define PALMAS_INT2_STATUS_SHORT                                0x40
-#define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
-#define PALMAS_INT2_STATUS_FBI_BB                               0x20
-#define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
-#define PALMAS_INT2_STATUS_RESET_IN                             0x10
-#define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
-#define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
-#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
-#define PALMAS_INT2_STATUS_WDT                                  0x04
-#define PALMAS_INT2_STATUS_WDT_SHIFT                            2
-#define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
-#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
-#define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
-#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
-
-/* Bit definitions for INT2_MASK */
-#define PALMAS_INT2_MASK_VAC_ACOK                               0x80
-#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
-#define PALMAS_INT2_MASK_SHORT                                  0x40
-#define PALMAS_INT2_MASK_SHORT_SHIFT                            6
-#define PALMAS_INT2_MASK_FBI_BB                                 0x20
-#define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
-#define PALMAS_INT2_MASK_RESET_IN                               0x10
-#define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
-#define PALMAS_INT2_MASK_BATREMOVAL                             0x08
-#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
-#define PALMAS_INT2_MASK_WDT                                    0x04
-#define PALMAS_INT2_MASK_WDT_SHIFT                              2
-#define PALMAS_INT2_MASK_RTC_TIMER                              0x02
-#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
-#define PALMAS_INT2_MASK_RTC_ALARM                              0x01
-#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
-
-/* Bit definitions for INT2_LINE_STATE */
-#define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
-#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
-#define PALMAS_INT2_LINE_STATE_SHORT                            0x40
-#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
-#define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
-#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
-#define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
-#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
-#define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
-#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
-#define PALMAS_INT2_LINE_STATE_WDT                              0x04
-#define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
-#define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
-#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
-#define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
-#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
-
-/* Bit definitions for INT3_STATUS */
-#define PALMAS_INT3_STATUS_VBUS                                 0x80
-#define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
-#define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
-#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
-#define PALMAS_INT3_STATUS_ID                                   0x20
-#define PALMAS_INT3_STATUS_ID_SHIFT                             5
-#define PALMAS_INT3_STATUS_ID_OTG                               0x10
-#define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
-#define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
-#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
-#define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
-#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
-#define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
-#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
-#define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
-#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
-
-/* Bit definitions for INT3_MASK */
-#define PALMAS_INT3_MASK_VBUS                                   0x80
-#define PALMAS_INT3_MASK_VBUS_SHIFT                             7
-#define PALMAS_INT3_MASK_VBUS_OTG                               0x40
-#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
-#define PALMAS_INT3_MASK_ID                                     0x20
-#define PALMAS_INT3_MASK_ID_SHIFT                               5
-#define PALMAS_INT3_MASK_ID_OTG                                 0x10
-#define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
-#define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
-#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
-#define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
-#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
-#define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
-#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
-#define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
-#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
-
-/* Bit definitions for INT3_LINE_STATE */
-#define PALMAS_INT3_LINE_STATE_VBUS                             0x80
-#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
-#define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
-#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
-#define PALMAS_INT3_LINE_STATE_ID                               0x20
-#define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
-#define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
-#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
-#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
-#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
-#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
-#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
-#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
-#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
-#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
-#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
-
-/* Bit definitions for INT4_STATUS */
-#define PALMAS_INT4_STATUS_GPIO_7                               0x80
-#define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
-#define PALMAS_INT4_STATUS_GPIO_6                               0x40
-#define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
-#define PALMAS_INT4_STATUS_GPIO_5                               0x20
-#define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
-#define PALMAS_INT4_STATUS_GPIO_4                               0x10
-#define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
-#define PALMAS_INT4_STATUS_GPIO_3                               0x08
-#define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
-#define PALMAS_INT4_STATUS_GPIO_2                               0x04
-#define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
-#define PALMAS_INT4_STATUS_GPIO_1                               0x02
-#define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
-#define PALMAS_INT4_STATUS_GPIO_0                               0x01
-#define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
-
-/* Bit definitions for INT4_MASK */
-#define PALMAS_INT4_MASK_GPIO_7                                 0x80
-#define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
-#define PALMAS_INT4_MASK_GPIO_6                                 0x40
-#define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
-#define PALMAS_INT4_MASK_GPIO_5                                 0x20
-#define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
-#define PALMAS_INT4_MASK_GPIO_4                                 0x10
-#define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
-#define PALMAS_INT4_MASK_GPIO_3                                 0x08
-#define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
-#define PALMAS_INT4_MASK_GPIO_2                                 0x04
-#define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
-#define PALMAS_INT4_MASK_GPIO_1                                 0x02
-#define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
-#define PALMAS_INT4_MASK_GPIO_0                                 0x01
-#define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
-
-/* Bit definitions for INT4_LINE_STATE */
-#define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
-#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
-#define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
-#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
-#define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
-#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
-#define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
-#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
-#define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
-#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
-#define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
-#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
-#define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
-#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
-#define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
-#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
-
-/* Bit definitions for INT4_EDGE_DETECT1 */
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
-#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
-
-/* Bit definitions for INT4_EDGE_DETECT2 */
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
-#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
-
-/* Bit definitions for INT_CTRL */
-#define PALMAS_INT_CTRL_INT_PENDING                             0x04
-#define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
-#define PALMAS_INT_CTRL_INT_CLEAR                               0x01
-#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
-
-/* Registers for function USB_OTG */
-#define PALMAS_USB_WAKEUP                                       0x3
-#define PALMAS_USB_VBUS_CTRL_SET                                0x4
-#define PALMAS_USB_VBUS_CTRL_CLR                                0x5
-#define PALMAS_USB_ID_CTRL_SET                                  0x6
-#define PALMAS_USB_ID_CTRL_CLEAR                                0x7
-#define PALMAS_USB_VBUS_INT_SRC                                 0x8
-#define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
-#define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
-#define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
-#define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
-#define PALMAS_USB_ID_INT_SRC                                   0xF
-#define PALMAS_USB_ID_INT_LATCH_SET                             0x10
-#define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
-#define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
-#define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
-#define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
-#define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
-#define PALMAS_USB_OTG_ADP_CTRL                                 0x16
-#define PALMAS_USB_OTG_ADP_HIGH                                 0x17
-#define PALMAS_USB_OTG_ADP_LOW                                  0x18
-#define PALMAS_USB_OTG_ADP_RISE                                 0x19
-#define PALMAS_USB_OTG_REVISION                                 0x1A
-
-/* Bit definitions for USB_WAKEUP */
-#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
-#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
-
-/* Bit definitions for USB_VBUS_CTRL_SET */
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
-#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
-
-/* Bit definitions for USB_VBUS_CTRL_CLR */
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
-#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
-
-/* Bit definitions for USB_ID_CTRL_SET */
-#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
-#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
-#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
-#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
-#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
-#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
-#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
-#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
-#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
-#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
-#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
-#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
-
-/* Bit definitions for USB_ID_CTRL_CLEAR */
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
-#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
-
-/* Bit definitions for USB_VBUS_INT_SRC */
-#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
-#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
-#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
-#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
-#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
-#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
-#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
-#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
-#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
-#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
-#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
-#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
-#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
-#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
-
-/* Bit definitions for USB_VBUS_INT_LATCH_SET */
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
-#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
-#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
-#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
-
-/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
-#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
-
-/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
-#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
-
-/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
-#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
-
-/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
-#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
-
-/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
-#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
-
-/* Bit definitions for USB_ID_INT_SRC */
-#define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
-#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
-#define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
-#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
-#define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
-#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
-#define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
-#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
-#define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
-#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
-
-/* Bit definitions for USB_ID_INT_LATCH_SET */
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
-#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
-
-/* Bit definitions for USB_ID_INT_LATCH_CLR */
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
-#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
-
-/* Bit definitions for USB_ID_INT_EN_LO_SET */
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
-#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
-
-/* Bit definitions for USB_ID_INT_EN_LO_CLR */
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
-#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
-
-/* Bit definitions for USB_ID_INT_EN_HI_SET */
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
-#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
-
-/* Bit definitions for USB_ID_INT_EN_HI_CLR */
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
-#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
-
-/* Bit definitions for USB_OTG_ADP_CTRL */
-#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
-#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
-#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
-#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
-
-/* Bit definitions for USB_OTG_ADP_HIGH */
-#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
-#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
-
-/* Bit definitions for USB_OTG_ADP_LOW */
-#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
-#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
-
-/* Bit definitions for USB_OTG_ADP_RISE */
-#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
-#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
-
-/* Bit definitions for USB_OTG_REVISION */
-#define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
-#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
-
-/* Registers for function VIBRATOR */
-#define PALMAS_VIBRA_CTRL                                       0x0
-
-/* Bit definitions for VIBRA_CTRL */
-#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
-#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
-#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
-#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
-
-/* Registers for function GPIO */
-#define PALMAS_GPIO_DATA_IN                                     0x0
-#define PALMAS_GPIO_DATA_DIR                                    0x1
-#define PALMAS_GPIO_DATA_OUT                                    0x2
-#define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
-#define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
-#define PALMAS_GPIO_SET_DATA_OUT                                0x5
-#define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
-#define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
-#define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
-
-/* Bit definitions for GPIO_DATA_IN */
-#define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
-#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
-#define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
-#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
-#define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
-#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
-#define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
-#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
-#define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
-#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
-#define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
-#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
-#define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
-#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
-#define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
-#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
-
-/* Bit definitions for GPIO_DATA_DIR */
-#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
-#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
-#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
-#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
-#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
-#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
-#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
-#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
-#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
-#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
-#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
-#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
-#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
-#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
-#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
-#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
-
-/* Bit definitions for GPIO_DATA_OUT */
-#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
-#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
-#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
-#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
-#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
-#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
-#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
-#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
-#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
-#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
-#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
-#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
-#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
-#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
-#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
-#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
-
-/* Bit definitions for GPIO_DEBOUNCE_EN */
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
-#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
-
-/* Bit definitions for GPIO_CLEAR_DATA_OUT */
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
-#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
-
-/* Bit definitions for GPIO_SET_DATA_OUT */
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
-#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
-
-/* Bit definitions for PU_PD_GPIO_CTRL1 */
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
-#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
-
-/* Bit definitions for PU_PD_GPIO_CTRL2 */
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
-#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
-
-/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
-#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
-#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
-#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
-#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
-#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
-#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
-
-/* Registers for function GPADC */
-#define PALMAS_GPADC_CTRL1                                      0x0
-#define PALMAS_GPADC_CTRL2                                      0x1
-#define PALMAS_GPADC_RT_CTRL                                    0x2
-#define PALMAS_GPADC_AUTO_CTRL                                  0x3
-#define PALMAS_GPADC_STATUS                                     0x4
-#define PALMAS_GPADC_RT_SELECT                                  0x5
-#define PALMAS_GPADC_RT_CONV0_LSB                               0x6
-#define PALMAS_GPADC_RT_CONV0_MSB                               0x7
-#define PALMAS_GPADC_AUTO_SELECT                                0x8
-#define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
-#define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
-#define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
-#define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
-#define PALMAS_GPADC_SW_SELECT                                  0xD
-#define PALMAS_GPADC_SW_CONV0_LSB                               0xE
-#define PALMAS_GPADC_SW_CONV0_MSB                               0xF
-#define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
-#define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
-#define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
-#define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
-#define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
-#define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
-
-/* Bit definitions for GPADC_CTRL1 */
-#define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
-#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
-#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
-#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
-#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
-#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
-#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
-#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
-#define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
-#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
-
-/* Bit definitions for GPADC_CTRL2 */
-#define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
-#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
-
-/* Bit definitions for GPADC_RT_CTRL */
-#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
-#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
-#define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
-#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
-
-/* Bit definitions for GPADC_AUTO_CTRL */
-#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
-#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
-#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
-#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
-#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
-#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
-#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
-#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
-#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
-#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
-
-/* Bit definitions for GPADC_STATUS */
-#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
-#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
-
-/* Bit definitions for GPADC_RT_SELECT */
-#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
-#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
-#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
-#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
-
-/* Bit definitions for GPADC_RT_CONV0_LSB */
-#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
-#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
-
-/* Bit definitions for GPADC_RT_CONV0_MSB */
-#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
-#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
-
-/* Bit definitions for GPADC_AUTO_SELECT */
-#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
-#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
-#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
-#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
-
-/* Bit definitions for GPADC_AUTO_CONV0_LSB */
-#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
-#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
-
-/* Bit definitions for GPADC_AUTO_CONV0_MSB */
-#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
-#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
-
-/* Bit definitions for GPADC_AUTO_CONV1_LSB */
-#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
-#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
-
-/* Bit definitions for GPADC_AUTO_CONV1_MSB */
-#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
-#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
-
-/* Bit definitions for GPADC_SW_SELECT */
-#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
-#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
-#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
-#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
-#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
-#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
-
-/* Bit definitions for GPADC_SW_CONV0_LSB */
-#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
-#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
-
-/* Bit definitions for GPADC_SW_CONV0_MSB */
-#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
-#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
-
-/* Bit definitions for GPADC_THRES_CONV0_LSB */
-#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
-#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
-
-/* Bit definitions for GPADC_THRES_CONV0_MSB */
-#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
-#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
-#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
-#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
-
-/* Bit definitions for GPADC_THRES_CONV1_LSB */
-#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
-#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
-
-/* Bit definitions for GPADC_THRES_CONV1_MSB */
-#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
-#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
-#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
-#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
-
-/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
-#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
-#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
-#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
-#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
-#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
-#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
-
-/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
-#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
-#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
-#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
-#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
-
-/* Registers for function GPADC */
-#define PALMAS_GPADC_TRIM1                                      0x0
-#define PALMAS_GPADC_TRIM2                                      0x1
-#define PALMAS_GPADC_TRIM3                                      0x2
-#define PALMAS_GPADC_TRIM4                                      0x3
-#define PALMAS_GPADC_TRIM5                                      0x4
-#define PALMAS_GPADC_TRIM6                                      0x5
-#define PALMAS_GPADC_TRIM7                                      0x6
-#define PALMAS_GPADC_TRIM8                                      0x7
-#define PALMAS_GPADC_TRIM9                                      0x8
-#define PALMAS_GPADC_TRIM10                                     0x9
-#define PALMAS_GPADC_TRIM11                                     0xA
-#define PALMAS_GPADC_TRIM12                                     0xB
-#define PALMAS_GPADC_TRIM13                                     0xC
-#define PALMAS_GPADC_TRIM14                                     0xD
-#define PALMAS_GPADC_TRIM15                                     0xE
-#define PALMAS_GPADC_TRIM16                                     0xF
-
-#endif /*  __LINUX_MFD_PALMAS_H */
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index a80840752b4..50d4a047118 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -21,7 +21,6 @@
 #include <linux/mfd/pcf50633/backlight.h>
 
 struct pcf50633;
-struct regmap;
 
 #define PCF50633_NUM_REGULATORS 11
 
@@ -135,7 +134,7 @@ enum {
 
 struct pcf50633 {
         struct device *dev;
-        struct regmap *regmap;
+        struct i2c_client *i2c_client;
 
         struct pcf50633_platform_data *pdata;
         int irq;
diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h
index f83d6b43ecb..4b21769f448 100644
--- a/include/linux/mfd/pm8xxx/irq.h
+++ b/include/linux/mfd/pm8xxx/irq.h
@@ -37,21 +37,21 @@ struct pm_irq_chip;
 
 #ifdef CONFIG_MFD_PM8XXX_IRQ
 int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
-struct pm_irq_chip *pm8xxx_irq_init(struct device *dev,
+struct pm_irq_chip * __devinit pm8xxx_irq_init(struct device *dev,
                                 const struct pm8xxx_irq_platform_data *pdata);
-int pm8xxx_irq_exit(struct pm_irq_chip *chip);
+int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip);
 #else
 static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
 {
         return -ENXIO;
 }
-static inline struct pm_irq_chip *pm8xxx_irq_init(
+static inline struct pm_irq_chip * __devinit pm8xxx_irq_init(
                                 const struct device *dev,
                                 const struct pm8xxx_irq_platform_data *pdata)
 {
         return ERR_PTR(-ENXIO);
 }
-static inline int pm8xxx_irq_exit(struct pm_irq_chip *chip)
+static inline int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip)
 {
         return -ENXIO;
 }
diff --git a/include/linux/mfd/pm8xxx/pm8921.h b/include/linux/mfd/pm8xxx/pm8921.h
index 00fa3de7659..d5517fd32d1 100644
--- a/include/linux/mfd/pm8xxx/pm8921.h
+++ b/include/linux/mfd/pm8xxx/pm8921.h
@@ -18,6 +18,7 @@
 #ifndef __MFD_PM8921_H
 #define __MFD_PM8921_H
 
+#include <linux/device.h>
 #include <linux/mfd/pm8xxx/irq.h>
 
 #define PM8921_NR_IRQS          256
diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h
index fd413ccab91..a2c61609d21 100644
--- a/include/linux/mfd/rc5t583.h
+++ b/include/linux/mfd/rc5t583.h
@@ -26,14 +26,12 @@
 
 #include <linux/mutex.h>
 #include <linux/types.h>
-#include <linux/regmap.h>
 
 #define RC5T583_MAX_REGS                0xF8
 
 /* Maximum number of main interrupts */
 #define MAX_MAIN_INTERRUPT              5
 #define RC5T583_MAX_GPEDGE_REG          2
-#define RC5T583_MAX_INTERRUPT_EN_REGS   8
 #define RC5T583_MAX_INTERRUPT_MASK_REGS 9
 
 /* Interrupt enable register */
@@ -147,28 +145,6 @@
 #define RC5T583_GPIO_MON_IOIN   0xAB
 #define RC5T583_GPIO_GPOFUNC    0xAC
 
-/* RTC registers */
-#define RC5T583_RTC_SEC         0xE0
-#define RC5T583_RTC_MIN         0xE1
-#define RC5T583_RTC_HOUR        0xE2
-#define RC5T583_RTC_WDAY        0xE3
-#define RC5T583_RTC_DAY         0xE4
-#define RC5T583_RTC_MONTH       0xE5
-#define RC5T583_RTC_YEAR        0xE6
-#define RC5T583_RTC_ADJ         0xE7
-#define RC5T583_RTC_AW_MIN      0xE8
-#define RC5T583_RTC_AW_HOUR     0xE9
-#define RC5T583_RTC_AW_WEEK     0xEA
-#define RC5T583_RTC_AD_MIN      0xEB
-#define RC5T583_RTC_AD_HOUR     0xEC
-#define RC5T583_RTC_CTL1        0xED
-#define RC5T583_RTC_CTL2        0xEE
-#define RC5T583_RTC_AY_MIN      0xF0
-#define RC5T583_RTC_AY_HOUR     0xF1
-#define RC5T583_RTC_AY_DAY      0xF2
-#define RC5T583_RTC_AY_MONTH 0xF3
-#define RC5T583_RTC_AY_YEAR     0xF4
-
 /* RICOH_RC5T583 IRQ definitions */
 enum {
         RC5T583_IRQ_ONKEY,
@@ -273,26 +249,6 @@ enum {
         RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
 };
 
-enum {
-        RC5T583_REGULATOR_DC0,
-        RC5T583_REGULATOR_DC1,
-        RC5T583_REGULATOR_DC2,
-        RC5T583_REGULATOR_DC3,
-        RC5T583_REGULATOR_LDO0,
-        RC5T583_REGULATOR_LDO1,
-        RC5T583_REGULATOR_LDO2,
-        RC5T583_REGULATOR_LDO3,
-        RC5T583_REGULATOR_LDO4,
-        RC5T583_REGULATOR_LDO5,
-        RC5T583_REGULATOR_LDO6,
-        RC5T583_REGULATOR_LDO7,
-        RC5T583_REGULATOR_LDO8,
-        RC5T583_REGULATOR_LDO9,
-
-        /* Should be last entry */
-        RC5T583_REGULATOR_MAX,
-};
-
 struct rc5t583 {
         struct device   *dev;
         struct regmap   *regmap;
@@ -305,7 +261,7 @@ struct rc5t583 {
         uint8_t         intc_inten_reg;
 
         /* For group interrupt bits and address */
-        uint8_t         irq_en_reg[RC5T583_MAX_INTERRUPT_EN_REGS];
+        uint8_t         irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];
 
         /* For gpio edge */
         uint8_t         gpedge_reg[RC5T583_MAX_GPEDGE_REG];
@@ -315,63 +271,22 @@ struct rc5t583 {
  * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
  * The board specific data is provided through this structure.
  * @irq_base: Irq base number on which this device registers their interrupts.
- * @gpio_base: GPIO base from which gpio of this device will start.
  * @enable_shutdown: Enable shutdown through the input pin "shutdown".
- * @regulator_deepsleep_slot: The slot number on which device goes to sleep
- *              in device sleep mode.
- * @regulator_ext_pwr_control: External power request regulator control. The
- *              regulator output enable/disable is controlled by the external
- *              power request input state.
- * @reg_init_data: Regulator init data.
  */
 
 struct rc5t583_platform_data {
         int             irq_base;
-        int             gpio_base;
         bool            enable_shutdown;
-        int             regulator_deepsleep_slot[RC5T583_REGULATOR_MAX];
-        unsigned long   regulator_ext_pwr_control[RC5T583_REGULATOR_MAX];
-        struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX];
 };
 
-static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
-{
-        struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
-        return regmap_write(rc5t583->regmap, reg, val);
-}
-
-static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)
-{
-        struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
-        unsigned int ival;
-        int ret;
-        ret = regmap_read(rc5t583->regmap, reg, &ival);
-        if (!ret)
-                *val = (uint8_t)ival;
-        return ret;
-}
-
-static inline int rc5t583_set_bits(struct device *dev, unsigned int reg,
-                        unsigned int bit_mask)
-{
-        struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
-        return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
-}
-
-static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg,
-                        unsigned int bit_mask)
-{
-        struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
-        return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
-}
-
-static inline int rc5t583_update(struct device *dev, unsigned int reg,
-                unsigned int val, unsigned int mask)
-{
-        struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
-        return regmap_update_bits(rc5t583->regmap, reg, mask, val);
-}
-
+int rc5t583_write(struct device *dev, u8 reg, uint8_t val);
+int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val);
+int rc5t583_set_bits(struct device *dev, unsigned int reg,
+                unsigned int bit_mask);
+int rc5t583_clear_bits(struct device *dev, unsigned int reg,
+                unsigned int bit_mask);
+int rc5t583_update(struct device *dev, unsigned int reg,
+                unsigned int val, unsigned int mask);
 int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
         int ext_pwr_req, int deepsleep_slot_nr);
 int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
diff --git a/include/linux/mfd/retu.h b/include/linux/mfd/retu.h
deleted file mode 100644
index 1e2715d5b83..00000000000
--- a/include/linux/mfd/retu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Retu MFD driver interface
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of this
- * archive for more details.
- */
-
-#ifndef __LINUX_MFD_RETU_H
-#define __LINUX_MFD_RETU_H
-
-struct retu_dev;
-
-int retu_read(struct retu_dev *, u8);
-int retu_write(struct retu_dev *, u8, u16);
-
-/* Registers */
-#define RETU_REG_WATCHDOG       0x17            /* Watchdog */
-#define RETU_REG_CC1            0x0d            /* Common control register 1 */
-#define RETU_REG_STATUS         0x16            /* Status register */
-
-#endif /* __LINUX_MFD_RETU_H */
diff --git a/include/linux/mfd/rtsx_common.h b/include/linux/mfd/rtsx_common.h
deleted file mode 100644
index a8d393e3066..00000000000
--- a/include/linux/mfd/rtsx_common.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Driver for Realtek driver-based card reader
- *
- * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- * Author:
- *   Wei WANG <wei_wang@realsil.com.cn>
- *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
- */
-
-#ifndef __RTSX_COMMON_H
-#define __RTSX_COMMON_H
-
-#define DRV_NAME_RTSX_PCI               "rtsx_pci"
-#define DRV_NAME_RTSX_PCI_SDMMC         "rtsx_pci_sdmmc"
-#define DRV_NAME_RTSX_PCI_MS            "rtsx_pci_ms"
-
-#define RTSX_REG_PAIR(addr, val)        (((u32)(addr) << 16) | (u8)(val))
-
-#define RTSX_SSC_DEPTH_4M               0x01
-#define RTSX_SSC_DEPTH_2M               0x02
-#define RTSX_SSC_DEPTH_1M               0x03
-#define RTSX_SSC_DEPTH_500K             0x04
-#define RTSX_SSC_DEPTH_250K             0x05
-
-#define RTSX_SD_CARD                    0
-#define RTSX_MS_CARD                    1
-
-struct platform_device;
-
-struct rtsx_slot {
-        struct platform_device  *p_dev;
-        void                    (*card_event)(struct platform_device *p_dev);
-};
-
-#endif
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
deleted file mode 100644
index 060b721fcbf..00000000000
--- a/include/linux/mfd/rtsx_pci.h
+++ /dev/null
@@ -1,794 +0,0 @@
-/* Driver for Realtek PCI-Express card reader
- *
- * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- * Author:
- *   Wei WANG <wei_wang@realsil.com.cn>
- *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
- */
-
-#ifndef __RTSX_PCI_H
-#define __RTSX_PCI_H
-
-#include <linux/sched.h>
-#include <linux/pci.h>
-
-#include "rtsx_common.h"
-
-#define MAX_RW_REG_CNT                  1024
-
-/* PCI Operation Register Address */
-#define RTSX_HCBAR                      0x00
-#define RTSX_HCBCTLR                    0x04
-#define RTSX_HDBAR                      0x08
-#define RTSX_HDBCTLR                    0x0C
-#define RTSX_HAIMR                      0x10
-#define RTSX_BIPR                       0x14
-#define RTSX_BIER                       0x18
-
-/* Host command buffer control register */
-#define STOP_CMD                        (0x01 << 28)
-
-/* Host data buffer control register */
-#define SDMA_MODE                       0x00
-#define ADMA_MODE                       (0x02 << 26)
-#define STOP_DMA                        (0x01 << 28)
-#define TRIG_DMA                        (0x01 << 31)
-
-/* Host access internal memory register */
-#define HAIMR_TRANS_START               (0x01 << 31)
-#define HAIMR_READ                      0x00
-#define HAIMR_WRITE                     (0x01 << 30)
-#define HAIMR_READ_START                (HAIMR_TRANS_START | HAIMR_READ)
-#define HAIMR_WRITE_START               (HAIMR_TRANS_START | HAIMR_WRITE)
-#define HAIMR_TRANS_END                 (HAIMR_TRANS_START)
-
-/* Bus interrupt pending register */
-#define CMD_DONE_INT                    (1 << 31)
-#define DATA_DONE_INT                   (1 << 30)
-#define TRANS_OK_INT                    (1 << 29)
-#define TRANS_FAIL_INT                  (1 << 28)
-#define XD_INT                          (1 << 27)
-#define MS_INT                          (1 << 26)
-#define SD_INT                          (1 << 25)
-#define GPIO0_INT                       (1 << 24)
-#define OC_INT                          (1 << 23)
-#define SD_WRITE_PROTECT                (1 << 19)
-#define XD_EXIST                        (1 << 18)
-#define MS_EXIST                        (1 << 17)
-#define SD_EXIST                        (1 << 16)
-#define DELINK_INT                      GPIO0_INT
-#define MS_OC_INT                       (1 << 23)
-#define SD_OC_INT                       (1 << 22)
-
-#define CARD_INT                (XD_INT | MS_INT | SD_INT)
-#define NEED_COMPLETE_INT       (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
-#define RTSX_INT                (CMD_DONE_INT | NEED_COMPLETE_INT | \
-                                        CARD_INT | GPIO0_INT | OC_INT)
-
-#define CARD_EXIST              (XD_EXIST | MS_EXIST | SD_EXIST)
-
-/* Bus interrupt enable register */
-#define CMD_DONE_INT_EN         (1 << 31)
-#define DATA_DONE_INT_EN        (1 << 30)
-#define TRANS_OK_INT_EN         (1 << 29)
-#define TRANS_FAIL_INT_EN       (1 << 28)
-#define XD_INT_EN               (1 << 27)
-#define MS_INT_EN               (1 << 26)
-#define SD_INT_EN               (1 << 25)
-#define GPIO0_INT_EN            (1 << 24)
-#define OC_INT_EN               (1 << 23)
-#define DELINK_INT_EN           GPIO0_INT_EN
-#define MS_OC_INT_EN            (1 << 23)
-#define SD_OC_INT_EN            (1 << 22)
-
-#define READ_REG_CMD            0
-#define WRITE_REG_CMD           1
-#define CHECK_REG_CMD           2
-
-/*
- * macros for easy use
- */
-#define rtsx_pci_writel(pcr, reg, value) \
-        iowrite32(value, (pcr)->remap_addr + reg)
-#define rtsx_pci_readl(pcr, reg) \
-        ioread32((pcr)->remap_addr + reg)
-#define rtsx_pci_writew(pcr, reg, value) \
-        iowrite16(value, (pcr)->remap_addr + reg)
-#define rtsx_pci_readw(pcr, reg) \
-        ioread16((pcr)->remap_addr + reg)
-#define rtsx_pci_writeb(pcr, reg, value) \
-        iowrite8(value, (pcr)->remap_addr + reg)
-#define rtsx_pci_readb(pcr, reg) \
-        ioread8((pcr)->remap_addr + reg)
-
-#define rtsx_pci_read_config_byte(pcr, where, val) \
-        pci_read_config_byte((pcr)->pci, where, val)
-
-#define rtsx_pci_write_config_byte(pcr, where, val) \
-        pci_write_config_byte((pcr)->pci, where, val)
-
-#define rtsx_pci_read_config_dword(pcr, where, val) \
-        pci_read_config_dword((pcr)->pci, where, val)
-
-#define rtsx_pci_write_config_dword(pcr, where, val) \
-        pci_write_config_dword((pcr)->pci, where, val)
-
-#define STATE_TRANS_NONE        0
-#define STATE_TRANS_CMD         1
-#define STATE_TRANS_BUF         2
-#define STATE_TRANS_SG          3
-
-#define TRANS_NOT_READY         0
-#define TRANS_RESULT_OK         1
-#define TRANS_RESULT_FAIL       2
-#define TRANS_NO_DEVICE         3
-
-#define RTSX_RESV_BUF_LEN       4096
-#define HOST_CMDS_BUF_LEN       1024
-#define HOST_SG_TBL_BUF_LEN     (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
-#define HOST_SG_TBL_ITEMS       (HOST_SG_TBL_BUF_LEN / 8)
-#define MAX_SG_ITEM_LEN         0x80000
-
-#define HOST_TO_DEVICE          0
-#define DEVICE_TO_HOST          1
-
-#define MAX_PHASE               31
-#define RX_TUNING_CNT           3
-
-/* SG descriptor */
-#define SG_INT                  0x04
-#define SG_END                  0x02
-#define SG_VALID                0x01
-
-#define SG_NO_OP                0x00
-#define SG_TRANS_DATA           (0x02 << 4)
-#define SG_LINK_DESC            (0x03 << 4)
-
-/* SD bank voltage */
-#define SD_IO_3V3               0
-#define SD_IO_1V8               1
-
-
-/* Card Clock Enable Register */
-#define SD_CLK_EN                       0x04
-#define MS_CLK_EN                       0x08
-
-/* Card Select Register */
-#define SD_MOD_SEL                      2
-#define MS_MOD_SEL                      3
-
-/* Card Output Enable Register */
-#define SD_OUTPUT_EN                    0x04
-#define MS_OUTPUT_EN                    0x08
-
-/* CARD_SHARE_MODE */
-#define CARD_SHARE_MASK                 0x0F
-#define CARD_SHARE_MULTI_LUN            0x00
-#define CARD_SHARE_NORMAL               0x00
-#define CARD_SHARE_48_SD                0x04
-#define CARD_SHARE_48_MS                0x08
-/* CARD_SHARE_MODE for barossa */
-#define CARD_SHARE_BAROSSA_SD           0x01
-#define CARD_SHARE_BAROSSA_MS           0x02
-
-/* SD30_DRIVE_SEL */
-#define DRIVER_TYPE_A                   0x05
-#define DRIVER_TYPE_B                   0x03
-#define DRIVER_TYPE_C                   0x02
-#define DRIVER_TYPE_D                   0x01
-
-/* FPDCTL */
-#define SSC_POWER_DOWN                  0x01
-#define SD_OC_POWER_DOWN                0x02
-#define ALL_POWER_DOWN                  0x07
-#define OC_POWER_DOWN                   0x06
-
-/* CLK_CTL */
-#define CHANGE_CLK                      0x01
-
-/* LDO_CTL */
-#define BPP_LDO_POWB                    0x03
-#define BPP_LDO_ON                      0x00
-#define BPP_LDO_SUSPEND                 0x02
-#define BPP_LDO_OFF                     0x03
-
-/* CD_PAD_CTL */
-#define CD_DISABLE_MASK                 0x07
-#define MS_CD_DISABLE                   0x04
-#define SD_CD_DISABLE                   0x02
-#define XD_CD_DISABLE                   0x01
-#define CD_DISABLE                      0x07
-#define CD_ENABLE                       0x00
-#define MS_CD_EN_ONLY                   0x03
-#define SD_CD_EN_ONLY                   0x05
-#define XD_CD_EN_ONLY                   0x06
-#define FORCE_CD_LOW_MASK               0x38
-#define FORCE_CD_XD_LOW                 0x08
-#define FORCE_CD_SD_LOW                 0x10
-#define FORCE_CD_MS_LOW                 0x20
-#define CD_AUTO_DISABLE                 0x40
-
-/* SD_STAT1 */
-#define SD_CRC7_ERR                     0x80
-#define SD_CRC16_ERR                    0x40
-#define SD_CRC_WRITE_ERR                0x20
-#define SD_CRC_WRITE_ERR_MASK           0x1C
-#define GET_CRC_TIME_OUT                0x02
-#define SD_TUNING_COMPARE_ERR           0x01
-
-/* SD_STAT2 */
-#define SD_RSP_80CLK_TIMEOUT            0x01
-
-/* SD_BUS_STAT */
-#define SD_CLK_TOGGLE_EN                0x80
-#define SD_CLK_FORCE_STOP               0x40
-#define SD_DAT3_STATUS                  0x10
-#define SD_DAT2_STATUS                  0x08
-#define SD_DAT1_STATUS                  0x04
-#define SD_DAT0_STATUS                  0x02
-#define SD_CMD_STATUS                   0x01
-
-/* SD_PAD_CTL */
-#define SD_IO_USING_1V8                 0x80
-#define SD_IO_USING_3V3                 0x7F
-#define TYPE_A_DRIVING                  0x00
-#define TYPE_B_DRIVING                  0x01
-#define TYPE_C_DRIVING                  0x02
-#define TYPE_D_DRIVING                  0x03
-
-/* SD_SAMPLE_POINT_CTL */
-#define DDR_FIX_RX_DAT                  0x00
-#define DDR_VAR_RX_DAT                  0x80
-#define DDR_FIX_RX_DAT_EDGE             0x00
-#define DDR_FIX_RX_DAT_14_DELAY         0x40
-#define DDR_FIX_RX_CMD                  0x00
-#define DDR_VAR_RX_CMD                  0x20
-#define DDR_FIX_RX_CMD_POS_EDGE         0x00
-#define DDR_FIX_RX_CMD_14_DELAY         0x10
-#define SD20_RX_POS_EDGE                0x00
-#define SD20_RX_14_DELAY                0x08
-#define SD20_RX_SEL_MASK                0x08
-
-/* SD_PUSH_POINT_CTL */
-#define DDR_FIX_TX_CMD_DAT              0x00
-#define DDR_VAR_TX_CMD_DAT              0x80
-#define DDR_FIX_TX_DAT_14_TSU           0x00
-#define DDR_FIX_TX_DAT_12_TSU           0x40
-#define DDR_FIX_TX_CMD_NEG_EDGE         0x00
-#define DDR_FIX_TX_CMD_14_AHEAD         0x20
-#define SD20_TX_NEG_EDGE                0x00
-#define SD20_TX_14_AHEAD                0x10
-#define SD20_TX_SEL_MASK                0x10
-#define DDR_VAR_SDCLK_POL_SWAP          0x01
-
-/* SD_TRANSFER */
-#define SD_TRANSFER_START               0x80
-#define SD_TRANSFER_END                 0x40
-#define SD_STAT_IDLE                    0x20
-#define SD_TRANSFER_ERR                 0x10
-/* SD Transfer Mode definition */
-#define SD_TM_NORMAL_WRITE              0x00
-#define SD_TM_AUTO_WRITE_3              0x01
-#define SD_TM_AUTO_WRITE_4              0x02
-#define SD_TM_AUTO_READ_3               0x05
-#define SD_TM_AUTO_READ_4               0x06
-#define SD_TM_CMD_RSP                   0x08
-#define SD_TM_AUTO_WRITE_1              0x09
-#define SD_TM_AUTO_WRITE_2              0x0A
-#define SD_TM_NORMAL_READ               0x0C
-#define SD_TM_AUTO_READ_1               0x0D
-#define SD_TM_AUTO_READ_2               0x0E
-#define SD_TM_AUTO_TUNING               0x0F
-
-/* SD_VPTX_CTL / SD_VPRX_CTL */
-#define PHASE_CHANGE                    0x80
-#define PHASE_NOT_RESET                 0x40
-
-/* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
-#define DCMPS_CHANGE                    0x80
-#define DCMPS_CHANGE_DONE               0x40
-#define DCMPS_ERROR                     0x20
-#define DCMPS_CURRENT_PHASE             0x1F
-
-/* SD Configure 1 Register */
-#define SD_CLK_DIVIDE_0                 0x00
-#define SD_CLK_DIVIDE_256               0xC0
-#define SD_CLK_DIVIDE_128               0x80
-#define SD_BUS_WIDTH_1BIT               0x00
-#define SD_BUS_WIDTH_4BIT               0x01
-#define SD_BUS_WIDTH_8BIT               0x02
-#define SD_ASYNC_FIFO_NOT_RST           0x10
-#define SD_20_MODE                      0x00
-#define SD_DDR_MODE                     0x04
-#define SD_30_MODE                      0x08
-
-#define SD_CLK_DIVIDE_MASK              0xC0
-
-/* SD_CMD_STATE */
-#define SD_CMD_IDLE                     0x80
-
-/* SD_DATA_STATE */
-#define SD_DATA_IDLE                    0x80
-
-/* DCM_DRP_CTL */
-#define DCM_RESET                       0x08
-#define DCM_LOCKED                      0x04
-#define DCM_208M                        0x00
-#define DCM_TX                          0x01
-#define DCM_RX                          0x02
-
-/* DCM_DRP_TRIG */
-#define DRP_START                       0x80
-#define DRP_DONE                        0x40
-
-/* DCM_DRP_CFG */
-#define DRP_WRITE                       0x80
-#define DRP_READ                        0x00
-#define DCM_WRITE_ADDRESS_50            0x50
-#define DCM_WRITE_ADDRESS_51            0x51
-#define DCM_READ_ADDRESS_00             0x00
-#define DCM_READ_ADDRESS_51             0x51
-
-/* IRQSTAT0 */
-#define DMA_DONE_INT                    0x80
-#define SUSPEND_INT                     0x40
-#define LINK_RDY_INT                    0x20
-#define LINK_DOWN_INT                   0x10
-
-/* DMACTL */
-#define DMA_RST                         0x80
-#define DMA_BUSY                        0x04
-#define DMA_DIR_TO_CARD                 0x00
-#define DMA_DIR_FROM_CARD               0x02
-#define DMA_EN                          0x01
-#define DMA_128                         (0 << 4)
-#define DMA_256                         (1 << 4)
-#define DMA_512                         (2 << 4)
-#define DMA_1024                        (3 << 4)
-#define DMA_PACK_SIZE_MASK              0x30
-
-/* SSC_CTL1 */
-#define SSC_RSTB                        0x80
-#define SSC_8X_EN                       0x40
-#define SSC_FIX_FRAC                    0x20
-#define SSC_SEL_1M                      0x00
-#define SSC_SEL_2M                      0x08
-#define SSC_SEL_4M                      0x10
-#define SSC_SEL_8M                      0x18
-
-/* SSC_CTL2 */
-#define SSC_DEPTH_MASK                  0x07
-#define SSC_DEPTH_DISALBE               0x00
-#define SSC_DEPTH_4M                    0x01
-#define SSC_DEPTH_2M                    0x02
-#define SSC_DEPTH_1M                    0x03
-#define SSC_DEPTH_500K                  0x04
-#define SSC_DEPTH_250K                  0x05
-
-/* System Clock Control Register */
-#define CLK_LOW_FREQ                    0x01
-
-/* System Clock Divider Register */
-#define CLK_DIV_1                       0x01
-#define CLK_DIV_2                       0x02
-#define CLK_DIV_4                       0x03
-#define CLK_DIV_8                       0x04
-
-/* MS_CFG */
-#define SAMPLE_TIME_RISING              0x00
-#define SAMPLE_TIME_FALLING             0x80
-#define PUSH_TIME_DEFAULT               0x00
-#define PUSH_TIME_ODD                   0x40
-#define NO_EXTEND_TOGGLE                0x00
-#define EXTEND_TOGGLE_CHK               0x20
-#define MS_BUS_WIDTH_1                  0x00
-#define MS_BUS_WIDTH_4                  0x10
-#define MS_BUS_WIDTH_8                  0x18
-#define MS_2K_SECTOR_MODE               0x04
-#define MS_512_SECTOR_MODE              0x00
-#define MS_TOGGLE_TIMEOUT_EN            0x00
-#define MS_TOGGLE_TIMEOUT_DISEN         0x01
-#define MS_NO_CHECK_INT                 0x02
-
-/* MS_TRANS_CFG */
-#define WAIT_INT                        0x80
-#define NO_WAIT_INT                     0x00
-#define NO_AUTO_READ_INT_REG            0x00
-#define AUTO_READ_INT_REG               0x40
-#define MS_CRC16_ERR                    0x20
-#define MS_RDY_TIMEOUT                  0x10
-#define MS_INT_CMDNK                    0x08
-#define MS_INT_BREQ                     0x04
-#define MS_INT_ERR                      0x02
-#define MS_INT_CED                      0x01
-
-/* MS_TRANSFER */
-#define MS_TRANSFER_START               0x80
-#define MS_TRANSFER_END                 0x40
-#define MS_TRANSFER_ERR                 0x20
-#define MS_BS_STATE                     0x10
-#define MS_TM_READ_BYTES                0x00
-#define MS_TM_NORMAL_READ               0x01
-#define MS_TM_WRITE_BYTES               0x04
-#define MS_TM_NORMAL_WRITE              0x05
-#define MS_TM_AUTO_READ                 0x08
-#define MS_TM_AUTO_WRITE                0x0C
-
-/* SD Configure 2 Register */
-#define SD_CALCULATE_CRC7               0x00
-#define SD_NO_CALCULATE_CRC7            0x80
-#define SD_CHECK_CRC16                  0x00
-#define SD_NO_CHECK_CRC16               0x40
-#define SD_NO_CHECK_WAIT_CRC_TO         0x20
-#define SD_WAIT_BUSY_END                0x08
-#define SD_NO_WAIT_BUSY_END             0x00
-#define SD_CHECK_CRC7                   0x00
-#define SD_NO_CHECK_CRC7                0x04
-#define SD_RSP_LEN_0                    0x00
-#define SD_RSP_LEN_6                    0x01
-#define SD_RSP_LEN_17                   0x02
-/* SD/MMC Response Type Definition */
-#define SD_RSP_TYPE_R0                  0x04
-#define SD_RSP_TYPE_R1                  0x01
-#define SD_RSP_TYPE_R1b                 0x09
-#define SD_RSP_TYPE_R2                  0x02
-#define SD_RSP_TYPE_R3                  0x05
-#define SD_RSP_TYPE_R4                  0x05
-#define SD_RSP_TYPE_R5                  0x01
-#define SD_RSP_TYPE_R6                  0x01
-#define SD_RSP_TYPE_R7                  0x01
-
-/* SD_CONFIURE3 */
-#define SD_RSP_80CLK_TIMEOUT_EN         0x01
-
-/* Card Transfer Reset Register */
-#define SPI_STOP                        0x01
-#define XD_STOP                         0x02
-#define SD_STOP                         0x04
-#define MS_STOP                         0x08
-#define SPI_CLR_ERR                     0x10
-#define XD_CLR_ERR                      0x20
-#define SD_CLR_ERR                      0x40
-#define MS_CLR_ERR                      0x80
-
-/* Card Data Source Register */
-#define PINGPONG_BUFFER                 0x01
-#define RING_BUFFER                     0x00
-
-/* Card Power Control Register */
-#define PMOS_STRG_MASK                  0x10
-#define PMOS_STRG_800mA                 0x10
-#define PMOS_STRG_400mA                 0x00
-#define SD_POWER_OFF                    0x03
-#define SD_PARTIAL_POWER_ON             0x01
-#define SD_POWER_ON                     0x00
-#define SD_POWER_MASK                   0x03
-#define MS_POWER_OFF                    0x0C
-#define MS_PARTIAL_POWER_ON             0x04
-#define MS_POWER_ON                     0x00
-#define MS_POWER_MASK                   0x0C
-#define BPP_POWER_OFF                   0x0F
-#define BPP_POWER_5_PERCENT_ON          0x0E
-#define BPP_POWER_10_PERCENT_ON         0x0C
-#define BPP_POWER_15_PERCENT_ON         0x08
-#define BPP_POWER_ON                    0x00
-#define BPP_POWER_MASK                  0x0F
-
-/* PWR_GATE_CTRL */
-#define PWR_GATE_EN                     0x01
-#define LDO3318_PWR_MASK                0x06
-#define LDO_ON                          0x00
-#define LDO_SUSPEND                     0x04
-#define LDO_OFF                         0x06
-
-/* CARD_CLK_SOURCE */
-#define CRC_FIX_CLK                     (0x00 << 0)
-#define CRC_VAR_CLK0                    (0x01 << 0)
-#define CRC_VAR_CLK1                    (0x02 << 0)
-#define SD30_FIX_CLK                    (0x00 << 2)
-#define SD30_VAR_CLK0                   (0x01 << 2)
-#define SD30_VAR_CLK1                   (0x02 << 2)
-#define SAMPLE_FIX_CLK                  (0x00 << 4)
-#define SAMPLE_VAR_CLK0                 (0x01 << 4)
-#define SAMPLE_VAR_CLK1                 (0x02 << 4)
-
-#define MS_CFG                          0xFD40
-#define MS_TPC                          0xFD41
-#define MS_TRANS_CFG                    0xFD42
-#define MS_TRANSFER                     0xFD43
-#define MS_INT_REG                      0xFD44
-#define MS_BYTE_CNT                     0xFD45
-#define MS_SECTOR_CNT_L                 0xFD46
-#define MS_SECTOR_CNT_H                 0xFD47
-#define MS_DBUS_H                       0xFD48
-
-#define SD_CFG1                         0xFDA0
-#define SD_CFG2                         0xFDA1
-#define SD_CFG3                         0xFDA2
-#define SD_STAT1                        0xFDA3
-#define SD_STAT2                        0xFDA4
-#define SD_BUS_STAT                     0xFDA5
-#define SD_PAD_CTL                      0xFDA6
-#define SD_SAMPLE_POINT_CTL             0xFDA7
-#define SD_PUSH_POINT_CTL               0xFDA8
-#define SD_CMD0                         0xFDA9
-#define SD_CMD1                         0xFDAA
-#define SD_CMD2                         0xFDAB
-#define SD_CMD3                         0xFDAC
-#define SD_CMD4                         0xFDAD
-#define SD_CMD5                         0xFDAE
-#define SD_BYTE_CNT_L                   0xFDAF
-#define SD_BYTE_CNT_H                   0xFDB0
-#define SD_BLOCK_CNT_L                  0xFDB1
-#define SD_BLOCK_CNT_H                  0xFDB2
-#define SD_TRANSFER                     0xFDB3
-#define SD_CMD_STATE                    0xFDB5
-#define SD_DATA_STATE                   0xFDB6
-
-#define SRCTL                           0xFC13
-
-#define DCM_DRP_CTL                     0xFC23
-#define DCM_DRP_TRIG                    0xFC24
-#define DCM_DRP_CFG                     0xFC25
-#define DCM_DRP_WR_DATA_L               0xFC26
-#define DCM_DRP_WR_DATA_H               0xFC27
-#define DCM_DRP_RD_DATA_L               0xFC28
-#define DCM_DRP_RD_DATA_H               0xFC29
-#define SD_VPCLK0_CTL                   0xFC2A
-#define SD_VPCLK1_CTL                   0xFC2B
-#define SD_DCMPS0_CTL                   0xFC2C
-#define SD_DCMPS1_CTL                   0xFC2D
-#define SD_VPTX_CTL                     SD_VPCLK0_CTL
-#define SD_VPRX_CTL                     SD_VPCLK1_CTL
-#define SD_DCMPS_TX_CTL                 SD_DCMPS0_CTL
-#define SD_DCMPS_RX_CTL                 SD_DCMPS1_CTL
-#define CARD_CLK_SOURCE                 0xFC2E
-
-#define CARD_PWR_CTL                    0xFD50
-#define CARD_CLK_SWITCH                 0xFD51
-#define CARD_SHARE_MODE                 0xFD52
-#define CARD_DRIVE_SEL                  0xFD53
-#define CARD_STOP                       0xFD54
-#define CARD_OE                         0xFD55
-#define CARD_AUTO_BLINK                 0xFD56
-#define CARD_GPIO_DIR                   0xFD57
-#define CARD_GPIO                       0xFD58
-#define CARD_DATA_SOURCE                0xFD5B
-#define CARD_SELECT                     0xFD5C
-#define SD30_DRIVE_SEL                  0xFD5E
-#define CARD_CLK_EN                     0xFD69
-#define SDIO_CTRL                       0xFD6B
-#define CD_PAD_CTL                      0xFD73
-
-#define FPDCTL                          0xFC00
-#define PDINFO                          0xFC01
-
-#define CLK_CTL                         0xFC02
-#define CLK_DIV                         0xFC03
-#define CLK_SEL                         0xFC04
-
-#define SSC_DIV_N_0                     0xFC0F
-#define SSC_DIV_N_1                     0xFC10
-#define SSC_CTL1                        0xFC11
-#define SSC_CTL2                        0xFC12
-
-#define RCCTL                           0xFC14
-
-#define FPGA_PULL_CTL                   0xFC1D
-#define OLT_LED_CTL                     0xFC1E
-#define GPIO_CTL                        0xFC1F
-
-#define LDO_CTL                         0xFC1E
-#define SYS_VER                         0xFC32
-
-#define CARD_PULL_CTL1                  0xFD60
-#define CARD_PULL_CTL2                  0xFD61
-#define CARD_PULL_CTL3                  0xFD62
-#define CARD_PULL_CTL4                  0xFD63
-#define CARD_PULL_CTL5                  0xFD64
-#define CARD_PULL_CTL6                  0xFD65
-
-/* PCI Express Related Registers */
-#define IRQEN0                          0xFE20
-#define IRQSTAT0                        0xFE21
-#define IRQEN1                          0xFE22
-#define IRQSTAT1                        0xFE23
-#define TLPRIEN                         0xFE24
-#define TLPRISTAT                       0xFE25
-#define TLPTIEN                         0xFE26
-#define TLPTISTAT                       0xFE27
-#define DMATC0                          0xFE28
-#define DMATC1                          0xFE29
-#define DMATC2                          0xFE2A
-#define DMATC3                          0xFE2B
-#define DMACTL                          0xFE2C
-#define BCTL                            0xFE2D
-#define RBBC0                           0xFE2E
-#define RBBC1                           0xFE2F
-#define RBDAT                           0xFE30
-#define RBCTL                           0xFE34
-#define CFGADDR0                        0xFE35
-#define CFGADDR1                        0xFE36
-#define CFGDATA0                        0xFE37
-#define CFGDATA1                        0xFE38
-#define CFGDATA2                        0xFE39
-#define CFGDATA3                        0xFE3A
-#define CFGRWCTL                        0xFE3B
-#define PHYRWCTL                        0xFE3C
-#define PHYDATA0                        0xFE3D
-#define PHYDATA1                        0xFE3E
-#define PHYADDR                         0xFE3F
-#define MSGRXDATA0                      0xFE40
-#define MSGRXDATA1                      0xFE41
-#define MSGRXDATA2                      0xFE42
-#define MSGRXDATA3                      0xFE43
-#define MSGTXDATA0                      0xFE44
-#define MSGTXDATA1                      0xFE45
-#define MSGTXDATA2                      0xFE46
-#define MSGTXDATA3                      0xFE47
-#define MSGTXCTL                        0xFE48
-#define PETXCFG                         0xFE49
-
-#define CDRESUMECTL                     0xFE52
-#define WAKE_SEL_CTL                    0xFE54
-#define PME_FORCE_CTL                   0xFE56
-#define ASPM_FORCE_CTL                  0xFE57
-#define PM_CLK_FORCE_CTL                0xFE58
-#define PERST_GLITCH_WIDTH              0xFE5C
-#define CHANGE_LINK_STATE               0xFE5B
-#define RESET_LOAD_REG                  0xFE5E
-#define EFUSE_CONTENT                   0xFE5F
-#define HOST_SLEEP_STATE                0xFE60
-#define SDIO_CFG                        0xFE70
-
-#define NFTS_TX_CTRL                    0xFE72
-
-#define PWR_GATE_CTRL                   0xFE75
-#define PWD_SUSPEND_EN                  0xFE76
-#define LDO_PWR_SEL                     0xFE78
-
-#define DUMMY_REG_RESET_0               0xFE90
-
-/* Memory mapping */
-#define SRAM_BASE                       0xE600
-#define RBUF_BASE                       0xF400
-#define PPBUF_BASE1                     0xF800
-#define PPBUF_BASE2                     0xFA00
-#define IMAGE_FLAG_ADDR0                0xCE80
-#define IMAGE_FLAG_ADDR1                0xCE81
-
-#define rtsx_pci_init_cmd(pcr)          ((pcr)->ci = 0)
-
-struct rtsx_pcr;
-
-struct pcr_handle {
-        struct rtsx_pcr                 *pcr;
-};
-
-struct pcr_ops {
-        int             (*extra_init_hw)(struct rtsx_pcr *pcr);
-        int             (*optimize_phy)(struct rtsx_pcr *pcr);
-        int             (*turn_on_led)(struct rtsx_pcr *pcr);
-        int             (*turn_off_led)(struct rtsx_pcr *pcr);
-        int             (*enable_auto_blink)(struct rtsx_pcr *pcr);
-        int             (*disable_auto_blink)(struct rtsx_pcr *pcr);
-        int             (*card_power_on)(struct rtsx_pcr *pcr, int card);
-        int             (*card_power_off)(struct rtsx_pcr *pcr, int card);
-        unsigned int    (*cd_deglitch)(struct rtsx_pcr *pcr);
-};
-
-enum PDEV_STAT  {PDEV_STAT_IDLE, PDEV_STAT_RUN};
-
-struct rtsx_pcr {
-        struct pci_dev                  *pci;
-        unsigned int                    id;
-
-        /* pci resources */
-        unsigned long                   addr;
-        void __iomem                    *remap_addr;
-        int                             irq;
-
-        /* host reserved buffer */
-        void                            *rtsx_resv_buf;
-        dma_addr_t                      rtsx_resv_buf_addr;
-
-        void                            *host_cmds_ptr;
-        dma_addr_t                      host_cmds_addr;
-        int                             ci;
-
-        void                            *host_sg_tbl_ptr;
-        dma_addr_t                      host_sg_tbl_addr;
-        int                             sgi;
-
-        u32                             bier;
-        char                            trans_result;
-
-        unsigned int                    card_inserted;
-        unsigned int                    card_removed;
-
-        struct delayed_work             carddet_work;
-        struct delayed_work             idle_work;
-
-        spinlock_t                      lock;
-        struct mutex                    pcr_mutex;
-        struct completion               *done;
-        struct completion               *finish_me;
-
-        unsigned int                    cur_clock;
-        bool                            ms_pmos;
-        bool                            remove_pci;
-        bool                            msi_en;
-
-#define EXTRA_CAPS_SD_SDR50             (1 << 0)
-#define EXTRA_CAPS_SD_SDR104            (1 << 1)
-#define EXTRA_CAPS_SD_DDR50             (1 << 2)
-#define EXTRA_CAPS_MMC_HSDDR            (1 << 3)
-#define EXTRA_CAPS_MMC_HS200            (1 << 4)
-#define EXTRA_CAPS_MMC_8BIT             (1 << 5)
-        u32                             extra_caps;
-
-#define IC_VER_A                        0
-#define IC_VER_B                        1
-#define IC_VER_C                        2
-#define IC_VER_D                        3
-        u8                              ic_version;
-
-        const u32                       *sd_pull_ctl_enable_tbl;
-        const u32                       *sd_pull_ctl_disable_tbl;
-        const u32                       *ms_pull_ctl_enable_tbl;
-        const u32                       *ms_pull_ctl_disable_tbl;
-
-        const struct pcr_ops            *ops;
-        enum PDEV_STAT                  state;
-
-        int                             num_slots;
-        struct rtsx_slot                *slots;
-};
-
-#define CHK_PCI_PID(pcr, pid)           ((pcr)->pci->device == (pid))
-#define PCI_VID(pcr)                    ((pcr)->pci->vendor)
-#define PCI_PID(pcr)                    ((pcr)->pci->device)
-
-void rtsx_pci_start_run(struct rtsx_pcr *pcr);
-int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
-int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
-int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
-int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
-void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
-void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
-                u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
-void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
-int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
-int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
-                int num_sg, bool read, int timeout);
-int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
-int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
-int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
-int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
-int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
-                u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
-int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
-int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
-unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
-void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
-
-static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
-{
-        return (u8 *)(pcr->host_cmds_ptr);
-}
-
-#endif
diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h
deleted file mode 100644
index b50c38f8bc4..00000000000
--- a/include/linux/mfd/samsung/core.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * core.h
- *
- * copyright (c) 2011 Samsung Electronics Co., Ltd
- *              http://www.samsung.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __LINUX_MFD_SEC_CORE_H
-#define __LINUX_MFD_SEC_CORE_H
-
-#define NUM_IRQ_REGS    4
-
-enum sec_device_type {
-        S5M8751X,
-        S5M8763X,
-        S5M8767X,
-        S2MPS11X,
-};
-
-/**
- * struct sec_pmic_dev - s5m87xx master device for sub-drivers
- * @dev: master device of the chip (can be used to access platform data)
- * @i2c: i2c client private data for regulator
- * @rtc: i2c client private data for rtc
- * @iolock: mutex for serializing io access
- * @irqlock: mutex for buslock
- * @irq_base: base IRQ number for sec-pmic, required for IRQs
- * @irq: generic IRQ number for s5m87xx
- * @ono: power onoff IRQ number for s5m87xx
- * @irq_masks_cur: currently active value
- * @irq_masks_cache: cached hardware value
- * @type: indicate which s5m87xx "variant" is used
- */
-struct sec_pmic_dev {
-        struct device *dev;
-        struct regmap *regmap;
-        struct i2c_client *i2c;
-        struct i2c_client *rtc;
-        struct mutex iolock;
-        struct mutex irqlock;
-
-        int device_type;
-        int irq_base;
-        int irq;
-        struct regmap_irq_chip_data *irq_data;
-
-        int ono;
-        u8 irq_masks_cur[NUM_IRQ_REGS];
-        u8 irq_masks_cache[NUM_IRQ_REGS];
-        int type;
-        bool wakeup;
-};
-
-int sec_irq_init(struct sec_pmic_dev *sec_pmic);
-void sec_irq_exit(struct sec_pmic_dev *sec_pmic);
-int sec_irq_resume(struct sec_pmic_dev *sec_pmic);
-
-extern int sec_reg_read(struct sec_pmic_dev *sec_pmic, u8 reg, void *dest);
-extern int sec_bulk_read(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf);
-extern int sec_reg_write(struct sec_pmic_dev *sec_pmic, u8 reg, u8 value);
-extern int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf);
-extern int sec_reg_update(struct sec_pmic_dev *sec_pmic, u8 reg, u8 val, u8 mask);
-
-struct sec_platform_data {
-        struct sec_regulator_data       *regulators;
-        struct sec_opmode_data          *opmode;
-        int                             device_type;
-        int                             num_regulators;
-
-        int                             irq_base;
-        int                             (*cfg_pmic_irq)(void);
-
-        int                             ono;
-        bool                            wakeup;
-        bool                            buck_voltage_lock;
-
-        int                             buck_gpios[3];
-        int                             buck_ds[3];
-        int                             buck2_voltage[8];
-        bool                            buck2_gpiodvs;
-        int                             buck3_voltage[8];
-        bool                            buck3_gpiodvs;
-        int                             buck4_voltage[8];
-        bool                            buck4_gpiodvs;
-
-        int                             buck_set1;
-        int                             buck_set2;
-        int                             buck_set3;
-        int                             buck2_enable;
-        int                             buck3_enable;
-        int                             buck4_enable;
-        int                             buck_default_idx;
-        int                             buck2_default_idx;
-        int                             buck3_default_idx;
-        int                             buck4_default_idx;
-
-        int                             buck_ramp_delay;
-
-        int                             buck2_ramp_delay;
-        int                             buck34_ramp_delay;
-        int                             buck5_ramp_delay;
-        int                             buck16_ramp_delay;
-        int                             buck7810_ramp_delay;
-        int                             buck9_ramp_delay;
-
-        bool                            buck2_ramp_enable;
-        bool                            buck3_ramp_enable;
-        bool                            buck4_ramp_enable;
-        bool                            buck6_ramp_enable;
-
-        int                             buck2_init;
-        int                             buck3_init;
-        int                             buck4_init;
-};
-
-/**
- * sec_regulator_data - regulator data
- * @id: regulator id
- * @initdata: regulator init data (contraints, supplies, ...)
- */
-struct sec_regulator_data {
-        int                             id;
-        struct regulator_init_data      *initdata;
-};
-
-/*
- * sec_opmode_data - regulator operation mode data
- * @id: regulator id
- * @mode: regulator operation mode
- */
-struct sec_opmode_data {
-        int id;
-        int mode;
-};
-
-/*
- * samsung regulator operation mode
- * SEC_OPMODE_OFF       Regulator always OFF
- * SEC_OPMODE_ON        Regulator always ON
- * SEC_OPMODE_LOWPOWER  Regulator is on in low-power mode
- * SEC_OPMODE_SUSPEND   Regulator is changed by PWREN pin
- *                      If PWREN is high, regulator is on
- *                      If PWREN is low, regulator is off
- */
-
-enum sec_opmode {
-        SEC_OPMODE_OFF,
-        SEC_OPMODE_ON,
-        SEC_OPMODE_LOWPOWER,
-        SEC_OPMODE_SUSPEND,
-};
-
-#endif /*  __LINUX_MFD_SEC_CORE_H */
diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/irq.h
deleted file mode 100644
index d43b4f9e7fb..00000000000
--- a/include/linux/mfd/samsung/irq.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/* irq.h
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd
- *              http://www.samsung.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __LINUX_MFD_SEC_IRQ_H
-#define __LINUX_MFD_SEC_IRQ_H
-
-enum s2mps11_irq {
-        S2MPS11_IRQ_PWRONF,
-        S2MPS11_IRQ_PWRONR,
-        S2MPS11_IRQ_JIGONBF,
-        S2MPS11_IRQ_JIGONBR,
-        S2MPS11_IRQ_ACOKBF,
-        S2MPS11_IRQ_ACOKBR,
-        S2MPS11_IRQ_PWRON1S,
-        S2MPS11_IRQ_MRB,
-
-        S2MPS11_IRQ_RTC60S,
-        S2MPS11_IRQ_RTCA1,
-        S2MPS11_IRQ_RTCA2,
-        S2MPS11_IRQ_SMPL,
-        S2MPS11_IRQ_RTC1S,
-        S2MPS11_IRQ_WTSR,
-
-        S2MPS11_IRQ_INT120C,
-        S2MPS11_IRQ_INT140C,
-
-        S2MPS11_IRQ_NR,
-};
-
-#define S2MPS11_IRQ_PWRONF_MASK         (1 << 0)
-#define S2MPS11_IRQ_PWRONR_MASK         (1 << 1)
-#define S2MPS11_IRQ_JIGONBF_MASK        (1 << 2)
-#define S2MPS11_IRQ_JIGONBR_MASK        (1 << 3)
-#define S2MPS11_IRQ_ACOKBF_MASK         (1 << 4)
-#define S2MPS11_IRQ_ACOKBR_MASK         (1 << 5)
-#define S2MPS11_IRQ_PWRON1S_MASK        (1 << 6)
-#define S2MPS11_IRQ_MRB_MASK            (1 << 7)
-
-#define S2MPS11_IRQ_RTC60S_MASK         (1 << 0)
-#define S2MPS11_IRQ_RTCA1_MASK          (1 << 1)
-#define S2MPS11_IRQ_RTCA2_MASK          (1 << 2)
-#define S2MPS11_IRQ_SMPL_MASK           (1 << 3)
-#define S2MPS11_IRQ_RTC1S_MASK          (1 << 4)
-#define S2MPS11_IRQ_WTSR_MASK           (1 << 5)
-
-#define S2MPS11_IRQ_INT120C_MASK        (1 << 0)
-#define S2MPS11_IRQ_INT140C_MASK        (1 << 1)
-
-enum s5m8767_irq {
-        S5M8767_IRQ_PWRR,
-        S5M8767_IRQ_PWRF,
-        S5M8767_IRQ_PWR1S,
-        S5M8767_IRQ_JIGR,
-        S5M8767_IRQ_JIGF,
-        S5M8767_IRQ_LOWBAT2,
-        S5M8767_IRQ_LOWBAT1,
-
-        S5M8767_IRQ_MRB,
-        S5M8767_IRQ_DVSOK2,
-        S5M8767_IRQ_DVSOK3,
-        S5M8767_IRQ_DVSOK4,
-
-        S5M8767_IRQ_RTC60S,
-        S5M8767_IRQ_RTCA1,
-        S5M8767_IRQ_RTCA2,
-        S5M8767_IRQ_SMPL,
-        S5M8767_IRQ_RTC1S,
-        S5M8767_IRQ_WTSR,
-
-        S5M8767_IRQ_NR,
-};
-
-#define S5M8767_IRQ_PWRR_MASK           (1 << 0)
-#define S5M8767_IRQ_PWRF_MASK           (1 << 1)
-#define S5M8767_IRQ_PWR1S_MASK          (1 << 3)
-#define S5M8767_IRQ_JIGR_MASK           (1 << 4)
-#define S5M8767_IRQ_JIGF_MASK           (1 << 5)
-#define S5M8767_IRQ_LOWBAT2_MASK        (1 << 6)
-#define S5M8767_IRQ_LOWBAT1_MASK        (1 << 7)
-
-#define S5M8767_IRQ_MRB_MASK            (1 << 2)
-#define S5M8767_IRQ_DVSOK2_MASK         (1 << 3)
-#define S5M8767_IRQ_DVSOK3_MASK         (1 << 4)
-#define S5M8767_IRQ_DVSOK4_MASK         (1 << 5)
-
-#define S5M8767_IRQ_RTC60S_MASK         (1 << 0)
-#define S5M8767_IRQ_RTCA1_MASK          (1 << 1)
-#define S5M8767_IRQ_RTCA2_MASK          (1 << 2)
-#define S5M8767_IRQ_SMPL_MASK           (1 << 3)
-#define S5M8767_IRQ_RTC1S_MASK          (1 << 4)
-#define S5M8767_IRQ_WTSR_MASK           (1 << 5)
-
-enum s5m8763_irq {
-        S5M8763_IRQ_DCINF,
-        S5M8763_IRQ_DCINR,
-        S5M8763_IRQ_JIGF,
-        S5M8763_IRQ_JIGR,
-        S5M8763_IRQ_PWRONF,
-        S5M8763_IRQ_PWRONR,
-
-        S5M8763_IRQ_WTSREVNT,
-        S5M8763_IRQ_SMPLEVNT,
-        S5M8763_IRQ_ALARM1,
-        S5M8763_IRQ_ALARM0,
-
-        S5M8763_IRQ_ONKEY1S,
-        S5M8763_IRQ_TOPOFFR,
-        S5M8763_IRQ_DCINOVPR,
-        S5M8763_IRQ_CHGRSTF,
-        S5M8763_IRQ_DONER,
-        S5M8763_IRQ_CHGFAULT,
-
-        S5M8763_IRQ_LOBAT1,
-        S5M8763_IRQ_LOBAT2,
-
-        S5M8763_IRQ_NR,
-};
-
-#define S5M8763_IRQ_DCINF_MASK          (1 << 2)
-#define S5M8763_IRQ_DCINR_MASK          (1 << 3)
-#define S5M8763_IRQ_JIGF_MASK           (1 << 4)
-#define S5M8763_IRQ_JIGR_MASK           (1 << 5)
-#define S5M8763_IRQ_PWRONF_MASK         (1 << 6)
-#define S5M8763_IRQ_PWRONR_MASK         (1 << 7)
-
-#define S5M8763_IRQ_WTSREVNT_MASK       (1 << 0)
-#define S5M8763_IRQ_SMPLEVNT_MASK       (1 << 1)
-#define S5M8763_IRQ_ALARM1_MASK         (1 << 2)
-#define S5M8763_IRQ_ALARM0_MASK         (1 << 3)
-
-#define S5M8763_IRQ_ONKEY1S_MASK        (1 << 0)
-#define S5M8763_IRQ_TOPOFFR_MASK        (1 << 2)
-#define S5M8763_IRQ_DCINOVPR_MASK       (1 << 3)
-#define S5M8763_IRQ_CHGRSTF_MASK        (1 << 4)
-#define S5M8763_IRQ_DONER_MASK          (1 << 5)
-#define S5M8763_IRQ_CHGFAULT_MASK       (1 << 7)
-
-#define S5M8763_IRQ_LOBAT1_MASK         (1 << 0)
-#define S5M8763_IRQ_LOBAT2_MASK         (1 << 1)
-
-#define S5M8763_ENRAMP                  (1 << 4)
-
-#endif /*  __LINUX_MFD_SEC_IRQ_H */
diff --git a/include/linux/mfd/samsung/rtc.h b/include/linux/mfd/samsung/rtc.h
deleted file mode 100644
index 71597e20cdd..00000000000
--- a/include/linux/mfd/samsung/rtc.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*  rtc.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd
- *              http://www.samsung.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __LINUX_MFD_SEC_RTC_H
-#define __LINUX_MFD_SEC_RTC_H
-
-enum sec_rtc_reg {
-        SEC_RTC_SEC,
-        SEC_RTC_MIN,
-        SEC_RTC_HOUR,
-        SEC_RTC_WEEKDAY,
-        SEC_RTC_DATE,
-        SEC_RTC_MONTH,
-        SEC_RTC_YEAR1,
-        SEC_RTC_YEAR2,
-        SEC_ALARM0_SEC,
-        SEC_ALARM0_MIN,
-        SEC_ALARM0_HOUR,
-        SEC_ALARM0_WEEKDAY,
-        SEC_ALARM0_DATE,
-        SEC_ALARM0_MONTH,
-        SEC_ALARM0_YEAR1,
-        SEC_ALARM0_YEAR2,
-        SEC_ALARM1_SEC,
-        SEC_ALARM1_MIN,
-        SEC_ALARM1_HOUR,
-        SEC_ALARM1_WEEKDAY,
-        SEC_ALARM1_DATE,
-        SEC_ALARM1_MONTH,
-        SEC_ALARM1_YEAR1,
-        SEC_ALARM1_YEAR2,
-        SEC_ALARM0_CONF,
-        SEC_ALARM1_CONF,
-        SEC_RTC_STATUS,
-        SEC_WTSR_SMPL_CNTL,
-        SEC_RTC_UDR_CON,
-};
-
-#define RTC_I2C_ADDR            (0x0C >> 1)
-
-#define HOUR_12                 (1 << 7)
-#define HOUR_AMPM               (1 << 6)
-#define HOUR_PM                 (1 << 5)
-#define ALARM0_STATUS           (1 << 1)
-#define ALARM1_STATUS           (1 << 2)
-#define UPDATE_AD               (1 << 0)
-
-/* RTC Control Register */
-#define BCD_EN_SHIFT            0
-#define BCD_EN_MASK             (1 << BCD_EN_SHIFT)
-#define MODEL24_SHIFT           1
-#define MODEL24_MASK            (1 << MODEL24_SHIFT)
-/* RTC Update Register1 */
-#define RTC_UDR_SHIFT           0
-#define RTC_UDR_MASK            (1 << RTC_UDR_SHIFT)
-/* RTC Hour register */
-#define HOUR_PM_SHIFT           6
-#define HOUR_PM_MASK            (1 << HOUR_PM_SHIFT)
-/* RTC Alarm Enable */
-#define ALARM_ENABLE_SHIFT      7
-#define ALARM_ENABLE_MASK       (1 << ALARM_ENABLE_SHIFT)
-
-enum {
-        RTC_SEC = 0,
-        RTC_MIN,
-        RTC_HOUR,
-        RTC_WEEKDAY,
-        RTC_DATE,
-        RTC_MONTH,
-        RTC_YEAR1,
-        RTC_YEAR2,
-};
-
-#endif /*  __LINUX_MFD_SEC_RTC_H */
diff --git a/include/linux/mfd/samsung/s2mps11.h b/include/linux/mfd/samsung/s2mps11.h
deleted file mode 100644
index ad2252f239d..00000000000
--- a/include/linux/mfd/samsung/s2mps11.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * s2mps11.h
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd
- *              http://www.samsung.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __LINUX_MFD_S2MPS11_H
-#define __LINUX_MFD_S2MPS11_H
-
-/* S2MPS11 registers */
-enum s2mps11_reg {
-        S2MPS11_REG_ID,
-        S2MPS11_REG_INT1,
-        S2MPS11_REG_INT2,
-        S2MPS11_REG_INT3,
-        S2MPS11_REG_INT1M,
-        S2MPS11_REG_INT2M,
-        S2MPS11_REG_INT3M,
-        S2MPS11_REG_ST1,
-        S2MPS11_REG_ST2,
-        S2MPS11_REG_OFFSRC,
-        S2MPS11_REG_PWRONSRC,
-        S2MPS11_REG_RTC_CTRL,
-        S2MPS11_REG_CTRL1,
-        S2MPS11_REG_ETC_TEST,
-        S2MPS11_REG_RSVD3,
-        S2MPS11_REG_BU_CHG,
-        S2MPS11_REG_RAMP,
-        S2MPS11_REG_RAMP_BUCK,
-        S2MPS11_REG_LDO1_8,
-        S2MPS11_REG_LDO9_16,
-        S2MPS11_REG_LDO17_24,
-        S2MPS11_REG_LDO25_32,
-        S2MPS11_REG_LDO33_38,
-        S2MPS11_REG_LDO1_8_1,
-        S2MPS11_REG_LDO9_16_1,
-        S2MPS11_REG_LDO17_24_1,
-        S2MPS11_REG_LDO25_32_1,
-        S2MPS11_REG_LDO33_38_1,
-        S2MPS11_REG_OTP_ADRL,
-        S2MPS11_REG_OTP_ADRH,
-        S2MPS11_REG_OTP_DATA,
-        S2MPS11_REG_MON1SEL,
-        S2MPS11_REG_MON2SEL,
-        S2MPS11_REG_LEE,
-        S2MPS11_REG_RSVD_NO,
-        S2MPS11_REG_UVLO,
-        S2MPS11_REG_LEE_NO,
-        S2MPS11_REG_B1CTRL1,
-        S2MPS11_REG_B1CTRL2,
-        S2MPS11_REG_B2CTRL1,
-        S2MPS11_REG_B2CTRL2,
-        S2MPS11_REG_B3CTRL1,
-        S2MPS11_REG_B3CTRL2,
-        S2MPS11_REG_B4CTRL1,
-        S2MPS11_REG_B4CTRL2,
-        S2MPS11_REG_B5CTRL1,
-        S2MPS11_REG_BUCK5_SW,
-        S2MPS11_REG_B5CTRL2,
-        S2MPS11_REG_B5CTRL3,
-        S2MPS11_REG_B5CTRL4,
-        S2MPS11_REG_B5CTRL5,
-        S2MPS11_REG_B6CTRL1,
-        S2MPS11_REG_B6CTRL2,
-        S2MPS11_REG_B7CTRL1,
-        S2MPS11_REG_B7CTRL2,
-        S2MPS11_REG_B8CTRL1,
-        S2MPS11_REG_B8CTRL2,
-        S2MPS11_REG_B9CTRL1,
-        S2MPS11_REG_B9CTRL2,
-        S2MPS11_REG_B10CTRL1,
-        S2MPS11_REG_B10CTRL2,
-        S2MPS11_REG_L1CTRL,
-        S2MPS11_REG_L2CTRL,
-        S2MPS11_REG_L3CTRL,
-        S2MPS11_REG_L4CTRL,
-        S2MPS11_REG_L5CTRL,
-        S2MPS11_REG_L6CTRL,
-        S2MPS11_REG_L7CTRL,
-        S2MPS11_REG_L8CTRL,
-        S2MPS11_REG_L9CTRL,
-        S2MPS11_REG_L10CTRL,
-        S2MPS11_REG_L11CTRL,
-        S2MPS11_REG_L12CTRL,
-        S2MPS11_REG_L13CTRL,
-        S2MPS11_REG_L14CTRL,
-        S2MPS11_REG_L15CTRL,
-        S2MPS11_REG_L16CTRL,
-        S2MPS11_REG_L17CTRL,
-        S2MPS11_REG_L18CTRL,
-        S2MPS11_REG_L19CTRL,
-        S2MPS11_REG_L20CTRL,
-        S2MPS11_REG_L21CTRL,
-        S2MPS11_REG_L22CTRL,
-        S2MPS11_REG_L23CTRL,
-        S2MPS11_REG_L24CTRL,
-        S2MPS11_REG_L25CTRL,
-        S2MPS11_REG_L26CTRL,
-        S2MPS11_REG_L27CTRL,
-        S2MPS11_REG_L28CTRL,
-        S2MPS11_REG_L29CTRL,
-        S2MPS11_REG_L30CTRL,
-        S2MPS11_REG_L31CTRL,
-        S2MPS11_REG_L32CTRL,
-        S2MPS11_REG_L33CTRL,
-        S2MPS11_REG_L34CTRL,
-        S2MPS11_REG_L35CTRL,
-        S2MPS11_REG_L36CTRL,
-        S2MPS11_REG_L37CTRL,
-        S2MPS11_REG_L38CTRL,
-};
-
-/* S2MPS11 regulator ids */
-enum s2mps11_regulators {
-        S2MPS11_LDO1,
-        S2MPS11_LDO2,
-        S2MPS11_LDO3,
-        S2MPS11_LDO4,
-        S2MPS11_LDO5,
-        S2MPS11_LDO6,
-        S2MPS11_LDO7,
-        S2MPS11_LDO8,
-        S2MPS11_LDO9,
-        S2MPS11_LDO10,
-        S2MPS11_LDO11,
-        S2MPS11_LDO12,
-        S2MPS11_LDO13,
-        S2MPS11_LDO14,
-        S2MPS11_LDO15,
-        S2MPS11_LDO16,
-        S2MPS11_LDO17,
-        S2MPS11_LDO18,
-        S2MPS11_LDO19,
-        S2MPS11_LDO20,
-        S2MPS11_LDO21,
-        S2MPS11_LDO22,
-        S2MPS11_LDO23,
-        S2MPS11_LDO24,
-        S2MPS11_LDO25,
-        S2MPS11_LDO26,
-        S2MPS11_LDO27,
-        S2MPS11_LDO28,
-        S2MPS11_LDO29,
-        S2MPS11_LDO30,
-        S2MPS11_LDO31,
-        S2MPS11_LDO32,
-        S2MPS11_LDO33,
-        S2MPS11_LDO34,
-        S2MPS11_LDO35,
-        S2MPS11_LDO36,
-        S2MPS11_LDO37,
-        S2MPS11_LDO38,
-        S2MPS11_BUCK1,
-        S2MPS11_BUCK2,
-        S2MPS11_BUCK3,
-        S2MPS11_BUCK4,
-        S2MPS11_BUCK5,
-        S2MPS11_BUCK6,
-        S2MPS11_BUCK7,
-        S2MPS11_BUCK8,
-        S2MPS11_BUCK9,
-        S2MPS11_BUCK10,
-        S2MPS11_AP_EN32KHZ,
-        S2MPS11_CP_EN32KHZ,
-        S2MPS11_BT_EN32KHZ,
-
-        S2MPS11_REG_MAX,
-};
-
-#define S2MPS11_BUCK_MIN1       600000
-#define S2MPS11_BUCK_MIN2       750000
-#define S2MPS11_BUCK_MIN3       3000000
-#define S2MPS11_LDO_MIN 800000
-#define S2MPS11_BUCK_STEP1      6250
-#define S2MPS11_BUCK_STEP2      12500
-#define S2MPS11_BUCK_STEP3      25000
-#define S2MPS11_LDO_STEP1       50000
-#define S2MPS11_LDO_STEP2       25000
-#define S2MPS11_LDO_VSEL_MASK   0x3F
-#define S2MPS11_BUCK_VSEL_MASK  0xFF
-#define S2MPS11_ENABLE_MASK     (0x03 << S2MPS11_ENABLE_SHIFT)
-#define S2MPS11_ENABLE_SHIFT    0x06
-#define S2MPS11_LDO_N_VOLTAGES  (S2MPS11_LDO_VSEL_MASK + 1)
-#define S2MPS11_BUCK_N_VOLTAGES (S2MPS11_BUCK_VSEL_MASK + 1)
-
-#define S2MPS11_PMIC_EN_SHIFT   6
-#define S2MPS11_REGULATOR_MAX (S2MPS11_REG_MAX - 3)
-
-#endif /*  __LINUX_MFD_S2MPS11_H */
diff --git a/include/linux/mfd/samsung/s5m8763.h b/include/linux/mfd/samsung/s5m8763.h
deleted file mode 100644
index e025418e558..00000000000
--- a/include/linux/mfd/samsung/s5m8763.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*  s5m8763.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd
- *              http://www.samsung.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __LINUX_MFD_S5M8763_H
-#define __LINUX_MFD_S5M8763_H
-
-/* S5M8763 registers */
-enum s5m8763_reg {
-        S5M8763_REG_IRQ1,
-        S5M8763_REG_IRQ2,
-        S5M8763_REG_IRQ3,
-        S5M8763_REG_IRQ4,
-        S5M8763_REG_IRQM1,
-        S5M8763_REG_IRQM2,
-        S5M8763_REG_IRQM3,
-        S5M8763_REG_IRQM4,
-        S5M8763_REG_STATUS1,
-        S5M8763_REG_STATUS2,
-        S5M8763_REG_STATUSM1,
-        S5M8763_REG_STATUSM2,
-        S5M8763_REG_CHGR1,
-        S5M8763_REG_CHGR2,
-        S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
-        S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
-        S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
-        S5M8763_REG_ONOFF1,
-        S5M8763_REG_ONOFF2,
-        S5M8763_REG_ONOFF3,
-        S5M8763_REG_ONOFF4,
-        S5M8763_REG_BUCK1_VOLTAGE1,
-        S5M8763_REG_BUCK1_VOLTAGE2,
-        S5M8763_REG_BUCK1_VOLTAGE3,
-        S5M8763_REG_BUCK1_VOLTAGE4,
-        S5M8763_REG_BUCK2_VOLTAGE1,
-        S5M8763_REG_BUCK2_VOLTAGE2,
-        S5M8763_REG_BUCK3,
-        S5M8763_REG_BUCK4,
-        S5M8763_REG_LDO1_LDO2,
-        S5M8763_REG_LDO3,
-        S5M8763_REG_LDO4,
-        S5M8763_REG_LDO5,
-        S5M8763_REG_LDO6,
-        S5M8763_REG_LDO7,
-        S5M8763_REG_LDO7_LDO8,
-        S5M8763_REG_LDO9_LDO10,
-        S5M8763_REG_LDO11,
-        S5M8763_REG_LDO12,
-        S5M8763_REG_LDO13,
-        S5M8763_REG_LDO14,
-        S5M8763_REG_LDO15,
-        S5M8763_REG_LDO16,
-        S5M8763_REG_BKCHR,
-        S5M8763_REG_LBCNFG1,
-        S5M8763_REG_LBCNFG2,
-};
-
-/* S5M8763 regulator ids */
-enum s5m8763_regulators {
-        S5M8763_LDO1,
-        S5M8763_LDO2,
-        S5M8763_LDO3,
-        S5M8763_LDO4,
-        S5M8763_LDO5,
-        S5M8763_LDO6,
-        S5M8763_LDO7,
-        S5M8763_LDO8,
-        S5M8763_LDO9,
-        S5M8763_LDO10,
-        S5M8763_LDO11,
-        S5M8763_LDO12,
-        S5M8763_LDO13,
-        S5M8763_LDO14,
-        S5M8763_LDO15,
-        S5M8763_LDO16,
-        S5M8763_BUCK1,
-        S5M8763_BUCK2,
-        S5M8763_BUCK3,
-        S5M8763_BUCK4,
-        S5M8763_AP_EN32KHZ,
-        S5M8763_CP_EN32KHZ,
-        S5M8763_ENCHGVI,
-        S5M8763_ESAFEUSB1,
-        S5M8763_ESAFEUSB2,
-};
-
-#define S5M8763_ENRAMP                  (1 << 4)
-#endif /* __LINUX_MFD_S5M8763_H */
diff --git a/include/linux/mfd/samsung/s5m8767.h b/include/linux/mfd/samsung/s5m8767.h
deleted file mode 100644
index 306a95fc558..00000000000
--- a/include/linux/mfd/samsung/s5m8767.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*  s5m8767.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd
- *              http://www.samsung.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __LINUX_MFD_S5M8767_H
-#define __LINUX_MFD_S5M8767_H
-
-/* S5M8767 registers */
-enum s5m8767_reg {
-        S5M8767_REG_ID,
-        S5M8767_REG_INT1,
-        S5M8767_REG_INT2,
-        S5M8767_REG_INT3,
-        S5M8767_REG_INT1M,
-        S5M8767_REG_INT2M,
-        S5M8767_REG_INT3M,
-        S5M8767_REG_STATUS1,
-        S5M8767_REG_STATUS2,
-        S5M8767_REG_STATUS3,
-        S5M8767_REG_CTRL1,
-        S5M8767_REG_CTRL2,
-        S5M8767_REG_LOWBAT1,
-        S5M8767_REG_LOWBAT2,
-        S5M8767_REG_BUCHG,
-        S5M8767_REG_DVSRAMP,
-        S5M8767_REG_DVSTIMER2 = 0x10,
-        S5M8767_REG_DVSTIMER3,
-        S5M8767_REG_DVSTIMER4,
-        S5M8767_REG_LDO1,
-        S5M8767_REG_LDO2,
-        S5M8767_REG_LDO3,
-        S5M8767_REG_LDO4,
-        S5M8767_REG_LDO5,
-        S5M8767_REG_LDO6,
-        S5M8767_REG_LDO7,
-        S5M8767_REG_LDO8,
-        S5M8767_REG_LDO9,
-        S5M8767_REG_LDO10,
-        S5M8767_REG_LDO11,
-        S5M8767_REG_LDO12,
-        S5M8767_REG_LDO13,
-        S5M8767_REG_LDO14 = 0x20,
-        S5M8767_REG_LDO15,
-        S5M8767_REG_LDO16,
-        S5M8767_REG_LDO17,
-        S5M8767_REG_LDO18,
-        S5M8767_REG_LDO19,
-        S5M8767_REG_LDO20,
-        S5M8767_REG_LDO21,
-        S5M8767_REG_LDO22,
-        S5M8767_REG_LDO23,
-        S5M8767_REG_LDO24,
-        S5M8767_REG_LDO25,
-        S5M8767_REG_LDO26,
-        S5M8767_REG_LDO27,
-        S5M8767_REG_LDO28,
-        S5M8767_REG_UVLO = 0x31,
-        S5M8767_REG_BUCK1CTRL1,
-        S5M8767_REG_BUCK1CTRL2,
-        S5M8767_REG_BUCK2CTRL,
-        S5M8767_REG_BUCK2DVS1,
-        S5M8767_REG_BUCK2DVS2,
-        S5M8767_REG_BUCK2DVS3,
-        S5M8767_REG_BUCK2DVS4,
-        S5M8767_REG_BUCK2DVS5,
-        S5M8767_REG_BUCK2DVS6,
-        S5M8767_REG_BUCK2DVS7,
-        S5M8767_REG_BUCK2DVS8,
-        S5M8767_REG_BUCK3CTRL,
-        S5M8767_REG_BUCK3DVS1,
-        S5M8767_REG_BUCK3DVS2,
-        S5M8767_REG_BUCK3DVS3,
-        S5M8767_REG_BUCK3DVS4,
-        S5M8767_REG_BUCK3DVS5,
-        S5M8767_REG_BUCK3DVS6,
-        S5M8767_REG_BUCK3DVS7,
-        S5M8767_REG_BUCK3DVS8,
-        S5M8767_REG_BUCK4CTRL,
-        S5M8767_REG_BUCK4DVS1,
-        S5M8767_REG_BUCK4DVS2,
-        S5M8767_REG_BUCK4DVS3,
-        S5M8767_REG_BUCK4DVS4,
-        S5M8767_REG_BUCK4DVS5,
-        S5M8767_REG_BUCK4DVS6,
-        S5M8767_REG_BUCK4DVS7,
-        S5M8767_REG_BUCK4DVS8,
-        S5M8767_REG_BUCK5CTRL1,
-        S5M8767_REG_BUCK5CTRL2,
-        S5M8767_REG_BUCK5CTRL3,
-        S5M8767_REG_BUCK5CTRL4,
-        S5M8767_REG_BUCK5CTRL5,
-        S5M8767_REG_BUCK6CTRL1,
-        S5M8767_REG_BUCK6CTRL2,
-        S5M8767_REG_BUCK7CTRL1,
-        S5M8767_REG_BUCK7CTRL2,
-        S5M8767_REG_BUCK8CTRL1,
-        S5M8767_REG_BUCK8CTRL2,
-        S5M8767_REG_BUCK9CTRL1,
-        S5M8767_REG_BUCK9CTRL2,
-        S5M8767_REG_LDO1CTRL,
-        S5M8767_REG_LDO2_1CTRL,
-        S5M8767_REG_LDO2_2CTRL,
-        S5M8767_REG_LDO2_3CTRL,
-        S5M8767_REG_LDO2_4CTRL,
-        S5M8767_REG_LDO3CTRL,
-        S5M8767_REG_LDO4CTRL,
-        S5M8767_REG_LDO5CTRL,
-        S5M8767_REG_LDO6CTRL,
-        S5M8767_REG_LDO7CTRL,
-        S5M8767_REG_LDO8CTRL,
-        S5M8767_REG_LDO9CTRL,
-        S5M8767_REG_LDO10CTRL,
-        S5M8767_REG_LDO11CTRL,
-        S5M8767_REG_LDO12CTRL,
-        S5M8767_REG_LDO13CTRL,
-        S5M8767_REG_LDO14CTRL,
-        S5M8767_REG_LDO15CTRL,
-        S5M8767_REG_LDO16CTRL,
-        S5M8767_REG_LDO17CTRL,
-        S5M8767_REG_LDO18CTRL,
-        S5M8767_REG_LDO19CTRL,
-        S5M8767_REG_LDO20CTRL,
-        S5M8767_REG_LDO21CTRL,
-        S5M8767_REG_LDO22CTRL,
-        S5M8767_REG_LDO23CTRL,
-        S5M8767_REG_LDO24CTRL,
-        S5M8767_REG_LDO25CTRL,
-        S5M8767_REG_LDO26CTRL,
-        S5M8767_REG_LDO27CTRL,
-        S5M8767_REG_LDO28CTRL,
-};
-
-/* S5M8767 regulator ids */
-enum s5m8767_regulators {
-        S5M8767_LDO1,
-        S5M8767_LDO2,
-        S5M8767_LDO3,
-        S5M8767_LDO4,
-        S5M8767_LDO5,
-        S5M8767_LDO6,
-        S5M8767_LDO7,
-        S5M8767_LDO8,
-        S5M8767_LDO9,
-        S5M8767_LDO10,
-        S5M8767_LDO11,
-        S5M8767_LDO12,
-        S5M8767_LDO13,
-        S5M8767_LDO14,
-        S5M8767_LDO15,
-        S5M8767_LDO16,
-        S5M8767_LDO17,
-        S5M8767_LDO18,
-        S5M8767_LDO19,
-        S5M8767_LDO20,
-        S5M8767_LDO21,
-        S5M8767_LDO22,
-        S5M8767_LDO23,
-        S5M8767_LDO24,
-        S5M8767_LDO25,
-        S5M8767_LDO26,
-        S5M8767_LDO27,
-        S5M8767_LDO28,
-        S5M8767_BUCK1,
-        S5M8767_BUCK2,
-        S5M8767_BUCK3,
-        S5M8767_BUCK4,
-        S5M8767_BUCK5,
-        S5M8767_BUCK6,
-        S5M8767_BUCK7,
-        S5M8767_BUCK8,
-        S5M8767_BUCK9,
-        S5M8767_AP_EN32KHZ,
-        S5M8767_CP_EN32KHZ,
-
-        S5M8767_REG_MAX,
-};
-
-#define S5M8767_ENCTRL_SHIFT  6
-
-#endif /* __LINUX_MFD_S5M8767_H */
diff --git a/include/linux/mfd/smsc.h b/include/linux/mfd/smsc.h
deleted file mode 100644
index 9747b29f356..00000000000
--- a/include/linux/mfd/smsc.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * SMSC ECE1099
- *
- * Copyright 2012 Texas Instruments Inc.
- *
- * Author: Sourav Poddar <sourav.poddar@ti.com>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under  the terms of the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __LINUX_MFD_SMSC_H
-#define __LINUX_MFD_SMSC_H
-
-#include <linux/regmap.h>
-
-#define SMSC_ID_ECE1099                 1
-#define SMSC_NUM_CLIENTS                2
-
-#define SMSC_BASE_ADDR                  0x38
-#define OMAP_GPIO_SMSC_IRQ              151
-
-#define SMSC_MAXGPIO         32
-#define SMSC_BANK(offs)      ((offs) >> 3)
-#define SMSC_BIT(offs)       (1u << ((offs) & 0x7))
-
-struct smsc {
-        struct device *dev;
-        struct i2c_client *i2c_clients[SMSC_NUM_CLIENTS];
-        struct regmap *regmap;
-        int clk;
-        /* Stored chip id */
-        int id;
-};
-
-struct smsc_gpio;
-struct smsc_keypad;
-
-static inline int smsc_read(struct device *child, unsigned int reg,
-        unsigned int *dest)
-{
-        struct smsc     *smsc = dev_get_drvdata(child->parent);
-
-        return regmap_read(smsc->regmap, reg, dest);
-}
-
-static inline int smsc_write(struct device *child, unsigned int reg,
-        unsigned int value)
-{
-        struct smsc     *smsc = dev_get_drvdata(child->parent);
-
-        return regmap_write(smsc->regmap, reg, value);
-}
-
-/* Registers for SMSC */
-#define SMSC_RESET                                              0xF5
-#define SMSC_GRP_INT                                            0xF9
-#define SMSC_CLK_CTRL                                           0xFA
-#define SMSC_WKUP_CTRL                                          0xFB
-#define SMSC_DEV_ID                                             0xFC
-#define SMSC_DEV_REV                                            0xFD
-#define SMSC_VEN_ID_L                                           0xFE
-#define SMSC_VEN_ID_H                                           0xFF
-
-/* CLK VALUE */
-#define SMSC_CLK_VALUE                                          0x13
-
-/* Registers for function GPIO INPUT */
-#define SMSC_GPIO_DATA_IN_START                                 0x00
-
-/* Registers for function GPIO OUPUT */
-#define SMSC_GPIO_DATA_OUT_START                                       0x05
-
-/* Definitions for SMSC GPIO CONFIGURATION REGISTER*/
-#define SMSC_GPIO_INPUT_LOW                                     0x01
-#define SMSC_GPIO_INPUT_RISING                                  0x09
-#define SMSC_GPIO_INPUT_FALLING                                 0x11
-#define SMSC_GPIO_INPUT_BOTH_EDGE                               0x19
-#define SMSC_GPIO_OUTPUT_PP                                     0x21
-#define SMSC_GPIO_OUTPUT_OP                                     0x31
-
-#define GRP_INT_STAT                                            0xf9
-#define SMSC_GPI_INT                                            0x0f
-#define SMSC_CFG_START                                          0x0A
-
-/* Registers for SMSC GPIO INTERRUPT STATUS REGISTER*/
-#define SMSC_GPIO_INT_STAT_START                                  0x32
-
-/* Registers for SMSC GPIO INTERRUPT MASK REGISTER*/
-#define SMSC_GPIO_INT_MASK_START                               0x37
-
-/* Registers for SMSC function KEYPAD*/
-#define SMSC_KP_OUT                                             0x40
-#define SMSC_KP_IN                                              0x41
-#define SMSC_KP_INT_STAT                                        0x42
-#define SMSC_KP_INT_MASK                                        0x43
-
-/* Definitions for keypad */
-#define SMSC_KP_KSO           0x70
-#define SMSC_KP_KSI           0x51
-#define SMSC_KSO_ALL_LOW        0x20
-#define SMSC_KP_SET_LOW_PWR        0x0B
-#define SMSC_KP_SET_HIGH           0xFF
-#define SMSC_KSO_EVAL           0x00
-
-#endif /*  __LINUX_MFD_SMSC_H */
diff --git a/include/linux/mfd/sta2x11-mfd.h b/include/linux/mfd/sta2x11-mfd.h
deleted file mode 100644
index 9a855ac11cb..00000000000
--- a/include/linux/mfd/sta2x11-mfd.h
+++ /dev/null
@@ -1,518 +0,0 @@
-/*
- * Copyright (c) 2009-2011 Wind River Systems, Inc.
- * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * The STMicroelectronics ConneXt (STA2X11) chip has several unrelated
- * functions in one PCI endpoint functions. This driver simply
- * registers the platform devices in this iomemregion and exports a few
- * functions to access common registers
- */
-
-#ifndef __STA2X11_MFD_H
-#define __STA2X11_MFD_H
-#include <linux/types.h>
-#include <linux/pci.h>
-
-enum sta2x11_mfd_plat_dev {
-        sta2x11_sctl = 0,
-        sta2x11_gpio,
-        sta2x11_scr,
-        sta2x11_time,
-        sta2x11_apbreg,
-        sta2x11_apb_soc_regs,
-        sta2x11_vic,
-        sta2x11_n_mfd_plat_devs,
-};
-
-#define STA2X11_MFD_SCTL_NAME          "sta2x11-sctl"
-#define STA2X11_MFD_GPIO_NAME          "sta2x11-gpio"
-#define STA2X11_MFD_SCR_NAME           "sta2x11-scr"
-#define STA2X11_MFD_TIME_NAME          "sta2x11-time"
-#define STA2X11_MFD_APBREG_NAME        "sta2x11-apbreg"
-#define STA2X11_MFD_APB_SOC_REGS_NAME  "sta2x11-apb-soc-regs"
-#define STA2X11_MFD_VIC_NAME           "sta2x11-vic"
-
-extern u32
-__sta2x11_mfd_mask(struct pci_dev *, u32, u32, u32, enum sta2x11_mfd_plat_dev);
-
-/*
- * The MFD PCI block includes the GPIO peripherals and other register blocks.
- * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".)
- */
-#define GSTA_GPIO_PER_BLOCK     32
-#define GSTA_NR_BLOCKS          4
-#define GSTA_NR_GPIO            (GSTA_GPIO_PER_BLOCK * GSTA_NR_BLOCKS)
-
-/* Pinconfig is set by the board definition: altfunc, pull-up, pull-down */
-struct sta2x11_gpio_pdata {
-        unsigned pinconfig[GSTA_NR_GPIO];
-};
-
-/* Macros below lifted from sh_pfc.h, with minor differences */
-#define PINMUX_TYPE_NONE                0
-#define PINMUX_TYPE_FUNCTION            1
-#define PINMUX_TYPE_OUTPUT_LOW          2
-#define PINMUX_TYPE_OUTPUT_HIGH         3
-#define PINMUX_TYPE_INPUT               4
-#define PINMUX_TYPE_INPUT_PULLUP        5
-#define PINMUX_TYPE_INPUT_PULLDOWN      6
-
-/* Give names to GPIO pins, like PXA does, taken from the manual */
-#define STA2X11_GPIO0                   0
-#define STA2X11_GPIO1                   1
-#define STA2X11_GPIO2                   2
-#define STA2X11_GPIO3                   3
-#define STA2X11_GPIO4                   4
-#define STA2X11_GPIO5                   5
-#define STA2X11_GPIO6                   6
-#define STA2X11_GPIO7                   7
-#define STA2X11_GPIO8_RGBOUT_RED7       8
-#define STA2X11_GPIO9_RGBOUT_RED6       9
-#define STA2X11_GPIO10_RGBOUT_RED5      10
-#define STA2X11_GPIO11_RGBOUT_RED4      11
-#define STA2X11_GPIO12_RGBOUT_RED3      12
-#define STA2X11_GPIO13_RGBOUT_RED2      13
-#define STA2X11_GPIO14_RGBOUT_RED1      14
-#define STA2X11_GPIO15_RGBOUT_RED0      15
-#define STA2X11_GPIO16_RGBOUT_GREEN7    16
-#define STA2X11_GPIO17_RGBOUT_GREEN6    17
-#define STA2X11_GPIO18_RGBOUT_GREEN5    18
-#define STA2X11_GPIO19_RGBOUT_GREEN4    19
-#define STA2X11_GPIO20_RGBOUT_GREEN3    20
-#define STA2X11_GPIO21_RGBOUT_GREEN2    21
-#define STA2X11_GPIO22_RGBOUT_GREEN1    22
-#define STA2X11_GPIO23_RGBOUT_GREEN0    23
-#define STA2X11_GPIO24_RGBOUT_BLUE7     24
-#define STA2X11_GPIO25_RGBOUT_BLUE6     25
-#define STA2X11_GPIO26_RGBOUT_BLUE5     26
-#define STA2X11_GPIO27_RGBOUT_BLUE4     27
-#define STA2X11_GPIO28_RGBOUT_BLUE3     28
-#define STA2X11_GPIO29_RGBOUT_BLUE2     29
-#define STA2X11_GPIO30_RGBOUT_BLUE1     30
-#define STA2X11_GPIO31_RGBOUT_BLUE0     31
-#define STA2X11_GPIO32_RGBOUT_VSYNCH    32
-#define STA2X11_GPIO33_RGBOUT_HSYNCH    33
-#define STA2X11_GPIO34_RGBOUT_DEN       34
-#define STA2X11_GPIO35_ETH_CRS_DV       35
-#define STA2X11_GPIO36_ETH_TXD1         36
-#define STA2X11_GPIO37_ETH_TXD0         37
-#define STA2X11_GPIO38_ETH_TX_EN        38
-#define STA2X11_GPIO39_MDIO             39
-#define STA2X11_GPIO40_ETH_REF_CLK      40
-#define STA2X11_GPIO41_ETH_RXD1         41
-#define STA2X11_GPIO42_ETH_RXD0         42
-#define STA2X11_GPIO43_MDC              43
-#define STA2X11_GPIO44_CAN_TX           44
-#define STA2X11_GPIO45_CAN_RX           45
-#define STA2X11_GPIO46_MLB_DAT          46
-#define STA2X11_GPIO47_MLB_SIG          47
-#define STA2X11_GPIO48_SPI0_CLK         48
-#define STA2X11_GPIO49_SPI0_TXD         49
-#define STA2X11_GPIO50_SPI0_RXD         50
-#define STA2X11_GPIO51_SPI0_FRM         51
-#define STA2X11_GPIO52_SPI1_CLK         52
-#define STA2X11_GPIO53_SPI1_TXD         53
-#define STA2X11_GPIO54_SPI1_RXD         54
-#define STA2X11_GPIO55_SPI1_FRM         55
-#define STA2X11_GPIO56_SPI2_CLK         56
-#define STA2X11_GPIO57_SPI2_TXD         57
-#define STA2X11_GPIO58_SPI2_RXD         58
-#define STA2X11_GPIO59_SPI2_FRM         59
-#define STA2X11_GPIO60_I2C0_SCL         60
-#define STA2X11_GPIO61_I2C0_SDA         61
-#define STA2X11_GPIO62_I2C1_SCL         62
-#define STA2X11_GPIO63_I2C1_SDA         63
-#define STA2X11_GPIO64_I2C2_SCL         64
-#define STA2X11_GPIO65_I2C2_SDA         65
-#define STA2X11_GPIO66_I2C3_SCL         66
-#define STA2X11_GPIO67_I2C3_SDA         67
-#define STA2X11_GPIO68_MSP0_RCK         68
-#define STA2X11_GPIO69_MSP0_RXD         69
-#define STA2X11_GPIO70_MSP0_RFS         70
-#define STA2X11_GPIO71_MSP0_TCK         71
-#define STA2X11_GPIO72_MSP0_TXD         72
-#define STA2X11_GPIO73_MSP0_TFS         73
-#define STA2X11_GPIO74_MSP0_SCK         74
-#define STA2X11_GPIO75_MSP1_CK          75
-#define STA2X11_GPIO76_MSP1_RXD         76
-#define STA2X11_GPIO77_MSP1_FS          77
-#define STA2X11_GPIO78_MSP1_TXD         78
-#define STA2X11_GPIO79_MSP2_CK          79
-#define STA2X11_GPIO80_MSP2_RXD         80
-#define STA2X11_GPIO81_MSP2_FS          81
-#define STA2X11_GPIO82_MSP2_TXD         82
-#define STA2X11_GPIO83_MSP3_CK          83
-#define STA2X11_GPIO84_MSP3_RXD         84
-#define STA2X11_GPIO85_MSP3_FS          85
-#define STA2X11_GPIO86_MSP3_TXD         86
-#define STA2X11_GPIO87_MSP4_CK          87
-#define STA2X11_GPIO88_MSP4_RXD         88
-#define STA2X11_GPIO89_MSP4_FS          89
-#define STA2X11_GPIO90_MSP4_TXD         90
-#define STA2X11_GPIO91_MSP5_CK          91
-#define STA2X11_GPIO92_MSP5_RXD         92
-#define STA2X11_GPIO93_MSP5_FS          93
-#define STA2X11_GPIO94_MSP5_TXD         94
-#define STA2X11_GPIO95_SDIO3_DAT3       95
-#define STA2X11_GPIO96_SDIO3_DAT2       96
-#define STA2X11_GPIO97_SDIO3_DAT1       97
-#define STA2X11_GPIO98_SDIO3_DAT0       98
-#define STA2X11_GPIO99_SDIO3_CLK        99
-#define STA2X11_GPIO100_SDIO3_CMD       100
-#define STA2X11_GPIO101                 101
-#define STA2X11_GPIO102                 102
-#define STA2X11_GPIO103                 103
-#define STA2X11_GPIO104                 104
-#define STA2X11_GPIO105_SDIO2_DAT3      105
-#define STA2X11_GPIO106_SDIO2_DAT2      106
-#define STA2X11_GPIO107_SDIO2_DAT1      107
-#define STA2X11_GPIO108_SDIO2_DAT0      108
-#define STA2X11_GPIO109_SDIO2_CLK       109
-#define STA2X11_GPIO110_SDIO2_CMD       110
-#define STA2X11_GPIO111                 111
-#define STA2X11_GPIO112                 112
-#define STA2X11_GPIO113                 113
-#define STA2X11_GPIO114                 114
-#define STA2X11_GPIO115_SDIO1_DAT3      115
-#define STA2X11_GPIO116_SDIO1_DAT2      116
-#define STA2X11_GPIO117_SDIO1_DAT1      117
-#define STA2X11_GPIO118_SDIO1_DAT0      118
-#define STA2X11_GPIO119_SDIO1_CLK       119
-#define STA2X11_GPIO120_SDIO1_CMD       120
-#define STA2X11_GPIO121                 121
-#define STA2X11_GPIO122                 122
-#define STA2X11_GPIO123                 123
-#define STA2X11_GPIO124                 124
-#define STA2X11_GPIO125_UART2_TXD       125
-#define STA2X11_GPIO126_UART2_RXD       126
-#define STA2X11_GPIO127_UART3_TXD       127
-
-/*
- * The APB bridge has its own registers, needed by our users as well.
- * They are accessed with the following read/mask/write function.
- */
-static inline u32
-sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
-{
-        return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg);
-}
-
-/* CAN and MLB */
-#define APBREG_BSR      0x00    /* Bridge Status Reg */
-#define APBREG_PAER     0x08    /* Peripherals Address Error Reg */
-#define APBREG_PWAC     0x20    /* Peripheral Write Access Control reg */
-#define APBREG_PRAC     0x40    /* Peripheral Read Access Control reg */
-#define APBREG_PCG      0x60    /* Peripheral Clock Gating Reg */
-#define APBREG_PUR      0x80    /* Peripheral Under Reset Reg */
-#define APBREG_EMU_PCG  0xA0    /* Emulator Peripheral Clock Gating Reg */
-
-#define APBREG_CAN      (1 << 1)
-#define APBREG_MLB      (1 << 3)
-
-/* SARAC */
-#define APBREG_BSR_SARAC     0x100 /* Bridge Status Reg */
-#define APBREG_PAER_SARAC    0x108 /* Peripherals Address Error Reg */
-#define APBREG_PWAC_SARAC    0x120 /* Peripheral Write Access Control reg */
-#define APBREG_PRAC_SARAC    0x140 /* Peripheral Read Access Control reg */
-#define APBREG_PCG_SARAC     0x160 /* Peripheral Clock Gating Reg */
-#define APBREG_PUR_SARAC     0x180 /* Peripheral Under Reset Reg */
-#define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */
-
-#define APBREG_SARAC    (1 << 2)
-
-/*
- * The system controller has its own registers. Some of these are accessed
- * by out users as well, using the following read/mask/write/function
- */
-static inline
-u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
-{
-        return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl);
-}
-
-#define SCTL_SCCTL              0x00    /* System controller control register */
-#define SCTL_ARMCFG             0x04    /* ARM configuration register */
-#define SCTL_SCPLLCTL           0x08    /* PLL control status register */
-
-#define SCTL_SCPLLCTL_AUDIO_PLL_PD           BIT(1)
-#define SCTL_SCPLLCTL_FRAC_CONTROL           BIT(3)
-#define SCTL_SCPLLCTL_STRB_BYPASS            BIT(6)
-#define SCTL_SCPLLCTL_STRB_INPUT             BIT(8)
-
-#define SCTL_SCPLLFCTRL         0x0c    /* PLL frequency control register */
-
-#define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_MASK     0xff
-#define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_SHIFT      10
-#define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_MASK         7
-#define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_SHIFT       21
-#define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_MASK         7
-#define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_SHIFT       18
-#define SCTL_SCPLLFCTRL_DITHER_DISABLE_MASK     0x03
-#define SCTL_SCPLLFCTRL_DITHER_DISABLE_SHIFT       4
-
-
-#define SCTL_SCRESFRACT         0x10    /* PLL fractional input register */
-
-#define SCTL_SCRESFRACT_MASK    0x0000ffff
-
-
-#define SCTL_SCRESCTRL1         0x14    /* Peripheral reset control 1 */
-#define SCTL_SCRESXTRL2         0x18    /* Peripheral reset control 2 */
-#define SCTL_SCPEREN0           0x1c    /* Peripheral clock enable register 0 */
-#define SCTL_SCPEREN1           0x20    /* Peripheral clock enable register 1 */
-#define SCTL_SCPEREN2           0x24    /* Peripheral clock enable register 2 */
-#define SCTL_SCGRST             0x28    /* Peripheral global reset */
-#define SCTL_SCPCIECSBRST       0x2c    /* PCIe PAB CSB reset status register */
-#define SCTL_SCPCIPMCR1         0x30    /* PCI power management control 1 */
-#define SCTL_SCPCIPMCR2         0x34    /* PCI power management control 2 */
-#define SCTL_SCPCIPMSR1         0x38    /* PCI power management status 1 */
-#define SCTL_SCPCIPMSR2         0x3c    /* PCI power management status 2 */
-#define SCTL_SCPCIPMSR3         0x40    /* PCI power management status 3 */
-#define SCTL_SCINTREN           0x44    /* Interrupt enable */
-#define SCTL_SCRISR             0x48    /* RAW interrupt status */
-#define SCTL_SCCLKSTAT0         0x4c    /* Peripheral clocks status 0 */
-#define SCTL_SCCLKSTAT1         0x50    /* Peripheral clocks status 1 */
-#define SCTL_SCCLKSTAT2         0x54    /* Peripheral clocks status 2 */
-#define SCTL_SCRSTSTA           0x58    /* Reset status register */
-
-#define SCTL_SCRESCTRL1_USB_PHY_POR     (1 << 0)
-#define SCTL_SCRESCTRL1_USB_OTG (1 << 1)
-#define SCTL_SCRESCTRL1_USB_HRST        (1 << 2)
-#define SCTL_SCRESCTRL1_USB_PHY_HOST    (1 << 3)
-#define SCTL_SCRESCTRL1_SATAII  (1 << 4)
-#define SCTL_SCRESCTRL1_VIP             (1 << 5)
-#define SCTL_SCRESCTRL1_PER_MMC0        (1 << 6)
-#define SCTL_SCRESCTRL1_PER_MMC1        (1 << 7)
-#define SCTL_SCRESCTRL1_PER_GPIO0       (1 << 8)
-#define SCTL_SCRESCTRL1_PER_GPIO1       (1 << 9)
-#define SCTL_SCRESCTRL1_PER_GPIO2       (1 << 10)
-#define SCTL_SCRESCTRL1_PER_GPIO3       (1 << 11)
-#define SCTL_SCRESCTRL1_PER_MTU0        (1 << 12)
-#define SCTL_SCRESCTRL1_KER_SPI0        (1 << 13)
-#define SCTL_SCRESCTRL1_KER_SPI1        (1 << 14)
-#define SCTL_SCRESCTRL1_KER_SPI2        (1 << 15)
-#define SCTL_SCRESCTRL1_KER_MCI0        (1 << 16)
-#define SCTL_SCRESCTRL1_KER_MCI1        (1 << 17)
-#define SCTL_SCRESCTRL1_PRE_HSI2C0      (1 << 18)
-#define SCTL_SCRESCTRL1_PER_HSI2C1      (1 << 19)
-#define SCTL_SCRESCTRL1_PER_HSI2C2      (1 << 20)
-#define SCTL_SCRESCTRL1_PER_HSI2C3      (1 << 21)
-#define SCTL_SCRESCTRL1_PER_MSP0        (1 << 22)
-#define SCTL_SCRESCTRL1_PER_MSP1        (1 << 23)
-#define SCTL_SCRESCTRL1_PER_MSP2        (1 << 24)
-#define SCTL_SCRESCTRL1_PER_MSP3        (1 << 25)
-#define SCTL_SCRESCTRL1_PER_MSP4        (1 << 26)
-#define SCTL_SCRESCTRL1_PER_MSP5        (1 << 27)
-#define SCTL_SCRESCTRL1_PER_MMC (1 << 28)
-#define SCTL_SCRESCTRL1_KER_MSP0        (1 << 29)
-#define SCTL_SCRESCTRL1_KER_MSP1        (1 << 30)
-#define SCTL_SCRESCTRL1_KER_MSP2        (1 << 31)
-
-#define SCTL_SCPEREN0_UART0             (1 << 0)
-#define SCTL_SCPEREN0_UART1             (1 << 1)
-#define SCTL_SCPEREN0_UART2             (1 << 2)
-#define SCTL_SCPEREN0_UART3             (1 << 3)
-#define SCTL_SCPEREN0_MSP0              (1 << 4)
-#define SCTL_SCPEREN0_MSP1              (1 << 5)
-#define SCTL_SCPEREN0_MSP2              (1 << 6)
-#define SCTL_SCPEREN0_MSP3              (1 << 7)
-#define SCTL_SCPEREN0_MSP4              (1 << 8)
-#define SCTL_SCPEREN0_MSP5              (1 << 9)
-#define SCTL_SCPEREN0_SPI0              (1 << 10)
-#define SCTL_SCPEREN0_SPI1              (1 << 11)
-#define SCTL_SCPEREN0_SPI2              (1 << 12)
-#define SCTL_SCPEREN0_I2C0              (1 << 13)
-#define SCTL_SCPEREN0_I2C1              (1 << 14)
-#define SCTL_SCPEREN0_I2C2              (1 << 15)
-#define SCTL_SCPEREN0_I2C3              (1 << 16)
-#define SCTL_SCPEREN0_SVDO_LVDS         (1 << 17)
-#define SCTL_SCPEREN0_USB_HOST          (1 << 18)
-#define SCTL_SCPEREN0_USB_OTG           (1 << 19)
-#define SCTL_SCPEREN0_MCI0              (1 << 20)
-#define SCTL_SCPEREN0_MCI1              (1 << 21)
-#define SCTL_SCPEREN0_MCI2              (1 << 22)
-#define SCTL_SCPEREN0_MCI3              (1 << 23)
-#define SCTL_SCPEREN0_SATA              (1 << 24)
-#define SCTL_SCPEREN0_ETHERNET          (1 << 25)
-#define SCTL_SCPEREN0_VIC               (1 << 26)
-#define SCTL_SCPEREN0_DMA_AUDIO         (1 << 27)
-#define SCTL_SCPEREN0_DMA_SOC           (1 << 28)
-#define SCTL_SCPEREN0_RAM               (1 << 29)
-#define SCTL_SCPEREN0_VIP               (1 << 30)
-#define SCTL_SCPEREN0_ARM               (1 << 31)
-
-#define SCTL_SCPEREN1_UART0             (1 << 0)
-#define SCTL_SCPEREN1_UART1             (1 << 1)
-#define SCTL_SCPEREN1_UART2             (1 << 2)
-#define SCTL_SCPEREN1_UART3             (1 << 3)
-#define SCTL_SCPEREN1_MSP0              (1 << 4)
-#define SCTL_SCPEREN1_MSP1              (1 << 5)
-#define SCTL_SCPEREN1_MSP2              (1 << 6)
-#define SCTL_SCPEREN1_MSP3              (1 << 7)
-#define SCTL_SCPEREN1_MSP4              (1 << 8)
-#define SCTL_SCPEREN1_MSP5              (1 << 9)
-#define SCTL_SCPEREN1_SPI0              (1 << 10)
-#define SCTL_SCPEREN1_SPI1              (1 << 11)
-#define SCTL_SCPEREN1_SPI2              (1 << 12)
-#define SCTL_SCPEREN1_I2C0              (1 << 13)
-#define SCTL_SCPEREN1_I2C1              (1 << 14)
-#define SCTL_SCPEREN1_I2C2              (1 << 15)
-#define SCTL_SCPEREN1_I2C3              (1 << 16)
-#define SCTL_SCPEREN1_USB_PHY           (1 << 17)
-
-/*
- * APB-SOC registers
- */
-static inline
-u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
-{
-        return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs);
-}
-
-#define PCIE_EP1_FUNC3_0_INTR_REG       0x000
-#define PCIE_EP1_FUNC7_4_INTR_REG       0x004
-#define PCIE_EP2_FUNC3_0_INTR_REG       0x008
-#define PCIE_EP2_FUNC7_4_INTR_REG       0x00c
-#define PCIE_EP3_FUNC3_0_INTR_REG       0x010
-#define PCIE_EP3_FUNC7_4_INTR_REG       0x014
-#define PCIE_EP4_FUNC3_0_INTR_REG       0x018
-#define PCIE_EP4_FUNC7_4_INTR_REG       0x01c
-#define PCIE_INTR_ENABLE0_REG           0x020
-#define PCIE_INTR_ENABLE1_REG           0x024
-#define PCIE_EP1_FUNC_TC_REG            0x028
-#define PCIE_EP2_FUNC_TC_REG            0x02c
-#define PCIE_EP3_FUNC_TC_REG            0x030
-#define PCIE_EP4_FUNC_TC_REG            0x034
-#define PCIE_EP1_FUNC_F_REG             0x038
-#define PCIE_EP2_FUNC_F_REG             0x03c
-#define PCIE_EP3_FUNC_F_REG             0x040
-#define PCIE_EP4_FUNC_F_REG             0x044
-#define PCIE_PAB_AMBA_SW_RST_REG        0x048
-#define PCIE_PM_STATUS_0_PORT_0_4       0x04c
-#define PCIE_PM_STATUS_7_0_EP1          0x050
-#define PCIE_PM_STATUS_7_0_EP2          0x054
-#define PCIE_PM_STATUS_7_0_EP3          0x058
-#define PCIE_PM_STATUS_7_0_EP4          0x05c
-#define PCIE_DEV_ID_0_EP1_REG           0x060
-#define PCIE_CC_REV_ID_0_EP1_REG        0x064
-#define PCIE_DEV_ID_1_EP1_REG           0x068
-#define PCIE_CC_REV_ID_1_EP1_REG        0x06c
-#define PCIE_DEV_ID_2_EP1_REG           0x070
-#define PCIE_CC_REV_ID_2_EP1_REG        0x074
-#define PCIE_DEV_ID_3_EP1_REG           0x078
-#define PCIE_CC_REV_ID_3_EP1_REG        0x07c
-#define PCIE_DEV_ID_4_EP1_REG           0x080
-#define PCIE_CC_REV_ID_4_EP1_REG        0x084
-#define PCIE_DEV_ID_5_EP1_REG           0x088
-#define PCIE_CC_REV_ID_5_EP1_REG        0x08c
-#define PCIE_DEV_ID_6_EP1_REG           0x090
-#define PCIE_CC_REV_ID_6_EP1_REG        0x094
-#define PCIE_DEV_ID_7_EP1_REG           0x098
-#define PCIE_CC_REV_ID_7_EP1_REG        0x09c
-#define PCIE_DEV_ID_0_EP2_REG           0x0a0
-#define PCIE_CC_REV_ID_0_EP2_REG        0x0a4
-#define PCIE_DEV_ID_1_EP2_REG           0x0a8
-#define PCIE_CC_REV_ID_1_EP2_REG        0x0ac
-#define PCIE_DEV_ID_2_EP2_REG           0x0b0
-#define PCIE_CC_REV_ID_2_EP2_REG        0x0b4
-#define PCIE_DEV_ID_3_EP2_REG           0x0b8
-#define PCIE_CC_REV_ID_3_EP2_REG        0x0bc
-#define PCIE_DEV_ID_4_EP2_REG           0x0c0
-#define PCIE_CC_REV_ID_4_EP2_REG        0x0c4
-#define PCIE_DEV_ID_5_EP2_REG           0x0c8
-#define PCIE_CC_REV_ID_5_EP2_REG        0x0cc
-#define PCIE_DEV_ID_6_EP2_REG           0x0d0
-#define PCIE_CC_REV_ID_6_EP2_REG        0x0d4
-#define PCIE_DEV_ID_7_EP2_REG           0x0d8
-#define PCIE_CC_REV_ID_7_EP2_REG        0x0dC
-#define PCIE_DEV_ID_0_EP3_REG           0x0e0
-#define PCIE_CC_REV_ID_0_EP3_REG        0x0e4
-#define PCIE_DEV_ID_1_EP3_REG           0x0e8
-#define PCIE_CC_REV_ID_1_EP3_REG        0x0ec
-#define PCIE_DEV_ID_2_EP3_REG           0x0f0
-#define PCIE_CC_REV_ID_2_EP3_REG        0x0f4
-#define PCIE_DEV_ID_3_EP3_REG           0x0f8
-#define PCIE_CC_REV_ID_3_EP3_REG        0x0fc
-#define PCIE_DEV_ID_4_EP3_REG           0x100
-#define PCIE_CC_REV_ID_4_EP3_REG        0x104
-#define PCIE_DEV_ID_5_EP3_REG           0x108
-#define PCIE_CC_REV_ID_5_EP3_REG        0x10c
-#define PCIE_DEV_ID_6_EP3_REG           0x110
-#define PCIE_CC_REV_ID_6_EP3_REG        0x114
-#define PCIE_DEV_ID_7_EP3_REG           0x118
-#define PCIE_CC_REV_ID_7_EP3_REG        0x11c
-#define PCIE_DEV_ID_0_EP4_REG           0x120
-#define PCIE_CC_REV_ID_0_EP4_REG        0x124
-#define PCIE_DEV_ID_1_EP4_REG           0x128
-#define PCIE_CC_REV_ID_1_EP4_REG        0x12c
-#define PCIE_DEV_ID_2_EP4_REG           0x130
-#define PCIE_CC_REV_ID_2_EP4_REG        0x134
-#define PCIE_DEV_ID_3_EP4_REG           0x138
-#define PCIE_CC_REV_ID_3_EP4_REG        0x13c
-#define PCIE_DEV_ID_4_EP4_REG           0x140
-#define PCIE_CC_REV_ID_4_EP4_REG        0x144
-#define PCIE_DEV_ID_5_EP4_REG           0x148
-#define PCIE_CC_REV_ID_5_EP4_REG        0x14c
-#define PCIE_DEV_ID_6_EP4_REG           0x150
-#define PCIE_CC_REV_ID_6_EP4_REG        0x154
-#define PCIE_DEV_ID_7_EP4_REG           0x158
-#define PCIE_CC_REV_ID_7_EP4_REG        0x15c
-#define PCIE_SUBSYS_VEN_ID_REG          0x160
-#define PCIE_COMMON_CLOCK_CONFIG_0_4_0  0x164
-#define PCIE_MIPHYP_SSC_EN_REG          0x168
-#define PCIE_MIPHYP_ADDR_REG            0x16c
-#define PCIE_L1_ASPM_READY_REG          0x170
-#define PCIE_EXT_CFG_RDY_REG            0x174
-#define PCIE_SoC_INT_ROUTER_STATUS0_REG 0x178
-#define PCIE_SoC_INT_ROUTER_STATUS1_REG 0x17c
-#define PCIE_SoC_INT_ROUTER_STATUS2_REG 0x180
-#define PCIE_SoC_INT_ROUTER_STATUS3_REG 0x184
-#define DMA_IP_CTRL_REG                 0x324
-#define DISP_BRIDGE_PU_PD_CTRL_REG      0x328
-#define VIP_PU_PD_CTRL_REG              0x32c
-#define USB_MLB_PU_PD_CTRL_REG          0x330
-#define SDIO_PU_PD_MISCFUNC_CTRL_REG1   0x334
-#define SDIO_PU_PD_MISCFUNC_CTRL_REG2   0x338
-#define UART_PU_PD_CTRL_REG             0x33c
-#define ARM_Lock                        0x340
-#define SYS_IO_CHAR_REG1                0x344
-#define SYS_IO_CHAR_REG2                0x348
-#define SATA_CORE_ID_REG                0x34c
-#define SATA_CTRL_REG                   0x350
-#define I2C_HSFIX_MISC_REG              0x354
-#define SPARE2_RESERVED                 0x358
-#define SPARE3_RESERVED                 0x35c
-#define MASTER_LOCK_REG                 0x368
-#define SYSTEM_CONFIG_STATUS_REG        0x36c
-#define MSP_CLK_CTRL_REG                0x39c
-#define COMPENSATION_REG1               0x3c4
-#define COMPENSATION_REG2               0x3c8
-#define COMPENSATION_REG3               0x3cc
-#define TEST_CTL_REG                    0x3d0
-
-/*
- * SECR (OTP) registers
- */
-#define STA2X11_SECR_CR                 0x00
-#define STA2X11_SECR_FVR0               0x10
-#define STA2X11_SECR_FVR1               0x14
-
-extern int sta2x11_mfd_get_regs_data(struct platform_device *pdev,
-                                     enum sta2x11_mfd_plat_dev index,
-                                     void __iomem **regs,
-                                     spinlock_t **lock);
-
-#endif /* __STA2X11_MFD_H */
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index 383ac1512a3..be1af7c42e5 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -8,9 +8,7 @@
 #ifndef __LINUX_MFD_STMPE_H
 #define __LINUX_MFD_STMPE_H
 
-#include <linux/mutex.h>
-
-struct device;
+#include <linux/device.h>
 
 enum stmpe_block {
         STMPE_BLOCK_GPIO        = 1 << 0,
@@ -22,13 +20,10 @@ enum stmpe_block {
 };
 
 enum stmpe_partnum {
-        STMPE610,
-        STMPE801,
         STMPE811,
         STMPE1601,
         STMPE2401,
         STMPE2403,
-        STMPE_NBR_PARTS
 };
 
 /*
@@ -55,21 +50,17 @@ enum {
 
 
 struct stmpe_variant_info;
-struct stmpe_client_info;
 
 /**
  * struct stmpe - STMPE MFD structure
  * @lock: lock protecting I/O operations
  * @irq_lock: IRQ bus lock
  * @dev: device, mostly for dev_dbg()
- * @irq_domain: IRQ domain
- * @client: client - i2c or spi
- * @ci: client specific information
+ * @i2c: i2c client
  * @partnum: part number
  * @variant: the detected STMPE model number
  * @regs: list of addresses of registers which are at different addresses on
  *        different variants.  Indexed by one of STMPE_IDX_*.
- * @irq: irq number for stmpe
  * @irq_base: starting IRQ number for internal IRQs
  * @num_gpios: number of gpios, differs for variants
  * @ier: cache of IER registers for bus_lock
@@ -80,14 +71,11 @@ struct stmpe {
         struct mutex lock;
         struct mutex irq_lock;
         struct device *dev;
-        struct irq_domain *domain;
-        void *client;
-        struct stmpe_client_info *ci;
+        struct i2c_client *i2c;
         enum stmpe_partnum partnum;
         struct stmpe_variant_info *variant;
         const u8 *regs;
 
-        int irq;
         int irq_base;
         int num_gpios;
         u8 ier[2];
@@ -119,7 +107,7 @@ struct matrix_keymap_data;
  * @no_autorepeat: disable key autorepeat
  */
 struct stmpe_keypad_platform_data {
-        const struct matrix_keymap_data *keymap_data;
+        struct matrix_keymap_data *keymap_data;
         unsigned int debounce_ms;
         unsigned int scan_count;
         bool no_autorepeat;
@@ -190,13 +178,11 @@ struct stmpe_ts_platform_data {
  * @id: device id to distinguish between multiple STMPEs on the same board
  * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
  * @irq_trigger: IRQ trigger to use for the interrupt to the host
+ * @irq_invert_polarity: IRQ line is connected with reversed polarity
  * @autosleep: bool to enable/disable stmpe autosleep
  * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
  * @irq_base: base IRQ number.  %STMPE_NR_IRQS irqs will be used, or
  *            %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used.
- * @irq_over_gpio: true if gpio is used to get irq
- * @irq_gpio: gpio number over which irq will be requested (significant only if
- *            irq_over_gpio is true)
  * @gpio: GPIO-specific platform data
  * @keypad: keypad-specific platform data
  * @ts: touchscreen-specific platform data
@@ -206,9 +192,8 @@ struct stmpe_platform_data {
         unsigned int blocks;
         int irq_base;
         unsigned int irq_trigger;
+        bool irq_invert_polarity;
         bool autosleep;
-        bool irq_over_gpio;
-        int irq_gpio;
         int autosleep_timeout;
 
         struct stmpe_gpio_platform_data *gpio;
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
deleted file mode 100644
index 6aeb6b8da64..00000000000
--- a/include/linux/mfd/syscon.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * System Control Driver
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro Ltd.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __LINUX_MFD_SYSCON_H__
-#define __LINUX_MFD_SYSCON_H__
-
-extern struct regmap *syscon_node_to_regmap(struct device_node *np);
-extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
-extern struct regmap *syscon_regmap_lookup_by_phandle(
-                                        struct device_node *np,
-                                        const char *property);
-#endif /* __LINUX_MFD_SYSCON_H__ */
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
deleted file mode 100644
index dab34a1deb2..00000000000
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
-#define __LINUX_IMX6Q_IOMUXC_GPR_H
-
-#include <linux/bitops.h>
-
-#define IOMUXC_GPR0     0x00
-#define IOMUXC_GPR1     0x04
-#define IOMUXC_GPR2     0x08
-#define IOMUXC_GPR3     0x0c
-#define IOMUXC_GPR4     0x10
-#define IOMUXC_GPR5     0x14
-#define IOMUXC_GPR6     0x18
-#define IOMUXC_GPR7     0x1c
-#define IOMUXC_GPR8     0x20
-#define IOMUXC_GPR9     0x24
-#define IOMUXC_GPR10    0x28
-#define IOMUXC_GPR11    0x2c
-#define IOMUXC_GPR12    0x30
-#define IOMUXC_GPR13    0x34
-
-#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK         (0x3 << 30)
-#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED        (0x0 << 30)
-#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7      (0x1 << 30)
-#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK        (0x2 << 30)
-#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK      (0x3 << 30)
-#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK         (0x3 << 28)
-#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED     (0x0 << 28)
-#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR   (0x1 << 28)
-#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR    (0x2 << 28)
-#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK         (0x3 << 26)
-#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED        (0x0 << 26)
-#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7      (0x1 << 26)
-#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK        (0x2 << 26)
-#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK      (0x3 << 26)
-#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK         (0x3 << 24)
-#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED        (0x3 << 24)
-#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7      (0x3 << 24)
-#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK        (0x3 << 24)
-#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK      (0x3 << 24)
-#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK         (0x3 << 22)
-#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED        (0x0 << 22)
-#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2      (0x1 << 22)
-#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK        (0x2 << 22)
-#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK      (0x3 << 22)
-#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK         (0x3 << 20)
-#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED        (0x0 << 20)
-#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2      (0x1 << 20)
-#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK        (0x2 << 20)
-#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK      (0x3 << 20)
-#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK         (0x3 << 18)
-#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED        (0x0 << 18)
-#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1      (0x1 << 18)
-#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK        (0x2 << 18)
-#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK  (0x3 << 18)
-#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK         (0x3 << 16)
-#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED        (0x0 << 16)
-#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1      (0x1 << 16)
-#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK        (0x2 << 16)
-#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK  (0x3 << 16)
-#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK         (0x3 << 14)
-#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1   (0x0 << 14)
-#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2   (0x1 << 14)
-#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3   (0x2 << 14)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK         BIT(7)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF        0x0
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX        BIT(7)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK         BIT(6)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI         0x0
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3         BIT(6)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK         BIT(5)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4       0x0
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2        BIT(5)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK         BIT(4)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4       0x0
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1         BIT(4)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK         BIT(3)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2       0x0
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1         BIT(3)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK         BIT(2)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1       0x0
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2         BIT(2)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK         BIT(1)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1       0x0
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3         BIT(1)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK         BIT(0)
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1         0x0
-#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX        BIT(0)
-
-#define IMX6Q_GPR1_PCIE_REQ_MASK                (0x3 << 30)
-#define IMX6Q_GPR1_PCIE_EXIT_L1                 BIT(28)
-#define IMX6Q_GPR1_PCIE_RDY_L23                 BIT(27)
-#define IMX6Q_GPR1_PCIE_ENTER_L1                BIT(26)
-#define IMX6Q_GPR1_MIPI_COLOR_SW                BIT(25)
-#define IMX6Q_GPR1_DPI_OFF                      BIT(24)
-#define IMX6Q_GPR1_EXC_MON_MASK                 BIT(22)
-#define IMX6Q_GPR1_EXC_MON_OKAY                 0x0
-#define IMX6Q_GPR1_EXC_MON_SLVE                 BIT(22)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK           BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET         0x0
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX          BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK           BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET         0x0
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX          BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK           BIT(19)
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET         0x0
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX          BIT(19)
-#define IMX6Q_GPR1_PCIE_TEST_PD                 BIT(18)
-#define IMX6Q_GPR1_IPU_VPU_MUX_MASK             BIT(17)
-#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1             0x0
-#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2             BIT(17)
-#define IMX6Q_GPR1_PCIE_REF_CLK_EN              BIT(16)
-#define IMX6Q_GPR1_USB_EXP_MODE                 BIT(15)
-#define IMX6Q_GPR1_PCIE_INT                     BIT(14)
-#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK          BIT(13)
-#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER    0x0
-#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1        BIT(13)
-#define IMX6Q_GPR1_GINT                         BIT(12)
-#define IMX6Q_GPR1_ADDRS3_MASK                  (0x3 << 10)
-#define IMX6Q_GPR1_ADDRS3_32MB                  (0x0 << 10)
-#define IMX6Q_GPR1_ADDRS3_64MB                  (0x1 << 10)
-#define IMX6Q_GPR1_ADDRS3_128MB                 (0x2 << 10)
-#define IMX6Q_GPR1_ACT_CS3                      BIT(9)
-#define IMX6Q_GPR1_ADDRS2_MASK                  (0x3 << 7)
-#define IMX6Q_GPR1_ACT_CS2                      BIT(6)
-#define IMX6Q_GPR1_ADDRS1_MASK                  (0x3 << 4)
-#define IMX6Q_GPR1_ACT_CS1                      BIT(3)
-#define IMX6Q_GPR1_ADDRS0_MASK                  (0x3 << 1)
-#define IMX6Q_GPR1_ACT_CS0                      BIT(0)
-
-#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK       (0x3 << 20)
-#define IMX6Q_GPR2_COUNTER_RESET_VAL_5          (0x0 << 20)
-#define IMX6Q_GPR2_COUNTER_RESET_VAL_3          (0x1 << 20)
-#define IMX6Q_GPR2_COUNTER_RESET_VAL_4          (0x2 << 20)
-#define IMX6Q_GPR2_COUNTER_RESET_VAL_6          (0x3 << 20)
-#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK          (0x7 << 16)
-#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0             (0x0 << 16)
-#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1             (0x1 << 16)
-#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2             (0x2 << 16)
-#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3             (0x3 << 16)
-#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4             (0x4 << 16)
-#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5             (0x5 << 16)
-#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6             (0x6 << 16)
-#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7             (0x7 << 16)
-#define IMX6Q_GPR2_BGREF_RRMODE_MASK            BIT(15)
-#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR    0x0
-#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR    BIT(15)
-#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK         BIT(10)
-#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H     0x0
-#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L     BIT(10)
-#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK         BIT(9)
-#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H     0x0
-#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L     BIT(9)
-#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK         BIT(8)
-#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG         0x0
-#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA        BIT(8)
-#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK          BIT(7)
-#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT         0x0
-#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT         BIT(7)
-#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK         BIT(6)
-#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG         0x0
-#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA        BIT(6)
-#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK          BIT(5)
-#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT         0x0
-#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT         BIT(5)
-#define IMX6Q_GPR2_SPLIT_MODE_EN                BIT(4)
-#define IMX6Q_GPR2_CH1_MODE_MASK                (0x3 << 2)
-#define IMX6Q_GPR2_CH1_MODE_DISABLE             (0x0 << 2)
-#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0        (0x1 << 2)
-#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1        (0x3 << 2)
-#define IMX6Q_GPR2_CH0_MODE_MASK                (0x3 << 0)
-#define IMX6Q_GPR2_CH0_MODE_DISABLE             (0x0 << 0)
-#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0        (0x1 << 0)
-#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1        (0x3 << 0)
-
-#define IMX6Q_GPR3_GPU_DBG_MASK                 (0x3 << 29)
-#define IMX6Q_GPR3_GPU_DBG_GPU3D                (0x0 << 29)
-#define IMX6Q_GPR3_GPU_DBG_GPU2D                (0x1 << 29)
-#define IMX6Q_GPR3_GPU_DBG_OPENVG               (0x2 << 29)
-#define IMX6Q_GPR3_BCH_WR_CACHE_CTL             BIT(28)
-#define IMX6Q_GPR3_BCH_RD_CACHE_CTL             BIT(27)
-#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL          BIT(26)
-#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL          BIT(25)
-#define IMX6Q_GPR3_OCRAM_CTL_MASK               (0xf << 21)
-#define IMX6Q_GPR3_OCRAM_STATUS_MASK            (0xf << 17)
-#define IMX6Q_GPR3_CORE3_DBG_ACK_EN             BIT(16)
-#define IMX6Q_GPR3_CORE2_DBG_ACK_EN             BIT(15)
-#define IMX6Q_GPR3_CORE1_DBG_ACK_EN             BIT(14)
-#define IMX6Q_GPR3_CORE0_DBG_ACK_EN             BIT(13)
-#define IMX6Q_GPR3_TZASC2_BOOT_LOCK             BIT(12)
-#define IMX6Q_GPR3_TZASC1_BOOT_LOCK             BIT(11)
-#define IMX6Q_GPR3_IPU_DIAG_MASK                BIT(10)
-#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK           (0x3 << 8)
-#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0       (0x0 << 8)
-#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1       (0x1 << 8)
-#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0       (0x2 << 8)
-#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1       (0x3 << 8)
-#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK           (0x3 << 6)
-#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0       (0x0 << 6)
-#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1       (0x1 << 6)
-#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0       (0x2 << 6)
-#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1       (0x3 << 6)
-#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK            (0x3 << 4)
-#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0        (0x0 << 4)
-#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1        (0x1 << 4)
-#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0        (0x2 << 4)
-#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1        (0x3 << 4)
-#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK            (0x3 << 2)
-#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0        (0x0 << 2)
-#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1        (0x1 << 2)
-#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0        (0x2 << 2)
-#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1        (0x3 << 2)
-
-#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL            BIT(31)
-#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL            BIT(30)
-#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL            BIT(29)
-#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL            BIT(28)
-#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL            BIT(27)
-#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL            BIT(26)
-#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL            BIT(25)
-#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL            BIT(24)
-#define IMX6Q_GPR4_SDMA_STOP_ACK                BIT(19)
-#define IMX6Q_GPR4_CAN2_STOP_ACK                BIT(18)
-#define IMX6Q_GPR4_CAN1_STOP_ACK                BIT(17)
-#define IMX6Q_GPR4_ENET_STOP_ACK                BIT(16)
-#define IMX6Q_GPR4_SOC_VERSION_MASK             (0xff << 8)
-#define IMX6Q_GPR4_SOC_VERSION_OFF              0x8
-#define IMX6Q_GPR4_VPU_WR_CACHE_SEL             BIT(7)
-#define IMX6Q_GPR4_VPU_RD_CACHE_SEL             BIT(6)
-#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL           BIT(3)
-#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK      BIT(2)
-#define IMX6Q_GPR4_IPU_WR_CACHE_CTL             BIT(1)
-#define IMX6Q_GPR4_IPU_RD_CACHE_CTL             BIT(0)
-
-#define IMX6Q_GPR5_L2_CLK_STOP                  BIT(8)
-
-#define IMX6Q_GPR9_TZASC2_BYP                   BIT(1)
-#define IMX6Q_GPR9_TZASC1_BYP                   BIT(0)
-
-#define IMX6Q_GPR10_LOCK_DBG_EN                 BIT(29)
-#define IMX6Q_GPR10_LOCK_DBG_CLK_EN             BIT(28)
-#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP           BIT(27)
-#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR          (0x3f << 21)
-#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN            BIT(20)
-#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK         (0x3 << 18)
-#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK         (0x3 << 16)
-#define IMX6Q_GPR10_DBG_EN                      BIT(13)
-#define IMX6Q_GPR10_DBG_CLK_EN                  BIT(12)
-#define IMX6Q_GPR10_SEC_ERR_RESP_MASK           BIT(11)
-#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY           0x0
-#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE           BIT(11)
-#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK          (0x3f << 5)
-#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK            BIT(4)
-#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK          (0x3 << 2)
-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0      (0x0 << 2)
-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1      (0x1 << 2)
-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0      (0x2 << 2)
-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1      (0x3 << 2)
-#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK          (0x3 << 0)
-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0      (0x0 << 0)
-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1      (0x1 << 0)
-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0      (0x2 << 0)
-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1      (0x3 << 0)
-
-#define IMX6Q_GPR12_ARMP_IPG_CLK_EN             BIT(27)
-#define IMX6Q_GPR12_ARMP_AHB_CLK_EN             BIT(26)
-#define IMX6Q_GPR12_ARMP_ATB_CLK_EN             BIT(25)
-#define IMX6Q_GPR12_ARMP_APB_CLK_EN             BIT(24)
-#define IMX6Q_GPR12_PCIE_CTL_2                  BIT(10)
-
-#define IMX6Q_GPR13_SDMA_STOP_REQ               BIT(30)
-#define IMX6Q_GPR13_CAN2_STOP_REQ               BIT(29)
-#define IMX6Q_GPR13_CAN1_STOP_REQ               BIT(28)
-#define IMX6Q_GPR13_ENET_STOP_REQ               BIT(27)
-#define IMX6Q_GPR13_SATA_PHY_8_MASK             (0x7 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB           (0x0 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB           (0x1 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB           (0x2 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB           (0x3 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB           (0x4 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB           (0x5 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB           (0x6 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB           (0x7 << 24)
-#define IMX6Q_GPR13_SATA_PHY_7_MASK             (0x1f << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1I           (0x10 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1M           (0x10 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1X           (0x1a << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2I           (0x12 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2M           (0x12 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2X           (0x1a << 19)
-#define IMX6Q_GPR13_SATA_PHY_6_MASK             (0x7 << 16)
-#define IMX6Q_GPR13_SATA_SPEED_MASK             BIT(15)
-#define IMX6Q_GPR13_SATA_SPEED_1P5G             0x0
-#define IMX6Q_GPR13_SATA_SPEED_3P0G             BIT(15)
-#define IMX6Q_GPR13_SATA_PHY_5                  BIT(14)
-#define IMX6Q_GPR13_SATA_PHY_4_MASK             (0x7 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_16_16            (0x0 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_14_16            (0x1 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_12_16            (0x2 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_10_16            (0x3 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_9_16             (0x4 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_8_16             (0x5 << 11)
-#define IMX6Q_GPR13_SATA_PHY_3_MASK             (0xf << 7)
-#define IMX6Q_GPR13_SATA_PHY_3_OFF              0x7
-#define IMX6Q_GPR13_SATA_PHY_2_MASK             (0x1f << 2)
-#define IMX6Q_GPR13_SATA_PHY_2_OFF              0x2
-#define IMX6Q_GPR13_SATA_PHY_1_MASK             (0x3 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_FAST             (0x0 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_MED              (0x1 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_SLOW             (0x2 << 0)
-
-#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
diff --git a/include/linux/mfd/tc3589x.h b/include/linux/mfd/tc3589x.h
index 6b8e1ff4672..16c76e124f9 100644
--- a/include/linux/mfd/tc3589x.h
+++ b/include/linux/mfd/tc3589x.h
@@ -7,7 +7,7 @@
 #ifndef __LINUX_MFD_TC3589x_H
 #define __LINUX_MFD_TC3589x_H
 
-struct device;
+#include <linux/device.h>
 
 enum tx3589x_block {
         TC3589x_BLOCK_GPIO        = 1 << 0,
@@ -117,7 +117,6 @@ struct tc3589x {
         struct mutex lock;
         struct device *dev;
         struct i2c_client *i2c;
-        struct irq_domain *domain;
 
         int irq_base;
         int num_gpio;
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
deleted file mode 100644
index c79ad5d2f27..00000000000
--- a/include/linux/mfd/ti_am335x_tscadc.h
+++ /dev/null
@@ -1,152 +0,0 @@
-#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
-#define __LINUX_TI_AM335X_TSCADC_MFD_H
-
-/*
- * TI Touch Screen / ADC MFD driver
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/mfd/core.h>
-
-#define REG_RAWIRQSTATUS        0x024
-#define REG_IRQSTATUS           0x028
-#define REG_IRQENABLE           0x02C
-#define REG_IRQCLR              0x030
-#define REG_IRQWAKEUP           0x034
-#define REG_CTRL                0x040
-#define REG_ADCFSM              0x044
-#define REG_CLKDIV              0x04C
-#define REG_SE                  0x054
-#define REG_IDLECONFIG          0x058
-#define REG_CHARGECONFIG        0x05C
-#define REG_CHARGEDELAY         0x060
-#define REG_STEPCONFIG(n)       (0x64 + ((n - 1) * 8))
-#define REG_STEPDELAY(n)        (0x68 + ((n - 1) * 8))
-#define REG_FIFO0CNT            0xE4
-#define REG_FIFO0THR            0xE8
-#define REG_FIFO1CNT            0xF0
-#define REG_FIFO1THR            0xF4
-#define REG_FIFO0               0x100
-#define REG_FIFO1               0x200
-
-/*      Register Bitfields      */
-/* IRQ wakeup enable */
-#define IRQWKUP_ENB             BIT(0)
-
-/* Step Enable */
-#define STEPENB_MASK            (0x1FFFF << 0)
-#define STEPENB(val)            ((val) << 0)
-#define STPENB_STEPENB          STEPENB(0x1FFFF)
-#define STPENB_STEPENB_TC       STEPENB(0x1FFF)
-
-/* IRQ enable */
-#define IRQENB_HW_PEN           BIT(0)
-#define IRQENB_FIFO0THRES       BIT(2)
-#define IRQENB_FIFO1THRES       BIT(5)
-#define IRQENB_PENUP            BIT(9)
-
-/* Step Configuration */
-#define STEPCONFIG_MODE_MASK    (3 << 0)
-#define STEPCONFIG_MODE(val)    ((val) << 0)
-#define STEPCONFIG_MODE_HWSYNC  STEPCONFIG_MODE(2)
-#define STEPCONFIG_AVG_MASK     (7 << 2)
-#define STEPCONFIG_AVG(val)     ((val) << 2)
-#define STEPCONFIG_AVG_16       STEPCONFIG_AVG(4)
-#define STEPCONFIG_XPP          BIT(5)
-#define STEPCONFIG_XNN          BIT(6)
-#define STEPCONFIG_YPP          BIT(7)
-#define STEPCONFIG_YNN          BIT(8)
-#define STEPCONFIG_XNP          BIT(9)
-#define STEPCONFIG_YPN          BIT(10)
-#define STEPCONFIG_INM_MASK     (0xF << 15)
-#define STEPCONFIG_INM(val)     ((val) << 15)
-#define STEPCONFIG_INM_ADCREFM  STEPCONFIG_INM(8)
-#define STEPCONFIG_INP_MASK     (0xF << 19)
-#define STEPCONFIG_INP(val)     ((val) << 19)
-#define STEPCONFIG_INP_AN2      STEPCONFIG_INP(2)
-#define STEPCONFIG_INP_AN3      STEPCONFIG_INP(3)
-#define STEPCONFIG_INP_AN4      STEPCONFIG_INP(4)
-#define STEPCONFIG_INP_ADCREFM  STEPCONFIG_INP(8)
-#define STEPCONFIG_FIFO1        BIT(26)
-
-/* Delay register */
-#define STEPDELAY_OPEN_MASK     (0x3FFFF << 0)
-#define STEPDELAY_OPEN(val)     ((val) << 0)
-#define STEPCONFIG_OPENDLY      STEPDELAY_OPEN(0x098)
-#define STEPDELAY_SAMPLE_MASK   (0xFF << 24)
-#define STEPDELAY_SAMPLE(val)   ((val) << 24)
-#define STEPCONFIG_SAMPLEDLY    STEPDELAY_SAMPLE(0)
-
-/* Charge Config */
-#define STEPCHARGE_RFP_MASK     (7 << 12)
-#define STEPCHARGE_RFP(val)     ((val) << 12)
-#define STEPCHARGE_RFP_XPUL     STEPCHARGE_RFP(1)
-#define STEPCHARGE_INM_MASK     (0xF << 15)
-#define STEPCHARGE_INM(val)     ((val) << 15)
-#define STEPCHARGE_INM_AN1      STEPCHARGE_INM(1)
-#define STEPCHARGE_INP_MASK     (0xF << 19)
-#define STEPCHARGE_INP(val)     ((val) << 19)
-#define STEPCHARGE_INP_AN1      STEPCHARGE_INP(1)
-#define STEPCHARGE_RFM_MASK     (3 << 23)
-#define STEPCHARGE_RFM(val)     ((val) << 23)
-#define STEPCHARGE_RFM_XNUR     STEPCHARGE_RFM(1)
-
-/* Charge delay */
-#define CHARGEDLY_OPEN_MASK     (0x3FFFF << 0)
-#define CHARGEDLY_OPEN(val)     ((val) << 0)
-#define CHARGEDLY_OPENDLY       CHARGEDLY_OPEN(1)
-
-/* Control register */
-#define CNTRLREG_TSCSSENB       BIT(0)
-#define CNTRLREG_STEPID         BIT(1)
-#define CNTRLREG_STEPCONFIGWRT  BIT(2)
-#define CNTRLREG_POWERDOWN      BIT(4)
-#define CNTRLREG_AFE_CTRL_MASK  (3 << 5)
-#define CNTRLREG_AFE_CTRL(val)  ((val) << 5)
-#define CNTRLREG_4WIRE          CNTRLREG_AFE_CTRL(1)
-#define CNTRLREG_5WIRE          CNTRLREG_AFE_CTRL(2)
-#define CNTRLREG_8WIRE          CNTRLREG_AFE_CTRL(3)
-#define CNTRLREG_TSCENB         BIT(7)
-
-#define ADC_CLK                 3000000
-#define MAX_CLK_DIV             7
-#define TOTAL_STEPS             16
-#define TOTAL_CHANNELS          8
-
-#define TSCADC_CELLS            2
-
-enum tscadc_cells {
-        TSC_CELL,
-        ADC_CELL,
-};
-
-struct mfd_tscadc_board {
-        struct tsc_data *tsc_init;
-        struct adc_data *adc_init;
-};
-
-struct ti_tscadc_dev {
-        struct device *dev;
-        struct regmap *regmap_tscadc;
-        void __iomem *tscadc_base;
-        int irq;
-        struct mfd_cell cells[TSCADC_CELLS];
-
-        /* tsc device */
-        struct titsc *tsc;
-
-        /* adc device */
-        struct adc_device *adc;
-};
-
-#endif
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index d83af39815a..0dc98044d8b 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -1,10 +1,8 @@
 #ifndef MFD_TMIO_H
 #define MFD_TMIO_H
 
-#include <linux/device.h>
 #include <linux/fb.h>
 #include <linux/io.h>
-#include <linux/jiffies.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 
@@ -66,8 +64,8 @@
 #define TMIO_MMC_SDIO_IRQ               (1 << 2)
 /*
  * Some platforms can detect card insertion events with controller powered
- * down, using a GPIO IRQ, in which case they have to fill in cd_irq, cd_gpio,
- * and cd_flags fields of struct tmio_mmc_data.
+ * down, in which case they have to call tmio_mmc_cd_wakeup() to power up the
+ * controller and report the event to the driver.
  */
 #define TMIO_MMC_HAS_COLD_CD            (1 << 3)
 /*
@@ -75,12 +73,6 @@
  * idle before writing to some registers.
  */
 #define TMIO_MMC_HAS_IDLE_WAIT          (1 << 4)
-/*
- * A GPIO is used for card hotplug detection. We need an extra flag for this,
- * because 0 is a valid GPIO number too, and requiring users to specify
- * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
- */
-#define TMIO_MMC_USE_GPIO_CD            (1 << 5)
 
 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@@ -101,31 +93,23 @@ struct tmio_mmc_host;
 struct tmio_mmc_data {
         unsigned int                    hclk;
         unsigned long                   capabilities;
-        unsigned long                   capabilities2;
         unsigned long                   flags;
         u32                             ocr_mask;       /* available voltages */
         struct tmio_mmc_dma             *dma;
         struct device                   *dev;
-        unsigned int                    cd_gpio;
+        bool                            power;
         void (*set_pwr)(struct platform_device *host, int state);
         void (*set_clk_div)(struct platform_device *host, int state);
         int (*get_cd)(struct platform_device *host);
         int (*write16_hook)(struct tmio_mmc_host *host, int addr);
-        /* clock management callbacks */
-        int (*clk_enable)(struct platform_device *pdev, unsigned int *f);
-        void (*clk_disable)(struct platform_device *pdev);
 };
 
-/*
- * This function is deprecated and will be removed soon. Please, convert your
- * platform to use drivers/mmc/core/cd-gpio.c
- */
-#include <linux/mmc/host.h>
 static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
 {
-        if (pdata)
-                mmc_detect_change(dev_get_drvdata(pdata->dev),
-                                  msecs_to_jiffies(100));
+        if (pdata && !pdata->power) {
+                pdata->power = true;
+                pm_runtime_get(pdata->dev);
+        }
 }
 
 /*
diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h
index 6694cf43e8b..511ced59ef1 100644
--- a/include/linux/mfd/tps65090.h
+++ b/include/linux/mfd/tps65090.h
@@ -1,4 +1,5 @@
 /*
+ * include/linux/mfd/tps65090.h
  * Core driver interface for TI TPS65090 PMIC family
  *
  * Copyright (C) 2012 NVIDIA Corporation
@@ -22,110 +23,31 @@
 #ifndef __LINUX_MFD_TPS65090_H
 #define __LINUX_MFD_TPS65090_H
 
-#include <linux/irq.h>
-#include <linux/regmap.h>
+#include <linux/rtc.h>
 
-/* TPS65090 IRQs */
-enum {
-        TPS65090_IRQ_VAC_STATUS_CHANGE,
-        TPS65090_IRQ_VSYS_STATUS_CHANGE,
-        TPS65090_IRQ_BAT_STATUS_CHANGE,
-        TPS65090_IRQ_CHARGING_STATUS_CHANGE,
-        TPS65090_IRQ_CHARGING_COMPLETE,
-        TPS65090_IRQ_OVERLOAD_DCDC1,
-        TPS65090_IRQ_OVERLOAD_DCDC2,
-        TPS65090_IRQ_OVERLOAD_DCDC3,
-        TPS65090_IRQ_OVERLOAD_FET1,
-        TPS65090_IRQ_OVERLOAD_FET2,
-        TPS65090_IRQ_OVERLOAD_FET3,
-        TPS65090_IRQ_OVERLOAD_FET4,
-        TPS65090_IRQ_OVERLOAD_FET5,
-        TPS65090_IRQ_OVERLOAD_FET6,
-        TPS65090_IRQ_OVERLOAD_FET7,
-};
-
-/* TPS65090 Regulator ID */
-enum {
-        TPS65090_REGULATOR_DCDC1,
-        TPS65090_REGULATOR_DCDC2,
-        TPS65090_REGULATOR_DCDC3,
-        TPS65090_REGULATOR_FET1,
-        TPS65090_REGULATOR_FET2,
-        TPS65090_REGULATOR_FET3,
-        TPS65090_REGULATOR_FET4,
-        TPS65090_REGULATOR_FET5,
-        TPS65090_REGULATOR_FET6,
-        TPS65090_REGULATOR_FET7,
-        TPS65090_REGULATOR_LDO1,
-        TPS65090_REGULATOR_LDO2,
-
-        /* Last entry for maximum ID */
-        TPS65090_REGULATOR_MAX,
-};
-
-struct tps65090 {
-        struct device           *dev;
-        struct regmap           *rmap;
-        struct regmap_irq_chip_data *irq_data;
-};
-
-/*
- * struct tps65090_regulator_plat_data
- *
- * @reg_init_data: The regulator init data.
- * @enable_ext_control: Enable extrenal control or not. Only available for
- *     DCDC1, DCDC2 and DCDC3.
- * @gpio: Gpio number if external control is enabled and controlled through
- *     gpio.
- */
-struct tps65090_regulator_plat_data {
-        struct regulator_init_data *reg_init_data;
-        bool enable_ext_control;
-        int gpio;
+struct tps65090_subdev_info {
+        int             id;
+        const char      *name;
+        void            *platform_data;
 };
 
 struct tps65090_platform_data {
         int irq_base;
-        struct tps65090_regulator_plat_data *reg_pdata[TPS65090_REGULATOR_MAX];
+        int num_subdevs;
+        struct tps65090_subdev_info *subdevs;
 };
 
 /*
  * NOTE: the functions below are not intended for use outside
  * of the TPS65090 sub-device drivers
  */
-static inline int tps65090_write(struct device *dev, int reg, uint8_t val)
-{
-        struct tps65090 *tps = dev_get_drvdata(dev);
-
-        return regmap_write(tps->rmap, reg, val);
-}
-
-static inline int tps65090_read(struct device *dev, int reg, uint8_t *val)
-{
-        struct tps65090 *tps = dev_get_drvdata(dev);
-        unsigned int temp_val;
-        int ret;
-
-        ret = regmap_read(tps->rmap, reg, &temp_val);
-        if (!ret)
-                *val = temp_val;
-        return ret;
-}
-
-static inline int tps65090_set_bits(struct device *dev, int reg,
-                uint8_t bit_num)
-{
-        struct tps65090 *tps = dev_get_drvdata(dev);
-
-        return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u);
-}
-
-static inline int tps65090_clr_bits(struct device *dev, int reg,
-                uint8_t bit_num)
-{
-        struct tps65090 *tps = dev_get_drvdata(dev);
-
-        return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u);
-}
+extern int tps65090_write(struct device *dev, int reg, uint8_t val);
+extern int tps65090_writes(struct device *dev, int reg, int len, uint8_t *val);
+extern int tps65090_read(struct device *dev, int reg, uint8_t *val);
+extern int tps65090_reads(struct device *dev, int reg, int len, uint8_t *val);
+extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num);
+extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num);
+extern int tps65090_update(struct device *dev, int reg, uint8_t val,
+                           uint8_t bit_num);
 
 #endif /*__LINUX_MFD_TPS65090_H */
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
deleted file mode 100644
index 290762f9393..00000000000
--- a/include/linux/mfd/tps65217.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * linux/mfd/tps65217.h
- *
- * Functions to access TPS65217 power management chip.
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __LINUX_MFD_TPS65217_H
-#define __LINUX_MFD_TPS65217_H
-
-#include <linux/i2c.h>
-#include <linux/regulator/driver.h>
-#include <linux/regulator/machine.h>
-
-/* TPS chip id list */
-#define TPS65217                        0xF0
-
-/* I2C ID for TPS65217 part */
-#define TPS65217_I2C_ID                 0x24
-
-/* All register addresses */
-#define TPS65217_REG_CHIPID             0X00
-#define TPS65217_REG_PPATH              0X01
-#define TPS65217_REG_INT                0X02
-#define TPS65217_REG_CHGCONFIG0         0X03
-#define TPS65217_REG_CHGCONFIG1         0X04
-#define TPS65217_REG_CHGCONFIG2         0X05
-#define TPS65217_REG_CHGCONFIG3         0X06
-#define TPS65217_REG_WLEDCTRL1          0X07
-#define TPS65217_REG_WLEDCTRL2          0X08
-#define TPS65217_REG_MUXCTRL            0X09
-#define TPS65217_REG_STATUS             0X0A
-#define TPS65217_REG_PASSWORD           0X0B
-#define TPS65217_REG_PGOOD              0X0C
-#define TPS65217_REG_DEFPG              0X0D
-#define TPS65217_REG_DEFDCDC1           0X0E
-#define TPS65217_REG_DEFDCDC2           0X0F
-#define TPS65217_REG_DEFDCDC3           0X10
-#define TPS65217_REG_DEFSLEW            0X11
-#define TPS65217_REG_DEFLDO1            0X12
-#define TPS65217_REG_DEFLDO2            0X13
-#define TPS65217_REG_DEFLS1             0X14
-#define TPS65217_REG_DEFLS2             0X15
-#define TPS65217_REG_ENABLE             0X16
-#define TPS65217_REG_DEFUVLO            0X18
-#define TPS65217_REG_SEQ1               0X19
-#define TPS65217_REG_SEQ2               0X1A
-#define TPS65217_REG_SEQ3               0X1B
-#define TPS65217_REG_SEQ4               0X1C
-#define TPS65217_REG_SEQ5               0X1D
-#define TPS65217_REG_SEQ6               0X1E
-
-/* Register field definitions */
-#define TPS65217_CHIPID_CHIP_MASK       0xF0
-#define TPS65217_CHIPID_REV_MASK        0x0F
-
-#define TPS65217_PPATH_ACSINK_ENABLE    BIT(7)
-#define TPS65217_PPATH_USBSINK_ENABLE   BIT(6)
-#define TPS65217_PPATH_AC_PW_ENABLE     BIT(5)
-#define TPS65217_PPATH_USB_PW_ENABLE    BIT(4)
-#define TPS65217_PPATH_AC_CURRENT_MASK  0x0C
-#define TPS65217_PPATH_USB_CURRENT_MASK 0x03
-
-#define TPS65217_INT_PBM                BIT(6)
-#define TPS65217_INT_ACM                BIT(5)
-#define TPS65217_INT_USBM               BIT(4)
-#define TPS65217_INT_PBI                BIT(2)
-#define TPS65217_INT_ACI                BIT(1)
-#define TPS65217_INT_USBI               BIT(0)
-
-#define TPS65217_CHGCONFIG0_TREG        BIT(7)
-#define TPS65217_CHGCONFIG0_DPPM        BIT(6)
-#define TPS65217_CHGCONFIG0_TSUSP       BIT(5)
-#define TPS65217_CHGCONFIG0_TERMI       BIT(4)
-#define TPS65217_CHGCONFIG0_ACTIVE      BIT(3)
-#define TPS65217_CHGCONFIG0_CHGTOUT     BIT(2)
-#define TPS65217_CHGCONFIG0_PCHGTOUT    BIT(1)
-#define TPS65217_CHGCONFIG0_BATTEMP     BIT(0)
-
-#define TPS65217_CHGCONFIG1_TMR_MASK    0xC0
-#define TPS65217_CHGCONFIG1_TMR_ENABLE  BIT(5)
-#define TPS65217_CHGCONFIG1_NTC_TYPE    BIT(4)
-#define TPS65217_CHGCONFIG1_RESET       BIT(3)
-#define TPS65217_CHGCONFIG1_TERM        BIT(2)
-#define TPS65217_CHGCONFIG1_SUSP        BIT(1)
-#define TPS65217_CHGCONFIG1_CHG_EN      BIT(0)
-
-#define TPS65217_CHGCONFIG2_DYNTMR      BIT(7)
-#define TPS65217_CHGCONFIG2_VPREGHG     BIT(6)
-#define TPS65217_CHGCONFIG2_VOREG_MASK  0x30
-
-#define TPS65217_CHGCONFIG3_ICHRG_MASK  0xC0
-#define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
-#define TPS65217_CHGCONFIG2_PCHRGT      BIT(3)
-#define TPS65217_CHGCONFIG2_TERMIF      0x06
-#define TPS65217_CHGCONFIG2_TRANGE      BIT(0)
-
-#define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
-#define TPS65217_WLEDCTRL1_ISEL         BIT(2)
-#define TPS65217_WLEDCTRL1_FDIM_MASK    0x03
-
-#define TPS65217_WLEDCTRL2_DUTY_MASK    0x7F
-
-#define TPS65217_MUXCTRL_MUX_MASK       0x07
-
-#define TPS65217_STATUS_OFF             BIT(7)
-#define TPS65217_STATUS_ACPWR           BIT(3)
-#define TPS65217_STATUS_USBPWR          BIT(2)
-#define TPS65217_STATUS_PB              BIT(0)
-
-#define TPS65217_PASSWORD_REGS_UNLOCK   0x7D
-
-#define TPS65217_PGOOD_LDO3_PG          BIT(6)
-#define TPS65217_PGOOD_LDO4_PG          BIT(5)
-#define TPS65217_PGOOD_DC1_PG           BIT(4)
-#define TPS65217_PGOOD_DC2_PG           BIT(3)
-#define TPS65217_PGOOD_DC3_PG           BIT(2)
-#define TPS65217_PGOOD_LDO1_PG          BIT(1)
-#define TPS65217_PGOOD_LDO2_PG          BIT(0)
-
-#define TPS65217_DEFPG_LDO1PGM          BIT(3)
-#define TPS65217_DEFPG_LDO2PGM          BIT(2)
-#define TPS65217_DEFPG_PGDLY_MASK       0x03
-
-#define TPS65217_DEFDCDCX_XADJX         BIT(7)
-#define TPS65217_DEFDCDCX_DCDC_MASK     0x3F
-
-#define TPS65217_DEFSLEW_GO             BIT(7)
-#define TPS65217_DEFSLEW_GODSBL         BIT(6)
-#define TPS65217_DEFSLEW_PFM_EN1        BIT(5)
-#define TPS65217_DEFSLEW_PFM_EN2        BIT(4)
-#define TPS65217_DEFSLEW_PFM_EN3        BIT(3)
-#define TPS65217_DEFSLEW_SLEW_MASK      0x07
-
-#define TPS65217_DEFLDO1_LDO1_MASK      0x0F
-
-#define TPS65217_DEFLDO2_TRACK          BIT(6)
-#define TPS65217_DEFLDO2_LDO2_MASK      0x3F
-
-#define TPS65217_DEFLDO3_LDO3_EN        BIT(5)
-#define TPS65217_DEFLDO3_LDO3_MASK      0x1F
-
-#define TPS65217_DEFLDO4_LDO4_EN        BIT(5)
-#define TPS65217_DEFLDO4_LDO4_MASK      0x1F
-
-#define TPS65217_ENABLE_LS1_EN          BIT(6)
-#define TPS65217_ENABLE_LS2_EN          BIT(5)
-#define TPS65217_ENABLE_DC1_EN          BIT(4)
-#define TPS65217_ENABLE_DC2_EN          BIT(3)
-#define TPS65217_ENABLE_DC3_EN          BIT(2)
-#define TPS65217_ENABLE_LDO1_EN         BIT(1)
-#define TPS65217_ENABLE_LDO2_EN         BIT(0)
-
-#define TPS65217_DEFUVLO_UVLOHYS        BIT(2)
-#define TPS65217_DEFUVLO_UVLO_MASK      0x03
-
-#define TPS65217_SEQ1_DC1_SEQ_MASK      0xF0
-#define TPS65217_SEQ1_DC2_SEQ_MASK      0x0F
-
-#define TPS65217_SEQ2_DC3_SEQ_MASK      0xF0
-#define TPS65217_SEQ2_LDO1_SEQ_MASK     0x0F
-
-#define TPS65217_SEQ3_LDO2_SEQ_MASK     0xF0
-#define TPS65217_SEQ3_LDO3_SEQ_MASK     0x0F
-
-#define TPS65217_SEQ4_LDO4_SEQ_MASK     0xF0
-
-#define TPS65217_SEQ5_DLY1_MASK         0xC0
-#define TPS65217_SEQ5_DLY2_MASK         0x30
-#define TPS65217_SEQ5_DLY3_MASK         0x0C
-#define TPS65217_SEQ5_DLY4_MASK         0x03
-
-#define TPS65217_SEQ6_DLY5_MASK         0xC0
-#define TPS65217_SEQ6_DLY6_MASK         0x30
-#define TPS65217_SEQ6_SEQUP             BIT(2)
-#define TPS65217_SEQ6_SEQDWN            BIT(1)
-#define TPS65217_SEQ6_INSTDWN           BIT(0)
-
-#define TPS65217_MAX_REGISTER           0x1E
-#define TPS65217_PROTECT_NONE           0
-#define TPS65217_PROTECT_L1             1
-#define TPS65217_PROTECT_L2             2
-
-
-enum tps65217_regulator_id {
-        /* DCDC's */
-        TPS65217_DCDC_1,
-        TPS65217_DCDC_2,
-        TPS65217_DCDC_3,
-        /* LDOs */
-        TPS65217_LDO_1,
-        TPS65217_LDO_2,
-        TPS65217_LDO_3,
-        TPS65217_LDO_4,
-};
-
-#define TPS65217_MAX_REG_ID             TPS65217_LDO_4
-
-/* Number of step-down converters available */
-#define TPS65217_NUM_DCDC               3
-/* Number of LDO voltage regulators available */
-#define TPS65217_NUM_LDO                4
-/* Number of total regulators available */
-#define TPS65217_NUM_REGULATOR          (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
-
-enum tps65217_bl_isel {
-        TPS65217_BL_ISET1 = 1,
-        TPS65217_BL_ISET2,
-};
-
-enum tps65217_bl_fdim {
-        TPS65217_BL_FDIM_100HZ,
-        TPS65217_BL_FDIM_200HZ,
-        TPS65217_BL_FDIM_500HZ,
-        TPS65217_BL_FDIM_1000HZ,
-};
-
-struct tps65217_bl_pdata {
-        enum tps65217_bl_isel isel;
-        enum tps65217_bl_fdim fdim;
-};
-
-/**
- * struct tps65217_board - packages regulator init data
- * @tps65217_regulator_data: regulator initialization values
- *
- * Board data may be used to initialize regulator.
- */
-struct tps65217_board {
-        struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
-        struct device_node *of_node[TPS65217_NUM_REGULATOR];
-        struct tps65217_bl_pdata *bl_pdata;
-};
-
-/**
- * struct tps_info - packages regulator constraints
- * @name:               Voltage regulator name
- * @min_uV:             minimum micro volts
- * @max_uV:             minimum micro volts
- * @vsel_to_uv:         Function pointer to get voltage from selector
- * @uv_to_vsel:         Function pointer to get selector from voltage
- *
- * This data is used to check the regualtor voltage limits while setting.
- */
-struct tps_info {
-        const char *name;
-        int min_uV;
-        int max_uV;
-        int (*vsel_to_uv)(unsigned int vsel);
-        int (*uv_to_vsel)(int uV, unsigned int *vsel);
-};
-
-/**
- * struct tps65217 - tps65217 sub-driver chip access routines
- *
- * Device data may be used to access the TPS65217 chip
- */
-
-struct tps65217 {
-        struct device *dev;
-        struct tps65217_board *pdata;
-        unsigned int id;
-        struct regulator_desc desc[TPS65217_NUM_REGULATOR];
-        struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
-        struct tps_info *info[TPS65217_NUM_REGULATOR];
-        struct regmap *regmap;
-};
-
-static inline struct tps65217 *dev_to_tps65217(struct device *dev)
-{
-        return dev_get_drvdata(dev);
-}
-
-static inline int tps65217_chip_id(struct tps65217 *tps65217)
-{
-        return tps65217->id;
-}
-
-int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
-                                        unsigned int *val);
-int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
-                        unsigned int val, unsigned int level);
-int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
-                unsigned int mask, unsigned int val, unsigned int level);
-int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
-                unsigned int mask, unsigned int level);
-
-#endif /*  __LINUX_MFD_TPS65217_H */
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index 87994542573..702cee59cc7 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -1,20 +1,11 @@
 #ifndef __LINUX_MFD_TPS6586X_H
 #define __LINUX_MFD_TPS6586X_H
 
-#define TPS6586X_SLEW_RATE_INSTANTLY    0x00
-#define TPS6586X_SLEW_RATE_110UV        0x01
-#define TPS6586X_SLEW_RATE_220UV        0x02
-#define TPS6586X_SLEW_RATE_440UV        0x03
-#define TPS6586X_SLEW_RATE_880UV        0x04
-#define TPS6586X_SLEW_RATE_1760UV       0x05
-#define TPS6586X_SLEW_RATE_3520UV       0x06
-#define TPS6586X_SLEW_RATE_7040UV       0x07
-
-#define TPS6586X_SLEW_RATE_SET          0x08
-#define TPS6586X_SLEW_RATE_MASK         0x07
+#define SM0_PWM_BIT 0
+#define SM1_PWM_BIT 1
+#define SM2_PWM_BIT 2
 
 enum {
-        TPS6586X_ID_SYS,
         TPS6586X_ID_SM_0,
         TPS6586X_ID_SM_1,
         TPS6586X_ID_SM_2,
@@ -29,7 +20,6 @@ enum {
         TPS6586X_ID_LDO_8,
         TPS6586X_ID_LDO_9,
         TPS6586X_ID_LDO_RTC,
-        TPS6586X_ID_MAX_REGULATOR,
 };
 
 enum {
@@ -62,15 +52,58 @@ enum {
         TPS6586X_INT_RTC_ALM2,
 };
 
+enum pwm_pfm_mode {
+        PWM_ONLY,
+        AUTO_PWM_PFM,
+        PWM_DEFAULT_VALUE,
+
+};
+
+enum slew_rate_settings {
+        SLEW_RATE_INSTANTLY = 0,
+        SLEW_RATE_0110UV_PER_SEC = 0x1,
+        SLEW_RATE_0220UV_PER_SEC = 0x2,
+        SLEW_RATE_0440UV_PER_SEC = 0x3,
+        SLEW_RATE_0880UV_PER_SEC = 0x4,
+        SLEW_RATE_1760UV_PER_SEC = 0x5,
+        SLEW_RATE_3520UV_PER_SEC = 0x6,
+        SLEW_RATE_7040UV_PER_SEC = 0x7,
+        SLEW_RATE_DEFAULT_VALUE,
+};
+
 struct tps6586x_settings {
-        int slew_rate;
+        /* SM0, SM1 and SM2 have PWM-only and auto PWM/PFM mode */
+        enum pwm_pfm_mode sm_pwm_mode;
+        /* SM0 and SM1 have slew rate settings */
+        enum slew_rate_settings slew_rate;
+};
+
+enum {
+        TPS6586X_RTC_CL_SEL_1_5PF  = 0x0,
+        TPS6586X_RTC_CL_SEL_6_5PF  = 0x1,
+        TPS6586X_RTC_CL_SEL_7_5PF  = 0x2,
+        TPS6586X_RTC_CL_SEL_12_5PF = 0x3,
 };
 
 struct tps6586x_subdev_info {
         int             id;
         const char      *name;
         void            *platform_data;
-        struct device_node *of_node;
+};
+
+struct tps6586x_epoch_start {
+        int year;
+        int month;
+        int day;
+        int hour;
+        int min;
+        int sec;
+};
+
+struct tps6586x_rtc_platform_data {
+        int irq;
+        struct tps6586x_epoch_start start;
+        int cl_sel; /* internal XTAL capacitance, see TPS6586X_RTC_CL_SEL* */
 };
 
 struct tps6586x_platform_data {
@@ -79,9 +112,8 @@ struct tps6586x_platform_data {
 
         int gpio_base;
         int irq_base;
-        bool pm_off;
 
-        struct regulator_init_data *reg_init_data[TPS6586X_ID_MAX_REGULATOR];
+        bool use_power_off;
 };
 
 /*
@@ -96,6 +128,5 @@ extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
 extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
 extern int tps6586x_update(struct device *dev, int reg, uint8_t val,
                            uint8_t mask);
-extern int tps6586x_irq_get_virq(struct device *dev, int irq);
 
 #endif /*__LINUX_MFD_TPS6586X_H */
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 20e433e551e..f6021cc9d91 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -17,9 +17,6 @@
 #ifndef __LINUX_MFD_TPS65910_H
 #define __LINUX_MFD_TPS65910_H
 
-#include <linux/gpio.h>
-#include <linux/regmap.h>
-
 /* TPS chip id list */
 #define TPS65910                        0
 #define TPS65911                        1
@@ -132,16 +129,6 @@
  *
  */
 
-/* RTC_CTRL_REG bitfields */
-#define TPS65910_RTC_CTRL_STOP_RTC                      0x01 /*0=stop, 1=run */
-#define TPS65910_RTC_CTRL_GET_TIME                      0x40
-
-/* RTC_STATUS_REG bitfields */
-#define TPS65910_RTC_STATUS_ALARM               0x40
-
-/* RTC_INTERRUPTS_REG bitfields */
-#define TPS65910_RTC_INTERRUPTS_EVERY           0x03
-#define TPS65910_RTC_INTERRUPTS_IT_ALARM        0x08
 
 /*Register BCK1  (0x80) register.RegisterDescription */
 #define BCK1_BCKUP_MASK                                 0xFF
@@ -376,8 +363,6 @@
 
 
 /*Register DEVCTRL  (0x80) register.RegisterDescription */
-#define DEVCTRL_PWR_OFF_MASK                            0x80
-#define DEVCTRL_PWR_OFF_SHIFT                           7
 #define DEVCTRL_RTC_PWDN_MASK                           0x40
 #define DEVCTRL_RTC_PWDN_SHIFT                          6
 #define DEVCTRL_CK32K_CTRL_MASK                         0x20
@@ -572,49 +557,6 @@
 #define SPARE_SPARE_MASK                                0xFF
 #define SPARE_SPARE_SHIFT                               0
 
-#define TPS65910_INT_STS_RTC_PERIOD_IT_MASK                     0x80
-#define TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT                    7
-#define TPS65910_INT_STS_RTC_ALARM_IT_MASK                      0x40
-#define TPS65910_INT_STS_RTC_ALARM_IT_SHIFT                     6
-#define TPS65910_INT_STS_HOTDIE_IT_MASK                         0x20
-#define TPS65910_INT_STS_HOTDIE_IT_SHIFT                        5
-#define TPS65910_INT_STS_PWRHOLD_F_IT_MASK                      0x10
-#define TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT                     4
-#define TPS65910_INT_STS_PWRON_LP_IT_MASK                       0x08
-#define TPS65910_INT_STS_PWRON_LP_IT_SHIFT                      3
-#define TPS65910_INT_STS_PWRON_IT_MASK                          0x04
-#define TPS65910_INT_STS_PWRON_IT_SHIFT                         2
-#define TPS65910_INT_STS_VMBHI_IT_MASK                          0x02
-#define TPS65910_INT_STS_VMBHI_IT_SHIFT                         1
-#define TPS65910_INT_STS_VMBDCH_IT_MASK                         0x01
-#define TPS65910_INT_STS_VMBDCH_IT_SHIFT                        0
-
-#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK                 0x80
-#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT                7
-#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK                  0x40
-#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT                 6
-#define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK                     0x20
-#define TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT                    5
-#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK                    0x10
-#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT                   4
-#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK                   0x08
-#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT                  3
-#define TPS65910_INT_MSK_PWRON_IT_MSK_MASK                      0x04
-#define TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT                     2
-#define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK                      0x02
-#define TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT                     1
-#define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK                     0x01
-#define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT                    0
-
-#define TPS65910_INT_STS2_GPIO0_F_IT_SHIFT                      2
-#define TPS65910_INT_STS2_GPIO0_F_IT_MASK                       0x02
-#define TPS65910_INT_STS2_GPIO0_R_IT_SHIFT                      1
-#define TPS65910_INT_STS2_GPIO0_R_IT_MASK                       0x01
-
-#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT                  2
-#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK                   0x02
-#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT                  1
-#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK                   0x01
 
 /*Register INT_STS  (0x80) register.RegisterDescription */
 #define INT_STS_RTC_PERIOD_IT_MASK                      0x80
@@ -623,16 +565,16 @@
 #define INT_STS_RTC_ALARM_IT_SHIFT                      6
 #define INT_STS_HOTDIE_IT_MASK                          0x20
 #define INT_STS_HOTDIE_IT_SHIFT                         5
-#define INT_STS_PWRHOLD_R_IT_MASK                       0x10
-#define INT_STS_PWRHOLD_R_IT_SHIFT                      4
+#define INT_STS_PWRHOLD_IT_MASK                         0x10
+#define INT_STS_PWRHOLD_IT_SHIFT                        4
 #define INT_STS_PWRON_LP_IT_MASK                        0x08
 #define INT_STS_PWRON_LP_IT_SHIFT                       3
 #define INT_STS_PWRON_IT_MASK                           0x04
 #define INT_STS_PWRON_IT_SHIFT                          2
 #define INT_STS_VMBHI_IT_MASK                           0x02
 #define INT_STS_VMBHI_IT_SHIFT                          1
-#define INT_STS_PWRHOLD_F_IT_MASK                       0x01
-#define INT_STS_PWRHOLD_F_IT_SHIFT                      0
+#define INT_STS_VMBDCH_IT_MASK                          0x01
+#define INT_STS_VMBDCH_IT_SHIFT                         0
 
 
 /*Register INT_MSK  (0x80) register.RegisterDescription */
@@ -642,16 +584,16 @@
 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT                  6
 #define INT_MSK_HOTDIE_IT_MSK_MASK                      0x20
 #define INT_MSK_HOTDIE_IT_MSK_SHIFT                     5
-#define INT_MSK_PWRHOLD_R_IT_MSK_MASK                   0x10
-#define INT_MSK_PWRHOLD_R_IT_MSK_SHIFT                  4
+#define INT_MSK_PWRHOLD_IT_MSK_MASK                     0x10
+#define INT_MSK_PWRHOLD_IT_MSK_SHIFT                    4
 #define INT_MSK_PWRON_LP_IT_MSK_MASK                    0x08
 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT                   3
 #define INT_MSK_PWRON_IT_MSK_MASK                       0x04
 #define INT_MSK_PWRON_IT_MSK_SHIFT                      2
 #define INT_MSK_VMBHI_IT_MSK_MASK                       0x02
 #define INT_MSK_VMBHI_IT_MSK_SHIFT                      1
-#define INT_MSK_PWRHOLD_F_IT_MSK_MASK                   0x01
-#define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT                  0
+#define INT_MSK_VMBDCH_IT_MSK_MASK                      0x01
+#define INT_MSK_VMBDCH_IT_MSK_SHIFT                     0
 
 
 /*Register INT_STS2  (0x80) register.RegisterDescription */
@@ -693,14 +635,6 @@
 
 
 /*Register INT_STS3  (0x80) register.RegisterDescription */
-#define INT_STS3_PWRDN_IT_MASK                          0x80
-#define INT_STS3_PWRDN_IT_SHIFT                         7
-#define INT_STS3_VMBCH2_L_IT_MASK                       0x40
-#define INT_STS3_VMBCH2_L_IT_SHIFT                      6
-#define INT_STS3_VMBCH2_H_IT_MASK                       0x20
-#define INT_STS3_VMBCH2_H_IT_SHIFT                      5
-#define INT_STS3_WTCHDG_IT_MASK                         0x10
-#define INT_STS3_WTCHDG_IT_SHIFT                        4
 #define INT_STS3_GPIO5_F_IT_MASK                        0x08
 #define INT_STS3_GPIO5_F_IT_SHIFT                       3
 #define INT_STS3_GPIO5_R_IT_MASK                        0x04
@@ -712,14 +646,6 @@
 
 
 /*Register INT_MSK3  (0x80) register.RegisterDescription */
-#define INT_MSK3_PWRDN_IT_MSK_MASK                      0x80
-#define INT_MSK3_PWRDN_IT_MSK_SHIFT                     7
-#define INT_MSK3_VMBCH2_L_IT_MSK_MASK                   0x40
-#define INT_MSK3_VMBCH2_L_IT_MSK_SHIFT                  6
-#define INT_MSK3_VMBCH2_H_IT_MSK_MASK                   0x20
-#define INT_MSK3_VMBCH2_H_IT_MSK_SHIFT                  5
-#define INT_MSK3_WTCHDG_IT_MSK_MASK                     0x10
-#define INT_MSK3_WTCHDG_IT_MSK_SHIFT                    4
 #define INT_MSK3_GPIO5_F_IT_MSK_MASK                    0x08
 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT                   3
 #define INT_MSK3_GPIO5_R_IT_MSK_MASK                    0x04
@@ -780,32 +706,34 @@
 #define TPS65910_IRQ_GPIO_F                             9
 #define TPS65910_NUM_IRQ                                10
 
-#define TPS65911_IRQ_PWRHOLD_F                          0
-#define TPS65911_IRQ_VBAT_VMHI                          1
-#define TPS65911_IRQ_PWRON                              2
-#define TPS65911_IRQ_PWRON_LP                           3
-#define TPS65911_IRQ_PWRHOLD_R                          4
-#define TPS65911_IRQ_HOTDIE                             5
-#define TPS65911_IRQ_RTC_ALARM                          6
-#define TPS65911_IRQ_RTC_PERIOD                         7
-#define TPS65911_IRQ_GPIO0_R                            8
-#define TPS65911_IRQ_GPIO0_F                            9
-#define TPS65911_IRQ_GPIO1_R                            10
-#define TPS65911_IRQ_GPIO1_F                            11
-#define TPS65911_IRQ_GPIO2_R                            12
-#define TPS65911_IRQ_GPIO2_F                            13
-#define TPS65911_IRQ_GPIO3_R                            14
-#define TPS65911_IRQ_GPIO3_F                            15
-#define TPS65911_IRQ_GPIO4_R                            16
-#define TPS65911_IRQ_GPIO4_F                            17
-#define TPS65911_IRQ_GPIO5_R                            18
-#define TPS65911_IRQ_GPIO5_F                            19
-#define TPS65911_IRQ_WTCHDG                             20
-#define TPS65911_IRQ_VMBCH2_H                           21
-#define TPS65911_IRQ_VMBCH2_L                           22
-#define TPS65911_IRQ_PWRDN                              23
-
-#define TPS65911_NUM_IRQ                                24
+#define TPS65911_IRQ_VBAT_VMBDCH                        0
+#define TPS65911_IRQ_VBAT_VMBDCH2L                      1
+#define TPS65911_IRQ_VBAT_VMBDCH2H                      2
+#define TPS65911_IRQ_VBAT_VMHI                          3
+#define TPS65911_IRQ_PWRON                              4
+#define TPS65911_IRQ_PWRON_LP                           5
+#define TPS65911_IRQ_PWRHOLD_F                          6
+#define TPS65911_IRQ_PWRHOLD_R                          7
+#define TPS65911_IRQ_HOTDIE                             8
+#define TPS65911_IRQ_RTC_ALARM                          9
+#define TPS65911_IRQ_RTC_PERIOD                         10
+#define TPS65911_IRQ_GPIO0_R                            11
+#define TPS65911_IRQ_GPIO0_F                            12
+#define TPS65911_IRQ_GPIO1_R                            13
+#define TPS65911_IRQ_GPIO1_F                            14
+#define TPS65911_IRQ_GPIO2_R                            15
+#define TPS65911_IRQ_GPIO2_F                            16
+#define TPS65911_IRQ_GPIO3_R                            17
+#define TPS65911_IRQ_GPIO3_F                            18
+#define TPS65911_IRQ_GPIO4_R                            19
+#define TPS65911_IRQ_GPIO4_F                            20
+#define TPS65911_IRQ_GPIO5_R                            21
+#define TPS65911_IRQ_GPIO5_F                            22
+#define TPS65911_IRQ_WTCHDG                             23
+#define TPS65911_IRQ_PWRDN                              24
+
+#define TPS65911_NUM_IRQ                                25
+
 
 /* GPIO Register Definitions */
 #define TPS65910_GPIO_DEB                               BIT(2)
@@ -853,18 +781,6 @@
 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3            0x4
 #define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP          0x8
 
-/*
- * Sleep keepon data: Maintains the state in sleep mode
- * @therm_keepon: Keep on the thermal monitoring in sleep state.
- * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state.
- * @i2chs_keepon: Keep on high speed internal clock in sleep state.
- */
-struct tps65910_sleep_keepon_data {
-        unsigned therm_keepon:1;
-        unsigned clkout32k_keepon:1;
-        unsigned i2chs_keepon:1;
-};
-
 /**
  * struct tps65910_board
  * Board platform data may be used to initialize regulators.
@@ -876,12 +792,8 @@ struct tps65910_board {
         int irq_base;
         int vmbch_threshold;
         int vmbch2_threshold;
-        bool en_ck32k_xtal;
-        bool en_dev_slp;
-        bool pm_off;
-        struct tps65910_sleep_keepon_data *slp_keepon;
-        bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
         unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
+        bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
         struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
 };
 
@@ -893,19 +805,25 @@ struct tps65910 {
         struct device *dev;
         struct i2c_client *i2c_client;
         struct regmap *regmap;
+        struct mutex io_mutex;
         unsigned int id;
+        int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
+        int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
 
         /* Client devices */
         struct tps65910_pmic *pmic;
         struct tps65910_rtc *rtc;
         struct tps65910_power *power;
 
-        /* Device node parsed board data */
-        struct tps65910_board *of_plat_data;
+        /* GPIO Handling */
+        struct gpio_chip gpio;
 
         /* IRQ Handling */
+        struct mutex irq_lock;
         int chip_irq;
-        struct regmap_irq_chip_data *irq_data;
+        int irq_base;
+        int irq_num;
+        u32 irq_mask;
 };
 
 struct tps65910_platform_data {
@@ -913,44 +831,16 @@ struct tps65910_platform_data {
         int irq_base;
 };
 
+int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
+int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
+void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
+int tps65910_irq_init(struct tps65910 *tps65910, int irq,
+                struct tps65910_platform_data *pdata);
+int tps65910_irq_exit(struct tps65910 *tps65910);
+
 static inline int tps65910_chip_id(struct tps65910 *tps65910)
 {
         return tps65910->id;
 }
 
-static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg,
-                unsigned int *val)
-{
-        return regmap_read(tps65910->regmap, reg, val);
-}
-
-static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg,
-                unsigned int val)
-{
-        return regmap_write(tps65910->regmap, reg, val);
-}
-
-static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg,
-                u8 mask)
-{
-        return regmap_update_bits(tps65910->regmap, reg, mask, mask);
-}
-
-static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg,
-                u8 mask)
-{
-        return regmap_update_bits(tps65910->regmap, reg, mask, 0);
-}
-
-static inline int tps65910_reg_update_bits(struct tps65910 *tps65910, u8 reg,
-                                           u8 mask, u8 val)
-{
-        return regmap_update_bits(tps65910->regmap, reg, mask, val);
-}
-
-static inline int tps65910_irq_get_virq(struct tps65910 *tps65910, int irq)
-{
-        return regmap_irq_get_virq(tps65910->irq_data, irq);
-}
-
 #endif /*  __LINUX_MFD_TPS65910_H */
diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h
index 2c75c9c9318..1802dfefef0 100644
--- a/include/linux/mfd/tps80031.h
+++ b/include/linux/mfd/tps80031.h
@@ -1,383 +1,30 @@
 /*
- * tps80031.h -- TI TPS80031 and TI TPS80032 PMIC driver.
+ * include/linux/mfd/tps80031.c
  *
- * Copyright (c) 2012, NVIDIA Corporation.
+ * Core driver interface for TI TPS80031 PMIC
  *
- * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ * Copyright (C) 2011 NVIDIA Corporation
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
- * whether express or implied; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- * 02111-1307, USA
  */
 
 #ifndef __LINUX_MFD_TPS80031_H
 #define __LINUX_MFD_TPS80031_H
 
-#include <linux/device.h>
-#include <linux/regmap.h>
-
-/* Pull-ups/Pull-downs */
-#define TPS80031_CFG_INPUT_PUPD1                        0xF0
-#define TPS80031_CFG_INPUT_PUPD2                        0xF1
-#define TPS80031_CFG_INPUT_PUPD3                        0xF2
-#define TPS80031_CFG_INPUT_PUPD4                        0xF3
-#define TPS80031_CFG_LDO_PD1                            0xF4
-#define TPS80031_CFG_LDO_PD2                            0xF5
-#define TPS80031_CFG_SMPS_PD                            0xF6
-
-/* Real Time Clock */
-#define TPS80031_SECONDS_REG                            0x00
-#define TPS80031_MINUTES_REG                            0x01
-#define TPS80031_HOURS_REG                              0x02
-#define TPS80031_DAYS_REG                               0x03
-#define TPS80031_MONTHS_REG                             0x04
-#define TPS80031_YEARS_REG                              0x05
-#define TPS80031_WEEKS_REG                              0x06
-#define TPS80031_ALARM_SECONDS_REG                      0x08
-#define TPS80031_ALARM_MINUTES_REG                      0x09
-#define TPS80031_ALARM_HOURS_REG                        0x0A
-#define TPS80031_ALARM_DAYS_REG                         0x0B
-#define TPS80031_ALARM_MONTHS_REG                       0x0C
-#define TPS80031_ALARM_YEARS_REG                        0x0D
-#define TPS80031_RTC_CTRL_REG                           0x10
-#define TPS80031_RTC_STATUS_REG                         0x11
-#define TPS80031_RTC_INTERRUPTS_REG                     0x12
-#define TPS80031_RTC_COMP_LSB_REG                       0x13
-#define TPS80031_RTC_COMP_MSB_REG                       0x14
-#define TPS80031_RTC_RESET_STATUS_REG                   0x16
-
-/*PMC Master Module */
-#define TPS80031_PHOENIX_START_CONDITION                0x1F
-#define TPS80031_PHOENIX_MSK_TRANSITION                 0x20
-#define TPS80031_STS_HW_CONDITIONS                      0x21
-#define TPS80031_PHOENIX_LAST_TURNOFF_STS               0x22
-#define TPS80031_VSYSMIN_LO_THRESHOLD                   0x23
-#define TPS80031_VSYSMIN_HI_THRESHOLD                   0x24
-#define TPS80031_PHOENIX_DEV_ON                         0x25
-#define TPS80031_STS_PWR_GRP_STATE                      0x27
-#define TPS80031_PH_CFG_VSYSLOW                         0x28
-#define TPS80031_PH_STS_BOOT                            0x29
-#define TPS80031_PHOENIX_SENS_TRANSITION                0x2A
-#define TPS80031_PHOENIX_SEQ_CFG                        0x2B
-#define TPS80031_PRIMARY_WATCHDOG_CFG                   0X2C
-#define TPS80031_KEY_PRESS_DUR_CFG                      0X2D
-#define TPS80031_SMPS_LDO_SHORT_STS                     0x2E
-
-/* PMC Slave Module - Broadcast */
-#define TPS80031_BROADCAST_ADDR_ALL                     0x31
-#define TPS80031_BROADCAST_ADDR_REF                     0x32
-#define TPS80031_BROADCAST_ADDR_PROV                    0x33
-#define TPS80031_BROADCAST_ADDR_CLK_RST                 0x34
-
-/* PMC Slave Module  SMPS Regulators */
-#define TPS80031_SMPS4_CFG_TRANS                        0x41
-#define TPS80031_SMPS4_CFG_STATE                        0x42
-#define TPS80031_SMPS4_CFG_VOLTAGE                      0x44
-#define TPS80031_VIO_CFG_TRANS                          0x47
-#define TPS80031_VIO_CFG_STATE                          0x48
-#define TPS80031_VIO_CFG_FORCE                          0x49
-#define TPS80031_VIO_CFG_VOLTAGE                        0x4A
-#define TPS80031_VIO_CFG_STEP                           0x48
-#define TPS80031_SMPS1_CFG_TRANS                        0x53
-#define TPS80031_SMPS1_CFG_STATE                        0x54
-#define TPS80031_SMPS1_CFG_FORCE                        0x55
-#define TPS80031_SMPS1_CFG_VOLTAGE                      0x56
-#define TPS80031_SMPS1_CFG_STEP                         0x57
-#define TPS80031_SMPS2_CFG_TRANS                        0x59
-#define TPS80031_SMPS2_CFG_STATE                        0x5A
-#define TPS80031_SMPS2_CFG_FORCE                        0x5B
-#define TPS80031_SMPS2_CFG_VOLTAGE                      0x5C
-#define TPS80031_SMPS2_CFG_STEP                         0x5D
-#define TPS80031_SMPS3_CFG_TRANS                        0x65
-#define TPS80031_SMPS3_CFG_STATE                        0x66
-#define TPS80031_SMPS3_CFG_VOLTAGE                      0x68
-
-/* PMC Slave Module  LDO Regulators */
-#define TPS80031_VANA_CFG_TRANS                         0x81
-#define TPS80031_VANA_CFG_STATE                         0x82
-#define TPS80031_VANA_CFG_VOLTAGE                       0x83
-#define TPS80031_LDO2_CFG_TRANS                         0x85
-#define TPS80031_LDO2_CFG_STATE                         0x86
-#define TPS80031_LDO2_CFG_VOLTAGE                       0x87
-#define TPS80031_LDO4_CFG_TRANS                         0x89
-#define TPS80031_LDO4_CFG_STATE                         0x8A
-#define TPS80031_LDO4_CFG_VOLTAGE                       0x8B
-#define TPS80031_LDO3_CFG_TRANS                         0x8D
-#define TPS80031_LDO3_CFG_STATE                         0x8E
-#define TPS80031_LDO3_CFG_VOLTAGE                       0x8F
-#define TPS80031_LDO6_CFG_TRANS                         0x91
-#define TPS80031_LDO6_CFG_STATE                         0x92
-#define TPS80031_LDO6_CFG_VOLTAGE                       0x93
-#define TPS80031_LDOLN_CFG_TRANS                        0x95
-#define TPS80031_LDOLN_CFG_STATE                        0x96
-#define TPS80031_LDOLN_CFG_VOLTAGE                      0x97
-#define TPS80031_LDO5_CFG_TRANS                         0x99
-#define TPS80031_LDO5_CFG_STATE                         0x9A
-#define TPS80031_LDO5_CFG_VOLTAGE                       0x9B
-#define TPS80031_LDO1_CFG_TRANS                         0x9D
-#define TPS80031_LDO1_CFG_STATE                         0x9E
-#define TPS80031_LDO1_CFG_VOLTAGE                       0x9F
-#define TPS80031_LDOUSB_CFG_TRANS                       0xA1
-#define TPS80031_LDOUSB_CFG_STATE                       0xA2
-#define TPS80031_LDOUSB_CFG_VOLTAGE                     0xA3
-#define TPS80031_LDO7_CFG_TRANS                         0xA5
-#define TPS80031_LDO7_CFG_STATE                         0xA6
-#define TPS80031_LDO7_CFG_VOLTAGE                       0xA7
-
-/* PMC Slave Module  External Control */
-#define TPS80031_REGEN1_CFG_TRANS                       0xAE
-#define TPS80031_REGEN1_CFG_STATE                       0xAF
-#define TPS80031_REGEN2_CFG_TRANS                       0xB1
-#define TPS80031_REGEN2_CFG_STATE                       0xB2
-#define TPS80031_SYSEN_CFG_TRANS                        0xB4
-#define TPS80031_SYSEN_CFG_STATE                        0xB5
-
-/* PMC Slave Module  Internal Control */
-#define TPS80031_NRESPWRON_CFG_TRANS                    0xB7
-#define TPS80031_NRESPWRON_CFG_STATE                    0xB8
-#define TPS80031_CLK32KAO_CFG_TRANS                     0xBA
-#define TPS80031_CLK32KAO_CFG_STATE                     0xBB
-#define TPS80031_CLK32KG_CFG_TRANS                      0xBD
-#define TPS80031_CLK32KG_CFG_STATE                      0xBE
-#define TPS80031_CLK32KAUDIO_CFG_TRANS                  0xC0
-#define TPS80031_CLK32KAUDIO_CFG_STATE                  0xC1
-#define TPS80031_VRTC_CFG_TRANS                         0xC3
-#define TPS80031_VRTC_CFG_STATE                         0xC4
-#define TPS80031_BIAS_CFG_TRANS                         0xC6
-#define TPS80031_BIAS_CFG_STATE                         0xC7
-#define TPS80031_VSYSMIN_HI_CFG_TRANS                   0xC9
-#define TPS80031_VSYSMIN_HI_CFG_STATE                   0xCA
-#define TPS80031_RC6MHZ_CFG_TRANS                       0xCC
-#define TPS80031_RC6MHZ_CFG_STATE                       0xCD
-#define TPS80031_TMP_CFG_TRANS                          0xCF
-#define TPS80031_TMP_CFG_STATE                          0xD0
-
-/* PMC Slave Module  resources assignment */
-#define TPS80031_PREQ1_RES_ASS_A                        0xD7
-#define TPS80031_PREQ1_RES_ASS_B                        0xD8
-#define TPS80031_PREQ1_RES_ASS_C                        0xD9
-#define TPS80031_PREQ2_RES_ASS_A                        0xDA
-#define TPS80031_PREQ2_RES_ASS_B                        0xDB
-#define TPS80031_PREQ2_RES_ASS_C                        0xDC
-#define TPS80031_PREQ3_RES_ASS_A                        0xDD
-#define TPS80031_PREQ3_RES_ASS_B                        0xDE
-#define TPS80031_PREQ3_RES_ASS_C                        0xDF
-
-/* PMC Slave Module  Miscellaneous */
-#define TPS80031_SMPS_OFFSET                            0xE0
-#define TPS80031_SMPS_MULT                              0xE3
-#define TPS80031_MISC1                                  0xE4
-#define TPS80031_MISC2                                  0xE5
-#define TPS80031_BBSPOR_CFG                             0xE6
-#define TPS80031_TMP_CFG                                0xE7
-
-/* Battery Charging Controller and Indicator LED */
-#define TPS80031_CONTROLLER_CTRL2                       0xDA
-#define TPS80031_CONTROLLER_VSEL_COMP                   0xDB
-#define TPS80031_CHARGERUSB_VSYSREG                     0xDC
-#define TPS80031_CHARGERUSB_VICHRG_PC                   0xDD
-#define TPS80031_LINEAR_CHRG_STS                        0xDE
-#define TPS80031_CONTROLLER_INT_MASK                    0xE0
-#define TPS80031_CONTROLLER_CTRL1                       0xE1
-#define TPS80031_CONTROLLER_WDG                         0xE2
-#define TPS80031_CONTROLLER_STAT1                       0xE3
-#define TPS80031_CHARGERUSB_INT_STATUS                  0xE4
-#define TPS80031_CHARGERUSB_INT_MASK                    0xE5
-#define TPS80031_CHARGERUSB_STATUS_INT1                 0xE6
-#define TPS80031_CHARGERUSB_STATUS_INT2                 0xE7
-#define TPS80031_CHARGERUSB_CTRL1                       0xE8
-#define TPS80031_CHARGERUSB_CTRL2                       0xE9
-#define TPS80031_CHARGERUSB_CTRL3                       0xEA
-#define TPS80031_CHARGERUSB_STAT1                       0xEB
-#define TPS80031_CHARGERUSB_VOREG                       0xEC
-#define TPS80031_CHARGERUSB_VICHRG                      0xED
-#define TPS80031_CHARGERUSB_CINLIMIT                    0xEE
-#define TPS80031_CHARGERUSB_CTRLLIMIT1                  0xEF
-#define TPS80031_CHARGERUSB_CTRLLIMIT2                  0xF0
-#define TPS80031_LED_PWM_CTRL1                          0xF4
-#define TPS80031_LED_PWM_CTRL2                          0xF5
-
-/* USB On-The-Go  */
-#define TPS80031_BACKUP_REG                             0xFA
-#define TPS80031_USB_VENDOR_ID_LSB                      0x00
-#define TPS80031_USB_VENDOR_ID_MSB                      0x01
-#define TPS80031_USB_PRODUCT_ID_LSB                     0x02
-#define TPS80031_USB_PRODUCT_ID_MSB                     0x03
-#define TPS80031_USB_VBUS_CTRL_SET                      0x04
-#define TPS80031_USB_VBUS_CTRL_CLR                      0x05
-#define TPS80031_USB_ID_CTRL_SET                        0x06
-#define TPS80031_USB_ID_CTRL_CLR                        0x07
-#define TPS80031_USB_VBUS_INT_SRC                       0x08
-#define TPS80031_USB_VBUS_INT_LATCH_SET                 0x09
-#define TPS80031_USB_VBUS_INT_LATCH_CLR                 0x0A
-#define TPS80031_USB_VBUS_INT_EN_LO_SET                 0x0B
-#define TPS80031_USB_VBUS_INT_EN_LO_CLR                 0x0C
-#define TPS80031_USB_VBUS_INT_EN_HI_SET                 0x0D
-#define TPS80031_USB_VBUS_INT_EN_HI_CLR                 0x0E
-#define TPS80031_USB_ID_INT_SRC                         0x0F
-#define TPS80031_USB_ID_INT_LATCH_SET                   0x10
-#define TPS80031_USB_ID_INT_LATCH_CLR                   0x11
-#define TPS80031_USB_ID_INT_EN_LO_SET                   0x12
-#define TPS80031_USB_ID_INT_EN_LO_CLR                   0x13
-#define TPS80031_USB_ID_INT_EN_HI_SET                   0x14
-#define TPS80031_USB_ID_INT_EN_HI_CLR                   0x15
-#define TPS80031_USB_OTG_ADP_CTRL                       0x16
-#define TPS80031_USB_OTG_ADP_HIGH                       0x17
-#define TPS80031_USB_OTG_ADP_LOW                        0x18
-#define TPS80031_USB_OTG_ADP_RISE                       0x19
-#define TPS80031_USB_OTG_REVISION                       0x1A
-
-/* Gas Gauge */
-#define TPS80031_FG_REG_00                              0xC0
-#define TPS80031_FG_REG_01                              0xC1
-#define TPS80031_FG_REG_02                              0xC2
-#define TPS80031_FG_REG_03                              0xC3
-#define TPS80031_FG_REG_04                              0xC4
-#define TPS80031_FG_REG_05                              0xC5
-#define TPS80031_FG_REG_06                              0xC6
-#define TPS80031_FG_REG_07                              0xC7
-#define TPS80031_FG_REG_08                              0xC8
-#define TPS80031_FG_REG_09                              0xC9
-#define TPS80031_FG_REG_10                              0xCA
-#define TPS80031_FG_REG_11                              0xCB
-
-/* General Purpose ADC */
-#define TPS80031_GPADC_CTRL                             0x2E
-#define TPS80031_GPADC_CTRL2                            0x2F
-#define TPS80031_RTSELECT_LSB                           0x32
-#define TPS80031_RTSELECT_ISB                           0x33
-#define TPS80031_RTSELECT_MSB                           0x34
-#define TPS80031_GPSELECT_ISB                           0x35
-#define TPS80031_CTRL_P1                                0x36
-#define TPS80031_RTCH0_LSB                              0x37
-#define TPS80031_RTCH0_MSB                              0x38
-#define TPS80031_RTCH1_LSB                              0x39
-#define TPS80031_RTCH1_MSB                              0x3A
-#define TPS80031_GPCH0_LSB                              0x3B
-#define TPS80031_GPCH0_MSB                              0x3C
-
-/* SIM, MMC and Battery Detection */
-#define TPS80031_SIMDEBOUNCING                          0xEB
-#define TPS80031_SIMCTRL                                0xEC
-#define TPS80031_MMCDEBOUNCING                          0xED
-#define TPS80031_MMCCTRL                                0xEE
-#define TPS80031_BATDEBOUNCING                          0xEF
-
-/* Vibrator Driver and PWMs */
-#define TPS80031_VIBCTRL                                0x9B
-#define TPS80031_VIBMODE                                0x9C
-#define TPS80031_PWM1ON                                 0xBA
-#define TPS80031_PWM1OFF                                0xBB
-#define TPS80031_PWM2ON                                 0xBD
-#define TPS80031_PWM2OFF                                0xBE
-
-/* Control Interface */
-#define TPS80031_INT_STS_A                              0xD0
-#define TPS80031_INT_STS_B                              0xD1
-#define TPS80031_INT_STS_C                              0xD2
-#define TPS80031_INT_MSK_LINE_A                         0xD3
-#define TPS80031_INT_MSK_LINE_B                         0xD4
-#define TPS80031_INT_MSK_LINE_C                         0xD5
-#define TPS80031_INT_MSK_STS_A                          0xD6
-#define TPS80031_INT_MSK_STS_B                          0xD7
-#define TPS80031_INT_MSK_STS_C                          0xD8
-#define TPS80031_TOGGLE1                                0x90
-#define TPS80031_TOGGLE2                                0x91
-#define TPS80031_TOGGLE3                                0x92
-#define TPS80031_PWDNSTATUS1                            0x93
-#define TPS80031_PWDNSTATUS2                            0x94
-#define TPS80031_VALIDITY0                              0x17
-#define TPS80031_VALIDITY1                              0x18
-#define TPS80031_VALIDITY2                              0x19
-#define TPS80031_VALIDITY3                              0x1A
-#define TPS80031_VALIDITY4                              0x1B
-#define TPS80031_VALIDITY5                              0x1C
-#define TPS80031_VALIDITY6                              0x1D
-#define TPS80031_VALIDITY7                              0x1E
-
-/* Version number related register */
-#define TPS80031_JTAGVERNUM                             0x87
-#define TPS80031_EPROM_REV                              0xDF
-
-/* GPADC Trimming Bits. */
-#define TPS80031_GPADC_TRIM0                            0xCC
-#define TPS80031_GPADC_TRIM1                            0xCD
-#define TPS80031_GPADC_TRIM2                            0xCE
-#define TPS80031_GPADC_TRIM3                            0xCF
-#define TPS80031_GPADC_TRIM4                            0xD0
-#define TPS80031_GPADC_TRIM5                            0xD1
-#define TPS80031_GPADC_TRIM6                            0xD2
-#define TPS80031_GPADC_TRIM7                            0xD3
-#define TPS80031_GPADC_TRIM8                            0xD4
-#define TPS80031_GPADC_TRIM9                            0xD5
-#define TPS80031_GPADC_TRIM10                           0xD6
-#define TPS80031_GPADC_TRIM11                           0xD7
-#define TPS80031_GPADC_TRIM12                           0xD8
-#define TPS80031_GPADC_TRIM13                           0xD9
-#define TPS80031_GPADC_TRIM14                           0xDA
-#define TPS80031_GPADC_TRIM15                           0xDB
-#define TPS80031_GPADC_TRIM16                           0xDC
-#define TPS80031_GPADC_TRIM17                           0xDD
-#define TPS80031_GPADC_TRIM18                           0xDE
-
-/* TPS80031_CONTROLLER_STAT1 bit fields */
-#define TPS80031_CONTROLLER_STAT1_BAT_TEMP              0
-#define TPS80031_CONTROLLER_STAT1_BAT_REMOVED           1
-#define TPS80031_CONTROLLER_STAT1_VBUS_DET              2
-#define TPS80031_CONTROLLER_STAT1_VAC_DET               3
-#define TPS80031_CONTROLLER_STAT1_FAULT_WDG             4
-#define TPS80031_CONTROLLER_STAT1_LINCH_GATED           6
-/* TPS80031_CONTROLLER_INT_MASK bit filed */
-#define TPS80031_CONTROLLER_INT_MASK_MVAC_DET           0
-#define TPS80031_CONTROLLER_INT_MASK_MVBUS_DET          1
-#define TPS80031_CONTROLLER_INT_MASK_MBAT_TEMP          2
-#define TPS80031_CONTROLLER_INT_MASK_MFAULT_WDG         3
-#define TPS80031_CONTROLLER_INT_MASK_MBAT_REMOVED       4
-#define TPS80031_CONTROLLER_INT_MASK_MLINCH_GATED       5
-
-#define TPS80031_CHARGE_CONTROL_SUB_INT_MASK            0x3F
-
-/* TPS80031_PHOENIX_DEV_ON bit field */
-#define TPS80031_DEVOFF                                 0x1
-
-#define TPS80031_EXT_CONTROL_CFG_TRANS                  0
-#define TPS80031_EXT_CONTROL_CFG_STATE                  1
-
-/* State register field */
-#define TPS80031_STATE_OFF                              0x00
-#define TPS80031_STATE_ON                               0x01
-#define TPS80031_STATE_MASK                             0x03
-
-/* Trans register field */
-#define TPS80031_TRANS_ACTIVE_OFF                       0x00
-#define TPS80031_TRANS_ACTIVE_ON                        0x01
-#define TPS80031_TRANS_ACTIVE_MASK                      0x03
-#define TPS80031_TRANS_SLEEP_OFF                        0x00
-#define TPS80031_TRANS_SLEEP_ON                         0x04
-#define TPS80031_TRANS_SLEEP_MASK                       0x0C
-#define TPS80031_TRANS_OFF_OFF                          0x00
-#define TPS80031_TRANS_OFF_ACTIVE                       0x10
-#define TPS80031_TRANS_OFF_MASK                         0x30
-
-#define TPS80031_EXT_PWR_REQ            (TPS80031_PWR_REQ_INPUT_PREQ1 | \
-                                        TPS80031_PWR_REQ_INPUT_PREQ2 | \
-                                        TPS80031_PWR_REQ_INPUT_PREQ3)
-
-/* TPS80031_BBSPOR_CFG bit field */
-#define TPS80031_BBSPOR_CHG_EN                          0x8
-#define TPS80031_MAX_REGISTER                           0xFF
-
-struct i2c_client;
+#include <linux/rtc.h>
 
 /* Supported chips */
 enum chips {
@@ -421,217 +68,136 @@ enum {
         TPS80031_INT_NR,
 };
 
-/* TPS80031 Slave IDs */
-#define TPS80031_NUM_SLAVES                             4
-#define TPS80031_SLAVE_ID0                              0
-#define TPS80031_SLAVE_ID1                              1
-#define TPS80031_SLAVE_ID2                              2
-#define TPS80031_SLAVE_ID3                              3
+enum adc_channel {
+        BATTERY_TYPE                    = 0,  /* External ADC */
+        BATTERY_TEMPERATURE             = 1,  /* External ADC */
+        AUDIO_ACCESSORY                 = 2,  /* External ADC */
+        TEMPERATURE_EXTERNAL_DIODE      = 3,  /* External ADC */
+        TEMPERATURE_MEASUREMENT         = 4,  /* External ADC */
+        GENERAL_PURPOSE_1               = 5,  /* External ADC */
+        GENERAL_PURPOSE_2               = 6,  /* External ADC */
+        SYSTEM_SUPPLY                   = 7,  /* Internal ADC */
+        BACKUP_BATTERY                  = 8,  /* Internal ADC */
+        EXTERNAL_CHARGER_INPUT          = 9,  /* Internal ADC */
+        VBUS                            = 10, /* Internal ADC */
+        VBUS_DCDC_OUTPUT_CURRENT        = 11, /* Internal ADC */
+        DIE_TEMPERATURE_1               = 12, /* Internal ADC */
+        DIE_TEMPERATURE_2               = 13, /* Internal ADC */
+        USB_ID_LINE                     = 14, /* Internal ADC */
+        TEST_NETWORK_1                  = 15, /* Internal ADC */
+        TEST_NETWORK_2                  = 16, /* Internal ADC */
+        BATTERY_CHARGING_CURRENT        = 17, /* Internal ADC */
+        BATTERY_VOLTAGE                 = 18, /* Internal ADC */
+};
 
-/* TPS80031 I2C addresses */
-#define TPS80031_I2C_ID0_ADDR                           0x12
-#define TPS80031_I2C_ID1_ADDR                           0x48
-#define TPS80031_I2C_ID2_ADDR                           0x49
-#define TPS80031_I2C_ID3_ADDR                           0x4A
+enum TPS80031_GPIO {
+        TPS80031_GPIO_REGEN1,
+        TPS80031_GPIO_REGEN2,
+        TPS80031_GPIO_SYSEN,
 
-enum {
-        TPS80031_REGULATOR_VIO,
-        TPS80031_REGULATOR_SMPS1,
-        TPS80031_REGULATOR_SMPS2,
-        TPS80031_REGULATOR_SMPS3,
-        TPS80031_REGULATOR_SMPS4,
-        TPS80031_REGULATOR_VANA,
-        TPS80031_REGULATOR_LDO1,
-        TPS80031_REGULATOR_LDO2,
-        TPS80031_REGULATOR_LDO3,
-        TPS80031_REGULATOR_LDO4,
-        TPS80031_REGULATOR_LDO5,
-        TPS80031_REGULATOR_LDO6,
-        TPS80031_REGULATOR_LDO7,
-        TPS80031_REGULATOR_LDOLN,
-        TPS80031_REGULATOR_LDOUSB,
-        TPS80031_REGULATOR_VBUS,
-        TPS80031_REGULATOR_REGEN1,
-        TPS80031_REGULATOR_REGEN2,
-        TPS80031_REGULATOR_SYSEN,
-        TPS80031_REGULATOR_MAX,
+        /* Last entry */
+        TPS80031_GPIO_NR,
 };
 
-/* Different configurations for the rails */
-enum {
-        /* USBLDO input selection */
-        TPS80031_USBLDO_INPUT_VSYS              = 0x00000001,
-        TPS80031_USBLDO_INPUT_PMID              = 0x00000002,
-
-        /* LDO3 output mode */
-        TPS80031_LDO3_OUTPUT_VIB                = 0x00000004,
+enum TPS80031_CLOCK32K {
+        TPS80031_CLOCK32K_AO,
+        TPS80031_CLOCK32K_G,
+        TPS80031_CLOCK32K_AUDIO,
 
-        /* VBUS configuration */
-        TPS80031_VBUS_DISCHRG_EN_PDN            = 0x00000004,
-        TPS80031_VBUS_SW_ONLY                   = 0x00000008,
-        TPS80031_VBUS_SW_N_ID                   = 0x00000010,
+        /* Last entry */
+        TPS80031_CLOCK32K_NR,
 };
 
-/* External controls requests */
-enum tps80031_ext_control {
-        TPS80031_PWR_REQ_INPUT_NONE             = 0x00000000,
-        TPS80031_PWR_REQ_INPUT_PREQ1            = 0x00000001,
-        TPS80031_PWR_REQ_INPUT_PREQ2            = 0x00000002,
-        TPS80031_PWR_REQ_INPUT_PREQ3            = 0x00000004,
-        TPS80031_PWR_OFF_ON_SLEEP               = 0x00000008,
-        TPS80031_PWR_ON_ON_SLEEP                = 0x00000010,
+enum {
+        SLAVE_ID0 = 0,
+        SLAVE_ID1 = 1,
+        SLAVE_ID2 = 2,
+        SLAVE_ID3 = 3,
 };
 
-enum tps80031_pupd_pins {
-        TPS80031_PREQ1 = 0,
-        TPS80031_PREQ2A,
-        TPS80031_PREQ2B,
-        TPS80031_PREQ2C,
-        TPS80031_PREQ3,
-        TPS80031_NRES_WARM,
-        TPS80031_PWM_FORCE,
-        TPS80031_CHRG_EXT_CHRG_STATZ,
-        TPS80031_SIM,
-        TPS80031_MMC,
-        TPS80031_GPADC_START,
-        TPS80031_DVSI2C_SCL,
-        TPS80031_DVSI2C_SDA,
-        TPS80031_CTLI2C_SCL,
-        TPS80031_CTLI2C_SDA,
+enum {
+        I2C_ID0_ADDR = 0x12,
+        I2C_ID1_ADDR = 0x48,
+        I2C_ID2_ADDR = 0x49,
+        I2C_ID3_ADDR = 0x4A,
 };
 
-enum tps80031_pupd_settings {
-        TPS80031_PUPD_NORMAL,
-        TPS80031_PUPD_PULLDOWN,
-        TPS80031_PUPD_PULLUP,
+/* External controls requests */
+enum tps80031_ext_control {
+        PWR_REQ_INPUT_NONE      = 0x00000000,
+        PWR_REQ_INPUT_PREQ1     = 0x00000001,
+        PWR_REQ_INPUT_PREQ2     = 0x00000002,
+        PWR_REQ_INPUT_PREQ3     = 0x00000004,
+        PWR_OFF_ON_SLEEP        = 0x00000008,
+        PWR_ON_ON_SLEEP         = 0x00000010,
 };
 
-struct tps80031 {
-        struct device           *dev;
-        unsigned long           chip_info;
-        int                     es_version;
-        struct i2c_client       *clients[TPS80031_NUM_SLAVES];
-        struct regmap           *regmap[TPS80031_NUM_SLAVES];
-        struct regmap_irq_chip_data *irq_data;
+struct tps80031_subdev_info {
+        int             id;
+        const char      *name;
+        void            *platform_data;
 };
 
-struct tps80031_pupd_init_data {
-        int input_pin;
-        int setting;
+struct tps80031_rtc_platform_data {
+        int irq;
+        struct rtc_time time;
 };
 
-/*
- * struct tps80031_regulator_platform_data - tps80031 regulator platform data.
- *
- * @reg_init_data: The regulator init data.
- * @ext_ctrl_flag: External control flag for sleep/power request control.
- * @config_flags: Configuration flag to configure the rails.
- *                It should be ORed of config enums.
- */
+struct tps80031_clk32k_init_data {
+        int clk32k_nr;
+        bool enable;
+        unsigned long ext_ctrl_flag;
+};
 
-struct tps80031_regulator_platform_data {
-        struct regulator_init_data *reg_init_data;
-        unsigned int ext_ctrl_flag;
-        unsigned int config_flags;
+struct tps80031_gpio_init_data {
+        int gpio_nr;
+        unsigned long ext_ctrl_flag;
 };
 
 struct tps80031_platform_data {
+        int num_subdevs;
+        struct tps80031_subdev_info *subdevs;
+        int gpio_base;
         int irq_base;
+        struct tps80031_32kclock_plat_data *clk32k_pdata;
+        struct tps80031_gpio_init_data *gpio_init_data;
+        int gpio_init_data_size;
+        struct tps80031_clk32k_init_data *clk32k_init_data;
+        int clk32k_init_data_size;
         bool use_power_off;
-        struct tps80031_pupd_init_data *pupd_init_data;
-        int pupd_init_data_size;
-        struct tps80031_regulator_platform_data
-                        *regulator_pdata[TPS80031_REGULATOR_MAX];
 };
 
-static inline int tps80031_write(struct device *dev, int sid,
-                int reg, uint8_t val)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
-
-        return regmap_write(tps80031->regmap[sid], reg, val);
-}
-
-static inline int tps80031_writes(struct device *dev, int sid, int reg,
-                int len, uint8_t *val)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
-
-        return regmap_bulk_write(tps80031->regmap[sid], reg, val, len);
-}
-
-static inline int tps80031_read(struct device *dev, int sid,
-                int reg, uint8_t *val)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
-        unsigned int ival;
-        int ret;
-
-        ret = regmap_read(tps80031->regmap[sid], reg, &ival);
-        if (ret < 0) {
-                dev_err(dev, "failed reading from reg 0x%02x\n", reg);
-                return ret;
-        }
-
-        *val = ival;
-        return ret;
-}
-
-static inline int tps80031_reads(struct device *dev, int sid,
-                int reg, int len, uint8_t *val)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
-
-        return regmap_bulk_read(tps80031->regmap[sid], reg, val, len);
-}
-
-static inline int tps80031_set_bits(struct device *dev, int sid,
-                int reg, uint8_t bit_mask)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
-
-        return regmap_update_bits(tps80031->regmap[sid], reg,
-                                bit_mask, bit_mask);
-}
-
-static inline int tps80031_clr_bits(struct device *dev, int sid,
-                int reg, uint8_t bit_mask)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
-
-        return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0);
-}
-
-static inline int tps80031_update(struct device *dev, int sid,
-                int reg, uint8_t val, uint8_t mask)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
-
-        return regmap_update_bits(tps80031->regmap[sid], reg, mask, val);
-}
-
-static inline unsigned long tps80031_get_chip_info(struct device *dev)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
-
-        return tps80031->chip_info;
-}
+struct tps80031_bg_platform_data {
+        int irq_base;
+        int battery_present;
+};
 
-static inline int tps80031_get_pmu_version(struct device *dev)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
+/*
+ * NOTE: the functions below are not intended for use outside
+ * of the TPS80031 sub-device drivers
+ */
+extern int tps80031_write(struct device *dev, int sid, int reg, uint8_t val);
+extern int tps80031_writes(struct device *dev, int sid, int reg, int len,
+                                uint8_t *val);
+extern int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val);
+extern int tps80031_reads(struct device *dev, int sid, int reg, int len,
+                                uint8_t *val);
+extern int tps80031_set_bits(struct device *dev, int sid, int reg,
+                                uint8_t bit_mask);
+extern int tps80031_clr_bits(struct device *dev, int sid, int reg,
+                                uint8_t bit_mask);
+extern int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
+                           uint8_t mask);
+extern int tps80031_force_update(struct device *dev, int sid, int reg,
+                                 uint8_t val, uint8_t mask);
+extern int tps80031_ext_power_req_config(struct device *dev,
+                unsigned long ext_ctrl_flag, int preq_bit,
+                int state_reg_add, int trans_reg_add);
 
-        return tps80031->es_version;
-}
+extern unsigned long tps80031_get_chip_info(struct device *dev);
 
-static inline int tps80031_irq_get_virq(struct device *dev, int irq)
-{
-        struct tps80031 *tps80031 = dev_get_drvdata(dev);
+extern int tps80031_gpadc_conversion(int channle_no);
 
-        return regmap_irq_get_virq(tps80031->irq_data, irq);
-}
+extern int tps80031_get_pmu_version(struct device *dev);
 
-extern int tps80031_ext_power_req_config(struct device *dev,
-                unsigned long ext_ctrl_flag, int preq_bit,
-                int state_reg_add, int trans_reg_add);
 #endif /*__LINUX_MFD_TPS80031_H */
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index 94ac944d12f..4c806f6d663 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -27,7 +27,6 @@
 
 #include <linux/interrupt.h>
 #include <linux/mfd/core.h>
-#include <linux/regulator/consumer.h>
 
 #define TWL6040_REG_ASICID              0x01
 #define TWL6040_REG_ASICREV             0x02
@@ -69,6 +68,11 @@
 #define TWL6040_REG_ACCCTL              0x2D
 #define TWL6040_REG_STATUS              0x2E
 
+#define TWL6040_CACHEREGNUM             (TWL6040_REG_STATUS + 1)
+
+#define TWL6040_VIOREGNUM               18
+#define TWL6040_VDDREGNUM               21
+
 /* INTID (0x03) fields */
 
 #define TWL6040_THINT                   0x01
@@ -121,29 +125,39 @@
 #define TWL6040_LPLLFIN                 0x08
 #define TWL6040_HPLLSEL                 0x10
 
-/* HSLCTL/R (0x10/0x11) fields */
+/* HSLCTL (0x10) fields */
+
+#define TWL6040_HSDACMODEL              0x02
+#define TWL6040_HSDRVMODEL              0x08
 
-#define TWL6040_HSDACENA                (1 << 0)
-#define TWL6040_HSDACMODE               (1 << 1)
-#define TWL6040_HSDRVMODE               (1 << 3)
+/* HSRCTL (0x11) fields */
 
-/* VIBCTLL/R (0x18/0x1A) fields */
+#define TWL6040_HSDACMODER              0x02
+#define TWL6040_HSDRVMODER              0x08
 
-#define TWL6040_VIBENA                  (1 << 0)
-#define TWL6040_VIBSEL                  (1 << 1)
-#define TWL6040_VIBCTRL                 (1 << 2)
-#define TWL6040_VIBCTRL_P               (1 << 3)
-#define TWL6040_VIBCTRL_N               (1 << 4)
+/* VIBCTLL (0x18) fields */
 
-/* VIBDATL/R (0x19/0x1B) fields */
+#define TWL6040_VIBENAL                 0x01
+#define TWL6040_VIBCTRLL                0x04
+#define TWL6040_VIBCTRLLP               0x08
+#define TWL6040_VIBCTRLLN               0x10
+
+/* VIBDATL (0x19) fields */
 
 #define TWL6040_VIBDAT_MAX              0x64
 
+/* VIBCTLR (0x1A) fields */
+
+#define TWL6040_VIBENAR                 0x01
+#define TWL6040_VIBCTRLR                0x04
+#define TWL6040_VIBCTRLRP               0x08
+#define TWL6040_VIBCTRLRN               0x10
+
 /* GPOCTL (0x1E) fields */
 
 #define TWL6040_GPO1                    0x01
 #define TWL6040_GPO2                    0x02
-#define TWL6040_GPO3                    0x04
+#define TWL6040_GPO3                    0x03
 
 /* ACCCTL (0x2D) fields */
 
@@ -158,12 +172,11 @@
 #define TWL6040_VIBROCDET               0x20
 #define TWL6040_TSHUTDET                0x40
 
-#define TWL6040_CELLS                   3
+#define TWL6040_CELLS                   2
 
 #define TWL6040_REV_ES1_0               0x00
-#define TWL6040_REV_ES1_1               0x01 /* Rev ES1.1 and ES1.2 */
-#define TWL6040_REV_ES1_3               0x02
-#define TWL6041_REV_ES2_0               0x10
+#define TWL6040_REV_ES1_1               0x01
+#define TWL6040_REV_ES1_2               0x02
 
 #define TWL6040_IRQ_TH                  0
 #define TWL6040_IRQ_PLUG                1
@@ -176,45 +189,10 @@
 #define TWL6040_SYSCLK_SEL_LPPLL        0
 #define TWL6040_SYSCLK_SEL_HPPLL        1
 
-#define TWL6040_GPO_MAX 3
-
-struct twl6040_codec_data {
-        u16 hs_left_step;
-        u16 hs_right_step;
-        u16 hf_left_step;
-        u16 hf_right_step;
-};
-
-struct twl6040_vibra_data {
-        unsigned int vibldrv_res;       /* left driver resistance */
-        unsigned int vibrdrv_res;       /* right driver resistance */
-        unsigned int viblmotor_res;     /* left motor resistance */
-        unsigned int vibrmotor_res;     /* right motor resistance */
-        int vddvibl_uV;                 /* VDDVIBL volt, set 0 for fixed reg */
-        int vddvibr_uV;                 /* VDDVIBR volt, set 0 for fixed reg */
-};
-
-struct twl6040_gpo_data {
-        int gpio_base;
-};
-
-struct twl6040_platform_data {
-        int audpwron_gpio;      /* audio power-on gpio */
-
-        struct twl6040_codec_data *codec;
-        struct twl6040_vibra_data *vibra;
-        struct twl6040_gpo_data *gpo;
-};
-
-struct regmap;
-struct regmap_irq_chips_data;
-
 struct twl6040 {
         struct device *dev;
-        struct regmap *regmap;
-        struct regmap_irq_chip_data *irq_data;
-        struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
         struct mutex mutex;
+        struct mutex io_mutex;
         struct mutex irq_mutex;
         struct mfd_cell cells[TWL6040_CELLS];
         struct completion ready;
@@ -222,16 +200,14 @@ struct twl6040 {
         int audpwron;
         int power_count;
         int rev;
-        u8 vibra_ctrl_cache[2];
 
-        /* PLL configuration */
         int pll;
         unsigned int sysclk;
-        unsigned int mclk;
 
         unsigned int irq;
-        unsigned int irq_ready;
-        unsigned int irq_th;
+        unsigned int irq_base;
+        u8 irq_masks_cur;
+        u8 irq_masks_cache;
 };
 
 int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
@@ -246,14 +222,7 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
                     unsigned int freq_in, unsigned int freq_out);
 int twl6040_get_pll(struct twl6040 *twl6040);
 unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
-
-/* Get the combined status of the vibra control register */
-int twl6040_get_vibralr_status(struct twl6040 *twl6040);
-
-static inline int twl6040_get_revid(struct twl6040 *twl6040)
-{
-        return twl6040->rev;
-}
-
+int twl6040_irq_init(struct twl6040 *twl6040);
+void twl6040_irq_exit(struct twl6040 *twl6040);
 
 #endif  /* End of __TWL6040_CODEC_H__ */
diff --git a/include/linux/mfd/ucb1x00.h b/include/linux/mfd/ucb1x00.h
index 28af4175636..4321f044d1e 100644
--- a/include/linux/mfd/ucb1x00.h
+++ b/include/linux/mfd/ucb1x00.h
@@ -12,7 +12,7 @@
 
 #include <linux/mfd/mcp.h>
 #include <linux/gpio.h>
-#include <linux/mutex.h>
+#include <linux/semaphore.h>
 
 #define UCB_IO_DATA     0x00
 #define UCB_IO_DIR      0x01
@@ -104,27 +104,17 @@
 #define UCB_MODE_DYN_VFLAG_ENA  (1 << 12)
 #define UCB_MODE_AUD_OFF_CAN    (1 << 13)
 
-enum ucb1x00_reset {
-        UCB_RST_PROBE,
-        UCB_RST_RESUME,
-        UCB_RST_SUSPEND,
-        UCB_RST_REMOVE,
-        UCB_RST_PROBE_FAIL,
-};
 
-struct ucb1x00_plat_data {
-        void                    (*reset)(enum ucb1x00_reset);
-        unsigned                irq_base;
-        int                     gpio_base;
-        unsigned                can_wakeup;
+struct ucb1x00_irq {
+        void *devid;
+        void (*fn)(int, void *);
 };
 
 struct ucb1x00 {
-        raw_spinlock_t          irq_lock;
+        spinlock_t              lock;
         struct mcp              *mcp;
         unsigned int            irq;
-        int                     irq_base;
-        struct mutex            adc_mutex;
+        struct semaphore        adc_sem;
         spinlock_t              io_lock;
         u16                     id;
         u16                     io_dir;
@@ -132,8 +122,7 @@ struct ucb1x00 {
         u16                     adc_cr;
         u16                     irq_fal_enbl;
         u16                     irq_ris_enbl;
-        u16                     irq_mask;
-        u16                     irq_wake;
+        struct ucb1x00_irq      irq_handler[16];
         struct device           dev;
         struct list_head        node;
         struct list_head        devs;
@@ -155,7 +144,7 @@ struct ucb1x00_driver {
         struct list_head        devs;
         int     (*add)(struct ucb1x00_dev *dev);
         void    (*remove)(struct ucb1x00_dev *dev);
-        int     (*suspend)(struct ucb1x00_dev *dev);
+        int     (*suspend)(struct ucb1x00_dev *dev, pm_message_t state);
         int     (*resume)(struct ucb1x00_dev *dev);
 };
 
@@ -256,4 +245,15 @@ unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
 void ucb1x00_adc_enable(struct ucb1x00 *ucb);
 void ucb1x00_adc_disable(struct ucb1x00 *ucb);
 
+/*
+ * Which edges of the IRQ do you want to control today?
+ */
+#define UCB_RISING      (1 << 0)
+#define UCB_FALLING     (1 << 1)
+
+int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid);
+void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
+void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
+int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid);
+
 #endif
diff --git a/include/linux/mfd/viperboard.h b/include/linux/mfd/viperboard.h
deleted file mode 100644
index 193452848c0..00000000000
--- a/include/linux/mfd/viperboard.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- *  include/linux/mfd/viperboard.h
- *
- *  Nano River Technologies viperboard definitions
- *
- *  (C) 2012 by Lemonage GmbH
- *  Author: Lars Poeschel <poeschel@lemonage.de>
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __MFD_VIPERBOARD_H__
-#define __MFD_VIPERBOARD_H__
-
-#include <linux/types.h>
-#include <linux/usb.h>
-
-#define VPRBRD_EP_OUT               0x02
-#define VPRBRD_EP_IN                0x86
-
-#define VPRBRD_I2C_MSG_LEN          512 /* max length of a msg on USB level */
-
-#define VPRBRD_I2C_FREQ_6MHZ        1                        /*   6 MBit/s */
-#define VPRBRD_I2C_FREQ_3MHZ        2                        /*   3 MBit/s */
-#define VPRBRD_I2C_FREQ_1MHZ        3                        /*   1 MBit/s */
-#define VPRBRD_I2C_FREQ_FAST        4                        /* 400 kbit/s */
-#define VPRBRD_I2C_FREQ_400KHZ      VPRBRD_I2C_FREQ_FAST
-#define VPRBRD_I2C_FREQ_200KHZ      5                        /* 200 kbit/s */
-#define VPRBRD_I2C_FREQ_STD         6                        /* 100 kbit/s */
-#define VPRBRD_I2C_FREQ_100KHZ      VPRBRD_I2C_FREQ_STD
-#define VPRBRD_I2C_FREQ_10KHZ       7                        /*  10 kbit/s */
-
-#define VPRBRD_I2C_CMD_WRITE        0x00
-#define VPRBRD_I2C_CMD_READ         0x01
-#define VPRBRD_I2C_CMD_ADDR         0x02
-
-#define VPRBRD_USB_TYPE_OUT         0x40
-#define VPRBRD_USB_TYPE_IN          0xc0
-#define VPRBRD_USB_TIMEOUT_MS       100
-#define VPRBRD_USB_REQUEST_I2C_FREQ 0xe6
-#define VPRBRD_USB_REQUEST_I2C      0xe9
-#define VPRBRD_USB_REQUEST_MAJOR    0xea
-#define VPRBRD_USB_REQUEST_MINOR    0xeb
-#define VPRBRD_USB_REQUEST_ADC      0xec
-#define VPRBRD_USB_REQUEST_GPIOA    0xed
-#define VPRBRD_USB_REQUEST_GPIOB    0xdd
-
-struct vprbrd_i2c_write_hdr {
-        u8 cmd;
-        u16 addr;
-        u8 len1;
-        u8 len2;
-        u8 last;
-        u8 chan;
-        u16 spi;
-} __packed;
-
-struct vprbrd_i2c_read_hdr {
-        u8 cmd;
-        u16 addr;
-        u8 len0;
-        u8 len1;
-        u8 len2;
-        u8 len3;
-        u8 len4;
-        u8 len5;
-        u16 tf1;                        /* transfer 1 length */
-        u16 tf2;                        /* transfer 2 length */
-} __packed;
-
-struct vprbrd_i2c_status {
-        u8 unknown[11];
-        u8 status;
-} __packed;
-
-struct vprbrd_i2c_write_msg {
-        struct vprbrd_i2c_write_hdr header;
-        u8 data[VPRBRD_I2C_MSG_LEN
-                - sizeof(struct vprbrd_i2c_write_hdr)];
-} __packed;
-
-struct vprbrd_i2c_read_msg {
-        struct vprbrd_i2c_read_hdr header;
-        u8 data[VPRBRD_I2C_MSG_LEN
-                - sizeof(struct vprbrd_i2c_read_hdr)];
-} __packed;
-
-struct vprbrd_i2c_addr_msg {
-        u8 cmd;
-        u8 addr;
-        u8 unknown1;
-        u16 len;
-        u8 unknown2;
-        u8 unknown3;
-} __packed;
-
-/* Structure to hold all device specific stuff */
-struct vprbrd {
-        struct usb_device *usb_dev; /* the usb device for this device */
-        struct mutex lock;
-        u8 buf[sizeof(struct vprbrd_i2c_write_msg)];
-        struct platform_device pdev;
-};
-
-#endif /* __MFD_VIPERBOARD_H__ */
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 4a3b83a7761..ed8fe0d0409 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -17,7 +17,6 @@
 
 #include <linux/completion.h>
 #include <linux/interrupt.h>
-#include <linux/irqdomain.h>
 #include <linux/list.h>
 #include <linux/regmap.h>
 
@@ -339,7 +338,6 @@
 #define WM831X_FLL_CLK_SRC_WIDTH                     2  /* FLL_CLK_SRC - [1:0] */
 
 struct regulator_dev;
-struct irq_domain;
 
 #define WM831X_NUM_IRQ_REGS 5
 #define WM831X_NUM_GPIO_REGS 16
@@ -369,7 +367,7 @@ struct wm831x {
 
         int irq;  /* Our chip IRQ */
         struct mutex irq_lock;
-        struct irq_domain *irq_domain;
+        int irq_base;
         int irq_masks_cur[WM831X_NUM_IRQ_REGS];   /* Currently active value */
         int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
 
@@ -384,8 +382,6 @@ struct wm831x {
 
         /* Used by the interrupt controller code to post writes */
         int gpio_update[WM831X_NUM_GPIO_REGS];
-        bool gpio_level_high[WM831X_NUM_GPIO_REGS];
-        bool gpio_level_low[WM831X_NUM_GPIO_REGS];
 
         struct mutex auxadc_lock;
         struct list_head auxadc_pending;
@@ -420,11 +416,6 @@ int wm831x_irq_init(struct wm831x *wm831x, int irq);
 void wm831x_irq_exit(struct wm831x *wm831x);
 void wm831x_auxadc_init(struct wm831x *wm831x);
 
-static inline int wm831x_irq(struct wm831x *wm831x, int irq)
-{
-        return irq_create_mapping(wm831x->irq_domain, irq);
-}
-
 extern struct regmap_config wm831x_regmap_config;
 
 #endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index dcc9631b305..1d7a3f7b3b5 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -26,7 +26,7 @@ struct wm831x_backlight_pdata {
 struct wm831x_backup_pdata {
         int charger_enable;
         int no_constant_voltage;  /** Disable constant voltage charging */
-        int vlim;   /** Voltage limit in millivolts */
+        int vlim;   /** Voltage limit in milivolts */
         int ilim;   /** Current limit in microamps */
 };
 
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h
index 509481d9cf1..98fcc977e82 100644
--- a/include/linux/mfd/wm8350/core.h
+++ b/include/linux/mfd/wm8350/core.h
@@ -17,7 +17,6 @@
 #include <linux/mutex.h>
 #include <linux/interrupt.h>
 #include <linux/completion.h>
-#include <linux/regmap.h>
 
 #include <linux/mfd/wm8350/audio.h>
 #include <linux/mfd/wm8350/gpio.h>
@@ -67,9 +66,6 @@
 
 #define WM8350_MAX_REGISTER                     0xFF
 
-#define WM8350_UNLOCK_KEY               0x0013
-#define WM8350_LOCK_KEY                 0x0000
-
 /*
  * Field Definitions.
  */
@@ -586,7 +582,24 @@
 
 #define WM8350_NUM_IRQ_REGS 7
 
-extern const struct regmap_config wm8350_regmap;
+struct wm8350_reg_access {
+        u16 readable;           /* Mask of readable bits */
+        u16 writable;           /* Mask of writable bits */
+        u16 vol;                /* Mask of volatile bits */
+};
+extern const struct wm8350_reg_access wm8350_reg_io_map[];
+extern const u16 wm8350_mode0_defaults[];
+extern const u16 wm8350_mode1_defaults[];
+extern const u16 wm8350_mode2_defaults[];
+extern const u16 wm8350_mode3_defaults[];
+extern const u16 wm8351_mode0_defaults[];
+extern const u16 wm8351_mode1_defaults[];
+extern const u16 wm8351_mode2_defaults[];
+extern const u16 wm8351_mode3_defaults[];
+extern const u16 wm8352_mode0_defaults[];
+extern const u16 wm8352_mode1_defaults[];
+extern const u16 wm8352_mode2_defaults[];
+extern const u16 wm8352_mode3_defaults[];
 
 struct wm8350;
 
@@ -599,8 +612,14 @@ struct wm8350 {
         struct device *dev;
 
         /* device IO */
-        struct regmap *regmap;
-        bool unlocked;
+        union {
+                struct i2c_client *i2c_client;
+                struct spi_device *spi_device;
+        };
+        int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest);
+        int (*write_dev)(struct wm8350 *wm8350, char reg, int size,
+                         void *src);
+        u16 *reg_cache;
 
         struct mutex auxadc_mutex;
         struct completion auxadc_done;
diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h
index 2de565b94d0..0147b696851 100644
--- a/include/linux/mfd/wm8400-private.h
+++ b/include/linux/mfd/wm8400-private.h
@@ -24,14 +24,19 @@
 #include <linux/mfd/wm8400.h>
 #include <linux/mutex.h>
 #include <linux/platform_device.h>
-#include <linux/regmap.h>
+
+struct regmap;
 
 #define WM8400_REGISTER_COUNT 0x55
 
 struct wm8400 {
         struct device *dev;
+
+        struct mutex io_lock;
         struct regmap *regmap;
 
+        u16 reg_cache[WM8400_REGISTER_COUNT];
+
         struct platform_device regulators[6];
 };
 
@@ -925,11 +930,6 @@ struct wm8400 {
 
 u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg);
 int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data);
-
-static inline int wm8400_set_bits(struct wm8400 *wm8400, u8 reg,
-                                  u16 mask, u16 val)
-{
-        return regmap_update_bits(wm8400->regmap, reg, mask, val);
-}
+int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val);
 
 #endif
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index ae5c249530b..45df450d869 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -15,20 +15,16 @@
 #ifndef __MFD_WM8994_CORE_H__
 #define __MFD_WM8994_CORE_H__
 
-#include <linux/mutex.h>
 #include <linux/interrupt.h>
-#include <linux/regmap.h>
-
-#include <linux/mfd/wm8994/pdata.h>
 
 enum wm8994_type {
         WM8994 = 0,
         WM8958 = 1,
-        WM1811 = 2,
 };
 
 struct regulator_dev;
 struct regulator_bulk_data;
+struct regmap;
 
 #define WM8994_NUM_GPIO_REGS 11
 #define WM8994_NUM_LDO_REGS   2
@@ -57,25 +53,22 @@ struct regulator_bulk_data;
 struct wm8994 {
         struct mutex irq_lock;
 
-        struct wm8994_pdata pdata;
-
         enum wm8994_type type;
-        int revision;
-        int cust_id;
 
         struct device *dev;
         struct regmap *regmap;
 
-        bool ldo_ena_always_driven;
-
         int gpio_base;
         int irq_base;
 
         int irq;
-        struct regmap_irq_chip_data *irq_data;
+        u16 irq_masks_cur[WM8994_NUM_IRQ_REGS];
+        u16 irq_masks_cache[WM8994_NUM_IRQ_REGS];
 
         /* Used over suspend/resume */
         bool suspended;
+        u16 ldo_regs[WM8994_NUM_LDO_REGS];
+        u16 gpio_regs[WM8994_NUM_GPIO_REGS];
 
         struct regulator_dev *dbvdd;
         int num_supplies;
@@ -99,17 +92,17 @@ static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq,
                                      irq_handler_t handler, const char *name,
                                      void *data)
 {
-        if (!wm8994->irq_data)
+        if (!wm8994->irq_base)
                 return -EINVAL;
-        return request_threaded_irq(regmap_irq_get_virq(wm8994->irq_data, irq),
-                                    NULL, handler, IRQF_TRIGGER_RISING, name,
+        return request_threaded_irq(wm8994->irq_base + irq, NULL, handler,
+                                    IRQF_TRIGGER_RISING, name,
                                     data);
 }
 static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data)
 {
-        if (!wm8994->irq_data)
+        if (!wm8994->irq_base)
                 return;
-        free_irq(regmap_irq_get_virq(wm8994->irq_data, irq), data);
+        free_irq(wm8994->irq_base + irq, data);
 }
 
 int wm8994_irq_init(struct wm8994 *wm8994);
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 8e21a094836..97cf4f27d64 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -22,7 +22,8 @@ struct wm8994_ldo_pdata {
         /** GPIOs to enable regulator, 0 or less if not available */
         int enable;
 
-        const struct regulator_init_data *init_data;
+        const char *supply;
+        struct regulator_init_data *init_data;
 };
 
 #define WM8994_CONFIGURE_GPIO 0x10000
@@ -112,23 +113,6 @@ struct wm8958_enh_eq_cfg {
         u16 regs[WM8958_ENH_EQ_REGS];
 };
 
-/**
- * Microphone detection rates, used to tune response rates and power
- * consumption for WM8958/WM1811 microphone detection.
- *
- * @sysclk: System clock rate to use this configuration for.
- * @idle: True if this configuration should use when no accessory is detected,
- *        false otherwise.
- * @start: Value for MICD_BIAS_START_TIME register field (not shifted).
- * @rate: Value for MICD_RATE register field (not shifted).
- */
-struct wm8958_micd_rate {
-        int sysclk;
-        bool idle;
-        int start;
-        int rate;
-};
-
 struct wm8994_pdata {
         int gpio_base;
 
@@ -141,7 +125,6 @@ struct wm8994_pdata {
         struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO];
 
         int irq_base;  /** Base IRQ number for WM8994, required for IRQs */
-        unsigned long irq_flags; /** user irq flags */
 
         int num_drc_cfgs;
         struct wm8994_drc_cfg *drc_cfgs;
@@ -161,13 +144,6 @@ struct wm8994_pdata {
         int num_enh_eq_cfgs;
         struct wm8958_enh_eq_cfg *enh_eq_cfgs;
 
-        int num_micd_rates;
-        struct wm8958_micd_rate *micd_rates;
-
-        /* Power up delays to add after microphone bias power up (ms) */
-        int micb1_delay;
-        int micb2_delay;
-
         /* LINEOUT can be differential or single ended */
         unsigned int lineout1_diff:1;
         unsigned int lineout2_diff:1;
@@ -176,11 +152,6 @@ struct wm8994_pdata {
         unsigned int lineout1fb:1;
         unsigned int lineout2fb:1;
 
-        /* Delay between detecting a jack and starting microphone
-         * detect (specified in ms)
-         */
-        int micdet_delay;
-
         /* IRQ for microphone detection if brought out directly as a
          * signal.
          */
@@ -194,27 +165,8 @@ struct wm8994_pdata {
         unsigned int jd_scthr:2;
         unsigned int jd_thr:2;
 
-        /* Configure WM1811 jack detection for use with external capacitor */
-        unsigned int jd_ext_cap:1;
-
         /* WM8958 microphone bias configuration */
         int micbias[2];
-
-        /* WM8958 microphone detection ranges */
-        u16 micd_lvl_sel;
-
-        /* Disable the internal pull downs on the LDOs if they are
-         * always driven (eg, connected to an always on supply or
-         * GPIO that always drives an output.  If they float power
-         * consumption will rise.
-         */
-        bool ldo_ena_always_driven;
-
-        /*
-         * SPKMODE must be pulled internally by the device on this
-         * system.
-         */
-        bool spkmode_pu;
 };
 
 #endif
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h
index 053548961c1..f3ee8428467 100644
--- a/include/linux/mfd/wm8994/registers.h
+++ b/include/linux/mfd/wm8994/registers.h
@@ -72,7 +72,6 @@
 #define WM8994_DC_SERVO_2                       0x55
 #define WM8994_DC_SERVO_4                       0x57
 #define WM8994_DC_SERVO_READBACK                0x58
-#define WM8994_DC_SERVO_4E                      0x59
 #define WM8994_ANALOGUE_HP_1                    0x60
 #define WM8958_MIC_DETECT_1                     0xD0
 #define WM8958_MIC_DETECT_2                     0xD1
@@ -95,15 +94,11 @@
 #define WM8994_FLL1_CONTROL_3                   0x222
 #define WM8994_FLL1_CONTROL_4                   0x223
 #define WM8994_FLL1_CONTROL_5                   0x224
-#define WM8958_FLL1_EFS_1                       0x226
-#define WM8958_FLL1_EFS_2                       0x227
 #define WM8994_FLL2_CONTROL_1                   0x240
 #define WM8994_FLL2_CONTROL_2                   0x241
 #define WM8994_FLL2_CONTROL_3                   0x242
 #define WM8994_FLL2_CONTROL_4                   0x243
 #define WM8994_FLL2_CONTROL_5                   0x244
-#define WM8958_FLL2_EFS_1                       0x246
-#define WM8958_FLL2_EFS_2                       0x247
 #define WM8994_AIF1_CONTROL_1                   0x300
 #define WM8994_AIF1_CONTROL_2                   0x301
 #define WM8994_AIF1_MASTER_SLAVE                0x302
@@ -120,7 +115,6 @@
 #define WM8994_AIF2DAC_LRCLK                    0x315
 #define WM8994_AIF2DAC_DATA                     0x316
 #define WM8994_AIF2ADC_DATA                     0x317
-#define WM1811_AIF2TX_CONTROL                   0x318
 #define WM8958_AIF3_CONTROL_1                   0x320
 #define WM8958_AIF3_CONTROL_2                   0x321
 #define WM8958_AIF3DAC_DATA                     0x322
@@ -139,8 +133,6 @@
 #define WM8994_AIF1_DAC1_FILTERS_2              0x421
 #define WM8994_AIF1_DAC2_FILTERS_1              0x422
 #define WM8994_AIF1_DAC2_FILTERS_2              0x423
-#define WM8958_AIF1_DAC1_NOISE_GATE             0x430
-#define WM8958_AIF1_DAC2_NOISE_GATE             0x431
 #define WM8994_AIF1_DRC1_1                      0x440
 #define WM8994_AIF1_DRC1_2                      0x441
 #define WM8994_AIF1_DRC1_3                      0x442
@@ -171,7 +163,6 @@
 #define WM8994_AIF1_DAC1_EQ_BAND_5_A            0x491
 #define WM8994_AIF1_DAC1_EQ_BAND_5_B            0x492
 #define WM8994_AIF1_DAC1_EQ_BAND_5_PG           0x493
-#define WM8994_AIF1_DAC1_EQ_BAND_1_C            0x494
 #define WM8994_AIF1_DAC2_EQ_GAINS_1             0x4A0
 #define WM8994_AIF1_DAC2_EQ_GAINS_2             0x4A1
 #define WM8994_AIF1_DAC2_EQ_BAND_1_A            0x4A2
@@ -192,7 +183,6 @@
 #define WM8994_AIF1_DAC2_EQ_BAND_5_A            0x4B1
 #define WM8994_AIF1_DAC2_EQ_BAND_5_B            0x4B2
 #define WM8994_AIF1_DAC2_EQ_BAND_5_PG           0x4B3
-#define WM8994_AIF1_DAC2_EQ_BAND_1_C            0x4B4
 #define WM8994_AIF2_ADC_LEFT_VOLUME             0x500
 #define WM8994_AIF2_ADC_RIGHT_VOLUME            0x501
 #define WM8994_AIF2_DAC_LEFT_VOLUME             0x502
@@ -200,7 +190,6 @@
 #define WM8994_AIF2_ADC_FILTERS                 0x510
 #define WM8994_AIF2_DAC_FILTERS_1               0x520
 #define WM8994_AIF2_DAC_FILTERS_2               0x521
-#define WM8958_AIF2_DAC_NOISE_GATE              0x530
 #define WM8994_AIF2_DRC_1                       0x540
 #define WM8994_AIF2_DRC_2                       0x541
 #define WM8994_AIF2_DRC_3                       0x542
@@ -226,7 +215,6 @@
 #define WM8994_AIF2_EQ_BAND_5_A                 0x591
 #define WM8994_AIF2_EQ_BAND_5_B                 0x592
 #define WM8994_AIF2_EQ_BAND_5_PG                0x593
-#define WM8994_AIF2_EQ_BAND_1_C                 0x594
 #define WM8994_DAC1_MIXER_VOLUMES               0x600
 #define WM8994_DAC1_LEFT_MIXER_ROUTING          0x601
 #define WM8994_DAC1_RIGHT_MIXER_ROUTING         0x602
@@ -250,7 +238,6 @@
 #define WM8994_GPIO_4                           0x703
 #define WM8994_GPIO_5                           0x704
 #define WM8994_GPIO_6                           0x705
-#define WM1811_JACKDET_CTRL                     0x705
 #define WM8994_GPIO_7                           0x706
 #define WM8994_GPIO_8                           0x707
 #define WM8994_GPIO_9                           0x708
@@ -273,43 +260,7 @@
 #define WM8958_DSP2_RELEASETIME                 0xA03
 #define WM8958_DSP2_VERMAJMIN                   0xA04
 #define WM8958_DSP2_VERBUILD                    0xA05
-#define WM8958_DSP2_TESTREG                     0xA06
-#define WM8958_DSP2_XORREG                      0xA07
-#define WM8958_DSP2_SHIFTMAXX                   0xA08
-#define WM8958_DSP2_SHIFTMAXY                   0xA09
-#define WM8958_DSP2_SHIFTMAXZ                   0xA0A
-#define WM8958_DSP2_SHIFTMAXEXTLO               0xA0B
-#define WM8958_DSP2_AESSELECT                   0xA0C
 #define WM8958_DSP2_EXECCONTROL                 0xA0D
-#define WM8958_DSP2_SAMPLEBREAK                 0xA0E
-#define WM8958_DSP2_COUNTBREAK                  0xA0F
-#define WM8958_DSP2_INTSTATUS                   0xA10
-#define WM8958_DSP2_EVENTSTATUS                 0xA11
-#define WM8958_DSP2_INTMASK                     0xA12
-#define WM8958_DSP2_CONFIGDWIDTH                0xA13
-#define WM8958_DSP2_CONFIGINSTR                 0xA14
-#define WM8958_DSP2_CONFIGDMEM                  0xA15
-#define WM8958_DSP2_CONFIGDELAYS                0xA16
-#define WM8958_DSP2_CONFIGNUMIO                 0xA17
-#define WM8958_DSP2_CONFIGEXTDEPTH              0xA18
-#define WM8958_DSP2_CONFIGMULTIPLIER            0xA19
-#define WM8958_DSP2_CONFIGCTRLDWIDTH            0xA1A
-#define WM8958_DSP2_CONFIGPIPELINE              0xA1B
-#define WM8958_DSP2_SHIFTMAXEXTHI               0xA1C
-#define WM8958_DSP2_SWVERSIONREG                0xA1D
-#define WM8958_DSP2_CONFIGXMEM                  0xA1E
-#define WM8958_DSP2_CONFIGYMEM                  0xA1F
-#define WM8958_DSP2_CONFIGZMEM                  0xA20
-#define WM8958_FW_BUILD_1                       0x2000
-#define WM8958_FW_BUILD_0                       0x2001
-#define WM8958_FW_ID_1                          0x2002
-#define WM8958_FW_ID_0                          0x2003
-#define WM8958_FW_MAJOR_1                       0x2004
-#define WM8958_FW_MAJOR_0                       0x2005
-#define WM8958_FW_MINOR_1                       0x2006
-#define WM8958_FW_MINOR_0                       0x2007
-#define WM8958_FW_PATCH_1                       0x2008
-#define WM8958_FW_PATCH_0                       0x2009
 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1     0x2200
 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2     0x2201
 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1     0x2202
@@ -378,14 +329,6 @@
 #define WM8958_MBC_B2_PG2_2                     0x242D
 #define WM8958_MBC_B1_PG2_1                     0x242E
 #define WM8958_MBC_B1_PG2_2                     0x242F
-#define WM8958_MBC_CROSSOVER_1                  0x2600
-#define WM8958_MBC_CROSSOVER_2                  0x2601
-#define WM8958_MBC_HPF_1                        0x2602
-#define WM8958_MBC_HPF_2                        0x2603
-#define WM8958_MBC_LPF_1                        0x2606
-#define WM8958_MBC_LPF_2                        0x2607
-#define WM8958_MBC_RMS_LIMIT_1                  0x260A
-#define WM8958_MBC_RMS_LIMIT_2                  0x260B
 #define WM8994_WRITE_SEQUENCER_0                0x3000
 #define WM8994_WRITE_SEQUENCER_1                0x3001
 #define WM8994_WRITE_SEQUENCER_2                0x3002
@@ -1905,9 +1848,6 @@
 /*
  * R57 (0x39) - AntiPOP (2)
  */
-#define WM1811_JACKDET_MODE_MASK                0x0180  /* JACKDET_MODE - [8:7] */
-#define WM1811_JACKDET_MODE_SHIFT                    7  /* JACKDET_MODE - [8:7] */
-#define WM1811_JACKDET_MODE_WIDTH                    2  /* JACKDET_MODE - [8:7] */
 #define WM8994_MICB2_DISCH                      0x0100  /* MICB2_DISCH */
 #define WM8994_MICB2_DISCH_MASK                 0x0100  /* MICB2_DISCH */
 #define WM8994_MICB2_DISCH_SHIFT                     8  /* MICB2_DISCH */
@@ -1981,59 +1921,6 @@
 #define WM8994_LDO2_DISCH_WIDTH                      1  /* LDO2_DISCH */
 
 /*
- * R61 (0x3D) - MICBIAS1
- */
-#define WM8958_MICB1_RATE                       0x0020  /* MICB1_RATE */
-#define WM8958_MICB1_RATE_MASK                  0x0020  /* MICB1_RATE */
-#define WM8958_MICB1_RATE_SHIFT                      5  /* MICB1_RATE */
-#define WM8958_MICB1_RATE_WIDTH                      1  /* MICB1_RATE */
-#define WM8958_MICB1_MODE                       0x0010  /* MICB1_MODE */
-#define WM8958_MICB1_MODE_MASK                  0x0010  /* MICB1_MODE */
-#define WM8958_MICB1_MODE_SHIFT                      4  /* MICB1_MODE */
-#define WM8958_MICB1_MODE_WIDTH                      1  /* MICB1_MODE */
-#define WM8958_MICB1_LVL_MASK                   0x000E  /* MICB1_LVL - [3:1] */
-#define WM8958_MICB1_LVL_SHIFT                       1  /* MICB1_LVL - [3:1] */
-#define WM8958_MICB1_LVL_WIDTH                       3  /* MICB1_LVL - [3:1] */
-#define WM8958_MICB1_DISCH                      0x0001  /* MICB1_DISCH */
-#define WM8958_MICB1_DISCH_MASK                 0x0001  /* MICB1_DISCH */
-#define WM8958_MICB1_DISCH_SHIFT                     0  /* MICB1_DISCH */
-#define WM8958_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
-
-/*
- * R62 (0x3E) - MICBIAS2
- */
-#define WM8958_MICB2_RATE                       0x0020  /* MICB2_RATE */
-#define WM8958_MICB2_RATE_MASK                  0x0020  /* MICB2_RATE */
-#define WM8958_MICB2_RATE_SHIFT                      5  /* MICB2_RATE */
-#define WM8958_MICB2_RATE_WIDTH                      1  /* MICB2_RATE */
-#define WM8958_MICB2_MODE                       0x0010  /* MICB2_MODE */
-#define WM8958_MICB2_MODE_MASK                  0x0010  /* MICB2_MODE */
-#define WM8958_MICB2_MODE_SHIFT                      4  /* MICB2_MODE */
-#define WM8958_MICB2_MODE_WIDTH                      1  /* MICB2_MODE */
-#define WM8958_MICB2_LVL_MASK                   0x000E  /* MICB2_LVL - [3:1] */
-#define WM8958_MICB2_LVL_SHIFT                       1  /* MICB2_LVL - [3:1] */
-#define WM8958_MICB2_LVL_WIDTH                       3  /* MICB2_LVL - [3:1] */
-#define WM8958_MICB2_DISCH                      0x0001  /* MICB2_DISCH */
-#define WM8958_MICB2_DISCH_MASK                 0x0001  /* MICB2_DISCH */
-#define WM8958_MICB2_DISCH_SHIFT                     0  /* MICB2_DISCH */
-#define WM8958_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
-
-/*
- * R210 (0xD2) - Mic Detect 3
- */
-#define WM8958_MICD_LVL_MASK                    0x07FC  /* MICD_LVL - [10:2] */
-#define WM8958_MICD_LVL_SHIFT                        2  /* MICD_LVL - [10:2] */
-#define WM8958_MICD_LVL_WIDTH                        9  /* MICD_LVL - [10:2] */
-#define WM8958_MICD_VALID                       0x0002  /* MICD_VALID */
-#define WM8958_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
-#define WM8958_MICD_VALID_SHIFT                      1  /* MICD_VALID */
-#define WM8958_MICD_VALID_WIDTH                      1  /* MICD_VALID */
-#define WM8958_MICD_STS                         0x0001  /* MICD_STS */
-#define WM8958_MICD_STS_MASK                    0x0001  /* MICD_STS */
-#define WM8958_MICD_STS_SHIFT                        0  /* MICD_STS */
-#define WM8958_MICD_STS_WIDTH                        1  /* MICD_STS */
-
-/*
  * R76 (0x4C) - Charge Pump (1)
  */
 #define WM8994_CP_ENA                           0x8000  /* CP_ENA */
@@ -2140,10 +2027,6 @@
 /*
  * R96 (0x60) - Analogue HP (1)
  */
-#define WM1811_HPOUT1_ATTN                      0x0100  /* HPOUT1_ATTN */
-#define WM1811_HPOUT1_ATTN_MASK                 0x0100  /* HPOUT1_ATTN */
-#define WM1811_HPOUT1_ATTN_SHIFT                     8  /* HPOUT1_ATTN */
-#define WM1811_HPOUT1_ATTN_WIDTH                     1  /* HPOUT1_ATTN */
 #define WM8994_HPOUT1L_RMV_SHORT                0x0080  /* HPOUT1L_RMV_SHORT */
 #define WM8994_HPOUT1L_RMV_SHORT_MASK           0x0080  /* HPOUT1L_RMV_SHORT */
 #define WM8994_HPOUT1L_RMV_SHORT_SHIFT               7  /* HPOUT1L_RMV_SHORT */
@@ -2212,9 +2095,6 @@
 /*
  * R256 (0x100) - Chip Revision
  */
-#define WM8994_CUST_ID_MASK                     0xFF00  /* CUST_ID - [15:8] */
-#define WM8994_CUST_ID_SHIFT                         8  /* CUST_ID - [15:8] */
-#define WM8994_CUST_ID_WIDTH                         8  /* CUST_ID - [15:8] */
 #define WM8994_CHIP_REV_MASK                    0x000F  /* CHIP_REV - [3:0] */
 #define WM8994_CHIP_REV_SHIFT                        0  /* CHIP_REV - [3:0] */
 #define WM8994_CHIP_REV_WIDTH                        4  /* CHIP_REV - [3:0] */
@@ -2448,10 +2328,6 @@
 /*
  * R548 (0x224) - FLL1 Control (5)
  */
-#define WM8958_FLL1_BYP                         0x8000  /* FLL1_BYP */
-#define WM8958_FLL1_BYP_MASK                    0x8000  /* FLL1_BYP */
-#define WM8958_FLL1_BYP_SHIFT                       15  /* FLL1_BYP */
-#define WM8958_FLL1_BYP_WIDTH                        1  /* FLL1_BYP */
 #define WM8994_FLL1_FRC_NCO_VAL_MASK            0x1F80  /* FLL1_FRC_NCO_VAL - [12:7] */
 #define WM8994_FLL1_FRC_NCO_VAL_SHIFT                7  /* FLL1_FRC_NCO_VAL - [12:7] */
 #define WM8994_FLL1_FRC_NCO_VAL_WIDTH                6  /* FLL1_FRC_NCO_VAL - [12:7] */
@@ -2467,24 +2343,6 @@
 #define WM8994_FLL1_REFCLK_SRC_WIDTH                 2  /* FLL1_REFCLK_SRC - [1:0] */
 
 /*
- * R550 (0x226) - FLL1 EFS 1
- */
-#define WM8958_FLL1_LAMBDA_MASK                 0xFFFF  /* FLL1_LAMBDA - [15:0] */
-#define WM8958_FLL1_LAMBDA_SHIFT                     0  /* FLL1_LAMBDA - [15:0] */
-#define WM8958_FLL1_LAMBDA_WIDTH                    16  /* FLL1_LAMBDA - [15:0] */
-
-/*
- * R551 (0x227) - FLL1 EFS 2
- */
-#define WM8958_FLL1_LFSR_SEL_MASK               0x0006  /* FLL1_LFSR_SEL - [2:1] */
-#define WM8958_FLL1_LFSR_SEL_SHIFT                   1  /* FLL1_LFSR_SEL - [2:1] */
-#define WM8958_FLL1_LFSR_SEL_WIDTH                   2  /* FLL1_LFSR_SEL - [2:1] */
-#define WM8958_FLL1_EFS_ENA                     0x0001  /* FLL1_EFS_ENA */
-#define WM8958_FLL1_EFS_ENA_MASK                0x0001  /* FLL1_EFS_ENA */
-#define WM8958_FLL1_EFS_ENA_SHIFT                    0  /* FLL1_EFS_ENA */
-#define WM8958_FLL1_EFS_ENA_WIDTH                    1  /* FLL1_EFS_ENA */
-
-/*
  * R576 (0x240) - FLL2 Control (1)
  */
 #define WM8994_FLL2_FRAC                        0x0004  /* FLL2_FRAC */
@@ -2533,10 +2391,6 @@
 /*
  * R580 (0x244) - FLL2 Control (5)
  */
-#define WM8958_FLL2_BYP                         0x8000  /* FLL2_BYP */
-#define WM8958_FLL2_BYP_MASK                    0x8000  /* FLL2_BYP */
-#define WM8958_FLL2_BYP_SHIFT                       15  /* FLL2_BYP */
-#define WM8958_FLL2_BYP_WIDTH                        1  /* FLL2_BYP */
 #define WM8994_FLL2_FRC_NCO_VAL_MASK            0x1F80  /* FLL2_FRC_NCO_VAL - [12:7] */
 #define WM8994_FLL2_FRC_NCO_VAL_SHIFT                7  /* FLL2_FRC_NCO_VAL - [12:7] */
 #define WM8994_FLL2_FRC_NCO_VAL_WIDTH                6  /* FLL2_FRC_NCO_VAL - [12:7] */
@@ -2552,24 +2406,6 @@
 #define WM8994_FLL2_REFCLK_SRC_WIDTH                 2  /* FLL2_REFCLK_SRC - [1:0] */
 
 /*
- * R582 (0x246) - FLL2 EFS 1
- */
-#define WM8958_FLL2_LAMBDA_MASK                 0xFFFF  /* FLL2_LAMBDA - [15:0] */
-#define WM8958_FLL2_LAMBDA_SHIFT                     0  /* FLL2_LAMBDA - [15:0] */
-#define WM8958_FLL2_LAMBDA_WIDTH                    16  /* FLL2_LAMBDA - [15:0] */
-
-/*
- * R583 (0x247) - FLL2 EFS 2
- */
-#define WM8958_FLL2_LFSR_SEL_MASK               0x0006  /* FLL2_LFSR_SEL - [2:1] */
-#define WM8958_FLL2_LFSR_SEL_SHIFT                   1  /* FLL2_LFSR_SEL - [2:1] */
-#define WM8958_FLL2_LFSR_SEL_WIDTH                   2  /* FLL2_LFSR_SEL - [2:1] */
-#define WM8958_FLL2_EFS_ENA                     0x0001  /* FLL2_EFS_ENA */
-#define WM8958_FLL2_EFS_ENA_MASK                0x0001  /* FLL2_EFS_ENA */
-#define WM8958_FLL2_EFS_ENA_SHIFT                    0  /* FLL2_EFS_ENA */
-#define WM8958_FLL2_EFS_ENA_WIDTH                    1  /* FLL2_EFS_ENA */
-
-/*
  * R768 (0x300) - AIF1 Control (1)
  */
 #define WM8994_AIF1ADCL_SRC                     0x8000  /* AIF1ADCL_SRC */
@@ -3113,34 +2949,6 @@
 #define WM8994_AIF1DAC2_3D_ENA_WIDTH                 1  /* AIF1DAC2_3D_ENA */
 
 /*
- * R1072 (0x430) - AIF1 DAC1 Noise Gate
- */
-#define WM8958_AIF1DAC1_NG_HLD_MASK             0x0060  /* AIF1DAC1_NG_HLD - [6:5] */
-#define WM8958_AIF1DAC1_NG_HLD_SHIFT                 5  /* AIF1DAC1_NG_HLD - [6:5] */
-#define WM8958_AIF1DAC1_NG_HLD_WIDTH                 2  /* AIF1DAC1_NG_HLD - [6:5] */
-#define WM8958_AIF1DAC1_NG_THR_MASK             0x000E  /* AIF1DAC1_NG_THR - [3:1] */
-#define WM8958_AIF1DAC1_NG_THR_SHIFT                 1  /* AIF1DAC1_NG_THR - [3:1] */
-#define WM8958_AIF1DAC1_NG_THR_WIDTH                 3  /* AIF1DAC1_NG_THR - [3:1] */
-#define WM8958_AIF1DAC1_NG_ENA                  0x0001  /* AIF1DAC1_NG_ENA */
-#define WM8958_AIF1DAC1_NG_ENA_MASK             0x0001  /* AIF1DAC1_NG_ENA */
-#define WM8958_AIF1DAC1_NG_ENA_SHIFT                 0  /* AIF1DAC1_NG_ENA */
-#define WM8958_AIF1DAC1_NG_ENA_WIDTH                 1  /* AIF1DAC1_NG_ENA */
-
-/*
- * R1073 (0x431) - AIF1 DAC2 Noise Gate
- */
-#define WM8958_AIF1DAC2_NG_HLD_MASK             0x0060  /* AIF1DAC2_NG_HLD - [6:5] */
-#define WM8958_AIF1DAC2_NG_HLD_SHIFT                 5  /* AIF1DAC2_NG_HLD - [6:5] */
-#define WM8958_AIF1DAC2_NG_HLD_WIDTH                 2  /* AIF1DAC2_NG_HLD - [6:5] */
-#define WM8958_AIF1DAC2_NG_THR_MASK             0x000E  /* AIF1DAC2_NG_THR - [3:1] */
-#define WM8958_AIF1DAC2_NG_THR_SHIFT                 1  /* AIF1DAC2_NG_THR - [3:1] */
-#define WM8958_AIF1DAC2_NG_THR_WIDTH                 3  /* AIF1DAC2_NG_THR - [3:1] */
-#define WM8958_AIF1DAC2_NG_ENA                  0x0001  /* AIF1DAC2_NG_ENA */
-#define WM8958_AIF1DAC2_NG_ENA_MASK             0x0001  /* AIF1DAC2_NG_ENA */
-#define WM8958_AIF1DAC2_NG_ENA_SHIFT                 0  /* AIF1DAC2_NG_ENA */
-#define WM8958_AIF1DAC2_NG_ENA_WIDTH                 1  /* AIF1DAC2_NG_ENA */
-
-/*
  * R1088 (0x440) - AIF1 DRC1 (1)
  */
 #define WM8994_AIF1DRC1_SIG_DET_RMS_MASK        0xF800  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
@@ -3752,20 +3560,6 @@
 #define WM8994_AIF2DAC_3D_ENA_WIDTH                  1  /* AIF2DAC_3D_ENA */
 
 /*
- * R1328 (0x530) - AIF2 DAC Noise Gate
- */
-#define WM8958_AIF2DAC_NG_HLD_MASK              0x0060  /* AIF2DAC_NG_HLD - [6:5] */
-#define WM8958_AIF2DAC_NG_HLD_SHIFT                  5  /* AIF2DAC_NG_HLD - [6:5] */
-#define WM8958_AIF2DAC_NG_HLD_WIDTH                  2  /* AIF2DAC_NG_HLD - [6:5] */
-#define WM8958_AIF2DAC_NG_THR_MASK              0x000E  /* AIF2DAC_NG_THR - [3:1] */
-#define WM8958_AIF2DAC_NG_THR_SHIFT                  1  /* AIF2DAC_NG_THR - [3:1] */
-#define WM8958_AIF2DAC_NG_THR_WIDTH                  3  /* AIF2DAC_NG_THR - [3:1] */
-#define WM8958_AIF2DAC_NG_ENA                   0x0001  /* AIF2DAC_NG_ENA */
-#define WM8958_AIF2DAC_NG_ENA_MASK              0x0001  /* AIF2DAC_NG_ENA */
-#define WM8958_AIF2DAC_NG_ENA_SHIFT                  0  /* AIF2DAC_NG_ENA */
-#define WM8958_AIF2DAC_NG_ENA_WIDTH                  1  /* AIF2DAC_NG_ENA */
-
-/*
  * R1344 (0x540) - AIF2 DRC (1)
  */
 #define WM8994_AIF2DRC_SIG_DET_RMS_MASK         0xF800  /* AIF2DRC_SIG_DET_RMS - [15:11] */
@@ -4290,18 +4084,6 @@
 #define WM8994_STL_SEL_WIDTH                         1  /* STL_SEL */
 
 /*
- * R1797 (0x705) - JACKDET Ctrl
- */
-#define WM1811_JACKDET_DB                       0x0100  /* JACKDET_DB */
-#define WM1811_JACKDET_DB_MASK                  0x0100  /* JACKDET_DB */
-#define WM1811_JACKDET_DB_SHIFT                      8  /* JACKDET_DB */
-#define WM1811_JACKDET_DB_WIDTH                      1  /* JACKDET_DB */
-#define WM1811_JACKDET_LVL                      0x0040  /* JACKDET_LVL */
-#define WM1811_JACKDET_LVL_MASK                 0x0040  /* JACKDET_LVL */
-#define WM1811_JACKDET_LVL_SHIFT                     6  /* JACKDET_LVL */
-#define WM1811_JACKDET_LVL_WIDTH                     1  /* JACKDET_LVL */
-
-/*
  * R1824 (0x720) - Pull Control (1)
  */
 #define WM8994_DMICDAT2_PU                      0x0800  /* DMICDAT2_PU */