diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-28 16:56:35 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-28 16:56:35 -0400 |
commit | 30304e5a79d424eb2c8707b3ff0e9b8bf6ab3e8f (patch) | |
tree | 63968fb97b86861e31922515395feef8a110f884 /include/linux/mfd/tps65217.h | |
parent | 750f77064a290beb162352077b52c61b04bcae0e (diff) | |
parent | b8589e2a8065b8e7773742b60ae96b63b757bb69 (diff) |
Merge tag 'mfd_3.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
Pull MFD changes from Samuel Ortiz:
- 4 new drivers: Freescale i.MX on-chip Anatop, Ricoh's RC5T583 and
TI's TPS65090 and TPS65217.
- New variants support (8420, 8520 ab9540), cleanups and bug fixes for
the abx500 and db8500 ST-E chipsets.
- Some minor fixes and update for the wm8994 from Mark.
- The beginning of a long term TWL cleanup effort coming from the TI
folks.
- Various fixes and cleanups for the s5m, TPS659xx, pm860x, and MAX8997
drivers.
Fix up trivial conflicts due to duplicate patches and header file
cleanups (<linux/device.h> removal etc).
* tag 'mfd_3.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (97 commits)
gpio/twl: Add DT support to gpio-twl4030 driver
gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ support
mfd: Detach twl6040 from the pmic mfd driver
mfd: Replace twl-* pr_ macros by the dev_ equivalent and do various cleanups
mfd: Micro-optimization on twl4030 IRQ handler
mfd: Make twl4030 SIH SPARSE_IRQ capable
mfd: Move twl-core IRQ allocation into twl[4030|6030]-irq files
mfd: Remove references already defineid in header file from twl-core
mfd: Remove unneeded header from twl-core
mfd: Make twl-core not depend on pdata->irq_base/end
ARM: OMAP2+: board-omap4-*: Do not use anymore TWL6030_IRQ_BASE in board files
mfd: Return twl6030_mmc_card_detect IRQ for board setup
Revert "mfd: Add platform data for MAX8997 haptic driver"
mfd: Add support for TPS65090
mfd: Add some da9052-i2c section annotations
mfd: Build rtc5t583 only if I2C config is selected to y.
mfd: Add anatop mfd driver
mfd: Fix compilation error in tps65910.h
mfd: Add 8420 variant to db8500-prcmu
mfd: Add 8520 PRCMU variant to db8500-prcmu
...
Diffstat (limited to 'include/linux/mfd/tps65217.h')
-rw-r--r-- | include/linux/mfd/tps65217.h | 283 |
1 files changed, 283 insertions, 0 deletions
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h new file mode 100644 index 00000000000..e030ef9a64e --- /dev/null +++ b/include/linux/mfd/tps65217.h | |||
@@ -0,0 +1,283 @@ | |||
1 | /* | ||
2 | * linux/mfd/tps65217.h | ||
3 | * | ||
4 | * Functions to access TPS65217 power management chip. | ||
5 | * | ||
6 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License as | ||
10 | * published by the Free Software Foundation version 2. | ||
11 | * | ||
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
13 | * kind, whether express or implied; without even the implied warranty | ||
14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | */ | ||
17 | |||
18 | #ifndef __LINUX_MFD_TPS65217_H | ||
19 | #define __LINUX_MFD_TPS65217_H | ||
20 | |||
21 | #include <linux/i2c.h> | ||
22 | #include <linux/regulator/driver.h> | ||
23 | #include <linux/regulator/machine.h> | ||
24 | |||
25 | /* I2C ID for TPS65217 part */ | ||
26 | #define TPS65217_I2C_ID 0x24 | ||
27 | |||
28 | /* All register addresses */ | ||
29 | #define TPS65217_REG_CHIPID 0X00 | ||
30 | #define TPS65217_REG_PPATH 0X01 | ||
31 | #define TPS65217_REG_INT 0X02 | ||
32 | #define TPS65217_REG_CHGCONFIG0 0X03 | ||
33 | #define TPS65217_REG_CHGCONFIG1 0X04 | ||
34 | #define TPS65217_REG_CHGCONFIG2 0X05 | ||
35 | #define TPS65217_REG_CHGCONFIG3 0X06 | ||
36 | #define TPS65217_REG_WLEDCTRL1 0X07 | ||
37 | #define TPS65217_REG_WLEDCTRL2 0X08 | ||
38 | #define TPS65217_REG_MUXCTRL 0X09 | ||
39 | #define TPS65217_REG_STATUS 0X0A | ||
40 | #define TPS65217_REG_PASSWORD 0X0B | ||
41 | #define TPS65217_REG_PGOOD 0X0C | ||
42 | #define TPS65217_REG_DEFPG 0X0D | ||
43 | #define TPS65217_REG_DEFDCDC1 0X0E | ||
44 | #define TPS65217_REG_DEFDCDC2 0X0F | ||
45 | #define TPS65217_REG_DEFDCDC3 0X10 | ||
46 | #define TPS65217_REG_DEFSLEW 0X11 | ||
47 | #define TPS65217_REG_DEFLDO1 0X12 | ||
48 | #define TPS65217_REG_DEFLDO2 0X13 | ||
49 | #define TPS65217_REG_DEFLS1 0X14 | ||
50 | #define TPS65217_REG_DEFLS2 0X15 | ||
51 | #define TPS65217_REG_ENABLE 0X16 | ||
52 | #define TPS65217_REG_DEFUVLO 0X18 | ||
53 | #define TPS65217_REG_SEQ1 0X19 | ||
54 | #define TPS65217_REG_SEQ2 0X1A | ||
55 | #define TPS65217_REG_SEQ3 0X1B | ||
56 | #define TPS65217_REG_SEQ4 0X1C | ||
57 | #define TPS65217_REG_SEQ5 0X1D | ||
58 | #define TPS65217_REG_SEQ6 0X1E | ||
59 | |||
60 | /* Register field definitions */ | ||
61 | #define TPS65217_CHIPID_CHIP_MASK 0xF0 | ||
62 | #define TPS65217_CHIPID_REV_MASK 0x0F | ||
63 | |||
64 | #define TPS65217_PPATH_ACSINK_ENABLE BIT(7) | ||
65 | #define TPS65217_PPATH_USBSINK_ENABLE BIT(6) | ||
66 | #define TPS65217_PPATH_AC_PW_ENABLE BIT(5) | ||
67 | #define TPS65217_PPATH_USB_PW_ENABLE BIT(4) | ||
68 | #define TPS65217_PPATH_AC_CURRENT_MASK 0x0C | ||
69 | #define TPS65217_PPATH_USB_CURRENT_MASK 0x03 | ||
70 | |||
71 | #define TPS65217_INT_PBM BIT(6) | ||
72 | #define TPS65217_INT_ACM BIT(5) | ||
73 | #define TPS65217_INT_USBM BIT(4) | ||
74 | #define TPS65217_INT_PBI BIT(2) | ||
75 | #define TPS65217_INT_ACI BIT(1) | ||
76 | #define TPS65217_INT_USBI BIT(0) | ||
77 | |||
78 | #define TPS65217_CHGCONFIG0_TREG BIT(7) | ||
79 | #define TPS65217_CHGCONFIG0_DPPM BIT(6) | ||
80 | #define TPS65217_CHGCONFIG0_TSUSP BIT(5) | ||
81 | #define TPS65217_CHGCONFIG0_TERMI BIT(4) | ||
82 | #define TPS65217_CHGCONFIG0_ACTIVE BIT(3) | ||
83 | #define TPS65217_CHGCONFIG0_CHGTOUT BIT(2) | ||
84 | #define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1) | ||
85 | #define TPS65217_CHGCONFIG0_BATTEMP BIT(0) | ||
86 | |||
87 | #define TPS65217_CHGCONFIG1_TMR_MASK 0xC0 | ||
88 | #define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5) | ||
89 | #define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4) | ||
90 | #define TPS65217_CHGCONFIG1_RESET BIT(3) | ||
91 | #define TPS65217_CHGCONFIG1_TERM BIT(2) | ||
92 | #define TPS65217_CHGCONFIG1_SUSP BIT(1) | ||
93 | #define TPS65217_CHGCONFIG1_CHG_EN BIT(0) | ||
94 | |||
95 | #define TPS65217_CHGCONFIG2_DYNTMR BIT(7) | ||
96 | #define TPS65217_CHGCONFIG2_VPREGHG BIT(6) | ||
97 | #define TPS65217_CHGCONFIG2_VOREG_MASK 0x30 | ||
98 | |||
99 | #define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0 | ||
100 | #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30 | ||
101 | #define TPS65217_CHGCONFIG2_PCHRGT BIT(3) | ||
102 | #define TPS65217_CHGCONFIG2_TERMIF 0x06 | ||
103 | #define TPS65217_CHGCONFIG2_TRANGE BIT(0) | ||
104 | |||
105 | #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3) | ||
106 | #define TPS65217_WLEDCTRL1_ISEL BIT(2) | ||
107 | #define TPS65217_WLEDCTRL1_FDIM_MASK 0x03 | ||
108 | |||
109 | #define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F | ||
110 | |||
111 | #define TPS65217_MUXCTRL_MUX_MASK 0x07 | ||
112 | |||
113 | #define TPS65217_STATUS_OFF BIT(7) | ||
114 | #define TPS65217_STATUS_ACPWR BIT(3) | ||
115 | #define TPS65217_STATUS_USBPWR BIT(2) | ||
116 | #define TPS65217_STATUS_PB BIT(0) | ||
117 | |||
118 | #define TPS65217_PASSWORD_REGS_UNLOCK 0x7D | ||
119 | |||
120 | #define TPS65217_PGOOD_LDO3_PG BIT(6) | ||
121 | #define TPS65217_PGOOD_LDO4_PG BIT(5) | ||
122 | #define TPS65217_PGOOD_DC1_PG BIT(4) | ||
123 | #define TPS65217_PGOOD_DC2_PG BIT(3) | ||
124 | #define TPS65217_PGOOD_DC3_PG BIT(2) | ||
125 | #define TPS65217_PGOOD_LDO1_PG BIT(1) | ||
126 | #define TPS65217_PGOOD_LDO2_PG BIT(0) | ||
127 | |||
128 | #define TPS65217_DEFPG_LDO1PGM BIT(3) | ||
129 | #define TPS65217_DEFPG_LDO2PGM BIT(2) | ||
130 | #define TPS65217_DEFPG_PGDLY_MASK 0x03 | ||
131 | |||
132 | #define TPS65217_DEFDCDCX_XADJX BIT(7) | ||
133 | #define TPS65217_DEFDCDCX_DCDC_MASK 0x3F | ||
134 | |||
135 | #define TPS65217_DEFSLEW_GO BIT(7) | ||
136 | #define TPS65217_DEFSLEW_GODSBL BIT(6) | ||
137 | #define TPS65217_DEFSLEW_PFM_EN1 BIT(5) | ||
138 | #define TPS65217_DEFSLEW_PFM_EN2 BIT(4) | ||
139 | #define TPS65217_DEFSLEW_PFM_EN3 BIT(3) | ||
140 | #define TPS65217_DEFSLEW_SLEW_MASK 0x07 | ||
141 | |||
142 | #define TPS65217_DEFLDO1_LDO1_MASK 0x0F | ||
143 | |||
144 | #define TPS65217_DEFLDO2_TRACK BIT(6) | ||
145 | #define TPS65217_DEFLDO2_LDO2_MASK 0x3F | ||
146 | |||
147 | #define TPS65217_DEFLDO3_LDO3_EN BIT(5) | ||
148 | #define TPS65217_DEFLDO3_LDO3_MASK 0x1F | ||
149 | |||
150 | #define TPS65217_DEFLDO4_LDO4_EN BIT(5) | ||
151 | #define TPS65217_DEFLDO4_LDO4_MASK 0x1F | ||
152 | |||
153 | #define TPS65217_ENABLE_LS1_EN BIT(6) | ||
154 | #define TPS65217_ENABLE_LS2_EN BIT(5) | ||
155 | #define TPS65217_ENABLE_DC1_EN BIT(4) | ||
156 | #define TPS65217_ENABLE_DC2_EN BIT(3) | ||
157 | #define TPS65217_ENABLE_DC3_EN BIT(2) | ||
158 | #define TPS65217_ENABLE_LDO1_EN BIT(1) | ||
159 | #define TPS65217_ENABLE_LDO2_EN BIT(0) | ||
160 | |||
161 | #define TPS65217_DEFUVLO_UVLOHYS BIT(2) | ||
162 | #define TPS65217_DEFUVLO_UVLO_MASK 0x03 | ||
163 | |||
164 | #define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0 | ||
165 | #define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F | ||
166 | |||
167 | #define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0 | ||
168 | #define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F | ||
169 | |||
170 | #define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0 | ||
171 | #define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F | ||
172 | |||
173 | #define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0 | ||
174 | |||
175 | #define TPS65217_SEQ5_DLY1_MASK 0xC0 | ||
176 | #define TPS65217_SEQ5_DLY2_MASK 0x30 | ||
177 | #define TPS65217_SEQ5_DLY3_MASK 0x0C | ||
178 | #define TPS65217_SEQ5_DLY4_MASK 0x03 | ||
179 | |||
180 | #define TPS65217_SEQ6_DLY5_MASK 0xC0 | ||
181 | #define TPS65217_SEQ6_DLY6_MASK 0x30 | ||
182 | #define TPS65217_SEQ6_SEQUP BIT(2) | ||
183 | #define TPS65217_SEQ6_SEQDWN BIT(1) | ||
184 | #define TPS65217_SEQ6_INSTDWN BIT(0) | ||
185 | |||
186 | #define TPS65217_MAX_REGISTER 0x1E | ||
187 | #define TPS65217_PROTECT_NONE 0 | ||
188 | #define TPS65217_PROTECT_L1 1 | ||
189 | #define TPS65217_PROTECT_L2 2 | ||
190 | |||
191 | |||
192 | enum tps65217_regulator_id { | ||
193 | /* DCDC's */ | ||
194 | TPS65217_DCDC_1, | ||
195 | TPS65217_DCDC_2, | ||
196 | TPS65217_DCDC_3, | ||
197 | /* LDOs */ | ||
198 | TPS65217_LDO_1, | ||
199 | TPS65217_LDO_2, | ||
200 | TPS65217_LDO_3, | ||
201 | TPS65217_LDO_4, | ||
202 | }; | ||
203 | |||
204 | #define TPS65217_MAX_REG_ID TPS65217_LDO_4 | ||
205 | |||
206 | /* Number of step-down converters available */ | ||
207 | #define TPS65217_NUM_DCDC 3 | ||
208 | /* Number of LDO voltage regulators available */ | ||
209 | #define TPS65217_NUM_LDO 4 | ||
210 | /* Number of total regulators available */ | ||
211 | #define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO) | ||
212 | |||
213 | /** | ||
214 | * struct tps65217_board - packages regulator init data | ||
215 | * @tps65217_regulator_data: regulator initialization values | ||
216 | * | ||
217 | * Board data may be used to initialize regulator. | ||
218 | */ | ||
219 | struct tps65217_board { | ||
220 | struct regulator_init_data *tps65217_init_data; | ||
221 | }; | ||
222 | |||
223 | /** | ||
224 | * struct tps_info - packages regulator constraints | ||
225 | * @name: Voltage regulator name | ||
226 | * @min_uV: minimum micro volts | ||
227 | * @max_uV: minimum micro volts | ||
228 | * @vsel_to_uv: Function pointer to get voltage from selector | ||
229 | * @uv_to_vsel: Function pointer to get selector from voltage | ||
230 | * @table: Table for non-uniform voltage step-size | ||
231 | * @table_len: Length of the voltage table | ||
232 | * @enable_mask: Regulator enable mask bits | ||
233 | * @set_vout_reg: Regulator output voltage set register | ||
234 | * @set_vout_mask: Regulator output voltage set mask | ||
235 | * | ||
236 | * This data is used to check the regualtor voltage limits while setting. | ||
237 | */ | ||
238 | struct tps_info { | ||
239 | const char *name; | ||
240 | int min_uV; | ||
241 | int max_uV; | ||
242 | int (*vsel_to_uv)(unsigned int vsel); | ||
243 | int (*uv_to_vsel)(int uV, unsigned int *vsel); | ||
244 | const int *table; | ||
245 | unsigned int table_len; | ||
246 | unsigned int enable_mask; | ||
247 | unsigned int set_vout_reg; | ||
248 | unsigned int set_vout_mask; | ||
249 | }; | ||
250 | |||
251 | /** | ||
252 | * struct tps65217 - tps65217 sub-driver chip access routines | ||
253 | * | ||
254 | * Device data may be used to access the TPS65217 chip | ||
255 | */ | ||
256 | |||
257 | struct tps65217 { | ||
258 | struct device *dev; | ||
259 | struct tps65217_board *pdata; | ||
260 | struct regulator_desc desc[TPS65217_NUM_REGULATOR]; | ||
261 | struct regulator_dev *rdev[TPS65217_NUM_REGULATOR]; | ||
262 | struct tps_info *info[TPS65217_NUM_REGULATOR]; | ||
263 | struct regmap *regmap; | ||
264 | |||
265 | /* Client devices */ | ||
266 | struct platform_device *regulator_pdev[TPS65217_NUM_REGULATOR]; | ||
267 | }; | ||
268 | |||
269 | static inline struct tps65217 *dev_to_tps65217(struct device *dev) | ||
270 | { | ||
271 | return dev_get_drvdata(dev); | ||
272 | } | ||
273 | |||
274 | int tps65217_reg_read(struct tps65217 *tps, unsigned int reg, | ||
275 | unsigned int *val); | ||
276 | int tps65217_reg_write(struct tps65217 *tps, unsigned int reg, | ||
277 | unsigned int val, unsigned int level); | ||
278 | int tps65217_set_bits(struct tps65217 *tps, unsigned int reg, | ||
279 | unsigned int mask, unsigned int val, unsigned int level); | ||
280 | int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg, | ||
281 | unsigned int mask, unsigned int level); | ||
282 | |||
283 | #endif /* __LINUX_MFD_TPS65217_H */ | ||