Merge branch 'drm-intel-next' of git://people.freedesktop.org/~keithp/linux into drm-core-next

* 'drm-intel-next' of git://people.freedesktop.org/~keithp/linux: (72 commits)
  drm/i915/dp: Fix eDP on PCH DP on CPT/PPT
  drm/i915/dp: Introduce is_cpu_edp()
  drm/i915: use correct SPD type value
  drm/i915: fix ILK+ infoframe support
  drm/i915: add DP test request handling
  drm/i915: read full receiver capability field during DP hot plug
  drm/i915/dp: Remove eDP special cases from bandwidth checks
  drm/i915/dp: Fix the math in intel_dp_link_required
  drm/i915/panel: Always record the backlight level again (but cleverly)
  i915: Move i915_read/write out of line
  drm/i915: remove transcoder PLL mashing from mode_set per specs
  drm/i915: if transcoder disable fails, say which
  drm/i915: set watermarks for third pipe on IVB
  drm/i915: export a CPT mode set verification function
  drm/i915: fix transcoder PLL select masking
  drm/i915: fix IVB cursor support
  drm/i915: fix debug output for 3 pipe configs
  drm/i915: add PLL sharing support to handle 3 pipes
  drm/i915: fix PCH PLL assertion check for 3 pipes
  drm/i915: use transcoder select bits on VGA and HDMI on CPT
  ...

2 files changed, 63 insertions, 0 deletions

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 91567bbdb02..0d2f727e96b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -74,6 +74,20 @@
 
 #define DP_TRAINING_AUX_RD_INTERVAL         0x00e
 
+#define DP_PSR_SUPPORT                      0x070
+# define DP_PSR_IS_SUPPORTED                1
+#define DP_PSR_CAPS                         0x071
+# define DP_PSR_NO_TRAIN_ON_EXIT            1
+# define DP_PSR_SETUP_TIME_330              (0 << 1)
+# define DP_PSR_SETUP_TIME_275              (1 << 1)
+# define DP_PSR_SETUP_TIME_220              (2 << 1)
+# define DP_PSR_SETUP_TIME_165              (3 << 1)
+# define DP_PSR_SETUP_TIME_110              (4 << 1)
+# define DP_PSR_SETUP_TIME_55               (5 << 1)
+# define DP_PSR_SETUP_TIME_0                (6 << 1)
+# define DP_PSR_SETUP_TIME_MASK             (7 << 1)
+# define DP_PSR_SETUP_TIME_SHIFT            1
+
 /* link configuration */
 #define DP_LINK_BW_SET                      0x100
 # define DP_LINK_BW_1_62                    0x06
@@ -133,6 +147,18 @@
 #define DP_MAIN_LINK_CHANNEL_CODING_SET     0x108
 # define DP_SET_ANSI_8B10B                  (1 << 0)
 
+#define DP_PSR_EN_CFG                       0x170
+# define DP_PSR_ENABLE                      (1 << 0)
+# define DP_PSR_MAIN_LINK_ACTIVE            (1 << 1)
+# define DP_PSR_CRC_VERIFICATION            (1 << 2)
+# define DP_PSR_FRAME_CAPTURE               (1 << 3)
+
+#define DP_DEVICE_SERVICE_IRQ_VECTOR        0x201
+# define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
+# define DP_AUTOMATED_TEST_REQUEST          (1 << 1)
+# define DP_CP_IRQ                          (1 << 2)
+# define DP_SINK_SPECIFIC_IRQ               (1 << 6)
+
 #define DP_LANE0_1_STATUS                   0x202
 #define DP_LANE2_3_STATUS                   0x203
 # define DP_LANE_CR_DONE                    (1 << 0)
@@ -165,10 +191,45 @@
 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
 
+#define DP_TEST_REQUEST                     0x218
+# define DP_TEST_LINK_TRAINING              (1 << 0)
+# define DP_TEST_LINK_PATTERN               (1 << 1)
+# define DP_TEST_LINK_EDID_READ             (1 << 2)
+# define DP_TEST_LINK_PHY_TEST_PATTERN      (1 << 3) /* DPCD >= 1.1 */
+
+#define DP_TEST_LINK_RATE                   0x219
+# define DP_LINK_RATE_162                   (0x6)
+# define DP_LINK_RATE_27                    (0xa)
+
+#define DP_TEST_LANE_COUNT                  0x220
+
+#define DP_TEST_PATTERN                     0x221
+
+#define DP_TEST_RESPONSE                    0x260
+# define DP_TEST_ACK                        (1 << 0)
+# define DP_TEST_NAK                        (1 << 1)
+# define DP_TEST_EDID_CHECKSUM_WRITE        (1 << 2)
+
 #define DP_SET_POWER                        0x600
 # define DP_SET_POWER_D0                    0x1
 # define DP_SET_POWER_D3                    0x2
 
+#define DP_PSR_ERROR_STATUS                 0x2006
+# define DP_PSR_LINK_CRC_ERROR              (1 << 0)
+# define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
+
+#define DP_PSR_ESI                          0x2007
+# define DP_PSR_CAPS_CHANGE                 (1 << 0)
+
+#define DP_PSR_STATUS                       0x2008
+# define DP_PSR_SINK_INACTIVE               0
+# define DP_PSR_SINK_ACTIVE_SRC_SYNCED      1
+# define DP_PSR_SINK_ACTIVE_RFB             2
+# define DP_PSR_SINK_ACTIVE_SINK_SYNCED     3
+# define DP_PSR_SINK_ACTIVE_RESYNC          4
+# define DP_PSR_SINK_INTERNAL_ERROR         7
+# define DP_PSR_SINK_STATE_MASK             0x07
+
 #define MODE_I2C_START  1
 #define MODE_I2C_WRITE  2
 #define MODE_I2C_READ   4
diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h
index 9e343c0998b..b174620cc9b 100644
--- a/include/drm/intel-gtt.h
+++ b/include/drm/intel-gtt.h
@@ -13,6 +13,8 @@ const struct intel_gtt {
         unsigned int gtt_mappable_entries;
         /* Whether i915 needs to use the dmar apis or not. */
         unsigned int needs_dmar : 1;
+        /* Whether we idle the gpu before mapping/unmapping */
+        unsigned int do_idle_maps : 1;
 } *intel_gtt_get(void);
 
 void intel_gtt_chipset_flush(void);