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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-sh/cpu-sh4
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-sh/cpu-sh4')
-rw-r--r--include/asm-sh/cpu-sh4/addrspace.h26
-rw-r--r--include/asm-sh/cpu-sh4/cache.h35
-rw-r--r--include/asm-sh/cpu-sh4/cacheflush.h64
-rw-r--r--include/asm-sh/cpu-sh4/dma.h17
-rw-r--r--include/asm-sh/cpu-sh4/freq.h22
-rw-r--r--include/asm-sh/cpu-sh4/mmu_context.h39
-rw-r--r--include/asm-sh/cpu-sh4/rtc.h25
-rw-r--r--include/asm-sh/cpu-sh4/shmparam.h19
-rw-r--r--include/asm-sh/cpu-sh4/sigcontext.h24
-rw-r--r--include/asm-sh/cpu-sh4/sq.h48
-rw-r--r--include/asm-sh/cpu-sh4/timer.h51
-rw-r--r--include/asm-sh/cpu-sh4/ubc.h27
-rw-r--r--include/asm-sh/cpu-sh4/watchdog.h25
13 files changed, 422 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h
new file mode 100644
index 00000000000..727634d886c
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/addrspace.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH-4 CPUs.
9 */
10#ifndef __ASM_CPU_SH4_ADDRSPACE_H
11#define __ASM_CPU_SH4_ADDRSPACE_H
12
13/* Detailed P4SEG */
14#define P4SEG_STORE_QUE (P4SEG)
15#define P4SEG_IC_ADDR 0xf0000000
16#define P4SEG_IC_DATA 0xf1000000
17#define P4SEG_ITLB_ADDR 0xf2000000
18#define P4SEG_ITLB_DATA 0xf3000000
19#define P4SEG_OC_ADDR 0xf4000000
20#define P4SEG_OC_DATA 0xf5000000
21#define P4SEG_TLB_ADDR 0xf6000000
22#define P4SEG_TLB_DATA 0xf7000000
23#define P4SEG_REG_BASE 0xff000000
24
25#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
26
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h
new file mode 100644
index 00000000000..1fe20359312
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/cache.h
@@ -0,0 +1,35 @@
1/*
2 * include/asm-sh/cpu-sh4/cache.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_CACHE_H
11#define __ASM_CPU_SH4_CACHE_H
12
13#define L1_CACHE_SHIFT 5
14
15#define CCR 0xff00001c /* Address of Cache Control Register */
16#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
17#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
18#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
19#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
20#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
21#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
22#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
23#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
24#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
25#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
26
27/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
28#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
29#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
30
31#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
32#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
33
34#endif /* __ASM_CPU_SH4_CACHE_H */
35
diff --git a/include/asm-sh/cpu-sh4/cacheflush.h b/include/asm-sh/cpu-sh4/cacheflush.h
new file mode 100644
index 00000000000..f323567e085
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/cacheflush.h
@@ -0,0 +1,64 @@
1/*
2 * include/asm-sh/cpu-sh4/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
12#define __ASM_CPU_SH4_CACHEFLUSH_H
13
14/*
15 * Caches are broken on SH-4 (unless we use write-through
16 * caching; in which case they're only semi-broken),
17 * so we need them.
18 */
19
20/* Page is 4K, OC size is 16K, there are four lines. */
21#define CACHE_ALIAS 0x00003000
22
23struct page;
24struct mm_struct;
25struct vm_area_struct;
26
27extern void flush_cache_all(void);
28extern void flush_cache_mm(struct mm_struct *mm);
29extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
30 unsigned long end);
31extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
32extern void flush_dcache_page(struct page *pg);
33
34#define flush_dcache_mmap_lock(mapping) do { } while (0)
35#define flush_dcache_mmap_unlock(mapping) do { } while (0)
36
37extern void flush_icache_range(unsigned long start, unsigned long end);
38extern void flush_cache_sigtramp(unsigned long addr);
39extern void flush_icache_user_range(struct vm_area_struct *vma,
40 struct page *page, unsigned long addr,
41 int len);
42
43#define flush_icache_page(vma,pg) do { } while (0)
44
45/* Initialization of P3 area for copy_user_page */
46extern void p3_cache_init(void);
47
48#define PG_mapped PG_arch_1
49
50/* We provide our own get_unmapped_area to avoid cache alias issue */
51#define HAVE_ARCH_UNMAPPED_AREA
52
53#ifdef CONFIG_MMU
54extern int remap_area_pages(unsigned long addr, unsigned long phys_addr,
55 unsigned long size, unsigned long flags);
56#else /* CONFIG_MMU */
57static inline int remap_area_pages(unsigned long addr, unsigned long phys_addr,
58 unsigned long size, unsigned long flags)
59{
60 return 0;
61}
62#endif /* CONFIG_MMU */
63#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
64
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
new file mode 100644
index 00000000000..e2b91adf821
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -0,0 +1,17 @@
1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H
3
4#define SH_DMAC_BASE 0xffa00000
5
6#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \
7 SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30})
8#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \
9 SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34})
10#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \
11 SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38})
12#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
13 SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c})
14#define DMAOR (SH_DMAC_BASE + 0x40)
15
16#endif /* __ASM_CPU_SH4_DMA_H */
17
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
new file mode 100644
index 00000000000..201d94fd214
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -0,0 +1,22 @@
1/*
2 * include/asm-sh/cpu-sh4/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_FREQ_H
11#define __ASM_CPU_SH4_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH73180)
14#define FRQCR 0xa4150000
15#else
16#define FRQCR 0xffc00000
17#endif
18#define MIN_DIVISOR_NR 0
19#define MAX_DIVISOR_NR 3
20
21#endif /* __ASM_CPU_SH4_FREQ_H */
22
diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h
new file mode 100644
index 00000000000..5b64d041f0b
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/mmu_context.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-sh/cpu-sh4/mmu_context.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
11#define __ASM_CPU_SH4_MMU_CONTEXT_H
12
13#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
15#define MMU_TTB 0xFF000008 /* Translation table base register */
16#define MMU_TEA 0xFF00000C /* TLB Exception Address */
17#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
18
19#define MMUCR 0xFF000010 /* MMU Control Register */
20
21#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
23#define MMU_PAGE_ASSOC_BIT 0x80
24
25#define MMU_NTLB_ENTRIES 64 /* for 7750 */
26#define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */
27
28#define MMU_ITLB_DATA_ARRAY 0xF3000000
29#define MMU_UTLB_DATA_ARRAY 0xF7000000
30
31#define MMU_UTLB_ENTRIES 64
32#define MMU_U_ENTRY_SHIFT 8
33#define MMU_UTLB_VALID 0x100
34#define MMU_ITLB_ENTRIES 4
35#define MMU_I_ENTRY_SHIFT 8
36#define MMU_ITLB_VALID 0x100
37
38#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
39
diff --git a/include/asm-sh/cpu-sh4/rtc.h b/include/asm-sh/cpu-sh4/rtc.h
new file mode 100644
index 00000000000..e091e32a67b
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/rtc.h
@@ -0,0 +1,25 @@
1#ifndef __ASM_CPU_SH4_RTC_H
2#define __ASM_CPU_SH4_RTC_H
3
4/* SH-4 RTC */
5#define R64CNT 0xffc80000
6#define RSECCNT 0xffc80004
7#define RMINCNT 0xffc80008
8#define RHRCNT 0xffc8000c
9#define RWKCNT 0xffc80010
10#define RDAYCNT 0xffc80014
11#define RMONCNT 0xffc80018
12#define RYRCNT 0xffc8001c /* 16bit */
13#define RSECAR 0xffc80020
14#define RMINAR 0xffc80024
15#define RHRAR 0xffc80028
16#define RWKAR 0xffc8002c
17#define RDAYAR 0xffc80030
18#define RMONAR 0xffc80034
19#define RCR1 0xffc80038
20#define RCR2 0xffc8003c
21
22#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
23
24#endif /* __ASM_CPU_SH4_RTC_H */
25
diff --git a/include/asm-sh/cpu-sh4/shmparam.h b/include/asm-sh/cpu-sh4/shmparam.h
new file mode 100644
index 00000000000..a5a0aa9425f
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/shmparam.h
@@ -0,0 +1,19 @@
1/*
2 * include/asm-sh/cpu-sh4/shmparam.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_SHMPARAM_H
11#define __ASM_CPU_SH4_SHMPARAM_H
12
13/*
14 * SH-4 has D-cache alias issue
15 */
16#define SHMLBA (PAGE_SIZE*4) /* attach addr a multiple of this */
17
18#endif /* __ASM_CPU_SH4_SHMPARAM_H */
19
diff --git a/include/asm-sh/cpu-sh4/sigcontext.h b/include/asm-sh/cpu-sh4/sigcontext.h
new file mode 100644
index 00000000000..ab392f120e0
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/sigcontext.h
@@ -0,0 +1,24 @@
1#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
2#define __ASM_CPU_SH4_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15
16 /* FPU registers */
17 unsigned long sc_fpregs[16];
18 unsigned long sc_xfpregs[16];
19 unsigned int sc_fpscr;
20 unsigned int sc_fpul;
21 unsigned int sc_ownedfp;
22};
23
24#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh4/sq.h b/include/asm-sh/cpu-sh4/sq.h
new file mode 100644
index 00000000000..366b09166d3
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/sq.h
@@ -0,0 +1,48 @@
1/*
2 * include/asm-sh/cpu-sh4/sq.h
3 *
4 * Copyright (C) 2001, 2002, 2003 Paul Mundt
5 * Copyright (C) 2001, 2002 M. R. Brown
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_SQ_H
12#define __ASM_CPU_SH4_SQ_H
13
14#include <asm/addrspace.h>
15
16/*
17 * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
18 * mapped to any physical address space. Since data is written (and aligned)
19 * to 32-byte boundaries, we need to be sure that all allocations are aligned.
20 */
21#define SQ_SIZE 32
22#define SQ_ALIGN_MASK (~(SQ_SIZE - 1))
23#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
24
25#define SQ_QACR0 (P4SEG_REG_BASE + 0x38)
26#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c)
27#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000)
28
29struct sq_mapping {
30 const char *name;
31
32 unsigned long sq_addr;
33 unsigned long addr;
34 unsigned int size;
35
36 struct list_head list;
37};
38
39/* arch/sh/kernel/cpu/sh4/sq.c */
40extern struct sq_mapping *sq_remap(unsigned long phys, unsigned int size, const char *name);
41extern void sq_unmap(struct sq_mapping *map);
42
43extern void sq_clear(unsigned long addr, unsigned int len);
44extern void sq_flush(void *addr);
45extern void sq_flush_range(unsigned long start, unsigned int len);
46
47#endif /* __ASM_CPU_SH4_SQ_H */
48
diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h
new file mode 100644
index 00000000000..8a4af126c89
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/timer.h
@@ -0,0 +1,51 @@
1/*
2 * include/asm-sh/cpu-sh4/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_TIMER_H
11#define __ASM_CPU_SH4_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH4 processors
16 * SH7750S/SH7750R
17 * SH7751/SH7751R
18 * SH7760
19 * ---------------------------------------------------------------------------
20 */
21
22#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
23#define TMU_TOCR 0xffd80000 /* Byte access */
24#endif
25#define TMU_TSTR 0xffd80004 /* Byte access */
26
27#define TMU0_TCOR 0xffd80008 /* Long access */
28#define TMU0_TCNT 0xffd8000c /* Long access */
29#define TMU0_TCR 0xffd80010 /* Word access */
30
31#define TMU1_TCOR 0xffd80014 /* Long access */
32#define TMU1_TCNT 0xffd80018 /* Long access */
33#define TMU1_TCR 0xffd8001c /* Word access */
34
35#define TMU2_TCOR 0xffd80020 /* Long access */
36#define TMU2_TCNT 0xffd80024 /* Long access */
37#define TMU2_TCR 0xffd80028 /* Word access */
38#define TMU2_TCPR 0xffd8002c /* Long access */
39
40#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
41#define TMU3_TCOR 0xfe100008 /* Long access */
42#define TMU3_TCNT 0xfe10000c /* Long access */
43#define TMU3_TCR 0xfe100010 /* Word access */
44
45#define TMU4_TCOR 0xfe100014 /* Long access */
46#define TMU4_TCNT 0xfe100018 /* Long access */
47#define TMU4_TCR 0xfe10001c /* Word access */
48#endif
49
50#endif /* __ASM_CPU_SH4_TIMER_H */
51
diff --git a/include/asm-sh/cpu-sh4/ubc.h b/include/asm-sh/cpu-sh4/ubc.h
new file mode 100644
index 00000000000..3d094316765
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/ubc.h
@@ -0,0 +1,27 @@
1/*
2 * include/asm-sh/cpu-sh4/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_UBC_H
12#define __ASM_CPU_SH4_UBC_H
13
14#define UBC_BARA 0xff200000
15#define UBC_BAMRA 0xff200004
16#define UBC_BBRA 0xff200008
17#define UBC_BASRA 0xff000014
18#define UBC_BARB 0xff20000c
19#define UBC_BAMRB 0xff200010
20#define UBC_BBRB 0xff200014
21#define UBC_BASRB 0xff000018
22#define UBC_BDRB 0xff200018
23#define UBC_BDMRB 0xff20001c
24#define UBC_BRCR 0xff200020
25
26#endif /* __ASM_CPU_SH4_UBC_H */
27
diff --git a/include/asm-sh/cpu-sh4/watchdog.h b/include/asm-sh/cpu-sh4/watchdog.h
new file mode 100644
index 00000000000..259f6a0ce23
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/watchdog.h
@@ -0,0 +1,25 @@
1/*
2 * include/asm-sh/cpu-sh4/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_WATCHDOG_H
11#define __ASM_CPU_SH4_WATCHDOG_H
12
13/* Register definitions */
14#define WTCNT 0xffc00008
15#define WTCSR 0xffc0000c
16
17/* Bit definitions */
18#define WTCSR_TME 0x80
19#define WTCSR_WT 0x40
20#define WTCSR_RSTS 0x20
21#define WTCSR_WOVF 0x10
22#define WTCSR_IOVF 0x08
23
24#endif /* __ASM_CPU_SH4_WATCHDOG_H */
25