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authorChris Dearman <chris@mips.com>2007-05-08 09:05:39 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-05-11 09:28:31 -0400
commitd725cf3818b12a17d78b87a2de19e8eec17126ae (patch)
tree9d200020488b886201771bd6516c63ef43397baa /include/asm-mips/mips-boards
parentef300e42234eac066b193c871714203d999b481c (diff)
[MIPS] MT: Reenable EIC support and add support for SOCit SC.
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mips-boards')
-rw-r--r--include/asm-mips/mips-boards/malta.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
index b0ba3c5a921..eec91001bb6 100644
--- a/include/asm-mips/mips-boards/malta.h
+++ b/include/asm-mips/mips-boards/malta.h
@@ -25,6 +25,10 @@
25#include <asm/mips-boards/msc01_pci.h> 25#include <asm/mips-boards/msc01_pci.h>
26#include <asm/gt64120.h> 26#include <asm/gt64120.h>
27 27
28/* Mips interrupt controller found in SOCit variations */
29#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
30#define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
31
28/* 32/*
29 * Malta I/O ports base address for the Galileo GT64120 and Algorithmics 33 * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
30 * Bonito system controllers. 34 * Bonito system controllers.