[MIPS] MIPS64 R2 optimizations for 64-bit endianess swapping.

    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 18 insertions, 0 deletions

diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index 584f8128fff..aefc02f16fd 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -39,6 +39,24 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
 }
 #define __arch__swab32(x)       ___arch__swab32(x)
 
+#ifdef CONFIG_CPU_MIPS64_R2
+
+static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+{
+        __asm__(
+        "       dsbh    %0, %1                  \n"
+        "       dshd    %0, %0                  \n"
+        "       drotr   %0, %0, 32              \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+
+#define __arch__swab64(x)       ___arch__swab64(x)
+
+#endif /* CONFIG_CPU_MIPS64_R2 */
+
 #endif /* CONFIG_CPU_MIPSR2 */
 
 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)