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authorRoy Huang <roy.huang@analog.com>2007-07-12 10:41:45 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-12 10:41:45 -0400
commit24a07a124198153540f8f43d9e91d16227aba66e (patch)
tree917b2011e67e224515830833b1151e276b6c6137 /include/asm-blackfin/mach-bf548/dma.h
parent088eec1192a0ae60fc218796027e622008af36c0 (diff)
Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will be submitted later. Please enjoy the show. Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf548/dma.h')
-rw-r--r--include/asm-blackfin/mach-bf548/dma.h14
1 files changed, 12 insertions, 2 deletions
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
index 5a334c813c7..fcc8b4c34c6 100644
--- a/include/asm-blackfin/mach-bf548/dma.h
+++ b/include/asm-blackfin/mach-bf548/dma.h
@@ -44,7 +44,6 @@
44#define CH_UART1_TX 9 44#define CH_UART1_TX 9
45#define CH_ATAPI_RX 10 45#define CH_ATAPI_RX 10
46#define CH_ATAPI_TX 11 46#define CH_ATAPI_TX 11
47
48#define CH_EPPI0 12 47#define CH_EPPI0 12
49#define CH_EPPI1 13 48#define CH_EPPI1 13
50#define CH_EPPI2 14 49#define CH_EPPI2 14
@@ -58,6 +57,17 @@
58#define CH_SDH 22 57#define CH_SDH 22
59#define CH_SPI2 23 58#define CH_SPI2 23
60 59
61#define MAX_BLACKFIN_DMA_CHANNEL CH_SPI2 60#define CH_MEM_STREAM0_DEST 24
61#define CH_MEM_STREAM0_SRC 25
62#define CH_MEM_STREAM1_DEST 26
63#define CH_MEM_STREAM1_SRC 27
64#define CH_MEM_STREAM2_DEST 28
65#define CH_MEM_STREAM2_SRC 29
66#define CH_MEM_STREAM3_DEST 30
67#define CH_MEM_STREAM3_SRC 31
68
69#define MAX_BLACKFIN_DMA_CHANNEL 32
62 70
71extern int channel2irq(unsigned int channel);
72extern struct dma_register *base_addr[];
63#endif 73#endif