diff options
| author | Guennadi Liakhovetski <g.liakhovetski@pengutronix.de> | 2008-04-11 16:19:45 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-19 12:14:30 -0400 |
| commit | 3f3acefb63dc70d767f730045ab7ebaa81938d77 (patch) | |
| tree | ab81ca4991541a251c7e67b92e9098041d7c2f95 /include/asm-arm/arch-pxa/pxa2xx-gpio.h | |
| parent | 0e623941bec7e80c97b076d346327b31ae17d84a (diff) | |
[ARM] pxa: V4L2 soc_camera driver for PXA270
This patch adds a driver for the Quick Capture Interface on the PXA270.
It is based on the original driver from Intel, but has been re-worked
multiple times since then, now it also supports the V4L2 API.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-pxa/pxa2xx-gpio.h')
| -rw-r--r-- | include/asm-arm/arch-pxa/pxa2xx-gpio.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h index fb418944753..763313c5e6b 100644 --- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h +++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h | |||
| @@ -22,10 +22,15 @@ | |||
| 22 | #define GPIO19_DREQ1 19 /* External DMA Request */ | 22 | #define GPIO19_DREQ1 19 /* External DMA Request */ |
| 23 | #define GPIO20_DREQ0 20 /* External DMA Request */ | 23 | #define GPIO20_DREQ0 20 /* External DMA Request */ |
| 24 | #define GPIO23_SCLK 23 /* SSP clock */ | 24 | #define GPIO23_SCLK 23 /* SSP clock */ |
| 25 | #define GPIO23_CIF_MCLK 23 /* Camera Master Clock */ | ||
| 25 | #define GPIO24_SFRM 24 /* SSP Frame */ | 26 | #define GPIO24_SFRM 24 /* SSP Frame */ |
| 27 | #define GPIO24_CIF_FV 24 /* Camera frame start signal */ | ||
| 26 | #define GPIO25_STXD 25 /* SSP transmit */ | 28 | #define GPIO25_STXD 25 /* SSP transmit */ |
| 29 | #define GPIO25_CIF_LV 25 /* Camera line start signal */ | ||
| 27 | #define GPIO26_SRXD 26 /* SSP receive */ | 30 | #define GPIO26_SRXD 26 /* SSP receive */ |
| 31 | #define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */ | ||
| 28 | #define GPIO27_SEXTCLK 27 /* SSP ext_clk */ | 32 | #define GPIO27_SEXTCLK 27 /* SSP ext_clk */ |
| 33 | #define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */ | ||
| 29 | #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ | 34 | #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ |
| 30 | #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ | 35 | #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ |
| 31 | #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ | 36 | #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ |
| @@ -46,18 +51,24 @@ | |||
| 46 | #define GPIO41_FFRTS 41 /* FFUART request to send */ | 51 | #define GPIO41_FFRTS 41 /* FFUART request to send */ |
| 47 | #define GPIO42_BTRXD 42 /* BTUART receive data */ | 52 | #define GPIO42_BTRXD 42 /* BTUART receive data */ |
| 48 | #define GPIO42_HWRXD 42 /* HWUART receive data */ | 53 | #define GPIO42_HWRXD 42 /* HWUART receive data */ |
| 54 | #define GPIO42_CIF_MCLK 42 /* Camera Master Clock */ | ||
| 49 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ | 55 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ |
| 50 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ | 56 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ |
| 57 | #define GPIO43_CIF_FV 43 /* Camera frame start signal */ | ||
| 51 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ | 58 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ |
| 52 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ | 59 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ |
| 60 | #define GPIO44_CIF_LV 44 /* Camera line start signal */ | ||
| 53 | #define GPIO45_BTRTS 45 /* BTUART request to send */ | 61 | #define GPIO45_BTRTS 45 /* BTUART request to send */ |
| 54 | #define GPIO45_HWRTS 45 /* HWUART request to send */ | 62 | #define GPIO45_HWRTS 45 /* HWUART request to send */ |
| 55 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ | 63 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ |
| 64 | #define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */ | ||
| 56 | #define GPIO46_ICPRXD 46 /* ICP receive data */ | 65 | #define GPIO46_ICPRXD 46 /* ICP receive data */ |
| 57 | #define GPIO46_STRXD 46 /* STD_UART receive data */ | 66 | #define GPIO46_STRXD 46 /* STD_UART receive data */ |
| 58 | #define GPIO47_ICPTXD 47 /* ICP transmit data */ | 67 | #define GPIO47_ICPTXD 47 /* ICP transmit data */ |
| 59 | #define GPIO47_STTXD 47 /* STD_UART transmit data */ | 68 | #define GPIO47_STTXD 47 /* STD_UART transmit data */ |
| 69 | #define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */ | ||
| 60 | #define GPIO48_nPOE 48 /* Output Enable for Card Space */ | 70 | #define GPIO48_nPOE 48 /* Output Enable for Card Space */ |
| 71 | #define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */ | ||
| 61 | #define GPIO49_nPWE 49 /* Write Enable for Card Space */ | 72 | #define GPIO49_nPWE 49 /* Write Enable for Card Space */ |
| 62 | #define GPIO50_nPIOR 50 /* I/O Read for Card Space */ | 73 | #define GPIO50_nPIOR 50 /* I/O Read for Card Space */ |
| 63 | #define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */ | 74 | #define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */ |
| @@ -112,12 +123,25 @@ | |||
| 112 | #define GPIO82_NSFRM 82 /* NSSP Frame */ | 123 | #define GPIO82_NSFRM 82 /* NSSP Frame */ |
| 113 | #define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */ | 124 | #define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */ |
| 114 | #define GPIO83_NSTXD 83 /* NSSP transmit */ | 125 | #define GPIO83_NSTXD 83 /* NSSP transmit */ |
| 126 | #define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */ | ||
| 115 | #define GPIO84_NSRXD 84 /* NSSP receive */ | 127 | #define GPIO84_NSRXD 84 /* NSSP receive */ |
| 116 | #define GPIO84_CIF_FV 84 /* Camera frame start signal */ | 128 | #define GPIO84_CIF_FV 84 /* Camera frame start signal */ |
| 117 | #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ | 129 | #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ |
| 118 | #define GPIO85_CIF_LV 85 /* Camera line start signal */ | 130 | #define GPIO85_CIF_LV 85 /* Camera line start signal */ |
| 131 | #define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */ | ||
| 132 | #define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */ | ||
| 119 | #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ | 133 | #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ |
| 134 | #define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */ | ||
| 135 | #define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */ | ||
| 136 | #define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */ | ||
| 137 | #define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */ | ||
| 120 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ | 138 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ |
| 139 | #define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */ | ||
| 140 | #define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */ | ||
| 141 | #define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */ | ||
| 142 | #define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */ | ||
| 143 | #define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */ | ||
| 144 | #define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */ | ||
| 121 | #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ | 145 | #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ |
| 122 | #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ | 146 | #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ |
| 123 | #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ | 147 | #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ |
| @@ -126,6 +150,9 @@ | |||
| 126 | #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ | 150 | #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ |
| 127 | #define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ | 151 | #define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ |
| 128 | #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ | 152 | #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ |
| 153 | #define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */ | ||
| 154 | #define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */ | ||
| 155 | #define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */ | ||
| 129 | 156 | ||
| 130 | /* GPIO alternate function mode & direction */ | 157 | /* GPIO alternate function mode & direction */ |
| 131 | 158 | ||
| @@ -161,11 +188,16 @@ | |||
| 161 | #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) | 188 | #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) |
| 162 | #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) | 189 | #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) |
| 163 | #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) | 190 | #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) |
| 191 | #define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT) | ||
| 164 | #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) | 192 | #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) |
| 193 | #define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT) | ||
| 165 | #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) | 194 | #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) |
| 195 | #define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT) | ||
| 166 | #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) | 196 | #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) |
| 167 | #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) | 197 | #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) |
| 198 | #define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN) | ||
| 168 | #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) | 199 | #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) |
| 200 | #define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN) | ||
| 169 | #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) | 201 | #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) |
| 170 | #define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) | 202 | #define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) |
| 171 | #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) | 203 | #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) |
| @@ -193,25 +225,33 @@ | |||
| 193 | #define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT) | 225 | #define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT) |
| 194 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) | 226 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) |
| 195 | #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) | 227 | #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) |
| 228 | #define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT) | ||
| 196 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) | 229 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) |
| 197 | #define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) | 230 | #define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) |
| 231 | #define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT) | ||
| 198 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) | 232 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) |
| 199 | #define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) | 233 | #define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) |
| 234 | #define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT) | ||
| 235 | #define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN) | ||
| 200 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) | 236 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) |
| 201 | #define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) | 237 | #define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) |
| 202 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) | 238 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) |
| 203 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) | 239 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) |
| 204 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) | 240 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) |
| 241 | #define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN) | ||
| 205 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) | 242 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) |
| 206 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) | 243 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) |
| 244 | #define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN) | ||
| 207 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | 245 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) |
| 208 | #define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) | 246 | #define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) |
| 209 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | 247 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) |
| 210 | #define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) | 248 | #define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) |
| 211 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) | 249 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) |
| 250 | #define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 212 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) | 251 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) |
| 213 | #define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) | 252 | #define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) |
| 214 | #define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) | 253 | #define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) |
| 254 | #define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) | ||
| 215 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) | 255 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) |
| 216 | #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) | 256 | #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) |
| 217 | #define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) | 257 | #define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) |
| @@ -269,26 +309,39 @@ | |||
| 269 | #define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN) | 309 | #define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN) |
| 270 | #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) | 310 | #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) |
| 271 | #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) | 311 | #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) |
| 312 | #define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN) | ||
| 272 | #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) | 313 | #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) |
| 273 | #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) | 314 | #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) |
| 274 | #define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN) | 315 | #define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN) |
| 275 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) | 316 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) |
| 276 | #define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) | 317 | #define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) |
| 277 | #define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) | 318 | #define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) |
| 319 | #define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN) | ||
| 320 | #define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN) | ||
| 278 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) | 321 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) |
| 322 | #define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN) | ||
| 323 | #define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN) | ||
| 324 | #define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN) | ||
| 279 | #define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) | 325 | #define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) |
| 280 | #define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) | 326 | #define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) |
| 281 | #define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) | 327 | #define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) |
| 328 | #define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN) | ||
| 282 | #define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) | 329 | #define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) |
| 283 | #define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) | 330 | #define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) |
| 284 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) | 331 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) |
| 285 | #define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN) | 332 | #define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN) |
| 333 | #define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN) | ||
| 286 | #define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT) | 334 | #define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT) |
| 335 | #define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN) | ||
| 287 | #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) | 336 | #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) |
| 288 | #define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT) | 337 | #define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT) |
| 338 | #define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN) | ||
| 289 | #define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT) | 339 | #define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT) |
| 340 | #define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN) | ||
| 290 | #define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT) | 341 | #define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT) |
| 342 | #define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN) | ||
| 291 | #define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT) | 343 | #define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT) |
| 344 | #define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN) | ||
| 292 | #define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT) | 345 | #define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT) |
| 293 | #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) | 346 | #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) |
| 294 | #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) | 347 | #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) |