OMAPDSS: HDMI: Add M2 divider while calculating clkout

While calculating regm and regmf value add using M2 divider in
the equation.
Formula for calculating:
Output clock on digital core domain:
	CLKOUT = (M / (N+1))*CLKINP*(1/M2)
Internal oscillator output clock on internal LDO domain:
	CLKDCOLDO = (M / (N+1))*CLKINP
The current code when allows variable M2 values as input
ignores using M2 divider values in calculation of regm and regmf.
so fix it by using M2 in calculation although the default value for
M2 is 1.

Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

1 files changed, 8 insertions, 8 deletions

diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index a229d0f8365..c4b4f6950a9 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -278,24 +278,24 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 
         refclk = clkin / pi->regn;
 
-        /*
-         * multiplier is pixel_clk/ref_clk
-         * Multiplying by 100 to avoid fractional part removal
-         */
-        pi->regm = (phy * 100 / (refclk)) / 100;
-
         if (dssdev->clocks.hdmi.regm2 == 0)
                 pi->regm2 = HDMI_DEFAULT_REGM2;
         else
                 pi->regm2 = dssdev->clocks.hdmi.regm2;
 
         /*
+         * multiplier is pixel_clk/ref_clk
+         * Multiplying by 100 to avoid fractional part removal
+         */
+        pi->regm = phy * pi->regm2 / refclk;
+
+        /*
          * fractional multiplier is remainder of the difference between
          * multiplier and actual phy(required pixel clock thus should be
          * multiplied by 2^18(262144) divided by the reference clock
          */
-        mf = (phy - pi->regm * refclk) * 262144;
-        pi->regmf = mf / (refclk);
+        mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
+        pi->regmf = pi->regm2 * mf / refclk;
 
         /*
          * Dcofreq should be set to 1 if required pixel clock