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authorZhenyu Wang <zhenyuw@linux.intel.com>2010-04-07 04:15:54 -0400
committerEric Anholt <eric@anholt.net>2010-04-12 12:23:40 -0400
commit8db9d77b1b14fd730561f64beea8c00e4478d7c5 (patch)
tree2bcf1d1b4772c07d98d2ab462956c80a64bb0419 /drivers
parent3bad0781832e4e8c9a532f1169bfcd7257bcfd9e (diff)
drm/i915: Support for Cougarpoint PCH display pipeline
Cougarpoint is the new PCH for Sandybridge CPU. This one resolves the chipset change for display pipeline compared to previous Ibexpeak PCH. Sandybridge/Cougarpoint has different FDI training parameters, so this also makes seperate FDI training functions for IBX and CPT. Other change includes new transcoder DPLL select function to set which DPLL for transcoder to pick up. And with another new transcoder C introduced in Cougarpoint, each connector has new transcoder select bits. This one adds that change to light up VGA. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h82
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c10
-rw-r--r--drivers/gpu/drm/i915/intel_display.c458
3 files changed, 426 insertions, 124 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbbf59f56df..8de8194a5e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1754,6 +1754,14 @@
1754#define DP_LINK_TRAIN_MASK (3 << 28) 1754#define DP_LINK_TRAIN_MASK (3 << 28)
1755#define DP_LINK_TRAIN_SHIFT 28 1755#define DP_LINK_TRAIN_SHIFT 28
1756 1756
1757/* CPT Link training mode */
1758#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
1759#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
1760#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
1761#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
1762#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
1763#define DP_LINK_TRAIN_SHIFT_CPT 8
1764
1757/* Signal voltages. These are mostly controlled by the other end */ 1765/* Signal voltages. These are mostly controlled by the other end */
1758#define DP_VOLTAGE_0_4 (0 << 25) 1766#define DP_VOLTAGE_0_4 (0 << 25)
1759#define DP_VOLTAGE_0_6 (1 << 25) 1767#define DP_VOLTAGE_0_6 (1 << 25)
@@ -2305,6 +2313,11 @@
2305#define SDE_PORTB_HOTPLUG (1 << 8) 2313#define SDE_PORTB_HOTPLUG (1 << 8)
2306#define SDE_SDVOB_HOTPLUG (1 << 6) 2314#define SDE_SDVOB_HOTPLUG (1 << 6)
2307#define SDE_HOTPLUG_MASK (0xf << 8) 2315#define SDE_HOTPLUG_MASK (0xf << 8)
2316/* CPT */
2317#define SDE_CRT_HOTPLUG_CPT (1 << 19)
2318#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2319#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2320#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2308 2321
2309#define SDEISR 0xc4000 2322#define SDEISR 0xc4000
2310#define SDEIMR 0xc4004 2323#define SDEIMR 0xc4004
@@ -2396,6 +2409,17 @@
2396#define PCH_SSC4_PARMS 0xc6210 2409#define PCH_SSC4_PARMS 0xc6210
2397#define PCH_SSC4_AUX_PARMS 0xc6214 2410#define PCH_SSC4_AUX_PARMS 0xc6214
2398 2411
2412#define PCH_DPLL_SEL 0xc7000
2413#define TRANSA_DPLL_ENABLE (1<<3)
2414#define TRANSA_DPLLB_SEL (1<<0)
2415#define TRANSA_DPLLA_SEL 0
2416#define TRANSB_DPLL_ENABLE (1<<7)
2417#define TRANSB_DPLLB_SEL (1<<4)
2418#define TRANSB_DPLLA_SEL (0)
2419#define TRANSC_DPLL_ENABLE (1<<11)
2420#define TRANSC_DPLLB_SEL (1<<8)
2421#define TRANSC_DPLLA_SEL (0)
2422
2399/* transcoder */ 2423/* transcoder */
2400 2424
2401#define TRANS_HTOTAL_A 0xe0000 2425#define TRANS_HTOTAL_A 0xe0000
@@ -2482,6 +2506,19 @@
2482#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 2506#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
2483#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 2507#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
2484#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 2508#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
2509/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
2510 SNB has different settings. */
2511/* SNB A-stepping */
2512#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
2513#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
2514#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
2515#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
2516/* SNB B-stepping */
2517#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
2518#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
2519#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
2520#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
2521#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
2485#define FDI_DP_PORT_WIDTH_X1 (0<<19) 2522#define FDI_DP_PORT_WIDTH_X1 (0<<19)
2486#define FDI_DP_PORT_WIDTH_X2 (1<<19) 2523#define FDI_DP_PORT_WIDTH_X2 (1<<19)
2487#define FDI_DP_PORT_WIDTH_X3 (2<<19) 2524#define FDI_DP_PORT_WIDTH_X3 (2<<19)
@@ -2514,6 +2551,13 @@
2514#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 2551#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2515#define FDI_SEL_RAWCLK (0<<4) 2552#define FDI_SEL_RAWCLK (0<<4)
2516#define FDI_SEL_PCDCLK (1<<4) 2553#define FDI_SEL_PCDCLK (1<<4)
2554/* CPT */
2555#define FDI_AUTO_TRAINING (1<<10)
2556#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
2557#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
2558#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
2559#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
2560#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
2517 2561
2518#define FDI_RXA_MISC 0xf0010 2562#define FDI_RXA_MISC 0xf0010
2519#define FDI_RXB_MISC 0xf1010 2563#define FDI_RXB_MISC 0xf1010
@@ -2642,4 +2686,42 @@
2642#define PCH_DPD_AUX_CH_DATA4 0xe4320 2686#define PCH_DPD_AUX_CH_DATA4 0xe4320
2643#define PCH_DPD_AUX_CH_DATA5 0xe4324 2687#define PCH_DPD_AUX_CH_DATA5 0xe4324
2644 2688
2689/* CPT */
2690#define PORT_TRANS_A_SEL_CPT 0
2691#define PORT_TRANS_B_SEL_CPT (1<<29)
2692#define PORT_TRANS_C_SEL_CPT (2<<29)
2693#define PORT_TRANS_SEL_MASK (3<<29)
2694
2695#define TRANS_DP_CTL_A 0xe0300
2696#define TRANS_DP_CTL_B 0xe1300
2697#define TRANS_DP_CTL_C 0xe2300
2698#define TRANS_DP_OUTPUT_ENABLE (1<<31)
2699#define TRANS_DP_PORT_SEL_B (0<<29)
2700#define TRANS_DP_PORT_SEL_C (1<<29)
2701#define TRANS_DP_PORT_SEL_D (2<<29)
2702#define TRANS_DP_PORT_SEL_MASK (3<<29)
2703#define TRANS_DP_AUDIO_ONLY (1<<26)
2704#define TRANS_DP_ENH_FRAMING (1<<18)
2705#define TRANS_DP_8BPC (0<<9)
2706#define TRANS_DP_10BPC (1<<9)
2707#define TRANS_DP_6BPC (2<<9)
2708#define TRANS_DP_12BPC (3<<9)
2709#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
2710#define TRANS_DP_VSYNC_ACTIVE_LOW 0
2711#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
2712#define TRANS_DP_HSYNC_ACTIVE_LOW 0
2713
2714/* SNB eDP training params */
2715/* SNB A-stepping */
2716#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
2717#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
2718#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
2719#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
2720/* SNB B-stepping */
2721#define EDP_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
2722#define EDP_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
2723#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
2724#define EDP_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
2725#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
2726
2645#endif /* _I915_REG_H_ */ 2727#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 4dd5daa8ebe..1f732ba568f 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -135,11 +135,17 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
135 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 135 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
136 136
137 if (intel_crtc->pipe == 0) { 137 if (intel_crtc->pipe == 0) {
138 adpa |= ADPA_PIPE_A_SELECT; 138 if (HAS_PCH_CPT(dev))
139 adpa |= PORT_TRANS_A_SEL_CPT;
140 else
141 adpa |= ADPA_PIPE_A_SELECT;
139 if (!HAS_PCH_SPLIT(dev)) 142 if (!HAS_PCH_SPLIT(dev))
140 I915_WRITE(BCLRPAT_A, 0); 143 I915_WRITE(BCLRPAT_A, 0);
141 } else { 144 } else {
142 adpa |= ADPA_PIPE_B_SELECT; 145 if (HAS_PCH_CPT(dev))
146 adpa |= PORT_TRANS_B_SEL_CPT;
147 else
148 adpa |= ADPA_PIPE_B_SELECT;
143 if (!HAS_PCH_SPLIT(dev)) 149 if (!HAS_PCH_SPLIT(dev))
144 I915_WRITE(BCLRPAT_B, 0); 150 I915_WRITE(BCLRPAT_B, 0);
145 } 151 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9b59979729c..716ab9ea19b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1508,6 +1508,217 @@ static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1508 udelay(500); 1508 udelay(500);
1509} 1509}
1510 1510
1511/* The FDI link training functions for ILK/Ibexpeak. */
1512static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1513{
1514 struct drm_device *dev = crtc->dev;
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1517 int pipe = intel_crtc->pipe;
1518 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1519 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1520 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1521 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1522 u32 temp, tries = 0;
1523
1524 /* enable CPU FDI TX and PCH FDI RX */
1525 temp = I915_READ(fdi_tx_reg);
1526 temp |= FDI_TX_ENABLE;
1527 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1528 temp &= ~FDI_LINK_TRAIN_NONE;
1529 temp |= FDI_LINK_TRAIN_PATTERN_1;
1530 I915_WRITE(fdi_tx_reg, temp);
1531 I915_READ(fdi_tx_reg);
1532
1533 temp = I915_READ(fdi_rx_reg);
1534 temp &= ~FDI_LINK_TRAIN_NONE;
1535 temp |= FDI_LINK_TRAIN_PATTERN_1;
1536 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1537 I915_READ(fdi_rx_reg);
1538 udelay(150);
1539
1540 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1541 for train result */
1542 temp = I915_READ(fdi_rx_imr_reg);
1543 temp &= ~FDI_RX_SYMBOL_LOCK;
1544 temp &= ~FDI_RX_BIT_LOCK;
1545 I915_WRITE(fdi_rx_imr_reg, temp);
1546 I915_READ(fdi_rx_imr_reg);
1547 udelay(150);
1548
1549 for (;;) {
1550 temp = I915_READ(fdi_rx_iir_reg);
1551 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1552
1553 if ((temp & FDI_RX_BIT_LOCK)) {
1554 DRM_DEBUG_KMS("FDI train 1 done.\n");
1555 I915_WRITE(fdi_rx_iir_reg,
1556 temp | FDI_RX_BIT_LOCK);
1557 break;
1558 }
1559
1560 tries++;
1561
1562 if (tries > 5) {
1563 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1564 break;
1565 }
1566 }
1567
1568 /* Train 2 */
1569 temp = I915_READ(fdi_tx_reg);
1570 temp &= ~FDI_LINK_TRAIN_NONE;
1571 temp |= FDI_LINK_TRAIN_PATTERN_2;
1572 I915_WRITE(fdi_tx_reg, temp);
1573
1574 temp = I915_READ(fdi_rx_reg);
1575 temp &= ~FDI_LINK_TRAIN_NONE;
1576 temp |= FDI_LINK_TRAIN_PATTERN_2;
1577 I915_WRITE(fdi_rx_reg, temp);
1578 udelay(150);
1579
1580 tries = 0;
1581
1582 for (;;) {
1583 temp = I915_READ(fdi_rx_iir_reg);
1584 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1585
1586 if (temp & FDI_RX_SYMBOL_LOCK) {
1587 I915_WRITE(fdi_rx_iir_reg,
1588 temp | FDI_RX_SYMBOL_LOCK);
1589 DRM_DEBUG_KMS("FDI train 2 done.\n");
1590 break;
1591 }
1592
1593 tries++;
1594
1595 if (tries > 5) {
1596 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1597 break;
1598 }
1599 }
1600
1601 DRM_DEBUG_KMS("FDI train done\n");
1602}
1603
1604static int snb_b_fdi_train_param [] = {
1605 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1606 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1607 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1608 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1609};
1610
1611/* The FDI link training functions for SNB/Cougarpoint. */
1612static void gen6_fdi_link_train(struct drm_crtc *crtc)
1613{
1614 struct drm_device *dev = crtc->dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1617 int pipe = intel_crtc->pipe;
1618 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1619 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1620 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1621 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1622 u32 temp, i;
1623
1624 /* enable CPU FDI TX and PCH FDI RX */
1625 temp = I915_READ(fdi_tx_reg);
1626 temp |= FDI_TX_ENABLE;
1627 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1628 temp &= ~FDI_LINK_TRAIN_NONE;
1629 temp |= FDI_LINK_TRAIN_PATTERN_1;
1630 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1631 /* SNB-B */
1632 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1633 I915_WRITE(fdi_tx_reg, temp);
1634 I915_READ(fdi_tx_reg);
1635
1636 temp = I915_READ(fdi_rx_reg);
1637 if (HAS_PCH_CPT(dev)) {
1638 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1639 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1640 } else {
1641 temp &= ~FDI_LINK_TRAIN_NONE;
1642 temp |= FDI_LINK_TRAIN_PATTERN_1;
1643 }
1644 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1645 I915_READ(fdi_rx_reg);
1646 udelay(150);
1647
1648 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1649 for train result */
1650 temp = I915_READ(fdi_rx_imr_reg);
1651 temp &= ~FDI_RX_SYMBOL_LOCK;
1652 temp &= ~FDI_RX_BIT_LOCK;
1653 I915_WRITE(fdi_rx_imr_reg, temp);
1654 I915_READ(fdi_rx_imr_reg);
1655 udelay(150);
1656
1657 for (i = 0; i < 4; i++ ) {
1658 temp = I915_READ(fdi_tx_reg);
1659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1660 temp |= snb_b_fdi_train_param[i];
1661 I915_WRITE(fdi_tx_reg, temp);
1662 udelay(500);
1663
1664 temp = I915_READ(fdi_rx_iir_reg);
1665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1666
1667 if (temp & FDI_RX_BIT_LOCK) {
1668 I915_WRITE(fdi_rx_iir_reg,
1669 temp | FDI_RX_BIT_LOCK);
1670 DRM_DEBUG_KMS("FDI train 1 done.\n");
1671 break;
1672 }
1673 }
1674 if (i == 4)
1675 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1676
1677 /* Train 2 */
1678 temp = I915_READ(fdi_tx_reg);
1679 temp &= ~FDI_LINK_TRAIN_NONE;
1680 temp |= FDI_LINK_TRAIN_PATTERN_2;
1681 if (IS_GEN6(dev)) {
1682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1683 /* SNB-B */
1684 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1685 }
1686 I915_WRITE(fdi_tx_reg, temp);
1687
1688 temp = I915_READ(fdi_rx_reg);
1689 if (HAS_PCH_CPT(dev)) {
1690 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1691 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1692 } else {
1693 temp &= ~FDI_LINK_TRAIN_NONE;
1694 temp |= FDI_LINK_TRAIN_PATTERN_2;
1695 }
1696 I915_WRITE(fdi_rx_reg, temp);
1697 udelay(150);
1698
1699 for (i = 0; i < 4; i++ ) {
1700 temp = I915_READ(fdi_tx_reg);
1701 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1702 temp |= snb_b_fdi_train_param[i];
1703 I915_WRITE(fdi_tx_reg, temp);
1704 udelay(500);
1705
1706 temp = I915_READ(fdi_rx_iir_reg);
1707 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1708
1709 if (temp & FDI_RX_SYMBOL_LOCK) {
1710 I915_WRITE(fdi_rx_iir_reg,
1711 temp | FDI_RX_SYMBOL_LOCK);
1712 DRM_DEBUG_KMS("FDI train 2 done.\n");
1713 break;
1714 }
1715 }
1716 if (i == 4)
1717 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1718
1719 DRM_DEBUG_KMS("FDI train done.\n");
1720}
1721
1511static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) 1722static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1512{ 1723{
1513 struct drm_device *dev = crtc->dev; 1724 struct drm_device *dev = crtc->dev;
@@ -1521,8 +1732,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1521 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; 1732 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1522 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; 1733 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1523 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 1734 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1524 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1525 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1526 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; 1735 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1527 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; 1736 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1528 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ; 1737 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
@@ -1539,8 +1748,9 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1539 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; 1748 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1540 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; 1749 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1541 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1750 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1751 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1542 u32 temp; 1752 u32 temp;
1543 int tries = 5, j, n; 1753 int n;
1544 u32 pipe_bpc; 1754 u32 pipe_bpc;
1545 1755
1546 temp = I915_READ(pipeconf_reg); 1756 temp = I915_READ(pipeconf_reg);
@@ -1567,12 +1777,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1567 /* enable eDP PLL */ 1777 /* enable eDP PLL */
1568 ironlake_enable_pll_edp(crtc); 1778 ironlake_enable_pll_edp(crtc);
1569 } else { 1779 } else {
1570 /* enable PCH DPLL */
1571 temp = I915_READ(pch_dpll_reg);
1572 if ((temp & DPLL_VCO_ENABLE) == 0) {
1573 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1574 I915_READ(pch_dpll_reg);
1575 }
1576 1780
1577 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1781 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1578 temp = I915_READ(fdi_rx_reg); 1782 temp = I915_READ(fdi_rx_reg);
@@ -1583,11 +1787,16 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1583 temp &= ~(0x7 << 16); 1787 temp &= ~(0x7 << 16);
1584 temp |= (pipe_bpc << 11); 1788 temp |= (pipe_bpc << 11);
1585 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | 1789 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1586 FDI_SEL_PCDCLK |
1587 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ 1790 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1588 I915_READ(fdi_rx_reg); 1791 I915_READ(fdi_rx_reg);
1589 udelay(200); 1792 udelay(200);
1590 1793
1794 /* Switch from Rawclk to PCDclk */
1795 temp = I915_READ(fdi_rx_reg);
1796 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1797 I915_READ(fdi_rx_reg);
1798 udelay(200);
1799
1591 /* Enable CPU FDI TX PLL, always on for Ironlake */ 1800 /* Enable CPU FDI TX PLL, always on for Ironlake */
1592 temp = I915_READ(fdi_tx_reg); 1801 temp = I915_READ(fdi_tx_reg);
1593 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 1802 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
@@ -1627,91 +1836,32 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1627 } 1836 }
1628 1837
1629 if (!HAS_eDP) { 1838 if (!HAS_eDP) {
1630 /* enable CPU FDI TX and PCH FDI RX */ 1839 /* For PCH output, training FDI link */
1631 temp = I915_READ(fdi_tx_reg); 1840 if (IS_GEN6(dev))
1632 temp |= FDI_TX_ENABLE; 1841 gen6_fdi_link_train(crtc);
1633 temp |= FDI_DP_PORT_WIDTH_X4; /* default */ 1842 else
1634 temp &= ~FDI_LINK_TRAIN_NONE; 1843 ironlake_fdi_link_train(crtc);
1635 temp |= FDI_LINK_TRAIN_PATTERN_1;
1636 I915_WRITE(fdi_tx_reg, temp);
1637 I915_READ(fdi_tx_reg);
1638
1639 temp = I915_READ(fdi_rx_reg);
1640 temp &= ~FDI_LINK_TRAIN_NONE;
1641 temp |= FDI_LINK_TRAIN_PATTERN_1;
1642 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1643 I915_READ(fdi_rx_reg);
1644
1645 udelay(150);
1646
1647 /* Train FDI. */
1648 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1649 for train result */
1650 temp = I915_READ(fdi_rx_imr_reg);
1651 temp &= ~FDI_RX_SYMBOL_LOCK;
1652 temp &= ~FDI_RX_BIT_LOCK;
1653 I915_WRITE(fdi_rx_imr_reg, temp);
1654 I915_READ(fdi_rx_imr_reg);
1655 udelay(150);
1656 1844
1657 temp = I915_READ(fdi_rx_iir_reg); 1845 /* enable PCH DPLL */
1658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 1846 temp = I915_READ(pch_dpll_reg);
1659 1847 if ((temp & DPLL_VCO_ENABLE) == 0) {
1660 if ((temp & FDI_RX_BIT_LOCK) == 0) { 1848 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1661 for (j = 0; j < tries; j++) { 1849 I915_READ(pch_dpll_reg);
1662 temp = I915_READ(fdi_rx_iir_reg);
1663 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1664 temp);
1665 if (temp & FDI_RX_BIT_LOCK)
1666 break;
1667 udelay(200);
1668 }
1669 if (j != tries)
1670 I915_WRITE(fdi_rx_iir_reg,
1671 temp | FDI_RX_BIT_LOCK);
1672 else
1673 DRM_DEBUG_KMS("train 1 fail\n");
1674 } else {
1675 I915_WRITE(fdi_rx_iir_reg,
1676 temp | FDI_RX_BIT_LOCK);
1677 DRM_DEBUG_KMS("train 1 ok 2!\n");
1678 } 1850 }
1679 temp = I915_READ(fdi_tx_reg); 1851 udelay(200);
1680 temp &= ~FDI_LINK_TRAIN_NONE;
1681 temp |= FDI_LINK_TRAIN_PATTERN_2;
1682 I915_WRITE(fdi_tx_reg, temp);
1683
1684 temp = I915_READ(fdi_rx_reg);
1685 temp &= ~FDI_LINK_TRAIN_NONE;
1686 temp |= FDI_LINK_TRAIN_PATTERN_2;
1687 I915_WRITE(fdi_rx_reg, temp);
1688
1689 udelay(150);
1690 1852
1691 temp = I915_READ(fdi_rx_iir_reg); 1853 if (HAS_PCH_CPT(dev)) {
1692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 1854 /* Be sure PCH DPLL SEL is set */
1693 1855 temp = I915_READ(PCH_DPLL_SEL);
1694 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { 1856 if (trans_dpll_sel == 0 &&
1695 for (j = 0; j < tries; j++) { 1857 (temp & TRANSA_DPLL_ENABLE) == 0)
1696 temp = I915_READ(fdi_rx_iir_reg); 1858 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1697 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", 1859 else if (trans_dpll_sel == 1 &&
1698 temp); 1860 (temp & TRANSB_DPLL_ENABLE) == 0)
1699 if (temp & FDI_RX_SYMBOL_LOCK) 1861 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1700 break; 1862 I915_WRITE(PCH_DPLL_SEL, temp);
1701 udelay(200); 1863 I915_READ(PCH_DPLL_SEL);
1702 }
1703 if (j != tries) {
1704 I915_WRITE(fdi_rx_iir_reg,
1705 temp | FDI_RX_SYMBOL_LOCK);
1706 DRM_DEBUG_KMS("train 2 ok 1!\n");
1707 } else
1708 DRM_DEBUG_KMS("train 2 fail\n");
1709 } else {
1710 I915_WRITE(fdi_rx_iir_reg,
1711 temp | FDI_RX_SYMBOL_LOCK);
1712 DRM_DEBUG_KMS("train 2 ok 2!\n");
1713 } 1864 }
1714 DRM_DEBUG_KMS("train done\n");
1715 1865
1716 /* set transcoder timing */ 1866 /* set transcoder timing */
1717 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); 1867 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
@@ -1722,6 +1872,27 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1722 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); 1872 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1723 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); 1873 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1724 1874
1875 /* enable normal train */
1876 temp = I915_READ(fdi_tx_reg);
1877 temp &= ~FDI_LINK_TRAIN_NONE;
1878 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1879 FDI_TX_ENHANCE_FRAME_ENABLE);
1880 I915_READ(fdi_tx_reg);
1881
1882 temp = I915_READ(fdi_rx_reg);
1883 if (HAS_PCH_CPT(dev)) {
1884 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1885 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1886 } else {
1887 temp &= ~FDI_LINK_TRAIN_NONE;
1888 temp |= FDI_LINK_TRAIN_NONE;
1889 }
1890 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1891 I915_READ(fdi_rx_reg);
1892
1893 /* wait one idle pattern time */
1894 udelay(100);
1895
1725 /* enable PCH transcoder */ 1896 /* enable PCH transcoder */
1726 temp = I915_READ(transconf_reg); 1897 temp = I915_READ(transconf_reg);
1727 /* 1898 /*
@@ -1736,23 +1907,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1736 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) 1907 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1737 ; 1908 ;
1738 1909
1739 /* enable normal */
1740
1741 temp = I915_READ(fdi_tx_reg);
1742 temp &= ~FDI_LINK_TRAIN_NONE;
1743 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1744 FDI_TX_ENHANCE_FRAME_ENABLE);
1745 I915_READ(fdi_tx_reg);
1746
1747 temp = I915_READ(fdi_rx_reg);
1748 temp &= ~FDI_LINK_TRAIN_NONE;
1749 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1750 FDI_RX_ENHANCE_FRAME_ENABLE);
1751 I915_READ(fdi_rx_reg);
1752
1753 /* wait one idle pattern time */
1754 udelay(100);
1755
1756 } 1910 }
1757 1911
1758 intel_crtc_load_lut(crtc); 1912 intel_crtc_load_lut(crtc);
@@ -1803,6 +1957,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1803 I915_READ(pf_ctl_reg); 1957 I915_READ(pf_ctl_reg);
1804 } 1958 }
1805 I915_WRITE(pf_win_size, 0); 1959 I915_WRITE(pf_win_size, 0);
1960 POSTING_READ(pf_win_size);
1961
1806 1962
1807 /* disable CPU FDI tx and PCH FDI rx */ 1963 /* disable CPU FDI tx and PCH FDI rx */
1808 temp = I915_READ(fdi_tx_reg); 1964 temp = I915_READ(fdi_tx_reg);
@@ -1823,11 +1979,18 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1823 temp &= ~FDI_LINK_TRAIN_NONE; 1979 temp &= ~FDI_LINK_TRAIN_NONE;
1824 temp |= FDI_LINK_TRAIN_PATTERN_1; 1980 temp |= FDI_LINK_TRAIN_PATTERN_1;
1825 I915_WRITE(fdi_tx_reg, temp); 1981 I915_WRITE(fdi_tx_reg, temp);
1982 POSTING_READ(fdi_tx_reg);
1826 1983
1827 temp = I915_READ(fdi_rx_reg); 1984 temp = I915_READ(fdi_rx_reg);
1828 temp &= ~FDI_LINK_TRAIN_NONE; 1985 if (HAS_PCH_CPT(dev)) {
1829 temp |= FDI_LINK_TRAIN_PATTERN_1; 1986 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1987 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1988 } else {
1989 temp &= ~FDI_LINK_TRAIN_NONE;
1990 temp |= FDI_LINK_TRAIN_PATTERN_1;
1991 }
1830 I915_WRITE(fdi_rx_reg, temp); 1992 I915_WRITE(fdi_rx_reg, temp);
1993 POSTING_READ(fdi_rx_reg);
1831 1994
1832 udelay(100); 1995 udelay(100);
1833 1996
@@ -1857,6 +2020,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1857 } 2020 }
1858 } 2021 }
1859 } 2022 }
2023
1860 temp = I915_READ(transconf_reg); 2024 temp = I915_READ(transconf_reg);
1861 /* BPC in transcoder is consistent with that in pipeconf */ 2025 /* BPC in transcoder is consistent with that in pipeconf */
1862 temp &= ~PIPE_BPC_MASK; 2026 temp &= ~PIPE_BPC_MASK;
@@ -1865,35 +2029,45 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1865 I915_READ(transconf_reg); 2029 I915_READ(transconf_reg);
1866 udelay(100); 2030 udelay(100);
1867 2031
2032 if (HAS_PCH_CPT(dev)) {
2033
2034 /* disable DPLL_SEL */
2035 temp = I915_READ(PCH_DPLL_SEL);
2036 if (trans_dpll_sel == 0)
2037 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2038 else
2039 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2040 I915_WRITE(PCH_DPLL_SEL, temp);
2041 I915_READ(PCH_DPLL_SEL);
2042
2043 }
2044
1868 /* disable PCH DPLL */ 2045 /* disable PCH DPLL */
1869 temp = I915_READ(pch_dpll_reg); 2046 temp = I915_READ(pch_dpll_reg);
1870 if ((temp & DPLL_VCO_ENABLE) != 0) { 2047 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1871 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); 2048 I915_READ(pch_dpll_reg);
1872 I915_READ(pch_dpll_reg);
1873 }
1874 2049
1875 if (HAS_eDP) { 2050 if (HAS_eDP) {
1876 ironlake_disable_pll_edp(crtc); 2051 ironlake_disable_pll_edp(crtc);
1877 } 2052 }
1878 2053
2054 /* Switch from PCDclk to Rawclk */
1879 temp = I915_READ(fdi_rx_reg); 2055 temp = I915_READ(fdi_rx_reg);
1880 temp &= ~FDI_SEL_PCDCLK; 2056 temp &= ~FDI_SEL_PCDCLK;
1881 I915_WRITE(fdi_rx_reg, temp); 2057 I915_WRITE(fdi_rx_reg, temp);
1882 I915_READ(fdi_rx_reg); 2058 I915_READ(fdi_rx_reg);
1883 2059
2060 /* Disable CPU FDI TX PLL */
2061 temp = I915_READ(fdi_tx_reg);
2062 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2063 I915_READ(fdi_tx_reg);
2064 udelay(100);
2065
1884 temp = I915_READ(fdi_rx_reg); 2066 temp = I915_READ(fdi_rx_reg);
1885 temp &= ~FDI_RX_PLL_ENABLE; 2067 temp &= ~FDI_RX_PLL_ENABLE;
1886 I915_WRITE(fdi_rx_reg, temp); 2068 I915_WRITE(fdi_rx_reg, temp);
1887 I915_READ(fdi_rx_reg); 2069 I915_READ(fdi_rx_reg);
1888 2070
1889 /* Disable CPU FDI TX PLL */
1890 temp = I915_READ(fdi_tx_reg);
1891 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1892 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1893 I915_READ(fdi_tx_reg);
1894 udelay(100);
1895 }
1896
1897 /* Wait for the clocks to turn off. */ 2071 /* Wait for the clocks to turn off. */
1898 udelay(100); 2072 udelay(100);
1899 break; 2073 break;
@@ -2934,6 +3108,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2934 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0; 3108 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2935 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; 3109 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2936 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 3110 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3111 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3112 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
2937 int lvds_reg = LVDS; 3113 int lvds_reg = LVDS;
2938 u32 temp; 3114 u32 temp;
2939 int sdvo_pixel_multiply; 3115 int sdvo_pixel_multiply;
@@ -3292,6 +3468,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3292 udelay(150); 3468 udelay(150);
3293 } 3469 }
3294 3470
3471 /* enable transcoder DPLL */
3472 if (HAS_PCH_CPT(dev)) {
3473 temp = I915_READ(PCH_DPLL_SEL);
3474 if (trans_dpll_sel == 0)
3475 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3476 else
3477 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3478 I915_WRITE(PCH_DPLL_SEL, temp);
3479 I915_READ(PCH_DPLL_SEL);
3480 udelay(150);
3481 }
3482
3295 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 3483 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3296 * This is an exception to the general rule that mode_set doesn't turn 3484 * This is an exception to the general rule that mode_set doesn't turn
3297 * things on. 3485 * things on.
@@ -3341,6 +3529,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3341 } 3529 }
3342 if (is_dp) 3530 if (is_dp)
3343 intel_dp_set_m_n(crtc, mode, adjusted_mode); 3531 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3532 else if (HAS_PCH_SPLIT(dev)) {
3533 /* For non-DP output, clear any trans DP clock recovery setting.*/
3534 if (pipe == 0) {
3535 I915_WRITE(TRANSA_DATA_M1, 0);
3536 I915_WRITE(TRANSA_DATA_N1, 0);
3537 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3538 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3539 } else {
3540 I915_WRITE(TRANSB_DATA_M1, 0);
3541 I915_WRITE(TRANSB_DATA_N1, 0);
3542 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3543 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3544 }
3545 }
3344 3546
3345 if (!is_edp) { 3547 if (!is_edp) {
3346 I915_WRITE(fp_reg, fp); 3548 I915_WRITE(fp_reg, fp);
@@ -3415,6 +3617,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3415 /* enable FDI RX PLL too */ 3617 /* enable FDI RX PLL too */
3416 temp = I915_READ(fdi_rx_reg); 3618 temp = I915_READ(fdi_rx_reg);
3417 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); 3619 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3620 I915_READ(fdi_rx_reg);
3621 udelay(200);
3622
3623 /* enable FDI TX PLL too */
3624 temp = I915_READ(fdi_tx_reg);
3625 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3626 I915_READ(fdi_tx_reg);
3627
3628 /* enable FDI RX PCDCLK */
3629 temp = I915_READ(fdi_rx_reg);
3630 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3631 I915_READ(fdi_rx_reg);
3418 udelay(200); 3632 udelay(200);
3419 } 3633 }
3420 } 3634 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 19:34:51 -0400