diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-10 02:45:24 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-02 23:12:46 -0400 |
commit | 8aceb7de47ea2491abc1a577dc875b19e9947a54 (patch) | |
tree | 3645a1980be8d4d2b1689475d9e72fd7a4b9c8b9 /drivers | |
parent | 4196faa8623264b79279a06fd186654c959f2767 (diff) |
drm/nouveau/clk: implement stub clock subdev
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/nouveau/Makefile | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/include/subdev/clock.h | 40 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c | 65 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c | 65 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c | 65 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c | 65 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c | 65 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nv04.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nv10.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nv20.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nv30.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nv40.c | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nv50.c | 15 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nve0.c | 3 |
15 files changed, 437 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index 40ce4e18e7e..2964d71d399 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile | |||
@@ -23,6 +23,11 @@ nouveau-y += core/subdev/bios/bit.o | |||
23 | nouveau-y += core/subdev/bios/dcb.o | 23 | nouveau-y += core/subdev/bios/dcb.o |
24 | nouveau-y += core/subdev/bios/gpio.o | 24 | nouveau-y += core/subdev/bios/gpio.o |
25 | nouveau-y += core/subdev/bios/i2c.o | 25 | nouveau-y += core/subdev/bios/i2c.o |
26 | nouveau-y += core/subdev/clock/nv04.o | ||
27 | nouveau-y += core/subdev/clock/nv40.o | ||
28 | nouveau-y += core/subdev/clock/nv50.o | ||
29 | nouveau-y += core/subdev/clock/nva3.o | ||
30 | nouveau-y += core/subdev/clock/nvc0.o | ||
26 | nouveau-y += core/subdev/device/base.o | 31 | nouveau-y += core/subdev/device/base.o |
27 | nouveau-y += core/subdev/device/nv04.o | 32 | nouveau-y += core/subdev/device/nv04.o |
28 | nouveau-y += core/subdev/device/nv10.o | 33 | nouveau-y += core/subdev/device/nv10.o |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h new file mode 100644 index 00000000000..137c4598a1b --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h | |||
@@ -0,0 +1,40 @@ | |||
1 | #ifndef __NOUVEAU_CLOCK_H__ | ||
2 | #define __NOUVEAU_CLOCK_H__ | ||
3 | |||
4 | #include <core/device.h> | ||
5 | #include <core/subdev.h> | ||
6 | |||
7 | struct nouveau_clock { | ||
8 | struct nouveau_subdev base; | ||
9 | void (*pll_set)(struct nouveau_clock *, u32 type, u32 freq); | ||
10 | }; | ||
11 | |||
12 | static inline struct nouveau_clock * | ||
13 | nouveau_clock(void *obj) | ||
14 | { | ||
15 | return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_CLOCK]; | ||
16 | } | ||
17 | |||
18 | #define nouveau_clock_create(p,e,o,d) \ | ||
19 | nouveau_subdev_create((p), (e), (o), 0, "CLOCK", "clock", d) | ||
20 | #define nouveau_clock_destroy(p) \ | ||
21 | nouveau_subdev_destroy(&(p)->base) | ||
22 | #define nouveau_clock_init(p) \ | ||
23 | nouveau_subdev_init(&(p)->base) | ||
24 | #define nouveau_clock_fini(p,s) \ | ||
25 | nouveau_subdev_fini(&(p)->base, (s)) | ||
26 | |||
27 | int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *, | ||
28 | struct nouveau_oclass *, void *, u32, int, void **); | ||
29 | |||
30 | #define _nouveau_clock_dtor _nouveau_subdev_dtor | ||
31 | #define _nouveau_clock_init _nouveau_subdev_init | ||
32 | #define _nouveau_clock_fini _nouveau_subdev_fini | ||
33 | |||
34 | extern struct nouveau_oclass nv04_clock_oclass; | ||
35 | extern struct nouveau_oclass nv40_clock_oclass; | ||
36 | extern struct nouveau_oclass nv50_clock_oclass; | ||
37 | extern struct nouveau_oclass nva3_clock_oclass; | ||
38 | extern struct nouveau_oclass nvc0_clock_oclass; | ||
39 | |||
40 | #endif | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c new file mode 100644 index 00000000000..3a3b3b14969 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include <subdev/clock.h> | ||
26 | |||
27 | struct nv04_clock_priv { | ||
28 | struct nouveau_clock base; | ||
29 | }; | ||
30 | |||
31 | static void | ||
32 | nv04_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) | ||
33 | { | ||
34 | struct nv04_clock_priv *priv = (void *)clk; | ||
35 | |||
36 | nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq); | ||
37 | } | ||
38 | |||
39 | static int | ||
40 | nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | ||
41 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
42 | struct nouveau_object **pobject) | ||
43 | { | ||
44 | struct nv04_clock_priv *priv; | ||
45 | int ret; | ||
46 | |||
47 | ret = nouveau_clock_create(parent, engine, oclass, &priv); | ||
48 | *pobject = nv_object(priv); | ||
49 | if (ret) | ||
50 | return ret; | ||
51 | |||
52 | priv->base.pll_set = nv04_clock_pll_set; | ||
53 | return 0; | ||
54 | } | ||
55 | |||
56 | struct nouveau_oclass | ||
57 | nv04_clock_oclass = { | ||
58 | .handle = NV_SUBDEV(CLOCK, 0x04), | ||
59 | .ofuncs = &(struct nouveau_ofuncs) { | ||
60 | .ctor = nv04_clock_ctor, | ||
61 | .dtor = _nouveau_clock_dtor, | ||
62 | .init = _nouveau_clock_init, | ||
63 | .fini = _nouveau_clock_fini, | ||
64 | }, | ||
65 | }; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c new file mode 100644 index 00000000000..60d1ca44e39 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include <subdev/clock.h> | ||
26 | |||
27 | struct nv40_clock_priv { | ||
28 | struct nouveau_clock base; | ||
29 | }; | ||
30 | |||
31 | static void | ||
32 | nv40_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) | ||
33 | { | ||
34 | struct nv40_clock_priv *priv = (void *)clk; | ||
35 | |||
36 | nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq); | ||
37 | } | ||
38 | |||
39 | static int | ||
40 | nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | ||
41 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
42 | struct nouveau_object **pobject) | ||
43 | { | ||
44 | struct nv40_clock_priv *priv; | ||
45 | int ret; | ||
46 | |||
47 | ret = nouveau_clock_create(parent, engine, oclass, &priv); | ||
48 | *pobject = nv_object(priv); | ||
49 | if (ret) | ||
50 | return ret; | ||
51 | |||
52 | priv->base.pll_set = nv40_clock_pll_set; | ||
53 | return 0; | ||
54 | } | ||
55 | |||
56 | struct nouveau_oclass | ||
57 | nv40_clock_oclass = { | ||
58 | .handle = NV_SUBDEV(CLOCK, 0x40), | ||
59 | .ofuncs = &(struct nouveau_ofuncs) { | ||
60 | .ctor = nv40_clock_ctor, | ||
61 | .dtor = _nouveau_clock_dtor, | ||
62 | .init = _nouveau_clock_init, | ||
63 | .fini = _nouveau_clock_fini, | ||
64 | }, | ||
65 | }; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c new file mode 100644 index 00000000000..82804bdcec3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include <subdev/clock.h> | ||
26 | |||
27 | struct nv50_clock_priv { | ||
28 | struct nouveau_clock base; | ||
29 | }; | ||
30 | |||
31 | static void | ||
32 | nv50_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) | ||
33 | { | ||
34 | struct nv50_clock_priv *priv = (void *)clk; | ||
35 | |||
36 | nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq); | ||
37 | } | ||
38 | |||
39 | static int | ||
40 | nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | ||
41 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
42 | struct nouveau_object **pobject) | ||
43 | { | ||
44 | struct nv50_clock_priv *priv; | ||
45 | int ret; | ||
46 | |||
47 | ret = nouveau_clock_create(parent, engine, oclass, &priv); | ||
48 | *pobject = nv_object(priv); | ||
49 | if (ret) | ||
50 | return ret; | ||
51 | |||
52 | priv->base.pll_set = nv50_clock_pll_set; | ||
53 | return 0; | ||
54 | } | ||
55 | |||
56 | struct nouveau_oclass | ||
57 | nv50_clock_oclass = { | ||
58 | .handle = NV_SUBDEV(CLOCK, 0x50), | ||
59 | .ofuncs = &(struct nouveau_ofuncs) { | ||
60 | .ctor = nv50_clock_ctor, | ||
61 | .dtor = _nouveau_clock_dtor, | ||
62 | .init = _nouveau_clock_init, | ||
63 | .fini = _nouveau_clock_fini, | ||
64 | }, | ||
65 | }; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c new file mode 100644 index 00000000000..876ec46e2b4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include <subdev/clock.h> | ||
26 | |||
27 | struct nva3_clock_priv { | ||
28 | struct nouveau_clock base; | ||
29 | }; | ||
30 | |||
31 | static void | ||
32 | nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) | ||
33 | { | ||
34 | struct nva3_clock_priv *priv = (void *)clk; | ||
35 | |||
36 | nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq); | ||
37 | } | ||
38 | |||
39 | static int | ||
40 | nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | ||
41 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
42 | struct nouveau_object **pobject) | ||
43 | { | ||
44 | struct nva3_clock_priv *priv; | ||
45 | int ret; | ||
46 | |||
47 | ret = nouveau_clock_create(parent, engine, oclass, &priv); | ||
48 | *pobject = nv_object(priv); | ||
49 | if (ret) | ||
50 | return ret; | ||
51 | |||
52 | priv->base.pll_set = nva3_clock_pll_set; | ||
53 | return 0; | ||
54 | } | ||
55 | |||
56 | struct nouveau_oclass | ||
57 | nva3_clock_oclass = { | ||
58 | .handle = NV_SUBDEV(CLOCK, 0xa3), | ||
59 | .ofuncs = &(struct nouveau_ofuncs) { | ||
60 | .ctor = nva3_clock_ctor, | ||
61 | .dtor = _nouveau_clock_dtor, | ||
62 | .init = _nouveau_clock_init, | ||
63 | .fini = _nouveau_clock_fini, | ||
64 | }, | ||
65 | }; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c new file mode 100644 index 00000000000..00641566f2e --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include <subdev/clock.h> | ||
26 | |||
27 | struct nvc0_clock_priv { | ||
28 | struct nouveau_clock base; | ||
29 | }; | ||
30 | |||
31 | static void | ||
32 | nvc0_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) | ||
33 | { | ||
34 | struct nvc0_clock_priv *priv = (void *)clk; | ||
35 | |||
36 | nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq); | ||
37 | } | ||
38 | |||
39 | static int | ||
40 | nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | ||
41 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
42 | struct nouveau_object **pobject) | ||
43 | { | ||
44 | struct nvc0_clock_priv *priv; | ||
45 | int ret; | ||
46 | |||
47 | ret = nouveau_clock_create(parent, engine, oclass, &priv); | ||
48 | *pobject = nv_object(priv); | ||
49 | if (ret) | ||
50 | return ret; | ||
51 | |||
52 | priv->base.pll_set = nvc0_clock_pll_set; | ||
53 | return 0; | ||
54 | } | ||
55 | |||
56 | struct nouveau_oclass | ||
57 | nvc0_clock_oclass = { | ||
58 | .handle = NV_SUBDEV(CLOCK, 0xc0), | ||
59 | .ofuncs = &(struct nouveau_ofuncs) { | ||
60 | .ctor = nvc0_clock_ctor, | ||
61 | .dtor = _nouveau_clock_dtor, | ||
62 | .init = _nouveau_clock_init, | ||
63 | .fini = _nouveau_clock_fini, | ||
64 | }, | ||
65 | }; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv04.c index e0ebbe184c9..e24e74b9c43 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv04.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <subdev/device.h> | 25 | #include <subdev/device.h> |
26 | #include <subdev/bios.h> | 26 | #include <subdev/bios.h> |
27 | #include <subdev/i2c.h> | 27 | #include <subdev/i2c.h> |
28 | #include <subdev/clock.h> | ||
28 | 29 | ||
29 | int | 30 | int |
30 | nv04_identify(struct nouveau_device *device) | 31 | nv04_identify(struct nouveau_device *device) |
@@ -33,10 +34,12 @@ nv04_identify(struct nouveau_device *device) | |||
33 | case 0x04: | 34 | case 0x04: |
34 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 35 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
35 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 36 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
37 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
36 | break; | 38 | break; |
37 | case 0x05: | 39 | case 0x05: |
38 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 40 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
39 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 41 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
42 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
40 | break; | 43 | break; |
41 | default: | 44 | default: |
42 | nv_fatal(device, "unknown RIVA chipset\n"); | 45 | nv_fatal(device, "unknown RIVA chipset\n"); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv10.c index 19b1de60db2..0b8eb741686 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nv10.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv10.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <subdev/bios.h> | 26 | #include <subdev/bios.h> |
27 | #include <subdev/gpio.h> | 27 | #include <subdev/gpio.h> |
28 | #include <subdev/i2c.h> | 28 | #include <subdev/i2c.h> |
29 | #include <subdev/clock.h> | ||
29 | 30 | ||
30 | int | 31 | int |
31 | nv10_identify(struct nouveau_device *device) | 32 | nv10_identify(struct nouveau_device *device) |
@@ -35,41 +36,49 @@ nv10_identify(struct nouveau_device *device) | |||
35 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 36 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
36 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 37 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
37 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 38 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
39 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
38 | break; | 40 | break; |
39 | case 0x15: | 41 | case 0x15: |
40 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 42 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
41 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 43 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
42 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 44 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
45 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
43 | break; | 46 | break; |
44 | case 0x16: | 47 | case 0x16: |
45 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 48 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
46 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 49 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
47 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 50 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
51 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
48 | break; | 52 | break; |
49 | case 0x1a: | 53 | case 0x1a: |
50 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 54 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
51 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 55 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
52 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 56 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
57 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
53 | break; | 58 | break; |
54 | case 0x11: | 59 | case 0x11: |
55 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
56 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
57 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
63 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
58 | break; | 64 | break; |
59 | case 0x17: | 65 | case 0x17: |
60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 66 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 67 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 68 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
69 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
63 | break; | 70 | break; |
64 | case 0x1f: | 71 | case 0x1f: |
65 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 72 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
66 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 73 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
67 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 74 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
75 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
68 | break; | 76 | break; |
69 | case 0x18: | 77 | case 0x18: |
70 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 78 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
71 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 79 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
72 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 80 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
81 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
73 | break; | 82 | break; |
74 | default: | 83 | default: |
75 | nv_fatal(device, "unknown Celsius chipset\n"); | 84 | nv_fatal(device, "unknown Celsius chipset\n"); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv20.c index 8f735275b88..1432ef046b7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nv20.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv20.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <subdev/bios.h> | 26 | #include <subdev/bios.h> |
27 | #include <subdev/gpio.h> | 27 | #include <subdev/gpio.h> |
28 | #include <subdev/i2c.h> | 28 | #include <subdev/i2c.h> |
29 | #include <subdev/clock.h> | ||
29 | 30 | ||
30 | int | 31 | int |
31 | nv20_identify(struct nouveau_device *device) | 32 | nv20_identify(struct nouveau_device *device) |
@@ -35,21 +36,25 @@ nv20_identify(struct nouveau_device *device) | |||
35 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 36 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
36 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 37 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
37 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 38 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
39 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
38 | break; | 40 | break; |
39 | case 0x25: | 41 | case 0x25: |
40 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 42 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
41 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 43 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
42 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 44 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
45 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
43 | break; | 46 | break; |
44 | case 0x28: | 47 | case 0x28: |
45 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 48 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
46 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 49 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
47 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 50 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
51 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
48 | break; | 52 | break; |
49 | case 0x2a: | 53 | case 0x2a: |
50 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 54 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
51 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 55 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
52 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 56 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
57 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
53 | break; | 58 | break; |
54 | default: | 59 | default: |
55 | nv_fatal(device, "unknown Kelvin chipset\n"); | 60 | nv_fatal(device, "unknown Kelvin chipset\n"); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv30.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv30.c index eefc3455bd2..7eeab784179 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nv30.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv30.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <subdev/bios.h> | 26 | #include <subdev/bios.h> |
27 | #include <subdev/gpio.h> | 27 | #include <subdev/gpio.h> |
28 | #include <subdev/i2c.h> | 28 | #include <subdev/i2c.h> |
29 | #include <subdev/clock.h> | ||
29 | 30 | ||
30 | int | 31 | int |
31 | nv30_identify(struct nouveau_device *device) | 32 | nv30_identify(struct nouveau_device *device) |
@@ -35,26 +36,31 @@ nv30_identify(struct nouveau_device *device) | |||
35 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 36 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
36 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 37 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
37 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 38 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
39 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
38 | break; | 40 | break; |
39 | case 0x35: | 41 | case 0x35: |
40 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 42 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
41 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 43 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
42 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 44 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
45 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
43 | break; | 46 | break; |
44 | case 0x31: | 47 | case 0x31: |
45 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 48 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
46 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 49 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
47 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 50 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
51 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
48 | break; | 52 | break; |
49 | case 0x36: | 53 | case 0x36: |
50 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 54 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
51 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 55 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
52 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 56 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
57 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
53 | break; | 58 | break; |
54 | case 0x34: | 59 | case 0x34: |
55 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
56 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
57 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
63 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | ||
58 | break; | 64 | break; |
59 | default: | 65 | default: |
60 | nv_fatal(device, "unknown Rankine chipset\n"); | 66 | nv_fatal(device, "unknown Rankine chipset\n"); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c index 63047c5bfdc..ec7c03f96d7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <subdev/bios.h> | 26 | #include <subdev/bios.h> |
27 | #include <subdev/gpio.h> | 27 | #include <subdev/gpio.h> |
28 | #include <subdev/i2c.h> | 28 | #include <subdev/i2c.h> |
29 | #include <subdev/clock.h> | ||
29 | 30 | ||
30 | int | 31 | int |
31 | nv40_identify(struct nouveau_device *device) | 32 | nv40_identify(struct nouveau_device *device) |
@@ -35,81 +36,97 @@ nv40_identify(struct nouveau_device *device) | |||
35 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 36 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
36 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 37 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
37 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 38 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
39 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
38 | break; | 40 | break; |
39 | case 0x41: | 41 | case 0x41: |
40 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 42 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
41 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 43 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
42 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 44 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
45 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
43 | break; | 46 | break; |
44 | case 0x42: | 47 | case 0x42: |
45 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 48 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
46 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 49 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
47 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 50 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
51 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
48 | break; | 52 | break; |
49 | case 0x43: | 53 | case 0x43: |
50 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 54 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
51 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 55 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
52 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 56 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
57 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
53 | break; | 58 | break; |
54 | case 0x45: | 59 | case 0x45: |
55 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
56 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
57 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
63 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
58 | break; | 64 | break; |
59 | case 0x47: | 65 | case 0x47: |
60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 66 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 67 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 68 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
69 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
63 | break; | 70 | break; |
64 | case 0x49: | 71 | case 0x49: |
65 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 72 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
66 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 73 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
67 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 74 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
75 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
68 | break; | 76 | break; |
69 | case 0x4b: | 77 | case 0x4b: |
70 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 78 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
71 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 79 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
72 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 80 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
81 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
73 | break; | 82 | break; |
74 | case 0x44: | 83 | case 0x44: |
75 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 84 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
76 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 85 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
77 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 86 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
87 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
78 | break; | 88 | break; |
79 | case 0x46: | 89 | case 0x46: |
80 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 90 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
81 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 91 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
82 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 92 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
93 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
83 | break; | 94 | break; |
84 | case 0x4a: | 95 | case 0x4a: |
85 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 96 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
86 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 97 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
87 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 98 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
99 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
88 | break; | 100 | break; |
89 | case 0x4c: | 101 | case 0x4c: |
90 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 102 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
91 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 103 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
92 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 104 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
105 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
93 | break; | 106 | break; |
94 | case 0x4e: | 107 | case 0x4e: |
95 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 108 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
96 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 109 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
97 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 110 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
111 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
98 | break; | 112 | break; |
99 | case 0x63: | 113 | case 0x63: |
100 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 114 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
101 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 115 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
102 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 116 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
117 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
103 | break; | 118 | break; |
104 | case 0x67: | 119 | case 0x67: |
105 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 120 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
106 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 121 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
107 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 122 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
123 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
108 | break; | 124 | break; |
109 | case 0x68: | 125 | case 0x68: |
110 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 126 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
111 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 127 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
112 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 128 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
129 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | ||
113 | break; | 130 | break; |
114 | default: | 131 | default: |
115 | nv_fatal(device, "unknown Curie chipset\n"); | 132 | nv_fatal(device, "unknown Curie chipset\n"); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c index 9f4f6eff443..0674163506c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <subdev/bios.h> | 26 | #include <subdev/bios.h> |
27 | #include <subdev/gpio.h> | 27 | #include <subdev/gpio.h> |
28 | #include <subdev/i2c.h> | 28 | #include <subdev/i2c.h> |
29 | #include <subdev/clock.h> | ||
29 | 30 | ||
30 | int | 31 | int |
31 | nv50_identify(struct nouveau_device *device) | 32 | nv50_identify(struct nouveau_device *device) |
@@ -35,71 +36,85 @@ nv50_identify(struct nouveau_device *device) | |||
35 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 36 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
36 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 37 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
37 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 38 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
39 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
38 | break; | 40 | break; |
39 | case 0x84: | 41 | case 0x84: |
40 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 42 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
41 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 43 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
42 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 44 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
45 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
43 | break; | 46 | break; |
44 | case 0x86: | 47 | case 0x86: |
45 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 48 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
46 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 49 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
47 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 50 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
51 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
48 | break; | 52 | break; |
49 | case 0x92: | 53 | case 0x92: |
50 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 54 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
51 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 55 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
52 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 56 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
57 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
53 | break; | 58 | break; |
54 | case 0x94: | 59 | case 0x94: |
55 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
56 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
57 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
63 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
58 | break; | 64 | break; |
59 | case 0x96: | 65 | case 0x96: |
60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 66 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 67 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 68 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
69 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
63 | break; | 70 | break; |
64 | case 0x98: | 71 | case 0x98: |
65 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 72 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
66 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 73 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
67 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 74 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
75 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
68 | break; | 76 | break; |
69 | case 0xa0: | 77 | case 0xa0: |
70 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 78 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
71 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 79 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
72 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 80 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
81 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
73 | break; | 82 | break; |
74 | case 0xaa: | 83 | case 0xaa: |
75 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 84 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
76 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 85 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
77 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 86 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
87 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
78 | break; | 88 | break; |
79 | case 0xac: | 89 | case 0xac: |
80 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 90 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
81 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 91 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
82 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 92 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
93 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; | ||
83 | break; | 94 | break; |
84 | case 0xa3: | 95 | case 0xa3: |
85 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 96 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
86 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 97 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
87 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 98 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
99 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; | ||
88 | break; | 100 | break; |
89 | case 0xa5: | 101 | case 0xa5: |
90 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 102 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
91 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 103 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
92 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 104 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
105 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; | ||
93 | break; | 106 | break; |
94 | case 0xa8: | 107 | case 0xa8: |
95 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 108 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
96 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 109 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
97 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 110 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
111 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; | ||
98 | break; | 112 | break; |
99 | case 0xaf: | 113 | case 0xaf: |
100 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 114 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
101 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 115 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
102 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 116 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
117 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; | ||
103 | break; | 118 | break; |
104 | default: | 119 | default: |
105 | nv_fatal(device, "unknown Tesla chipset\n"); | 120 | nv_fatal(device, "unknown Tesla chipset\n"); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c index f941024723c..56aae6bfbf2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <subdev/bios.h> | 26 | #include <subdev/bios.h> |
27 | #include <subdev/gpio.h> | 27 | #include <subdev/gpio.h> |
28 | #include <subdev/i2c.h> | 28 | #include <subdev/i2c.h> |
29 | #include <subdev/clock.h> | ||
29 | 30 | ||
30 | int | 31 | int |
31 | nvc0_identify(struct nouveau_device *device) | 32 | nvc0_identify(struct nouveau_device *device) |
@@ -35,41 +36,49 @@ nvc0_identify(struct nouveau_device *device) | |||
35 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 36 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
36 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 37 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
37 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 38 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
39 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
38 | break; | 40 | break; |
39 | case 0xc4: | 41 | case 0xc4: |
40 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 42 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
41 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 43 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
42 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 44 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
45 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
43 | break; | 46 | break; |
44 | case 0xc3: | 47 | case 0xc3: |
45 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 48 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
46 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 49 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
47 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 50 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
51 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
48 | break; | 52 | break; |
49 | case 0xce: | 53 | case 0xce: |
50 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 54 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
51 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 55 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
52 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 56 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
57 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
53 | break; | 58 | break; |
54 | case 0xcf: | 59 | case 0xcf: |
55 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
56 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
57 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
63 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
58 | break; | 64 | break; |
59 | case 0xc1: | 65 | case 0xc1: |
60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 66 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 67 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 68 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
69 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
63 | break; | 70 | break; |
64 | case 0xc8: | 71 | case 0xc8: |
65 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 72 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
66 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; | 73 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
67 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 74 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
75 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
68 | break; | 76 | break; |
69 | case 0xd9: | 77 | case 0xd9: |
70 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 78 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
71 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; | 79 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; |
72 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 80 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
81 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
73 | break; | 82 | break; |
74 | default: | 83 | default: |
75 | nv_fatal(device, "unknown Fermi chipset\n"); | 84 | nv_fatal(device, "unknown Fermi chipset\n"); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c index 21763cf39ec..8ad51cc0543 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <subdev/bios.h> | 26 | #include <subdev/bios.h> |
27 | #include <subdev/gpio.h> | 27 | #include <subdev/gpio.h> |
28 | #include <subdev/i2c.h> | 28 | #include <subdev/i2c.h> |
29 | #include <subdev/clock.h> | ||
29 | 30 | ||
30 | int | 31 | int |
31 | nve0_identify(struct nouveau_device *device) | 32 | nve0_identify(struct nouveau_device *device) |
@@ -35,11 +36,13 @@ nve0_identify(struct nouveau_device *device) | |||
35 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 36 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
36 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; | 37 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; |
37 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 38 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
39 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
38 | break; | 40 | break; |
39 | case 0xe7: | 41 | case 0xe7: |
40 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 42 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
41 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; | 43 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; |
42 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; | 44 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
45 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | ||
43 | break; | 46 | break; |
44 | default: | 47 | default: |
45 | nv_fatal(device, "unknown Kepler chipset\n"); | 48 | nv_fatal(device, "unknown Kepler chipset\n"); |