diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-13 21:03:52 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-02 23:12:52 -0400 |
commit | 8a9b889e668a5bc2f4031015fe4893005c43403d (patch) | |
tree | 3372d2cf612c4dc77496df1f6acd6f85248a10f2 /drivers | |
parent | 092599da308bf56b96c849ecdd315b8a1a13ca52 (diff) |
drm/nouveau: remove last use of nouveau_gpuobj_new_fake()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_gpuobj.c | 152 |
2 files changed, 72 insertions, 84 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 0c03b472a9a..fad668793fa 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -247,6 +247,7 @@ struct nouveau_channel { | |||
247 | struct drm_mm notifier_heap; | 247 | struct drm_mm notifier_heap; |
248 | 248 | ||
249 | /* PFIFO context */ | 249 | /* PFIFO context */ |
250 | struct nouveau_gpuobj *engptr; | ||
250 | struct nouveau_gpuobj *ramfc; | 251 | struct nouveau_gpuobj *ramfc; |
251 | 252 | ||
252 | /* Execution engine contexts */ | 253 | /* Execution engine contexts */ |
@@ -862,9 +863,6 @@ extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, | |||
862 | struct nouveau_gpuobj **); | 863 | struct nouveau_gpuobj **); |
863 | extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, | 864 | extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, |
864 | struct nouveau_gpuobj **); | 865 | struct nouveau_gpuobj **); |
865 | extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, | ||
866 | u32 size, u32 flags, | ||
867 | struct nouveau_gpuobj **); | ||
868 | extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, | 866 | extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, |
869 | uint64_t offset, uint64_t size, int access, | 867 | uint64_t offset, uint64_t size, int access, |
870 | int target, struct nouveau_gpuobj **); | 868 | int target, struct nouveau_gpuobj **); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_gpuobj.c b/drivers/gpu/drm/nouveau/nouveau_gpuobj.c index 79f1d1ef379..0d370e8c468 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gpuobj.c +++ b/drivers/gpu/drm/nouveau/nouveau_gpuobj.c | |||
@@ -295,43 +295,6 @@ nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr) | |||
295 | *ptr = ref; | 295 | *ptr = ref; |
296 | } | 296 | } |
297 | 297 | ||
298 | int | ||
299 | nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst, | ||
300 | u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj) | ||
301 | { | ||
302 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
303 | struct nouveau_gpuobj *gpuobj = NULL; | ||
304 | int i; | ||
305 | |||
306 | NV_DEBUG(dev, | ||
307 | "pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n", | ||
308 | pinst, vinst, size, flags); | ||
309 | |||
310 | gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); | ||
311 | if (!gpuobj) | ||
312 | return -ENOMEM; | ||
313 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); | ||
314 | gpuobj->dev = dev; | ||
315 | gpuobj->flags = flags; | ||
316 | kref_init(&gpuobj->refcount); | ||
317 | gpuobj->size = size; | ||
318 | gpuobj->pinst = pinst; | ||
319 | gpuobj->cinst = NVOBJ_CINST_GLOBAL; | ||
320 | gpuobj->vinst = vinst; | ||
321 | |||
322 | if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { | ||
323 | for (i = 0; i < gpuobj->size; i += 4) | ||
324 | nv_wo32(gpuobj, i, 0); | ||
325 | dev_priv->engine.instmem.flush(dev); | ||
326 | } | ||
327 | |||
328 | spin_lock(&dev_priv->ramin_lock); | ||
329 | list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); | ||
330 | spin_unlock(&dev_priv->ramin_lock); | ||
331 | *pgpuobj = gpuobj; | ||
332 | return 0; | ||
333 | } | ||
334 | |||
335 | void | 298 | void |
336 | nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class, | 299 | nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class, |
337 | u64 base, u64 size, int target, int access, | 300 | u64 base, u64 size, int target, int access, |
@@ -512,43 +475,75 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class) | |||
512 | } | 475 | } |
513 | 476 | ||
514 | static int | 477 | static int |
515 | nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) | 478 | nv04_gpuobj_channel_init_pramin(struct nouveau_channel *chan) |
516 | { | 479 | { |
517 | struct drm_device *dev = chan->dev; | 480 | struct drm_device *dev = chan->dev; |
518 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
519 | uint32_t size; | ||
520 | uint32_t base; | ||
521 | int ret; | 481 | int ret; |
522 | 482 | ||
523 | NV_DEBUG(dev, "ch%d\n", chan->id); | 483 | ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000, |
524 | 484 | NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin); | |
525 | /* Base amount for object storage (4KiB enough?) */ | 485 | if (ret) |
526 | size = 0x2000; | 486 | return ret; |
527 | base = 0; | ||
528 | |||
529 | if (dev_priv->card_type == NV_50) { | ||
530 | /* Various fixed table thingos */ | ||
531 | size += 0x1400; /* mostly unknown stuff */ | ||
532 | size += 0x4000; /* vm pd */ | ||
533 | base = 0x6000; | ||
534 | /* RAMHT, not sure about setting size yet, 32KiB to be safe */ | ||
535 | size += 0x8000; | ||
536 | /* RAMFC */ | ||
537 | size += 0x1000; | ||
538 | } | ||
539 | 487 | ||
540 | ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin); | 488 | ret = drm_mm_init(&chan->ramin_heap, 0, chan->ramin->size); |
541 | if (ret) { | 489 | if (ret) |
542 | NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret); | ||
543 | return ret; | 490 | return ret; |
544 | } | ||
545 | 491 | ||
546 | ret = drm_mm_init(&chan->ramin_heap, base, size - base); | 492 | return 0; |
547 | if (ret) { | 493 | } |
548 | NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret); | 494 | |
549 | nouveau_gpuobj_ref(NULL, &chan->ramin); | 495 | static int |
496 | nv50_gpuobj_channel_init_pramin(struct nouveau_channel *chan) | ||
497 | { | ||
498 | struct drm_device *dev = chan->dev; | ||
499 | int ret; | ||
500 | |||
501 | ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000, | ||
502 | NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin); | ||
503 | if (ret) | ||
504 | return ret; | ||
505 | |||
506 | ret = drm_mm_init(&chan->ramin_heap, 0, chan->ramin->size); | ||
507 | if (ret) | ||
508 | return ret; | ||
509 | |||
510 | ret = nouveau_gpuobj_new(dev, chan, 0x0200, 0, 0, &chan->ramfc); | ||
511 | if (ret) | ||
512 | return ret; | ||
513 | |||
514 | ret = nouveau_gpuobj_new(dev, chan, 0x1000, 0, 0, &chan->engptr); | ||
515 | if (ret) | ||
516 | return ret; | ||
517 | |||
518 | ret = nouveau_gpuobj_new(dev, chan, 0x4000, 0, 0, &chan->vm_pd); | ||
519 | if (ret) | ||
520 | return ret; | ||
521 | |||
522 | return 0; | ||
523 | } | ||
524 | |||
525 | static int | ||
526 | nv84_gpuobj_channel_init_pramin(struct nouveau_channel *chan) | ||
527 | { | ||
528 | struct drm_device *dev = chan->dev; | ||
529 | int ret; | ||
530 | |||
531 | ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000, | ||
532 | NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin); | ||
533 | if (ret) | ||
534 | return ret; | ||
535 | |||
536 | ret = drm_mm_init(&chan->ramin_heap, 0, chan->ramin->size); | ||
537 | if (ret) | ||
538 | return ret; | ||
539 | |||
540 | ret = nouveau_gpuobj_new(dev, chan, 0x0200, 0, 0, &chan->engptr); | ||
541 | if (ret) | ||
542 | return ret; | ||
543 | |||
544 | ret = nouveau_gpuobj_new(dev, chan, 0x4000, 0, 0, &chan->vm_pd); | ||
545 | if (ret) | ||
550 | return ret; | 546 | return ret; |
551 | } | ||
552 | 547 | ||
553 | return 0; | 548 | return 0; |
554 | } | 549 | } |
@@ -603,7 +598,13 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, | |||
603 | return nvc0_gpuobj_channel_init(chan, vm); | 598 | return nvc0_gpuobj_channel_init(chan, vm); |
604 | 599 | ||
605 | /* Allocate a chunk of memory for per-channel object storage */ | 600 | /* Allocate a chunk of memory for per-channel object storage */ |
606 | ret = nouveau_gpuobj_channel_init_pramin(chan); | 601 | if (dev_priv->chipset >= 0x84) |
602 | ret = nv84_gpuobj_channel_init_pramin(chan); | ||
603 | else | ||
604 | if (dev_priv->chipset == 0x50) | ||
605 | ret = nv50_gpuobj_channel_init_pramin(chan); | ||
606 | else | ||
607 | ret = nv04_gpuobj_channel_init_pramin(chan); | ||
607 | if (ret) { | 608 | if (ret) { |
608 | NV_ERROR(dev, "init pramin\n"); | 609 | NV_ERROR(dev, "init pramin\n"); |
609 | return ret; | 610 | return ret; |
@@ -613,21 +614,8 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, | |||
613 | * - Allocate per-channel page-directory | 614 | * - Allocate per-channel page-directory |
614 | * - Link with shared channel VM | 615 | * - Link with shared channel VM |
615 | */ | 616 | */ |
616 | if (vm) { | 617 | if (vm) |
617 | u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200; | ||
618 | u64 vm_vinst = chan->ramin->vinst + pgd_offs; | ||
619 | u32 vm_pinst = chan->ramin->pinst; | ||
620 | |||
621 | if (vm_pinst != ~0) | ||
622 | vm_pinst += pgd_offs; | ||
623 | |||
624 | ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000, | ||
625 | 0, &chan->vm_pd); | ||
626 | if (ret) | ||
627 | return ret; | ||
628 | |||
629 | nouveau_vm_ref(vm, &chan->vm, chan->vm_pd); | 618 | nouveau_vm_ref(vm, &chan->vm, chan->vm_pd); |
630 | } | ||
631 | 619 | ||
632 | /* RAMHT */ | 620 | /* RAMHT */ |
633 | if (dev_priv->card_type < NV_50) { | 621 | if (dev_priv->card_type < NV_50) { |
@@ -707,6 +695,8 @@ nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) | |||
707 | 695 | ||
708 | nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd); | 696 | nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd); |
709 | nouveau_gpuobj_ref(NULL, &chan->vm_pd); | 697 | nouveau_gpuobj_ref(NULL, &chan->vm_pd); |
698 | nouveau_gpuobj_ref(NULL, &chan->ramfc); | ||
699 | nouveau_gpuobj_ref(NULL, &chan->engptr); | ||
710 | 700 | ||
711 | if (drm_mm_initialized(&chan->ramin_heap)) | 701 | if (drm_mm_initialized(&chan->ramin_heap)) |
712 | drm_mm_takedown(&chan->ramin_heap); | 702 | drm_mm_takedown(&chan->ramin_heap); |