diff options
author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2009-06-22 21:48:29 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-05-10 10:44:46 -0400 |
commit | 7b029d03c36e5b06e067884aaefcee2c1c62efc7 (patch) | |
tree | d5537abbfd8cc92a4c1d9d30c6199dfcd8e80142 /drivers | |
parent | f122a89222510e8f57e8e0b9b5cdd3ec8863fe4c (diff) |
i7core_edac: A few fixes at error injection code
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/edac/i7core_edac.c | 70 |
1 files changed, 55 insertions, 15 deletions
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c index 09a0998e1c3..0c17db67306 100644 --- a/drivers/edac/i7core_edac.c +++ b/drivers/edac/i7core_edac.c | |||
@@ -30,6 +30,8 @@ | |||
30 | 30 | ||
31 | #include "edac_core.h" | 31 | #include "edac_core.h" |
32 | 32 | ||
33 | /* To use the new pci_[read/write]_config_qword instead of two dword */ | ||
34 | #define USE_QWORD 1 | ||
33 | 35 | ||
34 | /* | 36 | /* |
35 | * Alter this version for the module when modifications are made | 37 | * Alter this version for the module when modifications are made |
@@ -639,44 +641,71 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci, | |||
639 | 641 | ||
640 | /* Sets pvt->inject.dimm mask */ | 642 | /* Sets pvt->inject.dimm mask */ |
641 | if (pvt->inject.dimm < 0) | 643 | if (pvt->inject.dimm < 0) |
642 | mask |= 1l << 41; | 644 | mask |= 1L << 41; |
643 | else { | 645 | else { |
644 | if (pvt->channel[pvt->inject.channel].dimms > 2) | 646 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
645 | mask |= (pvt->inject.dimm & 0x3l) << 35; | 647 | mask |= (pvt->inject.dimm & 0x3L) << 35; |
646 | else | 648 | else |
647 | mask |= (pvt->inject.dimm & 0x1l) << 36; | 649 | mask |= (pvt->inject.dimm & 0x1L) << 36; |
648 | } | 650 | } |
649 | 651 | ||
650 | /* Sets pvt->inject.rank mask */ | 652 | /* Sets pvt->inject.rank mask */ |
651 | if (pvt->inject.rank < 0) | 653 | if (pvt->inject.rank < 0) |
652 | mask |= 1l << 40; | 654 | mask |= 1L << 40; |
653 | else { | 655 | else { |
654 | if (pvt->channel[pvt->inject.channel].dimms > 2) | 656 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
655 | mask |= (pvt->inject.rank & 0x1l) << 34; | 657 | mask |= (pvt->inject.rank & 0x1L) << 34; |
656 | else | 658 | else |
657 | mask |= (pvt->inject.rank & 0x3l) << 34; | 659 | mask |= (pvt->inject.rank & 0x3L) << 34; |
658 | } | 660 | } |
659 | 661 | ||
660 | /* Sets pvt->inject.bank mask */ | 662 | /* Sets pvt->inject.bank mask */ |
661 | if (pvt->inject.bank < 0) | 663 | if (pvt->inject.bank < 0) |
662 | mask |= 1l << 39; | 664 | mask |= 1L << 39; |
663 | else | 665 | else |
664 | mask |= (pvt->inject.bank & 0x15l) << 30; | 666 | mask |= (pvt->inject.bank & 0x15L) << 30; |
665 | 667 | ||
666 | /* Sets pvt->inject.page mask */ | 668 | /* Sets pvt->inject.page mask */ |
667 | if (pvt->inject.page < 0) | 669 | if (pvt->inject.page < 0) |
668 | mask |= 1l << 38; | 670 | mask |= 1L << 38; |
669 | else | 671 | else |
670 | mask |= (pvt->inject.page & 0xffffl) << 14; | 672 | mask |= (pvt->inject.page & 0xffffL) << 14; |
671 | 673 | ||
672 | /* Sets pvt->inject.column mask */ | 674 | /* Sets pvt->inject.column mask */ |
673 | if (pvt->inject.col < 0) | 675 | if (pvt->inject.col < 0) |
674 | mask |= 1l << 37; | 676 | mask |= 1L << 37; |
675 | else | 677 | else |
676 | mask |= (pvt->inject.col & 0x3fffl); | 678 | mask |= (pvt->inject.col & 0x3fffL); |
677 | 679 | ||
680 | #if USE_QWORD | ||
678 | pci_write_config_qword(pvt->pci_ch[pvt->inject.channel][0], | 681 | pci_write_config_qword(pvt->pci_ch[pvt->inject.channel][0], |
679 | MC_CHANNEL_ADDR_MATCH, mask); | 682 | MC_CHANNEL_ADDR_MATCH, mask); |
683 | #else | ||
684 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], | ||
685 | MC_CHANNEL_ADDR_MATCH, mask); | ||
686 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], | ||
687 | MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L); | ||
688 | #endif | ||
689 | |||
690 | #if 1 | ||
691 | #if USE_QWORD | ||
692 | u64 rdmask; | ||
693 | pci_read_config_qword(pvt->pci_ch[pvt->inject.channel][0], | ||
694 | MC_CHANNEL_ADDR_MATCH, &rdmask); | ||
695 | debugf0("Inject addr match write 0x%016llx, read: 0x%016llx\n", | ||
696 | mask, rdmask); | ||
697 | #else | ||
698 | u32 rdmask1, rdmask2; | ||
699 | |||
700 | pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], | ||
701 | MC_CHANNEL_ADDR_MATCH, &rdmask1); | ||
702 | pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], | ||
703 | MC_CHANNEL_ADDR_MATCH + 4, &rdmask2); | ||
704 | |||
705 | debugf0("Inject addr match write 0x%016llx, read: 0x%08x%08x\n", | ||
706 | mask, rdmask1, rdmask2); | ||
707 | #endif | ||
708 | #endif | ||
680 | 709 | ||
681 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], | 710 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
682 | MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); | 711 | MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); |
@@ -688,17 +717,18 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci, | |||
688 | * bit 4: INJECT_ADDR_PARITY | 717 | * bit 4: INJECT_ADDR_PARITY |
689 | */ | 718 | */ |
690 | 719 | ||
691 | injectmask = (pvt->inject.type & 1) && | 720 | injectmask = (pvt->inject.type & 1) | |
692 | (pvt->inject.section & 0x3) << 1 && | 721 | (pvt->inject.section & 0x3) << 1 | |
693 | (pvt->inject.type & 0x6) << (3 - 1); | 722 | (pvt->inject.type & 0x6) << (3 - 1); |
694 | 723 | ||
695 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], | 724 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
696 | MC_CHANNEL_ERROR_MASK, injectmask); | 725 | MC_CHANNEL_ERROR_MASK, injectmask); |
697 | 726 | ||
698 | |||
699 | debugf0("Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n", | 727 | debugf0("Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n", |
700 | mask, pvt->inject.eccmask, injectmask); | 728 | mask, pvt->inject.eccmask, injectmask); |
701 | 729 | ||
730 | |||
731 | |||
702 | return count; | 732 | return count; |
703 | } | 733 | } |
704 | 734 | ||
@@ -706,6 +736,16 @@ static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci, | |||
706 | char *data) | 736 | char *data) |
707 | { | 737 | { |
708 | struct i7core_pvt *pvt = mci->pvt_info; | 738 | struct i7core_pvt *pvt = mci->pvt_info; |
739 | u32 injectmask; | ||
740 | |||
741 | pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], | ||
742 | MC_CHANNEL_ERROR_MASK, &injectmask); | ||
743 | |||
744 | debugf0("Inject error read: 0x%018x\n", injectmask); | ||
745 | |||
746 | if (injectmask & 0x0c) | ||
747 | pvt->inject.enable = 1; | ||
748 | |||
709 | return sprintf(data, "%d\n", pvt->inject.enable); | 749 | return sprintf(data, "%d\n", pvt->inject.enable); |
710 | } | 750 | } |
711 | 751 | ||