MIPS: AR7: Implement clock API

This patch makes the ar7 clock code implement the Linux clk API. Drivers
using the various clocks available in the SoC are updated accordingly.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
To: linux-mips@linux-mips.org
Cc: Wim Van Sebroeck <wim@iguana.be>
Cc: netdev@vger.kernel.org
Cc: David Miller <davem@davemloft.net>
Patchwork: http://patchwork.linux-mips.org/patch/881/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 24 insertions, 4 deletions

diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c
index 8d0be26f94e..bf2072e5420 100644
--- a/drivers/net/cpmac.c
+++ b/drivers/net/cpmac.c
@@ -36,6 +36,7 @@
 #include <linux/phy_fixed.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/clk.h>
 #include <asm/gpio.h>
 #include <asm/atomic.h>
 
@@ -294,9 +295,16 @@ static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
 
 static int cpmac_mdio_reset(struct mii_bus *bus)
 {
+        struct clk *cpmac_clk;
+
+        cpmac_clk = clk_get(&bus->dev, "cpmac");
+        if (IS_ERR(cpmac_clk)) {
+                printk(KERN_ERR "unable to get cpmac clock\n");
+                return -1;
+        }
         ar7_device_reset(AR7_RESET_BIT_MDIO);
         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
-                    MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
+                    MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
         return 0;
 }
 
diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c
index 2e94b71b20d..2bb95cd308c 100644
--- a/drivers/watchdog/ar7_wdt.c
+++ b/drivers/watchdog/ar7_wdt.c
@@ -34,6 +34,7 @@
 #include <linux/ioport.h>
 #include <linux/io.h>
 #include <linux/uaccess.h>
+#include <linux/clk.h>
 
 #include <asm/addrspace.h>
 #include <asm/mach-ar7/ar7.h>
@@ -80,6 +81,8 @@ static struct resource *ar7_regs_wdt;
 /* Pointer to the remapped WDT IO space */
 static struct ar7_wdt *ar7_wdt;
 
+static struct clk *vbus_clk;
+
 static void ar7_wdt_kick(u32 value)
 {
         WRITE_REG(ar7_wdt->kick_lock, 0x5555);
@@ -138,17 +141,19 @@ static void ar7_wdt_disable(u32 value)
 static void ar7_wdt_update_margin(int new_margin)
 {
         u32 change;
+        u32 vbus_rate;
 
-        change = new_margin * (ar7_vbus_freq() / prescale_value);
+        vbus_rate = clk_get_rate(vbus_clk);
+        change = new_margin * (vbus_rate / prescale_value);
         if (change < 1)
                 change = 1;
         if (change > 0xffff)
                 change = 0xffff;
         ar7_wdt_change(change);
-        margin = change * prescale_value / ar7_vbus_freq();
+        margin = change * prescale_value / vbus_rate;
         printk(KERN_INFO DRVNAME
                ": timer margin %d seconds (prescale %d, change %d, freq %d)\n",
-               margin, prescale_value, change, ar7_vbus_freq());
+               margin, prescale_value, change, vbus_rate);
 }
 
 static void ar7_wdt_enable_wdt(void)
@@ -298,6 +303,13 @@ static int __devinit ar7_wdt_probe(struct platform_device *pdev)
                 goto out_mem_region;
         }
 
+        vbus_clk = clk_get(NULL, "vbus");
+        if (IS_ERR(vbus_clk)) {
+                printk(KERN_ERR DRVNAME ": could not get vbus clock\n");
+                rc = PTR_ERR(vbus_clk);
+                goto out_mem_region;
+        }
+
         ar7_wdt_disable_wdt();
         ar7_wdt_prescale(prescale_value);
         ar7_wdt_update_margin(margin);