diff options
author | Ulf Hansson <ulf.hansson@linaro.org> | 2012-10-22 09:58:01 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2012-11-09 20:05:33 -0500 |
commit | 4a0ae7befc92765c05b4bdd79e931a2058ea9fb7 (patch) | |
tree | cda4c43233250628525b336d797677a5bdbbc033 /drivers | |
parent | 86497f54556d70df60ef3030bddcb544f1fb8746 (diff) |
clk: ux500: Register slimbus clock lookups for u8500
At the same time the prcc bit for the kclk is corrected to
bit 8 instead of 3.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/ux500/u8500_clk.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 668839ff67f..4ec6f60e372 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c | |||
@@ -257,6 +257,7 @@ void u8500_clk_init(void) | |||
257 | 257 | ||
258 | clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE, | 258 | clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE, |
259 | BIT(8), 0); | 259 | BIT(8), 0); |
260 | clk_register_clkdev(clk, "apb_pclk", "slimbus0"); | ||
260 | 261 | ||
261 | clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE, | 262 | clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE, |
262 | BIT(9), 0); | 263 | BIT(9), 0); |
@@ -444,8 +445,8 @@ void u8500_clk_init(void) | |||
444 | clk_register_clkdev(clk, NULL, "nmk-i2c.2"); | 445 | clk_register_clkdev(clk, NULL, "nmk-i2c.2"); |
445 | 446 | ||
446 | clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", | 447 | clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", |
447 | U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE); | 448 | U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE); |
448 | /* FIXME: Redefinition of BIT(3). */ | 449 | clk_register_clkdev(clk, NULL, "slimbus0"); |
449 | 450 | ||
450 | clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", | 451 | clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", |
451 | U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE); | 452 | U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE); |