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authorMike McCormack <mikem@ring3k.org>2011-02-06 08:54:29 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-02-09 14:50:18 -0500
commit4803ef77da6ac74b0288be1fd15bdc7fe240acfa (patch)
treefd2f1a7986a7fd59853c79bed4273aa91c5ad9e2 /drivers
parentaebbafddf78e148378eee71f9063f510e9a1cf05 (diff)
staging: rtl8192e: Remove RTL8192P and RTL8192U ifdefs
Signed-off-by: Mike McCormack <mikem@ring3k.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/rtl8192e/r8190_rtl8256.c200
-rw-r--r--drivers/staging/rtl8192e/r8190_rtl8256.h4
-rw-r--r--drivers/staging/rtl8192e/r8192E_core.c316
-rw-r--r--drivers/staging/rtl8192e/r8192E_dm.c383
-rw-r--r--drivers/staging/rtl8192e/r8192E_hw.h18
-rw-r--r--drivers/staging/rtl8192e/r8192_pm.c9
-rw-r--r--drivers/staging/rtl8192e/r819xE_cmdpkt.c14
-rw-r--r--drivers/staging/rtl8192e/r819xE_phy.c958
-rw-r--r--drivers/staging/rtl8192e/r819xE_phy.h20
9 files changed, 41 insertions, 1881 deletions
diff --git a/drivers/staging/rtl8192e/r8190_rtl8256.c b/drivers/staging/rtl8192e/r8190_rtl8256.c
index d911eddd057..4c1a5c849b8 100644
--- a/drivers/staging/rtl8192e/r8190_rtl8256.c
+++ b/drivers/staging/rtl8192e/r8190_rtl8256.c
@@ -59,13 +59,6 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)
59 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff); 59 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff);
60 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1); 60 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1);
61 61
62 //cosa add for sd3's request 01/23/2008
63 #if 0
64 if(priv->chan == 3 || priv->chan == 9) //I need to set priv->chan whenever current channel changes
65 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
66 else
67 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
68 #endif
69 } 62 }
70 else 63 else
71 { 64 {
@@ -241,41 +234,6 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
241{ 234{
242 u32 TxAGC=0; 235 u32 TxAGC=0;
243 struct r8192_priv *priv = ieee80211_priv(dev); 236 struct r8192_priv *priv = ieee80211_priv(dev);
244#ifdef RTL8190P
245 u8 byte0, byte1;
246
247 TxAGC |= ((powerlevel<<8)|powerlevel);
248 TxAGC += priv->CCKTxPowerLevelOriginalOffset;
249
250 if(priv->bDynamicTxLowPower == true //cosa 04282008 for cck long range
251 /*pMgntInfo->bScanInProgress == TRUE*/ ) //cosa 05/22/2008 for scan
252 {
253 if(priv->CustomerID == RT_CID_819x_Netcore)
254 TxAGC = 0x2222;
255 else
256 TxAGC += ((priv->CckPwEnl<<8)|priv->CckPwEnl);
257 }
258
259 byte0 = (u8)(TxAGC & 0xff);
260 byte1 = (u8)((TxAGC & 0xff00)>>8);
261 if(byte0 > 0x24)
262 byte0 = 0x24;
263 if(byte1 > 0x24)
264 byte1 = 0x24;
265 if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset
266 { // check antenna C over the max index 0x24
267 if(priv->RF_C_TxPwDiff > 0)
268 {
269 if( (byte0 + (u8)priv->RF_C_TxPwDiff) > 0x24)
270 byte0 = 0x24 - priv->RF_C_TxPwDiff;
271 if( (byte1 + (u8)priv->RF_C_TxPwDiff) > 0x24)
272 byte1 = 0x24 - priv->RF_C_TxPwDiff;
273 }
274 }
275 TxAGC = (byte1<<8) |byte0;
276 write_nic_dword(priv, CCK_TXAGC, TxAGC);
277#else
278 #ifdef RTL8192E
279 237
280 TxAGC = powerlevel; 238 TxAGC = powerlevel;
281 if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range 239 if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
@@ -288,86 +246,13 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
288 if(TxAGC > 0x24) 246 if(TxAGC > 0x24)
289 TxAGC = 0x24; 247 TxAGC = 0x24;
290 rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); 248 rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
291 #endif
292#endif
293} 249}
294 250
295 251
296void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) 252void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
297{ 253{
298 struct r8192_priv *priv = ieee80211_priv(dev); 254 struct r8192_priv *priv = ieee80211_priv(dev);
299 //Joseph TxPower for 8192 testing
300#ifdef RTL8190P
301 u32 TxAGC1=0, TxAGC2=0, TxAGC2_tmp = 0;
302 u8 i, byteVal1[4], byteVal2[4], byteVal3[4];
303
304 if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06
305 {
306 TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel);
307 //for tx power track
308 TxAGC2_tmp = TxAGC1;
309
310 TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0];
311 TxAGC2 =0x03030303;
312
313 //for tx power track
314 TxAGC2_tmp += priv->MCSTxPowerLevelOriginalOffset[1];
315 }
316 else
317 {
318 TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel);
319 TxAGC2 = TxAGC1;
320
321 TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0];
322 TxAGC2 += priv->MCSTxPowerLevelOriginalOffset[1];
323
324 TxAGC2_tmp = TxAGC2;
325
326 }
327 for(i=0; i<4; i++)
328 {
329 byteVal1[i] = (u8)( (TxAGC1 & (0xff<<(i*8))) >>(i*8) );
330 if(byteVal1[i] > 0x24)
331 byteVal1[i] = 0x24;
332 byteVal2[i] = (u8)( (TxAGC2 & (0xff<<(i*8))) >>(i*8) );
333 if(byteVal2[i] > 0x24)
334 byteVal2[i] = 0x24;
335
336 //for tx power track
337 byteVal3[i] = (u8)( (TxAGC2_tmp & (0xff<<(i*8))) >>(i*8) );
338 if(byteVal3[i] > 0x24)
339 byteVal3[i] = 0x24;
340 }
341
342 if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset
343 { // check antenna C over the max index 0x24
344 if(priv->RF_C_TxPwDiff > 0)
345 {
346 for(i=0; i<4; i++)
347 {
348 if( (byteVal1[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
349 byteVal1[i] = 0x24 - priv->RF_C_TxPwDiff;
350 if( (byteVal2[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
351 byteVal2[i] = 0x24 - priv->RF_C_TxPwDiff;
352 if( (byteVal3[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
353 byteVal3[i] = 0x24 - priv->RF_C_TxPwDiff;
354 }
355 }
356 }
357
358 TxAGC1 = (byteVal1[3]<<24) | (byteVal1[2]<<16) |(byteVal1[1]<<8) |byteVal1[0];
359 TxAGC2 = (byteVal2[3]<<24) | (byteVal2[2]<<16) |(byteVal2[1]<<8) |byteVal2[0];
360 255
361 //for tx power track
362 TxAGC2_tmp = (byteVal3[3]<<24) | (byteVal3[2]<<16) |(byteVal3[1]<<8) |byteVal3[0];
363 priv->Pwr_Track = TxAGC2_tmp;
364 //DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp);
365
366 //DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2);
367 write_nic_dword(priv, MCS_TXAGC, TxAGC1);
368 write_nic_dword(priv, MCS_TXAGC+4, TxAGC2);
369#else
370#ifdef RTL8192E
371 u32 writeVal, powerBase0, powerBase1, writeVal_tmp; 256 u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
372 u8 index = 0; 257 u8 index = 0;
373 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; 258 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
@@ -410,9 +295,6 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
410 } 295 }
411 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); 296 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
412 } 297 }
413
414#endif
415#endif
416} 298}
417 299
418#define MAX_DOZE_WAITING_TIMES_9x 64 300#define MAX_DOZE_WAITING_TIMES_9x 64
@@ -443,56 +325,7 @@ SetRFPowerState8190(
443 //RXTX enable control: On 325 //RXTX enable control: On
444 //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 326 //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
445 // PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2); 327 // PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2);
446#ifdef RTL8190P
447 if(priv->rf_type == RF_2T4R)
448 {
449 //enable RF-Chip A/B
450 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
451 //enable RF-Chip C/D
452 rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4]
453 //analog to digital on
454 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
455 //digital to analog on
456 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf); // 0x880[8:5]
457 //rx antenna on
458 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0xf);// 0xc04[3:0]
459 //rx antenna on
460 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0xf);// 0xd04[3:0]
461 //analog to digital part2 on
462 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf); // 0x880[12:9]
463 }
464 else if(priv->rf_type == RF_1T2R) //RF-C, RF-D
465 {
466 //enable RF-Chip C/D
467 rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4]
468 //analog to digital on
469 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
470 //digital to analog on
471 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3); // 0x880[8:7]
472 //rx antenna on
473 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xc, 0x3);// 0xc04[3:2]
474 //rx antenna on
475 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xc, 0x3);// 0xd04[3:2]
476 //analog to digital part2 on
477 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); // 0x880[12:11]
478 }
479 else if(priv->rf_type == RF_1T1R) //RF-C
480 {
481 //enable RF-Chip C/D
482 rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4]
483 //analog to digital on
484 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x400, 0x1);// 0x88c[10]
485 //digital to analog on
486 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1); // 0x880[7]
487 //rx antenna on
488 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x4, 0x1);// 0xc04[2]
489 //rx antenna on
490 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x4, 0x1);// 0xd04[2]
491 //analog to digital part2 on
492 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1); // 0x880[11]
493 }
494 328
495#elif defined RTL8192E
496 // turn on RF 329 // turn on RF
497 if((priv->ieee80211->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) 330 if((priv->ieee80211->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
498 { // The current RF state is OFF and the RF OFF level is halting the NIC, re-initialize the NIC. 331 { // The current RF state is OFF and the RF OFF level is halting the NIC, re-initialize the NIC.
@@ -561,7 +394,6 @@ SetRFPowerState8190(
561 394
562 } 395 }
563 396
564 #endif
565 break; 397 break;
566 398
567 // 399 //
@@ -603,17 +435,7 @@ SetRFPowerState8190(
603 } 435 }
604 } 436 }
605 437
606 //if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P) 438 PHY_SetRtl8192eRfOff(dev);
607#ifdef RTL8190P
608 {
609 PHY_SetRtl8190pRfOff(dev);
610 }
611 //else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E)
612#elif defined RTL8192E
613 {
614 PHY_SetRtl8192eRfOff(dev);
615 }
616#endif
617 } 439 }
618 break; 440 break;
619 441
@@ -649,13 +471,6 @@ SetRFPowerState8190(
649 } 471 }
650 } 472 }
651 473
652 //if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
653#if defined RTL8190P
654 {
655 PHY_SetRtl8190pRfOff(dev);
656 }
657 //else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E)
658#elif defined RTL8192E
659 { 474 {
660 //if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC) && priv->ieee80211->RfOffReason > RF_CHANGE_BY_PS) 475 //if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC) && priv->ieee80211->RfOffReason > RF_CHANGE_BY_PS)
661 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) 476 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
@@ -687,14 +502,7 @@ SetRFPowerState8190(
687 PHY_SetRtl8192eRfOff(dev); 502 PHY_SetRtl8192eRfOff(dev);
688 } 503 }
689 } 504 }
690#else 505 break;
691 else
692 {
693 RT_TRACE(COMP_DBG,DBG_TRACE,("It is not 8190Pci and 8192PciE \n"));
694 }
695 #endif
696
697 break;
698 506
699 default: 507 default:
700 bResult = false; 508 bResult = false;
@@ -742,11 +550,7 @@ SetRFPowerState(
742 bool bResult = false; 550 bool bResult = false;
743 551
744 RT_TRACE(COMP_RF,"---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState); 552 RT_TRACE(COMP_RF,"---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
745#ifdef RTL8192E
746 if(eRFPowerState == priv->ieee80211->eRFPowerState && priv->bHwRfOffAction == 0) 553 if(eRFPowerState == priv->ieee80211->eRFPowerState && priv->bHwRfOffAction == 0)
747#else
748 if(eRFPowerState == priv->ieee80211->eRFPowerState)
749#endif
750 { 554 {
751 RT_TRACE(COMP_POWER, "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState); 555 RT_TRACE(COMP_POWER, "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
752 return bResult; 556 return bResult;
diff --git a/drivers/staging/rtl8192e/r8190_rtl8256.h b/drivers/staging/rtl8192e/r8190_rtl8256.h
index a50b14092cb..d9347fa4615 100644
--- a/drivers/staging/rtl8192e/r8190_rtl8256.h
+++ b/drivers/staging/rtl8192e/r8190_rtl8256.h
@@ -10,11 +10,7 @@
10#ifndef RTL8225_H 10#ifndef RTL8225_H
11#define RTL8225_H 11#define RTL8225_H
12 12
13#ifdef RTL8190P
14#define RTL819X_TOTAL_RF_PATH 4
15#else
16#define RTL819X_TOTAL_RF_PATH 2 /* for 8192E */ 13#define RTL819X_TOTAL_RF_PATH 2 /* for 8192E */
17#endif
18 14
19void PHY_SetRF8256Bandwidth(struct net_device *dev, 15void PHY_SetRF8256Bandwidth(struct net_device *dev,
20 HT_CHANNEL_WIDTH Bandwidth); 16 HT_CHANNEL_WIDTH Bandwidth);
diff --git a/drivers/staging/rtl8192e/r8192E_core.c b/drivers/staging/rtl8192e/r8192E_core.c
index 6190cdd3fb3..d3046afce0d 100644
--- a/drivers/staging/rtl8192e/r8192E_core.c
+++ b/drivers/staging/rtl8192e/r8192E_core.c
@@ -1,6 +1,6 @@
1/****************************************************************************** 1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 * Linux device driver for RTL8190P / RTL8192E 3 * Linux device driver for RTL8192E
4 * 4 *
5 * Based on the r8180 driver, which is: 5 * Based on the r8180 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. 6 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
@@ -90,21 +90,12 @@ u32 rt_global_debug_component =
90 COMP_ERR ; //always open err flags on 90 COMP_ERR ; //always open err flags on
91 91
92static DEFINE_PCI_DEVICE_TABLE(rtl8192_pci_id_tbl) = { 92static DEFINE_PCI_DEVICE_TABLE(rtl8192_pci_id_tbl) = {
93#ifdef RTL8190P
94 /* Realtek */
95 /* Dlink */
96 { PCI_DEVICE(0x10ec, 0x8190) },
97 /* Corega */
98 { PCI_DEVICE(0x07aa, 0x0045) },
99 { PCI_DEVICE(0x07aa, 0x0046) },
100#else
101 /* Realtek */ 93 /* Realtek */
102 { PCI_DEVICE(0x10ec, 0x8192) }, 94 { PCI_DEVICE(0x10ec, 0x8192) },
103 95
104 /* Corega */ 96 /* Corega */
105 { PCI_DEVICE(0x07aa, 0x0044) }, 97 { PCI_DEVICE(0x07aa, 0x0044) },
106 { PCI_DEVICE(0x07aa, 0x0047) }, 98 { PCI_DEVICE(0x07aa, 0x0047) },
107#endif
108 {} 99 {}
109}; 100};
110 101
@@ -887,9 +878,7 @@ void rtl8192_halt_adapter(struct net_device *dev, bool reset)
887 if (!reset) { 878 if (!reset) {
888 mdelay(150); 879 mdelay(150);
889 880
890#ifdef RTL8192E
891 priv->bHwRfOffAction = 2; 881 priv->bHwRfOffAction = 2;
892#endif
893 882
894 /* 883 /*
895 * Call MgntActSet_RF_State instead to 884 * Call MgntActSet_RF_State instead to
@@ -1396,12 +1385,8 @@ short rtl8192_tx(struct net_device *dev, struct sk_buff* skb)
1396 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { 1385 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1397 if (tcb_desc->bPacketBW) { 1386 if (tcb_desc->bPacketBW) {
1398 pTxFwInfo->TxBandwidth = 1; 1387 pTxFwInfo->TxBandwidth = 1;
1399#ifdef RTL8190P
1400 pTxFwInfo->TxSubCarrier = 3;
1401#else
1402 /* use duplicated mode */ 1388 /* use duplicated mode */
1403 pTxFwInfo->TxSubCarrier = 0; 1389 pTxFwInfo->TxSubCarrier = 0;
1404#endif
1405 } else { 1390 } else {
1406 pTxFwInfo->TxBandwidth = 0; 1391 pTxFwInfo->TxBandwidth = 0;
1407 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC; 1392 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
@@ -2285,15 +2270,9 @@ static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
2285{ 2270{
2286 struct net_device *dev = priv->ieee80211->dev; 2271 struct net_device *dev = priv->ieee80211->dev;
2287 u8 tempval; 2272 u8 tempval;
2288#ifdef RTL8192E
2289 u8 ICVer8192, ICVer8256; 2273 u8 ICVer8192, ICVer8256;
2290#endif
2291 u16 i,usValue, IC_Version; 2274 u16 i,usValue, IC_Version;
2292 u16 EEPROMId; 2275 u16 EEPROMId;
2293#ifdef RTL8190P
2294 u8 offset;
2295 u8 EepromTxPower[100];
2296#endif
2297 u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01}; 2276 u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
2298 RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n"); 2277 RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
2299 2278
@@ -2328,10 +2307,6 @@ static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
2328 priv->eeprom_ChannelPlan = usValue&0xff; 2307 priv->eeprom_ChannelPlan = usValue&0xff;
2329 IC_Version = ((usValue&0xff00)>>8); 2308 IC_Version = ((usValue&0xff00)>>8);
2330 2309
2331#ifdef RTL8190P
2332 priv->card_8192_version = (VERSION_8190)(IC_Version);
2333#else
2334 #ifdef RTL8192E
2335 ICVer8192 = (IC_Version&0xf); //bit0~3; 1:A cut, 2:B cut, 3:C cut... 2310 ICVer8192 = (IC_Version&0xf); //bit0~3; 1:A cut, 2:B cut, 3:C cut...
2336 ICVer8256 = ((IC_Version&0xf0)>>4);//bit4~6, bit7 reserved for other RF chip; 1:A cut, 2:B cut, 3:C cut... 2311 ICVer8256 = ((IC_Version&0xf0)>>4);//bit4~6, bit7 reserved for other RF chip; 1:A cut, 2:B cut, 3:C cut...
2337 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192); 2312 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
@@ -2341,8 +2316,7 @@ static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
2341 if(ICVer8256 == 0x5) //E-cut 2316 if(ICVer8256 == 0x5) //E-cut
2342 priv->card_8192_version= VERSION_8190_BE; 2317 priv->card_8192_version= VERSION_8190_BE;
2343 } 2318 }
2344 #endif 2319
2345#endif
2346 switch(priv->card_8192_version) 2320 switch(priv->card_8192_version)
2347 { 2321 {
2348 case VERSION_8190_BD: 2322 case VERSION_8190_BD:
@@ -2476,82 +2450,7 @@ static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
2476 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i+1, priv->EEPROMTxPowerLevelOFDM24G[i+1]); 2450 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i+1, priv->EEPROMTxPowerLevelOFDM24G[i+1]);
2477 } 2451 }
2478 } 2452 }
2479 else if(priv->epromtype== EPROM_93c56)
2480 {
2481 #ifdef RTL8190P
2482 // Read CrystalCap from EEPROM
2483 if(!priv->AutoloadFailFlag)
2484 {
2485 priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff;
2486 priv->EEPROMCrystalCap = (u8)(((eprom_read(dev, (EEPROM_C56_CrystalCap>>1))) & 0xf000)>>12);
2487 }
2488 else
2489 {
2490 priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff;
2491 priv->EEPROMCrystalCap = EEPROM_Default_TxPwDiff_CrystalCap;
2492 }
2493 RT_TRACE(COMP_INIT,"EEPROMAntPwDiff = %d\n", priv->EEPROMAntPwDiff);
2494 RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n", priv->EEPROMCrystalCap);
2495
2496 // Get Tx Power Level by Channel
2497 if(!priv->AutoloadFailFlag)
2498 {
2499 // Read Tx power of Channel 1 ~ 14 from EEPROM.
2500 for(i = 0; i < 12; i+=2)
2501 {
2502 if (i <6)
2503 offset = EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex + i;
2504 else
2505 offset = EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex + i - 6;
2506 usValue = eprom_read(dev, (offset>>1));
2507 *((u16*)(&EepromTxPower[i])) = usValue;
2508 }
2509
2510 for(i = 0; i < 12; i++)
2511 {
2512 if (i <= 2)
2513 priv->EEPROMRfACCKChnl1TxPwLevel[i] = EepromTxPower[i];
2514 else if ((i >=3 )&&(i <= 5))
2515 priv->EEPROMRfAOfdmChnlTxPwLevel[i-3] = EepromTxPower[i];
2516 else if ((i >=6 )&&(i <= 8))
2517 priv->EEPROMRfCCCKChnl1TxPwLevel[i-6] = EepromTxPower[i];
2518 else
2519 priv->EEPROMRfCOfdmChnlTxPwLevel[i-9] = EepromTxPower[i];
2520 }
2521 }
2522 else
2523 {
2524 priv->EEPROMRfACCKChnl1TxPwLevel[0] = EEPROM_Default_TxPowerLevel;
2525 priv->EEPROMRfACCKChnl1TxPwLevel[1] = EEPROM_Default_TxPowerLevel;
2526 priv->EEPROMRfACCKChnl1TxPwLevel[2] = EEPROM_Default_TxPowerLevel;
2527 2453
2528 priv->EEPROMRfAOfdmChnlTxPwLevel[0] = EEPROM_Default_TxPowerLevel;
2529 priv->EEPROMRfAOfdmChnlTxPwLevel[1] = EEPROM_Default_TxPowerLevel;
2530 priv->EEPROMRfAOfdmChnlTxPwLevel[2] = EEPROM_Default_TxPowerLevel;
2531
2532 priv->EEPROMRfCCCKChnl1TxPwLevel[0] = EEPROM_Default_TxPowerLevel;
2533 priv->EEPROMRfCCCKChnl1TxPwLevel[1] = EEPROM_Default_TxPowerLevel;
2534 priv->EEPROMRfCCCKChnl1TxPwLevel[2] = EEPROM_Default_TxPowerLevel;
2535
2536 priv->EEPROMRfCOfdmChnlTxPwLevel[0] = EEPROM_Default_TxPowerLevel;
2537 priv->EEPROMRfCOfdmChnlTxPwLevel[1] = EEPROM_Default_TxPowerLevel;
2538 priv->EEPROMRfCOfdmChnlTxPwLevel[2] = EEPROM_Default_TxPowerLevel;
2539 }
2540 RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[0] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[0]);
2541 RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[1] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[1]);
2542 RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[2] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[2]);
2543 RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[0] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[0]);
2544 RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[1] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[1]);
2545 RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[2] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[2]);
2546 RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[0] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[0]);
2547 RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[1] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[1]);
2548 RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[2] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[2]);
2549 RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[0] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[0]);
2550 RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[1] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[1]);
2551 RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[2] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[2]);
2552#endif
2553
2554 }
2555 // 2454 //
2556 // Update HAL variables. 2455 // Update HAL variables.
2557 // 2456 //
@@ -2711,13 +2610,7 @@ static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
2711 switch(priv->CustomerID) 2610 switch(priv->CustomerID)
2712 { 2611 {
2713 case RT_CID_DEFAULT: 2612 case RT_CID_DEFAULT:
2714 #ifdef RTL8190P
2715 priv->LedStrategy = HW_LED;
2716 #else
2717 #ifdef RTL8192E
2718 priv->LedStrategy = SW_LED_MODE1; 2613 priv->LedStrategy = SW_LED_MODE1;
2719 #endif
2720 #endif
2721 break; 2614 break;
2722 2615
2723 case RT_CID_819x_CAMEO: 2616 case RT_CID_819x_CAMEO:
@@ -2745,13 +2638,7 @@ static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
2745 //break; 2638 //break;
2746 2639
2747 default: 2640 default:
2748 #ifdef RTL8190P
2749 priv->LedStrategy = HW_LED;
2750 #else
2751 #ifdef RTL8192E
2752 priv->LedStrategy = SW_LED_MODE1; 2641 priv->LedStrategy = SW_LED_MODE1;
2753 #endif
2754 #endif
2755 break; 2642 break;
2756 } 2643 }
2757 2644
@@ -2917,13 +2804,8 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2917 RT_STATUS rtStatus = RT_STATUS_SUCCESS; 2804 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2918 //u8 eRFPath; 2805 //u8 eRFPath;
2919 u8 tmpvalue; 2806 u8 tmpvalue;
2920#ifdef RTL8192E
2921 u8 ICVersion,SwitchingRegulatorOutput; 2807 u8 ICVersion,SwitchingRegulatorOutput;
2922#endif
2923 bool bfirmwareok = true; 2808 bool bfirmwareok = true;
2924#ifdef RTL8190P
2925 u8 ucRegRead;
2926#endif
2927 u32 tmpRegA, tmpRegC, TempCCk; 2809 u32 tmpRegA, tmpRegC, TempCCk;
2928 int i =0; 2810 int i =0;
2929 2811
@@ -2932,7 +2814,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2932 rtl8192_pci_resetdescring(dev); 2814 rtl8192_pci_resetdescring(dev);
2933 // 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W. 2815 // 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W.
2934 priv->Rf_Mode = RF_OP_By_SW_3wire; 2816 priv->Rf_Mode = RF_OP_By_SW_3wire;
2935#ifdef RTL8192E 2817
2936 //dPLL on 2818 //dPLL on
2937 if(priv->ResetProgress == RESET_TYPE_NORESET) 2819 if(priv->ResetProgress == RESET_TYPE_NORESET)
2938 { 2820 {
@@ -2941,7 +2823,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2941 // Joseph increae the time to prevent firmware download fail 2823 // Joseph increae the time to prevent firmware download fail
2942 mdelay(500); 2824 mdelay(500);
2943 } 2825 }
2944#endif 2826
2945 //PlatformSleepUs(10000); 2827 //PlatformSleepUs(10000);
2946 // For any kind of InitializeAdapter process, we shall use system now!! 2828 // For any kind of InitializeAdapter process, we shall use system now!!
2947 priv->pFirmware->firmware_status = FW_STATUS_0_INIT; 2829 priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
@@ -2959,16 +2841,9 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2959 else 2841 else
2960 RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status); 2842 RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status);
2961 2843
2962#ifdef RTL8190P
2963 //2008.06.03, for WOL 90 hw bug
2964 ulRegRead &= (~(CPU_GEN_GPIO_UART));
2965#endif
2966
2967 write_nic_dword(priv, CPU_GEN, ulRegRead); 2844 write_nic_dword(priv, CPU_GEN, ulRegRead);
2968 //mdelay(100); 2845 //mdelay(100);
2969 2846
2970#ifdef RTL8192E
2971
2972 //3// 2847 //3//
2973 //3 //Fix the issue of E-cut high temperature issue 2848 //3 //Fix the issue of E-cut high temperature issue
2974 //3// 2849 //3//
@@ -2987,8 +2862,6 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2987 write_nic_byte(priv, SWREGULATOR, 0xb8); 2862 write_nic_byte(priv, SWREGULATOR, 0xb8);
2988 } 2863 }
2989 } 2864 }
2990#endif
2991
2992 2865
2993 //3// 2866 //3//
2994 //3// Initialize BB before MAC 2867 //3// Initialize BB before MAC
@@ -3042,16 +2915,9 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3042 write_nic_byte(priv, CMDR, CR_RE|CR_TE); 2915 write_nic_byte(priv, CMDR, CR_RE|CR_TE);
3043 2916
3044 //2Set Tx dma burst 2917 //2Set Tx dma burst
3045#ifdef RTL8190P
3046 write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
3047 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) |
3048 (1<<MULRW_SHIFT)));
3049#else
3050 #ifdef RTL8192E
3051 write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) | 2918 write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
3052 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) )); 2919 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) ));
3053 #endif 2920
3054#endif
3055 //set IDR0 here 2921 //set IDR0 here
3056 write_nic_dword(priv, MAC0, ((u32*)dev->dev_addr)[0]); 2922 write_nic_dword(priv, MAC0, ((u32*)dev->dev_addr)[0]);
3057 write_nic_word(priv, MAC4, ((u16*)(dev->dev_addr + 4))[0]); 2923 write_nic_word(priv, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
@@ -3185,20 +3051,8 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3185 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); 3051 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
3186 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); 3052 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
3187 3053
3188#ifdef RTL8192E
3189 //Enable Led 3054 //Enable Led
3190 write_nic_byte(priv, 0x87, 0x0); 3055 write_nic_byte(priv, 0x87, 0x0);
3191#endif
3192#ifdef RTL8190P
3193 //2008.06.03, for WOL
3194 ucRegRead = read_nic_byte(priv, GPE);
3195 ucRegRead |= BIT0;
3196 write_nic_byte(priv, GPE, ucRegRead);
3197
3198 ucRegRead = read_nic_byte(priv, GPO);
3199 ucRegRead &= ~BIT0;
3200 write_nic_byte(priv, GPO, ucRegRead);
3201#endif
3202 3056
3203 //2======================================================= 3057 //2=======================================================
3204 // RF Power Save 3058 // RF Power Save
@@ -3236,69 +3090,12 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3236 } 3090 }
3237} 3091}
3238#endif 3092#endif
3239 if(1){ 3093 // We can force firmware to do RF-R/W
3240#ifdef RTL8192E 3094 if(priv->ieee80211->FwRWRF)
3241 // We can force firmware to do RF-R/W 3095 priv->Rf_Mode = RF_OP_By_FW;
3242 if(priv->ieee80211->FwRWRF) 3096 else
3243 priv->Rf_Mode = RF_OP_By_FW; 3097 priv->Rf_Mode = RF_OP_By_SW_3wire;
3244 else
3245 priv->Rf_Mode = RF_OP_By_SW_3wire;
3246#else
3247 priv->Rf_Mode = RF_OP_By_SW_3wire;
3248#endif
3249 }
3250#ifdef RTL8190P
3251 if(priv->ResetProgress == RESET_TYPE_NORESET)
3252 {
3253 dm_initialize_txpower_tracking(dev);
3254
3255 tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord);
3256 tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord);
3257
3258 if(priv->rf_type == RF_2T4R){
3259 for(i = 0; i<TxBBGainTableLength; i++)
3260 {
3261 if(tmpRegA == priv->txbbgain_table[i].txbbgain_value)
3262 {
3263 priv->rfa_txpowertrackingindex= (u8)i;
3264 priv->rfa_txpowertrackingindex_real= (u8)i;
3265 priv->rfa_txpowertracking_default = priv->rfa_txpowertrackingindex;
3266 break;
3267 }
3268 }
3269 }
3270 for(i = 0; i<TxBBGainTableLength; i++)
3271 {
3272 if(tmpRegC == priv->txbbgain_table[i].txbbgain_value)
3273 {
3274 priv->rfc_txpowertrackingindex= (u8)i;
3275 priv->rfc_txpowertrackingindex_real= (u8)i;
3276 priv->rfc_txpowertracking_default = priv->rfc_txpowertrackingindex;
3277 break;
3278 }
3279 }
3280 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
3281 3098
3282 for(i=0 ; i<CCKTxBBGainTableLength ; i++)
3283 {
3284 if(TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0])
3285 {
3286 priv->CCKPresentAttentuation_20Mdefault =(u8) i;
3287 break;
3288 }
3289 }
3290 priv->CCKPresentAttentuation_40Mdefault = 0;
3291 priv->CCKPresentAttentuation_difference = 0;
3292 priv->CCKPresentAttentuation = priv->CCKPresentAttentuation_20Mdefault;
3293 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_initial = %d\n", priv->rfa_txpowertrackingindex);
3294 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real__initial = %d\n", priv->rfa_txpowertrackingindex_real);
3295 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_initial = %d\n", priv->rfc_txpowertrackingindex);
3296 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real_initial = %d\n", priv->rfc_txpowertrackingindex_real);
3297 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference_initial = %d\n", priv->CCKPresentAttentuation_difference);
3298 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_initial = %d\n", priv->CCKPresentAttentuation);
3299 }
3300#else
3301 #ifdef RTL8192E
3302 if(priv->ResetProgress == RESET_TYPE_NORESET) 3099 if(priv->ResetProgress == RESET_TYPE_NORESET)
3303 { 3100 {
3304 dm_initialize_txpower_tracking(dev); 3101 dm_initialize_txpower_tracking(dev);
@@ -3338,8 +3135,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3338 priv->btxpower_tracking = FALSE;//TEMPLY DISABLE 3135 priv->btxpower_tracking = FALSE;//TEMPLY DISABLE
3339 } 3136 }
3340 } 3137 }
3341 #endif 3138
3342#endif
3343 rtl8192_irq_enable(dev); 3139 rtl8192_irq_enable(dev);
3344 priv->being_init_adapter = false; 3140 priv->being_init_adapter = false;
3345 return rtStatus; 3141 return rtStatus;
@@ -4260,10 +4056,10 @@ static int _rtl8192_up(struct net_device *dev)
4260 return -1; 4056 return -1;
4261 } 4057 }
4262 RT_TRACE(COMP_INIT, "start adapter finished\n"); 4058 RT_TRACE(COMP_INIT, "start adapter finished\n");
4263#ifdef RTL8192E 4059
4264 if(priv->ieee80211->eRFPowerState!=eRfOn) 4060 if(priv->ieee80211->eRFPowerState!=eRfOn)
4265 MgntActSet_RF_State(dev, eRfOn, priv->ieee80211->RfOffReason); 4061 MgntActSet_RF_State(dev, eRfOn, priv->ieee80211->RfOffReason);
4266#endif 4062
4267 if(priv->ieee80211->state != IEEE80211_LINKED) 4063 if(priv->ieee80211->state != IEEE80211_LINKED)
4268 ieee80211_softmac_start_protocol(priv->ieee80211); 4064 ieee80211_softmac_start_protocol(priv->ieee80211);
4269 ieee80211_reset_queue(priv->ieee80211); 4065 ieee80211_reset_queue(priv->ieee80211);
@@ -4603,67 +4399,6 @@ static long rtl819x_translate_todbm(u8 signal_strength_index)// 0-100 index.
4603 return signal_power; 4399 return signal_power;
4604} 4400}
4605 4401
4606static void
4607rtl8190_process_cck_rxpathsel(
4608 struct r8192_priv * priv,
4609 struct ieee80211_rx_stats * pprevious_stats
4610 )
4611{
4612#ifdef RTL8190P //Only 90P 2T4R need to check
4613 char last_cck_adc_pwdb[4]={0,0,0,0};
4614 u8 i;
4615//cosa add for Rx path selection
4616 if(priv->rf_type == RF_2T4R && DM_RxPathSelTable.Enable)
4617 {
4618 if(pprevious_stats->bIsCCK &&
4619 (pprevious_stats->bPacketToSelf ||pprevious_stats->bPacketBeacon))
4620 {
4621 /* record the cck adc_pwdb to the sliding window. */
4622 if(priv->stats.cck_adc_pwdb.TotalNum++ >= PHY_RSSI_SLID_WIN_MAX)
4623 {
4624 priv->stats.cck_adc_pwdb.TotalNum = PHY_RSSI_SLID_WIN_MAX;
4625 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
4626 {
4627 last_cck_adc_pwdb[i] = priv->stats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index];
4628 priv->stats.cck_adc_pwdb.TotalVal[i] -= last_cck_adc_pwdb[i];
4629 }
4630 }
4631 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
4632 {
4633 priv->stats.cck_adc_pwdb.TotalVal[i] += pprevious_stats->cck_adc_pwdb[i];
4634 priv->stats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index] = pprevious_stats->cck_adc_pwdb[i];
4635 }
4636 priv->stats.cck_adc_pwdb.index++;
4637 if(priv->stats.cck_adc_pwdb.index >= PHY_RSSI_SLID_WIN_MAX)
4638 priv->stats.cck_adc_pwdb.index = 0;
4639
4640 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
4641 {
4642 DM_RxPathSelTable.cck_pwdb_sta[i] = priv->stats.cck_adc_pwdb.TotalVal[i]/priv->stats.cck_adc_pwdb.TotalNum;
4643 }
4644
4645 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
4646 {
4647 if(pprevious_stats->cck_adc_pwdb[i] > (char)priv->undecorated_smoothed_cck_adc_pwdb[i])
4648 {
4649 priv->undecorated_smoothed_cck_adc_pwdb[i] =
4650 ( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) +
4651 (pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor);
4652 priv->undecorated_smoothed_cck_adc_pwdb[i] = priv->undecorated_smoothed_cck_adc_pwdb[i] + 1;
4653 }
4654 else
4655 {
4656 priv->undecorated_smoothed_cck_adc_pwdb[i] =
4657 ( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) +
4658 (pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor);
4659 }
4660 }
4661 }
4662 }
4663#endif
4664}
4665
4666
4667/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to 4402/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to
4668 be a local static. Otherwise, it may increase when we return from S3/S4. The 4403 be a local static. Otherwise, it may increase when we return from S3/S4. The
4669 value will be kept in memory or disk. We must delcare the value in adapter 4404 value will be kept in memory or disk. We must delcare the value in adapter
@@ -4730,8 +4465,6 @@ static void rtl8192_process_phyinfo(struct r8192_priv * priv, u8* buffer,struct
4730 if(!bcheck) 4465 if(!bcheck)
4731 return; 4466 return;
4732 4467
4733 rtl8190_process_cck_rxpathsel(priv,pprevious_stats);
4734
4735 // <2> Showed on UI for engineering 4468 // <2> Showed on UI for engineering
4736 // hardware does not provide rssi information for each rf path in CCK 4469 // hardware does not provide rssi information for each rf path in CCK
4737 if(!pprevious_stats->bIsCCK && pprevious_stats->bPacketToSelf) 4470 if(!pprevious_stats->bIsCCK && pprevious_stats->bPacketToSelf)
@@ -5019,23 +4752,6 @@ static void rtl8192_query_rxphystatus(
5019 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) 4752 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
5020 // 4753 //
5021 u8 report;//, cck_agc_rpt; 4754 u8 report;//, cck_agc_rpt;
5022#ifdef RTL8190P
5023 u8 tmp_pwdb;
5024 char cck_adc_pwdb[4];
5025#endif
5026
5027#ifdef RTL8190P //Only 90P 2T4R need to check
5028 if(priv->rf_type == RF_2T4R && DM_RxPathSelTable.Enable && bpacket_match_bssid)
5029 {
5030 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
5031 {
5032 tmp_pwdb = pcck_buf->adc_pwdb_X[i];
5033 cck_adc_pwdb[i] = (char)tmp_pwdb;
5034 cck_adc_pwdb[i] /= 2;
5035 pstats->cck_adc_pwdb[i] = precord_stats->cck_adc_pwdb[i] = cck_adc_pwdb[i];
5036 }
5037 }
5038#endif
5039 4755
5040 if (!priv->phy_reg824_bit9) 4756 if (!priv->phy_reg824_bit9)
5041 { 4757 {
@@ -5126,11 +4842,7 @@ static void rtl8192_query_rxphystatus(
5126 4842
5127 //Fixed by Jacken from Bryant 2008-03-20 4843 //Fixed by Jacken from Bryant 2008-03-20
5128 //Original value is 106 4844 //Original value is 106
5129#ifdef RTL8190P //Modify by Jacken 2008/03/31
5130 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
5131#else
5132 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 110; 4845 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 110;
5133#endif
5134 4846
5135 //Get Rx snr value in DB 4847 //Get Rx snr value in DB
5136 tmp_rxsnr = pofdm_buf->rxsnr_X[i]; 4848 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
@@ -5699,9 +5411,7 @@ static void rtl8192_cancel_deferred_work(struct r8192_priv* priv)
5699 cancel_delayed_work(&priv->update_beacon_wq); 5411 cancel_delayed_work(&priv->update_beacon_wq);
5700 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); 5412 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
5701 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); 5413 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
5702#ifdef RTL8192E
5703 cancel_delayed_work(&priv->gpio_change_rf_wq); 5414 cancel_delayed_work(&priv->gpio_change_rf_wq);
5704#endif
5705 cancel_work_sync(&priv->reset_wq); 5415 cancel_work_sync(&priv->reset_wq);
5706 cancel_work_sync(&priv->qos_activate); 5416 cancel_work_sync(&priv->qos_activate);
5707 //cancel_work_sync(&priv->SetBWModeWorkItem); 5417 //cancel_work_sync(&priv->SetBWModeWorkItem);
diff --git a/drivers/staging/rtl8192e/r8192E_dm.c b/drivers/staging/rtl8192e/r8192E_dm.c
index 20d9c0b8a12..1ade3672546 100644
--- a/drivers/staging/rtl8192e/r8192E_dm.c
+++ b/drivers/staging/rtl8192e/r8192E_dm.c
@@ -25,24 +25,10 @@ Major Change History:
25// 25//
26// Indicate different AP vendor for IOT issue. 26// Indicate different AP vendor for IOT issue.
27// 27//
28#ifdef RTL8190P
29static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
30{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
31static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
32{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
33#else
34#ifdef RTL8192E
35static const u32 edca_setting_DL[HT_IOT_PEER_MAX] = 28static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
36{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322}; 29{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
37static const u32 edca_setting_UL[HT_IOT_PEER_MAX] = 30static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
38{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322}; 31{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
39#else
40static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
41{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f, 0x5e4322};
42static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
43{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f, 0x5e4322};
44#endif
45#endif
46 32
47#define RTK_UL_EDCA 0xa44f 33#define RTK_UL_EDCA 0xa44f
48#define RTK_DL_EDCA 0x5e4322 34#define RTK_DL_EDCA 0x5e4322
@@ -82,9 +68,7 @@ extern void dm_fsync_timer_callback(unsigned long data);
82extern void dm_check_fsync(struct net_device *dev); 68extern void dm_check_fsync(struct net_device *dev);
83extern void dm_initialize_txpower_tracking(struct net_device *dev); 69extern void dm_initialize_txpower_tracking(struct net_device *dev);
84 70
85#ifdef RTL8192E
86extern void dm_gpio_change_rf_callback(struct work_struct *work); 71extern void dm_gpio_change_rf_callback(struct work_struct *work);
87#endif
88 72
89 73
90// DM --> Rate Adaptive 74// DM --> Rate Adaptive
@@ -97,14 +81,6 @@ static void dm_bandwidth_autoswitch( struct net_device *dev);
97// DM --> TX power control 81// DM --> TX power control
98static void dm_check_txpower_tracking(struct net_device *dev); 82static void dm_check_txpower_tracking(struct net_device *dev);
99 83
100// DM --> BB init gain restore
101#ifndef RTL8192U
102static void dm_bb_initialgain_restore(struct net_device *dev);
103
104// DM --> BB init gain backup
105static void dm_bb_initialgain_backup(struct net_device *dev);
106#endif
107
108// DM --> Dynamic Init Gain by RSSI 84// DM --> Dynamic Init Gain by RSSI
109static void dm_dig_init(struct net_device *dev); 85static void dm_dig_init(struct net_device *dev);
110static void dm_ctrl_initgain_byrssi(struct net_device *dev); 86static void dm_ctrl_initgain_byrssi(struct net_device *dev);
@@ -166,9 +142,7 @@ void init_hal_dm(struct net_device *dev)
166 dm_init_fsync(dev); 142 dm_init_fsync(dev);
167 dm_init_rxpath_selection(dev); 143 dm_init_rxpath_selection(dev);
168 dm_init_ctstoself(dev); 144 dm_init_ctstoself(dev);
169#ifdef RTL8192E
170 INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback); 145 INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
171#endif
172 146
173} 147}
174 148
@@ -503,7 +477,6 @@ static void dm_bandwidth_autoswitch(struct net_device * dev)
503} 477}
504 478
505//OFDM default at 0db, index=6. 479//OFDM default at 0db, index=6.
506#ifndef RTL8190P
507static const u32 OFDMSwingTable[OFDM_Table_Length] = { 480static const u32 OFDMSwingTable[OFDM_Table_Length] = {
508 0x7f8001fe, // 0, +6db 481 0x7f8001fe, // 0, +6db
509 0x71c001c7, // 1, +5db 482 0x71c001c7, // 1, +5db
@@ -554,7 +527,7 @@ static const u8 CCKSwingTable_Ch14[CCK_Table_length][8] = {
554 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db 527 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
555 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db 528 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
556}; 529};
557#endif 530
558#define Pw_Track_Flag 0x11d 531#define Pw_Track_Flag 0x11d
559#define Tssi_Mea_Value 0x13c 532#define Tssi_Mea_Value 0x13c
560#define Tssi_Report_Value1 0x134 533#define Tssi_Report_Value1 0x134
@@ -571,9 +544,6 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
571 u32 Value; 544 u32 Value;
572 u8 Pwr_Flag; 545 u8 Pwr_Flag;
573 u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0; 546 u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0;
574#ifdef RTL8192U
575 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
576#endif
577// bool rtStatus = true; 547// bool rtStatus = true;
578 u32 delta=0; 548 u32 delta=0;
579 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__); 549 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
@@ -595,15 +565,7 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
595 tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING; 565 tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING;
596 tx_cmd.Length = 4; 566 tx_cmd.Length = 4;
597 tx_cmd.Value = Value; 567 tx_cmd.Value = Value;
598#ifdef RTL8192U
599 rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
600 if (rtStatus == RT_STATUS_FAILURE)
601 {
602 RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
603 }
604#else
605 cmpk_message_handle_tx(dev, (u8*)&tx_cmd, DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T)); 568 cmpk_message_handle_tx(dev, (u8*)&tx_cmd, DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
606#endif
607 mdelay(1); 569 mdelay(1);
608 570
609 for(i = 0;i <= 30; i++) 571 for(i = 0;i <= 30; i++)
@@ -679,10 +641,6 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
679 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n"); 641 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
680 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex); 642 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
681 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real); 643 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
682#ifdef RTL8190P
683 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
684 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
685#endif
686 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference); 644 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
687 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); 645 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
688 return; 646 return;
@@ -798,10 +756,6 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
798 } 756 }
799 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex); 757 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
800 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real); 758 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
801#ifdef RTL8190P
802 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
803 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
804#endif
805 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference); 759 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
806 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); 760 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
807 761
@@ -827,7 +781,7 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
827 priv->ieee80211->bdynamic_txpower_enable = TRUE; 781 priv->ieee80211->bdynamic_txpower_enable = TRUE;
828 write_nic_byte(priv, Pw_Track_Flag, 0); 782 write_nic_byte(priv, Pw_Track_Flag, 0);
829} 783}
830#ifndef RTL8190P 784
831static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev) 785static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
832{ 786{
833#define ThermalMeterVal 9 787#define ThermalMeterVal 9
@@ -941,22 +895,17 @@ static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
941 } 895 }
942 priv->txpower_count = 0; 896 priv->txpower_count = 0;
943} 897}
944#endif 898
945void dm_txpower_trackingcallback(struct work_struct *work) 899void dm_txpower_trackingcallback(struct work_struct *work)
946{ 900{
947 struct delayed_work *dwork = container_of(work,struct delayed_work,work); 901 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
948 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq); 902 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq);
949 struct net_device *dev = priv->ieee80211->dev; 903 struct net_device *dev = priv->ieee80211->dev;
950 904
951#ifdef RTL8190P
952 dm_TXPowerTrackingCallback_TSSI(dev);
953#else
954 //if(priv->bDcut == TRUE)
955 if(priv->IC_Cut >= IC_VersionCut_D) 905 if(priv->IC_Cut >= IC_VersionCut_D)
956 dm_TXPowerTrackingCallback_TSSI(dev); 906 dm_TXPowerTrackingCallback_TSSI(dev);
957 else 907 else
958 dm_TXPowerTrackingCallback_ThermalMeter(dev); 908 dm_TXPowerTrackingCallback_ThermalMeter(dev);
959#endif
960} 909}
961 910
962 911
@@ -1073,7 +1022,7 @@ static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
1073 priv->btxpower_trackingInit = FALSE; 1022 priv->btxpower_trackingInit = FALSE;
1074 1023
1075} 1024}
1076#ifndef RTL8190P 1025
1077static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev) 1026static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1078{ 1027{
1079 struct r8192_priv *priv = ieee80211_priv(dev); 1028 struct r8192_priv *priv = ieee80211_priv(dev);
@@ -1088,21 +1037,15 @@ static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1088 priv->txpower_count = 0; 1037 priv->txpower_count = 0;
1089 priv->btxpower_trackingInit = FALSE; 1038 priv->btxpower_trackingInit = FALSE;
1090} 1039}
1091#endif
1092 1040
1093void dm_initialize_txpower_tracking(struct net_device *dev) 1041void dm_initialize_txpower_tracking(struct net_device *dev)
1094{ 1042{
1095#ifndef RTL8190P
1096 struct r8192_priv *priv = ieee80211_priv(dev); 1043 struct r8192_priv *priv = ieee80211_priv(dev);
1097#endif 1044
1098#ifdef RTL8190P
1099 dm_InitializeTXPowerTracking_TSSI(dev);
1100#else
1101 if(priv->IC_Cut >= IC_VersionCut_D) 1045 if(priv->IC_Cut >= IC_VersionCut_D)
1102 dm_InitializeTXPowerTracking_TSSI(dev); 1046 dm_InitializeTXPowerTracking_TSSI(dev);
1103 else 1047 else
1104 dm_InitializeTXPowerTracking_ThermalMeter(dev); 1048 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1105#endif
1106} 1049}
1107 1050
1108 1051
@@ -1123,7 +1066,6 @@ static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1123 } 1066 }
1124} 1067}
1125 1068
1126#ifndef RTL8190P
1127static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev) 1069static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1128{ 1070{
1129 struct r8192_priv *priv = ieee80211_priv(dev); 1071 struct r8192_priv *priv = ieee80211_priv(dev);
@@ -1156,24 +1098,15 @@ static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1156 TM_Trigger = 0; 1098 TM_Trigger = 0;
1157 } 1099 }
1158} 1100}
1159#endif
1160 1101
1161static void dm_check_txpower_tracking(struct net_device *dev) 1102static void dm_check_txpower_tracking(struct net_device *dev)
1162{ 1103{
1163#ifndef RTL8190P
1164 struct r8192_priv *priv = ieee80211_priv(dev); 1104 struct r8192_priv *priv = ieee80211_priv(dev);
1165 //static u32 tx_power_track_counter = 0; 1105
1166#endif
1167#ifdef RTL8190P
1168 dm_CheckTXPowerTracking_TSSI(dev);
1169#else
1170 //if(priv->bDcut == TRUE)
1171 if(priv->IC_Cut >= IC_VersionCut_D) 1106 if(priv->IC_Cut >= IC_VersionCut_D)
1172 dm_CheckTXPowerTracking_TSSI(dev); 1107 dm_CheckTXPowerTracking_TSSI(dev);
1173 else 1108 else
1174 dm_CheckTXPowerTracking_ThermalMeter(dev); 1109 dm_CheckTXPowerTracking_ThermalMeter(dev);
1175#endif
1176
1177} 1110}
1178 1111
1179 1112
@@ -1226,7 +1159,7 @@ static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
1226 1159
1227 1160
1228} 1161}
1229#ifndef RTL8190P 1162
1230static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14) 1163static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14)
1231{ 1164{
1232 u32 TempVal; 1165 u32 TempVal;
@@ -1288,158 +1221,17 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH
1288 rCCK0_DebugPort, TempVal); 1221 rCCK0_DebugPort, TempVal);
1289 } 1222 }
1290} 1223}
1291#endif
1292
1293 1224
1294void dm_cck_txpower_adjust(struct net_device *dev, bool binch14) 1225void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1295{ 1226{
1296#ifndef RTL8190P
1297 struct r8192_priv *priv = ieee80211_priv(dev); 1227 struct r8192_priv *priv = ieee80211_priv(dev);
1298#endif 1228
1299#ifdef RTL8190P
1300 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1301#else
1302 if(priv->IC_Cut >= IC_VersionCut_D) 1229 if(priv->IC_Cut >= IC_VersionCut_D)
1303 dm_CCKTxPowerAdjust_TSSI(dev, binch14); 1230 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1304 else 1231 else
1305 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14); 1232 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1306#endif
1307}
1308
1309
1310#ifndef RTL8192U
1311static void dm_txpower_reset_recovery(
1312 struct net_device *dev
1313)
1314{
1315 struct r8192_priv *priv = ieee80211_priv(dev);
1316
1317 RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1318 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1319 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1320 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex);
1321 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1322 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->CCKPresentAttentuation);
1323 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1324
1325 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1326 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1327 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);
1328 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1329
1330} 1233}
1331 1234
1332void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1333{
1334 struct r8192_priv *priv = ieee80211_priv(dev);
1335 u32 reg_ratr = priv->rate_adaptive.last_ratr;
1336
1337 if(!priv->up)
1338 {
1339 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1340 return;
1341 }
1342
1343 //
1344 // Restore previous state for rate adaptive
1345 //
1346 if(priv->rate_adaptive.rate_adaptive_disabled)
1347 return;
1348 // TODO: Only 11n mode is implemented currently,
1349 if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||
1350 priv->ieee80211->mode==WIRELESS_MODE_N_5G))
1351 return;
1352 {
1353 /* 2007/11/15 MH Copy from 8190PCI. */
1354 u32 ratr_value;
1355 ratr_value = reg_ratr;
1356 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
1357 {
1358 ratr_value &=~ (RATE_ALL_OFDM_2SS);
1359 }
1360 write_nic_dword(priv, RATR0, ratr_value);
1361 write_nic_byte(priv, UFWP, 1);
1362 }
1363 //Resore TX Power Tracking Index
1364 if(priv->btxpower_trackingInit && priv->btxpower_tracking){
1365 dm_txpower_reset_recovery(dev);
1366 }
1367
1368 //
1369 //Restore BB Initial Gain
1370 //
1371 dm_bb_initialgain_restore(dev);
1372
1373}
1374
1375static void dm_bb_initialgain_restore(struct net_device *dev)
1376{
1377 struct r8192_priv *priv = ieee80211_priv(dev);
1378 u32 bit_mask = 0x7f; //Bit0~ Bit6
1379
1380 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1381 return;
1382
1383 //Disable Initial Gain
1384 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1385 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1386 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1387 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1388 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1389 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1390 bit_mask = bMaskByte2;
1391 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1392
1393 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1394 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1395 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1396 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1397 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1398 //Enable Initial Gain
1399 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
1400 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1401
1402}
1403
1404
1405void dm_backup_dynamic_mechanism_state(struct net_device *dev)
1406{
1407 struct r8192_priv *priv = ieee80211_priv(dev);
1408
1409 // Fsync to avoid reset
1410 priv->bswitch_fsync = false;
1411 //Backup BB InitialGain
1412 dm_bb_initialgain_backup(dev);
1413
1414}
1415
1416
1417static void dm_bb_initialgain_backup(struct net_device *dev)
1418{
1419 struct r8192_priv *priv = ieee80211_priv(dev);
1420 u32 bit_mask = bMaskByte0; //Bit0~ Bit6
1421
1422 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1423 return;
1424
1425 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1426 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1427 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1428 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1429 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1430 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1431 bit_mask = bMaskByte2;
1432 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1433
1434 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1435 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1436 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1437 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1438 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1439
1440}
1441
1442#endif
1443 1235
1444void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value) 1236void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value)
1445{ 1237{
@@ -1660,19 +1452,7 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1660 { 1452 {
1661 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ 1453 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1662 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. 1454 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1663 #ifdef RTL8190P 1455 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
1664 write_nic_byte(priv, rOFDM0_RxDetector1, 0x40);
1665 #else
1666 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
1667 #endif
1668 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1669 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1670 */
1671 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1672
1673
1674 //else
1675 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1676 } 1456 }
1677 else 1457 else
1678 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42); 1458 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
@@ -1730,19 +1510,7 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1730 { 1510 {
1731 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ 1511 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1732 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. 1512 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1733 #ifdef RTL8190P 1513 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
1734 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1735 #else
1736 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
1737 #endif
1738 /*
1739 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1740 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1741 */
1742 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1743
1744 //else
1745 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
1746 } 1514 }
1747 else 1515 else
1748 write_nic_byte(priv, rOFDM0_RxDetector1, 0x44); 1516 write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
@@ -1790,16 +1558,7 @@ static void dm_ctrl_initgain_byrssi_highpwr(
1790 // 3.1 Higher PD_TH for OFDM for high power state. 1558 // 3.1 Higher PD_TH for OFDM for high power state.
1791 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) 1559 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1792 { 1560 {
1793 #ifdef RTL8190P 1561 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
1794 write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
1795 #else
1796 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
1797 #endif
1798
1799 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1800 write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
1801 */
1802
1803 } 1562 }
1804 else 1563 else
1805 write_nic_byte(priv, rOFDM0_RxDetector1, 0x43); 1564 write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);
@@ -1818,15 +1577,7 @@ static void dm_ctrl_initgain_byrssi_highpwr(
1818 // 3.2 Recover PD_TH for OFDM for normal power region. 1577 // 3.2 Recover PD_TH for OFDM for normal power region.
1819 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) 1578 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1820 { 1579 {
1821 #ifdef RTL8190P 1580 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
1822 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1823 #else
1824 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
1825 #endif
1826 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1827 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1828 */
1829
1830 } 1581 }
1831 else 1582 else
1832 write_nic_byte(priv, rOFDM0_RxDetector1, 0x44); 1583 write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
@@ -1959,14 +1710,7 @@ static void dm_pd_th(
1959 { 1710 {
1960 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ 1711 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1961 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. 1712 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1962 #ifdef RTL8190P 1713 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
1963 write_nic_byte(priv, rOFDM0_RxDetector1, 0x40);
1964 #else
1965 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
1966 #endif
1967 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1968 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
1969 */
1970 } 1714 }
1971 else 1715 else
1972 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42); 1716 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
@@ -1978,14 +1722,7 @@ static void dm_pd_th(
1978 { 1722 {
1979 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ 1723 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1980 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. 1724 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1981 #ifdef RTL8190P 1725 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
1982 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1983 #else
1984 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
1985 #endif
1986 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1987 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1988 */
1989 } 1726 }
1990 else 1727 else
1991 write_nic_byte(priv, rOFDM0_RxDetector1, 0x44); 1728 write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
@@ -1995,14 +1732,7 @@ static void dm_pd_th(
1995 // Higher PD_TH for OFDM for high power state. 1732 // Higher PD_TH for OFDM for high power state.
1996 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) 1733 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1997 { 1734 {
1998 #ifdef RTL8190P 1735 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
1999 write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
2000 #else
2001 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
2002 #endif
2003 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2004 write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
2005 */
2006 } 1736 }
2007 else 1737 else
2008 write_nic_byte(priv, rOFDM0_RxDetector1, 0x43); 1738 write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);
@@ -2243,51 +1973,21 @@ static void dm_ctstoself(struct net_device *dev)
2243/* Copy 8187B template for 9xseries */ 1973/* Copy 8187B template for 9xseries */
2244static void dm_check_rfctrl_gpio(struct net_device * dev) 1974static void dm_check_rfctrl_gpio(struct net_device * dev)
2245{ 1975{
2246#ifdef RTL8192E
2247 struct r8192_priv *priv = ieee80211_priv(dev); 1976 struct r8192_priv *priv = ieee80211_priv(dev);
2248#endif
2249 1977
2250 // Walk around for DTM test, we will not enable HW - radio on/off because r/w 1978 // Walk around for DTM test, we will not enable HW - radio on/off because r/w
2251 // page 1 register before Lextra bus is enabled cause system fails when resuming 1979 // page 1 register before Lextra bus is enabled cause system fails when resuming
2252 // from S4. 20080218, Emily 1980 // from S4. 20080218, Emily
2253 1981
2254 // Stop to execute workitem to prevent S3/S4 bug. 1982 // Stop to execute workitem to prevent S3/S4 bug.
2255#ifdef RTL8190P 1983 queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
2256 return;
2257#endif
2258#ifdef RTL8192U
2259 return;
2260#endif
2261#ifdef RTL8192E
2262 queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
2263#endif
2264
2265} 1984}
2266 1985
2267/* Check if PBC button is pressed. */ 1986/* Check if PBC button is pressed. */
2268static void dm_check_pbc_gpio(struct net_device *dev) 1987static void dm_check_pbc_gpio(struct net_device *dev)
2269{ 1988{
2270#ifdef RTL8192U
2271 struct r8192_priv *priv = ieee80211_priv(dev);
2272 u8 tmp1byte;
2273
2274
2275 tmp1byte = read_nic_byte(priv, GPI);
2276 if(tmp1byte == 0xff)
2277 return;
2278
2279 if (tmp1byte&BIT6 || tmp1byte&BIT0)
2280 {
2281 // Here we only set bPbcPressed to TRUE
2282 // After trigger PBC, the variable will be set to FALSE
2283 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
2284 }
2285#endif
2286
2287} 1989}
2288 1990
2289#ifdef RTL8192E
2290
2291/* PCI will not support workitem call back HW radio on-off control. */ 1991/* PCI will not support workitem call back HW radio on-off control. */
2292void dm_gpio_change_rf_callback(struct work_struct *work) 1992void dm_gpio_change_rf_callback(struct work_struct *work)
2293{ 1993{
@@ -2328,8 +2028,6 @@ void dm_gpio_change_rf_callback(struct work_struct *work)
2328 } 2028 }
2329} 2029}
2330 2030
2331#endif
2332
2333/* Check if Current RF RX path is enabled */ 2031/* Check if Current RF RX path is enabled */
2334void dm_rf_pathcheck_workitemcallback(struct work_struct *work) 2032void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
2335{ 2033{
@@ -2655,11 +2353,7 @@ static void dm_init_fsync (struct net_device *dev)
2655 priv->ieee80211->fsync_time_interval = 500; 2353 priv->ieee80211->fsync_time_interval = 500;
2656 priv->ieee80211->fsync_rate_bitmap = 0x0f000800; 2354 priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
2657 priv->ieee80211->fsync_rssi_threshold = 30; 2355 priv->ieee80211->fsync_rssi_threshold = 30;
2658#ifdef RTL8190P
2659 priv->ieee80211->bfsync_enable = true;
2660#else
2661 priv->ieee80211->bfsync_enable = false; 2356 priv->ieee80211->bfsync_enable = false;
2662#endif
2663 priv->ieee80211->fsync_multiple_timeinterval = 3; 2357 priv->ieee80211->fsync_multiple_timeinterval = 3;
2664 priv->ieee80211->fsync_firstdiff_ratethreshold= 100; 2358 priv->ieee80211->fsync_firstdiff_ratethreshold= 100;
2665 priv->ieee80211->fsync_seconddiff_ratethreshold= 200; 2359 priv->ieee80211->fsync_seconddiff_ratethreshold= 200;
@@ -2741,20 +2435,12 @@ void dm_fsync_timer_callback(unsigned long data)
2741 priv->bswitch_fsync = !priv->bswitch_fsync; 2435 priv->bswitch_fsync = !priv->bswitch_fsync;
2742 if(priv->bswitch_fsync) 2436 if(priv->bswitch_fsync)
2743 { 2437 {
2744 #ifdef RTL8190P
2745 write_nic_byte(priv,0xC36, 0x00);
2746 #else
2747 write_nic_byte(priv,0xC36, 0x1c); 2438 write_nic_byte(priv,0xC36, 0x1c);
2748 #endif
2749 write_nic_byte(priv, 0xC3e, 0x90); 2439 write_nic_byte(priv, 0xC3e, 0x90);
2750 } 2440 }
2751 else 2441 else
2752 { 2442 {
2753 #ifdef RTL8190P
2754 write_nic_byte(priv, 0xC36, 0x40);
2755 #else
2756 write_nic_byte(priv, 0xC36, 0x5c); 2443 write_nic_byte(priv, 0xC36, 0x5c);
2757 #endif
2758 write_nic_byte(priv, 0xC3e, 0x96); 2444 write_nic_byte(priv, 0xC3e, 0x96);
2759 } 2445 }
2760 } 2446 }
@@ -2763,11 +2449,7 @@ void dm_fsync_timer_callback(unsigned long data)
2763 if(priv->bswitch_fsync) 2449 if(priv->bswitch_fsync)
2764 { 2450 {
2765 priv->bswitch_fsync = false; 2451 priv->bswitch_fsync = false;
2766 #ifdef RTL8190P
2767 write_nic_byte(priv, 0xC36, 0x40);
2768 #else
2769 write_nic_byte(priv, 0xC36, 0x5c); 2452 write_nic_byte(priv, 0xC36, 0x5c);
2770 #endif
2771 write_nic_byte(priv, 0xC3e, 0x96); 2453 write_nic_byte(priv, 0xC3e, 0x96);
2772 } 2454 }
2773 } 2455 }
@@ -2790,19 +2472,11 @@ void dm_fsync_timer_callback(unsigned long data)
2790 if(priv->bswitch_fsync) 2472 if(priv->bswitch_fsync)
2791 { 2473 {
2792 priv->bswitch_fsync = false; 2474 priv->bswitch_fsync = false;
2793 #ifdef RTL8190P
2794 write_nic_byte(priv, 0xC36, 0x40);
2795 #else
2796 write_nic_byte(priv, 0xC36, 0x5c); 2475 write_nic_byte(priv, 0xC36, 0x5c);
2797 #endif
2798 write_nic_byte(priv, 0xC3e, 0x96); 2476 write_nic_byte(priv, 0xC3e, 0x96);
2799 } 2477 }
2800 priv->ContiuneDiffCount = 0; 2478 priv->ContiuneDiffCount = 0;
2801 #ifdef RTL8190P
2802 write_nic_dword(priv, rOFDM0_RxDetector2, 0x164052cd);
2803 #else
2804 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd); 2479 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
2805 #endif
2806 } 2480 }
2807 RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount); 2481 RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
2808 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync); 2482 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
@@ -2829,20 +2503,14 @@ static void dm_EndSWFsync(struct net_device *dev)
2829 { 2503 {
2830 priv->bswitch_fsync = false; 2504 priv->bswitch_fsync = false;
2831 2505
2832 #ifdef RTL8190P 2506 write_nic_byte(priv, 0xC36, 0x40);
2833 write_nic_byte(priv, 0xC36, 0x40);
2834 #else
2835 write_nic_byte(priv, 0xC36, 0x5c);
2836#endif
2837 2507
2838 write_nic_byte(priv, 0xC3e, 0x96); 2508 write_nic_byte(priv, 0xC3e, 0x96);
2839 } 2509 }
2840 2510
2841 priv->ContiuneDiffCount = 0; 2511 priv->ContiuneDiffCount = 0;
2842#ifndef RTL8190P
2843 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
2844#endif
2845 2512
2513 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
2846} 2514}
2847 2515
2848static void dm_StartSWFsync(struct net_device *dev) 2516static void dm_StartSWFsync(struct net_device *dev)
@@ -2880,10 +2548,7 @@ static void dm_StartSWFsync(struct net_device *dev)
2880 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval); 2548 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
2881 add_timer(&priv->fsync_timer); 2549 add_timer(&priv->fsync_timer);
2882 2550
2883#ifndef RTL8190P
2884 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c12cd); 2551 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c12cd);
2885#endif
2886
2887} 2552}
2888 2553
2889static void dm_EndHWFsync(struct net_device *dev) 2554static void dm_EndHWFsync(struct net_device *dev)
@@ -2952,11 +2617,7 @@ void dm_check_fsync(struct net_device *dev)
2952 { 2617 {
2953 if(reg_c38_State != RegC38_Fsync_AP_BCM) 2618 if(reg_c38_State != RegC38_Fsync_AP_BCM)
2954 { //For broadcom AP we write different default value 2619 { //For broadcom AP we write different default value
2955 #ifdef RTL8190P 2620 write_nic_byte(priv, rOFDM0_RxDetector3, 0x95);
2956 write_nic_byte(priv, rOFDM0_RxDetector3, 0x15);
2957 #else
2958 write_nic_byte(priv, rOFDM0_RxDetector3, 0x95);
2959 #endif
2960 2621
2961 reg_c38_State = RegC38_Fsync_AP_BCM; 2622 reg_c38_State = RegC38_Fsync_AP_BCM;
2962 } 2623 }
@@ -2987,11 +2648,7 @@ void dm_check_fsync(struct net_device *dev)
2987 { 2648 {
2988 if(reg_c38_State != RegC38_NonFsync_Other_AP) 2649 if(reg_c38_State != RegC38_NonFsync_Other_AP)
2989 { 2650 {
2990 #ifdef RTL8190P 2651 write_nic_byte(priv, rOFDM0_RxDetector3, 0x90);
2991 write_nic_byte(priv, rOFDM0_RxDetector3, 0x10);
2992 #else
2993 write_nic_byte(priv, rOFDM0_RxDetector3, 0x90);
2994 #endif
2995 2652
2996 reg_c38_State = RegC38_NonFsync_Other_AP; 2653 reg_c38_State = RegC38_NonFsync_Other_AP;
2997 } 2654 }
diff --git a/drivers/staging/rtl8192e/r8192E_hw.h b/drivers/staging/rtl8192e/r8192E_hw.h
index 346bfb18e2b..7c1cd5d1867 100644
--- a/drivers/staging/rtl8192e/r8192E_hw.h
+++ b/drivers/staging/rtl8192e/r8192E_hw.h
@@ -95,27 +95,13 @@ typedef enum _RT_RF_TYPE_819xU{
95#define EEPROM_Default_TxPower 0x1010 95#define EEPROM_Default_TxPower 0x1010
96#define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChannelPlan, 0x7D:IC_Version 96#define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChannelPlan, 0x7D:IC_Version
97#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID 97#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID
98#ifdef RTL8190P 98
99#define EEPROM_RFInd_PowerDiff 0x14
100#define EEPROM_ThermalMeter 0x15
101#define EEPROM_TxPwDiff_CrystalCap 0x16
102#define EEPROM_TxPwIndex_CCK 0x18 //0x18~0x25
103#define EEPROM_TxPwIndex_OFDM_24G 0x26 //0x26~0x33
104#define EEPROM_TxPwIndex_OFDM_5G 0x34 //0x34~0x7B
105#define EEPROM_C56_CrystalCap 0x17 //0x17
106#define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex 0x80 //0x80
107#define EEPROM_C56_RfA_HT_OFDM_TxPwIndex 0x81 //0x81~0x83
108#define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex 0xbc //0xb8
109#define EEPROM_C56_RfC_HT_OFDM_TxPwIndex 0xb9 //0xb9~0xbb
110#else
111#ifdef RTL8192E
112#define EEPROM_RFInd_PowerDiff 0x28 99#define EEPROM_RFInd_PowerDiff 0x28
113#define EEPROM_ThermalMeter 0x29 100#define EEPROM_ThermalMeter 0x29
114#define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B 101#define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B
115#define EEPROM_TxPwIndex_CCK 0x2C //0x23 102#define EEPROM_TxPwIndex_CCK 0x2C //0x23
116#define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x24~0x26 103#define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x24~0x26
117#endif 104
118#endif
119#define EEPROM_Default_TxPowerLevel 0x10 105#define EEPROM_Default_TxPowerLevel 0x10
120//#define EEPROM_ChannelPlan 0x7c //0x7C 106//#define EEPROM_ChannelPlan 0x7c //0x7C
121#define EEPROM_IC_VER 0x7d //0x7D 107#define EEPROM_IC_VER 0x7d //0x7D
diff --git a/drivers/staging/rtl8192e/r8192_pm.c b/drivers/staging/rtl8192e/r8192_pm.c
index 8781735d5a3..5679c8ba370 100644
--- a/drivers/staging/rtl8192e/r8192_pm.c
+++ b/drivers/staging/rtl8192e/r8192_pm.c
@@ -25,9 +25,6 @@ int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state)
25{ 25{
26 struct net_device *dev = pci_get_drvdata(pdev); 26 struct net_device *dev = pci_get_drvdata(pdev);
27 struct r8192_priv *priv = ieee80211_priv(dev); 27 struct r8192_priv *priv = ieee80211_priv(dev);
28#ifdef RTL8190P
29 u8 ucRegRead;
30#endif
31 u32 ulRegRead; 28 u32 ulRegRead;
32 29
33 RT_TRACE(COMP_POWER, "============> r8192E suspend call.\n"); 30 RT_TRACE(COMP_POWER, "============> r8192E suspend call.\n");
@@ -49,12 +46,6 @@ int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state)
49 write_nic_dword(priv, WFCRC0, 0xffffffff); 46 write_nic_dword(priv, WFCRC0, 0xffffffff);
50 write_nic_dword(priv, WFCRC1, 0xffffffff); 47 write_nic_dword(priv, WFCRC1, 0xffffffff);
51 write_nic_dword(priv, WFCRC2, 0xffffffff); 48 write_nic_dword(priv, WFCRC2, 0xffffffff);
52#ifdef RTL8190P
53 //GPIO 0 = TRUE
54 ucRegRead = read_nic_byte(priv, GPO);
55 ucRegRead |= BIT0;
56 write_nic_byte(priv, GPO, ucRegRead);
57#endif
58 //Write PMR register 49 //Write PMR register
59 write_nic_byte(priv, PMR, 0x5); 50 write_nic_byte(priv, PMR, 0x5);
60 //Disable tx, enanble rx 51 //Disable tx, enanble rx
diff --git a/drivers/staging/rtl8192e/r819xE_cmdpkt.c b/drivers/staging/rtl8192e/r819xE_cmdpkt.c
index 11ad7cf16f7..ef6f2deb304 100644
--- a/drivers/staging/rtl8192e/r819xE_cmdpkt.c
+++ b/drivers/staging/rtl8192e/r819xE_cmdpkt.c
@@ -40,9 +40,6 @@ RT_STATUS cmpk_message_handle_tx(
40{ 40{
41 41
42 RT_STATUS rt_status = RT_STATUS_SUCCESS; 42 RT_STATUS rt_status = RT_STATUS_SUCCESS;
43#ifdef RTL8192U
44 return rt_status;
45#else
46 struct r8192_priv *priv = ieee80211_priv(dev); 43 struct r8192_priv *priv = ieee80211_priv(dev);
47 u16 frag_threshold; 44 u16 frag_threshold;
48 u16 frag_length = 0, frag_offset = 0; 45 u16 frag_length = 0, frag_offset = 0;
@@ -74,11 +71,7 @@ RT_STATUS cmpk_message_handle_tx(
74 /* Allocate skb buffer to contain firmware info and tx descriptor info 71 /* Allocate skb buffer to contain firmware info and tx descriptor info
75 * add 4 to avoid packet appending overflow. 72 * add 4 to avoid packet appending overflow.
76 * */ 73 * */
77#ifdef RTL8192U
78 skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4);
79#else
80 skb = dev_alloc_skb(frag_length + priv->ieee80211->tx_headroom + 4); 74 skb = dev_alloc_skb(frag_length + priv->ieee80211->tx_headroom + 4);
81#endif
82 if(skb == NULL) { 75 if(skb == NULL) {
83 rt_status = RT_STATUS_FAILURE; 76 rt_status = RT_STATUS_FAILURE;
84 goto Failed; 77 goto Failed;
@@ -91,10 +84,6 @@ RT_STATUS cmpk_message_handle_tx(
91 tcb_desc->bLastIniPkt = bLastIniPkt; 84 tcb_desc->bLastIniPkt = bLastIniPkt;
92 tcb_desc->pkt_size = frag_length; 85 tcb_desc->pkt_size = frag_length;
93 86
94#ifdef RTL8192U
95 skb_reserve(skb, USB_HWDESC_HEADER_LEN);
96#endif
97
98 //seg_ptr = skb_put(skb, frag_length + priv->ieee80211->tx_headroom); 87 //seg_ptr = skb_put(skb, frag_length + priv->ieee80211->tx_headroom);
99 seg_ptr = skb_put(skb, priv->ieee80211->tx_headroom); 88 seg_ptr = skb_put(skb, priv->ieee80211->tx_headroom);
100 89
@@ -126,9 +115,6 @@ RT_STATUS cmpk_message_handle_tx(
126Failed: 115Failed:
127 //spin_unlock_irqrestore(&priv->tx_lock,flags); 116 //spin_unlock_irqrestore(&priv->tx_lock,flags);
128 return rt_status; 117 return rt_status;
129
130
131#endif
132} 118}
133 119
134static void 120static void
diff --git a/drivers/staging/rtl8192e/r819xE_phy.c b/drivers/staging/rtl8192e/r819xE_phy.c
index bcd1eda7795..a1312d8f751 100644
--- a/drivers/staging/rtl8192e/r819xE_phy.c
+++ b/drivers/staging/rtl8192e/r819xE_phy.c
@@ -24,839 +24,7 @@ static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
24 0x0e5c, //2472 13 24 0x0e5c, //2472 13
25 0x0f72, //2484 25 0x0f72, //2484
26}; 26};
27#ifdef RTL8190P
28u32 Rtl8190PciMACPHY_Array[] = {
290x03c,0xffff0000,0x00000f0f,
300x340,0xffffffff,0x161a1a1a,
310x344,0xffffffff,0x12121416,
320x348,0x0000ffff,0x00001818,
330x12c,0xffffffff,0x04000802,
340x318,0x00000fff,0x00000800,
35};
36u32 Rtl8190PciMACPHY_Array_PG[] = {
370x03c,0xffff0000,0x00000f0f,
380x340,0xffffffff,0x0a0c0d0f,
390x344,0xffffffff,0x06070809,
400x344,0xffffffff,0x06070809,
410x348,0x0000ffff,0x00000000,
420x12c,0xffffffff,0x04000802,
430x318,0x00000fff,0x00000800,
44};
45
46u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLength] = {
470xc78,0x7d000001,
480xc78,0x7d010001,
490xc78,0x7d020001,
500xc78,0x7d030001,
510xc78,0x7c040001,
520xc78,0x7b050001,
530xc78,0x7a060001,
540xc78,0x79070001,
550xc78,0x78080001,
560xc78,0x77090001,
570xc78,0x760a0001,
580xc78,0x750b0001,
590xc78,0x740c0001,
600xc78,0x730d0001,
610xc78,0x720e0001,
620xc78,0x710f0001,
630xc78,0x70100001,
640xc78,0x6f110001,
650xc78,0x6e120001,
660xc78,0x6d130001,
670xc78,0x6c140001,
680xc78,0x6b150001,
690xc78,0x6a160001,
700xc78,0x69170001,
710xc78,0x68180001,
720xc78,0x67190001,
730xc78,0x661a0001,
740xc78,0x651b0001,
750xc78,0x641c0001,
760xc78,0x491d0001,
770xc78,0x481e0001,
780xc78,0x471f0001,
790xc78,0x46200001,
800xc78,0x45210001,
810xc78,0x44220001,
820xc78,0x43230001,
830xc78,0x28240001,
840xc78,0x27250001,
850xc78,0x26260001,
860xc78,0x25270001,
870xc78,0x24280001,
880xc78,0x23290001,
890xc78,0x222a0001,
900xc78,0x212b0001,
910xc78,0x202c0001,
920xc78,0x0a2d0001,
930xc78,0x082e0001,
940xc78,0x062f0001,
950xc78,0x05300001,
960xc78,0x04310001,
970xc78,0x03320001,
980xc78,0x02330001,
990xc78,0x01340001,
1000xc78,0x00350001,
1010xc78,0x00360001,
1020xc78,0x00370001,
1030xc78,0x00380001,
1040xc78,0x00390001,
1050xc78,0x003a0001,
1060xc78,0x003b0001,
1070xc78,0x003c0001,
1080xc78,0x003d0001,
1090xc78,0x003e0001,
1100xc78,0x003f0001,
1110xc78,0x7d400001,
1120xc78,0x7d410001,
1130xc78,0x7d420001,
1140xc78,0x7d430001,
1150xc78,0x7c440001,
1160xc78,0x7b450001,
1170xc78,0x7a460001,
1180xc78,0x79470001,
1190xc78,0x78480001,
1200xc78,0x77490001,
1210xc78,0x764a0001,
1220xc78,0x754b0001,
1230xc78,0x744c0001,
1240xc78,0x734d0001,
1250xc78,0x724e0001,
1260xc78,0x714f0001,
1270xc78,0x70500001,
1280xc78,0x6f510001,
1290xc78,0x6e520001,
1300xc78,0x6d530001,
1310xc78,0x6c540001,
1320xc78,0x6b550001,
1330xc78,0x6a560001,
1340xc78,0x69570001,
1350xc78,0x68580001,
1360xc78,0x67590001,
1370xc78,0x665a0001,
1380xc78,0x655b0001,
1390xc78,0x645c0001,
1400xc78,0x495d0001,
1410xc78,0x485e0001,
1420xc78,0x475f0001,
1430xc78,0x46600001,
1440xc78,0x45610001,
1450xc78,0x44620001,
1460xc78,0x43630001,
1470xc78,0x28640001,
1480xc78,0x27650001,
1490xc78,0x26660001,
1500xc78,0x25670001,
1510xc78,0x24680001,
1520xc78,0x23690001,
1530xc78,0x226a0001,
1540xc78,0x216b0001,
1550xc78,0x206c0001,
1560xc78,0x0a6d0001,
1570xc78,0x086e0001,
1580xc78,0x066f0001,
1590xc78,0x05700001,
1600xc78,0x04710001,
1610xc78,0x03720001,
1620xc78,0x02730001,
1630xc78,0x01740001,
1640xc78,0x00750001,
1650xc78,0x00760001,
1660xc78,0x00770001,
1670xc78,0x00780001,
1680xc78,0x00790001,
1690xc78,0x007a0001,
1700xc78,0x007b0001,
1710xc78,0x007c0001,
1720xc78,0x007d0001,
1730xc78,0x007e0001,
1740xc78,0x007f0001,
1750xc78,0x3600001e,
1760xc78,0x3601001e,
1770xc78,0x3602001e,
1780xc78,0x3603001e,
1790xc78,0x3604001e,
1800xc78,0x3605001e,
1810xc78,0x3a06001e,
1820xc78,0x3c07001e,
1830xc78,0x3e08001e,
1840xc78,0x4209001e,
1850xc78,0x430a001e,
1860xc78,0x450b001e,
1870xc78,0x470c001e,
1880xc78,0x480d001e,
1890xc78,0x490e001e,
1900xc78,0x4b0f001e,
1910xc78,0x4c10001e,
1920xc78,0x4d11001e,
1930xc78,0x4d12001e,
1940xc78,0x4e13001e,
1950xc78,0x4f14001e,
1960xc78,0x5015001e,
1970xc78,0x5116001e,
1980xc78,0x5117001e,
1990xc78,0x5218001e,
2000xc78,0x5219001e,
2010xc78,0x531a001e,
2020xc78,0x541b001e,
2030xc78,0x541c001e,
2040xc78,0x551d001e,
2050xc78,0x561e001e,
2060xc78,0x561f001e,
2070xc78,0x5720001e,
2080xc78,0x5821001e,
2090xc78,0x5822001e,
2100xc78,0x5923001e,
2110xc78,0x5924001e,
2120xc78,0x5a25001e,
2130xc78,0x5b26001e,
2140xc78,0x5b27001e,
2150xc78,0x5c28001e,
2160xc78,0x5c29001e,
2170xc78,0x5d2a001e,
2180xc78,0x5d2b001e,
2190xc78,0x5e2c001e,
2200xc78,0x5e2d001e,
2210xc78,0x5f2e001e,
2220xc78,0x602f001e,
2230xc78,0x6030001e,
2240xc78,0x6131001e,
2250xc78,0x6132001e,
2260xc78,0x6233001e,
2270xc78,0x6234001e,
2280xc78,0x6335001e,
2290xc78,0x6336001e,
2300xc78,0x6437001e,
2310xc78,0x6538001e,
2320xc78,0x6639001e,
2330xc78,0x663a001e,
2340xc78,0x673b001e,
2350xc78,0x683c001e,
2360xc78,0x693d001e,
2370xc78,0x6a3e001e,
2380xc78,0x6b3f001e,
239};
240
241u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLength] = {
2420x800,0x00050060,
2430x804,0x00000005,
2440x808,0x0000fc00,
2450x80c,0x0000001c,
2460x810,0x801010aa,
2470x814,0x000908c0,
2480x818,0x00000000,
2490x81c,0x00000000,
2500x820,0x00000004,
2510x824,0x00690000,
2520x828,0x00000004,
2530x82c,0x00e90000,
2540x830,0x00000004,
2550x834,0x00690000,
2560x838,0x00000004,
2570x83c,0x00e90000,
2580x840,0x00000000,
2590x844,0x00000000,
2600x848,0x00000000,
2610x84c,0x00000000,
2620x850,0x00000000,
2630x854,0x00000000,
2640x858,0x65a965a9,
2650x85c,0x65a965a9,
2660x860,0x001f0010,
2670x864,0x007f0010,
2680x868,0x001f0010,
2690x86c,0x007f0010,
2700x870,0x0f100f70,
2710x874,0x0f100f70,
2720x878,0x00000000,
2730x87c,0x00000000,
2740x880,0x5c385eb8,
2750x884,0x6357060d,
2760x888,0x0460c341,
2770x88c,0x0000ff00,
2780x890,0x00000000,
2790x894,0xfffffffe,
2800x898,0x4c42382f,
2810x89c,0x00656056,
2820x8b0,0x00000000,
2830x8e0,0x00000000,
2840x8e4,0x00000000,
2850x900,0x00000000,
2860x904,0x00000023,
2870x908,0x00000000,
2880x90c,0x35541545,
2890xa00,0x00d0c7d8,
2900xa04,0xab1f0008,
2910xa08,0x80cd8300,
2920xa0c,0x2e62740f,
2930xa10,0x95009b78,
2940xa14,0x11145008,
2950xa18,0x00881117,
2960xa1c,0x89140fa0,
2970xa20,0x1a1b0000,
2980xa24,0x090e1317,
2990xa28,0x00000204,
3000xa2c,0x00000000,
3010xc00,0x00000040,
3020xc04,0x0000500f,
3030xc08,0x000000e4,
3040xc0c,0x6c6c6c6c,
3050xc10,0x08000000,
3060xc14,0x40000100,
3070xc18,0x08000000,
3080xc1c,0x40000100,
3090xc20,0x08000000,
3100xc24,0x40000100,
3110xc28,0x08000000,
3120xc2c,0x40000100,
3130xc30,0x6de9ac44,
3140xc34,0x164052cd,
3150xc38,0x00070a14,
3160xc3c,0x0a969764,
3170xc40,0x1f7c403f,
3180xc44,0x000100b7,
3190xc48,0xec020000,
3200xc4c,0x00000300,
3210xc50,0x69543420,
3220xc54,0x433c0094,
3230xc58,0x69543420,
3240xc5c,0x433c0094,
3250xc60,0x69543420,
3260xc64,0x433c0094,
3270xc68,0x69543420,
3280xc6c,0x433c0094,
3290xc70,0x2c7f000d,
3300xc74,0x0186175b,
3310xc78,0x0000001f,
3320xc7c,0x00b91612,
3330xc80,0x40000100,
3340xc84,0x00000000,
3350xc88,0x40000100,
3360xc8c,0x08000000,
3370xc90,0x40000100,
3380xc94,0x00000000,
3390xc98,0x40000100,
3400xc9c,0x00000000,
3410xca0,0x00492492,
3420xca4,0x00000000,
3430xca8,0x00000000,
3440xcac,0x00000000,
3450xcb0,0x00000000,
3460xcb4,0x00000000,
3470xcb8,0x00000000,
3480xcbc,0x00492492,
3490xcc0,0x00000000,
3500xcc4,0x00000000,
3510xcc8,0x00000000,
3520xccc,0x00000000,
3530xcd0,0x00000000,
3540xcd4,0x00000000,
3550xcd8,0x64b22427,
3560xcdc,0x00766932,
3570xce0,0x00222222,
3580xd00,0x00000740,
3590xd04,0x0000040f,
3600xd08,0x0000803f,
3610xd0c,0x00000001,
3620xd10,0xa0633333,
3630xd14,0x33333c63,
3640xd18,0x6a8f5b6b,
3650xd1c,0x00000000,
3660xd20,0x00000000,
3670xd24,0x00000000,
3680xd28,0x00000000,
3690xd2c,0xcc979975,
3700xd30,0x00000000,
3710xd34,0x00000000,
3720xd38,0x00000000,
3730xd3c,0x00027293,
3740xd40,0x00000000,
3750xd44,0x00000000,
3760xd48,0x00000000,
3770xd4c,0x00000000,
3780xd50,0x6437140a,
3790xd54,0x024dbd02,
3800xd58,0x00000000,
3810xd5c,0x14032064,
382};
383u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
3840x800,0x00050060,
3850x804,0x00000004,
3860x808,0x0000fc00,
3870x80c,0x0000001c,
3880x810,0x801010aa,
3890x814,0x000908c0,
3900x818,0x00000000,
3910x81c,0x00000000,
3920x820,0x00000004,
3930x824,0x00690000,
3940x828,0x00000004,
3950x82c,0x00e90000,
3960x830,0x00000004,
3970x834,0x00690000,
3980x838,0x00000004,
3990x83c,0x00e90000,
4000x840,0x00000000,
4010x844,0x00000000,
4020x848,0x00000000,
4030x84c,0x00000000,
4040x850,0x00000000,
4050x854,0x00000000,
4060x858,0x65a965a9,
4070x85c,0x65a965a9,
4080x860,0x001f0000,
4090x864,0x007f0000,
4100x868,0x001f0010,
4110x86c,0x007f0010,
4120x870,0x0f100f70,
4130x874,0x0f100f70,
4140x878,0x00000000,
4150x87c,0x00000000,
4160x880,0x5c385898,
4170x884,0x6357060d,
4180x888,0x0460c341,
4190x88c,0x0000fc00,
4200x890,0x00000000,
4210x894,0xfffffffe,
4220x898,0x4c42382f,
4230x89c,0x00656056,
4240x8b0,0x00000000,
4250x8e0,0x00000000,
4260x8e4,0x00000000,
4270x900,0x00000000,
4280x904,0x00000023,
4290x908,0x00000000,
4300x90c,0x34441444,
4310xa00,0x00d0c7d8,
4320xa04,0x2b1f0008,
4330xa08,0x80cd8300,
4340xa0c,0x2e62740f,
4350xa10,0x95009b78,
4360xa14,0x11145008,
4370xa18,0x00881117,
4380xa1c,0x89140fa0,
4390xa20,0x1a1b0000,
4400xa24,0x090e1317,
4410xa28,0x00000204,
4420xa2c,0x00000000,
4430xc00,0x00000040,
4440xc04,0x0000500c,
4450xc08,0x000000e4,
4460xc0c,0x6c6c6c6c,
4470xc10,0x08000000,
4480xc14,0x40000100,
4490xc18,0x08000000,
4500xc1c,0x40000100,
4510xc20,0x08000000,
4520xc24,0x40000100,
4530xc28,0x08000000,
4540xc2c,0x40000100,
4550xc30,0x6de9ac44,
4560xc34,0x164052cd,
4570xc38,0x00070a14,
4580xc3c,0x0a969764,
4590xc40,0x1f7c403f,
4600xc44,0x000100b7,
4610xc48,0xec020000,
4620xc4c,0x00000300,
4630xc50,0x69543420,
4640xc54,0x433c0094,
4650xc58,0x69543420,
4660xc5c,0x433c0094,
4670xc60,0x69543420,
4680xc64,0x433c0094,
4690xc68,0x69543420,
4700xc6c,0x433c0094,
4710xc70,0x2c7f000d,
4720xc74,0x0186175b,
4730xc78,0x0000001f,
4740xc7c,0x00b91612,
4750xc80,0x40000100,
4760xc84,0x00000000,
4770xc88,0x40000100,
4780xc8c,0x08000000,
4790xc90,0x40000100,
4800xc94,0x00000000,
4810xc98,0x40000100,
4820xc9c,0x00000000,
4830xca0,0x00492492,
4840xca4,0x00000000,
4850xca8,0x00000000,
4860xcac,0x00000000,
4870xcb0,0x00000000,
4880xcb4,0x00000000,
4890xcb8,0x00000000,
4900xcbc,0x00492492,
4910xcc0,0x00000000,
4920xcc4,0x00000000,
4930xcc8,0x00000000,
4940xccc,0x00000000,
4950xcd0,0x00000000,
4960xcd4,0x00000000,
4970xcd8,0x64b22427,
4980xcdc,0x00766932,
4990xce0,0x00222222,
5000xd00,0x00000740,
5010xd04,0x0000040c,
5020xd08,0x0000803f,
5030xd0c,0x00000001,
5040xd10,0xa0633333,
5050xd14,0x33333c63,
5060xd18,0x6a8f5b6b,
5070xd1c,0x00000000,
5080xd20,0x00000000,
5090xd24,0x00000000,
5100xd28,0x00000000,
5110xd2c,0xcc979975,
5120xd30,0x00000000,
5130xd34,0x00000000,
5140xd38,0x00000000,
5150xd3c,0x00027293,
5160xd40,0x00000000,
5170xd44,0x00000000,
5180xd48,0x00000000,
5190xd4c,0x00000000,
5200xd50,0x6437140a,
5210xd54,0x024dbd02,
5220xd58,0x00000000,
5230xd5c,0x14032064,
524};
525 27
526u32 Rtl8190PciRadioA_Array[RadioA_ArrayLength] = {
5270x019,0x00000003,
5280x000,0x000000bf,
5290x001,0x00000ee0,
5300x002,0x0000004c,
5310x003,0x000007f1,
5320x004,0x00000975,
5330x005,0x00000c58,
5340x006,0x00000ae6,
5350x007,0x000000ca,
5360x008,0x00000e1c,
5370x009,0x000007f0,
5380x00a,0x000009d0,
5390x00b,0x000001ba,
5400x00c,0x00000240,
5410x00e,0x00000020,
5420x00f,0x00000990,
5430x012,0x00000806,
5440x014,0x000005ab,
5450x015,0x00000f80,
5460x016,0x00000020,
5470x017,0x00000597,
5480x018,0x0000050a,
5490x01a,0x00000f80,
5500x01b,0x00000f5e,
5510x01c,0x00000008,
5520x01d,0x00000607,
5530x01e,0x000006cc,
5540x01f,0x00000000,
5550x020,0x000001a5,
5560x01f,0x00000001,
5570x020,0x00000165,
5580x01f,0x00000002,
5590x020,0x000000c6,
5600x01f,0x00000003,
5610x020,0x00000086,
5620x01f,0x00000004,
5630x020,0x00000046,
5640x01f,0x00000005,
5650x020,0x000001e6,
5660x01f,0x00000006,
5670x020,0x000001a6,
5680x01f,0x00000007,
5690x020,0x00000166,
5700x01f,0x00000008,
5710x020,0x000000c7,
5720x01f,0x00000009,
5730x020,0x00000087,
5740x01f,0x0000000a,
5750x020,0x000000f7,
5760x01f,0x0000000b,
5770x020,0x000000d7,
5780x01f,0x0000000c,
5790x020,0x000000b7,
5800x01f,0x0000000d,
5810x020,0x00000097,
5820x01f,0x0000000e,
5830x020,0x00000077,
5840x01f,0x0000000f,
5850x020,0x00000057,
5860x01f,0x00000010,
5870x020,0x00000037,
5880x01f,0x00000011,
5890x020,0x000000fb,
5900x01f,0x00000012,
5910x020,0x000000db,
5920x01f,0x00000013,
5930x020,0x000000bb,
5940x01f,0x00000014,
5950x020,0x000000ff,
5960x01f,0x00000015,
5970x020,0x000000e3,
5980x01f,0x00000016,
5990x020,0x000000c3,
6000x01f,0x00000017,
6010x020,0x000000a3,
6020x01f,0x00000018,
6030x020,0x00000083,
6040x01f,0x00000019,
6050x020,0x00000063,
6060x01f,0x0000001a,
6070x020,0x00000043,
6080x01f,0x0000001b,
6090x020,0x00000023,
6100x01f,0x0000001c,
6110x020,0x00000003,
6120x01f,0x0000001d,
6130x020,0x000001e3,
6140x01f,0x0000001e,
6150x020,0x000001c3,
6160x01f,0x0000001f,
6170x020,0x000001a3,
6180x01f,0x00000020,
6190x020,0x00000183,
6200x01f,0x00000021,
6210x020,0x00000163,
6220x01f,0x00000022,
6230x020,0x00000143,
6240x01f,0x00000023,
6250x020,0x00000123,
6260x01f,0x00000024,
6270x020,0x00000103,
6280x023,0x00000203,
6290x024,0x00000200,
6300x00b,0x000001ba,
6310x02c,0x000003d7,
6320x02d,0x00000ff0,
6330x000,0x00000037,
6340x004,0x00000160,
6350x007,0x00000080,
6360x002,0x0000088d,
6370x0fe,0x00000000,
6380x0fe,0x00000000,
6390x016,0x00000200,
6400x016,0x00000380,
6410x016,0x00000020,
6420x016,0x000001a0,
6430x000,0x000000bf,
6440x00d,0x0000001f,
6450x00d,0x00000c9f,
6460x002,0x0000004d,
6470x000,0x00000cbf,
6480x004,0x00000975,
6490x007,0x00000700,
650};
651u32 Rtl8190PciRadioB_Array[RadioB_ArrayLength] = {
6520x019,0x00000003,
6530x000,0x000000bf,
6540x001,0x000006e0,
6550x002,0x0000004c,
6560x003,0x000007f1,
6570x004,0x00000975,
6580x005,0x00000c58,
6590x006,0x00000ae6,
6600x007,0x000000ca,
6610x008,0x00000e1c,
6620x000,0x000000b7,
6630x00a,0x00000850,
6640x000,0x000000bf,
6650x00b,0x000001ba,
6660x00c,0x00000240,
6670x00e,0x00000020,
6680x015,0x00000f80,
6690x016,0x00000020,
6700x017,0x00000597,
6710x018,0x0000050a,
6720x01a,0x00000e00,
6730x01b,0x00000f5e,
6740x01d,0x00000607,
6750x01e,0x000006cc,
6760x00b,0x000001ba,
6770x023,0x00000203,
6780x024,0x00000200,
6790x000,0x00000037,
6800x004,0x00000160,
6810x016,0x00000200,
6820x016,0x00000380,
6830x016,0x00000020,
6840x016,0x000001a0,
6850x00d,0x00000ccc,
6860x000,0x000000bf,
6870x002,0x0000004d,
6880x000,0x00000cbf,
6890x004,0x00000975,
6900x007,0x00000700,
691};
692u32 Rtl8190PciRadioC_Array[RadioC_ArrayLength] = {
6930x019,0x00000003,
6940x000,0x000000bf,
6950x001,0x00000ee0,
6960x002,0x0000004c,
6970x003,0x000007f1,
6980x004,0x00000975,
6990x005,0x00000c58,
7000x006,0x00000ae6,
7010x007,0x000000ca,
7020x008,0x00000e1c,
7030x009,0x000007f0,
7040x00a,0x000009d0,
7050x00b,0x000001ba,
7060x00c,0x00000240,
7070x00e,0x00000020,
7080x00f,0x00000990,
7090x012,0x00000806,
7100x014,0x000005ab,
7110x015,0x00000f80,
7120x016,0x00000020,
7130x017,0x00000597,
7140x018,0x0000050a,
7150x01a,0x00000f80,
7160x01b,0x00000f5e,
7170x01c,0x00000008,
7180x01d,0x00000607,
7190x01e,0x000006cc,
7200x01f,0x00000000,
7210x020,0x000001a5,
7220x01f,0x00000001,
7230x020,0x00000165,
7240x01f,0x00000002,
7250x020,0x000000c6,
7260x01f,0x00000003,
7270x020,0x00000086,
7280x01f,0x00000004,
7290x020,0x00000046,
7300x01f,0x00000005,
7310x020,0x000001e6,
7320x01f,0x00000006,
7330x020,0x000001a6,
7340x01f,0x00000007,
7350x020,0x00000166,
7360x01f,0x00000008,
7370x020,0x000000c7,
7380x01f,0x00000009,
7390x020,0x00000087,
7400x01f,0x0000000a,
7410x020,0x000000f7,
7420x01f,0x0000000b,
7430x020,0x000000d7,
7440x01f,0x0000000c,
7450x020,0x000000b7,
7460x01f,0x0000000d,
7470x020,0x00000097,
7480x01f,0x0000000e,
7490x020,0x00000077,
7500x01f,0x0000000f,
7510x020,0x00000057,
7520x01f,0x00000010,
7530x020,0x00000037,
7540x01f,0x00000011,
7550x020,0x000000fb,
7560x01f,0x00000012,
7570x020,0x000000db,
7580x01f,0x00000013,
7590x020,0x000000bb,
7600x01f,0x00000014,
7610x020,0x000000ff,
7620x01f,0x00000015,
7630x020,0x000000e3,
7640x01f,0x00000016,
7650x020,0x000000c3,
7660x01f,0x00000017,
7670x020,0x000000a3,
7680x01f,0x00000018,
7690x020,0x00000083,
7700x01f,0x00000019,
7710x020,0x00000063,
7720x01f,0x0000001a,
7730x020,0x00000043,
7740x01f,0x0000001b,
7750x020,0x00000023,
7760x01f,0x0000001c,
7770x020,0x00000003,
7780x01f,0x0000001d,
7790x020,0x000001e3,
7800x01f,0x0000001e,
7810x020,0x000001c3,
7820x01f,0x0000001f,
7830x020,0x000001a3,
7840x01f,0x00000020,
7850x020,0x00000183,
7860x01f,0x00000021,
7870x020,0x00000163,
7880x01f,0x00000022,
7890x020,0x00000143,
7900x01f,0x00000023,
7910x020,0x00000123,
7920x01f,0x00000024,
7930x020,0x00000103,
7940x023,0x00000203,
7950x024,0x00000200,
7960x00b,0x000001ba,
7970x02c,0x000003d7,
7980x02d,0x00000ff0,
7990x000,0x00000037,
8000x004,0x00000160,
8010x007,0x00000080,
8020x002,0x0000088d,
8030x0fe,0x00000000,
8040x0fe,0x00000000,
8050x016,0x00000200,
8060x016,0x00000380,
8070x016,0x00000020,
8080x016,0x000001a0,
8090x000,0x000000bf,
8100x00d,0x0000001f,
8110x00d,0x00000c9f,
8120x002,0x0000004d,
8130x000,0x00000cbf,
8140x004,0x00000975,
8150x007,0x00000700,
816};
817u32 Rtl8190PciRadioD_Array[RadioD_ArrayLength] = {
8180x019,0x00000003,
8190x000,0x000000bf,
8200x001,0x000006e0,
8210x002,0x0000004c,
8220x003,0x000007f1,
8230x004,0x00000975,
8240x005,0x00000c58,
8250x006,0x00000ae6,
8260x007,0x000000ca,
8270x008,0x00000e1c,
8280x000,0x000000b7,
8290x00a,0x00000850,
8300x000,0x000000bf,
8310x00b,0x000001ba,
8320x00c,0x00000240,
8330x00e,0x00000020,
8340x015,0x00000f80,
8350x016,0x00000020,
8360x017,0x00000597,
8370x018,0x0000050a,
8380x01a,0x00000e00,
8390x01b,0x00000f5e,
8400x01d,0x00000607,
8410x01e,0x000006cc,
8420x00b,0x000001ba,
8430x023,0x00000203,
8440x024,0x00000200,
8450x000,0x00000037,
8460x004,0x00000160,
8470x016,0x00000200,
8480x016,0x00000380,
8490x016,0x00000020,
8500x016,0x000001a0,
8510x00d,0x00000ccc,
8520x000,0x000000bf,
8530x002,0x0000004d,
8540x000,0x00000cbf,
8550x004,0x00000975,
8560x007,0x00000700,
857};
858#endif
859#ifdef RTL8192E
860static u32 Rtl8192PciEMACPHY_Array[] = { 28static u32 Rtl8192PciEMACPHY_Array[] = {
8610x03c,0xffff0000,0x00000f0f, 290x03c,0xffff0000,0x00000f0f,
8620x340,0xffffffff,0x161a1a1a, 300x340,0xffffffff,0x161a1a1a,
@@ -1393,7 +561,6 @@ static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
13930x0, }; 5610x0, };
1394static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = { 562static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
13950x0, }; 5630x0, };
1396#endif
1397 564
1398/*************************Define local function prototype**********************/ 565/*************************Define local function prototype**********************/
1399 566
@@ -1427,20 +594,7 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
1427{ 594{
1428 u8 ret = 1; 595 u8 ret = 1;
1429 struct r8192_priv *priv = ieee80211_priv(dev); 596 struct r8192_priv *priv = ieee80211_priv(dev);
1430#ifdef RTL8190P 597
1431 if(priv->rf_type == RF_2T4R)
1432 {
1433 ret= 1;
1434 }
1435 else if (priv->rf_type == RF_1T2R)
1436 {
1437 if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1438 ret = 0;
1439 else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1440 ret = 1;
1441 }
1442#else
1443 #ifdef RTL8192E
1444 if (priv->rf_type == RF_2T4R) 598 if (priv->rf_type == RF_2T4R)
1445 ret = 0; 599 ret = 0;
1446 else if (priv->rf_type == RF_1T2R) 600 else if (priv->rf_type == RF_1T2R)
@@ -1450,8 +604,7 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
1450 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) 604 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1451 ret = 0; 605 ret = 0;
1452 } 606 }
1453 #endif 607
1454#endif
1455 return ret; 608 return ret;
1456} 609}
1457/****************************************************************************** 610/******************************************************************************
@@ -1518,15 +671,8 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eR
1518 //switch page for 8256 RF IC 671 //switch page for 8256 RF IC
1519 if (priv->rf_chip == RF_8256) 672 if (priv->rf_chip == RF_8256)
1520 { 673 {
1521#ifdef RTL8190P
1522 //analog to digital off, for protection
1523 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1524#else
1525 #ifdef RTL8192E
1526 //analog to digital off, for protection 674 //analog to digital off, for protection
1527 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] 675 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1528 #endif
1529#endif
1530 if (Offset >= 31) 676 if (Offset >= 31)
1531 { 677 {
1532 priv->RfReg0Value[eRFPath] |= 0x140; 678 priv->RfReg0Value[eRFPath] |= 0x140;
@@ -1577,23 +723,8 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eR
1577 bMaskDWord, 723 bMaskDWord,
1578 (priv->RfReg0Value[eRFPath] << 16)); 724 (priv->RfReg0Value[eRFPath] << 16));
1579 725
1580#ifdef RTL8190P
1581 if(priv->rf_type == RF_2T4R)
1582 {
1583 //analog to digital on
1584 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1585 }
1586 else if(priv->rf_type == RF_1T2R)
1587 {
1588 //analog to digital on
1589 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1590 }
1591#else
1592 #ifdef RTL8192E
1593 //analog to digital on 726 //analog to digital on
1594 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] 727 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1595 #endif
1596#endif
1597 } 728 }
1598 729
1599 730
@@ -1631,15 +762,8 @@ static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E
1631 if (priv->rf_chip == RF_8256) 762 if (priv->rf_chip == RF_8256)
1632 { 763 {
1633 764
1634#ifdef RTL8190P
1635 //analog to digital off, for protection 765 //analog to digital off, for protection
1636 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] 766 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1637#else
1638 #ifdef RTL8192E
1639 //analog to digital off, for protection
1640 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1641 #endif
1642#endif
1643 767
1644 if (Offset >= 31) 768 if (Offset >= 31)
1645 { 769 {
@@ -1685,23 +809,8 @@ static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E
1685 bMaskDWord, 809 bMaskDWord,
1686 (priv->RfReg0Value[eRFPath] << 16)); 810 (priv->RfReg0Value[eRFPath] << 16));
1687 } 811 }
1688#ifdef RTL8190P
1689 if(priv->rf_type == RF_2T4R)
1690 {
1691 //analog to digital on
1692 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1693 }
1694 else if(priv->rf_type == RF_1T2R)
1695 {
1696 //analog to digital on
1697 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1698 }
1699#else
1700 #ifdef RTL8192E
1701 //analog to digital on 812 //analog to digital on
1702 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] 813 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1703 #endif
1704#endif
1705 } 814 }
1706} 815}
1707 816
@@ -1724,10 +833,8 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
1724 833
1725 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 834 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1726 return; 835 return;
1727#ifdef RTL8192E
1728 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter) 836 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1729 return; 837 return;
1730#endif
1731 //down(&priv->rf_sem); 838 //down(&priv->rf_sem);
1732 839
1733 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); 840 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
@@ -1775,10 +882,8 @@ u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u3
1775 struct r8192_priv *priv = ieee80211_priv(dev); 882 struct r8192_priv *priv = ieee80211_priv(dev);
1776 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 883 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1777 return 0; 884 return 0;
1778#ifdef RTL8192E
1779 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter) 885 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1780 return 0; 886 return 0;
1781#endif
1782 down(&priv->rf_sem); 887 down(&priv->rf_sem);
1783 if (priv->Rf_Mode == RF_OP_By_FW) 888 if (priv->Rf_Mode == RF_OP_By_FW)
1784 { 889 {
@@ -2281,18 +1386,8 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
2281 1386
2282 1387
2283 //XSTALLCap 1388 //XSTALLCap
2284#ifdef RTL8190P
2285 dwRegValue = priv->CrystalCap & 0x3; // bit0~1 of crystal cap
2286 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue);
2287 dwRegValue = ((priv->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap
2288 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue);
2289#else
2290 #ifdef RTL8192E
2291 dwRegValue = priv->CrystalCap; 1389 dwRegValue = priv->CrystalCap;
2292 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); 1390 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
2293 #endif
2294#endif
2295
2296 } 1391 }
2297 1392
2298 // Check if the CCK HighPower is turned ON. 1393 // Check if the CCK HighPower is turned ON.
@@ -2325,15 +1420,7 @@ RT_STATUS rtl8192_BBConfig(struct net_device* dev)
2325void rtl8192_phy_getTxPower(struct net_device* dev) 1420void rtl8192_phy_getTxPower(struct net_device* dev)
2326{ 1421{
2327 struct r8192_priv *priv = ieee80211_priv(dev); 1422 struct r8192_priv *priv = ieee80211_priv(dev);
2328#ifdef RTL8190P 1423
2329 priv->MCSTxPowerLevelOriginalOffset[0] =
2330 read_nic_dword(priv, MCS_TXAGC);
2331 priv->MCSTxPowerLevelOriginalOffset[1] =
2332 read_nic_dword(priv, (MCS_TXAGC+4));
2333 priv->CCKTxPowerLevelOriginalOffset =
2334 read_nic_dword(priv, CCK_TXAGC);
2335#else
2336 #ifdef RTL8192E
2337 priv->MCSTxPowerLevelOriginalOffset[0] = 1424 priv->MCSTxPowerLevelOriginalOffset[0] =
2338 read_nic_dword(priv, rTxAGC_Rate18_06); 1425 read_nic_dword(priv, rTxAGC_Rate18_06);
2339 priv->MCSTxPowerLevelOriginalOffset[1] = 1426 priv->MCSTxPowerLevelOriginalOffset[1] =
@@ -2346,8 +1433,6 @@ void rtl8192_phy_getTxPower(struct net_device* dev)
2346 read_nic_dword(priv, rTxAGC_Mcs11_Mcs08); 1433 read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
2347 priv->MCSTxPowerLevelOriginalOffset[5] = 1434 priv->MCSTxPowerLevelOriginalOffset[5] =
2348 read_nic_dword(priv, rTxAGC_Mcs15_Mcs12); 1435 read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
2349 #endif
2350#endif
2351 1436
2352 // read rx initial gain 1437 // read rx initial gain
2353 priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1); 1438 priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
@@ -3002,7 +2087,6 @@ static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
3002 } 2087 }
3003} 2088}
3004 2089
3005#ifndef RTL8190P
3006static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) 2090static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
3007{ 2091{
3008 struct r8192_priv *priv = ieee80211_priv(dev); 2092 struct r8192_priv *priv = ieee80211_priv(dev);
@@ -3031,23 +2115,16 @@ static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
3031 } 2115 }
3032 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 2116 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
3033} 2117}
3034#endif
3035 2118
3036static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) 2119static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
3037{ 2120{
3038#ifdef RTL8192E
3039 struct r8192_priv *priv = ieee80211_priv(dev); 2121 struct r8192_priv *priv = ieee80211_priv(dev);
3040#endif
3041 2122
3042#ifdef RTL8190P
3043 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3044#else
3045 //if(pHalData->bDcut == TRUE) 2123 //if(pHalData->bDcut == TRUE)
3046 if(priv->IC_Cut >= IC_VersionCut_D) 2124 if(priv->IC_Cut >= IC_VersionCut_D)
3047 CCK_Tx_Power_Track_BW_Switch_TSSI(dev); 2125 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3048 else 2126 else
3049 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev); 2127 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
3050#endif
3051} 2128}
3052 2129
3053 2130
@@ -3126,15 +2203,7 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3126 else 2203 else
3127 CCK_Tx_Power_Track_BW_Switch(dev); 2204 CCK_Tx_Power_Track_BW_Switch(dev);
3128 2205
3129#ifdef RTL8190P
3130 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
3131 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44); // 0xc30 is for 8190 only, Emily
3132#else
3133 #ifdef RTL8192E
3134 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 2206 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3135 #endif
3136#endif
3137
3138 break; 2207 break;
3139 case HT_CHANNEL_WIDTH_20_40: 2208 case HT_CHANNEL_WIDTH_20_40:
3140 // Add by Vivi 20071119 2209 // Add by Vivi 20071119
@@ -3162,25 +2231,7 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3162 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); 2231 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3163 2232
3164 2233
3165#ifdef RTL8190P
3166 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3167 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42); // 0xc30 is for 8190 only, Emily
3168
3169 // Set whether CCK should be sent in upper or lower channel. Suggest by YN. 20071207
3170 // It is set in Tx descriptor for 8192x series
3171 if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3172 {
3173 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01);
3174 }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3175 {
3176 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02);
3177 }
3178
3179#else
3180 #ifdef RTL8192E
3181 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 2234 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3182 #endif
3183#endif
3184 break; 2235 break;
3185 default: 2236 default:
3186 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); 2237 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
@@ -3189,7 +2240,6 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3189 } 2240 }
3190 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 2241 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3191 2242
3192#if 1
3193 //<3>Set RF related register 2243 //<3>Set RF related register
3194 switch( priv->rf_chip ) 2244 switch( priv->rf_chip )
3195 { 2245 {
@@ -3215,7 +2265,7 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3215 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 2265 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
3216 break; 2266 break;
3217 } 2267 }
3218#endif 2268
3219 atomic_dec(&(priv->ieee80211->atm_swbw)); 2269 atomic_dec(&(priv->ieee80211->atm_swbw));
3220 priv->SetBWModeInProgress= false; 2270 priv->SetBWModeInProgress= false;
3221 2271
diff --git a/drivers/staging/rtl8192e/r819xE_phy.h b/drivers/staging/rtl8192e/r819xE_phy.h
index 95a509fa35f..c676c3ad0c8 100644
--- a/drivers/staging/rtl8192e/r819xE_phy.h
+++ b/drivers/staging/rtl8192e/r819xE_phy.h
@@ -6,25 +6,6 @@
6#define MAX_RFDEPENDCMD_CNT 16 6#define MAX_RFDEPENDCMD_CNT 16
7#define MAX_POSTCMD_CNT 16 7#define MAX_POSTCMD_CNT 16
8 8
9#ifdef RTL8190P
10#define MACPHY_Array_PGLength 21
11#define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG
12#define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array
13#define RadioC_ArrayLength 246
14#define RadioD_ArrayLength 78
15#define Rtl819XRadioA_Array Rtl8190PciRadioA_Array
16#define Rtl819XRadioB_Array Rtl8190PciRadioB_Array
17#define Rtl819XRadioC_Array Rtl8190PciRadioC_Array
18#define Rtl819XRadioD_Array Rtl8190PciRadioD_Array
19#define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array
20#define PHY_REGArrayLength 280
21#define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray
22#define PHY_REG_1T2RArrayLength 280
23#define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray
24#endif
25
26
27#ifdef RTL8192E
28#define MACPHY_Array_PGLength 30 9#define MACPHY_Array_PGLength 30
29#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG 10#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
30#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array 11#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
@@ -39,7 +20,6 @@
39#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray 20#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
40#define PHY_REG_1T2RArrayLength 296 21#define PHY_REG_1T2RArrayLength 296
41#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray 22#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
42#endif
43 23
44#define AGCTAB_ArrayLength 384 24#define AGCTAB_ArrayLength 384
45#define MACPHY_ArrayLength 18 25#define MACPHY_ArrayLength 18
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 02:39:04 -0400