drm/i915: Turn on a required 3D clock gating bit on Sandybridge.

Fixes rendering failures in Unigine Tropics and Sanctuary and the mesa
"fire" demo.

Signed-off-by: Eric Anholt <eric@anholt.net>
Cc: stable@kernel.org
Signed-off-by: Keith Packard <keithp@keithp.com>

2 files changed, 12 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a09416e611..b807275ea73 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3444,6 +3444,9 @@
 #define  GT_FIFO_FREE_ENTRIES                   0x120008
 #define    GT_FIFO_NUM_RESERVED_ENTRIES         20
 
+#define GEN6_UCGCTL2                            0x9404
+# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE               (1 << 12)
+
 #define GEN6_RPNSWREQ                           0xA008
 #define   GEN6_TURBO_DISABLE                    (1<<31)
 #define   GEN6_FREQUENCY(x)                     ((x)<<25)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9fa342e8945..2b2a7645cd0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8148,6 +8148,15 @@ static void gen6_init_clock_gating(struct drm_device *dev)
         I915_WRITE(WM2_LP_ILK, 0);
         I915_WRITE(WM1_LP_ILK, 0);
 
+        /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
+         * gating disable must be set.  Failure to set it results in
+         * flickering pixels due to Z write ordering failures after
+         * some amount of runtime in the Mesa "fire" demo, and Unigine
+         * Sanctuary and Tropics, and apparently anything else with
+         * alpha test or pixel discard.
+         */
+        I915_WRITE(GEN6_UCGCTL2, GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
+
         /*
          * According to the spec the following bits should be
          * set in order to enable memory self-refresh and fbc: