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authorBen Hutchings <bhutchings@solarflare.com>2009-10-23 04:30:36 -0400
committerDavid S. Miller <davem@davemloft.net>2009-10-24 07:27:03 -0400
commit3e6c4538542ab2103ab7c01f4458bc2e21b672a1 (patch)
tree0ae49634fa3288704d6c5bf8e279909b52401734 /drivers
parent625b451455cebb7120492766c8425b6e808fc209 (diff)
sfc: Update hardware definitions for Siena
Siena is still based on the Falcon hardware architecture and will share many of these definitions, so replace falcon_hwdefs.h with regs.h. The new definitions have been generated according to a naming convention which incorporates the type and revision information. Update the code accordingly. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/sfc/falcon.c848
-rw-r--r--drivers/net/sfc/falcon_boards.c14
-rw-r--r--drivers/net/sfc/falcon_gmac.c92
-rw-r--r--drivers/net/sfc/falcon_hwdefs.h1332
-rw-r--r--drivers/net/sfc/falcon_xmac.c175
-rw-r--r--drivers/net/sfc/regs.h3180
-rw-r--r--drivers/net/sfc/tenxpress.c2
7 files changed, 3756 insertions, 1887 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index c23e8e2b094..b35e01031e2 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -22,7 +22,7 @@
22#include "mac.h" 22#include "mac.h"
23#include "spi.h" 23#include "spi.h"
24#include "falcon.h" 24#include "falcon.h"
25#include "falcon_hwdefs.h" 25#include "regs.h"
26#include "falcon_io.h" 26#include "falcon_io.h"
27#include "mdio_10g.h" 27#include "mdio_10g.h"
28#include "phy.h" 28#include "phy.h"
@@ -109,17 +109,17 @@ module_param(rx_xon_thresh_bytes, int, 0644);
109MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold"); 109MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
110 110
111/* TX descriptor ring size - min 512 max 4k */ 111/* TX descriptor ring size - min 512 max 4k */
112#define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K 112#define FALCON_TXD_RING_ORDER FFE_AZ_TX_DESCQ_SIZE_1K
113#define FALCON_TXD_RING_SIZE 1024 113#define FALCON_TXD_RING_SIZE 1024
114#define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1) 114#define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
115 115
116/* RX descriptor ring size - min 512 max 4k */ 116/* RX descriptor ring size - min 512 max 4k */
117#define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K 117#define FALCON_RXD_RING_ORDER FFE_AZ_RX_DESCQ_SIZE_1K
118#define FALCON_RXD_RING_SIZE 1024 118#define FALCON_RXD_RING_SIZE 1024
119#define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1) 119#define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
120 120
121/* Event queue size - max 32k */ 121/* Event queue size - max 32k */
122#define FALCON_EVQ_ORDER EVQ_SIZE_4K 122#define FALCON_EVQ_ORDER FFE_AZ_EVQ_SIZE_4K
123#define FALCON_EVQ_SIZE 4096 123#define FALCON_EVQ_SIZE 4096
124#define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1) 124#define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
125 125
@@ -199,9 +199,9 @@ static void falcon_setsda(void *data, int state)
199 struct efx_nic *efx = (struct efx_nic *)data; 199 struct efx_nic *efx = (struct efx_nic *)data;
200 efx_oword_t reg; 200 efx_oword_t reg;
201 201
202 falcon_read(efx, &reg, GPIO_CTL_REG_KER); 202 falcon_read(efx, &reg, FR_AB_GPIO_CTL);
203 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state); 203 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
204 falcon_write(efx, &reg, GPIO_CTL_REG_KER); 204 falcon_write(efx, &reg, FR_AB_GPIO_CTL);
205} 205}
206 206
207static void falcon_setscl(void *data, int state) 207static void falcon_setscl(void *data, int state)
@@ -209,9 +209,9 @@ static void falcon_setscl(void *data, int state)
209 struct efx_nic *efx = (struct efx_nic *)data; 209 struct efx_nic *efx = (struct efx_nic *)data;
210 efx_oword_t reg; 210 efx_oword_t reg;
211 211
212 falcon_read(efx, &reg, GPIO_CTL_REG_KER); 212 falcon_read(efx, &reg, FR_AB_GPIO_CTL);
213 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state); 213 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
214 falcon_write(efx, &reg, GPIO_CTL_REG_KER); 214 falcon_write(efx, &reg, FR_AB_GPIO_CTL);
215} 215}
216 216
217static int falcon_getsda(void *data) 217static int falcon_getsda(void *data)
@@ -219,8 +219,8 @@ static int falcon_getsda(void *data)
219 struct efx_nic *efx = (struct efx_nic *)data; 219 struct efx_nic *efx = (struct efx_nic *)data;
220 efx_oword_t reg; 220 efx_oword_t reg;
221 221
222 falcon_read(efx, &reg, GPIO_CTL_REG_KER); 222 falcon_read(efx, &reg, FR_AB_GPIO_CTL);
223 return EFX_OWORD_FIELD(reg, GPIO3_IN); 223 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
224} 224}
225 225
226static int falcon_getscl(void *data) 226static int falcon_getscl(void *data)
@@ -228,8 +228,8 @@ static int falcon_getscl(void *data)
228 struct efx_nic *efx = (struct efx_nic *)data; 228 struct efx_nic *efx = (struct efx_nic *)data;
229 efx_oword_t reg; 229 efx_oword_t reg;
230 230
231 falcon_read(efx, &reg, GPIO_CTL_REG_KER); 231 falcon_read(efx, &reg, FR_AB_GPIO_CTL);
232 return EFX_OWORD_FIELD(reg, GPIO0_IN); 232 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
233} 233}
234 234
235static struct i2c_algo_bit_data falcon_i2c_bit_operations = { 235static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
@@ -274,11 +274,10 @@ falcon_init_special_buffer(struct efx_nic *efx,
274 dma_addr = buffer->dma_addr + (i * 4096); 274 dma_addr = buffer->dma_addr + (i * 4096);
275 EFX_LOG(efx, "mapping special buffer %d at %llx\n", 275 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
276 index, (unsigned long long)dma_addr); 276 index, (unsigned long long)dma_addr);
277 EFX_POPULATE_QWORD_4(buf_desc, 277 EFX_POPULATE_QWORD_3(buf_desc,
278 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K, 278 FRF_AZ_BUF_ADR_REGION, 0,
279 BUF_ADR_REGION, 0, 279 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
280 BUF_ADR_FBUF, (dma_addr >> 12), 280 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
281 BUF_OWNER_ID_FBUF, 0);
282 falcon_write_sram(efx, &buf_desc, index); 281 falcon_write_sram(efx, &buf_desc, index);
283 } 282 }
284} 283}
@@ -299,11 +298,11 @@ falcon_fini_special_buffer(struct efx_nic *efx,
299 buffer->index, buffer->index + buffer->entries - 1); 298 buffer->index, buffer->index + buffer->entries - 1);
300 299
301 EFX_POPULATE_OWORD_4(buf_tbl_upd, 300 EFX_POPULATE_OWORD_4(buf_tbl_upd,
302 BUF_UPD_CMD, 0, 301 FRF_AZ_BUF_UPD_CMD, 0,
303 BUF_CLR_CMD, 1, 302 FRF_AZ_BUF_CLR_CMD, 1,
304 BUF_CLR_END_ID, end, 303 FRF_AZ_BUF_CLR_END_ID, end,
305 BUF_CLR_START_ID, start); 304 FRF_AZ_BUF_CLR_START_ID, start);
306 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER); 305 falcon_write(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
307} 306}
308 307
309/* 308/*
@@ -415,9 +414,9 @@ static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
415 efx_dword_t reg; 414 efx_dword_t reg;
416 415
417 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK; 416 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
418 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr); 417 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
419 falcon_writel_page(tx_queue->efx, &reg, 418 falcon_writel_page(tx_queue->efx, &reg,
420 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue); 419 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
421} 420}
422 421
423 422
@@ -441,12 +440,11 @@ void falcon_push_buffers(struct efx_tx_queue *tx_queue)
441 ++tx_queue->write_count; 440 ++tx_queue->write_count;
442 441
443 /* Create TX descriptor ring entry */ 442 /* Create TX descriptor ring entry */
444 EFX_POPULATE_QWORD_5(*txd, 443 EFX_POPULATE_QWORD_4(*txd,
445 TX_KER_PORT, 0, 444 FSF_AZ_TX_KER_CONT, buffer->continuation,
446 TX_KER_CONT, buffer->continuation, 445 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
447 TX_KER_BYTE_CNT, buffer->len, 446 FSF_AZ_TX_KER_BUF_REGION, 0,
448 TX_KER_BUF_REGION, 0, 447 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
449 TX_KER_BUF_ADR, buffer->dma_addr);
450 } while (tx_queue->write_count != tx_queue->insert_count); 448 } while (tx_queue->write_count != tx_queue->insert_count);
451 449
452 wmb(); /* Ensure descriptors are written before they are fetched */ 450 wmb(); /* Ensure descriptors are written before they are fetched */
@@ -474,21 +472,23 @@ void falcon_init_tx(struct efx_tx_queue *tx_queue)
474 472
475 /* Push TX descriptor ring to card */ 473 /* Push TX descriptor ring to card */
476 EFX_POPULATE_OWORD_10(tx_desc_ptr, 474 EFX_POPULATE_OWORD_10(tx_desc_ptr,
477 TX_DESCQ_EN, 1, 475 FRF_AZ_TX_DESCQ_EN, 1,
478 TX_ISCSI_DDIG_EN, 0, 476 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
479 TX_ISCSI_HDIG_EN, 0, 477 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
480 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, 478 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
481 TX_DESCQ_EVQ_ID, tx_queue->channel->channel, 479 FRF_AZ_TX_DESCQ_EVQ_ID,
482 TX_DESCQ_OWNER_ID, 0, 480 tx_queue->channel->channel,
483 TX_DESCQ_LABEL, tx_queue->queue, 481 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
484 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER, 482 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
485 TX_DESCQ_TYPE, 0, 483 FRF_AZ_TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
486 TX_NON_IP_DROP_DIS_B0, 1); 484 FRF_AZ_TX_DESCQ_TYPE, 0,
485 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
487 486
488 if (falcon_rev(efx) >= FALCON_REV_B0) { 487 if (falcon_rev(efx) >= FALCON_REV_B0) {
489 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM; 488 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
490 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum); 489 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
491 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum); 490 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
491 !csum);
492 } 492 }
493 493
494 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, 494 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
@@ -500,12 +500,12 @@ void falcon_init_tx(struct efx_tx_queue *tx_queue)
500 /* Only 128 bits in this register */ 500 /* Only 128 bits in this register */
501 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128); 501 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
502 502
503 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1); 503 falcon_read(efx, &reg, FR_AA_TX_CHKSM_CFG);
504 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM) 504 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
505 clear_bit_le(tx_queue->queue, (void *)&reg); 505 clear_bit_le(tx_queue->queue, (void *)&reg);
506 else 506 else
507 set_bit_le(tx_queue->queue, (void *)&reg); 507 set_bit_le(tx_queue->queue, (void *)&reg);
508 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1); 508 falcon_write(efx, &reg, FR_AA_TX_CHKSM_CFG);
509 } 509 }
510} 510}
511 511
@@ -516,9 +516,9 @@ static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
516 516
517 /* Post a flush command */ 517 /* Post a flush command */
518 EFX_POPULATE_OWORD_2(tx_flush_descq, 518 EFX_POPULATE_OWORD_2(tx_flush_descq,
519 TX_FLUSH_DESCQ_CMD, 1, 519 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
520 TX_FLUSH_DESCQ, tx_queue->queue); 520 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
521 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER); 521 falcon_write(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
522} 522}
523 523
524void falcon_fini_tx(struct efx_tx_queue *tx_queue) 524void falcon_fini_tx(struct efx_tx_queue *tx_queue)
@@ -567,11 +567,11 @@ static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
567 rxd = falcon_rx_desc(rx_queue, index); 567 rxd = falcon_rx_desc(rx_queue, index);
568 rx_buf = efx_rx_buffer(rx_queue, index); 568 rx_buf = efx_rx_buffer(rx_queue, index);
569 EFX_POPULATE_QWORD_3(*rxd, 569 EFX_POPULATE_QWORD_3(*rxd,
570 RX_KER_BUF_SIZE, 570 FSF_AZ_RX_KER_BUF_SIZE,
571 rx_buf->len - 571 rx_buf->len -
572 rx_queue->efx->type->rx_buffer_padding, 572 rx_queue->efx->type->rx_buffer_padding,
573 RX_KER_BUF_REGION, 0, 573 FSF_AZ_RX_KER_BUF_REGION, 0,
574 RX_KER_BUF_ADR, rx_buf->dma_addr); 574 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
575} 575}
576 576
577/* This writes to the RX_DESC_WPTR register for the specified receive 577/* This writes to the RX_DESC_WPTR register for the specified receive
@@ -591,9 +591,9 @@ void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
591 591
592 wmb(); 592 wmb();
593 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK; 593 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
594 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr); 594 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
595 falcon_writel_page(rx_queue->efx, &reg, 595 falcon_writel_page(rx_queue->efx, &reg,
596 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue); 596 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
597} 597}
598 598
599int falcon_probe_rx(struct efx_rx_queue *rx_queue) 599int falcon_probe_rx(struct efx_rx_queue *rx_queue)
@@ -622,17 +622,18 @@ void falcon_init_rx(struct efx_rx_queue *rx_queue)
622 622
623 /* Push RX descriptor ring to card */ 623 /* Push RX descriptor ring to card */
624 EFX_POPULATE_OWORD_10(rx_desc_ptr, 624 EFX_POPULATE_OWORD_10(rx_desc_ptr,
625 RX_ISCSI_DDIG_EN, iscsi_digest_en, 625 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
626 RX_ISCSI_HDIG_EN, iscsi_digest_en, 626 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
627 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, 627 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
628 RX_DESCQ_EVQ_ID, rx_queue->channel->channel, 628 FRF_AZ_RX_DESCQ_EVQ_ID,
629 RX_DESCQ_OWNER_ID, 0, 629 rx_queue->channel->channel,
630 RX_DESCQ_LABEL, rx_queue->queue, 630 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
631 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER, 631 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
632 RX_DESCQ_TYPE, 0 /* kernel queue */ , 632 FRF_AZ_RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
633 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
633 /* For >=B0 this is scatter so disable */ 634 /* For >=B0 this is scatter so disable */
634 RX_DESCQ_JUMBO, !is_b0, 635 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
635 RX_DESCQ_EN, 1); 636 FRF_AZ_RX_DESCQ_EN, 1);
636 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, 637 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
637 rx_queue->queue); 638 rx_queue->queue);
638} 639}
@@ -644,9 +645,9 @@ static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
644 645
645 /* Post a flush command */ 646 /* Post a flush command */
646 EFX_POPULATE_OWORD_2(rx_flush_descq, 647 EFX_POPULATE_OWORD_2(rx_flush_descq,
647 RX_FLUSH_DESCQ_CMD, 1, 648 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
648 RX_FLUSH_DESCQ, rx_queue->queue); 649 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
649 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER); 650 falcon_write(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
650} 651}
651 652
652void falcon_fini_rx(struct efx_rx_queue *rx_queue) 653void falcon_fini_rx(struct efx_rx_queue *rx_queue)
@@ -693,7 +694,7 @@ void falcon_eventq_read_ack(struct efx_channel *channel)
693 efx_dword_t reg; 694 efx_dword_t reg;
694 struct efx_nic *efx = channel->efx; 695 struct efx_nic *efx = channel->efx;
695 696
696 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr); 697 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
697 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base, 698 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
698 channel->channel); 699 channel->channel);
699} 700}
@@ -703,11 +704,14 @@ void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
703{ 704{
704 efx_oword_t drv_ev_reg; 705 efx_oword_t drv_ev_reg;
705 706
706 EFX_POPULATE_OWORD_2(drv_ev_reg, 707 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
707 DRV_EV_QID, channel->channel, 708 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
708 DRV_EV_DATA, 709 drv_ev_reg.u32[0] = event->u32[0];
709 EFX_QWORD_FIELD64(*event, WHOLE_EVENT)); 710 drv_ev_reg.u32[1] = event->u32[1];
710 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER); 711 drv_ev_reg.u32[2] = 0;
712 drv_ev_reg.u32[3] = 0;
713 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
714 falcon_write(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
711} 715}
712 716
713/* Handle a transmit completion event 717/* Handle a transmit completion event
@@ -723,18 +727,18 @@ static void falcon_handle_tx_event(struct efx_channel *channel,
723 struct efx_tx_queue *tx_queue; 727 struct efx_tx_queue *tx_queue;
724 struct efx_nic *efx = channel->efx; 728 struct efx_nic *efx = channel->efx;
725 729
726 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) { 730 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
727 /* Transmit completion */ 731 /* Transmit completion */
728 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR); 732 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
729 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL); 733 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
730 tx_queue = &efx->tx_queue[tx_ev_q_label]; 734 tx_queue = &efx->tx_queue[tx_ev_q_label];
731 channel->irq_mod_score += 735 channel->irq_mod_score +=
732 (tx_ev_desc_ptr - tx_queue->read_count) & 736 (tx_ev_desc_ptr - tx_queue->read_count) &
733 efx->type->txd_ring_mask; 737 efx->type->txd_ring_mask;
734 efx_xmit_done(tx_queue, tx_ev_desc_ptr); 738 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
735 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) { 739 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
736 /* Rewrite the FIFO write pointer */ 740 /* Rewrite the FIFO write pointer */
737 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL); 741 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
738 tx_queue = &efx->tx_queue[tx_ev_q_label]; 742 tx_queue = &efx->tx_queue[tx_ev_q_label];
739 743
740 if (efx_dev_registered(efx)) 744 if (efx_dev_registered(efx))
@@ -742,7 +746,7 @@ static void falcon_handle_tx_event(struct efx_channel *channel,
742 falcon_notify_tx_desc(tx_queue); 746 falcon_notify_tx_desc(tx_queue);
743 if (efx_dev_registered(efx)) 747 if (efx_dev_registered(efx))
744 netif_tx_unlock(efx->net_dev); 748 netif_tx_unlock(efx->net_dev);
745 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) && 749 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
746 EFX_WORKAROUND_10727(efx)) { 750 EFX_WORKAROUND_10727(efx)) {
747 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); 751 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
748 } else { 752 } else {
@@ -766,22 +770,22 @@ static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
766 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt; 770 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
767 unsigned rx_ev_pkt_type; 771 unsigned rx_ev_pkt_type;
768 772
769 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE); 773 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
770 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT); 774 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
771 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC); 775 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
772 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE); 776 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
773 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, 777 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
774 RX_EV_BUF_OWNER_ID_ERR); 778 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
775 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR); 779 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
776 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, 780 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
777 RX_EV_IP_HDR_CHKSUM_ERR); 781 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
778 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, 782 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
779 RX_EV_TCP_UDP_CHKSUM_ERR); 783 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
780 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR); 784 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
781 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC); 785 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
782 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ? 786 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
783 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB)); 787 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
784 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR); 788 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
785 789
786 /* Every error apart from tobe_disc and pause_frm */ 790 /* Every error apart from tobe_disc and pause_frm */
787 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | 791 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
@@ -865,16 +869,17 @@ static void falcon_handle_rx_event(struct efx_channel *channel,
865 struct efx_nic *efx = channel->efx; 869 struct efx_nic *efx = channel->efx;
866 870
867 /* Basic packet information */ 871 /* Basic packet information */
868 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT); 872 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
869 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK); 873 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
870 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE); 874 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
871 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT)); 875 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
872 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1); 876 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
873 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel); 877 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
878 channel->channel);
874 879
875 rx_queue = &efx->rx_queue[channel->channel]; 880 rx_queue = &efx->rx_queue[channel->channel];
876 881
877 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR); 882 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
878 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK; 883 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
879 if (unlikely(rx_ev_desc_ptr != expected_ptr)) 884 if (unlikely(rx_ev_desc_ptr != expected_ptr))
880 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); 885 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
@@ -883,7 +888,9 @@ static void falcon_handle_rx_event(struct efx_channel *channel,
883 /* If packet is marked as OK and packet type is TCP/IPv4 or 888 /* If packet is marked as OK and packet type is TCP/IPv4 or
884 * UDP/IPv4, then we can rely on the hardware checksum. 889 * UDP/IPv4, then we can rely on the hardware checksum.
885 */ 890 */
886 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type); 891 checksummed =
892 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
893 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP;
887 } else { 894 } else {
888 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, 895 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
889 &discard); 896 &discard);
@@ -891,10 +898,10 @@ static void falcon_handle_rx_event(struct efx_channel *channel,
891 } 898 }
892 899
893 /* Detect multicast packets that didn't match the filter */ 900 /* Detect multicast packets that didn't match the filter */
894 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT); 901 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
895 if (rx_ev_mcast_pkt) { 902 if (rx_ev_mcast_pkt) {
896 unsigned int rx_ev_mcast_hash_match = 903 unsigned int rx_ev_mcast_hash_match =
897 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH); 904 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
898 905
899 if (unlikely(!rx_ev_mcast_hash_match)) 906 if (unlikely(!rx_ev_mcast_hash_match))
900 discard = true; 907 discard = true;
@@ -914,24 +921,23 @@ static void falcon_handle_global_event(struct efx_channel *channel,
914 struct efx_nic *efx = channel->efx; 921 struct efx_nic *efx = channel->efx;
915 bool handled = false; 922 bool handled = false;
916 923
917 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) || 924 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
918 EFX_QWORD_FIELD(*event, G_PHY1_INTR) || 925 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
919 EFX_QWORD_FIELD(*event, XG_PHY_INTR) || 926 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
920 EFX_QWORD_FIELD(*event, XFP_PHY_INTR)) {
921 efx->phy_op->clear_interrupt(efx); 927 efx->phy_op->clear_interrupt(efx);
922 queue_work(efx->workqueue, &efx->phy_work); 928 queue_work(efx->workqueue, &efx->phy_work);
923 handled = true; 929 handled = true;
924 } 930 }
925 931
926 if ((falcon_rev(efx) >= FALCON_REV_B0) && 932 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
927 EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0)) { 933 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
928 queue_work(efx->workqueue, &efx->mac_work); 934 queue_work(efx->workqueue, &efx->mac_work);
929 handled = true; 935 handled = true;
930 } 936 }
931 937
932 if (falcon_rev(efx) <= FALCON_REV_A1 ? 938 if (falcon_rev(efx) <= FALCON_REV_A1 ?
933 EFX_QWORD_FIELD(*event, RX_RECOVERY_A1) : 939 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
934 EFX_QWORD_FIELD(*event, RX_RECOVERY_B0)) { 940 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
935 EFX_ERR(efx, "channel %d seen global RX_RESET " 941 EFX_ERR(efx, "channel %d seen global RX_RESET "
936 "event. Resetting.\n", channel->channel); 942 "event. Resetting.\n", channel->channel);
937 943
@@ -954,35 +960,35 @@ static void falcon_handle_driver_event(struct efx_channel *channel,
954 unsigned int ev_sub_code; 960 unsigned int ev_sub_code;
955 unsigned int ev_sub_data; 961 unsigned int ev_sub_data;
956 962
957 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE); 963 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
958 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA); 964 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
959 965
960 switch (ev_sub_code) { 966 switch (ev_sub_code) {
961 case TX_DESCQ_FLS_DONE_EV_DECODE: 967 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
962 EFX_TRACE(efx, "channel %d TXQ %d flushed\n", 968 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
963 channel->channel, ev_sub_data); 969 channel->channel, ev_sub_data);
964 break; 970 break;
965 case RX_DESCQ_FLS_DONE_EV_DECODE: 971 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
966 EFX_TRACE(efx, "channel %d RXQ %d flushed\n", 972 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
967 channel->channel, ev_sub_data); 973 channel->channel, ev_sub_data);
968 break; 974 break;
969 case EVQ_INIT_DONE_EV_DECODE: 975 case FSE_AZ_EVQ_INIT_DONE_EV:
970 EFX_LOG(efx, "channel %d EVQ %d initialised\n", 976 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
971 channel->channel, ev_sub_data); 977 channel->channel, ev_sub_data);
972 break; 978 break;
973 case SRM_UPD_DONE_EV_DECODE: 979 case FSE_AZ_SRM_UPD_DONE_EV:
974 EFX_TRACE(efx, "channel %d SRAM update done\n", 980 EFX_TRACE(efx, "channel %d SRAM update done\n",
975 channel->channel); 981 channel->channel);
976 break; 982 break;
977 case WAKE_UP_EV_DECODE: 983 case FSE_AZ_WAKE_UP_EV:
978 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n", 984 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
979 channel->channel, ev_sub_data); 985 channel->channel, ev_sub_data);
980 break; 986 break;
981 case TIMER_EV_DECODE: 987 case FSE_AZ_TIMER_EV:
982 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n", 988 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
983 channel->channel, ev_sub_data); 989 channel->channel, ev_sub_data);
984 break; 990 break;
985 case RX_RECOVERY_EV_DECODE: 991 case FSE_AA_RX_RECOVER_EV:
986 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. " 992 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
987 "Resetting.\n", channel->channel); 993 "Resetting.\n", channel->channel);
988 atomic_inc(&efx->rx_reset); 994 atomic_inc(&efx->rx_reset);
@@ -991,12 +997,12 @@ static void falcon_handle_driver_event(struct efx_channel *channel,
991 RESET_TYPE_RX_RECOVERY : 997 RESET_TYPE_RX_RECOVERY :
992 RESET_TYPE_DISABLE); 998 RESET_TYPE_DISABLE);
993 break; 999 break;
994 case RX_DSC_ERROR_EV_DECODE: 1000 case FSE_BZ_RX_DSC_ERROR_EV:
995 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error." 1001 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
996 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data); 1002 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
997 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); 1003 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
998 break; 1004 break;
999 case TX_DSC_ERROR_EV_DECODE: 1005 case FSE_BZ_TX_DSC_ERROR_EV:
1000 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error." 1006 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1001 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data); 1007 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1002 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); 1008 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
@@ -1032,27 +1038,27 @@ int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1032 /* Clear this event by marking it all ones */ 1038 /* Clear this event by marking it all ones */
1033 EFX_SET_QWORD(*p_event); 1039 EFX_SET_QWORD(*p_event);
1034 1040
1035 ev_code = EFX_QWORD_FIELD(event, EV_CODE); 1041 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1036 1042
1037 switch (ev_code) { 1043 switch (ev_code) {
1038 case RX_IP_EV_DECODE: 1044 case FSE_AZ_EV_CODE_RX_EV:
1039 falcon_handle_rx_event(channel, &event); 1045 falcon_handle_rx_event(channel, &event);
1040 ++rx_packets; 1046 ++rx_packets;
1041 break; 1047 break;
1042 case TX_IP_EV_DECODE: 1048 case FSE_AZ_EV_CODE_TX_EV:
1043 falcon_handle_tx_event(channel, &event); 1049 falcon_handle_tx_event(channel, &event);
1044 break; 1050 break;
1045 case DRV_GEN_EV_DECODE: 1051 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1046 channel->eventq_magic 1052 channel->eventq_magic = EFX_QWORD_FIELD(
1047 = EFX_QWORD_FIELD(event, EVQ_MAGIC); 1053 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1048 EFX_LOG(channel->efx, "channel %d received generated " 1054 EFX_LOG(channel->efx, "channel %d received generated "
1049 "event "EFX_QWORD_FMT"\n", channel->channel, 1055 "event "EFX_QWORD_FMT"\n", channel->channel,
1050 EFX_QWORD_VAL(event)); 1056 EFX_QWORD_VAL(event));
1051 break; 1057 break;
1052 case GLOBAL_EV_DECODE: 1058 case FSE_AZ_EV_CODE_GLOBAL_EV:
1053 falcon_handle_global_event(channel, &event); 1059 falcon_handle_global_event(channel, &event);
1054 break; 1060 break;
1055 case DRIVER_EV_DECODE: 1061 case FSE_AZ_EV_CODE_DRIVER_EV:
1056 falcon_handle_driver_event(channel, &event); 1062 falcon_handle_driver_event(channel, &event);
1057 break; 1063 break;
1058 default: 1064 default:
@@ -1086,16 +1092,19 @@ void falcon_set_int_moderation(struct efx_channel *channel)
1086 if (channel->irq_moderation < FALCON_IRQ_MOD_RESOLUTION) 1092 if (channel->irq_moderation < FALCON_IRQ_MOD_RESOLUTION)
1087 channel->irq_moderation = FALCON_IRQ_MOD_RESOLUTION; 1093 channel->irq_moderation = FALCON_IRQ_MOD_RESOLUTION;
1088 EFX_POPULATE_DWORD_2(timer_cmd, 1094 EFX_POPULATE_DWORD_2(timer_cmd,
1089 TIMER_MODE, TIMER_MODE_INT_HLDOFF, 1095 FRF_AB_TC_TIMER_MODE,
1090 TIMER_VAL, 1096 FFE_BB_TIMER_MODE_INT_HLDOFF,
1097 FRF_AB_TC_TIMER_VAL,
1091 channel->irq_moderation / 1098 channel->irq_moderation /
1092 FALCON_IRQ_MOD_RESOLUTION - 1); 1099 FALCON_IRQ_MOD_RESOLUTION - 1);
1093 } else { 1100 } else {
1094 EFX_POPULATE_DWORD_2(timer_cmd, 1101 EFX_POPULATE_DWORD_2(timer_cmd,
1095 TIMER_MODE, TIMER_MODE_DIS, 1102 FRF_AB_TC_TIMER_MODE,
1096 TIMER_VAL, 0); 1103 FFE_BB_TIMER_MODE_DIS,
1104 FRF_AB_TC_TIMER_VAL, 0);
1097 } 1105 }
1098 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER, 1106 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1107 falcon_writel_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1099 channel->channel); 1108 channel->channel);
1100 1109
1101} 1110}
@@ -1127,9 +1136,9 @@ void falcon_init_eventq(struct efx_channel *channel)
1127 1136
1128 /* Push event queue to card */ 1137 /* Push event queue to card */
1129 EFX_POPULATE_OWORD_3(evq_ptr, 1138 EFX_POPULATE_OWORD_3(evq_ptr,
1130 EVQ_EN, 1, 1139 FRF_AZ_EVQ_EN, 1,
1131 EVQ_SIZE, FALCON_EVQ_ORDER, 1140 FRF_AZ_EVQ_SIZE, FALCON_EVQ_ORDER,
1132 EVQ_BUF_BASE_ID, channel->eventq.index); 1141 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1133 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base, 1142 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1134 channel->channel); 1143 channel->channel);
1135 1144
@@ -1165,9 +1174,9 @@ void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1165{ 1174{
1166 efx_qword_t test_event; 1175 efx_qword_t test_event;
1167 1176
1168 EFX_POPULATE_QWORD_2(test_event, 1177 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1169 EV_CODE, DRV_GEN_EV_DECODE, 1178 FSE_AZ_EV_CODE_DRV_GEN_EV,
1170 EVQ_MAGIC, magic); 1179 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1171 falcon_generate_event(channel, &test_event); 1180 falcon_generate_event(channel, &test_event);
1172} 1181}
1173 1182
@@ -1175,11 +1184,12 @@ void falcon_sim_phy_event(struct efx_nic *efx)
1175{ 1184{
1176 efx_qword_t phy_event; 1185 efx_qword_t phy_event;
1177 1186
1178 EFX_POPULATE_QWORD_1(phy_event, EV_CODE, GLOBAL_EV_DECODE); 1187 EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1188 FSE_AZ_EV_CODE_GLOBAL_EV);
1179 if (EFX_IS10G(efx)) 1189 if (EFX_IS10G(efx))
1180 EFX_SET_QWORD_FIELD(phy_event, XG_PHY_INTR, 1); 1190 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1181 else 1191 else
1182 EFX_SET_QWORD_FIELD(phy_event, G_PHY0_INTR, 1); 1192 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1183 1193
1184 falcon_generate_event(&efx->channel[0], &phy_event); 1194 falcon_generate_event(&efx->channel[0], &phy_event);
1185} 1195}
@@ -1207,22 +1217,23 @@ static void falcon_poll_flush_events(struct efx_nic *efx)
1207 if (!falcon_event_present(event)) 1217 if (!falcon_event_present(event))
1208 break; 1218 break;
1209 1219
1210 ev_code = EFX_QWORD_FIELD(*event, EV_CODE); 1220 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1211 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE); 1221 ev_sub_code = EFX_QWORD_FIELD(*event,
1212 if (ev_code == DRIVER_EV_DECODE && 1222 FSF_AZ_DRIVER_EV_SUBCODE);
1213 ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) { 1223 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1224 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1214 ev_queue = EFX_QWORD_FIELD(*event, 1225 ev_queue = EFX_QWORD_FIELD(*event,
1215 DRIVER_EV_TX_DESCQ_ID); 1226 FSF_AZ_DRIVER_EV_SUBDATA);
1216 if (ev_queue < EFX_TX_QUEUE_COUNT) { 1227 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1217 tx_queue = efx->tx_queue + ev_queue; 1228 tx_queue = efx->tx_queue + ev_queue;
1218 tx_queue->flushed = true; 1229 tx_queue->flushed = true;
1219 } 1230 }
1220 } else if (ev_code == DRIVER_EV_DECODE && 1231 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1221 ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) { 1232 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1222 ev_queue = EFX_QWORD_FIELD(*event, 1233 ev_queue = EFX_QWORD_FIELD(
1223 DRIVER_EV_RX_DESCQ_ID); 1234 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1224 ev_failed = EFX_QWORD_FIELD(*event, 1235 ev_failed = EFX_QWORD_FIELD(
1225 DRIVER_EV_RX_FLUSH_FAIL); 1236 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1226 if (ev_queue < efx->n_rx_queues) { 1237 if (ev_queue < efx->n_rx_queues) {
1227 rx_queue = efx->rx_queue + ev_queue; 1238 rx_queue = efx->rx_queue + ev_queue;
1228 1239
@@ -1312,9 +1323,9 @@ static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1312 efx_oword_t int_en_reg_ker; 1323 efx_oword_t int_en_reg_ker;
1313 1324
1314 EFX_POPULATE_OWORD_2(int_en_reg_ker, 1325 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1315 KER_INT_KER, force, 1326 FRF_AZ_KER_INT_KER, force,
1316 DRV_INT_EN_KER, enabled); 1327 FRF_AZ_DRV_INT_EN_KER, enabled);
1317 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER); 1328 falcon_write(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1318} 1329}
1319 1330
1320void falcon_enable_interrupts(struct efx_nic *efx) 1331void falcon_enable_interrupts(struct efx_nic *efx)
@@ -1327,9 +1338,10 @@ void falcon_enable_interrupts(struct efx_nic *efx)
1327 1338
1328 /* Program address */ 1339 /* Program address */
1329 EFX_POPULATE_OWORD_2(int_adr_reg_ker, 1340 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1330 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx), 1341 FRF_AZ_NORM_INT_VEC_DIS_KER,
1331 INT_ADR_KER, efx->irq_status.dma_addr); 1342 EFX_INT_MODE_USE_MSI(efx),
1332 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER); 1343 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1344 falcon_write(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1333 1345
1334 /* Enable interrupts */ 1346 /* Enable interrupts */
1335 falcon_interrupts(efx, 1, 0); 1347 falcon_interrupts(efx, 1, 0);
@@ -1369,9 +1381,9 @@ static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1369{ 1381{
1370 efx_dword_t reg; 1382 efx_dword_t reg;
1371 1383
1372 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e); 1384 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1373 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1); 1385 falcon_writel(efx, &reg, FR_AA_INT_ACK_KER);
1374 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1); 1386 falcon_readl(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1375} 1387}
1376 1388
1377/* Process a fatal interrupt 1389/* Process a fatal interrupt
@@ -1384,8 +1396,8 @@ static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1384 efx_oword_t fatal_intr; 1396 efx_oword_t fatal_intr;
1385 int error, mem_perr; 1397 int error, mem_perr;
1386 1398
1387 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER); 1399 falcon_read(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1388 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR); 1400 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1389 1401
1390 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status " 1402 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1391 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), 1403 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
@@ -1395,10 +1407,10 @@ static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1395 goto out; 1407 goto out;
1396 1408
1397 /* If this is a memory parity error dump which blocks are offending */ 1409 /* If this is a memory parity error dump which blocks are offending */
1398 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER); 1410 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1399 if (mem_perr) { 1411 if (mem_perr) {
1400 efx_oword_t reg; 1412 efx_oword_t reg;
1401 falcon_read(efx, &reg, MEM_STAT_REG_KER); 1413 falcon_read(efx, &reg, FR_AZ_MEM_STAT);
1402 EFX_ERR(efx, "SYSTEM ERROR: memory parity error " 1414 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1403 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg)); 1415 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1404 } 1416 }
@@ -1442,11 +1454,11 @@ static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1442 int syserr; 1454 int syserr;
1443 1455
1444 /* Read the ISR which also ACKs the interrupts */ 1456 /* Read the ISR which also ACKs the interrupts */
1445 falcon_readl(efx, &reg, INT_ISR0_B0); 1457 falcon_readl(efx, &reg, FR_BZ_INT_ISR0);
1446 queues = EFX_EXTRACT_DWORD(reg, 0, 31); 1458 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1447 1459
1448 /* Check to see if we have a serious error condition */ 1460 /* Check to see if we have a serious error condition */
1449 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); 1461 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1450 if (unlikely(syserr)) 1462 if (unlikely(syserr))
1451 return falcon_fatal_interrupt(efx); 1463 return falcon_fatal_interrupt(efx);
1452 1464
@@ -1492,7 +1504,7 @@ static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1492 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); 1504 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1493 1505
1494 /* Check to see if we have a serious error condition */ 1506 /* Check to see if we have a serious error condition */
1495 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); 1507 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1496 if (unlikely(syserr)) 1508 if (unlikely(syserr))
1497 return falcon_fatal_interrupt(efx); 1509 return falcon_fatal_interrupt(efx);
1498 1510
@@ -1559,10 +1571,10 @@ static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1559 if (falcon_rev(efx) < FALCON_REV_B0) 1571 if (falcon_rev(efx) < FALCON_REV_B0)
1560 return; 1572 return;
1561 1573
1562 for (offset = RX_RSS_INDIR_TBL_B0; 1574 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1563 offset < RX_RSS_INDIR_TBL_B0 + 0x800; 1575 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1564 offset += 0x10) { 1576 offset += 0x10) {
1565 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0, 1577 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1566 i % efx->n_rx_queues); 1578 i % efx->n_rx_queues);
1567 falcon_writel(efx, &dword, offset); 1579 falcon_writel(efx, &dword, offset);
1568 i++; 1580 i++;
@@ -1627,7 +1639,7 @@ void falcon_fini_interrupt(struct efx_nic *efx)
1627 1639
1628 /* ACK legacy interrupt */ 1640 /* ACK legacy interrupt */
1629 if (falcon_rev(efx) >= FALCON_REV_B0) 1641 if (falcon_rev(efx) >= FALCON_REV_B0)
1630 falcon_read(efx, &reg, INT_ISR0_B0); 1642 falcon_read(efx, &reg, FR_BZ_INT_ISR0);
1631 else 1643 else
1632 falcon_irq_ack_a1(efx); 1644 falcon_irq_ack_a1(efx);
1633 1645
@@ -1648,8 +1660,8 @@ void falcon_fini_interrupt(struct efx_nic *efx)
1648static int falcon_spi_poll(struct efx_nic *efx) 1660static int falcon_spi_poll(struct efx_nic *efx)
1649{ 1661{
1650 efx_oword_t reg; 1662 efx_oword_t reg;
1651 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER); 1663 falcon_read(efx, &reg, FR_AB_EE_SPI_HCMD);
1652 return EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; 1664 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1653} 1665}
1654 1666
1655/* Wait for SPI command completion */ 1667/* Wait for SPI command completion */
@@ -1701,27 +1713,27 @@ int falcon_spi_cmd(const struct efx_spi_device *spi,
1701 1713
1702 /* Program address register, if we have an address */ 1714 /* Program address register, if we have an address */
1703 if (addressed) { 1715 if (addressed) {
1704 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address); 1716 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1705 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER); 1717 falcon_write(efx, &reg, FR_AB_EE_SPI_HADR);
1706 } 1718 }
1707 1719
1708 /* Program data register, if we have data */ 1720 /* Program data register, if we have data */
1709 if (in != NULL) { 1721 if (in != NULL) {
1710 memcpy(&reg, in, len); 1722 memcpy(&reg, in, len);
1711 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER); 1723 falcon_write(efx, &reg, FR_AB_EE_SPI_HDATA);
1712 } 1724 }
1713 1725
1714 /* Issue read/write command */ 1726 /* Issue read/write command */
1715 EFX_POPULATE_OWORD_7(reg, 1727 EFX_POPULATE_OWORD_7(reg,
1716 EE_SPI_HCMD_CMD_EN, 1, 1728 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1717 EE_SPI_HCMD_SF_SEL, spi->device_id, 1729 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1718 EE_SPI_HCMD_DABCNT, len, 1730 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1719 EE_SPI_HCMD_READ, reading, 1731 FRF_AB_EE_SPI_HCMD_READ, reading,
1720 EE_SPI_HCMD_DUBCNT, 0, 1732 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1721 EE_SPI_HCMD_ADBCNT, 1733 FRF_AB_EE_SPI_HCMD_ADBCNT,
1722 (addressed ? spi->addr_len : 0), 1734 (addressed ? spi->addr_len : 0),
1723 EE_SPI_HCMD_ENC, command); 1735 FRF_AB_EE_SPI_HCMD_ENC, command);
1724 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER); 1736 falcon_write(efx, &reg, FR_AB_EE_SPI_HCMD);
1725 1737
1726 /* Wait for read/write to complete */ 1738 /* Wait for read/write to complete */
1727 rc = falcon_spi_wait(efx); 1739 rc = falcon_spi_wait(efx);
@@ -1730,7 +1742,7 @@ int falcon_spi_cmd(const struct efx_spi_device *spi,
1730 1742
1731 /* Read data */ 1743 /* Read data */
1732 if (out != NULL) { 1744 if (out != NULL) {
1733 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER); 1745 falcon_read(efx, &reg, FR_AB_EE_SPI_HDATA);
1734 memcpy(out, &reg, len); 1746 memcpy(out, &reg, len);
1735 } 1747 }
1736 1748
@@ -1871,21 +1883,22 @@ static int falcon_reset_macs(struct efx_nic *efx)
1871 * macs, so instead use the internal MAC resets 1883 * macs, so instead use the internal MAC resets
1872 */ 1884 */
1873 if (!EFX_IS10G(efx)) { 1885 if (!EFX_IS10G(efx)) {
1874 EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 1); 1886 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1875 falcon_write(efx, &reg, GM_CFG1_REG); 1887 falcon_write(efx, &reg, FR_AB_GM_CFG1);
1876 udelay(1000); 1888 udelay(1000);
1877 1889
1878 EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 0); 1890 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1879 falcon_write(efx, &reg, GM_CFG1_REG); 1891 falcon_write(efx, &reg, FR_AB_GM_CFG1);
1880 udelay(1000); 1892 udelay(1000);
1881 return 0; 1893 return 0;
1882 } else { 1894 } else {
1883 EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1); 1895 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1884 falcon_write(efx, &reg, XM_GLB_CFG_REG); 1896 falcon_write(efx, &reg, FR_AB_XM_GLB_CFG);
1885 1897
1886 for (count = 0; count < 10000; count++) { 1898 for (count = 0; count < 10000; count++) {
1887 falcon_read(efx, &reg, XM_GLB_CFG_REG); 1899 falcon_read(efx, &reg, FR_AB_XM_GLB_CFG);
1888 if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0) 1900 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1901 0)
1889 return 0; 1902 return 0;
1890 udelay(10); 1903 udelay(10);
1891 } 1904 }
@@ -1899,22 +1912,22 @@ static int falcon_reset_macs(struct efx_nic *efx)
1899 * the drain sequence with the statistics fetch */ 1912 * the drain sequence with the statistics fetch */
1900 efx_stats_disable(efx); 1913 efx_stats_disable(efx);
1901 1914
1902 falcon_read(efx, &reg, MAC0_CTRL_REG_KER); 1915 falcon_read(efx, &reg, FR_AB_MAC_CTRL);
1903 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 1); 1916 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1904 falcon_write(efx, &reg, MAC0_CTRL_REG_KER); 1917 falcon_write(efx, &reg, FR_AB_MAC_CTRL);
1905 1918
1906 falcon_read(efx, &reg, GLB_CTL_REG_KER); 1919 falcon_read(efx, &reg, FR_AB_GLB_CTL);
1907 EFX_SET_OWORD_FIELD(reg, RST_XGTX, 1); 1920 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1908 EFX_SET_OWORD_FIELD(reg, RST_XGRX, 1); 1921 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1909 EFX_SET_OWORD_FIELD(reg, RST_EM, 1); 1922 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1910 falcon_write(efx, &reg, GLB_CTL_REG_KER); 1923 falcon_write(efx, &reg, FR_AB_GLB_CTL);
1911 1924
1912 count = 0; 1925 count = 0;
1913 while (1) { 1926 while (1) {
1914 falcon_read(efx, &reg, GLB_CTL_REG_KER); 1927 falcon_read(efx, &reg, FR_AB_GLB_CTL);
1915 if (!EFX_OWORD_FIELD(reg, RST_XGTX) && 1928 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1916 !EFX_OWORD_FIELD(reg, RST_XGRX) && 1929 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1917 !EFX_OWORD_FIELD(reg, RST_EM)) { 1930 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1918 EFX_LOG(efx, "Completed MAC reset after %d loops\n", 1931 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1919 count); 1932 count);
1920 break; 1933 break;
@@ -1945,9 +1958,9 @@ void falcon_drain_tx_fifo(struct efx_nic *efx)
1945 (efx->loopback_mode != LOOPBACK_NONE)) 1958 (efx->loopback_mode != LOOPBACK_NONE))
1946 return; 1959 return;
1947 1960
1948 falcon_read(efx, &reg, MAC0_CTRL_REG_KER); 1961 falcon_read(efx, &reg, FR_AB_MAC_CTRL);
1949 /* There is no point in draining more than once */ 1962 /* There is no point in draining more than once */
1950 if (EFX_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0)) 1963 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1951 return; 1964 return;
1952 1965
1953 falcon_reset_macs(efx); 1966 falcon_reset_macs(efx);
@@ -1961,9 +1974,9 @@ void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1961 return; 1974 return;
1962 1975
1963 /* Isolate the MAC -> RX */ 1976 /* Isolate the MAC -> RX */
1964 falcon_read(efx, &reg, RX_CFG_REG_KER); 1977 falcon_read(efx, &reg, FR_AZ_RX_CFG);
1965 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 0); 1978 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1966 falcon_write(efx, &reg, RX_CFG_REG_KER); 1979 falcon_write(efx, &reg, FR_AZ_RX_CFG);
1967 1980
1968 if (!efx->link_up) 1981 if (!efx->link_up)
1969 falcon_drain_tx_fifo(efx); 1982 falcon_drain_tx_fifo(efx);
@@ -1986,19 +1999,19 @@ void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1986 * indefinitely held and TX queue can be flushed at any point 1999 * indefinitely held and TX queue can be flushed at any point
1987 * while the link is down. */ 2000 * while the link is down. */
1988 EFX_POPULATE_OWORD_5(reg, 2001 EFX_POPULATE_OWORD_5(reg,
1989 MAC_XOFF_VAL, 0xffff /* max pause time */, 2002 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1990 MAC_BCAD_ACPT, 1, 2003 FRF_AB_MAC_BCAD_ACPT, 1,
1991 MAC_UC_PROM, efx->promiscuous, 2004 FRF_AB_MAC_UC_PROM, efx->promiscuous,
1992 MAC_LINK_STATUS, 1, /* always set */ 2005 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1993 MAC_SPEED, link_speed); 2006 FRF_AB_MAC_SPEED, link_speed);
1994 /* On B0, MAC backpressure can be disabled and packets get 2007 /* On B0, MAC backpressure can be disabled and packets get
1995 * discarded. */ 2008 * discarded. */
1996 if (falcon_rev(efx) >= FALCON_REV_B0) { 2009 if (falcon_rev(efx) >= FALCON_REV_B0) {
1997 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 2010 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1998 !efx->link_up); 2011 !efx->link_up);
1999 } 2012 }
2000 2013
2001 falcon_write(efx, &reg, MAC0_CTRL_REG_KER); 2014 falcon_write(efx, &reg, FR_AB_MAC_CTRL);
2002 2015
2003 /* Restore the multicast hash registers. */ 2016 /* Restore the multicast hash registers. */
2004 falcon_set_multicast_hash(efx); 2017 falcon_set_multicast_hash(efx);
@@ -2007,13 +2020,13 @@ void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
2007 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL. 2020 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2008 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */ 2021 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2009 tx_fc = !!(efx->link_fc & EFX_FC_TX); 2022 tx_fc = !!(efx->link_fc & EFX_FC_TX);
2010 falcon_read(efx, &reg, RX_CFG_REG_KER); 2023 falcon_read(efx, &reg, FR_AZ_RX_CFG);
2011 EFX_SET_OWORD_FIELD(reg, RX_XOFF_MAC_EN, tx_fc); 2024 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
2012 2025
2013 /* Unisolate the MAC -> RX */ 2026 /* Unisolate the MAC -> RX */
2014 if (falcon_rev(efx) >= FALCON_REV_B0) 2027 if (falcon_rev(efx) >= FALCON_REV_B0)
2015 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1); 2028 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2016 falcon_write(efx, &reg, RX_CFG_REG_KER); 2029 falcon_write(efx, &reg, FR_AZ_RX_CFG);
2017} 2030}
2018 2031
2019int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset) 2032int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
@@ -2028,8 +2041,8 @@ int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2028 /* Statistics fetch will fail if the MAC is in TX drain */ 2041 /* Statistics fetch will fail if the MAC is in TX drain */
2029 if (falcon_rev(efx) >= FALCON_REV_B0) { 2042 if (falcon_rev(efx) >= FALCON_REV_B0) {
2030 efx_oword_t temp; 2043 efx_oword_t temp;
2031 falcon_read(efx, &temp, MAC0_CTRL_REG_KER); 2044 falcon_read(efx, &temp, FR_AB_MAC_CTRL);
2032 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0)) 2045 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2033 return 0; 2046 return 0;
2034 } 2047 }
2035 2048
@@ -2039,10 +2052,10 @@ int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2039 2052
2040 /* Initiate DMA transfer of stats */ 2053 /* Initiate DMA transfer of stats */
2041 EFX_POPULATE_OWORD_2(reg, 2054 EFX_POPULATE_OWORD_2(reg,
2042 MAC_STAT_DMA_CMD, 1, 2055 FRF_AB_MAC_STAT_DMA_CMD, 1,
2043 MAC_STAT_DMA_ADR, 2056 FRF_AB_MAC_STAT_DMA_ADR,
2044 efx->stats_buffer.dma_addr); 2057 efx->stats_buffer.dma_addr);
2045 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER); 2058 falcon_write(efx, &reg, FR_AB_MAC_STAT_DMA);
2046 2059
2047 /* Wait for transfer to complete */ 2060 /* Wait for transfer to complete */
2048 for (i = 0; i < 400; i++) { 2061 for (i = 0; i < 400; i++) {
@@ -2072,10 +2085,10 @@ static int falcon_gmii_wait(struct efx_nic *efx)
2072 2085
2073 /* wait upto 50ms - taken max from datasheet */ 2086 /* wait upto 50ms - taken max from datasheet */
2074 for (count = 0; count < 5000; count++) { 2087 for (count = 0; count < 5000; count++) {
2075 falcon_readl(efx, &md_stat, MD_STAT_REG_KER); 2088 falcon_readl(efx, &md_stat, FR_AB_MD_STAT);
2076 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) { 2089 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2077 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 || 2090 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2078 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) { 2091 EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2079 EFX_ERR(efx, "error from GMII access " 2092 EFX_ERR(efx, "error from GMII access "
2080 EFX_DWORD_FMT"\n", 2093 EFX_DWORD_FMT"\n",
2081 EFX_DWORD_VAL(md_stat)); 2094 EFX_DWORD_VAL(md_stat));
@@ -2108,29 +2121,30 @@ static int falcon_mdio_write(struct net_device *net_dev,
2108 goto out; 2121 goto out;
2109 2122
2110 /* Write the address/ID register */ 2123 /* Write the address/ID register */
2111 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr); 2124 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2112 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER); 2125 falcon_write(efx, &reg, FR_AB_MD_PHY_ADR);
2113 2126
2114 EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad); 2127 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2115 falcon_write(efx, &reg, MD_ID_REG_KER); 2128 FRF_AB_MD_DEV_ADR, devad);
2129 falcon_write(efx, &reg, FR_AB_MD_ID);
2116 2130
2117 /* Write data */ 2131 /* Write data */
2118 EFX_POPULATE_OWORD_1(reg, MD_TXD, value); 2132 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2119 falcon_write(efx, &reg, MD_TXD_REG_KER); 2133 falcon_write(efx, &reg, FR_AB_MD_TXD);
2120 2134
2121 EFX_POPULATE_OWORD_2(reg, 2135 EFX_POPULATE_OWORD_2(reg,
2122 MD_WRC, 1, 2136 FRF_AB_MD_WRC, 1,
2123 MD_GC, 0); 2137 FRF_AB_MD_GC, 0);
2124 falcon_write(efx, &reg, MD_CS_REG_KER); 2138 falcon_write(efx, &reg, FR_AB_MD_CS);
2125 2139
2126 /* Wait for data to be written */ 2140 /* Wait for data to be written */
2127 rc = falcon_gmii_wait(efx); 2141 rc = falcon_gmii_wait(efx);
2128 if (rc) { 2142 if (rc) {
2129 /* Abort the write operation */ 2143 /* Abort the write operation */
2130 EFX_POPULATE_OWORD_2(reg, 2144 EFX_POPULATE_OWORD_2(reg,
2131 MD_WRC, 0, 2145 FRF_AB_MD_WRC, 0,
2132 MD_GC, 1); 2146 FRF_AB_MD_GC, 1);
2133 falcon_write(efx, &reg, MD_CS_REG_KER); 2147 falcon_write(efx, &reg, FR_AB_MD_CS);
2134 udelay(10); 2148 udelay(10);
2135 } 2149 }
2136 2150
@@ -2154,29 +2168,30 @@ static int falcon_mdio_read(struct net_device *net_dev,
2154 if (rc) 2168 if (rc)
2155 goto out; 2169 goto out;
2156 2170
2157 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr); 2171 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2158 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER); 2172 falcon_write(efx, &reg, FR_AB_MD_PHY_ADR);
2159 2173
2160 EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad); 2174 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2161 falcon_write(efx, &reg, MD_ID_REG_KER); 2175 FRF_AB_MD_DEV_ADR, devad);
2176 falcon_write(efx, &reg, FR_AB_MD_ID);
2162 2177
2163 /* Request data to be read */ 2178 /* Request data to be read */
2164 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0); 2179 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2165 falcon_write(efx, &reg, MD_CS_REG_KER); 2180 falcon_write(efx, &reg, FR_AB_MD_CS);
2166 2181
2167 /* Wait for data to become available */ 2182 /* Wait for data to become available */
2168 rc = falcon_gmii_wait(efx); 2183 rc = falcon_gmii_wait(efx);
2169 if (rc == 0) { 2184 if (rc == 0) {
2170 falcon_read(efx, &reg, MD_RXD_REG_KER); 2185 falcon_read(efx, &reg, FR_AB_MD_RXD);
2171 rc = EFX_OWORD_FIELD(reg, MD_RXD); 2186 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2172 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n", 2187 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2173 prtad, devad, addr, rc); 2188 prtad, devad, addr, rc);
2174 } else { 2189 } else {
2175 /* Abort the read operation */ 2190 /* Abort the read operation */
2176 EFX_POPULATE_OWORD_2(reg, 2191 EFX_POPULATE_OWORD_2(reg,
2177 MD_RIC, 0, 2192 FRF_AB_MD_RIC, 0,
2178 MD_GC, 1); 2193 FRF_AB_MD_GC, 1);
2179 falcon_write(efx, &reg, MD_CS_REG_KER); 2194 falcon_write(efx, &reg, FR_AB_MD_CS);
2180 2195
2181 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n", 2196 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2182 prtad, devad, addr, rc); 2197 prtad, devad, addr, rc);
@@ -2243,16 +2258,17 @@ int falcon_switch_mac(struct efx_nic *efx)
2243 2258
2244 /* Always push the NIC_STAT_REG setting even if the mac hasn't 2259 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2245 * changed, because this function is run post online reset */ 2260 * changed, because this function is run post online reset */
2246 falcon_read(efx, &nic_stat, NIC_STAT_REG); 2261 falcon_read(efx, &nic_stat, FR_AB_NIC_STAT);
2247 strap_val = EFX_IS10G(efx) ? 5 : 3; 2262 strap_val = EFX_IS10G(efx) ? 5 : 3;
2248 if (falcon_rev(efx) >= FALCON_REV_B0) { 2263 if (falcon_rev(efx) >= FALCON_REV_B0) {
2249 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_EN, 1); 2264 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2250 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_OVR, strap_val); 2265 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2251 falcon_write(efx, &nic_stat, NIC_STAT_REG); 2266 falcon_write(efx, &nic_stat, FR_AB_NIC_STAT);
2252 } else { 2267 } else {
2253 /* Falcon A1 does not support 1G/10G speed switching 2268 /* Falcon A1 does not support 1G/10G speed switching
2254 * and must not be used with a PHY that does. */ 2269 * and must not be used with a PHY that does. */
2255 BUG_ON(EFX_OWORD_FIELD(nic_stat, STRAP_PINS) != strap_val); 2270 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2271 strap_val);
2256 } 2272 }
2257 2273
2258 if (old_mac_op == efx->mac_op) 2274 if (old_mac_op == efx->mac_op)
@@ -2325,8 +2341,8 @@ void falcon_set_multicast_hash(struct efx_nic *efx)
2325 */ 2341 */
2326 set_bit_le(0xff, mc_hash->byte); 2342 set_bit_le(0xff, mc_hash->byte);
2327 2343
2328 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER); 2344 falcon_write(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2329 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER); 2345 falcon_write(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2330} 2346}
2331 2347
2332 2348
@@ -2352,7 +2368,7 @@ int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2352 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); 2368 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2353 if (!region) 2369 if (!region)
2354 return -ENOMEM; 2370 return -ENOMEM;
2355 nvconfig = region + NVCONFIG_OFFSET; 2371 nvconfig = region + FALCON_NVCONFIG_OFFSET;
2356 2372
2357 mutex_lock(&efx->spi_lock); 2373 mutex_lock(&efx->spi_lock);
2358 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region); 2374 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
@@ -2368,7 +2384,7 @@ int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2368 struct_ver = le16_to_cpu(nvconfig->board_struct_ver); 2384 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2369 2385
2370 rc = -EINVAL; 2386 rc = -EINVAL;
2371 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) { 2387 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2372 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num); 2388 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2373 goto out; 2389 goto out;
2374 } 2390 }
@@ -2404,41 +2420,41 @@ static struct {
2404 unsigned address; 2420 unsigned address;
2405 efx_oword_t mask; 2421 efx_oword_t mask;
2406} efx_test_registers[] = { 2422} efx_test_registers[] = {
2407 { ADR_REGION_REG_KER, 2423 { FR_AZ_ADR_REGION,
2408 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) }, 2424 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2409 { RX_CFG_REG_KER, 2425 { FR_AZ_RX_CFG,
2410 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, 2426 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2411 { TX_CFG_REG_KER, 2427 { FR_AZ_TX_CFG,
2412 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, 2428 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2413 { TX_CFG2_REG_KER, 2429 { FR_AZ_TX_RESERVED,
2414 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, 2430 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2415 { MAC0_CTRL_REG_KER, 2431 { FR_AB_MAC_CTRL,
2416 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, 2432 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2417 { SRM_TX_DC_CFG_REG_KER, 2433 { FR_AZ_SRM_TX_DC_CFG,
2418 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, 2434 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2419 { RX_DC_CFG_REG_KER, 2435 { FR_AZ_RX_DC_CFG,
2420 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, 2436 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2421 { RX_DC_PF_WM_REG_KER, 2437 { FR_AZ_RX_DC_PF_WM,
2422 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, 2438 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2423 { DP_CTRL_REG, 2439 { FR_BZ_DP_CTRL,
2424 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, 2440 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2425 { GM_CFG2_REG, 2441 { FR_AB_GM_CFG2,
2426 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, 2442 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2427 { GMF_CFG0_REG, 2443 { FR_AB_GMF_CFG0,
2428 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, 2444 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2429 { XM_GLB_CFG_REG, 2445 { FR_AB_XM_GLB_CFG,
2430 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, 2446 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2431 { XM_TX_CFG_REG, 2447 { FR_AB_XM_TX_CFG,
2432 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, 2448 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2433 { XM_RX_CFG_REG, 2449 { FR_AB_XM_RX_CFG,
2434 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, 2450 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2435 { XM_RX_PARAM_REG, 2451 { FR_AB_XM_RX_PARAM,
2436 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, 2452 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2437 { XM_FC_REG, 2453 { FR_AB_XM_FC,
2438 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, 2454 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2439 { XM_ADR_LO_REG, 2455 { FR_AB_XM_ADR_LO,
2440 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, 2456 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2441 { XX_SD_CTL_REG, 2457 { FR_AB_XX_SD_CTL,
2442 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, 2458 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2443}; 2459};
2444 2460
@@ -2538,22 +2554,24 @@ int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2538 } 2554 }
2539 2555
2540 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, 2556 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2541 EXT_PHY_RST_DUR, 0x7, 2557 FRF_AB_EXT_PHY_RST_DUR,
2542 SWRST, 1); 2558 FFE_AB_EXT_PHY_RST_DUR_10240US,
2559 FRF_AB_SWRST, 1);
2543 } else { 2560 } else {
2544 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2545 EXCLUDE_FROM_RESET : 0);
2546
2547 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, 2561 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2548 EXT_PHY_RST_CTL, reset_phy, 2562 /* exclude PHY from "invisible" reset */
2549 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET, 2563 FRF_AB_EXT_PHY_RST_CTL,
2550 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET, 2564 method == RESET_TYPE_INVISIBLE,
2551 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET, 2565 /* exclude EEPROM/flash and PCIe */
2552 EE_RST_CTL, EXCLUDE_FROM_RESET, 2566 FRF_AB_PCIE_CORE_RST_CTL, 1,
2553 EXT_PHY_RST_DUR, 0x7 /* 10ms */, 2567 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2554 SWRST, 1); 2568 FRF_AB_PCIE_SD_RST_CTL, 1,
2555 } 2569 FRF_AB_EE_RST_CTL, 1,
2556 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER); 2570 FRF_AB_EXT_PHY_RST_DUR,
2571 FFE_AB_EXT_PHY_RST_DUR_10240US,
2572 FRF_AB_SWRST, 1);
2573 }
2574 falcon_write(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2557 2575
2558 EFX_LOG(efx, "waiting for hardware reset\n"); 2576 EFX_LOG(efx, "waiting for hardware reset\n");
2559 schedule_timeout_uninterruptible(HZ / 20); 2577 schedule_timeout_uninterruptible(HZ / 20);
@@ -2578,8 +2596,8 @@ int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2578 } 2596 }
2579 2597
2580 /* Assert that reset complete */ 2598 /* Assert that reset complete */
2581 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER); 2599 falcon_read(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2582 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) { 2600 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2583 rc = -ETIMEDOUT; 2601 rc = -ETIMEDOUT;
2584 EFX_ERR(efx, "timed out waiting for hardware reset\n"); 2602 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2585 goto fail5; 2603 goto fail5;
@@ -2607,16 +2625,16 @@ static int falcon_reset_sram(struct efx_nic *efx)
2607 int count; 2625 int count;
2608 2626
2609 /* Set the SRAM wake/sleep GPIO appropriately. */ 2627 /* Set the SRAM wake/sleep GPIO appropriately. */
2610 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER); 2628 falcon_read(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2611 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1); 2629 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2612 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1); 2630 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2613 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER); 2631 falcon_write(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2614 2632
2615 /* Initiate SRAM reset */ 2633 /* Initiate SRAM reset */
2616 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, 2634 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2617 SRAM_OOB_BT_INIT_EN, 1, 2635 FRF_AZ_SRM_INIT_EN, 1,
2618 SRM_NUM_BANKS_AND_BANK_SIZE, 0); 2636 FRF_AZ_SRM_NB_SZ, 0);
2619 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER); 2637 falcon_write(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2620 2638
2621 /* Wait for SRAM reset to complete */ 2639 /* Wait for SRAM reset to complete */
2622 count = 0; 2640 count = 0;
@@ -2627,8 +2645,8 @@ static int falcon_reset_sram(struct efx_nic *efx)
2627 schedule_timeout_uninterruptible(HZ / 50); 2645 schedule_timeout_uninterruptible(HZ / 50);
2628 2646
2629 /* Check for reset complete */ 2647 /* Check for reset complete */
2630 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER); 2648 falcon_read(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2631 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) { 2649 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2632 EFX_LOG(efx, "SRAM reset complete\n"); 2650 EFX_LOG(efx, "SRAM reset complete\n");
2633 2651
2634 return 0; 2652 return 0;
@@ -2713,16 +2731,16 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
2713 board_rev = le16_to_cpu(v2->board_revision); 2731 board_rev = le16_to_cpu(v2->board_revision);
2714 2732
2715 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { 2733 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2716 __le32 fl = v3->spi_device_type[EE_SPI_FLASH]; 2734 rc = falcon_spi_device_init(
2717 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM]; 2735 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2718 rc = falcon_spi_device_init(efx, &efx->spi_flash, 2736 le32_to_cpu(v3->spi_device_type
2719 EE_SPI_FLASH, 2737 [FFE_AB_SPI_DEVICE_FLASH]));
2720 le32_to_cpu(fl));
2721 if (rc) 2738 if (rc)
2722 goto fail2; 2739 goto fail2;
2723 rc = falcon_spi_device_init(efx, &efx->spi_eeprom, 2740 rc = falcon_spi_device_init(
2724 EE_SPI_EEPROM, 2741 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2725 le32_to_cpu(ee)); 2742 le32_to_cpu(v3->spi_device_type
2743 [FFE_AB_SPI_DEVICE_EEPROM]));
2726 if (rc) 2744 if (rc)
2727 goto fail2; 2745 goto fail2;
2728 } 2746 }
@@ -2753,13 +2771,13 @@ static int falcon_probe_nic_variant(struct efx_nic *efx)
2753 efx_oword_t altera_build; 2771 efx_oword_t altera_build;
2754 efx_oword_t nic_stat; 2772 efx_oword_t nic_stat;
2755 2773
2756 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER); 2774 falcon_read(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2757 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) { 2775 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2758 EFX_ERR(efx, "Falcon FPGA not supported\n"); 2776 EFX_ERR(efx, "Falcon FPGA not supported\n");
2759 return -ENODEV; 2777 return -ENODEV;
2760 } 2778 }
2761 2779
2762 falcon_read(efx, &nic_stat, NIC_STAT_REG); 2780 falcon_read(efx, &nic_stat, FR_AB_NIC_STAT);
2763 2781
2764 switch (falcon_rev(efx)) { 2782 switch (falcon_rev(efx)) {
2765 case FALCON_REV_A0: 2783 case FALCON_REV_A0:
@@ -2768,7 +2786,7 @@ static int falcon_probe_nic_variant(struct efx_nic *efx)
2768 return -ENODEV; 2786 return -ENODEV;
2769 2787
2770 case FALCON_REV_A1: 2788 case FALCON_REV_A1:
2771 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) { 2789 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2772 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n"); 2790 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2773 return -ENODEV; 2791 return -ENODEV;
2774 } 2792 }
@@ -2783,7 +2801,7 @@ static int falcon_probe_nic_variant(struct efx_nic *efx)
2783 } 2801 }
2784 2802
2785 /* Initial assumed speed */ 2803 /* Initial assumed speed */
2786 efx->link_speed = EFX_OWORD_FIELD(nic_stat, STRAP_10G) ? 10000 : 1000; 2804 efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2787 2805
2788 return 0; 2806 return 0;
2789} 2807}
@@ -2794,34 +2812,36 @@ static void falcon_probe_spi_devices(struct efx_nic *efx)
2794 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; 2812 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2795 int boot_dev; 2813 int boot_dev;
2796 2814
2797 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER); 2815 falcon_read(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2798 falcon_read(efx, &nic_stat, NIC_STAT_REG); 2816 falcon_read(efx, &nic_stat, FR_AB_NIC_STAT);
2799 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER); 2817 falcon_read(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2800 2818
2801 if (EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE)) { 2819 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2802 boot_dev = (EFX_OWORD_FIELD(nic_stat, SF_PRST) ? 2820 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2803 EE_SPI_FLASH : EE_SPI_EEPROM); 2821 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2804 EFX_LOG(efx, "Booted from %s\n", 2822 EFX_LOG(efx, "Booted from %s\n",
2805 boot_dev == EE_SPI_FLASH ? "flash" : "EEPROM"); 2823 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2806 } else { 2824 } else {
2807 /* Disable VPD and set clock dividers to safe 2825 /* Disable VPD and set clock dividers to safe
2808 * values for initial programming. */ 2826 * values for initial programming. */
2809 boot_dev = -1; 2827 boot_dev = -1;
2810 EFX_LOG(efx, "Booted from internal ASIC settings;" 2828 EFX_LOG(efx, "Booted from internal ASIC settings;"
2811 " setting SPI config\n"); 2829 " setting SPI config\n");
2812 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0, 2830 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2813 /* 125 MHz / 7 ~= 20 MHz */ 2831 /* 125 MHz / 7 ~= 20 MHz */
2814 EE_SF_CLOCK_DIV, 7, 2832 FRF_AB_EE_SF_CLOCK_DIV, 7,
2815 /* 125 MHz / 63 ~= 2 MHz */ 2833 /* 125 MHz / 63 ~= 2 MHz */
2816 EE_EE_CLOCK_DIV, 63); 2834 FRF_AB_EE_EE_CLOCK_DIV, 63);
2817 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER); 2835 falcon_write(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2818 } 2836 }
2819 2837
2820 if (boot_dev == EE_SPI_FLASH) 2838 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2821 falcon_spi_device_init(efx, &efx->spi_flash, EE_SPI_FLASH, 2839 falcon_spi_device_init(efx, &efx->spi_flash,
2840 FFE_AB_SPI_DEVICE_FLASH,
2822 default_flash_type); 2841 default_flash_type);
2823 if (boot_dev == EE_SPI_EEPROM) 2842 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2824 falcon_spi_device_init(efx, &efx->spi_eeprom, EE_SPI_EEPROM, 2843 falcon_spi_device_init(efx, &efx->spi_eeprom,
2844 FFE_AB_SPI_DEVICE_EEPROM,
2825 large_eeprom_type); 2845 large_eeprom_type);
2826} 2846}
2827 2847
@@ -2926,34 +2946,36 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
2926 int data_xoff_thr = rx_xoff_thresh_bytes >> 8; 2946 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2927 efx_oword_t reg; 2947 efx_oword_t reg;
2928 2948
2929 falcon_read(efx, &reg, RX_CFG_REG_KER); 2949 falcon_read(efx, &reg, FR_AZ_RX_CFG);
2930 if (falcon_rev(efx) <= FALCON_REV_A1) { 2950 if (falcon_rev(efx) <= FALCON_REV_A1) {
2931 /* Data FIFO size is 5.5K */ 2951 /* Data FIFO size is 5.5K */
2932 if (data_xon_thr < 0) 2952 if (data_xon_thr < 0)
2933 data_xon_thr = 512 >> 8; 2953 data_xon_thr = 512 >> 8;
2934 if (data_xoff_thr < 0) 2954 if (data_xoff_thr < 0)
2935 data_xoff_thr = 2048 >> 8; 2955 data_xoff_thr = 2048 >> 8;
2936 EFX_SET_OWORD_FIELD(reg, RX_DESC_PUSH_EN_A1, 0); 2956 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2937 EFX_SET_OWORD_FIELD(reg, RX_USR_BUF_SIZE_A1, huge_buf_size); 2957 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2938 EFX_SET_OWORD_FIELD(reg, RX_XON_MAC_TH_A1, data_xon_thr); 2958 huge_buf_size);
2939 EFX_SET_OWORD_FIELD(reg, RX_XOFF_MAC_TH_A1, data_xoff_thr); 2959 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2940 EFX_SET_OWORD_FIELD(reg, RX_XON_TX_TH_A1, ctrl_xon_thr); 2960 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2941 EFX_SET_OWORD_FIELD(reg, RX_XOFF_TX_TH_A1, ctrl_xoff_thr); 2961 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2962 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2942 } else { 2963 } else {
2943 /* Data FIFO size is 80K; register fields moved */ 2964 /* Data FIFO size is 80K; register fields moved */
2944 if (data_xon_thr < 0) 2965 if (data_xon_thr < 0)
2945 data_xon_thr = 27648 >> 8; /* ~3*max MTU */ 2966 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2946 if (data_xoff_thr < 0) 2967 if (data_xoff_thr < 0)
2947 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */ 2968 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2948 EFX_SET_OWORD_FIELD(reg, RX_DESC_PUSH_EN_B0, 0); 2969 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2949 EFX_SET_OWORD_FIELD(reg, RX_USR_BUF_SIZE_B0, huge_buf_size); 2970 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2950 EFX_SET_OWORD_FIELD(reg, RX_XON_MAC_TH_B0, data_xon_thr); 2971 huge_buf_size);
2951 EFX_SET_OWORD_FIELD(reg, RX_XOFF_MAC_TH_B0, data_xoff_thr); 2972 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2952 EFX_SET_OWORD_FIELD(reg, RX_XON_TX_TH_B0, ctrl_xon_thr); 2973 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2953 EFX_SET_OWORD_FIELD(reg, RX_XOFF_TX_TH_B0, ctrl_xoff_thr); 2974 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2954 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1); 2975 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2976 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2955 } 2977 }
2956 falcon_write(efx, &reg, RX_CFG_REG_KER); 2978 falcon_write(efx, &reg, FR_AZ_RX_CFG);
2957} 2979}
2958 2980
2959/* This call performs hardware-specific global initialisation, such as 2981/* This call performs hardware-specific global initialisation, such as
@@ -2966,15 +2988,15 @@ int falcon_init_nic(struct efx_nic *efx)
2966 int rc; 2988 int rc;
2967 2989
2968 /* Use on-chip SRAM */ 2990 /* Use on-chip SRAM */
2969 falcon_read(efx, &temp, NIC_STAT_REG); 2991 falcon_read(efx, &temp, FR_AB_NIC_STAT);
2970 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1); 2992 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2971 falcon_write(efx, &temp, NIC_STAT_REG); 2993 falcon_write(efx, &temp, FR_AB_NIC_STAT);
2972 2994
2973 /* Set the source of the GMAC clock */ 2995 /* Set the source of the GMAC clock */
2974 if (falcon_rev(efx) == FALCON_REV_B0) { 2996 if (falcon_rev(efx) == FALCON_REV_B0) {
2975 falcon_read(efx, &temp, GPIO_CTL_REG_KER); 2997 falcon_read(efx, &temp, FR_AB_GPIO_CTL);
2976 EFX_SET_OWORD_FIELD(temp, GPIO_USE_NIC_CLK, true); 2998 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2977 falcon_write(efx, &temp, GPIO_CTL_REG_KER); 2999 falcon_write(efx, &temp, FR_AB_GPIO_CTL);
2978 } 3000 }
2979 3001
2980 rc = falcon_reset_sram(efx); 3002 rc = falcon_reset_sram(efx);
@@ -2982,32 +3004,32 @@ int falcon_init_nic(struct efx_nic *efx)
2982 return rc; 3004 return rc;
2983 3005
2984 /* Set positions of descriptor caches in SRAM. */ 3006 /* Set positions of descriptor caches in SRAM. */
2985 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); 3007 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2986 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER); 3008 falcon_write(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
2987 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); 3009 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2988 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER); 3010 falcon_write(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
2989 3011
2990 /* Set TX descriptor cache size. */ 3012 /* Set TX descriptor cache size. */
2991 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER)); 3013 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2992 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER); 3014 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2993 falcon_write(efx, &temp, TX_DC_CFG_REG_KER); 3015 falcon_write(efx, &temp, FR_AZ_TX_DC_CFG);
2994 3016
2995 /* Set RX descriptor cache size. Set low watermark to size-8, as 3017 /* Set RX descriptor cache size. Set low watermark to size-8, as
2996 * this allows most efficient prefetching. 3018 * this allows most efficient prefetching.
2997 */ 3019 */
2998 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER)); 3020 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2999 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER); 3021 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3000 falcon_write(efx, &temp, RX_DC_CFG_REG_KER); 3022 falcon_write(efx, &temp, FR_AZ_RX_DC_CFG);
3001 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8); 3023 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3002 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER); 3024 falcon_write(efx, &temp, FR_AZ_RX_DC_PF_WM);
3003 3025
3004 /* Clear the parity enables on the TX data fifos as 3026 /* Clear the parity enables on the TX data fifos as
3005 * they produce false parity errors because of timing issues 3027 * they produce false parity errors because of timing issues
3006 */ 3028 */
3007 if (EFX_WORKAROUND_5129(efx)) { 3029 if (EFX_WORKAROUND_5129(efx)) {
3008 falcon_read(efx, &temp, SPARE_REG_KER); 3030 falcon_read(efx, &temp, FR_AZ_CSR_SPARE);
3009 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0); 3031 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3010 falcon_write(efx, &temp, SPARE_REG_KER); 3032 falcon_write(efx, &temp, FR_AZ_CSR_SPARE);
3011 } 3033 }
3012 3034
3013 /* Enable all the genuinely fatal interrupts. (They are still 3035 /* Enable all the genuinely fatal interrupts. (They are still
@@ -3017,64 +3039,65 @@ int falcon_init_nic(struct efx_nic *efx)
3017 * Note: All other fatal interrupts are enabled 3039 * Note: All other fatal interrupts are enabled
3018 */ 3040 */
3019 EFX_POPULATE_OWORD_3(temp, 3041 EFX_POPULATE_OWORD_3(temp,
3020 ILL_ADR_INT_KER_EN, 1, 3042 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3021 RBUF_OWN_INT_KER_EN, 1, 3043 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3022 TBUF_OWN_INT_KER_EN, 1); 3044 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3023 EFX_INVERT_OWORD(temp); 3045 EFX_INVERT_OWORD(temp);
3024 falcon_write(efx, &temp, FATAL_INTR_REG_KER); 3046 falcon_write(efx, &temp, FR_AZ_FATAL_INTR_KER);
3025 3047
3026 if (EFX_WORKAROUND_7244(efx)) { 3048 if (EFX_WORKAROUND_7244(efx)) {
3027 falcon_read(efx, &temp, RX_FILTER_CTL_REG); 3049 falcon_read(efx, &temp, FR_BZ_RX_FILTER_CTL);
3028 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8); 3050 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3029 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8); 3051 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3030 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8); 3052 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3031 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8); 3053 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3032 falcon_write(efx, &temp, RX_FILTER_CTL_REG); 3054 falcon_write(efx, &temp, FR_BZ_RX_FILTER_CTL);
3033 } 3055 }
3034 3056
3035 falcon_setup_rss_indir_table(efx); 3057 falcon_setup_rss_indir_table(efx);
3036 3058
3059 /* XXX This is documented only for Falcon A0/A1 */
3037 /* Setup RX. Wait for descriptor is broken and must 3060 /* Setup RX. Wait for descriptor is broken and must
3038 * be disabled. RXDP recovery shouldn't be needed, but is. 3061 * be disabled. RXDP recovery shouldn't be needed, but is.
3039 */ 3062 */
3040 falcon_read(efx, &temp, RX_SELF_RST_REG_KER); 3063 falcon_read(efx, &temp, FR_AA_RX_SELF_RST);
3041 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1); 3064 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3042 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1); 3065 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3043 if (EFX_WORKAROUND_5583(efx)) 3066 if (EFX_WORKAROUND_5583(efx))
3044 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1); 3067 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3045 falcon_write(efx, &temp, RX_SELF_RST_REG_KER); 3068 falcon_write(efx, &temp, FR_AA_RX_SELF_RST);
3046 3069
3047 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be 3070 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3048 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. 3071 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3049 */ 3072 */
3050 falcon_read(efx, &temp, TX_CFG2_REG_KER); 3073 falcon_read(efx, &temp, FR_AZ_TX_RESERVED);
3051 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe); 3074 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3052 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1); 3075 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3053 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1); 3076 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3054 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0); 3077 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3055 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1); 3078 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3056 /* Enable SW_EV to inherit in char driver - assume harmless here */ 3079 /* Enable SW_EV to inherit in char driver - assume harmless here */
3057 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1); 3080 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3058 /* Prefetch threshold 2 => fetch when descriptor cache half empty */ 3081 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3059 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2); 3082 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3060 /* Squash TX of packets of 16 bytes or less */ 3083 /* Squash TX of packets of 16 bytes or less */
3061 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx)) 3084 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3062 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1); 3085 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3063 falcon_write(efx, &temp, TX_CFG2_REG_KER); 3086 falcon_write(efx, &temp, FR_AZ_TX_RESERVED);
3064 3087
3065 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 3088 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3066 * descriptors (which is bad). 3089 * descriptors (which is bad).
3067 */ 3090 */
3068 falcon_read(efx, &temp, TX_CFG_REG_KER); 3091 falcon_read(efx, &temp, FR_AZ_TX_CFG);
3069 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0); 3092 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3070 falcon_write(efx, &temp, TX_CFG_REG_KER); 3093 falcon_write(efx, &temp, FR_AZ_TX_CFG);
3071 3094
3072 falcon_init_rx_cfg(efx); 3095 falcon_init_rx_cfg(efx);
3073 3096
3074 /* Set destination of both TX and RX Flush events */ 3097 /* Set destination of both TX and RX Flush events */
3075 if (falcon_rev(efx) >= FALCON_REV_B0) { 3098 if (falcon_rev(efx) >= FALCON_REV_B0) {
3076 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0); 3099 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3077 falcon_write(efx, &temp, DP_CTRL_REG); 3100 falcon_write(efx, &temp, FR_BZ_DP_CTRL);
3078 } 3101 }
3079 3102
3080 return 0; 3103 return 0;
@@ -3110,8 +3133,9 @@ void falcon_update_nic_stats(struct efx_nic *efx)
3110{ 3133{
3111 efx_oword_t cnt; 3134 efx_oword_t cnt;
3112 3135
3113 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER); 3136 falcon_read(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3114 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT); 3137 efx->n_rx_nodesc_drop_cnt +=
3138 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3115} 3139}
3116 3140
3117/************************************************************************** 3141/**************************************************************************
@@ -3124,11 +3148,11 @@ void falcon_update_nic_stats(struct efx_nic *efx)
3124struct efx_nic_type falcon_a_nic_type = { 3148struct efx_nic_type falcon_a_nic_type = {
3125 .mem_bar = 2, 3149 .mem_bar = 2,
3126 .mem_map_size = 0x20000, 3150 .mem_map_size = 0x20000,
3127 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1, 3151 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3128 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1, 3152 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3129 .buf_tbl_base = BUF_TBL_KER_A1, 3153 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3130 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1, 3154 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3131 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1, 3155 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3132 .txd_ring_mask = FALCON_TXD_RING_MASK, 3156 .txd_ring_mask = FALCON_TXD_RING_MASK,
3133 .rxd_ring_mask = FALCON_RXD_RING_MASK, 3157 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3134 .evq_size = FALCON_EVQ_SIZE, 3158 .evq_size = FALCON_EVQ_SIZE,
@@ -3145,12 +3169,14 @@ struct efx_nic_type falcon_b_nic_type = {
3145 /* Map everything up to and including the RSS indirection 3169 /* Map everything up to and including the RSS indirection
3146 * table. Don't map MSI-X table, MSI-X PBA since Linux 3170 * table. Don't map MSI-X table, MSI-X PBA since Linux
3147 * requires that they not be mapped. */ 3171 * requires that they not be mapped. */
3148 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800, 3172 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3149 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0, 3173 FR_BZ_RX_INDIRECTION_TBL_STEP *
3150 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0, 3174 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3151 .buf_tbl_base = BUF_TBL_KER_B0, 3175 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3152 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0, 3176 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3153 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0, 3177 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3178 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3179 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3154 .txd_ring_mask = FALCON_TXD_RING_MASK, 3180 .txd_ring_mask = FALCON_TXD_RING_MASK,
3155 .rxd_ring_mask = FALCON_RXD_RING_MASK, 3181 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3156 .evq_size = FALCON_EVQ_SIZE, 3182 .evq_size = FALCON_EVQ_SIZE,
diff --git a/drivers/net/sfc/falcon_boards.c b/drivers/net/sfc/falcon_boards.c
index ab940756ac7..68ca45c5d5d 100644
--- a/drivers/net/sfc/falcon_boards.c
+++ b/drivers/net/sfc/falcon_boards.c
@@ -13,7 +13,7 @@
13#include "phy.h" 13#include "phy.h"
14#include "efx.h" 14#include "efx.h"
15#include "falcon.h" 15#include "falcon.h"
16#include "falcon_hwdefs.h" 16#include "regs.h"
17#include "falcon_io.h" 17#include "falcon_io.h"
18#include "workarounds.h" 18#include "workarounds.h"
19 19
@@ -332,14 +332,14 @@ static int sfn4111t_reset(struct efx_nic *efx)
332 * FLASH_CFG_1 strap (GPIO 3) appropriately. Only change the 332 * FLASH_CFG_1 strap (GPIO 3) appropriately. Only change the
333 * output enables; the output levels should always be 0 (low) 333 * output enables; the output levels should always be 0 (low)
334 * and we rely on external pull-ups. */ 334 * and we rely on external pull-ups. */
335 falcon_read(efx, &reg, GPIO_CTL_REG_KER); 335 falcon_read(efx, &reg, FR_AB_GPIO_CTL);
336 EFX_SET_OWORD_FIELD(reg, GPIO2_OEN, true); 336 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, true);
337 falcon_write(efx, &reg, GPIO_CTL_REG_KER); 337 falcon_write(efx, &reg, FR_AB_GPIO_CTL);
338 msleep(1000); 338 msleep(1000);
339 EFX_SET_OWORD_FIELD(reg, GPIO2_OEN, false); 339 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, false);
340 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, 340 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN,
341 !!(efx->phy_mode & PHY_MODE_SPECIAL)); 341 !!(efx->phy_mode & PHY_MODE_SPECIAL));
342 falcon_write(efx, &reg, GPIO_CTL_REG_KER); 342 falcon_write(efx, &reg, FR_AB_GPIO_CTL);
343 msleep(1); 343 msleep(1);
344 344
345 mutex_unlock(&efx->i2c_adap.bus_lock); 345 mutex_unlock(&efx->i2c_adap.bus_lock);
diff --git a/drivers/net/sfc/falcon_gmac.c b/drivers/net/sfc/falcon_gmac.c
index 36f57b102ac..0d156c88ca4 100644
--- a/drivers/net/sfc/falcon_gmac.c
+++ b/drivers/net/sfc/falcon_gmac.c
@@ -13,7 +13,7 @@
13#include "efx.h" 13#include "efx.h"
14#include "falcon.h" 14#include "falcon.h"
15#include "mac.h" 15#include "mac.h"
16#include "falcon_hwdefs.h" 16#include "regs.h"
17#include "falcon_io.h" 17#include "falcon_io.h"
18 18
19/************************************************************************** 19/**************************************************************************
@@ -36,89 +36,89 @@ static void falcon_reconfigure_gmac(struct efx_nic *efx)
36 bytemode = (efx->link_speed == 1000); 36 bytemode = (efx->link_speed == 1000);
37 37
38 EFX_POPULATE_OWORD_5(reg, 38 EFX_POPULATE_OWORD_5(reg,
39 GM_LOOP, loopback, 39 FRF_AB_GM_LOOP, loopback,
40 GM_TX_EN, 1, 40 FRF_AB_GM_TX_EN, 1,
41 GM_TX_FC_EN, tx_fc, 41 FRF_AB_GM_TX_FC_EN, tx_fc,
42 GM_RX_EN, 1, 42 FRF_AB_GM_RX_EN, 1,
43 GM_RX_FC_EN, rx_fc); 43 FRF_AB_GM_RX_FC_EN, rx_fc);
44 falcon_write(efx, &reg, GM_CFG1_REG); 44 falcon_write(efx, &reg, FR_AB_GM_CFG1);
45 udelay(10); 45 udelay(10);
46 46
47 /* Configuration register 2 */ 47 /* Configuration register 2 */
48 if_mode = (bytemode) ? 2 : 1; 48 if_mode = (bytemode) ? 2 : 1;
49 EFX_POPULATE_OWORD_5(reg, 49 EFX_POPULATE_OWORD_5(reg,
50 GM_IF_MODE, if_mode, 50 FRF_AB_GM_IF_MODE, if_mode,
51 GM_PAD_CRC_EN, 1, 51 FRF_AB_GM_PAD_CRC_EN, 1,
52 GM_LEN_CHK, 1, 52 FRF_AB_GM_LEN_CHK, 1,
53 GM_FD, efx->link_fd, 53 FRF_AB_GM_FD, efx->link_fd,
54 GM_PAMBL_LEN, 0x7/*datasheet recommended */); 54 FRF_AB_GM_PAMBL_LEN, 0x7/*datasheet recommended */);
55 55
56 falcon_write(efx, &reg, GM_CFG2_REG); 56 falcon_write(efx, &reg, FR_AB_GM_CFG2);
57 udelay(10); 57 udelay(10);
58 58
59 /* Max frame len register */ 59 /* Max frame len register */
60 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); 60 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
61 EFX_POPULATE_OWORD_1(reg, GM_MAX_FLEN, max_frame_len); 61 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_MAX_FLEN, max_frame_len);
62 falcon_write(efx, &reg, GM_MAX_FLEN_REG); 62 falcon_write(efx, &reg, FR_AB_GM_MAX_FLEN);
63 udelay(10); 63 udelay(10);
64 64
65 /* FIFO configuration register 0 */ 65 /* FIFO configuration register 0 */
66 EFX_POPULATE_OWORD_5(reg, 66 EFX_POPULATE_OWORD_5(reg,
67 GMF_FTFENREQ, 1, 67 FRF_AB_GMF_FTFENREQ, 1,
68 GMF_STFENREQ, 1, 68 FRF_AB_GMF_STFENREQ, 1,
69 GMF_FRFENREQ, 1, 69 FRF_AB_GMF_FRFENREQ, 1,
70 GMF_SRFENREQ, 1, 70 FRF_AB_GMF_SRFENREQ, 1,
71 GMF_WTMENREQ, 1); 71 FRF_AB_GMF_WTMENREQ, 1);
72 falcon_write(efx, &reg, GMF_CFG0_REG); 72 falcon_write(efx, &reg, FR_AB_GMF_CFG0);
73 udelay(10); 73 udelay(10);
74 74
75 /* FIFO configuration register 1 */ 75 /* FIFO configuration register 1 */
76 EFX_POPULATE_OWORD_2(reg, 76 EFX_POPULATE_OWORD_2(reg,
77 GMF_CFGFRTH, 0x12, 77 FRF_AB_GMF_CFGFRTH, 0x12,
78 GMF_CFGXOFFRTX, 0xffff); 78 FRF_AB_GMF_CFGXOFFRTX, 0xffff);
79 falcon_write(efx, &reg, GMF_CFG1_REG); 79 falcon_write(efx, &reg, FR_AB_GMF_CFG1);
80 udelay(10); 80 udelay(10);
81 81
82 /* FIFO configuration register 2 */ 82 /* FIFO configuration register 2 */
83 EFX_POPULATE_OWORD_2(reg, 83 EFX_POPULATE_OWORD_2(reg,
84 GMF_CFGHWM, 0x3f, 84 FRF_AB_GMF_CFGHWM, 0x3f,
85 GMF_CFGLWM, 0xa); 85 FRF_AB_GMF_CFGLWM, 0xa);
86 falcon_write(efx, &reg, GMF_CFG2_REG); 86 falcon_write(efx, &reg, FR_AB_GMF_CFG2);
87 udelay(10); 87 udelay(10);
88 88
89 /* FIFO configuration register 3 */ 89 /* FIFO configuration register 3 */
90 EFX_POPULATE_OWORD_2(reg, 90 EFX_POPULATE_OWORD_2(reg,
91 GMF_CFGHWMFT, 0x1c, 91 FRF_AB_GMF_CFGHWMFT, 0x1c,
92 GMF_CFGFTTH, 0x08); 92 FRF_AB_GMF_CFGFTTH, 0x08);
93 falcon_write(efx, &reg, GMF_CFG3_REG); 93 falcon_write(efx, &reg, FR_AB_GMF_CFG3);
94 udelay(10); 94 udelay(10);
95 95
96 /* FIFO configuration register 4 */ 96 /* FIFO configuration register 4 */
97 EFX_POPULATE_OWORD_1(reg, GMF_HSTFLTRFRM_PAUSE, 1); 97 EFX_POPULATE_OWORD_1(reg, FRF_AB_GMF_HSTFLTRFRM_PAUSE, 1);
98 falcon_write(efx, &reg, GMF_CFG4_REG); 98 falcon_write(efx, &reg, FR_AB_GMF_CFG4);
99 udelay(10); 99 udelay(10);
100 100
101 /* FIFO configuration register 5 */ 101 /* FIFO configuration register 5 */
102 falcon_read(efx, &reg, GMF_CFG5_REG); 102 falcon_read(efx, &reg, FR_AB_GMF_CFG5);
103 EFX_SET_OWORD_FIELD(reg, GMF_CFGBYTMODE, bytemode); 103 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGBYTMODE, bytemode);
104 EFX_SET_OWORD_FIELD(reg, GMF_CFGHDPLX, !efx->link_fd); 104 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGHDPLX, !efx->link_fd);
105 EFX_SET_OWORD_FIELD(reg, GMF_HSTDRPLT64, !efx->link_fd); 105 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTDRPLT64, !efx->link_fd);
106 EFX_SET_OWORD_FIELD(reg, GMF_HSTFLTRFRMDC_PAUSE, 0); 106 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTFLTRFRMDC_PAUSE, 0);
107 falcon_write(efx, &reg, GMF_CFG5_REG); 107 falcon_write(efx, &reg, FR_AB_GMF_CFG5);
108 udelay(10); 108 udelay(10);
109 109
110 /* MAC address */ 110 /* MAC address */
111 EFX_POPULATE_OWORD_4(reg, 111 EFX_POPULATE_OWORD_4(reg,
112 GM_HWADDR_5, efx->net_dev->dev_addr[5], 112 FRF_AB_GM_ADR_B0, efx->net_dev->dev_addr[5],
113 GM_HWADDR_4, efx->net_dev->dev_addr[4], 113 FRF_AB_GM_ADR_B1, efx->net_dev->dev_addr[4],
114 GM_HWADDR_3, efx->net_dev->dev_addr[3], 114 FRF_AB_GM_ADR_B2, efx->net_dev->dev_addr[3],
115 GM_HWADDR_2, efx->net_dev->dev_addr[2]); 115 FRF_AB_GM_ADR_B3, efx->net_dev->dev_addr[2]);
116 falcon_write(efx, &reg, GM_ADR1_REG); 116 falcon_write(efx, &reg, FR_AB_GM_ADR1);
117 udelay(10); 117 udelay(10);
118 EFX_POPULATE_OWORD_2(reg, 118 EFX_POPULATE_OWORD_2(reg,
119 GM_HWADDR_1, efx->net_dev->dev_addr[1], 119 FRF_AB_GM_ADR_B4, efx->net_dev->dev_addr[1],
120 GM_HWADDR_0, efx->net_dev->dev_addr[0]); 120 FRF_AB_GM_ADR_B5, efx->net_dev->dev_addr[0]);
121 falcon_write(efx, &reg, GM_ADR2_REG); 121 falcon_write(efx, &reg, FR_AB_GM_ADR2);
122 udelay(10); 122 udelay(10);
123 123
124 falcon_reconfigure_mac_wrapper(efx); 124 falcon_reconfigure_mac_wrapper(efx);
diff --git a/drivers/net/sfc/falcon_hwdefs.h b/drivers/net/sfc/falcon_hwdefs.h
deleted file mode 100644
index 13f3999449f..00000000000
--- a/drivers/net/sfc/falcon_hwdefs.h
+++ /dev/null
@@ -1,1332 +0,0 @@
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_FALCON_HWDEFS_H
12#define EFX_FALCON_HWDEFS_H
13
14/*
15 * Falcon hardware value definitions.
16 * Falcon is the internal codename for the SFC4000 controller that is
17 * present in SFE400X evaluation boards
18 */
19
20/**************************************************************************
21 *
22 * Falcon registers
23 *
24 **************************************************************************
25 */
26
27/* Address region register */
28#define ADR_REGION_REG_KER 0x00
29#define ADR_REGION0_LBN 0
30#define ADR_REGION0_WIDTH 18
31#define ADR_REGION1_LBN 32
32#define ADR_REGION1_WIDTH 18
33#define ADR_REGION2_LBN 64
34#define ADR_REGION2_WIDTH 18
35#define ADR_REGION3_LBN 96
36#define ADR_REGION3_WIDTH 18
37
38/* Interrupt enable register */
39#define INT_EN_REG_KER 0x0010
40#define KER_INT_KER_LBN 3
41#define KER_INT_KER_WIDTH 1
42#define DRV_INT_EN_KER_LBN 0
43#define DRV_INT_EN_KER_WIDTH 1
44
45/* Interrupt status address register */
46#define INT_ADR_REG_KER 0x0030
47#define NORM_INT_VEC_DIS_KER_LBN 64
48#define NORM_INT_VEC_DIS_KER_WIDTH 1
49#define INT_ADR_KER_LBN 0
50#define INT_ADR_KER_WIDTH EFX_DMA_TYPE_WIDTH(64) /* not 46 for this one */
51
52/* Interrupt status register (B0 only) */
53#define INT_ISR0_B0 0x90
54#define INT_ISR1_B0 0xA0
55
56/* Interrupt acknowledge register (A0/A1 only) */
57#define INT_ACK_REG_KER_A1 0x0050
58#define INT_ACK_DUMMY_DATA_LBN 0
59#define INT_ACK_DUMMY_DATA_WIDTH 32
60
61/* Interrupt acknowledge work-around register (A0/A1 only )*/
62#define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070
63
64/* SPI host command register */
65#define EE_SPI_HCMD_REG_KER 0x0100
66#define EE_SPI_HCMD_CMD_EN_LBN 31
67#define EE_SPI_HCMD_CMD_EN_WIDTH 1
68#define EE_WR_TIMER_ACTIVE_LBN 28
69#define EE_WR_TIMER_ACTIVE_WIDTH 1
70#define EE_SPI_HCMD_SF_SEL_LBN 24
71#define EE_SPI_HCMD_SF_SEL_WIDTH 1
72#define EE_SPI_EEPROM 0
73#define EE_SPI_FLASH 1
74#define EE_SPI_HCMD_DABCNT_LBN 16
75#define EE_SPI_HCMD_DABCNT_WIDTH 5
76#define EE_SPI_HCMD_READ_LBN 15
77#define EE_SPI_HCMD_READ_WIDTH 1
78#define EE_SPI_READ 1
79#define EE_SPI_WRITE 0
80#define EE_SPI_HCMD_DUBCNT_LBN 12
81#define EE_SPI_HCMD_DUBCNT_WIDTH 2
82#define EE_SPI_HCMD_ADBCNT_LBN 8
83#define EE_SPI_HCMD_ADBCNT_WIDTH 2
84#define EE_SPI_HCMD_ENC_LBN 0
85#define EE_SPI_HCMD_ENC_WIDTH 8
86
87/* SPI host address register */
88#define EE_SPI_HADR_REG_KER 0x0110
89#define EE_SPI_HADR_ADR_LBN 0
90#define EE_SPI_HADR_ADR_WIDTH 24
91
92/* SPI host data register */
93#define EE_SPI_HDATA_REG_KER 0x0120
94
95/* SPI/VPD config register */
96#define EE_VPD_CFG_REG_KER 0x0140
97#define EE_VPD_EN_LBN 0
98#define EE_VPD_EN_WIDTH 1
99#define EE_VPD_EN_AD9_MODE_LBN 1
100#define EE_VPD_EN_AD9_MODE_WIDTH 1
101#define EE_EE_CLOCK_DIV_LBN 112
102#define EE_EE_CLOCK_DIV_WIDTH 7
103#define EE_SF_CLOCK_DIV_LBN 120
104#define EE_SF_CLOCK_DIV_WIDTH 7
105
106/* PCIE CORE ACCESS REG */
107#define PCIE_CORE_ADDR_PCIE_DEVICE_CTRL_STAT 0x68
108#define PCIE_CORE_ADDR_PCIE_LINK_CTRL_STAT 0x70
109#define PCIE_CORE_ADDR_ACK_RPL_TIMER 0x700
110#define PCIE_CORE_ADDR_ACK_FREQ 0x70C
111
112/* NIC status register */
113#define NIC_STAT_REG 0x0200
114#define EE_STRAP_EN_LBN 31
115#define EE_STRAP_EN_WIDTH 1
116#define EE_STRAP_OVR_LBN 24
117#define EE_STRAP_OVR_WIDTH 4
118#define ONCHIP_SRAM_LBN 16
119#define ONCHIP_SRAM_WIDTH 1
120#define SF_PRST_LBN 9
121#define SF_PRST_WIDTH 1
122#define EE_PRST_LBN 8
123#define EE_PRST_WIDTH 1
124#define STRAP_PINS_LBN 0
125#define STRAP_PINS_WIDTH 3
126/* These bit definitions are extrapolated from the list of numerical
127 * values for STRAP_PINS.
128 */
129#define STRAP_10G_LBN 2
130#define STRAP_10G_WIDTH 1
131#define STRAP_PCIE_LBN 0
132#define STRAP_PCIE_WIDTH 1
133
134#define BOOTED_USING_NVDEVICE_LBN 3
135#define BOOTED_USING_NVDEVICE_WIDTH 1
136
137/* GPIO control register */
138#define GPIO_CTL_REG_KER 0x0210
139#define GPIO_USE_NIC_CLK_LBN (30)
140#define GPIO_USE_NIC_CLK_WIDTH (1)
141#define GPIO_OUTPUTS_LBN (16)
142#define GPIO_OUTPUTS_WIDTH (4)
143#define GPIO_INPUTS_LBN (8)
144#define GPIO_DIRECTION_LBN (24)
145#define GPIO_DIRECTION_WIDTH (4)
146#define GPIO_DIRECTION_OUT (1)
147#define GPIO_SRAM_SLEEP (1 << 1)
148
149#define GPIO3_OEN_LBN (GPIO_DIRECTION_LBN + 3)
150#define GPIO3_OEN_WIDTH 1
151#define GPIO2_OEN_LBN (GPIO_DIRECTION_LBN + 2)
152#define GPIO2_OEN_WIDTH 1
153#define GPIO1_OEN_LBN (GPIO_DIRECTION_LBN + 1)
154#define GPIO1_OEN_WIDTH 1
155#define GPIO0_OEN_LBN (GPIO_DIRECTION_LBN + 0)
156#define GPIO0_OEN_WIDTH 1
157
158#define GPIO3_OUT_LBN (GPIO_OUTPUTS_LBN + 3)
159#define GPIO3_OUT_WIDTH 1
160#define GPIO2_OUT_LBN (GPIO_OUTPUTS_LBN + 2)
161#define GPIO2_OUT_WIDTH 1
162#define GPIO1_OUT_LBN (GPIO_OUTPUTS_LBN + 1)
163#define GPIO1_OUT_WIDTH 1
164#define GPIO0_OUT_LBN (GPIO_OUTPUTS_LBN + 0)
165#define GPIO0_OUT_WIDTH 1
166
167#define GPIO3_IN_LBN (GPIO_INPUTS_LBN + 3)
168#define GPIO3_IN_WIDTH 1
169#define GPIO2_IN_WIDTH 1
170#define GPIO1_IN_WIDTH 1
171#define GPIO0_IN_LBN (GPIO_INPUTS_LBN + 0)
172#define GPIO0_IN_WIDTH 1
173
174/* Global control register */
175#define GLB_CTL_REG_KER 0x0220
176#define EXT_PHY_RST_CTL_LBN 63
177#define EXT_PHY_RST_CTL_WIDTH 1
178#define PCIE_SD_RST_CTL_LBN 61
179#define PCIE_SD_RST_CTL_WIDTH 1
180
181#define PCIE_NSTCK_RST_CTL_LBN 58
182#define PCIE_NSTCK_RST_CTL_WIDTH 1
183#define PCIE_CORE_RST_CTL_LBN 57
184#define PCIE_CORE_RST_CTL_WIDTH 1
185#define EE_RST_CTL_LBN 49
186#define EE_RST_CTL_WIDTH 1
187#define RST_XGRX_LBN 24
188#define RST_XGRX_WIDTH 1
189#define RST_XGTX_LBN 23
190#define RST_XGTX_WIDTH 1
191#define RST_EM_LBN 22
192#define RST_EM_WIDTH 1
193#define EXT_PHY_RST_DUR_LBN 1
194#define EXT_PHY_RST_DUR_WIDTH 3
195#define SWRST_LBN 0
196#define SWRST_WIDTH 1
197#define INCLUDE_IN_RESET 0
198#define EXCLUDE_FROM_RESET 1
199
200/* Fatal interrupt register */
201#define FATAL_INTR_REG_KER 0x0230
202#define RBUF_OWN_INT_KER_EN_LBN 39
203#define RBUF_OWN_INT_KER_EN_WIDTH 1
204#define TBUF_OWN_INT_KER_EN_LBN 38
205#define TBUF_OWN_INT_KER_EN_WIDTH 1
206#define ILL_ADR_INT_KER_EN_LBN 33
207#define ILL_ADR_INT_KER_EN_WIDTH 1
208#define MEM_PERR_INT_KER_LBN 8
209#define MEM_PERR_INT_KER_WIDTH 1
210#define INT_KER_ERROR_LBN 0
211#define INT_KER_ERROR_WIDTH 12
212
213#define DP_CTRL_REG 0x250
214#define FLS_EVQ_ID_LBN 0
215#define FLS_EVQ_ID_WIDTH 11
216
217#define MEM_STAT_REG_KER 0x260
218
219/* Debug probe register */
220#define DEBUG_BLK_SEL_MISC 7
221#define DEBUG_BLK_SEL_SERDES 6
222#define DEBUG_BLK_SEL_EM 5
223#define DEBUG_BLK_SEL_SR 4
224#define DEBUG_BLK_SEL_EV 3
225#define DEBUG_BLK_SEL_RX 2
226#define DEBUG_BLK_SEL_TX 1
227#define DEBUG_BLK_SEL_BIU 0
228
229/* FPGA build version */
230#define ALTERA_BUILD_REG_KER 0x0300
231#define VER_ALL_LBN 0
232#define VER_ALL_WIDTH 32
233
234/* Spare EEPROM bits register (flash 0x390) */
235#define SPARE_REG_KER 0x310
236#define MEM_PERR_EN_TX_DATA_LBN 72
237#define MEM_PERR_EN_TX_DATA_WIDTH 2
238
239/* Timer table for kernel access */
240#define TIMER_CMD_REG_KER 0x420
241#define TIMER_MODE_LBN 12
242#define TIMER_MODE_WIDTH 2
243#define TIMER_MODE_DIS 0
244#define TIMER_MODE_INT_HLDOFF 2
245#define TIMER_VAL_LBN 0
246#define TIMER_VAL_WIDTH 12
247
248/* Driver generated event register */
249#define DRV_EV_REG_KER 0x440
250#define DRV_EV_QID_LBN 64
251#define DRV_EV_QID_WIDTH 12
252#define DRV_EV_DATA_LBN 0
253#define DRV_EV_DATA_WIDTH 64
254
255/* Buffer table configuration register */
256#define BUF_TBL_CFG_REG_KER 0x600
257#define BUF_TBL_MODE_LBN 3
258#define BUF_TBL_MODE_WIDTH 1
259#define BUF_TBL_MODE_HALF 0
260#define BUF_TBL_MODE_FULL 1
261
262/* SRAM receive descriptor cache configuration register */
263#define SRM_RX_DC_CFG_REG_KER 0x610
264#define SRM_RX_DC_BASE_ADR_LBN 0
265#define SRM_RX_DC_BASE_ADR_WIDTH 21
266
267/* SRAM transmit descriptor cache configuration register */
268#define SRM_TX_DC_CFG_REG_KER 0x620
269#define SRM_TX_DC_BASE_ADR_LBN 0
270#define SRM_TX_DC_BASE_ADR_WIDTH 21
271
272/* SRAM configuration register */
273#define SRM_CFG_REG_KER 0x630
274#define SRAM_OOB_BT_INIT_EN_LBN 3
275#define SRAM_OOB_BT_INIT_EN_WIDTH 1
276#define SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0
277#define SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3
278#define SRM_NB_BSZ_1BANKS_2M 0
279#define SRM_NB_BSZ_1BANKS_4M 1
280#define SRM_NB_BSZ_1BANKS_8M 2
281#define SRM_NB_BSZ_DEFAULT 3 /* char driver will set the default */
282#define SRM_NB_BSZ_2BANKS_4M 4
283#define SRM_NB_BSZ_2BANKS_8M 5
284#define SRM_NB_BSZ_2BANKS_16M 6
285#define SRM_NB_BSZ_RESERVED 7
286
287/* Special buffer table update register */
288#define BUF_TBL_UPD_REG_KER 0x0650
289#define BUF_UPD_CMD_LBN 63
290#define BUF_UPD_CMD_WIDTH 1
291#define BUF_CLR_CMD_LBN 62
292#define BUF_CLR_CMD_WIDTH 1
293#define BUF_CLR_END_ID_LBN 32
294#define BUF_CLR_END_ID_WIDTH 20
295#define BUF_CLR_START_ID_LBN 0
296#define BUF_CLR_START_ID_WIDTH 20
297
298/* Receive configuration register */
299#define RX_CFG_REG_KER 0x800
300
301/* B0 */
302#define RX_INGR_EN_B0_LBN 47
303#define RX_INGR_EN_B0_WIDTH 1
304#define RX_DESC_PUSH_EN_B0_LBN 43
305#define RX_DESC_PUSH_EN_B0_WIDTH 1
306#define RX_XON_TX_TH_B0_LBN 33
307#define RX_XON_TX_TH_B0_WIDTH 5
308#define RX_XOFF_TX_TH_B0_LBN 28
309#define RX_XOFF_TX_TH_B0_WIDTH 5
310#define RX_USR_BUF_SIZE_B0_LBN 19
311#define RX_USR_BUF_SIZE_B0_WIDTH 9
312#define RX_XON_MAC_TH_B0_LBN 10
313#define RX_XON_MAC_TH_B0_WIDTH 9
314#define RX_XOFF_MAC_TH_B0_LBN 1
315#define RX_XOFF_MAC_TH_B0_WIDTH 9
316
317/* A1 */
318#define RX_DESC_PUSH_EN_A1_LBN 35
319#define RX_DESC_PUSH_EN_A1_WIDTH 1
320#define RX_XON_TX_TH_A1_LBN 25
321#define RX_XON_TX_TH_A1_WIDTH 5
322#define RX_XOFF_TX_TH_A1_LBN 20
323#define RX_XOFF_TX_TH_A1_WIDTH 5
324#define RX_USR_BUF_SIZE_A1_LBN 11
325#define RX_USR_BUF_SIZE_A1_WIDTH 9
326#define RX_XON_MAC_TH_A1_LBN 6
327#define RX_XON_MAC_TH_A1_WIDTH 5
328#define RX_XOFF_MAC_TH_A1_LBN 1
329#define RX_XOFF_MAC_TH_A1_WIDTH 5
330
331#define RX_XOFF_MAC_EN_LBN 0
332#define RX_XOFF_MAC_EN_WIDTH 1
333
334/* Receive filter control register */
335#define RX_FILTER_CTL_REG 0x810
336#define UDP_FULL_SRCH_LIMIT_LBN 32
337#define UDP_FULL_SRCH_LIMIT_WIDTH 8
338#define NUM_KER_LBN 24
339#define NUM_KER_WIDTH 2
340#define UDP_WILD_SRCH_LIMIT_LBN 16
341#define UDP_WILD_SRCH_LIMIT_WIDTH 8
342#define TCP_WILD_SRCH_LIMIT_LBN 8
343#define TCP_WILD_SRCH_LIMIT_WIDTH 8
344#define TCP_FULL_SRCH_LIMIT_LBN 0
345#define TCP_FULL_SRCH_LIMIT_WIDTH 8
346
347/* RX queue flush register */
348#define RX_FLUSH_DESCQ_REG_KER 0x0820
349#define RX_FLUSH_DESCQ_CMD_LBN 24
350#define RX_FLUSH_DESCQ_CMD_WIDTH 1
351#define RX_FLUSH_DESCQ_LBN 0
352#define RX_FLUSH_DESCQ_WIDTH 12
353
354/* Receive descriptor update register */
355#define RX_DESC_UPD_REG_KER_DWORD (0x830 + 12)
356#define RX_DESC_WPTR_DWORD_LBN 0
357#define RX_DESC_WPTR_DWORD_WIDTH 12
358
359/* Receive descriptor cache configuration register */
360#define RX_DC_CFG_REG_KER 0x840
361#define RX_DC_SIZE_LBN 0
362#define RX_DC_SIZE_WIDTH 2
363
364#define RX_DC_PF_WM_REG_KER 0x850
365#define RX_DC_PF_LWM_LBN 0
366#define RX_DC_PF_LWM_WIDTH 6
367
368/* RX no descriptor drop counter */
369#define RX_NODESC_DROP_REG_KER 0x880
370#define RX_NODESC_DROP_CNT_LBN 0
371#define RX_NODESC_DROP_CNT_WIDTH 16
372
373/* RX black magic register */
374#define RX_SELF_RST_REG_KER 0x890
375#define RX_ISCSI_DIS_LBN 17
376#define RX_ISCSI_DIS_WIDTH 1
377#define RX_NODESC_WAIT_DIS_LBN 9
378#define RX_NODESC_WAIT_DIS_WIDTH 1
379#define RX_RECOVERY_EN_LBN 8
380#define RX_RECOVERY_EN_WIDTH 1
381
382/* TX queue flush register */
383#define TX_FLUSH_DESCQ_REG_KER 0x0a00
384#define TX_FLUSH_DESCQ_CMD_LBN 12
385#define TX_FLUSH_DESCQ_CMD_WIDTH 1
386#define TX_FLUSH_DESCQ_LBN 0
387#define TX_FLUSH_DESCQ_WIDTH 12
388
389/* Transmit descriptor update register */
390#define TX_DESC_UPD_REG_KER_DWORD (0xa10 + 12)
391#define TX_DESC_WPTR_DWORD_LBN 0
392#define TX_DESC_WPTR_DWORD_WIDTH 12
393
394/* Transmit descriptor cache configuration register */
395#define TX_DC_CFG_REG_KER 0xa20
396#define TX_DC_SIZE_LBN 0
397#define TX_DC_SIZE_WIDTH 2
398
399/* Transmit checksum configuration register (A0/A1 only) */
400#define TX_CHKSM_CFG_REG_KER_A1 0xa30
401
402/* Transmit configuration register */
403#define TX_CFG_REG_KER 0xa50
404#define TX_NO_EOP_DISC_EN_LBN 5
405#define TX_NO_EOP_DISC_EN_WIDTH 1
406
407/* Transmit configuration register 2 */
408#define TX_CFG2_REG_KER 0xa80
409#define TX_CSR_PUSH_EN_LBN 89
410#define TX_CSR_PUSH_EN_WIDTH 1
411#define TX_RX_SPACER_LBN 64
412#define TX_RX_SPACER_WIDTH 8
413#define TX_SW_EV_EN_LBN 59
414#define TX_SW_EV_EN_WIDTH 1
415#define TX_RX_SPACER_EN_LBN 57
416#define TX_RX_SPACER_EN_WIDTH 1
417#define TX_PREF_THRESHOLD_LBN 19
418#define TX_PREF_THRESHOLD_WIDTH 2
419#define TX_ONE_PKT_PER_Q_LBN 18
420#define TX_ONE_PKT_PER_Q_WIDTH 1
421#define TX_DIS_NON_IP_EV_LBN 17
422#define TX_DIS_NON_IP_EV_WIDTH 1
423#define TX_FLUSH_MIN_LEN_EN_B0_LBN 7
424#define TX_FLUSH_MIN_LEN_EN_B0_WIDTH 1
425
426/* PHY management transmit data register */
427#define MD_TXD_REG_KER 0xc00
428#define MD_TXD_LBN 0
429#define MD_TXD_WIDTH 16
430
431/* PHY management receive data register */
432#define MD_RXD_REG_KER 0xc10
433#define MD_RXD_LBN 0
434#define MD_RXD_WIDTH 16
435
436/* PHY management configuration & status register */
437#define MD_CS_REG_KER 0xc20
438#define MD_GC_LBN 4
439#define MD_GC_WIDTH 1
440#define MD_RIC_LBN 2
441#define MD_RIC_WIDTH 1
442#define MD_RDC_LBN 1
443#define MD_RDC_WIDTH 1
444#define MD_WRC_LBN 0
445#define MD_WRC_WIDTH 1
446
447/* PHY management PHY address register */
448#define MD_PHY_ADR_REG_KER 0xc30
449#define MD_PHY_ADR_LBN 0
450#define MD_PHY_ADR_WIDTH 16
451
452/* PHY management ID register */
453#define MD_ID_REG_KER 0xc40
454#define MD_PRT_ADR_LBN 11
455#define MD_PRT_ADR_WIDTH 5
456#define MD_DEV_ADR_LBN 6
457#define MD_DEV_ADR_WIDTH 5
458
459/* PHY management status & mask register (DWORD read only) */
460#define MD_STAT_REG_KER 0xc50
461#define MD_BSERR_LBN 2
462#define MD_BSERR_WIDTH 1
463#define MD_LNFL_LBN 1
464#define MD_LNFL_WIDTH 1
465#define MD_BSY_LBN 0
466#define MD_BSY_WIDTH 1
467
468/* Port 0 and 1 MAC stats registers */
469#define MAC0_STAT_DMA_REG_KER 0xc60
470#define MAC_STAT_DMA_CMD_LBN 48
471#define MAC_STAT_DMA_CMD_WIDTH 1
472#define MAC_STAT_DMA_ADR_LBN 0
473#define MAC_STAT_DMA_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46)
474
475/* Port 0 and 1 MAC control registers */
476#define MAC0_CTRL_REG_KER 0xc80
477#define MAC_XOFF_VAL_LBN 16
478#define MAC_XOFF_VAL_WIDTH 16
479#define TXFIFO_DRAIN_EN_B0_LBN 7
480#define TXFIFO_DRAIN_EN_B0_WIDTH 1
481#define MAC_BCAD_ACPT_LBN 4
482#define MAC_BCAD_ACPT_WIDTH 1
483#define MAC_UC_PROM_LBN 3
484#define MAC_UC_PROM_WIDTH 1
485#define MAC_LINK_STATUS_LBN 2
486#define MAC_LINK_STATUS_WIDTH 1
487#define MAC_SPEED_LBN 0
488#define MAC_SPEED_WIDTH 2
489
490/* 10G XAUI XGXS default values */
491#define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */
492#define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */
493#define XX_SD_CTL_DRV_DEFAULT 0 /* 20mA */
494
495/* Multicast address hash table */
496#define MAC_MCAST_HASH_REG0_KER 0xca0
497#define MAC_MCAST_HASH_REG1_KER 0xcb0
498
499/* GMAC configuration register 1 */
500#define GM_CFG1_REG 0xe00
501#define GM_SW_RST_LBN 31
502#define GM_SW_RST_WIDTH 1
503#define GM_LOOP_LBN 8
504#define GM_LOOP_WIDTH 1
505#define GM_RX_FC_EN_LBN 5
506#define GM_RX_FC_EN_WIDTH 1
507#define GM_TX_FC_EN_LBN 4
508#define GM_TX_FC_EN_WIDTH 1
509#define GM_RX_EN_LBN 2
510#define GM_RX_EN_WIDTH 1
511#define GM_TX_EN_LBN 0
512#define GM_TX_EN_WIDTH 1
513
514/* GMAC configuration register 2 */
515#define GM_CFG2_REG 0xe10
516#define GM_PAMBL_LEN_LBN 12
517#define GM_PAMBL_LEN_WIDTH 4
518#define GM_IF_MODE_LBN 8
519#define GM_IF_MODE_WIDTH 2
520#define GM_LEN_CHK_LBN 4
521#define GM_LEN_CHK_WIDTH 1
522#define GM_PAD_CRC_EN_LBN 2
523#define GM_PAD_CRC_EN_WIDTH 1
524#define GM_FD_LBN 0
525#define GM_FD_WIDTH 1
526
527/* GMAC maximum frame length register */
528#define GM_MAX_FLEN_REG 0xe40
529#define GM_MAX_FLEN_LBN 0
530#define GM_MAX_FLEN_WIDTH 16
531
532/* GMAC station address register 1 */
533#define GM_ADR1_REG 0xf00
534#define GM_HWADDR_5_LBN 24
535#define GM_HWADDR_5_WIDTH 8
536#define GM_HWADDR_4_LBN 16
537#define GM_HWADDR_4_WIDTH 8
538#define GM_HWADDR_3_LBN 8
539#define GM_HWADDR_3_WIDTH 8
540#define GM_HWADDR_2_LBN 0
541#define GM_HWADDR_2_WIDTH 8
542
543/* GMAC station address register 2 */
544#define GM_ADR2_REG 0xf10
545#define GM_HWADDR_1_LBN 24
546#define GM_HWADDR_1_WIDTH 8
547#define GM_HWADDR_0_LBN 16
548#define GM_HWADDR_0_WIDTH 8
549
550/* GMAC FIFO configuration register 0 */
551#define GMF_CFG0_REG 0xf20
552#define GMF_FTFENREQ_LBN 12
553#define GMF_FTFENREQ_WIDTH 1
554#define GMF_STFENREQ_LBN 11
555#define GMF_STFENREQ_WIDTH 1
556#define GMF_FRFENREQ_LBN 10
557#define GMF_FRFENREQ_WIDTH 1
558#define GMF_SRFENREQ_LBN 9
559#define GMF_SRFENREQ_WIDTH 1
560#define GMF_WTMENREQ_LBN 8
561#define GMF_WTMENREQ_WIDTH 1
562
563/* GMAC FIFO configuration register 1 */
564#define GMF_CFG1_REG 0xf30
565#define GMF_CFGFRTH_LBN 16
566#define GMF_CFGFRTH_WIDTH 5
567#define GMF_CFGXOFFRTX_LBN 0
568#define GMF_CFGXOFFRTX_WIDTH 16
569
570/* GMAC FIFO configuration register 2 */
571#define GMF_CFG2_REG 0xf40
572#define GMF_CFGHWM_LBN 16
573#define GMF_CFGHWM_WIDTH 6
574#define GMF_CFGLWM_LBN 0
575#define GMF_CFGLWM_WIDTH 6
576
577/* GMAC FIFO configuration register 3 */
578#define GMF_CFG3_REG 0xf50
579#define GMF_CFGHWMFT_LBN 16
580#define GMF_CFGHWMFT_WIDTH 6
581#define GMF_CFGFTTH_LBN 0
582#define GMF_CFGFTTH_WIDTH 6
583
584/* GMAC FIFO configuration register 4 */
585#define GMF_CFG4_REG 0xf60
586#define GMF_HSTFLTRFRM_PAUSE_LBN 12
587#define GMF_HSTFLTRFRM_PAUSE_WIDTH 12
588
589/* GMAC FIFO configuration register 5 */
590#define GMF_CFG5_REG 0xf70
591#define GMF_CFGHDPLX_LBN 22
592#define GMF_CFGHDPLX_WIDTH 1
593#define GMF_CFGBYTMODE_LBN 19
594#define GMF_CFGBYTMODE_WIDTH 1
595#define GMF_HSTDRPLT64_LBN 18
596#define GMF_HSTDRPLT64_WIDTH 1
597#define GMF_HSTFLTRFRMDC_PAUSE_LBN 12
598#define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
599
600/* XGMAC address register low */
601#define XM_ADR_LO_REG 0x1200
602#define XM_ADR_3_LBN 24
603#define XM_ADR_3_WIDTH 8
604#define XM_ADR_2_LBN 16
605#define XM_ADR_2_WIDTH 8
606#define XM_ADR_1_LBN 8
607#define XM_ADR_1_WIDTH 8
608#define XM_ADR_0_LBN 0
609#define XM_ADR_0_WIDTH 8
610
611/* XGMAC address register high */
612#define XM_ADR_HI_REG 0x1210
613#define XM_ADR_5_LBN 8
614#define XM_ADR_5_WIDTH 8
615#define XM_ADR_4_LBN 0
616#define XM_ADR_4_WIDTH 8
617
618/* XGMAC global configuration */
619#define XM_GLB_CFG_REG 0x1220
620#define XM_RX_STAT_EN_LBN 11
621#define XM_RX_STAT_EN_WIDTH 1
622#define XM_TX_STAT_EN_LBN 10
623#define XM_TX_STAT_EN_WIDTH 1
624#define XM_RX_JUMBO_MODE_LBN 6
625#define XM_RX_JUMBO_MODE_WIDTH 1
626#define XM_INTCLR_MODE_LBN 3
627#define XM_INTCLR_MODE_WIDTH 1
628#define XM_CORE_RST_LBN 0
629#define XM_CORE_RST_WIDTH 1
630
631/* XGMAC transmit configuration */
632#define XM_TX_CFG_REG 0x1230
633#define XM_IPG_LBN 16
634#define XM_IPG_WIDTH 4
635#define XM_FCNTL_LBN 10
636#define XM_FCNTL_WIDTH 1
637#define XM_TXCRC_LBN 8
638#define XM_TXCRC_WIDTH 1
639#define XM_AUTO_PAD_LBN 5
640#define XM_AUTO_PAD_WIDTH 1
641#define XM_TX_PRMBL_LBN 2
642#define XM_TX_PRMBL_WIDTH 1
643#define XM_TXEN_LBN 1
644#define XM_TXEN_WIDTH 1
645
646/* XGMAC receive configuration */
647#define XM_RX_CFG_REG 0x1240
648#define XM_PASS_CRC_ERR_LBN 25
649#define XM_PASS_CRC_ERR_WIDTH 1
650#define XM_ACPT_ALL_MCAST_LBN 11
651#define XM_ACPT_ALL_MCAST_WIDTH 1
652#define XM_ACPT_ALL_UCAST_LBN 9
653#define XM_ACPT_ALL_UCAST_WIDTH 1
654#define XM_AUTO_DEPAD_LBN 8
655#define XM_AUTO_DEPAD_WIDTH 1
656#define XM_RXEN_LBN 1
657#define XM_RXEN_WIDTH 1
658
659/* XGMAC management interrupt mask register */
660#define XM_MGT_INT_MSK_REG_B0 0x1250
661#define XM_MSK_PRMBLE_ERR_LBN 2
662#define XM_MSK_PRMBLE_ERR_WIDTH 1
663#define XM_MSK_RMTFLT_LBN 1
664#define XM_MSK_RMTFLT_WIDTH 1
665#define XM_MSK_LCLFLT_LBN 0
666#define XM_MSK_LCLFLT_WIDTH 1
667
668/* XGMAC flow control register */
669#define XM_FC_REG 0x1270
670#define XM_PAUSE_TIME_LBN 16
671#define XM_PAUSE_TIME_WIDTH 16
672#define XM_DIS_FCNTL_LBN 0
673#define XM_DIS_FCNTL_WIDTH 1
674
675/* XGMAC pause time count register */
676#define XM_PAUSE_TIME_REG 0x1290
677
678/* XGMAC transmit parameter register */
679#define XM_TX_PARAM_REG 0x012d0
680#define XM_TX_JUMBO_MODE_LBN 31
681#define XM_TX_JUMBO_MODE_WIDTH 1
682#define XM_MAX_TX_FRM_SIZE_LBN 16
683#define XM_MAX_TX_FRM_SIZE_WIDTH 14
684
685/* XGMAC receive parameter register */
686#define XM_RX_PARAM_REG 0x12e0
687#define XM_MAX_RX_FRM_SIZE_LBN 0
688#define XM_MAX_RX_FRM_SIZE_WIDTH 14
689
690/* XGMAC management interrupt status register */
691#define XM_MGT_INT_REG_B0 0x12f0
692#define XM_PRMBLE_ERR 2
693#define XM_PRMBLE_WIDTH 1
694#define XM_RMTFLT_LBN 1
695#define XM_RMTFLT_WIDTH 1
696#define XM_LCLFLT_LBN 0
697#define XM_LCLFLT_WIDTH 1
698
699/* XGXS/XAUI powerdown/reset register */
700#define XX_PWR_RST_REG 0x1300
701
702#define XX_SD_RST_ACT_LBN 16
703#define XX_SD_RST_ACT_WIDTH 1
704#define XX_PWRDND_EN_LBN 15
705#define XX_PWRDND_EN_WIDTH 1
706#define XX_PWRDNC_EN_LBN 14
707#define XX_PWRDNC_EN_WIDTH 1
708#define XX_PWRDNB_EN_LBN 13
709#define XX_PWRDNB_EN_WIDTH 1
710#define XX_PWRDNA_EN_LBN 12
711#define XX_PWRDNA_EN_WIDTH 1
712#define XX_RSTPLLCD_EN_LBN 9
713#define XX_RSTPLLCD_EN_WIDTH 1
714#define XX_RSTPLLAB_EN_LBN 8
715#define XX_RSTPLLAB_EN_WIDTH 1
716#define XX_RESETD_EN_LBN 7
717#define XX_RESETD_EN_WIDTH 1
718#define XX_RESETC_EN_LBN 6
719#define XX_RESETC_EN_WIDTH 1
720#define XX_RESETB_EN_LBN 5
721#define XX_RESETB_EN_WIDTH 1
722#define XX_RESETA_EN_LBN 4
723#define XX_RESETA_EN_WIDTH 1
724#define XX_RSTXGXSRX_EN_LBN 2
725#define XX_RSTXGXSRX_EN_WIDTH 1
726#define XX_RSTXGXSTX_EN_LBN 1
727#define XX_RSTXGXSTX_EN_WIDTH 1
728#define XX_RST_XX_EN_LBN 0
729#define XX_RST_XX_EN_WIDTH 1
730
731/* XGXS/XAUI powerdown/reset control register */
732#define XX_SD_CTL_REG 0x1310
733#define XX_HIDRVD_LBN 15
734#define XX_HIDRVD_WIDTH 1
735#define XX_LODRVD_LBN 14
736#define XX_LODRVD_WIDTH 1
737#define XX_HIDRVC_LBN 13
738#define XX_HIDRVC_WIDTH 1
739#define XX_LODRVC_LBN 12
740#define XX_LODRVC_WIDTH 1
741#define XX_HIDRVB_LBN 11
742#define XX_HIDRVB_WIDTH 1
743#define XX_LODRVB_LBN 10
744#define XX_LODRVB_WIDTH 1
745#define XX_HIDRVA_LBN 9
746#define XX_HIDRVA_WIDTH 1
747#define XX_LODRVA_LBN 8
748#define XX_LODRVA_WIDTH 1
749#define XX_LPBKD_LBN 3
750#define XX_LPBKD_WIDTH 1
751#define XX_LPBKC_LBN 2
752#define XX_LPBKC_WIDTH 1
753#define XX_LPBKB_LBN 1
754#define XX_LPBKB_WIDTH 1
755#define XX_LPBKA_LBN 0
756#define XX_LPBKA_WIDTH 1
757
758#define XX_TXDRV_CTL_REG 0x1320
759#define XX_DEQD_LBN 28
760#define XX_DEQD_WIDTH 4
761#define XX_DEQC_LBN 24
762#define XX_DEQC_WIDTH 4
763#define XX_DEQB_LBN 20
764#define XX_DEQB_WIDTH 4
765#define XX_DEQA_LBN 16
766#define XX_DEQA_WIDTH 4
767#define XX_DTXD_LBN 12
768#define XX_DTXD_WIDTH 4
769#define XX_DTXC_LBN 8
770#define XX_DTXC_WIDTH 4
771#define XX_DTXB_LBN 4
772#define XX_DTXB_WIDTH 4
773#define XX_DTXA_LBN 0
774#define XX_DTXA_WIDTH 4
775
776/* XAUI XGXS core status register */
777#define XX_CORE_STAT_REG 0x1360
778#define XX_FORCE_SIG_LBN 24
779#define XX_FORCE_SIG_WIDTH 8
780#define XX_FORCE_SIG_DECODE_FORCED 0xff
781#define XX_XGXS_LB_EN_LBN 23
782#define XX_XGXS_LB_EN_WIDTH 1
783#define XX_XGMII_LB_EN_LBN 22
784#define XX_XGMII_LB_EN_WIDTH 1
785#define XX_ALIGN_DONE_LBN 20
786#define XX_ALIGN_DONE_WIDTH 1
787#define XX_SYNC_STAT_LBN 16
788#define XX_SYNC_STAT_WIDTH 4
789#define XX_SYNC_STAT_DECODE_SYNCED 0xf
790#define XX_COMMA_DET_LBN 12
791#define XX_COMMA_DET_WIDTH 4
792#define XX_COMMA_DET_DECODE_DETECTED 0xf
793#define XX_COMMA_DET_RESET 0xf
794#define XX_CHARERR_LBN 4
795#define XX_CHARERR_WIDTH 4
796#define XX_CHARERR_RESET 0xf
797#define XX_DISPERR_LBN 0
798#define XX_DISPERR_WIDTH 4
799#define XX_DISPERR_RESET 0xf
800
801/* Receive filter table */
802#define RX_FILTER_TBL0 0xF00000
803
804/* Receive descriptor pointer table */
805#define RX_DESC_PTR_TBL_KER_A1 0x11800
806#define RX_DESC_PTR_TBL_KER_B0 0xF40000
807#define RX_DESC_PTR_TBL_KER_P0 0x900
808#define RX_ISCSI_DDIG_EN_LBN 88
809#define RX_ISCSI_DDIG_EN_WIDTH 1
810#define RX_ISCSI_HDIG_EN_LBN 87
811#define RX_ISCSI_HDIG_EN_WIDTH 1
812#define RX_DESCQ_BUF_BASE_ID_LBN 36
813#define RX_DESCQ_BUF_BASE_ID_WIDTH 20
814#define RX_DESCQ_EVQ_ID_LBN 24
815#define RX_DESCQ_EVQ_ID_WIDTH 12
816#define RX_DESCQ_OWNER_ID_LBN 10
817#define RX_DESCQ_OWNER_ID_WIDTH 14
818#define RX_DESCQ_LABEL_LBN 5
819#define RX_DESCQ_LABEL_WIDTH 5
820#define RX_DESCQ_SIZE_LBN 3
821#define RX_DESCQ_SIZE_WIDTH 2
822#define RX_DESCQ_SIZE_4K 3
823#define RX_DESCQ_SIZE_2K 2
824#define RX_DESCQ_SIZE_1K 1
825#define RX_DESCQ_SIZE_512 0
826#define RX_DESCQ_TYPE_LBN 2
827#define RX_DESCQ_TYPE_WIDTH 1
828#define RX_DESCQ_JUMBO_LBN 1
829#define RX_DESCQ_JUMBO_WIDTH 1
830#define RX_DESCQ_EN_LBN 0
831#define RX_DESCQ_EN_WIDTH 1
832
833/* Transmit descriptor pointer table */
834#define TX_DESC_PTR_TBL_KER_A1 0x11900
835#define TX_DESC_PTR_TBL_KER_B0 0xF50000
836#define TX_DESC_PTR_TBL_KER_P0 0xa40
837#define TX_NON_IP_DROP_DIS_B0_LBN 91
838#define TX_NON_IP_DROP_DIS_B0_WIDTH 1
839#define TX_IP_CHKSM_DIS_B0_LBN 90
840#define TX_IP_CHKSM_DIS_B0_WIDTH 1
841#define TX_TCP_CHKSM_DIS_B0_LBN 89
842#define TX_TCP_CHKSM_DIS_B0_WIDTH 1
843#define TX_DESCQ_EN_LBN 88
844#define TX_DESCQ_EN_WIDTH 1
845#define TX_ISCSI_DDIG_EN_LBN 87
846#define TX_ISCSI_DDIG_EN_WIDTH 1
847#define TX_ISCSI_HDIG_EN_LBN 86
848#define TX_ISCSI_HDIG_EN_WIDTH 1
849#define TX_DESCQ_BUF_BASE_ID_LBN 36
850#define TX_DESCQ_BUF_BASE_ID_WIDTH 20
851#define TX_DESCQ_EVQ_ID_LBN 24
852#define TX_DESCQ_EVQ_ID_WIDTH 12
853#define TX_DESCQ_OWNER_ID_LBN 10
854#define TX_DESCQ_OWNER_ID_WIDTH 14
855#define TX_DESCQ_LABEL_LBN 5
856#define TX_DESCQ_LABEL_WIDTH 5
857#define TX_DESCQ_SIZE_LBN 3
858#define TX_DESCQ_SIZE_WIDTH 2
859#define TX_DESCQ_SIZE_4K 3
860#define TX_DESCQ_SIZE_2K 2
861#define TX_DESCQ_SIZE_1K 1
862#define TX_DESCQ_SIZE_512 0
863#define TX_DESCQ_TYPE_LBN 1
864#define TX_DESCQ_TYPE_WIDTH 2
865
866/* Event queue pointer */
867#define EVQ_PTR_TBL_KER_A1 0x11a00
868#define EVQ_PTR_TBL_KER_B0 0xf60000
869#define EVQ_PTR_TBL_KER_P0 0x500
870#define EVQ_EN_LBN 23
871#define EVQ_EN_WIDTH 1
872#define EVQ_SIZE_LBN 20
873#define EVQ_SIZE_WIDTH 3
874#define EVQ_SIZE_32K 6
875#define EVQ_SIZE_16K 5
876#define EVQ_SIZE_8K 4
877#define EVQ_SIZE_4K 3
878#define EVQ_SIZE_2K 2
879#define EVQ_SIZE_1K 1
880#define EVQ_SIZE_512 0
881#define EVQ_BUF_BASE_ID_LBN 0
882#define EVQ_BUF_BASE_ID_WIDTH 20
883
884/* Event queue read pointer */
885#define EVQ_RPTR_REG_KER_A1 0x11b00
886#define EVQ_RPTR_REG_KER_B0 0xfa0000
887#define EVQ_RPTR_REG_KER_DWORD (EVQ_RPTR_REG_KER + 0)
888#define EVQ_RPTR_DWORD_LBN 0
889#define EVQ_RPTR_DWORD_WIDTH 14
890
891/* RSS indirection table */
892#define RX_RSS_INDIR_TBL_B0 0xFB0000
893#define RX_RSS_INDIR_ENT_B0_LBN 0
894#define RX_RSS_INDIR_ENT_B0_WIDTH 6
895
896/* Special buffer descriptors (full-mode) */
897#define BUF_FULL_TBL_KER_A1 0x8000
898#define BUF_FULL_TBL_KER_B0 0x800000
899#define IP_DAT_BUF_SIZE_LBN 50
900#define IP_DAT_BUF_SIZE_WIDTH 1
901#define IP_DAT_BUF_SIZE_8K 1
902#define IP_DAT_BUF_SIZE_4K 0
903#define BUF_ADR_REGION_LBN 48
904#define BUF_ADR_REGION_WIDTH 2
905#define BUF_ADR_FBUF_LBN 14
906#define BUF_ADR_FBUF_WIDTH 34
907#define BUF_OWNER_ID_FBUF_LBN 0
908#define BUF_OWNER_ID_FBUF_WIDTH 14
909
910/* Transmit descriptor */
911#define TX_KER_PORT_LBN 63
912#define TX_KER_PORT_WIDTH 1
913#define TX_KER_CONT_LBN 62
914#define TX_KER_CONT_WIDTH 1
915#define TX_KER_BYTE_CNT_LBN 48
916#define TX_KER_BYTE_CNT_WIDTH 14
917#define TX_KER_BUF_REGION_LBN 46
918#define TX_KER_BUF_REGION_WIDTH 2
919#define TX_KER_BUF_REGION0_DECODE 0
920#define TX_KER_BUF_REGION1_DECODE 1
921#define TX_KER_BUF_REGION2_DECODE 2
922#define TX_KER_BUF_REGION3_DECODE 3
923#define TX_KER_BUF_ADR_LBN 0
924#define TX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46)
925
926/* Receive descriptor */
927#define RX_KER_BUF_SIZE_LBN 48
928#define RX_KER_BUF_SIZE_WIDTH 14
929#define RX_KER_BUF_REGION_LBN 46
930#define RX_KER_BUF_REGION_WIDTH 2
931#define RX_KER_BUF_REGION0_DECODE 0
932#define RX_KER_BUF_REGION1_DECODE 1
933#define RX_KER_BUF_REGION2_DECODE 2
934#define RX_KER_BUF_REGION3_DECODE 3
935#define RX_KER_BUF_ADR_LBN 0
936#define RX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46)
937
938/**************************************************************************
939 *
940 * Falcon events
941 *
942 **************************************************************************
943 */
944
945/* Event queue entries */
946#define EV_CODE_LBN 60
947#define EV_CODE_WIDTH 4
948#define RX_IP_EV_DECODE 0
949#define TX_IP_EV_DECODE 2
950#define DRIVER_EV_DECODE 5
951#define GLOBAL_EV_DECODE 6
952#define DRV_GEN_EV_DECODE 7
953#define WHOLE_EVENT_LBN 0
954#define WHOLE_EVENT_WIDTH 64
955
956/* Receive events */
957#define RX_EV_PKT_OK_LBN 56
958#define RX_EV_PKT_OK_WIDTH 1
959#define RX_EV_PAUSE_FRM_ERR_LBN 55
960#define RX_EV_PAUSE_FRM_ERR_WIDTH 1
961#define RX_EV_BUF_OWNER_ID_ERR_LBN 54
962#define RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
963#define RX_EV_IF_FRAG_ERR_LBN 53
964#define RX_EV_IF_FRAG_ERR_WIDTH 1
965#define RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
966#define RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
967#define RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
968#define RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
969#define RX_EV_ETH_CRC_ERR_LBN 50
970#define RX_EV_ETH_CRC_ERR_WIDTH 1
971#define RX_EV_FRM_TRUNC_LBN 49
972#define RX_EV_FRM_TRUNC_WIDTH 1
973#define RX_EV_DRIB_NIB_LBN 48
974#define RX_EV_DRIB_NIB_WIDTH 1
975#define RX_EV_TOBE_DISC_LBN 47
976#define RX_EV_TOBE_DISC_WIDTH 1
977#define RX_EV_PKT_TYPE_LBN 44
978#define RX_EV_PKT_TYPE_WIDTH 3
979#define RX_EV_PKT_TYPE_ETH_DECODE 0
980#define RX_EV_PKT_TYPE_LLC_DECODE 1
981#define RX_EV_PKT_TYPE_JUMBO_DECODE 2
982#define RX_EV_PKT_TYPE_VLAN_DECODE 3
983#define RX_EV_PKT_TYPE_VLAN_LLC_DECODE 4
984#define RX_EV_PKT_TYPE_VLAN_JUMBO_DECODE 5
985#define RX_EV_HDR_TYPE_LBN 42
986#define RX_EV_HDR_TYPE_WIDTH 2
987#define RX_EV_HDR_TYPE_TCP_IPV4_DECODE 0
988#define RX_EV_HDR_TYPE_UDP_IPV4_DECODE 1
989#define RX_EV_HDR_TYPE_OTHER_IP_DECODE 2
990#define RX_EV_HDR_TYPE_NON_IP_DECODE 3
991#define RX_EV_HDR_TYPE_HAS_CHECKSUMS(hdr_type) \
992 ((hdr_type) <= RX_EV_HDR_TYPE_UDP_IPV4_DECODE)
993#define RX_EV_MCAST_HASH_MATCH_LBN 40
994#define RX_EV_MCAST_HASH_MATCH_WIDTH 1
995#define RX_EV_MCAST_PKT_LBN 39
996#define RX_EV_MCAST_PKT_WIDTH 1
997#define RX_EV_Q_LABEL_LBN 32
998#define RX_EV_Q_LABEL_WIDTH 5
999#define RX_EV_JUMBO_CONT_LBN 31
1000#define RX_EV_JUMBO_CONT_WIDTH 1
1001#define RX_EV_BYTE_CNT_LBN 16
1002#define RX_EV_BYTE_CNT_WIDTH 14
1003#define RX_EV_SOP_LBN 15
1004#define RX_EV_SOP_WIDTH 1
1005#define RX_EV_DESC_PTR_LBN 0
1006#define RX_EV_DESC_PTR_WIDTH 12
1007
1008/* Transmit events */
1009#define TX_EV_PKT_ERR_LBN 38
1010#define TX_EV_PKT_ERR_WIDTH 1
1011#define TX_EV_Q_LABEL_LBN 32
1012#define TX_EV_Q_LABEL_WIDTH 5
1013#define TX_EV_WQ_FF_FULL_LBN 15
1014#define TX_EV_WQ_FF_FULL_WIDTH 1
1015#define TX_EV_COMP_LBN 12
1016#define TX_EV_COMP_WIDTH 1
1017#define TX_EV_DESC_PTR_LBN 0
1018#define TX_EV_DESC_PTR_WIDTH 12
1019
1020/* Driver events */
1021#define DRIVER_EV_SUB_CODE_LBN 56
1022#define DRIVER_EV_SUB_CODE_WIDTH 4
1023#define DRIVER_EV_SUB_DATA_LBN 0
1024#define DRIVER_EV_SUB_DATA_WIDTH 14
1025#define TX_DESCQ_FLS_DONE_EV_DECODE 0
1026#define RX_DESCQ_FLS_DONE_EV_DECODE 1
1027#define EVQ_INIT_DONE_EV_DECODE 2
1028#define EVQ_NOT_EN_EV_DECODE 3
1029#define RX_DESCQ_FLSFF_OVFL_EV_DECODE 4
1030#define SRM_UPD_DONE_EV_DECODE 5
1031#define WAKE_UP_EV_DECODE 6
1032#define TX_PKT_NON_TCP_UDP_DECODE 9
1033#define TIMER_EV_DECODE 10
1034#define RX_RECOVERY_EV_DECODE 11
1035#define RX_DSC_ERROR_EV_DECODE 14
1036#define TX_DSC_ERROR_EV_DECODE 15
1037#define DRIVER_EV_TX_DESCQ_ID_LBN 0
1038#define DRIVER_EV_TX_DESCQ_ID_WIDTH 12
1039#define DRIVER_EV_RX_FLUSH_FAIL_LBN 12
1040#define DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
1041#define DRIVER_EV_RX_DESCQ_ID_LBN 0
1042#define DRIVER_EV_RX_DESCQ_ID_WIDTH 12
1043#define SRM_CLR_EV_DECODE 0
1044#define SRM_UPD_EV_DECODE 1
1045#define SRM_ILLCLR_EV_DECODE 2
1046
1047/* Global events */
1048#define RX_RECOVERY_B0_LBN 12
1049#define RX_RECOVERY_B0_WIDTH 1
1050#define XG_MNT_INTR_B0_LBN 11
1051#define XG_MNT_INTR_B0_WIDTH 1
1052#define RX_RECOVERY_A1_LBN 11
1053#define RX_RECOVERY_A1_WIDTH 1
1054#define XFP_PHY_INTR_LBN 10
1055#define XFP_PHY_INTR_WIDTH 1
1056#define XG_PHY_INTR_LBN 9
1057#define XG_PHY_INTR_WIDTH 1
1058#define G_PHY1_INTR_LBN 8
1059#define G_PHY1_INTR_WIDTH 1
1060#define G_PHY0_INTR_LBN 7
1061#define G_PHY0_INTR_WIDTH 1
1062
1063/* Driver-generated test events */
1064#define EVQ_MAGIC_LBN 0
1065#define EVQ_MAGIC_WIDTH 32
1066
1067/**************************************************************************
1068 *
1069 * Falcon MAC stats
1070 *
1071 **************************************************************************
1072 *
1073 */
1074
1075#define GRxGoodOct_offset 0x0
1076#define GRxGoodOct_WIDTH 48
1077#define GRxBadOct_offset 0x8
1078#define GRxBadOct_WIDTH 48
1079#define GRxMissPkt_offset 0x10
1080#define GRxMissPkt_WIDTH 32
1081#define GRxFalseCRS_offset 0x14
1082#define GRxFalseCRS_WIDTH 32
1083#define GRxPausePkt_offset 0x18
1084#define GRxPausePkt_WIDTH 32
1085#define GRxBadPkt_offset 0x1C
1086#define GRxBadPkt_WIDTH 32
1087#define GRxUcastPkt_offset 0x20
1088#define GRxUcastPkt_WIDTH 32
1089#define GRxMcastPkt_offset 0x24
1090#define GRxMcastPkt_WIDTH 32
1091#define GRxBcastPkt_offset 0x28
1092#define GRxBcastPkt_WIDTH 32
1093#define GRxGoodLt64Pkt_offset 0x2C
1094#define GRxGoodLt64Pkt_WIDTH 32
1095#define GRxBadLt64Pkt_offset 0x30
1096#define GRxBadLt64Pkt_WIDTH 32
1097#define GRx64Pkt_offset 0x34
1098#define GRx64Pkt_WIDTH 32
1099#define GRx65to127Pkt_offset 0x38
1100#define GRx65to127Pkt_WIDTH 32
1101#define GRx128to255Pkt_offset 0x3C
1102#define GRx128to255Pkt_WIDTH 32
1103#define GRx256to511Pkt_offset 0x40
1104#define GRx256to511Pkt_WIDTH 32
1105#define GRx512to1023Pkt_offset 0x44
1106#define GRx512to1023Pkt_WIDTH 32
1107#define GRx1024to15xxPkt_offset 0x48
1108#define GRx1024to15xxPkt_WIDTH 32
1109#define GRx15xxtoJumboPkt_offset 0x4C
1110#define GRx15xxtoJumboPkt_WIDTH 32
1111#define GRxGtJumboPkt_offset 0x50
1112#define GRxGtJumboPkt_WIDTH 32
1113#define GRxFcsErr64to15xxPkt_offset 0x54
1114#define GRxFcsErr64to15xxPkt_WIDTH 32
1115#define GRxFcsErr15xxtoJumboPkt_offset 0x58
1116#define GRxFcsErr15xxtoJumboPkt_WIDTH 32
1117#define GRxFcsErrGtJumboPkt_offset 0x5C
1118#define GRxFcsErrGtJumboPkt_WIDTH 32
1119#define GTxGoodBadOct_offset 0x80
1120#define GTxGoodBadOct_WIDTH 48
1121#define GTxGoodOct_offset 0x88
1122#define GTxGoodOct_WIDTH 48
1123#define GTxSglColPkt_offset 0x90
1124#define GTxSglColPkt_WIDTH 32
1125#define GTxMultColPkt_offset 0x94
1126#define GTxMultColPkt_WIDTH 32
1127#define GTxExColPkt_offset 0x98
1128#define GTxExColPkt_WIDTH 32
1129#define GTxDefPkt_offset 0x9C
1130#define GTxDefPkt_WIDTH 32
1131#define GTxLateCol_offset 0xA0
1132#define GTxLateCol_WIDTH 32
1133#define GTxExDefPkt_offset 0xA4
1134#define GTxExDefPkt_WIDTH 32
1135#define GTxPausePkt_offset 0xA8
1136#define GTxPausePkt_WIDTH 32
1137#define GTxBadPkt_offset 0xAC
1138#define GTxBadPkt_WIDTH 32
1139#define GTxUcastPkt_offset 0xB0
1140#define GTxUcastPkt_WIDTH 32
1141#define GTxMcastPkt_offset 0xB4
1142#define GTxMcastPkt_WIDTH 32
1143#define GTxBcastPkt_offset 0xB8
1144#define GTxBcastPkt_WIDTH 32
1145#define GTxLt64Pkt_offset 0xBC
1146#define GTxLt64Pkt_WIDTH 32
1147#define GTx64Pkt_offset 0xC0
1148#define GTx64Pkt_WIDTH 32
1149#define GTx65to127Pkt_offset 0xC4
1150#define GTx65to127Pkt_WIDTH 32
1151#define GTx128to255Pkt_offset 0xC8
1152#define GTx128to255Pkt_WIDTH 32
1153#define GTx256to511Pkt_offset 0xCC
1154#define GTx256to511Pkt_WIDTH 32
1155#define GTx512to1023Pkt_offset 0xD0
1156#define GTx512to1023Pkt_WIDTH 32
1157#define GTx1024to15xxPkt_offset 0xD4
1158#define GTx1024to15xxPkt_WIDTH 32
1159#define GTx15xxtoJumboPkt_offset 0xD8
1160#define GTx15xxtoJumboPkt_WIDTH 32
1161#define GTxGtJumboPkt_offset 0xDC
1162#define GTxGtJumboPkt_WIDTH 32
1163#define GTxNonTcpUdpPkt_offset 0xE0
1164#define GTxNonTcpUdpPkt_WIDTH 16
1165#define GTxMacSrcErrPkt_offset 0xE4
1166#define GTxMacSrcErrPkt_WIDTH 16
1167#define GTxIpSrcErrPkt_offset 0xE8
1168#define GTxIpSrcErrPkt_WIDTH 16
1169#define GDmaDone_offset 0xEC
1170#define GDmaDone_WIDTH 32
1171
1172#define XgRxOctets_offset 0x0
1173#define XgRxOctets_WIDTH 48
1174#define XgRxOctetsOK_offset 0x8
1175#define XgRxOctetsOK_WIDTH 48
1176#define XgRxPkts_offset 0x10
1177#define XgRxPkts_WIDTH 32
1178#define XgRxPktsOK_offset 0x14
1179#define XgRxPktsOK_WIDTH 32
1180#define XgRxBroadcastPkts_offset 0x18
1181#define XgRxBroadcastPkts_WIDTH 32
1182#define XgRxMulticastPkts_offset 0x1C
1183#define XgRxMulticastPkts_WIDTH 32
1184#define XgRxUnicastPkts_offset 0x20
1185#define XgRxUnicastPkts_WIDTH 32
1186#define XgRxUndersizePkts_offset 0x24
1187#define XgRxUndersizePkts_WIDTH 32
1188#define XgRxOversizePkts_offset 0x28
1189#define XgRxOversizePkts_WIDTH 32
1190#define XgRxJabberPkts_offset 0x2C
1191#define XgRxJabberPkts_WIDTH 32
1192#define XgRxUndersizeFCSerrorPkts_offset 0x30
1193#define XgRxUndersizeFCSerrorPkts_WIDTH 32
1194#define XgRxDropEvents_offset 0x34
1195#define XgRxDropEvents_WIDTH 32
1196#define XgRxFCSerrorPkts_offset 0x38
1197#define XgRxFCSerrorPkts_WIDTH 32
1198#define XgRxAlignError_offset 0x3C
1199#define XgRxAlignError_WIDTH 32
1200#define XgRxSymbolError_offset 0x40
1201#define XgRxSymbolError_WIDTH 32
1202#define XgRxInternalMACError_offset 0x44
1203#define XgRxInternalMACError_WIDTH 32
1204#define XgRxControlPkts_offset 0x48
1205#define XgRxControlPkts_WIDTH 32
1206#define XgRxPausePkts_offset 0x4C
1207#define XgRxPausePkts_WIDTH 32
1208#define XgRxPkts64Octets_offset 0x50
1209#define XgRxPkts64Octets_WIDTH 32
1210#define XgRxPkts65to127Octets_offset 0x54
1211#define XgRxPkts65to127Octets_WIDTH 32
1212#define XgRxPkts128to255Octets_offset 0x58
1213#define XgRxPkts128to255Octets_WIDTH 32
1214#define XgRxPkts256to511Octets_offset 0x5C
1215#define XgRxPkts256to511Octets_WIDTH 32
1216#define XgRxPkts512to1023Octets_offset 0x60
1217#define XgRxPkts512to1023Octets_WIDTH 32
1218#define XgRxPkts1024to15xxOctets_offset 0x64
1219#define XgRxPkts1024to15xxOctets_WIDTH 32
1220#define XgRxPkts15xxtoMaxOctets_offset 0x68
1221#define XgRxPkts15xxtoMaxOctets_WIDTH 32
1222#define XgRxLengthError_offset 0x6C
1223#define XgRxLengthError_WIDTH 32
1224#define XgTxPkts_offset 0x80
1225#define XgTxPkts_WIDTH 32
1226#define XgTxOctets_offset 0x88
1227#define XgTxOctets_WIDTH 48
1228#define XgTxMulticastPkts_offset 0x90
1229#define XgTxMulticastPkts_WIDTH 32
1230#define XgTxBroadcastPkts_offset 0x94
1231#define XgTxBroadcastPkts_WIDTH 32
1232#define XgTxUnicastPkts_offset 0x98
1233#define XgTxUnicastPkts_WIDTH 32
1234#define XgTxControlPkts_offset 0x9C
1235#define XgTxControlPkts_WIDTH 32
1236#define XgTxPausePkts_offset 0xA0
1237#define XgTxPausePkts_WIDTH 32
1238#define XgTxPkts64Octets_offset 0xA4
1239#define XgTxPkts64Octets_WIDTH 32
1240#define XgTxPkts65to127Octets_offset 0xA8
1241#define XgTxPkts65to127Octets_WIDTH 32
1242#define XgTxPkts128to255Octets_offset 0xAC
1243#define XgTxPkts128to255Octets_WIDTH 32
1244#define XgTxPkts256to511Octets_offset 0xB0
1245#define XgTxPkts256to511Octets_WIDTH 32
1246#define XgTxPkts512to1023Octets_offset 0xB4
1247#define XgTxPkts512to1023Octets_WIDTH 32
1248#define XgTxPkts1024to15xxOctets_offset 0xB8
1249#define XgTxPkts1024to15xxOctets_WIDTH 32
1250#define XgTxPkts1519toMaxOctets_offset 0xBC
1251#define XgTxPkts1519toMaxOctets_WIDTH 32
1252#define XgTxUndersizePkts_offset 0xC0
1253#define XgTxUndersizePkts_WIDTH 32
1254#define XgTxOversizePkts_offset 0xC4
1255#define XgTxOversizePkts_WIDTH 32
1256#define XgTxNonTcpUdpPkt_offset 0xC8
1257#define XgTxNonTcpUdpPkt_WIDTH 16
1258#define XgTxMacSrcErrPkt_offset 0xCC
1259#define XgTxMacSrcErrPkt_WIDTH 16
1260#define XgTxIpSrcErrPkt_offset 0xD0
1261#define XgTxIpSrcErrPkt_WIDTH 16
1262#define XgDmaDone_offset 0xD4
1263
1264#define FALCON_STATS_NOT_DONE 0x00000000
1265#define FALCON_STATS_DONE 0xffffffff
1266
1267/* Interrupt status register bits */
1268#define FATAL_INT_LBN 64
1269#define FATAL_INT_WIDTH 1
1270#define INT_EVQS_LBN 40
1271#define INT_EVQS_WIDTH 4
1272
1273/**************************************************************************
1274 *
1275 * Falcon non-volatile configuration
1276 *
1277 **************************************************************************
1278 */
1279
1280/* Board configuration v2 (v1 is obsolete; later versions are compatible) */
1281struct falcon_nvconfig_board_v2 {
1282 __le16 nports;
1283 u8 port0_phy_addr;
1284 u8 port0_phy_type;
1285 u8 port1_phy_addr;
1286 u8 port1_phy_type;
1287 __le16 asic_sub_revision;
1288 __le16 board_revision;
1289} __packed;
1290
1291/* Board configuration v3 extra information */
1292struct falcon_nvconfig_board_v3 {
1293 __le32 spi_device_type[2];
1294} __packed;
1295
1296/* Bit numbers for spi_device_type */
1297#define SPI_DEV_TYPE_SIZE_LBN 0
1298#define SPI_DEV_TYPE_SIZE_WIDTH 5
1299#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
1300#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
1301#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
1302#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
1303#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
1304#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
1305#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
1306#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
1307#define SPI_DEV_TYPE_FIELD(type, field) \
1308 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
1309
1310#define NVCONFIG_OFFSET 0x300
1311
1312#define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
1313struct falcon_nvconfig {
1314 efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
1315 u8 mac_address[2][8]; /* 0x310 */
1316 efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
1317 efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
1318 efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
1319 efx_oword_t hw_init_reg; /* 0x350 */
1320 efx_oword_t nic_stat_reg; /* 0x360 */
1321 efx_oword_t glb_ctl_reg; /* 0x370 */
1322 efx_oword_t srm_cfg_reg; /* 0x380 */
1323 efx_oword_t spare_reg; /* 0x390 */
1324 __le16 board_magic_num; /* 0x3A0 */
1325 __le16 board_struct_ver;
1326 __le16 board_checksum;
1327 struct falcon_nvconfig_board_v2 board_v2;
1328 efx_oword_t ee_base_page_reg; /* 0x3B0 */
1329 struct falcon_nvconfig_board_v3 board_v3;
1330} __packed;
1331
1332#endif /* EFX_FALCON_HWDEFS_H */
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c
index b486a2b317b..44e65584ee3 100644
--- a/drivers/net/sfc/falcon_xmac.c
+++ b/drivers/net/sfc/falcon_xmac.c
@@ -12,7 +12,7 @@
12#include "net_driver.h" 12#include "net_driver.h"
13#include "efx.h" 13#include "efx.h"
14#include "falcon.h" 14#include "falcon.h"
15#include "falcon_hwdefs.h" 15#include "regs.h"
16#include "falcon_io.h" 16#include "falcon_io.h"
17#include "mac.h" 17#include "mac.h"
18#include "mdio_10g.h" 18#include "mdio_10g.h"
@@ -35,27 +35,27 @@ static void falcon_setup_xaui(struct efx_nic *efx)
35 if (efx->phy_type == PHY_TYPE_NONE) 35 if (efx->phy_type == PHY_TYPE_NONE)
36 return; 36 return;
37 37
38 falcon_read(efx, &sdctl, XX_SD_CTL_REG); 38 falcon_read(efx, &sdctl, FR_AB_XX_SD_CTL);
39 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT); 39 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
40 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT); 40 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
41 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT); 41 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
42 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT); 42 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
43 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT); 43 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
44 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT); 44 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
45 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT); 45 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
46 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT); 46 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
47 falcon_write(efx, &sdctl, XX_SD_CTL_REG); 47 falcon_write(efx, &sdctl, FR_AB_XX_SD_CTL);
48 48
49 EFX_POPULATE_OWORD_8(txdrv, 49 EFX_POPULATE_OWORD_8(txdrv,
50 XX_DEQD, XX_TXDRV_DEQ_DEFAULT, 50 FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
51 XX_DEQC, XX_TXDRV_DEQ_DEFAULT, 51 FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
52 XX_DEQB, XX_TXDRV_DEQ_DEFAULT, 52 FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
53 XX_DEQA, XX_TXDRV_DEQ_DEFAULT, 53 FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
54 XX_DTXD, XX_TXDRV_DTX_DEFAULT, 54 FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
55 XX_DTXC, XX_TXDRV_DTX_DEFAULT, 55 FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
56 XX_DTXB, XX_TXDRV_DTX_DEFAULT, 56 FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
57 XX_DTXA, XX_TXDRV_DTX_DEFAULT); 57 FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
58 falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG); 58 falcon_write(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
59} 59}
60 60
61int falcon_reset_xaui(struct efx_nic *efx) 61int falcon_reset_xaui(struct efx_nic *efx)
@@ -64,14 +64,14 @@ int falcon_reset_xaui(struct efx_nic *efx)
64 int count; 64 int count;
65 65
66 /* Start reset sequence */ 66 /* Start reset sequence */
67 EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1); 67 EFX_POPULATE_DWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
68 falcon_write(efx, &reg, XX_PWR_RST_REG); 68 falcon_write(efx, &reg, FR_AB_XX_PWR_RST);
69 69
70 /* Wait up to 10 ms for completion, then reinitialise */ 70 /* Wait up to 10 ms for completion, then reinitialise */
71 for (count = 0; count < 1000; count++) { 71 for (count = 0; count < 1000; count++) {
72 falcon_read(efx, &reg, XX_PWR_RST_REG); 72 falcon_read(efx, &reg, FR_AB_XX_PWR_RST);
73 if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0 && 73 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
74 EFX_OWORD_FIELD(reg, XX_SD_RST_ACT) == 0) { 74 EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
75 falcon_setup_xaui(efx); 75 falcon_setup_xaui(efx);
76 return 0; 76 return 0;
77 } 77 }
@@ -99,12 +99,12 @@ static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
99 99
100 /* Flush the ISR */ 100 /* Flush the ISR */
101 if (enable) 101 if (enable)
102 falcon_read(efx, &reg, XM_MGT_INT_REG_B0); 102 falcon_read(efx, &reg, FR_AB_XM_MGT_INT_MSK);
103 103
104 EFX_POPULATE_OWORD_2(reg, 104 EFX_POPULATE_OWORD_2(reg,
105 XM_MSK_RMTFLT, !enable, 105 FRF_AB_XM_MSK_RMTFLT, !enable,
106 XM_MSK_LCLFLT, !enable); 106 FRF_AB_XM_MSK_LCLFLT, !enable);
107 falcon_write(efx, &reg, XM_MGT_INT_MSK_REG_B0); 107 falcon_write(efx, &reg, FR_AB_XM_MGT_INT_MASK);
108} 108}
109 109
110/* Get status of XAUI link */ 110/* Get status of XAUI link */
@@ -118,18 +118,18 @@ bool falcon_xaui_link_ok(struct efx_nic *efx)
118 return true; 118 return true;
119 119
120 /* Read link status */ 120 /* Read link status */
121 falcon_read(efx, &reg, XX_CORE_STAT_REG); 121 falcon_read(efx, &reg, FR_AB_XX_CORE_STAT);
122 122
123 align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE); 123 align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
124 sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT); 124 sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
125 if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED)) 125 if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
126 link_ok = true; 126 link_ok = true;
127 127
128 /* Clear link status ready for next read */ 128 /* Clear link status ready for next read */
129 EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET); 129 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
130 EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET); 130 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
131 EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET); 131 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
132 falcon_write(efx, &reg, XX_CORE_STAT_REG); 132 falcon_write(efx, &reg, FR_AB_XX_CORE_STAT);
133 133
134 /* If the link is up, then check the phy side of the xaui link */ 134 /* If the link is up, then check the phy side of the xaui link */
135 if (efx->link_up && link_ok) 135 if (efx->link_up && link_ok)
@@ -147,55 +147,49 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
147 147
148 /* Configure MAC - cut-thru mode is hard wired on */ 148 /* Configure MAC - cut-thru mode is hard wired on */
149 EFX_POPULATE_DWORD_3(reg, 149 EFX_POPULATE_DWORD_3(reg,
150 XM_RX_JUMBO_MODE, 1, 150 FRF_AB_XM_RX_JUMBO_MODE, 1,
151 XM_TX_STAT_EN, 1, 151 FRF_AB_XM_TX_STAT_EN, 1,
152 XM_RX_STAT_EN, 1); 152 FRF_AB_XM_RX_STAT_EN, 1);
153 falcon_write(efx, &reg, XM_GLB_CFG_REG); 153 falcon_write(efx, &reg, FR_AB_XM_GLB_CFG);
154 154
155 /* Configure TX */ 155 /* Configure TX */
156 EFX_POPULATE_DWORD_6(reg, 156 EFX_POPULATE_DWORD_6(reg,
157 XM_TXEN, 1, 157 FRF_AB_XM_TXEN, 1,
158 XM_TX_PRMBL, 1, 158 FRF_AB_XM_TX_PRMBL, 1,
159 XM_AUTO_PAD, 1, 159 FRF_AB_XM_AUTO_PAD, 1,
160 XM_TXCRC, 1, 160 FRF_AB_XM_TXCRC, 1,
161 XM_FCNTL, 1, 161 FRF_AB_XM_FCNTL, 1,
162 XM_IPG, 0x3); 162 FRF_AB_XM_IPG, 0x3);
163 falcon_write(efx, &reg, XM_TX_CFG_REG); 163 falcon_write(efx, &reg, FR_AB_XM_TX_CFG);
164 164
165 /* Configure RX */ 165 /* Configure RX */
166 EFX_POPULATE_DWORD_5(reg, 166 EFX_POPULATE_DWORD_5(reg,
167 XM_RXEN, 1, 167 FRF_AB_XM_RXEN, 1,
168 XM_AUTO_DEPAD, 0, 168 FRF_AB_XM_AUTO_DEPAD, 0,
169 XM_ACPT_ALL_MCAST, 1, 169 FRF_AB_XM_ACPT_ALL_MCAST, 1,
170 XM_ACPT_ALL_UCAST, efx->promiscuous, 170 FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
171 XM_PASS_CRC_ERR, 1); 171 FRF_AB_XM_PASS_CRC_ERR, 1);
172 falcon_write(efx, &reg, XM_RX_CFG_REG); 172 falcon_write(efx, &reg, FR_AB_XM_RX_CFG);
173 173
174 /* Set frame length */ 174 /* Set frame length */
175 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); 175 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
176 EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len); 176 EFX_POPULATE_DWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
177 falcon_write(efx, &reg, XM_RX_PARAM_REG); 177 falcon_write(efx, &reg, FR_AB_XM_RX_PARAM);
178 EFX_POPULATE_DWORD_2(reg, 178 EFX_POPULATE_DWORD_2(reg,
179 XM_MAX_TX_FRM_SIZE, max_frame_len, 179 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
180 XM_TX_JUMBO_MODE, 1); 180 FRF_AB_XM_TX_JUMBO_MODE, 1);
181 falcon_write(efx, &reg, XM_TX_PARAM_REG); 181 falcon_write(efx, &reg, FR_AB_XM_TX_PARAM);
182 182
183 EFX_POPULATE_DWORD_2(reg, 183 EFX_POPULATE_DWORD_2(reg,
184 XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ 184 FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
185 XM_DIS_FCNTL, !rx_fc); 185 FRF_AB_XM_DIS_FCNTL, !rx_fc);
186 falcon_write(efx, &reg, XM_FC_REG); 186 falcon_write(efx, &reg, FR_AB_XM_FC);
187 187
188 /* Set MAC address */ 188 /* Set MAC address */
189 EFX_POPULATE_DWORD_4(reg, 189 memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
190 XM_ADR_0, efx->net_dev->dev_addr[0], 190 falcon_write(efx, &reg, FR_AB_XM_ADR_LO);
191 XM_ADR_1, efx->net_dev->dev_addr[1], 191 memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
192 XM_ADR_2, efx->net_dev->dev_addr[2], 192 falcon_write(efx, &reg, FR_AB_XM_ADR_HI);
193 XM_ADR_3, efx->net_dev->dev_addr[3]);
194 falcon_write(efx, &reg, XM_ADR_LO_REG);
195 EFX_POPULATE_DWORD_2(reg,
196 XM_ADR_4, efx->net_dev->dev_addr[4],
197 XM_ADR_5, efx->net_dev->dev_addr[5]);
198 falcon_write(efx, &reg, XM_ADR_HI_REG);
199} 193}
200 194
201static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) 195static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
@@ -211,12 +205,13 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
211 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback; 205 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
212 bool reset_xgxs; 206 bool reset_xgxs;
213 207
214 falcon_read(efx, &reg, XX_CORE_STAT_REG); 208 falcon_read(efx, &reg, FR_AB_XX_CORE_STAT);
215 old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN); 209 old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
216 old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN); 210 old_xgmii_loopback =
211 EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
217 212
218 falcon_read(efx, &reg, XX_SD_CTL_REG); 213 falcon_read(efx, &reg, FR_AB_XX_SD_CTL);
219 old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA); 214 old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
220 215
221 /* The PHY driver may have turned XAUI off */ 216 /* The PHY driver may have turned XAUI off */
222 reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) || 217 reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
@@ -227,20 +222,20 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
227 falcon_reset_xaui(efx); 222 falcon_reset_xaui(efx);
228 } 223 }
229 224
230 falcon_read(efx, &reg, XX_CORE_STAT_REG); 225 falcon_read(efx, &reg, FR_AB_XX_CORE_STAT);
231 EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG, 226 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
232 (xgxs_loopback || xaui_loopback) ? 227 (xgxs_loopback || xaui_loopback) ?
233 XX_FORCE_SIG_DECODE_FORCED : 0); 228 FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
234 EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback); 229 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
235 EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback); 230 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
236 falcon_write(efx, &reg, XX_CORE_STAT_REG); 231 falcon_write(efx, &reg, FR_AB_XX_CORE_STAT);
237 232
238 falcon_read(efx, &reg, XX_SD_CTL_REG); 233 falcon_read(efx, &reg, FR_AB_XX_SD_CTL);
239 EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback); 234 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
240 EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback); 235 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
241 EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback); 236 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
242 EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback); 237 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
243 falcon_write(efx, &reg, XX_SD_CTL_REG); 238 falcon_write(efx, &reg, FR_AB_XX_SD_CTL);
244} 239}
245 240
246 241
diff --git a/drivers/net/sfc/regs.h b/drivers/net/sfc/regs.h
new file mode 100644
index 00000000000..f336d83d5fa
--- /dev/null
+++ b/drivers/net/sfc/regs.h
@@ -0,0 +1,3180 @@
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_REGS_H
12#define EFX_REGS_H
13
14/*
15 * Falcon hardware architecture definitions have a name prefix following
16 * the format:
17 *
18 * F<type>_<min-rev><max-rev>_
19 *
20 * The following <type> strings are used:
21 *
22 * MMIO register MC register Host memory structure
23 * -------------------------------------------------------------
24 * Address R MCR
25 * Bitfield RF MCRF SF
26 * Enumerator FE MCFE SE
27 *
28 * <min-rev> is the first revision to which the definition applies:
29 *
30 * A: Falcon A1 (SFC4000AB)
31 * B: Falcon B0 (SFC4000BA)
32 * C: Siena A0 (SFL9021AA)
33 *
34 * If the definition has been changed or removed in later revisions
35 * then <max-rev> is the last revision to which the definition applies;
36 * otherwise it is "Z".
37 */
38
39/**************************************************************************
40 *
41 * Falcon/Siena registers and descriptors
42 *
43 **************************************************************************
44 */
45
46/* ADR_REGION_REG: Address region register */
47#define FR_AZ_ADR_REGION 0x00000000
48#define FRF_AZ_ADR_REGION3_LBN 96
49#define FRF_AZ_ADR_REGION3_WIDTH 18
50#define FRF_AZ_ADR_REGION2_LBN 64
51#define FRF_AZ_ADR_REGION2_WIDTH 18
52#define FRF_AZ_ADR_REGION1_LBN 32
53#define FRF_AZ_ADR_REGION1_WIDTH 18
54#define FRF_AZ_ADR_REGION0_LBN 0
55#define FRF_AZ_ADR_REGION0_WIDTH 18
56
57/* INT_EN_REG_KER: Kernel driver Interrupt enable register */
58#define FR_AZ_INT_EN_KER 0x00000010
59#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8
60#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6
61#define FRF_AZ_KER_INT_CHAR_LBN 4
62#define FRF_AZ_KER_INT_CHAR_WIDTH 1
63#define FRF_AZ_KER_INT_KER_LBN 3
64#define FRF_AZ_KER_INT_KER_WIDTH 1
65#define FRF_AZ_DRV_INT_EN_KER_LBN 0
66#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1
67
68/* INT_EN_REG_CHAR: Char Driver interrupt enable register */
69#define FR_BZ_INT_EN_CHAR 0x00000020
70#define FRF_BZ_CHAR_INT_LEVE_SEL_LBN 8
71#define FRF_BZ_CHAR_INT_LEVE_SEL_WIDTH 6
72#define FRF_BZ_CHAR_INT_CHAR_LBN 4
73#define FRF_BZ_CHAR_INT_CHAR_WIDTH 1
74#define FRF_BZ_CHAR_INT_KER_LBN 3
75#define FRF_BZ_CHAR_INT_KER_WIDTH 1
76#define FRF_BZ_DRV_INT_EN_CHAR_LBN 0
77#define FRF_BZ_DRV_INT_EN_CHAR_WIDTH 1
78
79/* INT_ADR_REG_KER: Interrupt host address for Kernel driver */
80#define FR_AZ_INT_ADR_KER 0x00000030
81#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64
82#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1
83#define FRF_AZ_INT_ADR_KER_LBN 0
84#define FRF_AZ_INT_ADR_KER_WIDTH 64
85
86/* INT_ADR_REG_CHAR: Interrupt host address for Char driver */
87#define FR_BZ_INT_ADR_CHAR 0x00000040
88#define FRF_BZ_NORM_INT_VEC_DIS_CHAR_LBN 64
89#define FRF_BZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1
90#define FRF_BZ_INT_ADR_CHAR_LBN 0
91#define FRF_BZ_INT_ADR_CHAR_WIDTH 64
92
93/* INT_ACK_KER: Kernel interrupt acknowledge register */
94#define FR_AA_INT_ACK_KER 0x00000050
95#define FRF_AA_INT_ACK_KER_FIELD_LBN 0
96#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32
97
98/* INT_ISR0_REG: Function 0 Interrupt Acknowlege Status register */
99#define FR_BZ_INT_ISR0 0x00000090
100#define FRF_BZ_INT_ISR_REG_LBN 0
101#define FRF_BZ_INT_ISR_REG_WIDTH 64
102
103/* HW_INIT_REG: Hardware initialization register */
104#define FR_AZ_HW_INIT 0x000000c0
105#define FRF_BB_BDMRD_CPLF_FULL_LBN 124
106#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1
107#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121
108#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3
109#define FRF_CZ_TX_MRG_TAGS_LBN 120
110#define FRF_CZ_TX_MRG_TAGS_WIDTH 1
111#define FRF_AB_TRGT_MASK_ALL_LBN 100
112#define FRF_AB_TRGT_MASK_ALL_WIDTH 1
113#define FRF_AZ_DOORBELL_DROP_LBN 92
114#define FRF_AZ_DOORBELL_DROP_WIDTH 8
115#define FRF_AB_TX_RREQ_MASK_EN_LBN 76
116#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1
117#define FRF_AB_PE_EIDLE_DIS_LBN 75
118#define FRF_AB_PE_EIDLE_DIS_WIDTH 1
119#define FRF_AA_FC_BLOCKING_EN_LBN 45
120#define FRF_AA_FC_BLOCKING_EN_WIDTH 1
121#define FRF_BZ_B2B_REQ_EN_LBN 45
122#define FRF_BZ_B2B_REQ_EN_WIDTH 1
123#define FRF_AA_B2B_REQ_EN_LBN 44
124#define FRF_AA_B2B_REQ_EN_WIDTH 1
125#define FRF_BB_FC_BLOCKING_EN_LBN 44
126#define FRF_BB_FC_BLOCKING_EN_WIDTH 1
127#define FRF_AZ_POST_WR_MASK_LBN 40
128#define FRF_AZ_POST_WR_MASK_WIDTH 4
129#define FRF_AZ_TLP_TC_LBN 34
130#define FRF_AZ_TLP_TC_WIDTH 3
131#define FRF_AZ_TLP_ATTR_LBN 32
132#define FRF_AZ_TLP_ATTR_WIDTH 2
133#define FRF_AB_INTB_VEC_LBN 24
134#define FRF_AB_INTB_VEC_WIDTH 5
135#define FRF_AB_INTA_VEC_LBN 16
136#define FRF_AB_INTA_VEC_WIDTH 5
137#define FRF_AZ_WD_TIMER_LBN 8
138#define FRF_AZ_WD_TIMER_WIDTH 8
139#define FRF_AZ_US_DISABLE_LBN 5
140#define FRF_AZ_US_DISABLE_WIDTH 1
141#define FRF_AZ_TLP_EP_LBN 4
142#define FRF_AZ_TLP_EP_WIDTH 1
143#define FRF_AZ_ATTR_SEL_LBN 3
144#define FRF_AZ_ATTR_SEL_WIDTH 1
145#define FRF_AZ_TD_SEL_LBN 1
146#define FRF_AZ_TD_SEL_WIDTH 1
147#define FRF_AZ_TLP_TD_LBN 0
148#define FRF_AZ_TLP_TD_WIDTH 1
149
150/* EE_SPI_HCMD_REG: SPI host command register */
151#define FR_AB_EE_SPI_HCMD 0x00000100
152#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31
153#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1
154#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28
155#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1
156#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24
157#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1
158#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16
159#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5
160#define FRF_AB_EE_SPI_HCMD_READ_LBN 15
161#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1
162#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12
163#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2
164#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8
165#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2
166#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0
167#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8
168
169/* USR_EV_CFG: User Level Event Configuration register */
170#define FR_CZ_USR_EV_CFG 0x00000100
171#define FRF_CZ_USREV_DIS_LBN 16
172#define FRF_CZ_USREV_DIS_WIDTH 1
173#define FRF_CZ_DFLT_EVQ_LBN 0
174#define FRF_CZ_DFLT_EVQ_WIDTH 10
175
176/* EE_SPI_HADR_REG: SPI host address register */
177#define FR_AB_EE_SPI_HADR 0x00000110
178#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24
179#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8
180#define FRF_AB_EE_SPI_HADR_ADR_LBN 0
181#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24
182
183/* EE_SPI_HDATA_REG: SPI host data register */
184#define FR_AB_EE_SPI_HDATA 0x00000120
185#define FRF_AB_EE_SPI_HDATA3_LBN 96
186#define FRF_AB_EE_SPI_HDATA3_WIDTH 32
187#define FRF_AB_EE_SPI_HDATA2_LBN 64
188#define FRF_AB_EE_SPI_HDATA2_WIDTH 32
189#define FRF_AB_EE_SPI_HDATA1_LBN 32
190#define FRF_AB_EE_SPI_HDATA1_WIDTH 32
191#define FRF_AB_EE_SPI_HDATA0_LBN 0
192#define FRF_AB_EE_SPI_HDATA0_WIDTH 32
193
194/* EE_BASE_PAGE_REG: Expansion ROM base mirror register */
195#define FR_AB_EE_BASE_PAGE 0x00000130
196#define FRF_AB_EE_EXPROM_MASK_LBN 16
197#define FRF_AB_EE_EXPROM_MASK_WIDTH 13
198#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0
199#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13
200
201/* EE_VPD_CFG0_REG: SPI/VPD configuration register 0 */
202#define FR_AB_EE_VPD_CFG0 0x00000140
203#define FRF_AB_EE_SF_FASTRD_EN_LBN 127
204#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1
205#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120
206#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7
207#define FRF_AB_EE_VPD_WIP_POLL_LBN 119
208#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1
209#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112
210#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7
211#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96
212#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16
213#define FRF_AB_EE_VPDW_LENGTH_LBN 80
214#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15
215#define FRF_AB_EE_VPDW_BASE_LBN 64
216#define FRF_AB_EE_VPDW_BASE_WIDTH 15
217#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56
218#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8
219#define FRF_AB_EE_VPD_BASE_LBN 32
220#define FRF_AB_EE_VPD_BASE_WIDTH 24
221#define FRF_AB_EE_VPD_LENGTH_LBN 16
222#define FRF_AB_EE_VPD_LENGTH_WIDTH 15
223#define FRF_AB_EE_VPD_AD_SIZE_LBN 8
224#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5
225#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5
226#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1
227#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4
228#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1
229#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2
230#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1
231#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1
232#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1
233#define FRF_AB_EE_VPD_EN_LBN 0
234#define FRF_AB_EE_VPD_EN_WIDTH 1
235
236/* EE_VPD_SW_CNTL_REG: VPD access SW control register */
237#define FR_AB_EE_VPD_SW_CNTL 0x00000150
238#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31
239#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1
240#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28
241#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1
242#define FRF_AB_EE_VPD_CYC_ADR_LBN 0
243#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15
244
245/* EE_VPD_SW_DATA_REG: VPD access SW data register */
246#define FR_AB_EE_VPD_SW_DATA 0x00000160
247#define FRF_AB_EE_VPD_CYC_DAT_LBN 0
248#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32
249
250/* PBMX_DBG_IADDR_REG: Capture Module address register */
251#define FR_CZ_PBMX_DBG_IADDR 0x000001f0
252#define FRF_CZ_PBMX_DBG_IADDR_LBN 0
253#define FRF_CZ_PBMX_DBG_IADDR_WIDTH 32
254
255/* PCIE_CORE_INDIRECT_REG: Indirect Access to PCIE Core registers */
256#define FR_BB_PCIE_CORE_INDIRECT 0x000001f0
257#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32
258#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32
259#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15
260#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1
261#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0
262#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12
263
264/* PBMX_DBG_IDATA_REG: Capture Module data register */
265#define FR_CZ_PBMX_DBG_IDATA 0x000001f8
266#define FRF_CZ_PBMX_DBG_IDATA_LBN 0
267#define FRF_CZ_PBMX_DBG_IDATA_WIDTH 64
268
269/* NIC_STAT_REG: NIC status register */
270#define FR_AB_NIC_STAT 0x00000200
271#define FRF_BB_AER_DIS_LBN 34
272#define FRF_BB_AER_DIS_WIDTH 1
273#define FRF_BB_EE_STRAP_EN_LBN 31
274#define FRF_BB_EE_STRAP_EN_WIDTH 1
275#define FRF_BB_EE_STRAP_LBN 24
276#define FRF_BB_EE_STRAP_WIDTH 4
277#define FRF_BB_REVISION_ID_LBN 17
278#define FRF_BB_REVISION_ID_WIDTH 7
279#define FRF_AB_ONCHIP_SRAM_LBN 16
280#define FRF_AB_ONCHIP_SRAM_WIDTH 1
281#define FRF_AB_SF_PRST_LBN 9
282#define FRF_AB_SF_PRST_WIDTH 1
283#define FRF_AB_EE_PRST_LBN 8
284#define FRF_AB_EE_PRST_WIDTH 1
285#define FRF_AB_ATE_MODE_LBN 3
286#define FRF_AB_ATE_MODE_WIDTH 1
287#define FRF_AB_STRAP_PINS_LBN 0
288#define FRF_AB_STRAP_PINS_WIDTH 3
289
290/* GPIO_CTL_REG: GPIO control register */
291#define FR_AB_GPIO_CTL 0x00000210
292#define FRF_AB_GPIO_OUT3_LBN 112
293#define FRF_AB_GPIO_OUT3_WIDTH 16
294#define FRF_AB_GPIO_IN3_LBN 104
295#define FRF_AB_GPIO_IN3_WIDTH 8
296#define FRF_AB_GPIO_PWRUP_VALUE3_LBN 96
297#define FRF_AB_GPIO_PWRUP_VALUE3_WIDTH 8
298#define FRF_AB_GPIO_OUT2_LBN 80
299#define FRF_AB_GPIO_OUT2_WIDTH 16
300#define FRF_AB_GPIO_IN2_LBN 72
301#define FRF_AB_GPIO_IN2_WIDTH 8
302#define FRF_AB_GPIO_PWRUP_VALUE2_LBN 64
303#define FRF_AB_GPIO_PWRUP_VALUE2_WIDTH 8
304#define FRF_AB_GPIO15_OEN_LBN 63
305#define FRF_AB_GPIO15_OEN_WIDTH 1
306#define FRF_AB_GPIO14_OEN_LBN 62
307#define FRF_AB_GPIO14_OEN_WIDTH 1
308#define FRF_AB_GPIO13_OEN_LBN 61
309#define FRF_AB_GPIO13_OEN_WIDTH 1
310#define FRF_AB_GPIO12_OEN_LBN 60
311#define FRF_AB_GPIO12_OEN_WIDTH 1
312#define FRF_AB_GPIO11_OEN_LBN 59
313#define FRF_AB_GPIO11_OEN_WIDTH 1
314#define FRF_AB_GPIO10_OEN_LBN 58
315#define FRF_AB_GPIO10_OEN_WIDTH 1
316#define FRF_AB_GPIO9_OEN_LBN 57
317#define FRF_AB_GPIO9_OEN_WIDTH 1
318#define FRF_AB_GPIO8_OEN_LBN 56
319#define FRF_AB_GPIO8_OEN_WIDTH 1
320#define FRF_AB_GPIO15_OUT_LBN 55
321#define FRF_AB_GPIO15_OUT_WIDTH 1
322#define FRF_AB_GPIO14_OUT_LBN 54
323#define FRF_AB_GPIO14_OUT_WIDTH 1
324#define FRF_AB_GPIO13_OUT_LBN 53
325#define FRF_AB_GPIO13_OUT_WIDTH 1
326#define FRF_AB_GPIO12_OUT_LBN 52
327#define FRF_AB_GPIO12_OUT_WIDTH 1
328#define FRF_AB_GPIO11_OUT_LBN 51
329#define FRF_AB_GPIO11_OUT_WIDTH 1
330#define FRF_AB_GPIO10_OUT_LBN 50
331#define FRF_AB_GPIO10_OUT_WIDTH 1
332#define FRF_AB_GPIO9_OUT_LBN 49
333#define FRF_AB_GPIO9_OUT_WIDTH 1
334#define FRF_AB_GPIO8_OUT_LBN 48
335#define FRF_AB_GPIO8_OUT_WIDTH 1
336#define FRF_AB_GPIO15_IN_LBN 47
337#define FRF_AB_GPIO15_IN_WIDTH 1
338#define FRF_AB_GPIO14_IN_LBN 46
339#define FRF_AB_GPIO14_IN_WIDTH 1
340#define FRF_AB_GPIO13_IN_LBN 45
341#define FRF_AB_GPIO13_IN_WIDTH 1
342#define FRF_AB_GPIO12_IN_LBN 44
343#define FRF_AB_GPIO12_IN_WIDTH 1
344#define FRF_AB_GPIO11_IN_LBN 43
345#define FRF_AB_GPIO11_IN_WIDTH 1
346#define FRF_AB_GPIO10_IN_LBN 42
347#define FRF_AB_GPIO10_IN_WIDTH 1
348#define FRF_AB_GPIO9_IN_LBN 41
349#define FRF_AB_GPIO9_IN_WIDTH 1
350#define FRF_AB_GPIO8_IN_LBN 40
351#define FRF_AB_GPIO8_IN_WIDTH 1
352#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39
353#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1
354#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38
355#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1
356#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37
357#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1
358#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36
359#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1
360#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35
361#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1
362#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34
363#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1
364#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33
365#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1
366#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32
367#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1
368#define FRF_AB_CLK156_OUT_EN_LBN 31
369#define FRF_AB_CLK156_OUT_EN_WIDTH 1
370#define FRF_AB_USE_NIC_CLK_LBN 30
371#define FRF_AB_USE_NIC_CLK_WIDTH 1
372#define FRF_AB_GPIO5_OEN_LBN 29
373#define FRF_AB_GPIO5_OEN_WIDTH 1
374#define FRF_AB_GPIO4_OEN_LBN 28
375#define FRF_AB_GPIO4_OEN_WIDTH 1
376#define FRF_AB_GPIO3_OEN_LBN 27
377#define FRF_AB_GPIO3_OEN_WIDTH 1
378#define FRF_AB_GPIO2_OEN_LBN 26
379#define FRF_AB_GPIO2_OEN_WIDTH 1
380#define FRF_AB_GPIO1_OEN_LBN 25
381#define FRF_AB_GPIO1_OEN_WIDTH 1
382#define FRF_AB_GPIO0_OEN_LBN 24
383#define FRF_AB_GPIO0_OEN_WIDTH 1
384#define FRF_AB_GPIO7_OUT_LBN 23
385#define FRF_AB_GPIO7_OUT_WIDTH 1
386#define FRF_AB_GPIO6_OUT_LBN 22
387#define FRF_AB_GPIO6_OUT_WIDTH 1
388#define FRF_AB_GPIO5_OUT_LBN 21
389#define FRF_AB_GPIO5_OUT_WIDTH 1
390#define FRF_AB_GPIO4_OUT_LBN 20
391#define FRF_AB_GPIO4_OUT_WIDTH 1
392#define FRF_AB_GPIO3_OUT_LBN 19
393#define FRF_AB_GPIO3_OUT_WIDTH 1
394#define FRF_AB_GPIO2_OUT_LBN 18
395#define FRF_AB_GPIO2_OUT_WIDTH 1
396#define FRF_AB_GPIO1_OUT_LBN 17
397#define FRF_AB_GPIO1_OUT_WIDTH 1
398#define FRF_AB_GPIO0_OUT_LBN 16
399#define FRF_AB_GPIO0_OUT_WIDTH 1
400#define FRF_AB_GPIO7_IN_LBN 15
401#define FRF_AB_GPIO7_IN_WIDTH 1
402#define FRF_AB_GPIO6_IN_LBN 14
403#define FRF_AB_GPIO6_IN_WIDTH 1
404#define FRF_AB_GPIO5_IN_LBN 13
405#define FRF_AB_GPIO5_IN_WIDTH 1
406#define FRF_AB_GPIO4_IN_LBN 12
407#define FRF_AB_GPIO4_IN_WIDTH 1
408#define FRF_AB_GPIO3_IN_LBN 11
409#define FRF_AB_GPIO3_IN_WIDTH 1
410#define FRF_AB_GPIO2_IN_LBN 10
411#define FRF_AB_GPIO2_IN_WIDTH 1
412#define FRF_AB_GPIO1_IN_LBN 9
413#define FRF_AB_GPIO1_IN_WIDTH 1
414#define FRF_AB_GPIO0_IN_LBN 8
415#define FRF_AB_GPIO0_IN_WIDTH 1
416#define FRF_AB_GPIO7_PWRUP_VALUE_LBN 7
417#define FRF_AB_GPIO7_PWRUP_VALUE_WIDTH 1
418#define FRF_AB_GPIO6_PWRUP_VALUE_LBN 6
419#define FRF_AB_GPIO6_PWRUP_VALUE_WIDTH 1
420#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5
421#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1
422#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4
423#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1
424#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3
425#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1
426#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2
427#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1
428#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1
429#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1
430#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0
431#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1
432
433/* GLB_CTL_REG: Global control register */
434#define FR_AB_GLB_CTL 0x00000220
435#define FRF_AB_EXT_PHY_RST_CTL_LBN 63
436#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1
437#define FRF_AB_XAUI_SD_RST_CTL_LBN 62
438#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1
439#define FRF_AB_PCIE_SD_RST_CTL_LBN 61
440#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1
441#define FRF_AA_PCIX_RST_CTL_LBN 60
442#define FRF_AA_PCIX_RST_CTL_WIDTH 1
443#define FRF_BB_BIU_RST_CTL_LBN 60
444#define FRF_BB_BIU_RST_CTL_WIDTH 1
445#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59
446#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1
447#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58
448#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1
449#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57
450#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1
451#define FRF_AB_XGRX_RST_CTL_LBN 56
452#define FRF_AB_XGRX_RST_CTL_WIDTH 1
453#define FRF_AB_XGTX_RST_CTL_LBN 55
454#define FRF_AB_XGTX_RST_CTL_WIDTH 1
455#define FRF_AB_EM_RST_CTL_LBN 54
456#define FRF_AB_EM_RST_CTL_WIDTH 1
457#define FRF_AB_EV_RST_CTL_LBN 53
458#define FRF_AB_EV_RST_CTL_WIDTH 1
459#define FRF_AB_SR_RST_CTL_LBN 52
460#define FRF_AB_SR_RST_CTL_WIDTH 1
461#define FRF_AB_RX_RST_CTL_LBN 51
462#define FRF_AB_RX_RST_CTL_WIDTH 1
463#define FRF_AB_TX_RST_CTL_LBN 50
464#define FRF_AB_TX_RST_CTL_WIDTH 1
465#define FRF_AB_EE_RST_CTL_LBN 49
466#define FRF_AB_EE_RST_CTL_WIDTH 1
467#define FRF_AB_CS_RST_CTL_LBN 48
468#define FRF_AB_CS_RST_CTL_WIDTH 1
469#define FRF_AB_HOT_RST_CTL_LBN 40
470#define FRF_AB_HOT_RST_CTL_WIDTH 2
471#define FRF_AB_RST_EXT_PHY_LBN 31
472#define FRF_AB_RST_EXT_PHY_WIDTH 1
473#define FRF_AB_RST_XAUI_SD_LBN 30
474#define FRF_AB_RST_XAUI_SD_WIDTH 1
475#define FRF_AB_RST_PCIE_SD_LBN 29
476#define FRF_AB_RST_PCIE_SD_WIDTH 1
477#define FRF_AA_RST_PCIX_LBN 28
478#define FRF_AA_RST_PCIX_WIDTH 1
479#define FRF_BB_RST_BIU_LBN 28
480#define FRF_BB_RST_BIU_WIDTH 1
481#define FRF_AB_RST_PCIE_STKY_LBN 27
482#define FRF_AB_RST_PCIE_STKY_WIDTH 1
483#define FRF_AB_RST_PCIE_NSTKY_LBN 26
484#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1
485#define FRF_AB_RST_PCIE_CORE_LBN 25
486#define FRF_AB_RST_PCIE_CORE_WIDTH 1
487#define FRF_AB_RST_XGRX_LBN 24
488#define FRF_AB_RST_XGRX_WIDTH 1
489#define FRF_AB_RST_XGTX_LBN 23
490#define FRF_AB_RST_XGTX_WIDTH 1
491#define FRF_AB_RST_EM_LBN 22
492#define FRF_AB_RST_EM_WIDTH 1
493#define FRF_AB_RST_EV_LBN 21
494#define FRF_AB_RST_EV_WIDTH 1
495#define FRF_AB_RST_SR_LBN 20
496#define FRF_AB_RST_SR_WIDTH 1
497#define FRF_AB_RST_RX_LBN 19
498#define FRF_AB_RST_RX_WIDTH 1
499#define FRF_AB_RST_TX_LBN 18
500#define FRF_AB_RST_TX_WIDTH 1
501#define FRF_AB_RST_SF_LBN 17
502#define FRF_AB_RST_SF_WIDTH 1
503#define FRF_AB_RST_CS_LBN 16
504#define FRF_AB_RST_CS_WIDTH 1
505#define FRF_AB_INT_RST_DUR_LBN 4
506#define FRF_AB_INT_RST_DUR_WIDTH 3
507#define FRF_AB_EXT_PHY_RST_DUR_LBN 1
508#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3
509#define FFE_AB_EXT_PHY_RST_DUR_10240US 7
510#define FFE_AB_EXT_PHY_RST_DUR_5120US 6
511#define FFE_AB_EXT_PHY_RST_DUR_2560US 5
512#define FFE_AB_EXT_PHY_RST_DUR_1280US 4
513#define FFE_AB_EXT_PHY_RST_DUR_640US 3
514#define FFE_AB_EXT_PHY_RST_DUR_320US 2
515#define FFE_AB_EXT_PHY_RST_DUR_160US 1
516#define FFE_AB_EXT_PHY_RST_DUR_80US 0
517#define FRF_AB_SWRST_LBN 0
518#define FRF_AB_SWRST_WIDTH 1
519
520/* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */
521#define FR_AZ_FATAL_INTR_KER 0x00000230
522#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44
523#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1
524#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43
525#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1
526#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43
527#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1
528#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42
529#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1
530#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41
531#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1
532#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40
533#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1
534#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39
535#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1
536#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38
537#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1
538#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37
539#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1
540#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36
541#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1
542#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35
543#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1
544#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34
545#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1
546#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33
547#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1
548#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32
549#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1
550#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12
551#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1
552#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11
553#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1
554#define FRF_CZ_MBU_PERR_INT_KER_LBN 11
555#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1
556#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10
557#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1
558#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9
559#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1
560#define FRF_AZ_MEM_PERR_INT_KER_LBN 8
561#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1
562#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7
563#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1
564#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6
565#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1
566#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5
567#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1
568#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4
569#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1
570#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3
571#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1
572#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2
573#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1
574#define FRF_AZ_ILL_ADR_INT_KER_LBN 1
575#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1
576#define FRF_AZ_SRM_PERR_INT_KER_LBN 0
577#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1
578
579/* FATAL_INTR_REG_CHAR: Fatal interrupt register for Char */
580#define FR_BZ_FATAL_INTR_CHAR 0x00000240
581#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44
582#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1
583#define FRF_BB_PCI_BUSERR_INT_CHAR_EN_LBN 43
584#define FRF_BB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1
585#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43
586#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1
587#define FRF_BZ_SRAM_OOB_INT_CHAR_EN_LBN 42
588#define FRF_BZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1
589#define FRF_BZ_BUFID_OOB_INT_CHAR_EN_LBN 41
590#define FRF_BZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1
591#define FRF_BZ_MEM_PERR_INT_CHAR_EN_LBN 40
592#define FRF_BZ_MEM_PERR_INT_CHAR_EN_WIDTH 1
593#define FRF_BZ_RBUF_OWN_INT_CHAR_EN_LBN 39
594#define FRF_BZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1
595#define FRF_BZ_TBUF_OWN_INT_CHAR_EN_LBN 38
596#define FRF_BZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1
597#define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37
598#define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1
599#define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36
600#define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1
601#define FRF_BZ_EVQ_OWN_INT_CHAR_EN_LBN 35
602#define FRF_BZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1
603#define FRF_BZ_EVF_OFLO_INT_CHAR_EN_LBN 34
604#define FRF_BZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1
605#define FRF_BZ_ILL_ADR_INT_CHAR_EN_LBN 33
606#define FRF_BZ_ILL_ADR_INT_CHAR_EN_WIDTH 1
607#define FRF_BZ_SRM_PERR_INT_CHAR_EN_LBN 32
608#define FRF_BZ_SRM_PERR_INT_CHAR_EN_WIDTH 1
609#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12
610#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1
611#define FRF_BB_PCI_BUSERR_INT_CHAR_LBN 11
612#define FRF_BB_PCI_BUSERR_INT_CHAR_WIDTH 1
613#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11
614#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1
615#define FRF_BZ_SRAM_OOB_INT_CHAR_LBN 10
616#define FRF_BZ_SRAM_OOB_INT_CHAR_WIDTH 1
617#define FRF_BZ_BUFID_DC_OOB_INT_CHAR_LBN 9
618#define FRF_BZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1
619#define FRF_BZ_MEM_PERR_INT_CHAR_LBN 8
620#define FRF_BZ_MEM_PERR_INT_CHAR_WIDTH 1
621#define FRF_BZ_RBUF_OWN_INT_CHAR_LBN 7
622#define FRF_BZ_RBUF_OWN_INT_CHAR_WIDTH 1
623#define FRF_BZ_TBUF_OWN_INT_CHAR_LBN 6
624#define FRF_BZ_TBUF_OWN_INT_CHAR_WIDTH 1
625#define FRF_BZ_RDESCQ_OWN_INT_CHAR_LBN 5
626#define FRF_BZ_RDESCQ_OWN_INT_CHAR_WIDTH 1
627#define FRF_BZ_TDESCQ_OWN_INT_CHAR_LBN 4
628#define FRF_BZ_TDESCQ_OWN_INT_CHAR_WIDTH 1
629#define FRF_BZ_EVQ_OWN_INT_CHAR_LBN 3
630#define FRF_BZ_EVQ_OWN_INT_CHAR_WIDTH 1
631#define FRF_BZ_EVF_OFLO_INT_CHAR_LBN 2
632#define FRF_BZ_EVF_OFLO_INT_CHAR_WIDTH 1
633#define FRF_BZ_ILL_ADR_INT_CHAR_LBN 1
634#define FRF_BZ_ILL_ADR_INT_CHAR_WIDTH 1
635#define FRF_BZ_SRM_PERR_INT_CHAR_LBN 0
636#define FRF_BZ_SRM_PERR_INT_CHAR_WIDTH 1
637
638/* DP_CTRL_REG: Datapath control register */
639#define FR_BZ_DP_CTRL 0x00000250
640#define FRF_BZ_FLS_EVQ_ID_LBN 0
641#define FRF_BZ_FLS_EVQ_ID_WIDTH 12
642
643/* MEM_STAT_REG: Memory status register */
644#define FR_AZ_MEM_STAT 0x00000260
645#define FRF_AB_MEM_PERR_VEC_LBN 53
646#define FRF_AB_MEM_PERR_VEC_WIDTH 38
647#define FRF_AB_MBIST_CORR_LBN 38
648#define FRF_AB_MBIST_CORR_WIDTH 15
649#define FRF_AB_MBIST_ERR_LBN 0
650#define FRF_AB_MBIST_ERR_WIDTH 40
651#define FRF_CZ_MEM_PERR_VEC_LBN 0
652#define FRF_CZ_MEM_PERR_VEC_WIDTH 35
653
654/* CS_DEBUG_REG: Debug register */
655#define FR_AZ_CS_DEBUG 0x00000270
656#define FRF_AB_GLB_DEBUG2_SEL_LBN 50
657#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3
658#define FRF_AB_DEBUG_BLK_SEL2_LBN 47
659#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3
660#define FRF_AB_DEBUG_BLK_SEL1_LBN 44
661#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3
662#define FRF_AB_DEBUG_BLK_SEL0_LBN 41
663#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3
664#define FRF_CZ_CS_PORT_NUM_LBN 40
665#define FRF_CZ_CS_PORT_NUM_WIDTH 2
666#define FRF_AB_MISC_DEBUG_ADDR_LBN 36
667#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5
668#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31
669#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5
670#define FRF_CZ_CS_PORT_FPE_LBN 1
671#define FRF_CZ_CS_PORT_FPE_WIDTH 35
672#define FRF_AB_EM_DEBUG_ADDR_LBN 26
673#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5
674#define FRF_AB_SR_DEBUG_ADDR_LBN 21
675#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5
676#define FRF_AB_EV_DEBUG_ADDR_LBN 16
677#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5
678#define FRF_AB_RX_DEBUG_ADDR_LBN 11
679#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5
680#define FRF_AB_TX_DEBUG_ADDR_LBN 6
681#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5
682#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1
683#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5
684#define FRF_AZ_CS_DEBUG_EN_LBN 0
685#define FRF_AZ_CS_DEBUG_EN_WIDTH 1
686
687/* DRIVER_REG: Driver scratch register [0-7] */
688#define FR_AZ_DRIVER 0x00000280
689#define FR_AZ_DRIVER_STEP 16
690#define FR_AZ_DRIVER_ROWS 8
691#define FRF_AZ_DRIVER_DW0_LBN 0
692#define FRF_AZ_DRIVER_DW0_WIDTH 32
693
694/* ALTERA_BUILD_REG: Altera build register */
695#define FR_AZ_ALTERA_BUILD 0x00000300
696#define FRF_AZ_ALTERA_BUILD_VER_LBN 0
697#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32
698
699/* CSR_SPARE_REG: Spare register */
700#define FR_AZ_CSR_SPARE 0x00000310
701#define FRF_AB_MEM_PERR_EN_LBN 64
702#define FRF_AB_MEM_PERR_EN_WIDTH 38
703#define FRF_CZ_MEM_PERR_EN_LBN 64
704#define FRF_CZ_MEM_PERR_EN_WIDTH 35
705#define FRF_AB_MEM_PERR_EN_TX_DATA_LBN 72
706#define FRF_AB_MEM_PERR_EN_TX_DATA_WIDTH 2
707#define FRF_AZ_CSR_SPARE_BITS_LBN 0
708#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32
709
710/* PCIE_SD_CTL0123_REG: PCIE SerDes control register 0 to 3 */
711#define FR_AB_PCIE_SD_CTL0123 0x00000320
712#define FRF_AB_PCIE_TESTSIG_H_LBN 96
713#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19
714#define FRF_AB_PCIE_TESTSIG_L_LBN 64
715#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19
716#define FRF_AB_PCIE_OFFSET_LBN 56
717#define FRF_AB_PCIE_OFFSET_WIDTH 8
718#define FRF_AB_PCIE_OFFSETEN_H_LBN 55
719#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1
720#define FRF_AB_PCIE_OFFSETEN_L_LBN 54
721#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1
722#define FRF_AB_PCIE_HIVMODE_H_LBN 53
723#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1
724#define FRF_AB_PCIE_HIVMODE_L_LBN 52
725#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1
726#define FRF_AB_PCIE_PARRESET_H_LBN 51
727#define FRF_AB_PCIE_PARRESET_H_WIDTH 1
728#define FRF_AB_PCIE_PARRESET_L_LBN 50
729#define FRF_AB_PCIE_PARRESET_L_WIDTH 1
730#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49
731#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1
732#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48
733#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1
734#define FRF_AB_PCIE_LPBK_LBN 40
735#define FRF_AB_PCIE_LPBK_WIDTH 8
736#define FRF_AB_PCIE_PARLPBK_LBN 32
737#define FRF_AB_PCIE_PARLPBK_WIDTH 8
738#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30
739#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2
740#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28
741#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2
742#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3
743#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2
744#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1
745#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0
746#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26
747#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2
748#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24
749#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2
750#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3
751#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2
752#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1
753#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0
754#define FRF_AB_PCIE_RXEQCTL_H_LBN 18
755#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2
756#define FRF_AB_PCIE_RXEQCTL_L_LBN 16
757#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2
758#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3
759#define FFE_AB_PCIE_RXEQCTL_OFF 2
760#define FFE_AB_PCIE_RXEQCTL_MIN 1
761#define FFE_AB_PCIE_RXEQCTL_MAX 0
762#define FRF_AB_PCIE_HIDRV_LBN 8
763#define FRF_AB_PCIE_HIDRV_WIDTH 8
764#define FRF_AB_PCIE_LODRV_LBN 0
765#define FRF_AB_PCIE_LODRV_WIDTH 8
766
767/* PCIE_SD_CTL45_REG: PCIE SerDes control register 4 and 5 */
768#define FR_AB_PCIE_SD_CTL45 0x00000330
769#define FRF_AB_PCIE_DTX7_LBN 60
770#define FRF_AB_PCIE_DTX7_WIDTH 4
771#define FRF_AB_PCIE_DTX6_LBN 56
772#define FRF_AB_PCIE_DTX6_WIDTH 4
773#define FRF_AB_PCIE_DTX5_LBN 52
774#define FRF_AB_PCIE_DTX5_WIDTH 4
775#define FRF_AB_PCIE_DTX4_LBN 48
776#define FRF_AB_PCIE_DTX4_WIDTH 4
777#define FRF_AB_PCIE_DTX3_LBN 44
778#define FRF_AB_PCIE_DTX3_WIDTH 4
779#define FRF_AB_PCIE_DTX2_LBN 40
780#define FRF_AB_PCIE_DTX2_WIDTH 4
781#define FRF_AB_PCIE_DTX1_LBN 36
782#define FRF_AB_PCIE_DTX1_WIDTH 4
783#define FRF_AB_PCIE_DTX0_LBN 32
784#define FRF_AB_PCIE_DTX0_WIDTH 4
785#define FRF_AB_PCIE_DEQ7_LBN 28
786#define FRF_AB_PCIE_DEQ7_WIDTH 4
787#define FRF_AB_PCIE_DEQ6_LBN 24
788#define FRF_AB_PCIE_DEQ6_WIDTH 4
789#define FRF_AB_PCIE_DEQ5_LBN 20
790#define FRF_AB_PCIE_DEQ5_WIDTH 4
791#define FRF_AB_PCIE_DEQ4_LBN 16
792#define FRF_AB_PCIE_DEQ4_WIDTH 4
793#define FRF_AB_PCIE_DEQ3_LBN 12
794#define FRF_AB_PCIE_DEQ3_WIDTH 4
795#define FRF_AB_PCIE_DEQ2_LBN 8
796#define FRF_AB_PCIE_DEQ2_WIDTH 4
797#define FRF_AB_PCIE_DEQ1_LBN 4
798#define FRF_AB_PCIE_DEQ1_WIDTH 4
799#define FRF_AB_PCIE_DEQ0_LBN 0
800#define FRF_AB_PCIE_DEQ0_WIDTH 4
801
802/* PCIE_PCS_CTL_STAT_REG: PCIE PCS control and status register */
803#define FR_AB_PCIE_PCS_CTL_STAT 0x00000340
804#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52
805#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4
806#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48
807#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4
808#define FRF_AB_PCIE_PRBSERR_LBN 40
809#define FRF_AB_PCIE_PRBSERR_WIDTH 8
810#define FRF_AB_PCIE_PRBSERRH0_LBN 32
811#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8
812#define FRF_AB_PCIE_FASTINIT_H_LBN 15
813#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1
814#define FRF_AB_PCIE_FASTINIT_L_LBN 14
815#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1
816#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13
817#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1
818#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12
819#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1
820#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11
821#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1
822#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10
823#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1
824#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9
825#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1
826#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8
827#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1
828#define FRF_AB_PCIE_PRBSSEL_LBN 0
829#define FRF_AB_PCIE_PRBSSEL_WIDTH 8
830
831/* DEBUG_DATA_OUT_REG: Live Debug and Debug 2 out ports */
832#define FR_BB_DEBUG_DATA_OUT 0x00000350
833#define FRF_BB_DEBUG2_PORT_LBN 25
834#define FRF_BB_DEBUG2_PORT_WIDTH 15
835#define FRF_BB_DEBUG1_PORT_LBN 0
836#define FRF_BB_DEBUG1_PORT_WIDTH 25
837
838/* EVQ_RPTR_REGP0: Event queue read pointer register */
839#define FR_BZ_EVQ_RPTR_P0 0x00000400
840#define FR_BZ_EVQ_RPTR_P0_STEP 8192
841#define FR_BZ_EVQ_RPTR_P0_ROWS 1024
842/* EVQ_RPTR_REG_KER: Event queue read pointer register */
843#define FR_AA_EVQ_RPTR_KER 0x00011b00
844#define FR_AA_EVQ_RPTR_KER_STEP 4
845#define FR_AA_EVQ_RPTR_KER_ROWS 4
846/* EVQ_RPTR_REG: Event queue read pointer register */
847#define FR_BZ_EVQ_RPTR 0x00fa0000
848#define FR_BZ_EVQ_RPTR_STEP 16
849#define FR_BB_EVQ_RPTR_ROWS 4096
850#define FR_CZ_EVQ_RPTR_ROWS 1024
851/* EVQ_RPTR_REGP123: Event queue read pointer register */
852#define FR_BB_EVQ_RPTR_P123 0x01000400
853#define FR_BB_EVQ_RPTR_P123_STEP 8192
854#define FR_BB_EVQ_RPTR_P123_ROWS 3072
855#define FRF_AZ_EVQ_RPTR_VLD_LBN 15
856#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1
857#define FRF_AZ_EVQ_RPTR_LBN 0
858#define FRF_AZ_EVQ_RPTR_WIDTH 15
859
860/* TIMER_COMMAND_REGP0: Timer Command Registers */
861#define FR_BZ_TIMER_COMMAND_P0 0x00000420
862#define FR_BZ_TIMER_COMMAND_P0_STEP 8192
863#define FR_BZ_TIMER_COMMAND_P0_ROWS 1024
864/* TIMER_COMMAND_REG_KER: Timer Command Registers */
865#define FR_AA_TIMER_COMMAND_KER 0x00000420
866#define FR_AA_TIMER_COMMAND_KER_STEP 8192
867#define FR_AA_TIMER_COMMAND_KER_ROWS 4
868/* TIMER_COMMAND_REGP123: Timer Command Registers */
869#define FR_BB_TIMER_COMMAND_P123 0x01000420
870#define FR_BB_TIMER_COMMAND_P123_STEP 8192
871#define FR_BB_TIMER_COMMAND_P123_ROWS 3072
872#define FRF_CZ_TC_TIMER_MODE_LBN 14
873#define FRF_CZ_TC_TIMER_MODE_WIDTH 2
874#define FRF_AB_TC_TIMER_MODE_LBN 12
875#define FRF_AB_TC_TIMER_MODE_WIDTH 2
876#define FRF_CZ_TC_TIMER_VAL_LBN 0
877#define FRF_CZ_TC_TIMER_VAL_WIDTH 14
878#define FRF_AB_TC_TIMER_VAL_LBN 0
879#define FRF_AB_TC_TIMER_VAL_WIDTH 12
880
881/* DRV_EV_REG: Driver generated event register */
882#define FR_AZ_DRV_EV 0x00000440
883#define FRF_AZ_DRV_EV_QID_LBN 64
884#define FRF_AZ_DRV_EV_QID_WIDTH 12
885#define FRF_AZ_DRV_EV_DATA_LBN 0
886#define FRF_AZ_DRV_EV_DATA_WIDTH 64
887
888/* EVQ_CTL_REG: Event queue control register */
889#define FR_AZ_EVQ_CTL 0x00000450
890#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15
891#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10
892#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15
893#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6
894#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14
895#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1
896#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7
897#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7
898#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0
899#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7
900
901/* EVQ_CNT1_REG: Event counter 1 register */
902#define FR_AZ_EVQ_CNT1 0x00000460
903#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120
904#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7
905#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100
906#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20
907#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80
908#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20
909#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60
910#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20
911#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40
912#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20
913#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20
914#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20
915#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0
916#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20
917
918/* EVQ_CNT2_REG: Event counter 2 register */
919#define FR_AZ_EVQ_CNT2 0x00000470
920#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104
921#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20
922#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84
923#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20
924#define FRF_AZ_EVQ_RDY_CNT_LBN 80
925#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4
926#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60
927#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20
928#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40
929#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20
930#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20
931#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20
932#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0
933#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20
934
935/* USR_EV_REG: Event mailbox register */
936#define FR_CZ_USR_EV 0x00000540
937#define FR_CZ_USR_EV_STEP 8192
938#define FR_CZ_USR_EV_ROWS 1024
939#define FRF_CZ_USR_EV_DATA_LBN 0
940#define FRF_CZ_USR_EV_DATA_WIDTH 32
941
942/* BUF_TBL_CFG_REG: Buffer table configuration register */
943#define FR_AZ_BUF_TBL_CFG 0x00000600
944#define FRF_AZ_BUF_TBL_MODE_LBN 3
945#define FRF_AZ_BUF_TBL_MODE_WIDTH 1
946
947/* SRM_RX_DC_CFG_REG: SRAM receive descriptor cache configuration register */
948#define FR_AZ_SRM_RX_DC_CFG 0x00000610
949#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21
950#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1
951#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0
952#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21
953
954/* SRM_TX_DC_CFG_REG: SRAM transmit descriptor cache configuration register */
955#define FR_AZ_SRM_TX_DC_CFG 0x00000620
956#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0
957#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21
958
959/* SRM_CFG_REG: SRAM configuration register */
960#define FR_AZ_SRM_CFG 0x00000630
961#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5
962#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1
963#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4
964#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1
965#define FRF_AZ_SRM_INIT_EN_LBN 3
966#define FRF_AZ_SRM_INIT_EN_WIDTH 1
967#define FRF_AZ_SRM_NUM_BANK_LBN 2
968#define FRF_AZ_SRM_NUM_BANK_WIDTH 1
969#define FRF_AZ_SRM_BANK_SIZE_LBN 0
970#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2
971
972/* BUF_TBL_UPD_REG: Buffer table update register */
973#define FR_AZ_BUF_TBL_UPD 0x00000650
974#define FRF_AZ_BUF_UPD_CMD_LBN 63
975#define FRF_AZ_BUF_UPD_CMD_WIDTH 1
976#define FRF_AZ_BUF_CLR_CMD_LBN 62
977#define FRF_AZ_BUF_CLR_CMD_WIDTH 1
978#define FRF_AZ_BUF_CLR_END_ID_LBN 32
979#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20
980#define FRF_AZ_BUF_CLR_START_ID_LBN 0
981#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20
982
983/* SRM_UPD_EVQ_REG: Buffer table update register */
984#define FR_AZ_SRM_UPD_EVQ 0x00000660
985#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0
986#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12
987
988/* SRAM_PARITY_REG: SRAM parity register. */
989#define FR_AZ_SRAM_PARITY 0x00000670
990#define FRF_CZ_BYPASS_ECC_LBN 3
991#define FRF_CZ_BYPASS_ECC_WIDTH 1
992#define FRF_CZ_SEC_INT_LBN 2
993#define FRF_CZ_SEC_INT_WIDTH 1
994#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1
995#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1
996#define FRF_AB_FORCE_SRAM_PERR_LBN 0
997#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1
998#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0
999#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1
1000
1001/* RX_CFG_REG: Receive configuration register */
1002#define FR_AZ_RX_CFG 0x00000800
1003#define FRF_CZ_RX_MIN_KBUF_SIZE_LBN 72
1004#define FRF_CZ_RX_MIN_KBUF_SIZE_WIDTH 14
1005#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71
1006#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1
1007#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62
1008#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9
1009#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53
1010#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9
1011#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49
1012#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4
1013#define FRF_BZ_RX_TCP_SUP_LBN 48
1014#define FRF_BZ_RX_TCP_SUP_WIDTH 1
1015#define FRF_BZ_RX_INGR_EN_LBN 47
1016#define FRF_BZ_RX_INGR_EN_WIDTH 1
1017#define FRF_BZ_RX_IP_HASH_LBN 46
1018#define FRF_BZ_RX_IP_HASH_WIDTH 1
1019#define FRF_BZ_RX_HASH_ALG_LBN 45
1020#define FRF_BZ_RX_HASH_ALG_WIDTH 1
1021#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44
1022#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1
1023#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43
1024#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1
1025#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42
1026#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1
1027#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39
1028#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3
1029#define FRF_BZ_RX_OWNERR_CTL_LBN 38
1030#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1
1031#define FRF_BZ_RX_XON_TX_TH_LBN 33
1032#define FRF_BZ_RX_XON_TX_TH_WIDTH 5
1033#define FRF_AA_RX_DESC_PUSH_EN_LBN 35
1034#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1
1035#define FRF_AA_RX_RDW_PATCH_EN_LBN 34
1036#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1
1037#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31
1038#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3
1039#define FRF_BZ_RX_XOFF_TX_TH_LBN 28
1040#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5
1041#define FRF_AA_RX_OWNERR_CTL_LBN 30
1042#define FRF_AA_RX_OWNERR_CTL_WIDTH 1
1043#define FRF_AA_RX_XON_TX_TH_LBN 25
1044#define FRF_AA_RX_XON_TX_TH_WIDTH 5
1045#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19
1046#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9
1047#define FRF_AA_RX_XOFF_TX_TH_LBN 20
1048#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5
1049#define FRF_AA_RX_USR_BUF_SIZE_LBN 11
1050#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9
1051#define FRF_BZ_RX_XON_MAC_TH_LBN 10
1052#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9
1053#define FRF_AA_RX_XON_MAC_TH_LBN 6
1054#define FRF_AA_RX_XON_MAC_TH_WIDTH 5
1055#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1
1056#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9
1057#define FRF_AA_RX_XOFF_MAC_TH_LBN 1
1058#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5
1059#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0
1060#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1
1061
1062/* RX_FILTER_CTL_REG: Receive filter control registers */
1063#define FR_BZ_RX_FILTER_CTL 0x00000810
1064#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94
1065#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8
1066#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86
1067#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8
1068#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85
1069#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1
1070#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69
1071#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16
1072#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57
1073#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12
1074#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56
1075#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1076#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55
1077#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1078#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43
1079#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12
1080#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42
1081#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1082#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41
1083#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1084#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40
1085#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1
1086#define FRF_BZ_UDP_FULL_SRCH_LIMIT_LBN 32
1087#define FRF_BZ_UDP_FULL_SRCH_LIMIT_WIDTH 8
1088#define FRF_BZ_NUM_KER_LBN 24
1089#define FRF_BZ_NUM_KER_WIDTH 2
1090#define FRF_BZ_UDP_WILD_SRCH_LIMIT_LBN 16
1091#define FRF_BZ_UDP_WILD_SRCH_LIMIT_WIDTH 8
1092#define FRF_BZ_TCP_WILD_SRCH_LIMIT_LBN 8
1093#define FRF_BZ_TCP_WILD_SRCH_LIMIT_WIDTH 8
1094#define FRF_BZ_TCP_FULL_SRCH_LIMIT_LBN 0
1095#define FRF_BZ_TCP_FULL_SRCH_LIMIT_WIDTH 8
1096
1097/* RX_FLUSH_DESCQ_REG: Receive flush descriptor queue register */
1098#define FR_AZ_RX_FLUSH_DESCQ 0x00000820
1099#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24
1100#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1
1101#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0
1102#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12
1103
1104/* RX_DESC_UPD_REGP0: Receive descriptor update register. */
1105#define FR_BZ_RX_DESC_UPD_P0 0x00000830
1106#define FR_BZ_RX_DESC_UPD_P0_STEP 8192
1107#define FR_BZ_RX_DESC_UPD_P0_ROWS 1024
1108/* RX_DESC_UPD_REG_KER: Receive descriptor update register. */
1109#define FR_AA_RX_DESC_UPD_KER 0x00000830
1110#define FR_AA_RX_DESC_UPD_KER_STEP 8192
1111#define FR_AA_RX_DESC_UPD_KER_ROWS 4
1112/* RX_DESC_UPD_REGP123: Receive descriptor update register. */
1113#define FR_BB_RX_DESC_UPD_P123 0x01000830
1114#define FR_BB_RX_DESC_UPD_P123_STEP 8192
1115#define FR_BB_RX_DESC_UPD_P123_ROWS 3072
1116#define FRF_AZ_RX_DESC_WPTR_LBN 96
1117#define FRF_AZ_RX_DESC_WPTR_WIDTH 12
1118#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95
1119#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1
1120#define FRF_AZ_RX_DESC_LBN 0
1121#define FRF_AZ_RX_DESC_WIDTH 64
1122
1123/* RX_DC_CFG_REG: Receive descriptor cache configuration register */
1124#define FR_AZ_RX_DC_CFG 0x00000840
1125#define FRF_AB_RX_MAX_PF_LBN 2
1126#define FRF_AB_RX_MAX_PF_WIDTH 2
1127#define FRF_AZ_RX_DC_SIZE_LBN 0
1128#define FRF_AZ_RX_DC_SIZE_WIDTH 2
1129#define FFE_AZ_RX_DC_SIZE_64 3
1130#define FFE_AZ_RX_DC_SIZE_32 2
1131#define FFE_AZ_RX_DC_SIZE_16 1
1132#define FFE_AZ_RX_DC_SIZE_8 0
1133
1134/* RX_DC_PF_WM_REG: Receive descriptor cache pre-fetch watermark register */
1135#define FR_AZ_RX_DC_PF_WM 0x00000850
1136#define FRF_AZ_RX_DC_PF_HWM_LBN 6
1137#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6
1138#define FRF_AZ_RX_DC_PF_LWM_LBN 0
1139#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6
1140
1141/* RX_RSS_TKEY_REG: RSS Toeplitz hash key */
1142#define FR_BZ_RX_RSS_TKEY 0x00000860
1143#define FRF_BZ_RX_RSS_TKEY_HI_LBN 64
1144#define FRF_BZ_RX_RSS_TKEY_HI_WIDTH 64
1145#define FRF_BZ_RX_RSS_TKEY_LO_LBN 0
1146#define FRF_BZ_RX_RSS_TKEY_LO_WIDTH 64
1147
1148/* RX_NODESC_DROP_REG: Receive dropped packet counter register */
1149#define FR_AZ_RX_NODESC_DROP 0x00000880
1150#define FRF_CZ_RX_NODESC_DROP_CNT_LBN 0
1151#define FRF_CZ_RX_NODESC_DROP_CNT_WIDTH 32
1152#define FRF_AB_RX_NODESC_DROP_CNT_LBN 0
1153#define FRF_AB_RX_NODESC_DROP_CNT_WIDTH 16
1154
1155/* RX_SELF_RST_REG: Receive self reset register */
1156#define FR_AA_RX_SELF_RST 0x00000890
1157#define FRF_AA_RX_ISCSI_DIS_LBN 17
1158#define FRF_AA_RX_ISCSI_DIS_WIDTH 1
1159#define FRF_AA_RX_SW_RST_REG_LBN 16
1160#define FRF_AA_RX_SW_RST_REG_WIDTH 1
1161#define FRF_AA_RX_NODESC_WAIT_DIS_LBN 9
1162#define FRF_AA_RX_NODESC_WAIT_DIS_WIDTH 1
1163#define FRF_AA_RX_SELF_RST_EN_LBN 8
1164#define FRF_AA_RX_SELF_RST_EN_WIDTH 1
1165#define FRF_AA_RX_MAX_PF_LAT_LBN 4
1166#define FRF_AA_RX_MAX_PF_LAT_WIDTH 4
1167#define FRF_AA_RX_MAX_LU_LAT_LBN 0
1168#define FRF_AA_RX_MAX_LU_LAT_WIDTH 4
1169
1170/* RX_DEBUG_REG: undocumented register */
1171#define FR_AZ_RX_DEBUG 0x000008a0
1172#define FRF_AZ_RX_DEBUG_LBN 0
1173#define FRF_AZ_RX_DEBUG_WIDTH 64
1174
1175/* RX_PUSH_DROP_REG: Receive descriptor push dropped counter register */
1176#define FR_AZ_RX_PUSH_DROP 0x000008b0
1177#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0
1178#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32
1179
1180/* RX_RSS_IPV6_REG1: IPv6 RSS Toeplitz hash key low bytes */
1181#define FR_CZ_RX_RSS_IPV6_REG1 0x000008d0
1182#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0
1183#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128
1184
1185/* RX_RSS_IPV6_REG2: IPv6 RSS Toeplitz hash key middle bytes */
1186#define FR_CZ_RX_RSS_IPV6_REG2 0x000008e0
1187#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0
1188#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128
1189
1190/* RX_RSS_IPV6_REG3: IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings */
1191#define FR_CZ_RX_RSS_IPV6_REG3 0x000008f0
1192#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66
1193#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1
1194#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65
1195#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1
1196#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64
1197#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1
1198#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0
1199#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64
1200
1201/* TX_FLUSH_DESCQ_REG: Transmit flush descriptor queue register */
1202#define FR_AZ_TX_FLUSH_DESCQ 0x00000a00
1203#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12
1204#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1
1205#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0
1206#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12
1207
1208/* TX_DESC_UPD_REGP0: Transmit descriptor update register. */
1209#define FR_BZ_TX_DESC_UPD_P0 0x00000a10
1210#define FR_BZ_TX_DESC_UPD_P0_STEP 8192
1211#define FR_BZ_TX_DESC_UPD_P0_ROWS 1024
1212/* TX_DESC_UPD_REG_KER: Transmit descriptor update register. */
1213#define FR_AA_TX_DESC_UPD_KER 0x00000a10
1214#define FR_AA_TX_DESC_UPD_KER_STEP 8192
1215#define FR_AA_TX_DESC_UPD_KER_ROWS 8
1216/* TX_DESC_UPD_REGP123: Transmit descriptor update register. */
1217#define FR_BB_TX_DESC_UPD_P123 0x01000a10
1218#define FR_BB_TX_DESC_UPD_P123_STEP 8192
1219#define FR_BB_TX_DESC_UPD_P123_ROWS 3072
1220#define FRF_AZ_TX_DESC_WPTR_LBN 96
1221#define FRF_AZ_TX_DESC_WPTR_WIDTH 12
1222#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95
1223#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1
1224#define FRF_AZ_TX_DESC_LBN 0
1225#define FRF_AZ_TX_DESC_WIDTH 95
1226
1227/* TX_DC_CFG_REG: Transmit descriptor cache configuration register */
1228#define FR_AZ_TX_DC_CFG 0x00000a20
1229#define FRF_AZ_TX_DC_SIZE_LBN 0
1230#define FRF_AZ_TX_DC_SIZE_WIDTH 2
1231#define FFE_AZ_TX_DC_SIZE_32 2
1232#define FFE_AZ_TX_DC_SIZE_16 1
1233#define FFE_AZ_TX_DC_SIZE_8 0
1234
1235/* TX_CHKSM_CFG_REG: Transmit checksum configuration register */
1236#define FR_AA_TX_CHKSM_CFG 0x00000a30
1237#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96
1238#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32
1239#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64
1240#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32
1241#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32
1242#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32
1243#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0
1244#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32
1245
1246/* TX_CFG_REG: Transmit configuration register */
1247#define FR_AZ_TX_CFG 0x00000a50
1248#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114
1249#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8
1250#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113
1251#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1
1252#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105
1253#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1254#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97
1255#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1256#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89
1257#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1258#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81
1259#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1260#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73
1261#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1262#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65
1263#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1264#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64
1265#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1
1266#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48
1267#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16
1268#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47
1269#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1
1270#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16
1271#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15
1272#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5
1273#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1
1274#define FRF_AZ_TX_P1_PRI_EN_LBN 4
1275#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1
1276#define FRF_AZ_TX_OWNERR_CTL_LBN 2
1277#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1
1278#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1
1279#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1
1280#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0
1281#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1
1282
1283/* TX_PUSH_DROP_REG: Transmit push dropped register */
1284#define FR_AZ_TX_PUSH_DROP 0x00000a60
1285#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0
1286#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32
1287
1288/* TX_RESERVED_REG: Transmit configuration register */
1289#define FR_AZ_TX_RESERVED 0x00000a80
1290#define FRF_AZ_TX_EVT_CNT_LBN 121
1291#define FRF_AZ_TX_EVT_CNT_WIDTH 7
1292#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119
1293#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2
1294#define FRF_AZ_TX_RD_COMP_TMR_LBN 96
1295#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23
1296#define FRF_AZ_TX_PUSH_EN_LBN 89
1297#define FRF_AZ_TX_PUSH_EN_WIDTH 1
1298#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88
1299#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1
1300#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85
1301#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1
1302#define FRF_AZ_TX_DMAR_ST_P0_LBN 81
1303#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1
1304#define FRF_AZ_TX_DMAQ_ST_LBN 78
1305#define FRF_AZ_TX_DMAQ_ST_WIDTH 1
1306#define FRF_AZ_TX_RX_SPACER_LBN 64
1307#define FRF_AZ_TX_RX_SPACER_WIDTH 8
1308#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60
1309#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1
1310#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59
1311#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1
1312#define FRF_AZ_TX_PS_EVT_DIS_LBN 58
1313#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1
1314#define FRF_AZ_TX_RX_SPACER_EN_LBN 57
1315#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1
1316#define FRF_AZ_TX_XP_TIMER_LBN 52
1317#define FRF_AZ_TX_XP_TIMER_WIDTH 5
1318#define FRF_AZ_TX_PREF_SPACER_LBN 44
1319#define FRF_AZ_TX_PREF_SPACER_WIDTH 8
1320#define FRF_AZ_TX_PREF_WD_TMR_LBN 22
1321#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22
1322#define FRF_AZ_TX_ONLY1TAG_LBN 21
1323#define FRF_AZ_TX_ONLY1TAG_WIDTH 1
1324#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19
1325#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2
1326#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18
1327#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1
1328#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17
1329#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1
1330#define FRF_AA_TX_DMA_FF_THR_LBN 16
1331#define FRF_AA_TX_DMA_FF_THR_WIDTH 1
1332#define FRF_AZ_TX_DMA_SPACER_LBN 8
1333#define FRF_AZ_TX_DMA_SPACER_WIDTH 8
1334#define FRF_AA_TX_TCP_DIS_LBN 7
1335#define FRF_AA_TX_TCP_DIS_WIDTH 1
1336#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7
1337#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1
1338#define FRF_AA_TX_IP_DIS_LBN 6
1339#define FRF_AA_TX_IP_DIS_WIDTH 1
1340#define FRF_AZ_TX_MAX_CPL_LBN 2
1341#define FRF_AZ_TX_MAX_CPL_WIDTH 2
1342#define FFE_AZ_TX_MAX_CPL_16 3
1343#define FFE_AZ_TX_MAX_CPL_8 2
1344#define FFE_AZ_TX_MAX_CPL_4 1
1345#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0
1346#define FRF_AZ_TX_MAX_PREF_LBN 0
1347#define FRF_AZ_TX_MAX_PREF_WIDTH 2
1348#define FFE_AZ_TX_MAX_PREF_32 3
1349#define FFE_AZ_TX_MAX_PREF_16 2
1350#define FFE_AZ_TX_MAX_PREF_8 1
1351#define FFE_AZ_TX_MAX_PREF_OFF 0
1352
1353/* TX_PACE_REG: Transmit pace control register */
1354#define FR_BZ_TX_PACE 0x00000a90
1355#define FRF_BZ_TX_PACE_SB_NOT_AF_LBN 19
1356#define FRF_BZ_TX_PACE_SB_NOT_AF_WIDTH 10
1357#define FRF_BZ_TX_PACE_SB_AF_LBN 9
1358#define FRF_BZ_TX_PACE_SB_AF_WIDTH 10
1359#define FRF_BZ_TX_PACE_FB_BASE_LBN 5
1360#define FRF_BZ_TX_PACE_FB_BASE_WIDTH 4
1361#define FRF_BZ_TX_PACE_BIN_TH_LBN 0
1362#define FRF_BZ_TX_PACE_BIN_TH_WIDTH 5
1363
1364/* TX_PACE_DROP_QID_REG: PACE Drop QID Counter */
1365#define FR_BZ_TX_PACE_DROP_QID 0x00000aa0
1366#define FRF_BZ_TX_PACE_QID_DRP_CNT_LBN 0
1367#define FRF_BZ_TX_PACE_QID_DRP_CNT_WIDTH 16
1368
1369/* TX_VLAN_REG: Transmit VLAN tag register */
1370#define FR_BB_TX_VLAN 0x00000ae0
1371#define FRF_BB_TX_VLAN_EN_LBN 127
1372#define FRF_BB_TX_VLAN_EN_WIDTH 1
1373#define FRF_BB_TX_VLAN7_PORT1_EN_LBN 125
1374#define FRF_BB_TX_VLAN7_PORT1_EN_WIDTH 1
1375#define FRF_BB_TX_VLAN7_PORT0_EN_LBN 124
1376#define FRF_BB_TX_VLAN7_PORT0_EN_WIDTH 1
1377#define FRF_BB_TX_VLAN7_LBN 112
1378#define FRF_BB_TX_VLAN7_WIDTH 12
1379#define FRF_BB_TX_VLAN6_PORT1_EN_LBN 109
1380#define FRF_BB_TX_VLAN6_PORT1_EN_WIDTH 1
1381#define FRF_BB_TX_VLAN6_PORT0_EN_LBN 108
1382#define FRF_BB_TX_VLAN6_PORT0_EN_WIDTH 1
1383#define FRF_BB_TX_VLAN6_LBN 96
1384#define FRF_BB_TX_VLAN6_WIDTH 12
1385#define FRF_BB_TX_VLAN5_PORT1_EN_LBN 93
1386#define FRF_BB_TX_VLAN5_PORT1_EN_WIDTH 1
1387#define FRF_BB_TX_VLAN5_PORT0_EN_LBN 92
1388#define FRF_BB_TX_VLAN5_PORT0_EN_WIDTH 1
1389#define FRF_BB_TX_VLAN5_LBN 80
1390#define FRF_BB_TX_VLAN5_WIDTH 12
1391#define FRF_BB_TX_VLAN4_PORT1_EN_LBN 77
1392#define FRF_BB_TX_VLAN4_PORT1_EN_WIDTH 1
1393#define FRF_BB_TX_VLAN4_PORT0_EN_LBN 76
1394#define FRF_BB_TX_VLAN4_PORT0_EN_WIDTH 1
1395#define FRF_BB_TX_VLAN4_LBN 64
1396#define FRF_BB_TX_VLAN4_WIDTH 12
1397#define FRF_BB_TX_VLAN3_PORT1_EN_LBN 61
1398#define FRF_BB_TX_VLAN3_PORT1_EN_WIDTH 1
1399#define FRF_BB_TX_VLAN3_PORT0_EN_LBN 60
1400#define FRF_BB_TX_VLAN3_PORT0_EN_WIDTH 1
1401#define FRF_BB_TX_VLAN3_LBN 48
1402#define FRF_BB_TX_VLAN3_WIDTH 12
1403#define FRF_BB_TX_VLAN2_PORT1_EN_LBN 45
1404#define FRF_BB_TX_VLAN2_PORT1_EN_WIDTH 1
1405#define FRF_BB_TX_VLAN2_PORT0_EN_LBN 44
1406#define FRF_BB_TX_VLAN2_PORT0_EN_WIDTH 1
1407#define FRF_BB_TX_VLAN2_LBN 32
1408#define FRF_BB_TX_VLAN2_WIDTH 12
1409#define FRF_BB_TX_VLAN1_PORT1_EN_LBN 29
1410#define FRF_BB_TX_VLAN1_PORT1_EN_WIDTH 1
1411#define FRF_BB_TX_VLAN1_PORT0_EN_LBN 28
1412#define FRF_BB_TX_VLAN1_PORT0_EN_WIDTH 1
1413#define FRF_BB_TX_VLAN1_LBN 16
1414#define FRF_BB_TX_VLAN1_WIDTH 12
1415#define FRF_BB_TX_VLAN0_PORT1_EN_LBN 13
1416#define FRF_BB_TX_VLAN0_PORT1_EN_WIDTH 1
1417#define FRF_BB_TX_VLAN0_PORT0_EN_LBN 12
1418#define FRF_BB_TX_VLAN0_PORT0_EN_WIDTH 1
1419#define FRF_BB_TX_VLAN0_LBN 0
1420#define FRF_BB_TX_VLAN0_WIDTH 12
1421
1422/* TX_IPFIL_PORTEN_REG: Transmit filter control register */
1423#define FR_BZ_TX_IPFIL_PORTEN 0x00000af0
1424#define FRF_BZ_TX_MADR0_FIL_EN_LBN 64
1425#define FRF_BZ_TX_MADR0_FIL_EN_WIDTH 1
1426#define FRF_BB_TX_IPFIL31_PORT_EN_LBN 62
1427#define FRF_BB_TX_IPFIL31_PORT_EN_WIDTH 1
1428#define FRF_BB_TX_IPFIL30_PORT_EN_LBN 60
1429#define FRF_BB_TX_IPFIL30_PORT_EN_WIDTH 1
1430#define FRF_BB_TX_IPFIL29_PORT_EN_LBN 58
1431#define FRF_BB_TX_IPFIL29_PORT_EN_WIDTH 1
1432#define FRF_BB_TX_IPFIL28_PORT_EN_LBN 56
1433#define FRF_BB_TX_IPFIL28_PORT_EN_WIDTH 1
1434#define FRF_BB_TX_IPFIL27_PORT_EN_LBN 54
1435#define FRF_BB_TX_IPFIL27_PORT_EN_WIDTH 1
1436#define FRF_BB_TX_IPFIL26_PORT_EN_LBN 52
1437#define FRF_BB_TX_IPFIL26_PORT_EN_WIDTH 1
1438#define FRF_BB_TX_IPFIL25_PORT_EN_LBN 50
1439#define FRF_BB_TX_IPFIL25_PORT_EN_WIDTH 1
1440#define FRF_BB_TX_IPFIL24_PORT_EN_LBN 48
1441#define FRF_BB_TX_IPFIL24_PORT_EN_WIDTH 1
1442#define FRF_BB_TX_IPFIL23_PORT_EN_LBN 46
1443#define FRF_BB_TX_IPFIL23_PORT_EN_WIDTH 1
1444#define FRF_BB_TX_IPFIL22_PORT_EN_LBN 44
1445#define FRF_BB_TX_IPFIL22_PORT_EN_WIDTH 1
1446#define FRF_BB_TX_IPFIL21_PORT_EN_LBN 42
1447#define FRF_BB_TX_IPFIL21_PORT_EN_WIDTH 1
1448#define FRF_BB_TX_IPFIL20_PORT_EN_LBN 40
1449#define FRF_BB_TX_IPFIL20_PORT_EN_WIDTH 1
1450#define FRF_BB_TX_IPFIL19_PORT_EN_LBN 38
1451#define FRF_BB_TX_IPFIL19_PORT_EN_WIDTH 1
1452#define FRF_BB_TX_IPFIL18_PORT_EN_LBN 36
1453#define FRF_BB_TX_IPFIL18_PORT_EN_WIDTH 1
1454#define FRF_BB_TX_IPFIL17_PORT_EN_LBN 34
1455#define FRF_BB_TX_IPFIL17_PORT_EN_WIDTH 1
1456#define FRF_BB_TX_IPFIL16_PORT_EN_LBN 32
1457#define FRF_BB_TX_IPFIL16_PORT_EN_WIDTH 1
1458#define FRF_BB_TX_IPFIL15_PORT_EN_LBN 30
1459#define FRF_BB_TX_IPFIL15_PORT_EN_WIDTH 1
1460#define FRF_BB_TX_IPFIL14_PORT_EN_LBN 28
1461#define FRF_BB_TX_IPFIL14_PORT_EN_WIDTH 1
1462#define FRF_BB_TX_IPFIL13_PORT_EN_LBN 26
1463#define FRF_BB_TX_IPFIL13_PORT_EN_WIDTH 1
1464#define FRF_BB_TX_IPFIL12_PORT_EN_LBN 24
1465#define FRF_BB_TX_IPFIL12_PORT_EN_WIDTH 1
1466#define FRF_BB_TX_IPFIL11_PORT_EN_LBN 22
1467#define FRF_BB_TX_IPFIL11_PORT_EN_WIDTH 1
1468#define FRF_BB_TX_IPFIL10_PORT_EN_LBN 20
1469#define FRF_BB_TX_IPFIL10_PORT_EN_WIDTH 1
1470#define FRF_BB_TX_IPFIL9_PORT_EN_LBN 18
1471#define FRF_BB_TX_IPFIL9_PORT_EN_WIDTH 1
1472#define FRF_BB_TX_IPFIL8_PORT_EN_LBN 16
1473#define FRF_BB_TX_IPFIL8_PORT_EN_WIDTH 1
1474#define FRF_BB_TX_IPFIL7_PORT_EN_LBN 14
1475#define FRF_BB_TX_IPFIL7_PORT_EN_WIDTH 1
1476#define FRF_BB_TX_IPFIL6_PORT_EN_LBN 12
1477#define FRF_BB_TX_IPFIL6_PORT_EN_WIDTH 1
1478#define FRF_BB_TX_IPFIL5_PORT_EN_LBN 10
1479#define FRF_BB_TX_IPFIL5_PORT_EN_WIDTH 1
1480#define FRF_BB_TX_IPFIL4_PORT_EN_LBN 8
1481#define FRF_BB_TX_IPFIL4_PORT_EN_WIDTH 1
1482#define FRF_BB_TX_IPFIL3_PORT_EN_LBN 6
1483#define FRF_BB_TX_IPFIL3_PORT_EN_WIDTH 1
1484#define FRF_BB_TX_IPFIL2_PORT_EN_LBN 4
1485#define FRF_BB_TX_IPFIL2_PORT_EN_WIDTH 1
1486#define FRF_BB_TX_IPFIL1_PORT_EN_LBN 2
1487#define FRF_BB_TX_IPFIL1_PORT_EN_WIDTH 1
1488#define FRF_BB_TX_IPFIL0_PORT_EN_LBN 0
1489#define FRF_BB_TX_IPFIL0_PORT_EN_WIDTH 1
1490
1491/* TX_IPFIL_TBL: Transmit IP source address filter table */
1492#define FR_BB_TX_IPFIL_TBL 0x00000b00
1493#define FR_BB_TX_IPFIL_TBL_STEP 16
1494#define FR_BB_TX_IPFIL_TBL_ROWS 16
1495#define FRF_BB_TX_IPFIL_MASK_1_LBN 96
1496#define FRF_BB_TX_IPFIL_MASK_1_WIDTH 32
1497#define FRF_BB_TX_IP_SRC_ADR_1_LBN 64
1498#define FRF_BB_TX_IP_SRC_ADR_1_WIDTH 32
1499#define FRF_BB_TX_IPFIL_MASK_0_LBN 32
1500#define FRF_BB_TX_IPFIL_MASK_0_WIDTH 32
1501#define FRF_BB_TX_IP_SRC_ADR_0_LBN 0
1502#define FRF_BB_TX_IP_SRC_ADR_0_WIDTH 32
1503
1504/* MD_TXD_REG: PHY management transmit data register */
1505#define FR_AB_MD_TXD 0x00000c00
1506#define FRF_AB_MD_TXD_LBN 0
1507#define FRF_AB_MD_TXD_WIDTH 16
1508
1509/* MD_RXD_REG: PHY management receive data register */
1510#define FR_AB_MD_RXD 0x00000c10
1511#define FRF_AB_MD_RXD_LBN 0
1512#define FRF_AB_MD_RXD_WIDTH 16
1513
1514/* MD_CS_REG: PHY management configuration & status register */
1515#define FR_AB_MD_CS 0x00000c20
1516#define FRF_AB_MD_RD_EN_CMD_LBN 15
1517#define FRF_AB_MD_RD_EN_CMD_WIDTH 1
1518#define FRF_AB_MD_WR_EN_CMD_LBN 14
1519#define FRF_AB_MD_WR_EN_CMD_WIDTH 1
1520#define FRF_AB_MD_ADDR_CMD_LBN 13
1521#define FRF_AB_MD_ADDR_CMD_WIDTH 1
1522#define FRF_AB_MD_PT_LBN 7
1523#define FRF_AB_MD_PT_WIDTH 3
1524#define FRF_AB_MD_PL_LBN 6
1525#define FRF_AB_MD_PL_WIDTH 1
1526#define FRF_AB_MD_INT_CLR_LBN 5
1527#define FRF_AB_MD_INT_CLR_WIDTH 1
1528#define FRF_AB_MD_GC_LBN 4
1529#define FRF_AB_MD_GC_WIDTH 1
1530#define FRF_AB_MD_PRSP_LBN 3
1531#define FRF_AB_MD_PRSP_WIDTH 1
1532#define FRF_AB_MD_RIC_LBN 2
1533#define FRF_AB_MD_RIC_WIDTH 1
1534#define FRF_AB_MD_RDC_LBN 1
1535#define FRF_AB_MD_RDC_WIDTH 1
1536#define FRF_AB_MD_WRC_LBN 0
1537#define FRF_AB_MD_WRC_WIDTH 1
1538
1539/* MD_PHY_ADR_REG: PHY management PHY address register */
1540#define FR_AB_MD_PHY_ADR 0x00000c30
1541#define FRF_AB_MD_PHY_ADR_LBN 0
1542#define FRF_AB_MD_PHY_ADR_WIDTH 16
1543
1544/* MD_ID_REG: PHY management ID register */
1545#define FR_AB_MD_ID 0x00000c40
1546#define FRF_AB_MD_PRT_ADR_LBN 11
1547#define FRF_AB_MD_PRT_ADR_WIDTH 5
1548#define FRF_AB_MD_DEV_ADR_LBN 6
1549#define FRF_AB_MD_DEV_ADR_WIDTH 5
1550
1551/* MD_STAT_REG: PHY management status & mask register */
1552#define FR_AB_MD_STAT 0x00000c50
1553#define FRF_AB_MD_PINT_LBN 4
1554#define FRF_AB_MD_PINT_WIDTH 1
1555#define FRF_AB_MD_DONE_LBN 3
1556#define FRF_AB_MD_DONE_WIDTH 1
1557#define FRF_AB_MD_BSERR_LBN 2
1558#define FRF_AB_MD_BSERR_WIDTH 1
1559#define FRF_AB_MD_LNFL_LBN 1
1560#define FRF_AB_MD_LNFL_WIDTH 1
1561#define FRF_AB_MD_BSY_LBN 0
1562#define FRF_AB_MD_BSY_WIDTH 1
1563
1564/* MAC_STAT_DMA_REG: Port MAC statistical counter DMA register */
1565#define FR_AB_MAC_STAT_DMA 0x00000c60
1566#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48
1567#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1
1568#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0
1569#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48
1570
1571/* MAC_CTRL_REG: Port MAC control register */
1572#define FR_AB_MAC_CTRL 0x00000c80
1573#define FRF_AB_MAC_XOFF_VAL_LBN 16
1574#define FRF_AB_MAC_XOFF_VAL_WIDTH 16
1575#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7
1576#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1
1577#define FRF_AB_MAC_XG_DISTXCRC_LBN 5
1578#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1
1579#define FRF_AB_MAC_BCAD_ACPT_LBN 4
1580#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1
1581#define FRF_AB_MAC_UC_PROM_LBN 3
1582#define FRF_AB_MAC_UC_PROM_WIDTH 1
1583#define FRF_AB_MAC_LINK_STATUS_LBN 2
1584#define FRF_AB_MAC_LINK_STATUS_WIDTH 1
1585#define FRF_AB_MAC_SPEED_LBN 0
1586#define FRF_AB_MAC_SPEED_WIDTH 2
1587#define FFE_AB_MAC_SPEED_10G 3
1588#define FFE_AB_MAC_SPEED_1G 2
1589#define FFE_AB_MAC_SPEED_100M 1
1590#define FFE_AB_MAC_SPEED_10M 0
1591
1592/* GEN_MODE_REG: General Purpose mode register (external interrupt mask) */
1593#define FR_BB_GEN_MODE 0x00000c90
1594#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3
1595#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1
1596#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2
1597#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1
1598#define FRF_BB_XFP_PHY_INT_MASK_LBN 1
1599#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1
1600#define FRF_BB_XG_PHY_INT_MASK_LBN 0
1601#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1
1602
1603/* MAC_MC_HASH_REG0: Multicast address hash table */
1604#define FR_AB_MAC_MC_HASH_REG0 0x00000ca0
1605#define FRF_AB_MAC_MCAST_HASH0_LBN 0
1606#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128
1607
1608/* MAC_MC_HASH_REG1: Multicast address hash table */
1609#define FR_AB_MAC_MC_HASH_REG1 0x00000cb0
1610#define FRF_AB_MAC_MCAST_HASH1_LBN 0
1611#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128
1612
1613/* GM_CFG1_REG: GMAC configuration register 1 */
1614#define FR_AB_GM_CFG1 0x00000e00
1615#define FRF_AB_GM_SW_RST_LBN 31
1616#define FRF_AB_GM_SW_RST_WIDTH 1
1617#define FRF_AB_GM_SIM_RST_LBN 30
1618#define FRF_AB_GM_SIM_RST_WIDTH 1
1619#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19
1620#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1
1621#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18
1622#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1
1623#define FRF_AB_GM_RST_RX_FUNC_LBN 17
1624#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1
1625#define FRF_AB_GM_RST_TX_FUNC_LBN 16
1626#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1
1627#define FRF_AB_GM_LOOP_LBN 8
1628#define FRF_AB_GM_LOOP_WIDTH 1
1629#define FRF_AB_GM_RX_FC_EN_LBN 5
1630#define FRF_AB_GM_RX_FC_EN_WIDTH 1
1631#define FRF_AB_GM_TX_FC_EN_LBN 4
1632#define FRF_AB_GM_TX_FC_EN_WIDTH 1
1633#define FRF_AB_GM_SYNC_RXEN_LBN 3
1634#define FRF_AB_GM_SYNC_RXEN_WIDTH 1
1635#define FRF_AB_GM_RX_EN_LBN 2
1636#define FRF_AB_GM_RX_EN_WIDTH 1
1637#define FRF_AB_GM_SYNC_TXEN_LBN 1
1638#define FRF_AB_GM_SYNC_TXEN_WIDTH 1
1639#define FRF_AB_GM_TX_EN_LBN 0
1640#define FRF_AB_GM_TX_EN_WIDTH 1
1641
1642/* GM_CFG2_REG: GMAC configuration register 2 */
1643#define FR_AB_GM_CFG2 0x00000e10
1644#define FRF_AB_GM_PAMBL_LEN_LBN 12
1645#define FRF_AB_GM_PAMBL_LEN_WIDTH 4
1646#define FRF_AB_GM_IF_MODE_LBN 8
1647#define FRF_AB_GM_IF_MODE_WIDTH 2
1648#define FFE_AB_IF_MODE_BYTE_MODE 2
1649#define FFE_AB_IF_MODE_NIBBLE_MODE 1
1650#define FRF_AB_GM_HUGE_FRM_EN_LBN 5
1651#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1
1652#define FRF_AB_GM_LEN_CHK_LBN 4
1653#define FRF_AB_GM_LEN_CHK_WIDTH 1
1654#define FRF_AB_GM_PAD_CRC_EN_LBN 2
1655#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1
1656#define FRF_AB_GM_CRC_EN_LBN 1
1657#define FRF_AB_GM_CRC_EN_WIDTH 1
1658#define FRF_AB_GM_FD_LBN 0
1659#define FRF_AB_GM_FD_WIDTH 1
1660
1661/* GM_IPG_REG: GMAC IPG register */
1662#define FR_AB_GM_IPG 0x00000e20
1663#define FRF_AB_GM_NONB2B_IPG1_LBN 24
1664#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7
1665#define FRF_AB_GM_NONB2B_IPG2_LBN 16
1666#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7
1667#define FRF_AB_GM_MIN_IPG_ENF_LBN 8
1668#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8
1669#define FRF_AB_GM_B2B_IPG_LBN 0
1670#define FRF_AB_GM_B2B_IPG_WIDTH 7
1671
1672/* GM_HD_REG: GMAC half duplex register */
1673#define FR_AB_GM_HD 0x00000e30
1674#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20
1675#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4
1676#define FRF_AB_GM_ALT_BOFF_EN_LBN 19
1677#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1
1678#define FRF_AB_GM_BP_NO_BOFF_LBN 18
1679#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1
1680#define FRF_AB_GM_DIS_BOFF_LBN 17
1681#define FRF_AB_GM_DIS_BOFF_WIDTH 1
1682#define FRF_AB_GM_EXDEF_TX_EN_LBN 16
1683#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1
1684#define FRF_AB_GM_RTRY_LIMIT_LBN 12
1685#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4
1686#define FRF_AB_GM_COL_WIN_LBN 0
1687#define FRF_AB_GM_COL_WIN_WIDTH 10
1688
1689/* GM_MAX_FLEN_REG: GMAC maximum frame length register */
1690#define FR_AB_GM_MAX_FLEN 0x00000e40
1691#define FRF_AB_GM_MAX_FLEN_LBN 0
1692#define FRF_AB_GM_MAX_FLEN_WIDTH 16
1693
1694/* GM_TEST_REG: GMAC test register */
1695#define FR_AB_GM_TEST 0x00000e70
1696#define FRF_AB_GM_MAX_BOFF_LBN 3
1697#define FRF_AB_GM_MAX_BOFF_WIDTH 1
1698#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2
1699#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1
1700#define FRF_AB_GM_TEST_PAUSE_LBN 1
1701#define FRF_AB_GM_TEST_PAUSE_WIDTH 1
1702#define FRF_AB_GM_SHORT_SLOT_LBN 0
1703#define FRF_AB_GM_SHORT_SLOT_WIDTH 1
1704
1705/* GM_ADR1_REG: GMAC station address register 1 */
1706#define FR_AB_GM_ADR1 0x00000f00
1707#define FRF_AB_GM_ADR_B0_LBN 24
1708#define FRF_AB_GM_ADR_B0_WIDTH 8
1709#define FRF_AB_GM_ADR_B1_LBN 16
1710#define FRF_AB_GM_ADR_B1_WIDTH 8
1711#define FRF_AB_GM_ADR_B2_LBN 8
1712#define FRF_AB_GM_ADR_B2_WIDTH 8
1713#define FRF_AB_GM_ADR_B3_LBN 0
1714#define FRF_AB_GM_ADR_B3_WIDTH 8
1715
1716/* GM_ADR2_REG: GMAC station address register 2 */
1717#define FR_AB_GM_ADR2 0x00000f10
1718#define FRF_AB_GM_ADR_B4_LBN 24
1719#define FRF_AB_GM_ADR_B4_WIDTH 8
1720#define FRF_AB_GM_ADR_B5_LBN 16
1721#define FRF_AB_GM_ADR_B5_WIDTH 8
1722
1723/* GMF_CFG0_REG: GMAC FIFO configuration register 0 */
1724#define FR_AB_GMF_CFG0 0x00000f20
1725#define FRF_AB_GMF_FTFENRPLY_LBN 20
1726#define FRF_AB_GMF_FTFENRPLY_WIDTH 1
1727#define FRF_AB_GMF_STFENRPLY_LBN 19
1728#define FRF_AB_GMF_STFENRPLY_WIDTH 1
1729#define FRF_AB_GMF_FRFENRPLY_LBN 18
1730#define FRF_AB_GMF_FRFENRPLY_WIDTH 1
1731#define FRF_AB_GMF_SRFENRPLY_LBN 17
1732#define FRF_AB_GMF_SRFENRPLY_WIDTH 1
1733#define FRF_AB_GMF_WTMENRPLY_LBN 16
1734#define FRF_AB_GMF_WTMENRPLY_WIDTH 1
1735#define FRF_AB_GMF_FTFENREQ_LBN 12
1736#define FRF_AB_GMF_FTFENREQ_WIDTH 1
1737#define FRF_AB_GMF_STFENREQ_LBN 11
1738#define FRF_AB_GMF_STFENREQ_WIDTH 1
1739#define FRF_AB_GMF_FRFENREQ_LBN 10
1740#define FRF_AB_GMF_FRFENREQ_WIDTH 1
1741#define FRF_AB_GMF_SRFENREQ_LBN 9
1742#define FRF_AB_GMF_SRFENREQ_WIDTH 1
1743#define FRF_AB_GMF_WTMENREQ_LBN 8
1744#define FRF_AB_GMF_WTMENREQ_WIDTH 1
1745#define FRF_AB_GMF_HSTRSTFT_LBN 4
1746#define FRF_AB_GMF_HSTRSTFT_WIDTH 1
1747#define FRF_AB_GMF_HSTRSTST_LBN 3
1748#define FRF_AB_GMF_HSTRSTST_WIDTH 1
1749#define FRF_AB_GMF_HSTRSTFR_LBN 2
1750#define FRF_AB_GMF_HSTRSTFR_WIDTH 1
1751#define FRF_AB_GMF_HSTRSTSR_LBN 1
1752#define FRF_AB_GMF_HSTRSTSR_WIDTH 1
1753#define FRF_AB_GMF_HSTRSTWT_LBN 0
1754#define FRF_AB_GMF_HSTRSTWT_WIDTH 1
1755
1756/* GMF_CFG1_REG: GMAC FIFO configuration register 1 */
1757#define FR_AB_GMF_CFG1 0x00000f30
1758#define FRF_AB_GMF_CFGFRTH_LBN 16
1759#define FRF_AB_GMF_CFGFRTH_WIDTH 5
1760#define FRF_AB_GMF_CFGXOFFRTX_LBN 0
1761#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16
1762
1763/* GMF_CFG2_REG: GMAC FIFO configuration register 2 */
1764#define FR_AB_GMF_CFG2 0x00000f40
1765#define FRF_AB_GMF_CFGHWM_LBN 16
1766#define FRF_AB_GMF_CFGHWM_WIDTH 6
1767#define FRF_AB_GMF_CFGLWM_LBN 0
1768#define FRF_AB_GMF_CFGLWM_WIDTH 6
1769
1770/* GMF_CFG3_REG: GMAC FIFO configuration register 3 */
1771#define FR_AB_GMF_CFG3 0x00000f50
1772#define FRF_AB_GMF_CFGHWMFT_LBN 16
1773#define FRF_AB_GMF_CFGHWMFT_WIDTH 6
1774#define FRF_AB_GMF_CFGFTTH_LBN 0
1775#define FRF_AB_GMF_CFGFTTH_WIDTH 6
1776
1777/* GMF_CFG4_REG: GMAC FIFO configuration register 4 */
1778#define FR_AB_GMF_CFG4 0x00000f60
1779#define FRF_AB_GMF_HSTFLTRFRM_LBN 0
1780#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18
1781
1782/* GMF_CFG5_REG: GMAC FIFO configuration register 5 */
1783#define FR_AB_GMF_CFG5 0x00000f70
1784#define FRF_AB_GMF_CFGHDPLX_LBN 22
1785#define FRF_AB_GMF_CFGHDPLX_WIDTH 1
1786#define FRF_AB_GMF_SRFULL_LBN 21
1787#define FRF_AB_GMF_SRFULL_WIDTH 1
1788#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20
1789#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1
1790#define FRF_AB_GMF_CFGBYTMODE_LBN 19
1791#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1
1792#define FRF_AB_GMF_HSTDRPLT64_LBN 18
1793#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1
1794#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0
1795#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18
1796
1797/* TX_SRC_MAC_TBL: Transmit IP source address filter table */
1798#define FR_BB_TX_SRC_MAC_TBL 0x00001000
1799#define FR_BB_TX_SRC_MAC_TBL_STEP 16
1800#define FR_BB_TX_SRC_MAC_TBL_ROWS 16
1801#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64
1802#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48
1803#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0
1804#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48
1805
1806/* TX_SRC_MAC_CTL_REG: Transmit MAC source address filter control */
1807#define FR_BB_TX_SRC_MAC_CTL 0x00001100
1808#define FRF_BB_TX_SRC_DROP_CTR_LBN 16
1809#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16
1810#define FRF_BB_TX_SRC_FLTR_EN_LBN 15
1811#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1
1812#define FRF_BB_TX_DROP_CTR_CLR_LBN 12
1813#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1
1814#define FRF_BB_TX_MAC_QID_SEL_LBN 0
1815#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3
1816
1817/* XM_ADR_LO_REG: XGMAC address register low */
1818#define FR_AB_XM_ADR_LO 0x00001200
1819#define FRF_AB_XM_ADR_LO_LBN 0
1820#define FRF_AB_XM_ADR_LO_WIDTH 32
1821
1822/* XM_ADR_HI_REG: XGMAC address register high */
1823#define FR_AB_XM_ADR_HI 0x00001210
1824#define FRF_AB_XM_ADR_HI_LBN 0
1825#define FRF_AB_XM_ADR_HI_WIDTH 16
1826
1827/* XM_GLB_CFG_REG: XGMAC global configuration */
1828#define FR_AB_XM_GLB_CFG 0x00001220
1829#define FRF_AB_XM_RMTFLT_GEN_LBN 17
1830#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1
1831#define FRF_AB_XM_DEBUG_MODE_LBN 16
1832#define FRF_AB_XM_DEBUG_MODE_WIDTH 1
1833#define FRF_AB_XM_RX_STAT_EN_LBN 11
1834#define FRF_AB_XM_RX_STAT_EN_WIDTH 1
1835#define FRF_AB_XM_TX_STAT_EN_LBN 10
1836#define FRF_AB_XM_TX_STAT_EN_WIDTH 1
1837#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6
1838#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1
1839#define FRF_AB_XM_WAN_MODE_LBN 5
1840#define FRF_AB_XM_WAN_MODE_WIDTH 1
1841#define FRF_AB_XM_INTCLR_MODE_LBN 3
1842#define FRF_AB_XM_INTCLR_MODE_WIDTH 1
1843#define FRF_AB_XM_CORE_RST_LBN 0
1844#define FRF_AB_XM_CORE_RST_WIDTH 1
1845
1846/* XM_TX_CFG_REG: XGMAC transmit configuration */
1847#define FR_AB_XM_TX_CFG 0x00001230
1848#define FRF_AB_XM_TX_PROG_LBN 24
1849#define FRF_AB_XM_TX_PROG_WIDTH 1
1850#define FRF_AB_XM_IPG_LBN 16
1851#define FRF_AB_XM_IPG_WIDTH 4
1852#define FRF_AB_XM_FCNTL_LBN 10
1853#define FRF_AB_XM_FCNTL_WIDTH 1
1854#define FRF_AB_XM_TXCRC_LBN 8
1855#define FRF_AB_XM_TXCRC_WIDTH 1
1856#define FRF_AB_XM_EDRC_LBN 6
1857#define FRF_AB_XM_EDRC_WIDTH 1
1858#define FRF_AB_XM_AUTO_PAD_LBN 5
1859#define FRF_AB_XM_AUTO_PAD_WIDTH 1
1860#define FRF_AB_XM_TX_PRMBL_LBN 2
1861#define FRF_AB_XM_TX_PRMBL_WIDTH 1
1862#define FRF_AB_XM_TXEN_LBN 1
1863#define FRF_AB_XM_TXEN_WIDTH 1
1864#define FRF_AB_XM_TX_RST_LBN 0
1865#define FRF_AB_XM_TX_RST_WIDTH 1
1866
1867/* XM_RX_CFG_REG: XGMAC receive configuration */
1868#define FR_AB_XM_RX_CFG 0x00001240
1869#define FRF_AB_XM_PASS_LENERR_LBN 26
1870#define FRF_AB_XM_PASS_LENERR_WIDTH 1
1871#define FRF_AB_XM_PASS_CRC_ERR_LBN 25
1872#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1
1873#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24
1874#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1
1875#define FRF_AB_XM_REJ_BCAST_LBN 20
1876#define FRF_AB_XM_REJ_BCAST_WIDTH 1
1877#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11
1878#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1
1879#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9
1880#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1
1881#define FRF_AB_XM_AUTO_DEPAD_LBN 8
1882#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1
1883#define FRF_AB_XM_RXCRC_LBN 3
1884#define FRF_AB_XM_RXCRC_WIDTH 1
1885#define FRF_AB_XM_RX_PRMBL_LBN 2
1886#define FRF_AB_XM_RX_PRMBL_WIDTH 1
1887#define FRF_AB_XM_RXEN_LBN 1
1888#define FRF_AB_XM_RXEN_WIDTH 1
1889#define FRF_AB_XM_RX_RST_LBN 0
1890#define FRF_AB_XM_RX_RST_WIDTH 1
1891
1892/* XM_MGT_INT_MASK: documentation to be written for sum_XM_MGT_INT_MASK */
1893#define FR_AB_XM_MGT_INT_MASK 0x00001250
1894#define FRF_AB_XM_MSK_STA_INTR_LBN 16
1895#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1
1896#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9
1897#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1
1898#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8
1899#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1
1900#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2
1901#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1
1902#define FRF_AB_XM_MSK_RMTFLT_LBN 1
1903#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1
1904#define FRF_AB_XM_MSK_LCLFLT_LBN 0
1905#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1
1906
1907/* XM_FC_REG: XGMAC flow control register */
1908#define FR_AB_XM_FC 0x00001270
1909#define FRF_AB_XM_PAUSE_TIME_LBN 16
1910#define FRF_AB_XM_PAUSE_TIME_WIDTH 16
1911#define FRF_AB_XM_RX_MAC_STAT_LBN 11
1912#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1
1913#define FRF_AB_XM_TX_MAC_STAT_LBN 10
1914#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1
1915#define FRF_AB_XM_MCNTL_PASS_LBN 8
1916#define FRF_AB_XM_MCNTL_PASS_WIDTH 2
1917#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6
1918#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1
1919#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5
1920#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1
1921#define FRF_AB_XM_ZPAUSE_LBN 2
1922#define FRF_AB_XM_ZPAUSE_WIDTH 1
1923#define FRF_AB_XM_XMIT_PAUSE_LBN 1
1924#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1
1925#define FRF_AB_XM_DIS_FCNTL_LBN 0
1926#define FRF_AB_XM_DIS_FCNTL_WIDTH 1
1927
1928/* XM_PAUSE_TIME_REG: XGMAC pause time register */
1929#define FR_AB_XM_PAUSE_TIME 0x00001290
1930#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16
1931#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16
1932#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0
1933#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16
1934
1935/* XM_TX_PARAM_REG: XGMAC transmit parameter register */
1936#define FR_AB_XM_TX_PARAM 0x000012d0
1937#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31
1938#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1
1939#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19
1940#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11
1941#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16
1942#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3
1943#define FRF_AB_XM_PAD_CHAR_LBN 0
1944#define FRF_AB_XM_PAD_CHAR_WIDTH 8
1945
1946/* XM_RX_PARAM_REG: XGMAC receive parameter register */
1947#define FR_AB_XM_RX_PARAM 0x000012e0
1948#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3
1949#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11
1950#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0
1951#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3
1952
1953/* XM_MGT_INT_MSK_REG: XGMAC management interrupt mask register */
1954#define FR_AB_XM_MGT_INT_MSK 0x000012f0
1955#define FRF_AB_XM_STAT_CNTR_OF_LBN 9
1956#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1
1957#define FRF_AB_XM_STAT_CNTR_HF_LBN 8
1958#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1
1959#define FRF_AB_XM_PRMBLE_ERR_LBN 2
1960#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1
1961#define FRF_AB_XM_RMTFLT_LBN 1
1962#define FRF_AB_XM_RMTFLT_WIDTH 1
1963#define FRF_AB_XM_LCLFLT_LBN 0
1964#define FRF_AB_XM_LCLFLT_WIDTH 1
1965
1966/* XX_PWR_RST_REG: XGXS/XAUI powerdown/reset register */
1967#define FR_AB_XX_PWR_RST 0x00001300
1968#define FRF_AB_XX_PWRDND_SIG_LBN 31
1969#define FRF_AB_XX_PWRDND_SIG_WIDTH 1
1970#define FRF_AB_XX_PWRDNC_SIG_LBN 30
1971#define FRF_AB_XX_PWRDNC_SIG_WIDTH 1
1972#define FRF_AB_XX_PWRDNB_SIG_LBN 29
1973#define FRF_AB_XX_PWRDNB_SIG_WIDTH 1
1974#define FRF_AB_XX_PWRDNA_SIG_LBN 28
1975#define FRF_AB_XX_PWRDNA_SIG_WIDTH 1
1976#define FRF_AB_XX_SIM_MODE_LBN 27
1977#define FRF_AB_XX_SIM_MODE_WIDTH 1
1978#define FRF_AB_XX_RSTPLLCD_SIG_LBN 25
1979#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1
1980#define FRF_AB_XX_RSTPLLAB_SIG_LBN 24
1981#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1
1982#define FRF_AB_XX_RESETD_SIG_LBN 23
1983#define FRF_AB_XX_RESETD_SIG_WIDTH 1
1984#define FRF_AB_XX_RESETC_SIG_LBN 22
1985#define FRF_AB_XX_RESETC_SIG_WIDTH 1
1986#define FRF_AB_XX_RESETB_SIG_LBN 21
1987#define FRF_AB_XX_RESETB_SIG_WIDTH 1
1988#define FRF_AB_XX_RESETA_SIG_LBN 20
1989#define FRF_AB_XX_RESETA_SIG_WIDTH 1
1990#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18
1991#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1
1992#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17
1993#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1
1994#define FRF_AB_XX_SD_RST_ACT_LBN 16
1995#define FRF_AB_XX_SD_RST_ACT_WIDTH 1
1996#define FRF_AB_XX_PWRDND_EN_LBN 15
1997#define FRF_AB_XX_PWRDND_EN_WIDTH 1
1998#define FRF_AB_XX_PWRDNC_EN_LBN 14
1999#define FRF_AB_XX_PWRDNC_EN_WIDTH 1
2000#define FRF_AB_XX_PWRDNB_EN_LBN 13
2001#define FRF_AB_XX_PWRDNB_EN_WIDTH 1
2002#define FRF_AB_XX_PWRDNA_EN_LBN 12
2003#define FRF_AB_XX_PWRDNA_EN_WIDTH 1
2004#define FRF_AB_XX_RSTPLLCD_EN_LBN 9
2005#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1
2006#define FRF_AB_XX_RSTPLLAB_EN_LBN 8
2007#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1
2008#define FRF_AB_XX_RESETD_EN_LBN 7
2009#define FRF_AB_XX_RESETD_EN_WIDTH 1
2010#define FRF_AB_XX_RESETC_EN_LBN 6
2011#define FRF_AB_XX_RESETC_EN_WIDTH 1
2012#define FRF_AB_XX_RESETB_EN_LBN 5
2013#define FRF_AB_XX_RESETB_EN_WIDTH 1
2014#define FRF_AB_XX_RESETA_EN_LBN 4
2015#define FRF_AB_XX_RESETA_EN_WIDTH 1
2016#define FRF_AB_XX_RSTXGXSRX_EN_LBN 2
2017#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1
2018#define FRF_AB_XX_RSTXGXSTX_EN_LBN 1
2019#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1
2020#define FRF_AB_XX_RST_XX_EN_LBN 0
2021#define FRF_AB_XX_RST_XX_EN_WIDTH 1
2022
2023/* XX_SD_CTL_REG: XGXS/XAUI powerdown/reset control register */
2024#define FR_AB_XX_SD_CTL 0x00001310
2025#define FRF_AB_XX_TERMADJ1_LBN 17
2026#define FRF_AB_XX_TERMADJ1_WIDTH 1
2027#define FRF_AB_XX_TERMADJ0_LBN 16
2028#define FRF_AB_XX_TERMADJ0_WIDTH 1
2029#define FRF_AB_XX_HIDRVD_LBN 15
2030#define FRF_AB_XX_HIDRVD_WIDTH 1
2031#define FRF_AB_XX_LODRVD_LBN 14
2032#define FRF_AB_XX_LODRVD_WIDTH 1
2033#define FRF_AB_XX_HIDRVC_LBN 13
2034#define FRF_AB_XX_HIDRVC_WIDTH 1
2035#define FRF_AB_XX_LODRVC_LBN 12
2036#define FRF_AB_XX_LODRVC_WIDTH 1
2037#define FRF_AB_XX_HIDRVB_LBN 11
2038#define FRF_AB_XX_HIDRVB_WIDTH 1
2039#define FRF_AB_XX_LODRVB_LBN 10
2040#define FRF_AB_XX_LODRVB_WIDTH 1
2041#define FRF_AB_XX_HIDRVA_LBN 9
2042#define FRF_AB_XX_HIDRVA_WIDTH 1
2043#define FRF_AB_XX_LODRVA_LBN 8
2044#define FRF_AB_XX_LODRVA_WIDTH 1
2045#define FRF_AB_XX_LPBKD_LBN 3
2046#define FRF_AB_XX_LPBKD_WIDTH 1
2047#define FRF_AB_XX_LPBKC_LBN 2
2048#define FRF_AB_XX_LPBKC_WIDTH 1
2049#define FRF_AB_XX_LPBKB_LBN 1
2050#define FRF_AB_XX_LPBKB_WIDTH 1
2051#define FRF_AB_XX_LPBKA_LBN 0
2052#define FRF_AB_XX_LPBKA_WIDTH 1
2053
2054/* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */
2055#define FR_AB_XX_TXDRV_CTL 0x00001320
2056#define FRF_AB_XX_DEQD_LBN 28
2057#define FRF_AB_XX_DEQD_WIDTH 4
2058#define FRF_AB_XX_DEQC_LBN 24
2059#define FRF_AB_XX_DEQC_WIDTH 4
2060#define FRF_AB_XX_DEQB_LBN 20
2061#define FRF_AB_XX_DEQB_WIDTH 4
2062#define FRF_AB_XX_DEQA_LBN 16
2063#define FRF_AB_XX_DEQA_WIDTH 4
2064#define FRF_AB_XX_DTXD_LBN 12
2065#define FRF_AB_XX_DTXD_WIDTH 4
2066#define FRF_AB_XX_DTXC_LBN 8
2067#define FRF_AB_XX_DTXC_WIDTH 4
2068#define FRF_AB_XX_DTXB_LBN 4
2069#define FRF_AB_XX_DTXB_WIDTH 4
2070#define FRF_AB_XX_DTXA_LBN 0
2071#define FRF_AB_XX_DTXA_WIDTH 4
2072
2073/* XX_PRBS_CTL_REG: documentation to be written for sum_XX_PRBS_CTL_REG */
2074#define FR_AB_XX_PRBS_CTL 0x00001330
2075#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30
2076#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2
2077#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29
2078#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1
2079#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28
2080#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1
2081#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26
2082#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2
2083#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25
2084#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1
2085#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24
2086#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1
2087#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22
2088#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2
2089#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21
2090#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1
2091#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20
2092#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1
2093#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18
2094#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2
2095#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17
2096#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1
2097#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16
2098#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1
2099#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14
2100#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2
2101#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13
2102#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1
2103#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12
2104#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1
2105#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10
2106#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2
2107#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9
2108#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1
2109#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8
2110#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1
2111#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6
2112#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2
2113#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5
2114#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1
2115#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4
2116#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1
2117#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2
2118#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2
2119#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1
2120#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1
2121#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0
2122#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1
2123
2124/* XX_PRBS_CHK_REG: documentation to be written for sum_XX_PRBS_CHK_REG */
2125#define FR_AB_XX_PRBS_CHK 0x00001340
2126#define FRF_AB_XX_REV_LB_EN_LBN 16
2127#define FRF_AB_XX_REV_LB_EN_WIDTH 1
2128#define FRF_AB_XX_CH3_DEG_DET_LBN 15
2129#define FRF_AB_XX_CH3_DEG_DET_WIDTH 1
2130#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14
2131#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1
2132#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13
2133#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1
2134#define FRF_AB_XX_CH3_ERR_CHK_LBN 12
2135#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1
2136#define FRF_AB_XX_CH2_DEG_DET_LBN 11
2137#define FRF_AB_XX_CH2_DEG_DET_WIDTH 1
2138#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10
2139#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1
2140#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9
2141#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1
2142#define FRF_AB_XX_CH2_ERR_CHK_LBN 8
2143#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1
2144#define FRF_AB_XX_CH1_DEG_DET_LBN 7
2145#define FRF_AB_XX_CH1_DEG_DET_WIDTH 1
2146#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6
2147#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1
2148#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5
2149#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1
2150#define FRF_AB_XX_CH1_ERR_CHK_LBN 4
2151#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1
2152#define FRF_AB_XX_CH0_DEG_DET_LBN 3
2153#define FRF_AB_XX_CH0_DEG_DET_WIDTH 1
2154#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2
2155#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1
2156#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1
2157#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1
2158#define FRF_AB_XX_CH0_ERR_CHK_LBN 0
2159#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1
2160
2161/* XX_PRBS_ERR_REG: documentation to be written for sum_XX_PRBS_ERR_REG */
2162#define FR_AB_XX_PRBS_ERR 0x00001350
2163#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24
2164#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8
2165#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16
2166#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8
2167#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8
2168#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8
2169#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0
2170#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8
2171
2172/* XX_CORE_STAT_REG: XAUI XGXS core status register */
2173#define FR_AB_XX_CORE_STAT 0x00001360
2174#define FRF_AB_XX_FORCE_SIG3_LBN 31
2175#define FRF_AB_XX_FORCE_SIG3_WIDTH 1
2176#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30
2177#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1
2178#define FRF_AB_XX_FORCE_SIG2_LBN 29
2179#define FRF_AB_XX_FORCE_SIG2_WIDTH 1
2180#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28
2181#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1
2182#define FRF_AB_XX_FORCE_SIG1_LBN 27
2183#define FRF_AB_XX_FORCE_SIG1_WIDTH 1
2184#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26
2185#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1
2186#define FRF_AB_XX_FORCE_SIG0_LBN 25
2187#define FRF_AB_XX_FORCE_SIG0_WIDTH 1
2188#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24
2189#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1
2190#define FRF_AB_XX_XGXS_LB_EN_LBN 23
2191#define FRF_AB_XX_XGXS_LB_EN_WIDTH 1
2192#define FRF_AB_XX_XGMII_LB_EN_LBN 22
2193#define FRF_AB_XX_XGMII_LB_EN_WIDTH 1
2194#define FRF_AB_XX_MATCH_FAULT_LBN 21
2195#define FRF_AB_XX_MATCH_FAULT_WIDTH 1
2196#define FRF_AB_XX_ALIGN_DONE_LBN 20
2197#define FRF_AB_XX_ALIGN_DONE_WIDTH 1
2198#define FRF_AB_XX_SYNC_STAT3_LBN 19
2199#define FRF_AB_XX_SYNC_STAT3_WIDTH 1
2200#define FRF_AB_XX_SYNC_STAT2_LBN 18
2201#define FRF_AB_XX_SYNC_STAT2_WIDTH 1
2202#define FRF_AB_XX_SYNC_STAT1_LBN 17
2203#define FRF_AB_XX_SYNC_STAT1_WIDTH 1
2204#define FRF_AB_XX_SYNC_STAT0_LBN 16
2205#define FRF_AB_XX_SYNC_STAT0_WIDTH 1
2206#define FRF_AB_XX_COMMA_DET_CH3_LBN 15
2207#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1
2208#define FRF_AB_XX_COMMA_DET_CH2_LBN 14
2209#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1
2210#define FRF_AB_XX_COMMA_DET_CH1_LBN 13
2211#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1
2212#define FRF_AB_XX_COMMA_DET_CH0_LBN 12
2213#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1
2214#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11
2215#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1
2216#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10
2217#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1
2218#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9
2219#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1
2220#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8
2221#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1
2222#define FRF_AB_XX_CHAR_ERR_CH3_LBN 7
2223#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1
2224#define FRF_AB_XX_CHAR_ERR_CH2_LBN 6
2225#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1
2226#define FRF_AB_XX_CHAR_ERR_CH1_LBN 5
2227#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1
2228#define FRF_AB_XX_CHAR_ERR_CH0_LBN 4
2229#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1
2230#define FRF_AB_XX_DISPERR_CH3_LBN 3
2231#define FRF_AB_XX_DISPERR_CH3_WIDTH 1
2232#define FRF_AB_XX_DISPERR_CH2_LBN 2
2233#define FRF_AB_XX_DISPERR_CH2_WIDTH 1
2234#define FRF_AB_XX_DISPERR_CH1_LBN 1
2235#define FRF_AB_XX_DISPERR_CH1_WIDTH 1
2236#define FRF_AB_XX_DISPERR_CH0_LBN 0
2237#define FRF_AB_XX_DISPERR_CH0_WIDTH 1
2238
2239/* RX_DESC_PTR_TBL_KER: Receive descriptor pointer table */
2240#define FR_AA_RX_DESC_PTR_TBL_KER 0x00011800
2241#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16
2242#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4
2243/* RX_DESC_PTR_TBL: Receive descriptor pointer table */
2244#define FR_BZ_RX_DESC_PTR_TBL 0x00f40000
2245#define FR_BZ_RX_DESC_PTR_TBL_STEP 16
2246#define FR_BB_RX_DESC_PTR_TBL_ROWS 4096
2247#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024
2248#define FRF_CZ_RX_HDR_SPLIT_LBN 90
2249#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1
2250#define FRF_AA_RX_RESET_LBN 89
2251#define FRF_AA_RX_RESET_WIDTH 1
2252#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88
2253#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1
2254#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87
2255#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1
2256#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86
2257#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1
2258#define FRF_AZ_RX_DC_HW_RPTR_LBN 80
2259#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6
2260#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68
2261#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12
2262#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56
2263#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12
2264#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36
2265#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20
2266#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24
2267#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12
2268#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10
2269#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14
2270#define FRF_AZ_RX_DESCQ_LABEL_LBN 5
2271#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5
2272#define FRF_AZ_RX_DESCQ_SIZE_LBN 3
2273#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2
2274#define FFE_AZ_RX_DESCQ_SIZE_4K 3
2275#define FFE_AZ_RX_DESCQ_SIZE_2K 2
2276#define FFE_AZ_RX_DESCQ_SIZE_1K 1
2277#define FFE_AZ_RX_DESCQ_SIZE_512 0
2278#define FRF_AZ_RX_DESCQ_TYPE_LBN 2
2279#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1
2280#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1
2281#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1
2282#define FRF_AZ_RX_DESCQ_EN_LBN 0
2283#define FRF_AZ_RX_DESCQ_EN_WIDTH 1
2284
2285/* TX_DESC_PTR_TBL_KER: Transmit descriptor pointer */
2286#define FR_AA_TX_DESC_PTR_TBL_KER 0x00011900
2287#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16
2288#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8
2289/* TX_DESC_PTR_TBL: Transmit descriptor pointer */
2290#define FR_BZ_TX_DESC_PTR_TBL 0x00f50000
2291#define FR_BZ_TX_DESC_PTR_TBL_STEP 16
2292#define FR_BB_TX_DESC_PTR_TBL_ROWS 4096
2293#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024
2294#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94
2295#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2
2296#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93
2297#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1
2298#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92
2299#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1
2300#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91
2301#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1
2302#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90
2303#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1
2304#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89
2305#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1
2306#define FRF_AZ_TX_DESCQ_EN_LBN 88
2307#define FRF_AZ_TX_DESCQ_EN_WIDTH 1
2308#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87
2309#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1
2310#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86
2311#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1
2312#define FRF_AZ_TX_DC_HW_RPTR_LBN 80
2313#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6
2314#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68
2315#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12
2316#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56
2317#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12
2318#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36
2319#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20
2320#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24
2321#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12
2322#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10
2323#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14
2324#define FRF_AZ_TX_DESCQ_LABEL_LBN 5
2325#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5
2326#define FRF_AZ_TX_DESCQ_SIZE_LBN 3
2327#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2
2328#define FFE_AZ_TX_DESCQ_SIZE_4K 3
2329#define FFE_AZ_TX_DESCQ_SIZE_2K 2
2330#define FFE_AZ_TX_DESCQ_SIZE_1K 1
2331#define FFE_AZ_TX_DESCQ_SIZE_512 0
2332#define FRF_AZ_TX_DESCQ_TYPE_LBN 1
2333#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2
2334#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0
2335#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1
2336
2337/* EVQ_PTR_TBL_KER: Event queue pointer table */
2338#define FR_AA_EVQ_PTR_TBL_KER 0x00011a00
2339#define FR_AA_EVQ_PTR_TBL_KER_STEP 16
2340#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4
2341/* EVQ_PTR_TBL: Event queue pointer table */
2342#define FR_BZ_EVQ_PTR_TBL 0x00f60000
2343#define FR_BZ_EVQ_PTR_TBL_STEP 16
2344#define FR_CZ_EVQ_PTR_TBL_ROWS 1024
2345#define FR_BB_EVQ_PTR_TBL_ROWS 4096
2346#define FRF_BZ_EVQ_RPTR_IGN_LBN 40
2347#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1
2348#define FRF_AB_EVQ_WKUP_OR_INT_EN_LBN 39
2349#define FRF_AB_EVQ_WKUP_OR_INT_EN_WIDTH 1
2350#define FRF_CZ_EVQ_DOS_PROTECT_EN_LBN 39
2351#define FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH 1
2352#define FRF_AZ_EVQ_NXT_WPTR_LBN 24
2353#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15
2354#define FRF_AZ_EVQ_EN_LBN 23
2355#define FRF_AZ_EVQ_EN_WIDTH 1
2356#define FRF_AZ_EVQ_SIZE_LBN 20
2357#define FRF_AZ_EVQ_SIZE_WIDTH 3
2358#define FFE_AZ_EVQ_SIZE_32K 6
2359#define FFE_AZ_EVQ_SIZE_16K 5
2360#define FFE_AZ_EVQ_SIZE_8K 4
2361#define FFE_AZ_EVQ_SIZE_4K 3
2362#define FFE_AZ_EVQ_SIZE_2K 2
2363#define FFE_AZ_EVQ_SIZE_1K 1
2364#define FFE_AZ_EVQ_SIZE_512 0
2365#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0
2366#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20
2367
2368/* BUF_HALF_TBL_KER: Buffer table in half buffer table mode direct access by driver */
2369#define FR_AA_BUF_HALF_TBL_KER 0x00018000
2370#define FR_AA_BUF_HALF_TBL_KER_STEP 8
2371#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096
2372/* BUF_HALF_TBL: Buffer table in half buffer table mode direct access by driver */
2373#define FR_BZ_BUF_HALF_TBL 0x00800000
2374#define FR_BZ_BUF_HALF_TBL_STEP 8
2375#define FR_CZ_BUF_HALF_TBL_ROWS 147456
2376#define FR_BB_BUF_HALF_TBL_ROWS 524288
2377#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44
2378#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20
2379#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32
2380#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12
2381#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12
2382#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20
2383#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0
2384#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
2385
2386/* BUF_FULL_TBL_KER: Buffer table in full buffer table mode direct access by driver */
2387#define FR_AA_BUF_FULL_TBL_KER 0x00018000
2388#define FR_AA_BUF_FULL_TBL_KER_STEP 8
2389#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096
2390/* BUF_FULL_TBL: Buffer table in full buffer table mode direct access by driver */
2391#define FR_BZ_BUF_FULL_TBL 0x00800000
2392#define FR_BZ_BUF_FULL_TBL_STEP 8
2393#define FR_CZ_BUF_FULL_TBL_ROWS 147456
2394#define FR_BB_BUF_FULL_TBL_ROWS 917504
2395#define FRF_AZ_BUF_FULL_UNUSED_LBN 51
2396#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13
2397#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50
2398#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1
2399#define FRF_AZ_BUF_ADR_REGION_LBN 48
2400#define FRF_AZ_BUF_ADR_REGION_WIDTH 2
2401#define FFE_AZ_BUF_ADR_REGN3 3
2402#define FFE_AZ_BUF_ADR_REGN2 2
2403#define FFE_AZ_BUF_ADR_REGN1 1
2404#define FFE_AZ_BUF_ADR_REGN0 0
2405#define FRF_AZ_BUF_ADR_FBUF_LBN 14
2406#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34
2407#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0
2408#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14
2409
2410/* RX_FILTER_TBL0: TCP/IPv4 Receive filter table */
2411#define FR_BZ_RX_FILTER_TBL0 0x00f00000
2412#define FR_BZ_RX_FILTER_TBL0_STEP 32
2413#define FR_BZ_RX_FILTER_TBL0_ROWS 8192
2414/* RX_FILTER_TBL1: TCP/IPv4 Receive filter table */
2415#define FR_BB_RX_FILTER_TBL1 0x00f00010
2416#define FR_BB_RX_FILTER_TBL1_STEP 32
2417#define FR_BB_RX_FILTER_TBL1_ROWS 8192
2418#define FRF_BZ_RSS_EN_LBN 110
2419#define FRF_BZ_RSS_EN_WIDTH 1
2420#define FRF_BZ_SCATTER_EN_LBN 109
2421#define FRF_BZ_SCATTER_EN_WIDTH 1
2422#define FRF_BZ_TCP_UDP_LBN 108
2423#define FRF_BZ_TCP_UDP_WIDTH 1
2424#define FRF_BZ_RXQ_ID_LBN 96
2425#define FRF_BZ_RXQ_ID_WIDTH 12
2426#define FRF_BZ_DEST_IP_LBN 64
2427#define FRF_BZ_DEST_IP_WIDTH 32
2428#define FRF_BZ_DEST_PORT_TCP_LBN 48
2429#define FRF_BZ_DEST_PORT_TCP_WIDTH 16
2430#define FRF_BZ_SRC_IP_LBN 16
2431#define FRF_BZ_SRC_IP_WIDTH 32
2432#define FRF_BZ_SRC_TCP_DEST_UDP_LBN 0
2433#define FRF_BZ_SRC_TCP_DEST_UDP_WIDTH 16
2434
2435/* RX_MAC_FILTER_TBL0: Receive Ethernet filter table */
2436#define FR_CZ_RX_MAC_FILTER_TBL0 0x00f00010
2437#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32
2438#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512
2439#define FRF_CZ_RMFT_RSS_EN_LBN 75
2440#define FRF_CZ_RMFT_RSS_EN_WIDTH 1
2441#define FRF_CZ_RMFT_SCATTER_EN_LBN 74
2442#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1
2443#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73
2444#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1
2445#define FRF_CZ_RMFT_RXQ_ID_LBN 61
2446#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12
2447#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60
2448#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1
2449#define FRF_CZ_RMFT_DEST_MAC_LBN 16
2450#define FRF_CZ_RMFT_DEST_MAC_WIDTH 44
2451#define FRF_CZ_RMFT_VLAN_ID_LBN 0
2452#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12
2453
2454/* TIMER_TBL: Timer table */
2455#define FR_BZ_TIMER_TBL 0x00f70000
2456#define FR_BZ_TIMER_TBL_STEP 16
2457#define FR_CZ_TIMER_TBL_ROWS 1024
2458#define FR_BB_TIMER_TBL_ROWS 4096
2459#define FRF_CZ_TIMER_Q_EN_LBN 33
2460#define FRF_CZ_TIMER_Q_EN_WIDTH 1
2461#define FRF_CZ_INT_ARMD_LBN 32
2462#define FRF_CZ_INT_ARMD_WIDTH 1
2463#define FRF_CZ_INT_PEND_LBN 31
2464#define FRF_CZ_INT_PEND_WIDTH 1
2465#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30
2466#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1
2467#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16
2468#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14
2469#define FRF_CZ_TIMER_MODE_LBN 14
2470#define FRF_CZ_TIMER_MODE_WIDTH 2
2471#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3
2472#define FFE_CZ_TIMER_MODE_TRIG_START 2
2473#define FFE_CZ_TIMER_MODE_IMMED_START 1
2474#define FFE_CZ_TIMER_MODE_DIS 0
2475#define FRF_BB_TIMER_MODE_LBN 12
2476#define FRF_BB_TIMER_MODE_WIDTH 2
2477#define FFE_BB_TIMER_MODE_INT_HLDOFF 2
2478#define FFE_BB_TIMER_MODE_TRIG_START 2
2479#define FFE_BB_TIMER_MODE_IMMED_START 1
2480#define FFE_BB_TIMER_MODE_DIS 0
2481#define FRF_CZ_TIMER_VAL_LBN 0
2482#define FRF_CZ_TIMER_VAL_WIDTH 14
2483#define FRF_BB_TIMER_VAL_LBN 0
2484#define FRF_BB_TIMER_VAL_WIDTH 12
2485
2486/* TX_PACE_TBL: Transmit pacing table */
2487#define FR_BZ_TX_PACE_TBL 0x00f80000
2488#define FR_BZ_TX_PACE_TBL_STEP 16
2489#define FR_CZ_TX_PACE_TBL_ROWS 1024
2490#define FR_BB_TX_PACE_TBL_ROWS 4096
2491#define FRF_BZ_TX_PACE_LBN 0
2492#define FRF_BZ_TX_PACE_WIDTH 5
2493
2494/* RX_INDIRECTION_TBL: RX Indirection Table */
2495#define FR_BZ_RX_INDIRECTION_TBL 0x00fb0000
2496#define FR_BZ_RX_INDIRECTION_TBL_STEP 16
2497#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128
2498#define FRF_BZ_IT_QUEUE_LBN 0
2499#define FRF_BZ_IT_QUEUE_WIDTH 6
2500
2501/* TX_FILTER_TBL0: TCP/IPv4 Transmit filter table */
2502#define FR_CZ_TX_FILTER_TBL0 0x00fc0000
2503#define FR_CZ_TX_FILTER_TBL0_STEP 16
2504#define FR_CZ_TX_FILTER_TBL0_ROWS 8192
2505#define FRF_CZ_TIFT_TCP_UDP_LBN 108
2506#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1
2507#define FRF_CZ_TIFT_TXQ_ID_LBN 96
2508#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12
2509#define FRF_CZ_TIFT_DEST_IP_LBN 64
2510#define FRF_CZ_TIFT_DEST_IP_WIDTH 32
2511#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48
2512#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16
2513#define FRF_CZ_TIFT_SRC_IP_LBN 16
2514#define FRF_CZ_TIFT_SRC_IP_WIDTH 32
2515#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0
2516#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16
2517
2518/* TX_MAC_FILTER_TBL0: Transmit Ethernet filter table */
2519#define FR_CZ_TX_MAC_FILTER_TBL0 0x00fe0000
2520#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16
2521#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512
2522#define FRF_CZ_TMFT_TXQ_ID_LBN 61
2523#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12
2524#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60
2525#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1
2526#define FRF_CZ_TMFT_SRC_MAC_LBN 16
2527#define FRF_CZ_TMFT_SRC_MAC_WIDTH 44
2528#define FRF_CZ_TMFT_VLAN_ID_LBN 0
2529#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12
2530
2531/* MC_TREG_SMEM: MC Shared Memory */
2532#define FR_CZ_MC_TREG_SMEM 0x00ff0000
2533#define FR_CZ_MC_TREG_SMEM_STEP 4
2534#define FR_CZ_MC_TREG_SMEM_ROWS 512
2535#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0
2536#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32
2537
2538/* MSIX_VECTOR_TABLE: MSIX Vector Table */
2539#define FR_BB_MSIX_VECTOR_TABLE 0x00ff0000
2540#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16
2541#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64
2542/* MSIX_VECTOR_TABLE: MSIX Vector Table */
2543#define FR_CZ_MSIX_VECTOR_TABLE 0x00000000
2544/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */
2545#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024
2546#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97
2547#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31
2548#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96
2549#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1
2550#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64
2551#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32
2552#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32
2553#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32
2554#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0
2555#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32
2556
2557/* MSIX_PBA_TABLE: MSIX Pending Bit Array */
2558#define FR_BB_MSIX_PBA_TABLE 0x00ff2000
2559#define FR_BZ_MSIX_PBA_TABLE_STEP 4
2560#define FR_BB_MSIX_PBA_TABLE_ROWS 2
2561/* MSIX_PBA_TABLE: MSIX Pending Bit Array */
2562#define FR_CZ_MSIX_PBA_TABLE 0x00008000
2563/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */
2564#define FR_CZ_MSIX_PBA_TABLE_ROWS 32
2565#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0
2566#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32
2567
2568/* SRM_DBG_REG: SRAM debug access */
2569#define FR_BZ_SRM_DBG 0x03000000
2570#define FR_BZ_SRM_DBG_STEP 8
2571#define FR_CZ_SRM_DBG_ROWS 262144
2572#define FR_BB_SRM_DBG_ROWS 2097152
2573#define FRF_BZ_SRM_DBG_LBN 0
2574#define FRF_BZ_SRM_DBG_WIDTH 64
2575
2576/* TB_MSIX_PBA_TABLE: MSIX Pending Bit Array */
2577#define FR_CZ_TB_MSIX_PBA_TABLE 0x00008000
2578#define FR_CZ_TB_MSIX_PBA_TABLE_STEP 4
2579#define FR_CZ_TB_MSIX_PBA_TABLE_ROWS 1024
2580#define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_LBN 0
2581#define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_WIDTH 32
2582
2583/* DRIVER_EV */
2584#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56
2585#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4
2586#define FSE_BZ_TX_DSC_ERROR_EV 15
2587#define FSE_BZ_RX_DSC_ERROR_EV 14
2588#define FSE_AA_RX_RECOVER_EV 11
2589#define FSE_AZ_TIMER_EV 10
2590#define FSE_AZ_TX_PKT_NON_TCP_UDP 9
2591#define FSE_AZ_WAKE_UP_EV 6
2592#define FSE_AZ_SRM_UPD_DONE_EV 5
2593#define FSE_AB_EVQ_NOT_EN_EV 3
2594#define FSE_AZ_EVQ_INIT_DONE_EV 2
2595#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1
2596#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0
2597#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0
2598#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14
2599
2600/* EVENT_ENTRY */
2601#define FSF_AZ_EV_CODE_LBN 60
2602#define FSF_AZ_EV_CODE_WIDTH 4
2603#define FSE_CZ_EV_CODE_MCDI_EV 12
2604#define FSE_CZ_EV_CODE_USER_EV 8
2605#define FSE_AZ_EV_CODE_DRV_GEN_EV 7
2606#define FSE_AZ_EV_CODE_GLOBAL_EV 6
2607#define FSE_AZ_EV_CODE_DRIVER_EV 5
2608#define FSE_AZ_EV_CODE_TX_EV 2
2609#define FSE_AZ_EV_CODE_RX_EV 0
2610#define FSF_AZ_EV_DATA_LBN 0
2611#define FSF_AZ_EV_DATA_WIDTH 60
2612
2613/* GLOBAL_EV */
2614#define FSF_BB_GLB_EV_RX_RECOVERY_LBN 12
2615#define FSF_BB_GLB_EV_RX_RECOVERY_WIDTH 1
2616#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 11
2617#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1
2618#define FSF_BB_GLB_EV_XG_MGT_INTR_LBN 11
2619#define FSF_BB_GLB_EV_XG_MGT_INTR_WIDTH 1
2620#define FSF_AB_GLB_EV_XFP_PHY0_INTR_LBN 10
2621#define FSF_AB_GLB_EV_XFP_PHY0_INTR_WIDTH 1
2622#define FSF_AB_GLB_EV_XG_PHY0_INTR_LBN 9
2623#define FSF_AB_GLB_EV_XG_PHY0_INTR_WIDTH 1
2624#define FSF_AB_GLB_EV_G_PHY0_INTR_LBN 7
2625#define FSF_AB_GLB_EV_G_PHY0_INTR_WIDTH 1
2626
2627/* LEGACY_INT_VEC */
2628#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64
2629#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1
2630#define FSF_AZ_NET_IVEC_INT_Q_LBN 40
2631#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4
2632#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32
2633#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1
2634#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1
2635#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1
2636#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0
2637#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1
2638
2639/* MC_XGMAC_FLTR_RULE_DEF */
2640#define FSF_CZ_MC_XFRC_MODE_LBN 416
2641#define FSF_CZ_MC_XFRC_MODE_WIDTH 1
2642#define FSE_CZ_MC_XFRC_MODE_LAYERED 1
2643#define FSE_CZ_MC_XFRC_MODE_SIMPLE 0
2644#define FSF_CZ_MC_XFRC_HASH_LBN 384
2645#define FSF_CZ_MC_XFRC_HASH_WIDTH 32
2646#define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 256
2647#define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 128
2648#define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 128
2649#define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 128
2650#define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 0
2651#define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 128
2652
2653/* RX_EV */
2654#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58
2655#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1
2656#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57
2657#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1
2658#define FSF_AZ_RX_EV_PKT_OK_LBN 56
2659#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1
2660#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55
2661#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1
2662#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54
2663#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
2664#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53
2665#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1
2666#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
2667#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
2668#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
2669#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
2670#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50
2671#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1
2672#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49
2673#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1
2674#define FSF_AA_RX_EV_DRIB_NIB_LBN 49
2675#define FSF_AA_RX_EV_DRIB_NIB_WIDTH 1
2676#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47
2677#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1
2678#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44
2679#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3
2680#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5
2681#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4
2682#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3
2683#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2
2684#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1
2685#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0
2686#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42
2687#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2
2688#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3
2689#define FSE_AB_RX_EV_HDR_TYPE_IPV4_OTHER 2
2690#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2
2691#define FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP 1
2692#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1
2693#define FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP 0
2694#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0
2695#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41
2696#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1
2697#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40
2698#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1
2699#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39
2700#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1
2701#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37
2702#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1
2703#define FSF_AZ_RX_EV_Q_LABEL_LBN 32
2704#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5
2705#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31
2706#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1
2707#define FSF_AZ_RX_EV_PORT_LBN 30
2708#define FSF_AZ_RX_EV_PORT_WIDTH 1
2709#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16
2710#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14
2711#define FSF_AZ_RX_EV_SOP_LBN 15
2712#define FSF_AZ_RX_EV_SOP_WIDTH 1
2713#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14
2714#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1
2715#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13
2716#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1
2717#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12
2718#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1
2719#define FSF_AZ_RX_EV_DESC_PTR_LBN 0
2720#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12
2721
2722/* RX_KER_DESC */
2723#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48
2724#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14
2725#define FSF_AZ_RX_KER_BUF_REGION_LBN 46
2726#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2
2727#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0
2728#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46
2729
2730/* RX_USER_DESC */
2731#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20
2732#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12
2733#define FSF_AZ_RX_USER_BUF_ID_LBN 0
2734#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20
2735
2736/* TX_EV */
2737#define FSF_AZ_TX_EV_PKT_ERR_LBN 38
2738#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1
2739#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37
2740#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1
2741#define FSF_AZ_TX_EV_Q_LABEL_LBN 32
2742#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5
2743#define FSF_AZ_TX_EV_PORT_LBN 16
2744#define FSF_AZ_TX_EV_PORT_WIDTH 1
2745#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15
2746#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1
2747#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14
2748#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1
2749#define FSF_AZ_TX_EV_COMP_LBN 12
2750#define FSF_AZ_TX_EV_COMP_WIDTH 1
2751#define FSF_AZ_TX_EV_DESC_PTR_LBN 0
2752#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12
2753
2754/* TX_KER_DESC */
2755#define FSF_AZ_TX_KER_CONT_LBN 62
2756#define FSF_AZ_TX_KER_CONT_WIDTH 1
2757#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48
2758#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14
2759#define FSF_AZ_TX_KER_BUF_REGION_LBN 46
2760#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2
2761#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0
2762#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46
2763
2764/* TX_USER_DESC */
2765#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48
2766#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1
2767#define FSF_AZ_TX_USER_CONT_LBN 46
2768#define FSF_AZ_TX_USER_CONT_WIDTH 1
2769#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33
2770#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13
2771#define FSF_AZ_TX_USER_BUF_ID_LBN 13
2772#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20
2773#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0
2774#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13
2775
2776/* USER_EV */
2777#define FSF_CZ_USER_QID_LBN 32
2778#define FSF_CZ_USER_QID_WIDTH 10
2779#define FSF_CZ_USER_EV_REG_VALUE_LBN 0
2780#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32
2781
2782/**************************************************************************
2783 *
2784 * Falcon B0 PCIe core indirect registers
2785 *
2786 **************************************************************************
2787 */
2788
2789#define FPCR_BB_PCIE_DEVICE_CTRL_STAT 0x68
2790
2791#define FPCR_BB_PCIE_LINK_CTRL_STAT 0x70
2792
2793#define FPCR_BB_ACK_RPL_TIMER 0x700
2794#define FPCRF_BB_ACK_TL_LBN 0
2795#define FPCRF_BB_ACK_TL_WIDTH 16
2796#define FPCRF_BB_RPL_TL_LBN 16
2797#define FPCRF_BB_RPL_TL_WIDTH 16
2798
2799#define FPCR_BB_ACK_FREQ 0x70C
2800#define FPCRF_BB_ACK_FREQ_LBN 0
2801#define FPCRF_BB_ACK_FREQ_WIDTH 7
2802
2803/**************************************************************************
2804 *
2805 * Pseudo-registers and fields
2806 *
2807 **************************************************************************
2808 */
2809
2810/* Interrupt acknowledge work-around register (A0/A1 only) */
2811#define FR_AA_WORK_AROUND_BROKEN_PCI_READS 0x0070
2812
2813/* EE_SPI_HCMD_REG: SPI host command register */
2814/* Values for the EE_SPI_HCMD_SF_SEL register field */
2815#define FFE_AB_SPI_DEVICE_EEPROM 0
2816#define FFE_AB_SPI_DEVICE_FLASH 1
2817
2818/* NIC_STAT_REG: NIC status register */
2819#define FRF_AB_STRAP_10G_LBN 2
2820#define FRF_AB_STRAP_10G_WIDTH 1
2821#define FRF_AA_STRAP_PCIE_LBN 0
2822#define FRF_AA_STRAP_PCIE_WIDTH 1
2823
2824/* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */
2825#define FRF_AZ_FATAL_INTR_LBN 0
2826#define FRF_AZ_FATAL_INTR_WIDTH 12
2827
2828/* SRM_CFG_REG: SRAM configuration register */
2829/* We treat the number of SRAM banks and bank size as a single field */
2830#define FRF_AZ_SRM_NB_SZ_LBN FRF_AZ_SRM_BANK_SIZE_LBN
2831#define FRF_AZ_SRM_NB_SZ_WIDTH \
2832 (FRF_AZ_SRM_BANK_SIZE_WIDTH + FRF_AZ_SRM_NUM_BANK_WIDTH)
2833#define FFE_AB_SRM_NB1_SZ2M 0
2834#define FFE_AB_SRM_NB1_SZ4M 1
2835#define FFE_AB_SRM_NB1_SZ8M 2
2836#define FFE_AB_SRM_NB_SZ_DEF 3
2837#define FFE_AB_SRM_NB2_SZ4M 4
2838#define FFE_AB_SRM_NB2_SZ8M 5
2839#define FFE_AB_SRM_NB2_SZ16M 6
2840#define FFE_AB_SRM_NB_SZ_RES 7
2841
2842/* RX_DESC_UPD_REGP0: Receive descriptor update register. */
2843/* We write just the last dword of these registers */
2844#define FR_AZ_RX_DESC_UPD_DWORD_P0 \
2845 (BUILD_BUG_ON_ZERO(FR_AA_RX_DESC_UPD_KER != FR_BZ_RX_DESC_UPD_P0) + \
2846 FR_BZ_RX_DESC_UPD_P0 + 3 * 4)
2847#define FRF_AZ_RX_DESC_WPTR_DWORD_LBN (FRF_AZ_RX_DESC_WPTR_LBN - 3 * 32)
2848#define FRF_AZ_RX_DESC_WPTR_DWORD_WIDTH FRF_AZ_RX_DESC_WPTR_WIDTH
2849
2850/* TX_DESC_UPD_REGP0: Transmit descriptor update register. */
2851#define FR_AZ_TX_DESC_UPD_DWORD_P0 \
2852 (BUILD_BUG_ON_ZERO(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0) + \
2853 FR_BZ_TX_DESC_UPD_P0 + 3 * 4)
2854#define FRF_AZ_TX_DESC_WPTR_DWORD_LBN (FRF_AZ_TX_DESC_WPTR_LBN - 3 * 32)
2855#define FRF_AZ_TX_DESC_WPTR_DWORD_WIDTH FRF_AZ_TX_DESC_WPTR_WIDTH
2856
2857/* GMF_CFG4_REG: GMAC FIFO configuration register 4 */
2858#define FRF_AB_GMF_HSTFLTRFRM_PAUSE_LBN 12
2859#define FRF_AB_GMF_HSTFLTRFRM_PAUSE_WIDTH 1
2860
2861/* GMF_CFG5_REG: GMAC FIFO configuration register 5 */
2862#define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_LBN 12
2863#define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
2864
2865/* XM_TX_PARAM_REG: XGMAC transmit parameter register */
2866#define FRF_AB_XM_MAX_TX_FRM_SIZE_LBN FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN
2867#define FRF_AB_XM_MAX_TX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH + \
2868 FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH)
2869
2870/* XM_RX_PARAM_REG: XGMAC receive parameter register */
2871#define FRF_AB_XM_MAX_RX_FRM_SIZE_LBN FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN
2872#define FRF_AB_XM_MAX_RX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH + \
2873 FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH)
2874
2875/* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */
2876/* Default values */
2877#define FFE_AB_XX_TXDRV_DEQ_DEF 0xe /* deq=.6 */
2878#define FFE_AB_XX_TXDRV_DTX_DEF 0x5 /* 1.25 */
2879#define FFE_AB_XX_SD_CTL_DRV_DEF 0 /* 20mA */
2880
2881/* XX_CORE_STAT_REG: XAUI XGXS core status register */
2882/* XGXS all-lanes status fields */
2883#define FRF_AB_XX_SYNC_STAT_LBN FRF_AB_XX_SYNC_STAT0_LBN
2884#define FRF_AB_XX_SYNC_STAT_WIDTH 4
2885#define FRF_AB_XX_COMMA_DET_LBN FRF_AB_XX_COMMA_DET_CH0_LBN
2886#define FRF_AB_XX_COMMA_DET_WIDTH 4
2887#define FRF_AB_XX_CHAR_ERR_LBN FRF_AB_XX_CHAR_ERR_CH0_LBN
2888#define FRF_AB_XX_CHAR_ERR_WIDTH 4
2889#define FRF_AB_XX_DISPERR_LBN FRF_AB_XX_DISPERR_CH0_LBN
2890#define FRF_AB_XX_DISPERR_WIDTH 4
2891#define FFE_AB_XX_STAT_ALL_LANES 0xf
2892#define FRF_AB_XX_FORCE_SIG_LBN FRF_AB_XX_FORCE_SIG0_VAL_LBN
2893#define FRF_AB_XX_FORCE_SIG_WIDTH 8
2894#define FFE_AB_XX_FORCE_SIG_ALL_LANES 0xff
2895
2896/* DRIVER_EV */
2897/* Sub-fields of an RX flush completion event */
2898#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12
2899#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
2900#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0
2901#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12
2902
2903/* EVENT_ENTRY */
2904/* Magic number field for event test */
2905#define FSF_AZ_DRV_GEN_EV_MAGIC_LBN 0
2906#define FSF_AZ_DRV_GEN_EV_MAGIC_WIDTH 32
2907
2908/**************************************************************************
2909 *
2910 * Falcon MAC stats
2911 *
2912 **************************************************************************
2913 *
2914 */
2915
2916#define GRxGoodOct_offset 0x0
2917#define GRxGoodOct_WIDTH 48
2918#define GRxBadOct_offset 0x8
2919#define GRxBadOct_WIDTH 48
2920#define GRxMissPkt_offset 0x10
2921#define GRxMissPkt_WIDTH 32
2922#define GRxFalseCRS_offset 0x14
2923#define GRxFalseCRS_WIDTH 32
2924#define GRxPausePkt_offset 0x18
2925#define GRxPausePkt_WIDTH 32
2926#define GRxBadPkt_offset 0x1C
2927#define GRxBadPkt_WIDTH 32
2928#define GRxUcastPkt_offset 0x20
2929#define GRxUcastPkt_WIDTH 32
2930#define GRxMcastPkt_offset 0x24
2931#define GRxMcastPkt_WIDTH 32
2932#define GRxBcastPkt_offset 0x28
2933#define GRxBcastPkt_WIDTH 32
2934#define GRxGoodLt64Pkt_offset 0x2C
2935#define GRxGoodLt64Pkt_WIDTH 32
2936#define GRxBadLt64Pkt_offset 0x30
2937#define GRxBadLt64Pkt_WIDTH 32
2938#define GRx64Pkt_offset 0x34
2939#define GRx64Pkt_WIDTH 32
2940#define GRx65to127Pkt_offset 0x38
2941#define GRx65to127Pkt_WIDTH 32
2942#define GRx128to255Pkt_offset 0x3C
2943#define GRx128to255Pkt_WIDTH 32
2944#define GRx256to511Pkt_offset 0x40
2945#define GRx256to511Pkt_WIDTH 32
2946#define GRx512to1023Pkt_offset 0x44
2947#define GRx512to1023Pkt_WIDTH 32
2948#define GRx1024to15xxPkt_offset 0x48
2949#define GRx1024to15xxPkt_WIDTH 32
2950#define GRx15xxtoJumboPkt_offset 0x4C
2951#define GRx15xxtoJumboPkt_WIDTH 32
2952#define GRxGtJumboPkt_offset 0x50
2953#define GRxGtJumboPkt_WIDTH 32
2954#define GRxFcsErr64to15xxPkt_offset 0x54
2955#define GRxFcsErr64to15xxPkt_WIDTH 32
2956#define GRxFcsErr15xxtoJumboPkt_offset 0x58
2957#define GRxFcsErr15xxtoJumboPkt_WIDTH 32
2958#define GRxFcsErrGtJumboPkt_offset 0x5C
2959#define GRxFcsErrGtJumboPkt_WIDTH 32
2960#define GTxGoodBadOct_offset 0x80
2961#define GTxGoodBadOct_WIDTH 48
2962#define GTxGoodOct_offset 0x88
2963#define GTxGoodOct_WIDTH 48
2964#define GTxSglColPkt_offset 0x90
2965#define GTxSglColPkt_WIDTH 32
2966#define GTxMultColPkt_offset 0x94
2967#define GTxMultColPkt_WIDTH 32
2968#define GTxExColPkt_offset 0x98
2969#define GTxExColPkt_WIDTH 32
2970#define GTxDefPkt_offset 0x9C
2971#define GTxDefPkt_WIDTH 32
2972#define GTxLateCol_offset 0xA0
2973#define GTxLateCol_WIDTH 32
2974#define GTxExDefPkt_offset 0xA4
2975#define GTxExDefPkt_WIDTH 32
2976#define GTxPausePkt_offset 0xA8
2977#define GTxPausePkt_WIDTH 32
2978#define GTxBadPkt_offset 0xAC
2979#define GTxBadPkt_WIDTH 32
2980#define GTxUcastPkt_offset 0xB0
2981#define GTxUcastPkt_WIDTH 32
2982#define GTxMcastPkt_offset 0xB4
2983#define GTxMcastPkt_WIDTH 32
2984#define GTxBcastPkt_offset 0xB8
2985#define GTxBcastPkt_WIDTH 32
2986#define GTxLt64Pkt_offset 0xBC
2987#define GTxLt64Pkt_WIDTH 32
2988#define GTx64Pkt_offset 0xC0
2989#define GTx64Pkt_WIDTH 32
2990#define GTx65to127Pkt_offset 0xC4
2991#define GTx65to127Pkt_WIDTH 32
2992#define GTx128to255Pkt_offset 0xC8
2993#define GTx128to255Pkt_WIDTH 32
2994#define GTx256to511Pkt_offset 0xCC
2995#define GTx256to511Pkt_WIDTH 32
2996#define GTx512to1023Pkt_offset 0xD0
2997#define GTx512to1023Pkt_WIDTH 32
2998#define GTx1024to15xxPkt_offset 0xD4
2999#define GTx1024to15xxPkt_WIDTH 32
3000#define GTx15xxtoJumboPkt_offset 0xD8
3001#define GTx15xxtoJumboPkt_WIDTH 32
3002#define GTxGtJumboPkt_offset 0xDC
3003#define GTxGtJumboPkt_WIDTH 32
3004#define GTxNonTcpUdpPkt_offset 0xE0
3005#define GTxNonTcpUdpPkt_WIDTH 16
3006#define GTxMacSrcErrPkt_offset 0xE4
3007#define GTxMacSrcErrPkt_WIDTH 16
3008#define GTxIpSrcErrPkt_offset 0xE8
3009#define GTxIpSrcErrPkt_WIDTH 16
3010#define GDmaDone_offset 0xEC
3011#define GDmaDone_WIDTH 32
3012
3013#define XgRxOctets_offset 0x0
3014#define XgRxOctets_WIDTH 48
3015#define XgRxOctetsOK_offset 0x8
3016#define XgRxOctetsOK_WIDTH 48
3017#define XgRxPkts_offset 0x10
3018#define XgRxPkts_WIDTH 32
3019#define XgRxPktsOK_offset 0x14
3020#define XgRxPktsOK_WIDTH 32
3021#define XgRxBroadcastPkts_offset 0x18
3022#define XgRxBroadcastPkts_WIDTH 32
3023#define XgRxMulticastPkts_offset 0x1C
3024#define XgRxMulticastPkts_WIDTH 32
3025#define XgRxUnicastPkts_offset 0x20
3026#define XgRxUnicastPkts_WIDTH 32
3027#define XgRxUndersizePkts_offset 0x24
3028#define XgRxUndersizePkts_WIDTH 32
3029#define XgRxOversizePkts_offset 0x28
3030#define XgRxOversizePkts_WIDTH 32
3031#define XgRxJabberPkts_offset 0x2C
3032#define XgRxJabberPkts_WIDTH 32
3033#define XgRxUndersizeFCSerrorPkts_offset 0x30
3034#define XgRxUndersizeFCSerrorPkts_WIDTH 32
3035#define XgRxDropEvents_offset 0x34
3036#define XgRxDropEvents_WIDTH 32
3037#define XgRxFCSerrorPkts_offset 0x38
3038#define XgRxFCSerrorPkts_WIDTH 32
3039#define XgRxAlignError_offset 0x3C
3040#define XgRxAlignError_WIDTH 32
3041#define XgRxSymbolError_offset 0x40
3042#define XgRxSymbolError_WIDTH 32
3043#define XgRxInternalMACError_offset 0x44
3044#define XgRxInternalMACError_WIDTH 32
3045#define XgRxControlPkts_offset 0x48
3046#define XgRxControlPkts_WIDTH 32
3047#define XgRxPausePkts_offset 0x4C
3048#define XgRxPausePkts_WIDTH 32
3049#define XgRxPkts64Octets_offset 0x50
3050#define XgRxPkts64Octets_WIDTH 32
3051#define XgRxPkts65to127Octets_offset 0x54
3052#define XgRxPkts65to127Octets_WIDTH 32
3053#define XgRxPkts128to255Octets_offset 0x58
3054#define XgRxPkts128to255Octets_WIDTH 32
3055#define XgRxPkts256to511Octets_offset 0x5C
3056#define XgRxPkts256to511Octets_WIDTH 32
3057#define XgRxPkts512to1023Octets_offset 0x60
3058#define XgRxPkts512to1023Octets_WIDTH 32
3059#define XgRxPkts1024to15xxOctets_offset 0x64
3060#define XgRxPkts1024to15xxOctets_WIDTH 32
3061#define XgRxPkts15xxtoMaxOctets_offset 0x68
3062#define XgRxPkts15xxtoMaxOctets_WIDTH 32
3063#define XgRxLengthError_offset 0x6C
3064#define XgRxLengthError_WIDTH 32
3065#define XgTxPkts_offset 0x80
3066#define XgTxPkts_WIDTH 32
3067#define XgTxOctets_offset 0x88
3068#define XgTxOctets_WIDTH 48
3069#define XgTxMulticastPkts_offset 0x90
3070#define XgTxMulticastPkts_WIDTH 32
3071#define XgTxBroadcastPkts_offset 0x94
3072#define XgTxBroadcastPkts_WIDTH 32
3073#define XgTxUnicastPkts_offset 0x98
3074#define XgTxUnicastPkts_WIDTH 32
3075#define XgTxControlPkts_offset 0x9C
3076#define XgTxControlPkts_WIDTH 32
3077#define XgTxPausePkts_offset 0xA0
3078#define XgTxPausePkts_WIDTH 32
3079#define XgTxPkts64Octets_offset 0xA4
3080#define XgTxPkts64Octets_WIDTH 32
3081#define XgTxPkts65to127Octets_offset 0xA8
3082#define XgTxPkts65to127Octets_WIDTH 32
3083#define XgTxPkts128to255Octets_offset 0xAC
3084#define XgTxPkts128to255Octets_WIDTH 32
3085#define XgTxPkts256to511Octets_offset 0xB0
3086#define XgTxPkts256to511Octets_WIDTH 32
3087#define XgTxPkts512to1023Octets_offset 0xB4
3088#define XgTxPkts512to1023Octets_WIDTH 32
3089#define XgTxPkts1024to15xxOctets_offset 0xB8
3090#define XgTxPkts1024to15xxOctets_WIDTH 32
3091#define XgTxPkts1519toMaxOctets_offset 0xBC
3092#define XgTxPkts1519toMaxOctets_WIDTH 32
3093#define XgTxUndersizePkts_offset 0xC0
3094#define XgTxUndersizePkts_WIDTH 32
3095#define XgTxOversizePkts_offset 0xC4
3096#define XgTxOversizePkts_WIDTH 32
3097#define XgTxNonTcpUdpPkt_offset 0xC8
3098#define XgTxNonTcpUdpPkt_WIDTH 16
3099#define XgTxMacSrcErrPkt_offset 0xCC
3100#define XgTxMacSrcErrPkt_WIDTH 16
3101#define XgTxIpSrcErrPkt_offset 0xD0
3102#define XgTxIpSrcErrPkt_WIDTH 16
3103#define XgDmaDone_offset 0xD4
3104#define XgDmaDone_WIDTH 32
3105
3106#define FALCON_STATS_NOT_DONE 0x00000000
3107#define FALCON_STATS_DONE 0xffffffff
3108
3109/* Interrupt status register bits */
3110#define FATAL_INT_LBN 64
3111#define FATAL_INT_WIDTH 1
3112#define INT_EVQS_LBN 40
3113#define INT_EVQS_WIDTH 4
3114#define INT_FLAG_LBN 32
3115#define INT_FLAG_WIDTH 1
3116#define EVQ_FIFO_HF_LBN 1
3117#define EVQ_FIFO_HF_WIDTH 1
3118#define EVQ_FIFO_AF_LBN 0
3119#define EVQ_FIFO_AF_WIDTH 1
3120
3121/**************************************************************************
3122 *
3123 * Falcon non-volatile configuration
3124 *
3125 **************************************************************************
3126 */
3127
3128/* Board configuration v2 (v1 is obsolete; later versions are compatible) */
3129struct falcon_nvconfig_board_v2 {
3130 __le16 nports;
3131 u8 port0_phy_addr;
3132 u8 port0_phy_type;
3133 u8 port1_phy_addr;
3134 u8 port1_phy_type;
3135 __le16 asic_sub_revision;
3136 __le16 board_revision;
3137} __packed;
3138
3139/* Board configuration v3 extra information */
3140struct falcon_nvconfig_board_v3 {
3141 __le32 spi_device_type[2];
3142} __packed;
3143
3144/* Bit numbers for spi_device_type */
3145#define SPI_DEV_TYPE_SIZE_LBN 0
3146#define SPI_DEV_TYPE_SIZE_WIDTH 5
3147#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
3148#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
3149#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
3150#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
3151#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
3152#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
3153#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
3154#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
3155#define SPI_DEV_TYPE_FIELD(type, field) \
3156 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
3157
3158#define FALCON_NVCONFIG_OFFSET 0x300
3159
3160#define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
3161struct falcon_nvconfig {
3162 efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
3163 u8 mac_address[2][8]; /* 0x310 */
3164 efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
3165 efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
3166 efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
3167 efx_oword_t hw_init_reg; /* 0x350 */
3168 efx_oword_t nic_stat_reg; /* 0x360 */
3169 efx_oword_t glb_ctl_reg; /* 0x370 */
3170 efx_oword_t srm_cfg_reg; /* 0x380 */
3171 efx_oword_t spare_reg; /* 0x390 */
3172 __le16 board_magic_num; /* 0x3A0 */
3173 __le16 board_struct_ver;
3174 __le16 board_checksum;
3175 struct falcon_nvconfig_board_v2 board_v2;
3176 efx_oword_t ee_base_page_reg; /* 0x3B0 */
3177 struct falcon_nvconfig_board_v3 board_v3; /* 0x3C0 */
3178} __packed;
3179
3180#endif /* EFX_REGS_H */
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c
index f5797a3e1fe..390b27b5ace 100644
--- a/drivers/net/sfc/tenxpress.c
+++ b/drivers/net/sfc/tenxpress.c
@@ -14,7 +14,7 @@
14#include "mdio_10g.h" 14#include "mdio_10g.h"
15#include "falcon.h" 15#include "falcon.h"
16#include "phy.h" 16#include "phy.h"
17#include "falcon_hwdefs.h" 17#include "regs.h"
18#include "workarounds.h" 18#include "workarounds.h"
19#include "selftest.h" 19#include "selftest.h"
20 20
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 12:24:58 -0400