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authorAnilKumar Ch <anilkumar@ti.com>2012-05-29 01:43:15 -0400
committerMarc Kleine-Budde <mkl@pengutronix.de>2012-06-07 04:02:24 -0400
commit33f8100977693fa09c2a32b1ca6dbf4d6eabdd0c (patch)
tree8b28fd02dbe9c9ae460262a09b90ac3a80d4314a /drivers
parentc1864cfb80a64933c221e33fed9611356c031944 (diff)
can: c_can: Move overlay structure to array with offset as index
c_can uses overlay structure for accessing c_can module registers. With this kind of implementation it is difficult to add one more ip which is similar to c_can in functionality but different register offsets. This patch changes the overlay structure implementation to an array with register offset as index. This way we can overcome the above limitation. Signed-off-by: AnilKumar Ch <anilkumar@ti.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/can/c_can/c_can.c120
-rw-r--r--drivers/net/can/c_can/c_can.h118
-rw-r--r--drivers/net/can/c_can/c_can_platform.c23
3 files changed, 154 insertions, 107 deletions
diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c
index 8dc84d66eea..e2ce508c275 100644
--- a/drivers/net/can/c_can/c_can.c
+++ b/drivers/net/can/c_can/c_can.c
@@ -41,6 +41,10 @@
41 41
42#include "c_can.h" 42#include "c_can.h"
43 43
44/* Number of interface registers */
45#define IF_ENUM_REG_LEN 11
46#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
47
44/* control register */ 48/* control register */
45#define CONTROL_TEST BIT(7) 49#define CONTROL_TEST BIT(7)
46#define CONTROL_CCE BIT(6) 50#define CONTROL_CCE BIT(6)
@@ -209,10 +213,10 @@ static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
209 C_CAN_MSG_OBJ_TX_FIRST; 213 C_CAN_MSG_OBJ_TX_FIRST;
210} 214}
211 215
212static u32 c_can_read_reg32(struct c_can_priv *priv, void *reg) 216static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index)
213{ 217{
214 u32 val = priv->read_reg(priv, reg); 218 u32 val = priv->read_reg(priv, index);
215 val |= ((u32) priv->read_reg(priv, reg + 2)) << 16; 219 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
216 return val; 220 return val;
217} 221}
218 222
@@ -220,14 +224,14 @@ static void c_can_enable_all_interrupts(struct c_can_priv *priv,
220 int enable) 224 int enable)
221{ 225{
222 unsigned int cntrl_save = priv->read_reg(priv, 226 unsigned int cntrl_save = priv->read_reg(priv,
223 &priv->regs->control); 227 C_CAN_CTRL_REG);
224 228
225 if (enable) 229 if (enable)
226 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 230 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
227 else 231 else
228 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 232 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
229 233
230 priv->write_reg(priv, &priv->regs->control, cntrl_save); 234 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save);
231} 235}
232 236
233static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 237static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
@@ -235,7 +239,7 @@ static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
235 int count = MIN_TIMEOUT_VALUE; 239 int count = MIN_TIMEOUT_VALUE;
236 240
237 while (count && priv->read_reg(priv, 241 while (count && priv->read_reg(priv,
238 &priv->regs->ifregs[iface].com_req) & 242 C_CAN_IFACE(COMREQ_REG, iface)) &
239 IF_COMR_BUSY) { 243 IF_COMR_BUSY) {
240 count--; 244 count--;
241 udelay(1); 245 udelay(1);
@@ -258,9 +262,9 @@ static inline void c_can_object_get(struct net_device *dev,
258 * register and message RAM must be complete in 6 CAN-CLK 262 * register and message RAM must be complete in 6 CAN-CLK
259 * period. 263 * period.
260 */ 264 */
261 priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask, 265 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
262 IFX_WRITE_LOW_16BIT(mask)); 266 IFX_WRITE_LOW_16BIT(mask));
263 priv->write_reg(priv, &priv->regs->ifregs[iface].com_req, 267 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
264 IFX_WRITE_LOW_16BIT(objno)); 268 IFX_WRITE_LOW_16BIT(objno));
265 269
266 if (c_can_msg_obj_is_busy(priv, iface)) 270 if (c_can_msg_obj_is_busy(priv, iface))
@@ -278,9 +282,9 @@ static inline void c_can_object_put(struct net_device *dev,
278 * register and message RAM must be complete in 6 CAN-CLK 282 * register and message RAM must be complete in 6 CAN-CLK
279 * period. 283 * period.
280 */ 284 */
281 priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask, 285 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
282 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 286 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
283 priv->write_reg(priv, &priv->regs->ifregs[iface].com_req, 287 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
284 IFX_WRITE_LOW_16BIT(objno)); 288 IFX_WRITE_LOW_16BIT(objno));
285 289
286 if (c_can_msg_obj_is_busy(priv, iface)) 290 if (c_can_msg_obj_is_busy(priv, iface))
@@ -306,18 +310,18 @@ static void c_can_write_msg_object(struct net_device *dev,
306 310
307 flags |= IF_ARB_MSGVAL; 311 flags |= IF_ARB_MSGVAL;
308 312
309 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, 313 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
310 IFX_WRITE_LOW_16BIT(id)); 314 IFX_WRITE_LOW_16BIT(id));
311 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, flags | 315 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags |
312 IFX_WRITE_HIGH_16BIT(id)); 316 IFX_WRITE_HIGH_16BIT(id));
313 317
314 for (i = 0; i < frame->can_dlc; i += 2) { 318 for (i = 0; i < frame->can_dlc; i += 2) {
315 priv->write_reg(priv, &priv->regs->ifregs[iface].data[i / 2], 319 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
316 frame->data[i] | (frame->data[i + 1] << 8)); 320 frame->data[i] | (frame->data[i + 1] << 8));
317 } 321 }
318 322
319 /* enable interrupt for this message object */ 323 /* enable interrupt for this message object */
320 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 324 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
321 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 325 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
322 frame->can_dlc); 326 frame->can_dlc);
323 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 327 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
@@ -329,7 +333,7 @@ static inline void c_can_mark_rx_msg_obj(struct net_device *dev,
329{ 333{
330 struct c_can_priv *priv = netdev_priv(dev); 334 struct c_can_priv *priv = netdev_priv(dev);
331 335
332 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 336 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
333 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); 337 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND));
334 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 338 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
335 339
@@ -343,7 +347,7 @@ static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
343 struct c_can_priv *priv = netdev_priv(dev); 347 struct c_can_priv *priv = netdev_priv(dev);
344 348
345 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 349 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) {
346 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 350 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
347 ctrl_mask & ~(IF_MCONT_MSGLST | 351 ctrl_mask & ~(IF_MCONT_MSGLST |
348 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 352 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
349 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 353 c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
@@ -356,7 +360,7 @@ static inline void c_can_activate_rx_msg_obj(struct net_device *dev,
356{ 360{
357 struct c_can_priv *priv = netdev_priv(dev); 361 struct c_can_priv *priv = netdev_priv(dev);
358 362
359 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 363 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
360 ctrl_mask & ~(IF_MCONT_MSGLST | 364 ctrl_mask & ~(IF_MCONT_MSGLST |
361 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 365 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
362 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 366 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
@@ -374,7 +378,7 @@ static void c_can_handle_lost_msg_obj(struct net_device *dev,
374 378
375 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 379 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
376 380
377 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 381 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
378 IF_MCONT_CLR_MSGLST); 382 IF_MCONT_CLR_MSGLST);
379 383
380 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL); 384 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL);
@@ -410,8 +414,8 @@ static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
410 414
411 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 415 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
412 416
413 flags = priv->read_reg(priv, &priv->regs->ifregs[iface].arb2); 417 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface));
414 val = priv->read_reg(priv, &priv->regs->ifregs[iface].arb1) | 418 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) |
415 (flags << 16); 419 (flags << 16);
416 420
417 if (flags & IF_ARB_MSGXTD) 421 if (flags & IF_ARB_MSGXTD)
@@ -424,7 +428,7 @@ static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
424 else { 428 else {
425 for (i = 0; i < frame->can_dlc; i += 2) { 429 for (i = 0; i < frame->can_dlc; i += 2) {
426 data = priv->read_reg(priv, 430 data = priv->read_reg(priv,
427 &priv->regs->ifregs[iface].data[i / 2]); 431 C_CAN_IFACE(DATA1_REG, iface) + i / 2);
428 frame->data[i] = data; 432 frame->data[i] = data;
429 frame->data[i + 1] = data >> 8; 433 frame->data[i + 1] = data >> 8;
430 } 434 }
@@ -444,40 +448,40 @@ static void c_can_setup_receive_object(struct net_device *dev, int iface,
444{ 448{
445 struct c_can_priv *priv = netdev_priv(dev); 449 struct c_can_priv *priv = netdev_priv(dev);
446 450
447 priv->write_reg(priv, &priv->regs->ifregs[iface].mask1, 451 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface),
448 IFX_WRITE_LOW_16BIT(mask)); 452 IFX_WRITE_LOW_16BIT(mask));
449 priv->write_reg(priv, &priv->regs->ifregs[iface].mask2, 453 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface),
450 IFX_WRITE_HIGH_16BIT(mask)); 454 IFX_WRITE_HIGH_16BIT(mask));
451 455
452 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, 456 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
453 IFX_WRITE_LOW_16BIT(id)); 457 IFX_WRITE_LOW_16BIT(id));
454 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, 458 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface),
455 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 459 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
456 460
457 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, mcont); 461 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
458 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 462 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
459 463
460 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 464 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
461 c_can_read_reg32(priv, &priv->regs->msgval1)); 465 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
462} 466}
463 467
464static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 468static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
465{ 469{
466 struct c_can_priv *priv = netdev_priv(dev); 470 struct c_can_priv *priv = netdev_priv(dev);
467 471
468 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, 0); 472 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
469 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, 0); 473 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
470 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 0); 474 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
471 475
472 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 476 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
473 477
474 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 478 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
475 c_can_read_reg32(priv, &priv->regs->msgval1)); 479 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
476} 480}
477 481
478static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 482static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
479{ 483{
480 int val = c_can_read_reg32(priv, &priv->regs->txrqst1); 484 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
481 485
482 /* 486 /*
483 * as transmission request register's bit n-1 corresponds to 487 * as transmission request register's bit n-1 corresponds to
@@ -540,12 +544,12 @@ static int c_can_set_bittiming(struct net_device *dev)
540 netdev_info(dev, 544 netdev_info(dev,
541 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 545 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
542 546
543 ctrl_save = priv->read_reg(priv, &priv->regs->control); 547 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
544 priv->write_reg(priv, &priv->regs->control, 548 priv->write_reg(priv, C_CAN_CTRL_REG,
545 ctrl_save | CONTROL_CCE | CONTROL_INIT); 549 ctrl_save | CONTROL_CCE | CONTROL_INIT);
546 priv->write_reg(priv, &priv->regs->btr, reg_btr); 550 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
547 priv->write_reg(priv, &priv->regs->brp_ext, reg_brpe); 551 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
548 priv->write_reg(priv, &priv->regs->control, ctrl_save); 552 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
549 553
550 return 0; 554 return 0;
551} 555}
@@ -587,36 +591,36 @@ static void c_can_chip_config(struct net_device *dev)
587 struct c_can_priv *priv = netdev_priv(dev); 591 struct c_can_priv *priv = netdev_priv(dev);
588 592
589 /* enable automatic retransmission */ 593 /* enable automatic retransmission */
590 priv->write_reg(priv, &priv->regs->control, 594 priv->write_reg(priv, C_CAN_CTRL_REG,
591 CONTROL_ENABLE_AR); 595 CONTROL_ENABLE_AR);
592 596
593 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY & 597 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY &
594 CAN_CTRLMODE_LOOPBACK)) { 598 CAN_CTRLMODE_LOOPBACK)) {
595 /* loopback + silent mode : useful for hot self-test */ 599 /* loopback + silent mode : useful for hot self-test */
596 priv->write_reg(priv, &priv->regs->control, CONTROL_EIE | 600 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
597 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 601 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
598 priv->write_reg(priv, &priv->regs->test, 602 priv->write_reg(priv, C_CAN_TEST_REG,
599 TEST_LBACK | TEST_SILENT); 603 TEST_LBACK | TEST_SILENT);
600 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 604 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
601 /* loopback mode : useful for self-test function */ 605 /* loopback mode : useful for self-test function */
602 priv->write_reg(priv, &priv->regs->control, CONTROL_EIE | 606 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
603 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 607 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
604 priv->write_reg(priv, &priv->regs->test, TEST_LBACK); 608 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
605 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 609 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
606 /* silent mode : bus-monitoring mode */ 610 /* silent mode : bus-monitoring mode */
607 priv->write_reg(priv, &priv->regs->control, CONTROL_EIE | 611 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
608 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 612 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
609 priv->write_reg(priv, &priv->regs->test, TEST_SILENT); 613 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
610 } else 614 } else
611 /* normal mode*/ 615 /* normal mode*/
612 priv->write_reg(priv, &priv->regs->control, 616 priv->write_reg(priv, C_CAN_CTRL_REG,
613 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 617 CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
614 618
615 /* configure message objects */ 619 /* configure message objects */
616 c_can_configure_msg_objects(dev); 620 c_can_configure_msg_objects(dev);
617 621
618 /* set a `lec` value so that we can check for updates later */ 622 /* set a `lec` value so that we can check for updates later */
619 priv->write_reg(priv, &priv->regs->status, LEC_UNUSED); 623 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
620 624
621 /* set bittiming params */ 625 /* set bittiming params */
622 c_can_set_bittiming(dev); 626 c_can_set_bittiming(dev);
@@ -669,7 +673,7 @@ static int c_can_get_berr_counter(const struct net_device *dev,
669 unsigned int reg_err_counter; 673 unsigned int reg_err_counter;
670 struct c_can_priv *priv = netdev_priv(dev); 674 struct c_can_priv *priv = netdev_priv(dev);
671 675
672 reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt); 676 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
673 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 677 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
674 ERR_CNT_REC_SHIFT; 678 ERR_CNT_REC_SHIFT;
675 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 679 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
@@ -697,12 +701,12 @@ static void c_can_do_tx(struct net_device *dev)
697 701
698 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 702 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
699 msg_obj_no = get_tx_echo_msg_obj(priv); 703 msg_obj_no = get_tx_echo_msg_obj(priv);
700 val = c_can_read_reg32(priv, &priv->regs->txrqst1); 704 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
701 if (!(val & (1 << (msg_obj_no - 1)))) { 705 if (!(val & (1 << (msg_obj_no - 1)))) {
702 can_get_echo_skb(dev, 706 can_get_echo_skb(dev,
703 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 707 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
704 stats->tx_bytes += priv->read_reg(priv, 708 stats->tx_bytes += priv->read_reg(priv,
705 &priv->regs->ifregs[0].msg_cntrl) 709 C_CAN_IFACE(MSGCTRL_REG, 0))
706 & IF_MCONT_DLC_MASK; 710 & IF_MCONT_DLC_MASK;
707 stats->tx_packets++; 711 stats->tx_packets++;
708 c_can_inval_msg_object(dev, 0, msg_obj_no); 712 c_can_inval_msg_object(dev, 0, msg_obj_no);
@@ -744,11 +748,11 @@ static int c_can_do_rx_poll(struct net_device *dev, int quota)
744 u32 num_rx_pkts = 0; 748 u32 num_rx_pkts = 0;
745 unsigned int msg_obj, msg_ctrl_save; 749 unsigned int msg_obj, msg_ctrl_save;
746 struct c_can_priv *priv = netdev_priv(dev); 750 struct c_can_priv *priv = netdev_priv(dev);
747 u32 val = c_can_read_reg32(priv, &priv->regs->intpnd1); 751 u32 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG);
748 752
749 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST; 753 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST;
750 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0; 754 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0;
751 val = c_can_read_reg32(priv, &priv->regs->intpnd1), 755 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG),
752 msg_obj++) { 756 msg_obj++) {
753 /* 757 /*
754 * as interrupt pending register's bit n-1 corresponds to 758 * as interrupt pending register's bit n-1 corresponds to
@@ -758,7 +762,7 @@ static int c_can_do_rx_poll(struct net_device *dev, int quota)
758 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL & 762 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL &
759 ~IF_COMM_TXRQST); 763 ~IF_COMM_TXRQST);
760 msg_ctrl_save = priv->read_reg(priv, 764 msg_ctrl_save = priv->read_reg(priv,
761 &priv->regs->ifregs[0].msg_cntrl); 765 C_CAN_IFACE(MSGCTRL_REG, 0));
762 766
763 if (msg_ctrl_save & IF_MCONT_EOB) 767 if (msg_ctrl_save & IF_MCONT_EOB)
764 return num_rx_pkts; 768 return num_rx_pkts;
@@ -819,7 +823,7 @@ static int c_can_handle_state_change(struct net_device *dev,
819 return 0; 823 return 0;
820 824
821 c_can_get_berr_counter(dev, &bec); 825 c_can_get_berr_counter(dev, &bec);
822 reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt); 826 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
823 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 827 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
824 ERR_CNT_RP_SHIFT; 828 ERR_CNT_RP_SHIFT;
825 829
@@ -935,7 +939,7 @@ static int c_can_handle_bus_err(struct net_device *dev,
935 } 939 }
936 940
937 /* set a `lec` value so that we can check for updates later */ 941 /* set a `lec` value so that we can check for updates later */
938 priv->write_reg(priv, &priv->regs->status, LEC_UNUSED); 942 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
939 943
940 netif_receive_skb(skb); 944 netif_receive_skb(skb);
941 stats->rx_packets++; 945 stats->rx_packets++;
@@ -959,15 +963,15 @@ static int c_can_poll(struct napi_struct *napi, int quota)
959 /* status events have the highest priority */ 963 /* status events have the highest priority */
960 if (irqstatus == STATUS_INTERRUPT) { 964 if (irqstatus == STATUS_INTERRUPT) {
961 priv->current_status = priv->read_reg(priv, 965 priv->current_status = priv->read_reg(priv,
962 &priv->regs->status); 966 C_CAN_STS_REG);
963 967
964 /* handle Tx/Rx events */ 968 /* handle Tx/Rx events */
965 if (priv->current_status & STATUS_TXOK) 969 if (priv->current_status & STATUS_TXOK)
966 priv->write_reg(priv, &priv->regs->status, 970 priv->write_reg(priv, C_CAN_STS_REG,
967 priv->current_status & ~STATUS_TXOK); 971 priv->current_status & ~STATUS_TXOK);
968 972
969 if (priv->current_status & STATUS_RXOK) 973 if (priv->current_status & STATUS_RXOK)
970 priv->write_reg(priv, &priv->regs->status, 974 priv->write_reg(priv, C_CAN_STS_REG,
971 priv->current_status & ~STATUS_RXOK); 975 priv->current_status & ~STATUS_RXOK);
972 976
973 /* handle state changes */ 977 /* handle state changes */
@@ -1033,7 +1037,7 @@ static irqreturn_t c_can_isr(int irq, void *dev_id)
1033 struct net_device *dev = (struct net_device *)dev_id; 1037 struct net_device *dev = (struct net_device *)dev_id;
1034 struct c_can_priv *priv = netdev_priv(dev); 1038 struct c_can_priv *priv = netdev_priv(dev);
1035 1039
1036 priv->irqstatus = priv->read_reg(priv, &priv->regs->interrupt); 1040 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG);
1037 if (!priv->irqstatus) 1041 if (!priv->irqstatus)
1038 return IRQ_NONE; 1042 return IRQ_NONE;
1039 1043
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index 5f32d34af50..d1e141e3b99 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -22,43 +22,84 @@
22#ifndef C_CAN_H 22#ifndef C_CAN_H
23#define C_CAN_H 23#define C_CAN_H
24 24
25/* c_can IF registers */ 25enum reg {
26struct c_can_if_regs { 26 C_CAN_CTRL_REG = 0,
27 u16 com_req; 27 C_CAN_STS_REG,
28 u16 com_mask; 28 C_CAN_ERR_CNT_REG,
29 u16 mask1; 29 C_CAN_BTR_REG,
30 u16 mask2; 30 C_CAN_INT_REG,
31 u16 arb1; 31 C_CAN_TEST_REG,
32 u16 arb2; 32 C_CAN_BRPEXT_REG,
33 u16 msg_cntrl; 33 C_CAN_IF1_COMREQ_REG,
34 u16 data[4]; 34 C_CAN_IF1_COMMSK_REG,
35 u16 _reserved[13]; 35 C_CAN_IF1_MASK1_REG,
36 C_CAN_IF1_MASK2_REG,
37 C_CAN_IF1_ARB1_REG,
38 C_CAN_IF1_ARB2_REG,
39 C_CAN_IF1_MSGCTRL_REG,
40 C_CAN_IF1_DATA1_REG,
41 C_CAN_IF1_DATA2_REG,
42 C_CAN_IF1_DATA3_REG,
43 C_CAN_IF1_DATA4_REG,
44 C_CAN_IF2_COMREQ_REG,
45 C_CAN_IF2_COMMSK_REG,
46 C_CAN_IF2_MASK1_REG,
47 C_CAN_IF2_MASK2_REG,
48 C_CAN_IF2_ARB1_REG,
49 C_CAN_IF2_ARB2_REG,
50 C_CAN_IF2_MSGCTRL_REG,
51 C_CAN_IF2_DATA1_REG,
52 C_CAN_IF2_DATA2_REG,
53 C_CAN_IF2_DATA3_REG,
54 C_CAN_IF2_DATA4_REG,
55 C_CAN_TXRQST1_REG,
56 C_CAN_TXRQST2_REG,
57 C_CAN_NEWDAT1_REG,
58 C_CAN_NEWDAT2_REG,
59 C_CAN_INTPND1_REG,
60 C_CAN_INTPND2_REG,
61 C_CAN_MSGVAL1_REG,
62 C_CAN_MSGVAL2_REG,
36}; 63};
37 64
38/* c_can hardware registers */ 65static const u16 reg_map_c_can[] = {
39struct c_can_regs { 66 [C_CAN_CTRL_REG] = 0x00,
40 u16 control; 67 [C_CAN_STS_REG] = 0x02,
41 u16 status; 68 [C_CAN_ERR_CNT_REG] = 0x04,
42 u16 err_cnt; 69 [C_CAN_BTR_REG] = 0x06,
43 u16 btr; 70 [C_CAN_INT_REG] = 0x08,
44 u16 interrupt; 71 [C_CAN_TEST_REG] = 0x0A,
45 u16 test; 72 [C_CAN_BRPEXT_REG] = 0x0C,
46 u16 brp_ext; 73 [C_CAN_IF1_COMREQ_REG] = 0x10,
47 u16 _reserved1; 74 [C_CAN_IF1_COMMSK_REG] = 0x12,
48 struct c_can_if_regs ifregs[2]; /* [0] = IF1 and [1] = IF2 */ 75 [C_CAN_IF1_MASK1_REG] = 0x14,
49 u16 _reserved2[8]; 76 [C_CAN_IF1_MASK2_REG] = 0x16,
50 u16 txrqst1; 77 [C_CAN_IF1_ARB1_REG] = 0x18,
51 u16 txrqst2; 78 [C_CAN_IF1_ARB2_REG] = 0x1A,
52 u16 _reserved3[6]; 79 [C_CAN_IF1_MSGCTRL_REG] = 0x1C,
53 u16 newdat1; 80 [C_CAN_IF1_DATA1_REG] = 0x1E,
54 u16 newdat2; 81 [C_CAN_IF1_DATA2_REG] = 0x20,
55 u16 _reserved4[6]; 82 [C_CAN_IF1_DATA3_REG] = 0x22,
56 u16 intpnd1; 83 [C_CAN_IF1_DATA4_REG] = 0x24,
57 u16 intpnd2; 84 [C_CAN_IF2_COMREQ_REG] = 0x40,
58 u16 _reserved5[6]; 85 [C_CAN_IF2_COMMSK_REG] = 0x42,
59 u16 msgval1; 86 [C_CAN_IF2_MASK1_REG] = 0x44,
60 u16 msgval2; 87 [C_CAN_IF2_MASK2_REG] = 0x46,
61 u16 _reserved6[6]; 88 [C_CAN_IF2_ARB1_REG] = 0x48,
89 [C_CAN_IF2_ARB2_REG] = 0x4A,
90 [C_CAN_IF2_MSGCTRL_REG] = 0x4C,
91 [C_CAN_IF2_DATA1_REG] = 0x4E,
92 [C_CAN_IF2_DATA2_REG] = 0x50,
93 [C_CAN_IF2_DATA3_REG] = 0x52,
94 [C_CAN_IF2_DATA4_REG] = 0x54,
95 [C_CAN_TXRQST1_REG] = 0x80,
96 [C_CAN_TXRQST2_REG] = 0x82,
97 [C_CAN_NEWDAT1_REG] = 0x90,
98 [C_CAN_NEWDAT2_REG] = 0x92,
99 [C_CAN_INTPND1_REG] = 0xA0,
100 [C_CAN_INTPND2_REG] = 0xA2,
101 [C_CAN_MSGVAL1_REG] = 0xB0,
102 [C_CAN_MSGVAL2_REG] = 0xB2,
62}; 103};
63 104
64/* c_can private data structure */ 105/* c_can private data structure */
@@ -69,9 +110,10 @@ struct c_can_priv {
69 int tx_object; 110 int tx_object;
70 int current_status; 111 int current_status;
71 int last_status; 112 int last_status;
72 u16 (*read_reg) (struct c_can_priv *priv, void *reg); 113 u16 (*read_reg) (struct c_can_priv *priv, enum reg index);
73 void (*write_reg) (struct c_can_priv *priv, void *reg, u16 val); 114 void (*write_reg) (struct c_can_priv *priv, enum reg index, u16 val);
74 struct c_can_regs __iomem *regs; 115 void __iomem *base;
116 const u16 *regs;
75 unsigned long irq_flags; /* for request_irq() */ 117 unsigned long irq_flags; /* for request_irq() */
76 unsigned int tx_next; 118 unsigned int tx_next;
77 unsigned int tx_echo; 119 unsigned int tx_echo;
diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
index 5e1a5ff6476..a6e9b937683 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -42,27 +42,27 @@
42 * Handle the same by providing a common read/write interface. 42 * Handle the same by providing a common read/write interface.
43 */ 43 */
44static u16 c_can_plat_read_reg_aligned_to_16bit(struct c_can_priv *priv, 44static u16 c_can_plat_read_reg_aligned_to_16bit(struct c_can_priv *priv,
45 void *reg) 45 enum reg index)
46{ 46{
47 return readw(reg); 47 return readw(priv->base + priv->regs[index]);
48} 48}
49 49
50static void c_can_plat_write_reg_aligned_to_16bit(struct c_can_priv *priv, 50static void c_can_plat_write_reg_aligned_to_16bit(struct c_can_priv *priv,
51 void *reg, u16 val) 51 enum reg index, u16 val)
52{ 52{
53 writew(val, reg); 53 writew(val, priv->base + priv->regs[index]);
54} 54}
55 55
56static u16 c_can_plat_read_reg_aligned_to_32bit(struct c_can_priv *priv, 56static u16 c_can_plat_read_reg_aligned_to_32bit(struct c_can_priv *priv,
57 void *reg) 57 enum reg index)
58{ 58{
59 return readw(reg + (long)reg - (long)priv->regs); 59 return readw(priv->base + 2 * priv->regs[index]);
60} 60}
61 61
62static void c_can_plat_write_reg_aligned_to_32bit(struct c_can_priv *priv, 62static void c_can_plat_write_reg_aligned_to_32bit(struct c_can_priv *priv,
63 void *reg, u16 val) 63 enum reg index, u16 val)
64{ 64{
65 writew(val, reg + (long)reg - (long)priv->regs); 65 writew(val, priv->base + 2 * priv->regs[index]);
66} 66}
67 67
68static int __devinit c_can_plat_probe(struct platform_device *pdev) 68static int __devinit c_can_plat_probe(struct platform_device *pdev)
@@ -115,9 +115,10 @@ static int __devinit c_can_plat_probe(struct platform_device *pdev)
115 } 115 }
116 116
117 priv = netdev_priv(dev); 117 priv = netdev_priv(dev);
118 priv->regs = reg_map_c_can;
118 119
119 dev->irq = irq; 120 dev->irq = irq;
120 priv->regs = addr; 121 priv->base = addr;
121#ifdef CONFIG_HAVE_CLK 122#ifdef CONFIG_HAVE_CLK
122 priv->can.clock.freq = clk_get_rate(clk); 123 priv->can.clock.freq = clk_get_rate(clk);
123 priv->priv = clk; 124 priv->priv = clk;
@@ -146,7 +147,7 @@ static int __devinit c_can_plat_probe(struct platform_device *pdev)
146 } 147 }
147 148
148 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n", 149 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
149 KBUILD_MODNAME, priv->regs, dev->irq); 150 KBUILD_MODNAME, priv->base, dev->irq);
150 return 0; 151 return 0;
151 152
152exit_free_device: 153exit_free_device:
@@ -176,7 +177,7 @@ static int __devexit c_can_plat_remove(struct platform_device *pdev)
176 platform_set_drvdata(pdev, NULL); 177 platform_set_drvdata(pdev, NULL);
177 178
178 free_c_can_dev(dev); 179 free_c_can_dev(dev);
179 iounmap(priv->regs); 180 iounmap(priv->base);
180 181
181 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 182 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
182 release_mem_region(mem->start, resource_size(mem)); 183 release_mem_region(mem->start, resource_size(mem));