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authorAlan Cox <alan@linux.intel.com>2011-07-05 10:37:29 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-07-05 11:20:39 -0400
commit2f8a78fbffae3b89eba7a1d6807184a845a5b3b0 (patch)
tree9bd019dc7b69839de55fac69c5af9cade9533b3a /drivers
parenteee9b52e5e9024abd7fc9e5a71230218cbc9db93 (diff)
gma500: Extract BIOSisy stuff from psb_drv
This is too big already so lets rip out more of the device specific crud. It also means we pull the ugly stuff that needs work out of our main line of cleanup. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/gma500/Makefile1
-rw-r--r--drivers/staging/gma500/mrst_bios.c236
-rw-r--r--drivers/staging/gma500/mrst_bios.h22
-rw-r--r--drivers/staging/gma500/psb_drv.c209
4 files changed, 260 insertions, 208 deletions
diff --git a/drivers/staging/gma500/Makefile b/drivers/staging/gma500/Makefile
index 4c9c475958a..fdaac639deb 100644
--- a/drivers/staging/gma500/Makefile
+++ b/drivers/staging/gma500/Makefile
@@ -23,6 +23,7 @@ psb_gfx-y += gem_glue.o \
23 psb_irq.o \ 23 psb_irq.o \
24 mrst_crtc.o \ 24 mrst_crtc.o \
25 mrst_lvds.o \ 25 mrst_lvds.o \
26 mrst_bios.o \
26 mdfld_output.o \ 27 mdfld_output.o \
27 mdfld_pyr_cmd.o \ 28 mdfld_pyr_cmd.o \
28 mdfld_tmd_vid.o \ 29 mdfld_tmd_vid.o \
diff --git a/drivers/staging/gma500/mrst_bios.c b/drivers/staging/gma500/mrst_bios.c
new file mode 100644
index 00000000000..0d944c47bc9
--- /dev/null
+++ b/drivers/staging/gma500/mrst_bios.c
@@ -0,0 +1,236 @@
1/**************************************************************************
2 * Copyright (c) 2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20/* TODO
21 * - Split functions by vbt type
22 * - Make them all take drm_device
23 * - Check ioremap failures
24 */
25
26#include <drm/drmP.h>
27#include <drm/drm.h>
28#include "psb_drm.h"
29#include "psb_drv.h"
30#include "mrst_bios.h"
31
32void mrst_get_fuse_settings(struct drm_device *dev)
33{
34 struct drm_psb_private *dev_priv = dev->dev_private;
35 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
36 uint32_t fuse_value = 0;
37 uint32_t fuse_value_tmp = 0;
38
39#define FB_REG06 0xD0810600
40#define FB_MIPI_DISABLE (1 << 11)
41#define FB_REG09 0xD0810900
42#define FB_REG09 0xD0810900
43#define FB_SKU_MASK 0x7000
44#define FB_SKU_SHIFT 12
45#define FB_SKU_100 0
46#define FB_SKU_100L 1
47#define FB_SKU_83 2
48 pci_write_config_dword(pci_root, 0xD0, FB_REG06);
49 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
50
51 /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
52 if (IS_MRST(dev))
53 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
54
55 DRM_INFO("internal display is %s\n",
56 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
57
58 /* Prevent runtime suspend at start*/
59 if (dev_priv->iLVDS_enable) {
60 dev_priv->is_lvds_on = true;
61 dev_priv->is_mipi_on = false;
62 } else {
63 dev_priv->is_mipi_on = true;
64 dev_priv->is_lvds_on = false;
65 }
66
67 dev_priv->video_device_fuse = fuse_value;
68
69 pci_write_config_dword(pci_root, 0xD0, FB_REG09);
70 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
71
72 dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
73 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
74
75 dev_priv->fuse_reg_value = fuse_value;
76
77 switch (fuse_value_tmp) {
78 case FB_SKU_100:
79 dev_priv->core_freq = 200;
80 break;
81 case FB_SKU_100L:
82 dev_priv->core_freq = 100;
83 break;
84 case FB_SKU_83:
85 dev_priv->core_freq = 166;
86 break;
87 default:
88 dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
89 fuse_value_tmp);
90 dev_priv->core_freq = 0;
91 }
92 dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
93 pci_dev_put(pci_root);
94}
95
96/*
97 * Get the revison ID, B0:D2:F0;0x08
98 */
99void mid_get_pci_revID(struct drm_psb_private *dev_priv)
100{
101 uint32_t platform_rev_id = 0;
102 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
103
104 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
105 dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
106 pci_dev_put(pci_gfx_root);
107 dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
108 dev_priv->platform_rev_id);
109}
110
111void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
112{
113 struct drm_device *dev = dev_priv->dev;
114 struct mrst_vbt *vbt = &dev_priv->vbt_data;
115 u32 addr;
116 u16 new_size;
117 u8 *vbt_virtual;
118 u8 bpi;
119 u8 number_desc = 0;
120 struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
121 struct gct_r10_timing_info ti;
122 void *pGCT;
123 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
124
125 /* Get the address of the platform config vbt, B0:D2:F0;0xFC */
126 pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
127 pci_dev_put(pci_gfx_root);
128
129 dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
130
131 /* check for platform config address == 0. */
132 /* this means fw doesn't support vbt */
133
134 if (addr == 0) {
135 vbt->size = 0;
136 return;
137 }
138
139 /* get the virtual address of the vbt */
140 vbt_virtual = ioremap(addr, sizeof(*vbt));
141
142 memcpy(vbt, vbt_virtual, sizeof(*vbt));
143 iounmap(vbt_virtual); /* Free virtual address space */
144
145 dev_dbg(dev->dev, "GCT revision is %x\n", vbt->revision);
146
147 switch (vbt->revision) {
148 case 0:
149 vbt->mrst_gct = ioremap(addr + sizeof(*vbt) - 4,
150 vbt->size - sizeof(*vbt) + 4);
151 pGCT = vbt->mrst_gct;
152 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
153 dev_priv->gct_data.bpi = bpi;
154 dev_priv->gct_data.pt =
155 ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
156 memcpy(&dev_priv->gct_data.DTD,
157 &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
158 sizeof(struct mrst_timing_info));
159 dev_priv->gct_data.Panel_Port_Control =
160 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
161 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
162 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
163 break;
164 case 1:
165 vbt->mrst_gct = ioremap(addr + sizeof(*vbt) - 4,
166 vbt->size - sizeof(*vbt) + 4);
167 pGCT = vbt->mrst_gct;
168 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
169 dev_priv->gct_data.bpi = bpi;
170 dev_priv->gct_data.pt =
171 ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
172 memcpy(&dev_priv->gct_data.DTD,
173 &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
174 sizeof(struct mrst_timing_info));
175 dev_priv->gct_data.Panel_Port_Control =
176 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
177 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
178 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
179 break;
180 case 0x10:
181 /*header definition changed from rev 01 (v2) to rev 10h. */
182 /*so, some values have changed location*/
183 new_size = vbt->checksum; /*checksum contains lo size byte*/
184 /*LSB of mrst_gct contains hi size byte*/
185 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
186
187 vbt->checksum = vbt->size; /*size contains the checksum*/
188 if (new_size > 0xff)
189 vbt->size = 0xff; /*restrict size to 255*/
190 else
191 vbt->size = new_size;
192
193 /* number of descriptors defined in the GCT */
194 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
195 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
196 vbt->mrst_gct = ioremap(addr + GCT_R10_HEADER_SIZE,
197 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
198 pGCT = vbt->mrst_gct;
199 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
200 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
201
202 /*copy the GCT display timings into a temp structure*/
203 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
204
205 /*now copy the temp struct into the dev_priv->gct_data*/
206 dp_ti->pixel_clock = ti.pixel_clock;
207 dp_ti->hactive_hi = ti.hactive_hi;
208 dp_ti->hactive_lo = ti.hactive_lo;
209 dp_ti->hblank_hi = ti.hblank_hi;
210 dp_ti->hblank_lo = ti.hblank_lo;
211 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
212 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
213 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
214 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
215 dp_ti->vactive_hi = ti.vactive_hi;
216 dp_ti->vactive_lo = ti.vactive_lo;
217 dp_ti->vblank_hi = ti.vblank_hi;
218 dp_ti->vblank_lo = ti.vblank_lo;
219 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
220 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
221 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
222 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
223
224 /* Move the MIPI_Display_Descriptor data from GCT to dev priv */
225 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
226 *((u8 *)pGCT + 0x0d);
227 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
228 (*((u8 *)pGCT + 0x0e)) << 8;
229 break;
230 default:
231 dev_err(dev->dev, "Unknown revision of GCT!\n");
232 vbt->size = 0;
233 }
234 /* FIXME: Need to sort out Medfield panel identifiers in future */
235}
236
diff --git a/drivers/staging/gma500/mrst_bios.h b/drivers/staging/gma500/mrst_bios.h
new file mode 100644
index 00000000000..a257306d7e7
--- /dev/null
+++ b/drivers/staging/gma500/mrst_bios.h
@@ -0,0 +1,22 @@
1/**************************************************************************
2 * Copyright (c) 2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20extern void mrst_get_fuse_settings(struct drm_device *dev);
21extern void mid_get_pci_revID(struct drm_psb_private *dev_priv);
22extern void mrst_get_vbt_data(struct drm_psb_private *dev_priv);
diff --git a/drivers/staging/gma500/psb_drv.c b/drivers/staging/gma500/psb_drv.c
index 8df9c5889f6..cbdc02c8570 100644
--- a/drivers/staging/gma500/psb_drv.c
+++ b/drivers/staging/gma500/psb_drv.c
@@ -27,6 +27,7 @@
27#include "psb_reg.h" 27#include "psb_reg.h"
28#include "psb_intel_reg.h" 28#include "psb_intel_reg.h"
29#include "psb_intel_bios.h" 29#include "psb_intel_bios.h"
30#include "mrst_bios.h"
30#include <drm/drm_pciids.h> 31#include <drm/drm_pciids.h>
31#include "psb_powermgmt.h" 32#include "psb_powermgmt.h"
32#include <linux/cpu.h> 33#include <linux/cpu.h>
@@ -165,214 +166,6 @@ static void psb_do_takedown(struct drm_device *dev)
165 /* FIXME: do we need to clean up the gtt here ? */ 166 /* FIXME: do we need to clean up the gtt here ? */
166} 167}
167 168
168void mrst_get_fuse_settings(struct drm_device *dev)
169{
170 struct drm_psb_private *dev_priv = dev->dev_private;
171 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
172 uint32_t fuse_value = 0;
173 uint32_t fuse_value_tmp = 0;
174
175#define FB_REG06 0xD0810600
176#define FB_MIPI_DISABLE (1 << 11)
177#define FB_REG09 0xD0810900
178#define FB_REG09 0xD0810900
179#define FB_SKU_MASK 0x7000
180#define FB_SKU_SHIFT 12
181#define FB_SKU_100 0
182#define FB_SKU_100L 1
183#define FB_SKU_83 2
184 pci_write_config_dword(pci_root, 0xD0, FB_REG06);
185 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
186
187 /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
188 if (IS_MRST(dev))
189 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
190
191 DRM_INFO("internal display is %s\n",
192 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
193
194 /*prevent Runtime suspend at start*/
195 if (dev_priv->iLVDS_enable) {
196 dev_priv->is_lvds_on = true;
197 dev_priv->is_mipi_on = false;
198 } else {
199 dev_priv->is_mipi_on = true;
200 dev_priv->is_lvds_on = false;
201 }
202
203 dev_priv->video_device_fuse = fuse_value;
204
205 pci_write_config_dword(pci_root, 0xD0, FB_REG09);
206 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
207
208 DRM_INFO("SKU values is 0x%x.\n", fuse_value);
209 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
210
211 dev_priv->fuse_reg_value = fuse_value;
212
213 switch (fuse_value_tmp) {
214 case FB_SKU_100:
215 dev_priv->core_freq = 200;
216 break;
217 case FB_SKU_100L:
218 dev_priv->core_freq = 100;
219 break;
220 case FB_SKU_83:
221 dev_priv->core_freq = 166;
222 break;
223 default:
224 dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
225 fuse_value_tmp);
226 dev_priv->core_freq = 0;
227 }
228 DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
229 pci_dev_put(pci_root);
230}
231
232void mid_get_pci_revID(struct drm_psb_private *dev_priv)
233{
234 uint32_t platform_rev_id = 0;
235 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
236
237 /*get the revison ID, B0:D2:F0;0x08 */
238 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
239 dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
240 pci_dev_put(pci_gfx_root);
241 dev_info(dev_priv->dev->dev, "platform_rev_id is %x\n",
242 dev_priv->platform_rev_id);
243}
244
245void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
246{
247 struct mrst_vbt *vbt = &dev_priv->vbt_data;
248 u32 platform_config_address;
249 u16 new_size;
250 u8 *vbt_virtual;
251 u8 bpi;
252 u8 number_desc = 0;
253 struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
254 struct gct_r10_timing_info ti;
255 void *pGCT;
256 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
257
258 /*get the address of the platform config vbt, B0:D2:F0;0xFC */
259 pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
260 pci_dev_put(pci_gfx_root);
261 DRM_INFO("drm platform config address is %x\n",
262 platform_config_address);
263
264 /* check for platform config address == 0. */
265 /* this means fw doesn't support vbt */
266
267 if (platform_config_address == 0) {
268 vbt->size = 0;
269 return;
270 }
271
272 /* get the virtual address of the vbt */
273 vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
274
275 memcpy(vbt, vbt_virtual, sizeof(*vbt));
276 iounmap(vbt_virtual); /* Free virtual address space */
277
278 printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
279
280 switch (vbt->revision) {
281 case 0:
282 vbt->mrst_gct = NULL;
283 vbt->mrst_gct = \
284 ioremap(platform_config_address + sizeof(*vbt) - 4,
285 vbt->size - sizeof(*vbt) + 4);
286 pGCT = vbt->mrst_gct;
287 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
288 dev_priv->gct_data.bpi = bpi;
289 dev_priv->gct_data.pt =
290 ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
291 memcpy(&dev_priv->gct_data.DTD,
292 &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
293 sizeof(struct mrst_timing_info));
294 dev_priv->gct_data.Panel_Port_Control =
295 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
296 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
297 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
298 break;
299 case 1:
300 vbt->mrst_gct = NULL;
301 vbt->mrst_gct = \
302 ioremap(platform_config_address + sizeof(*vbt) - 4,
303 vbt->size - sizeof(*vbt) + 4);
304 pGCT = vbt->mrst_gct;
305 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
306 dev_priv->gct_data.bpi = bpi;
307 dev_priv->gct_data.pt =
308 ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
309 memcpy(&dev_priv->gct_data.DTD,
310 &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
311 sizeof(struct mrst_timing_info));
312 dev_priv->gct_data.Panel_Port_Control =
313 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
314 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
315 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
316 break;
317 case 0x10:
318 /*header definition changed from rev 01 (v2) to rev 10h. */
319 /*so, some values have changed location*/
320 new_size = vbt->checksum; /*checksum contains lo size byte*/
321 /*LSB of mrst_gct contains hi size byte*/
322 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
323
324 vbt->checksum = vbt->size; /*size contains the checksum*/
325 if (new_size > 0xff)
326 vbt->size = 0xff; /*restrict size to 255*/
327 else
328 vbt->size = new_size;
329
330 /* number of descriptors defined in the GCT */
331 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
332 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
333 vbt->mrst_gct = NULL;
334 vbt->mrst_gct = \
335 ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
336 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
337 pGCT = vbt->mrst_gct;
338 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
339 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
340
341 /*copy the GCT display timings into a temp structure*/
342 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
343
344 /*now copy the temp struct into the dev_priv->gct_data*/
345 dp_ti->pixel_clock = ti.pixel_clock;
346 dp_ti->hactive_hi = ti.hactive_hi;
347 dp_ti->hactive_lo = ti.hactive_lo;
348 dp_ti->hblank_hi = ti.hblank_hi;
349 dp_ti->hblank_lo = ti.hblank_lo;
350 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
351 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
352 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
353 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
354 dp_ti->vactive_hi = ti.vactive_hi;
355 dp_ti->vactive_lo = ti.vactive_lo;
356 dp_ti->vblank_hi = ti.vblank_hi;
357 dp_ti->vblank_lo = ti.vblank_lo;
358 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
359 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
360 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
361 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
362
363 /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
364 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
365 *((u8 *)pGCT + 0x0d);
366 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
367 (*((u8 *)pGCT + 0x0e)) << 8;
368 break;
369 default:
370 printk(KERN_ERR "Unknown revision of GCT!\n");
371 vbt->size = 0;
372 }
373 /* FIXME: Need to sort out Medfield panel identifiers in future */
374}
375
376static void psb_get_core_freq(struct drm_device *dev) 169static void psb_get_core_freq(struct drm_device *dev)
377{ 170{
378 uint32_t clock; 171 uint32_t clock;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 11:59:13 -0500