diff options
author | David Fries <david@fries.net> | 2008-10-16 01:05:01 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-16 14:21:50 -0400 |
commit | 8e3dae2b4727dc216e2dc16d2f0271b5f31b680c (patch) | |
tree | 9f6889372940cbccb57631ac487ad5c94aa5b430 /drivers/w1 | |
parent | 7dc8f527ef20bf95143dfbe2ecc01dc70b1e6ab7 (diff) |
W1: w1_io.c reset comments and msleep
w1_reset_bus, added some comments about the timing and switched to msleep
for the later delay. I don't have the hardware to test the sleep after
reset change. The one wire doesn't have a timing requirement between
commands so it is fine. I do have the USB hardware and it would be in big
trouble with 10ms interrupt transfers to find that the reset completed.
Signed-off-by: David Fries <david@fries.net>
Signed-off-by: Evgeniy Polyakov <johnpol@2ka.mipt.ru>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/w1')
-rw-r--r-- | drivers/w1/w1_io.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/w1/w1_io.c b/drivers/w1/w1_io.c index 97b338a16ab..f4f82f1f486 100644 --- a/drivers/w1/w1_io.c +++ b/drivers/w1/w1_io.c | |||
@@ -293,12 +293,24 @@ int w1_reset_bus(struct w1_master *dev) | |||
293 | result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1; | 293 | result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1; |
294 | else { | 294 | else { |
295 | dev->bus_master->write_bit(dev->bus_master->data, 0); | 295 | dev->bus_master->write_bit(dev->bus_master->data, 0); |
296 | /* minimum 480, max ? us | ||
297 | * be nice and sleep, except 18b20 spec lists 960us maximum, | ||
298 | * so until we can sleep with microsecond accuracy, spin. | ||
299 | * Feel free to come up with some other way to give up the | ||
300 | * cpu for such a short amount of time AND get it back in | ||
301 | * the maximum amount of time. | ||
302 | */ | ||
296 | w1_delay(480); | 303 | w1_delay(480); |
297 | dev->bus_master->write_bit(dev->bus_master->data, 1); | 304 | dev->bus_master->write_bit(dev->bus_master->data, 1); |
298 | w1_delay(70); | 305 | w1_delay(70); |
299 | 306 | ||
300 | result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1; | 307 | result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1; |
301 | w1_delay(410); | 308 | /* minmum 70 (above) + 410 = 480 us |
309 | * There aren't any timing requirements between a reset and | ||
310 | * the following transactions. Sleeping is safe here. | ||
311 | */ | ||
312 | /* w1_delay(410); min required time */ | ||
313 | msleep(1); | ||
302 | } | 314 | } |
303 | 315 | ||
304 | return result; | 316 | return result; |