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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /drivers/vme
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'drivers/vme')
-rw-r--r--drivers/vme/Kconfig19
-rw-r--r--drivers/vme/Makefile7
-rw-r--r--drivers/vme/boards/Kconfig9
-rw-r--r--drivers/vme/boards/Makefile5
-rw-r--r--drivers/vme/boards/vme_vmivme7805.c110
-rw-r--r--drivers/vme/boards/vme_vmivme7805.h37
-rw-r--r--drivers/vme/bridges/Kconfig15
-rw-r--r--drivers/vme/bridges/Makefile2
-rw-r--r--drivers/vme/bridges/vme_ca91cx42.c1946
-rw-r--r--drivers/vme/bridges/vme_ca91cx42.h583
-rw-r--r--drivers/vme/bridges/vme_tsi148.c2759
-rw-r--r--drivers/vme/bridges/vme_tsi148.h1410
-rw-r--r--drivers/vme/vme.c1517
-rw-r--r--drivers/vme/vme_bridge.h174
14 files changed, 0 insertions, 8593 deletions
diff --git a/drivers/vme/Kconfig b/drivers/vme/Kconfig
deleted file mode 100644
index c5c22465a80..00000000000
--- a/drivers/vme/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
1#
2# VME configuration.
3#
4
5menuconfig VME_BUS
6 tristate "VME bridge support"
7 depends on PCI
8 ---help---
9 If you say Y here you get support for the VME bridge Framework.
10
11if VME_BUS
12
13source "drivers/vme/bridges/Kconfig"
14
15source "drivers/vme/boards/Kconfig"
16
17source "drivers/staging/vme/devices/Kconfig"
18
19endif # VME
diff --git a/drivers/vme/Makefile b/drivers/vme/Makefile
deleted file mode 100644
index d7bfcb9fd5a..00000000000
--- a/drivers/vme/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for the VME bridge device drivers.
3#
4obj-$(CONFIG_VME_BUS) += vme.o
5
6obj-y += bridges/
7obj-y += boards/
diff --git a/drivers/vme/boards/Kconfig b/drivers/vme/boards/Kconfig
deleted file mode 100644
index 76163135352..00000000000
--- a/drivers/vme/boards/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
1comment "VME Board Drivers"
2
3config VMIVME_7805
4 tristate "VMIVME-7805"
5 help
6 If you say Y here you get support for the VMIVME-7805 board.
7 This board has an additional control interface to the Universe II
8 chip. This driver has to be included if you want to access VME bus
9 with VMIVME-7805 board.
diff --git a/drivers/vme/boards/Makefile b/drivers/vme/boards/Makefile
deleted file mode 100644
index 43658340885..00000000000
--- a/drivers/vme/boards/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the VME board drivers.
3#
4
5obj-$(CONFIG_VMIVME_7805) += vme_vmivme7805.o
diff --git a/drivers/vme/boards/vme_vmivme7805.c b/drivers/vme/boards/vme_vmivme7805.c
deleted file mode 100644
index dd22b5072e2..00000000000
--- a/drivers/vme/boards/vme_vmivme7805.c
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * Support for the VMIVME-7805 board access to the Universe II bridge.
3 *
4 * Author: Arthur Benilov <arthur.benilov@iba-group.com>
5 * Copyright 2010 Ion Beam Application, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/errno.h>
16#include <linux/pci.h>
17#include <linux/poll.h>
18#include <linux/io.h>
19
20#include "vme_vmivme7805.h"
21
22static int vmic_probe(struct pci_dev *, const struct pci_device_id *);
23static void vmic_remove(struct pci_dev *);
24
25/** Base address to access FPGA register */
26static void *vmic_base;
27
28static const char driver_name[] = "vmivme_7805";
29
30static DEFINE_PCI_DEVICE_TABLE(vmic_ids) = {
31 { PCI_DEVICE(PCI_VENDOR_ID_VMIC, PCI_DEVICE_ID_VTIMR) },
32 { },
33};
34
35static struct pci_driver vmic_driver = {
36 .name = driver_name,
37 .id_table = vmic_ids,
38 .probe = vmic_probe,
39 .remove = vmic_remove,
40};
41
42static int vmic_probe(struct pci_dev *pdev, const struct pci_device_id *id)
43{
44 int retval;
45 u32 data;
46
47 /* Enable the device */
48 retval = pci_enable_device(pdev);
49 if (retval) {
50 dev_err(&pdev->dev, "Unable to enable device\n");
51 goto err;
52 }
53
54 /* Map Registers */
55 retval = pci_request_regions(pdev, driver_name);
56 if (retval) {
57 dev_err(&pdev->dev, "Unable to reserve resources\n");
58 goto err_resource;
59 }
60
61 /* Map registers in BAR 0 */
62 vmic_base = ioremap_nocache(pci_resource_start(pdev, 0), 16);
63 if (!vmic_base) {
64 dev_err(&pdev->dev, "Unable to remap CRG region\n");
65 retval = -EIO;
66 goto err_remap;
67 }
68
69 /* Clear the FPGA VME IF contents */
70 iowrite32(0, vmic_base + VME_CONTROL);
71
72 /* Clear any initial BERR */
73 data = ioread32(vmic_base + VME_CONTROL) & 0x00000FFF;
74 data |= BM_VME_CONTROL_BERRST;
75 iowrite32(data, vmic_base + VME_CONTROL);
76
77 /* Enable the vme interface and byte swapping */
78 data = ioread32(vmic_base + VME_CONTROL) & 0x00000FFF;
79 data = data | BM_VME_CONTROL_MASTER_ENDIAN |
80 BM_VME_CONTROL_SLAVE_ENDIAN |
81 BM_VME_CONTROL_ABLE |
82 BM_VME_CONTROL_BERRI |
83 BM_VME_CONTROL_BPENA |
84 BM_VME_CONTROL_VBENA;
85 iowrite32(data, vmic_base + VME_CONTROL);
86
87 return 0;
88
89err_remap:
90 pci_release_regions(pdev);
91err_resource:
92 pci_disable_device(pdev);
93err:
94 return retval;
95}
96
97static void vmic_remove(struct pci_dev *pdev)
98{
99 iounmap(vmic_base);
100 pci_release_regions(pdev);
101 pci_disable_device(pdev);
102
103}
104
105module_pci_driver(vmic_driver);
106
107MODULE_DESCRIPTION("VMIVME-7805 board support driver");
108MODULE_AUTHOR("Arthur Benilov <arthur.benilov@iba-group.com>");
109MODULE_LICENSE("GPL");
110
diff --git a/drivers/vme/boards/vme_vmivme7805.h b/drivers/vme/boards/vme_vmivme7805.h
deleted file mode 100644
index 44c2c449808..00000000000
--- a/drivers/vme/boards/vme_vmivme7805.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * vmivme_7805.h
3 *
4 * Support for the VMIVME-7805 board access to the Universe II bridge.
5 *
6 * Author: Arthur Benilov <arthur.benilov@iba-group.com>
7 * Copyright 2010 Ion Beam Application, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15
16#ifndef _VMIVME_7805_H
17#define _VMIVME_7805_H
18
19#ifndef PCI_VENDOR_ID_VMIC
20#define PCI_VENDOR_ID_VMIC 0x114A
21#endif
22
23#ifndef PCI_DEVICE_ID_VTIMR
24#define PCI_DEVICE_ID_VTIMR 0x0004
25#endif
26
27#define VME_CONTROL 0x0000
28#define BM_VME_CONTROL_MASTER_ENDIAN 0x0001
29#define BM_VME_CONTROL_SLAVE_ENDIAN 0x0002
30#define BM_VME_CONTROL_ABLE 0x0004
31#define BM_VME_CONTROL_BERRI 0x0040
32#define BM_VME_CONTROL_BERRST 0x0080
33#define BM_VME_CONTROL_BPENA 0x0400
34#define BM_VME_CONTROL_VBENA 0x0800
35
36#endif /* _VMIVME_7805_H */
37
diff --git a/drivers/vme/bridges/Kconfig b/drivers/vme/bridges/Kconfig
deleted file mode 100644
index 9331064e047..00000000000
--- a/drivers/vme/bridges/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
1comment "VME Bridge Drivers"
2
3config VME_CA91CX42
4 tristate "Universe II"
5 depends on VIRT_TO_BUS
6 help
7 If you say Y here you get support for the Tundra CA91C142
8 (Universe II) VME bridge chip.
9
10config VME_TSI148
11 tristate "Tempe"
12 depends on VIRT_TO_BUS
13 help
14 If you say Y here you get support for the Tundra TSI148 VME bridge
15 chip.
diff --git a/drivers/vme/bridges/Makefile b/drivers/vme/bridges/Makefile
deleted file mode 100644
index 59638afcd50..00000000000
--- a/drivers/vme/bridges/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-$(CONFIG_VME_CA91CX42) += vme_ca91cx42.o
2obj-$(CONFIG_VME_TSI148) += vme_tsi148.o
diff --git a/drivers/vme/bridges/vme_ca91cx42.c b/drivers/vme/bridges/vme_ca91cx42.c
deleted file mode 100644
index 64bfea31442..00000000000
--- a/drivers/vme/bridges/vme_ca91cx42.c
+++ /dev/null
@@ -1,1946 +0,0 @@
1/*
2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
3 *
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * Derived from ca91c042.c by Michael Wyrick
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/module.h>
19#include <linux/mm.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/pci.h>
23#include <linux/dma-mapping.h>
24#include <linux/poll.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/time.h>
30#include <linux/io.h>
31#include <linux/uaccess.h>
32#include <linux/vme.h>
33
34#include "../vme_bridge.h"
35#include "vme_ca91cx42.h"
36
37static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
38static void ca91cx42_remove(struct pci_dev *);
39
40/* Module parameters */
41static int geoid;
42
43static const char driver_name[] = "vme_ca91cx42";
44
45static DEFINE_PCI_DEVICE_TABLE(ca91cx42_ids) = {
46 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
47 { },
48};
49
50static struct pci_driver ca91cx42_driver = {
51 .name = driver_name,
52 .id_table = ca91cx42_ids,
53 .probe = ca91cx42_probe,
54 .remove = ca91cx42_remove,
55};
56
57static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
58{
59 wake_up(&bridge->dma_queue);
60
61 return CA91CX42_LINT_DMA;
62}
63
64static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
65{
66 int i;
67 u32 serviced = 0;
68
69 for (i = 0; i < 4; i++) {
70 if (stat & CA91CX42_LINT_LM[i]) {
71 /* We only enable interrupts if the callback is set */
72 bridge->lm_callback[i](i);
73 serviced |= CA91CX42_LINT_LM[i];
74 }
75 }
76
77 return serviced;
78}
79
80/* XXX This needs to be split into 4 queues */
81static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
82{
83 wake_up(&bridge->mbox_queue);
84
85 return CA91CX42_LINT_MBOX;
86}
87
88static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
89{
90 wake_up(&bridge->iack_queue);
91
92 return CA91CX42_LINT_SW_IACK;
93}
94
95static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
96{
97 int val;
98 struct ca91cx42_driver *bridge;
99
100 bridge = ca91cx42_bridge->driver_priv;
101
102 val = ioread32(bridge->base + DGCS);
103
104 if (!(val & 0x00000800)) {
105 dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA "
106 "Read Error DGCS=%08X\n", val);
107 }
108
109 return CA91CX42_LINT_VERR;
110}
111
112static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
113{
114 int val;
115 struct ca91cx42_driver *bridge;
116
117 bridge = ca91cx42_bridge->driver_priv;
118
119 val = ioread32(bridge->base + DGCS);
120
121 if (!(val & 0x00000800))
122 dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA "
123 "Read Error DGCS=%08X\n", val);
124
125 return CA91CX42_LINT_LERR;
126}
127
128
129static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
130 int stat)
131{
132 int vec, i, serviced = 0;
133 struct ca91cx42_driver *bridge;
134
135 bridge = ca91cx42_bridge->driver_priv;
136
137
138 for (i = 7; i > 0; i--) {
139 if (stat & (1 << i)) {
140 vec = ioread32(bridge->base +
141 CA91CX42_V_STATID[i]) & 0xff;
142
143 vme_irq_handler(ca91cx42_bridge, i, vec);
144
145 serviced |= (1 << i);
146 }
147 }
148
149 return serviced;
150}
151
152static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
153{
154 u32 stat, enable, serviced = 0;
155 struct vme_bridge *ca91cx42_bridge;
156 struct ca91cx42_driver *bridge;
157
158 ca91cx42_bridge = ptr;
159
160 bridge = ca91cx42_bridge->driver_priv;
161
162 enable = ioread32(bridge->base + LINT_EN);
163 stat = ioread32(bridge->base + LINT_STAT);
164
165 /* Only look at unmasked interrupts */
166 stat &= enable;
167
168 if (unlikely(!stat))
169 return IRQ_NONE;
170
171 if (stat & CA91CX42_LINT_DMA)
172 serviced |= ca91cx42_DMA_irqhandler(bridge);
173 if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
174 CA91CX42_LINT_LM3))
175 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
176 if (stat & CA91CX42_LINT_MBOX)
177 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
178 if (stat & CA91CX42_LINT_SW_IACK)
179 serviced |= ca91cx42_IACK_irqhandler(bridge);
180 if (stat & CA91CX42_LINT_VERR)
181 serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge);
182 if (stat & CA91CX42_LINT_LERR)
183 serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge);
184 if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
185 CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
186 CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
187 CA91CX42_LINT_VIRQ7))
188 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
189
190 /* Clear serviced interrupts */
191 iowrite32(serviced, bridge->base + LINT_STAT);
192
193 return IRQ_HANDLED;
194}
195
196static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
197{
198 int result, tmp;
199 struct pci_dev *pdev;
200 struct ca91cx42_driver *bridge;
201
202 bridge = ca91cx42_bridge->driver_priv;
203
204 /* Need pdev */
205 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
206
207 /* Initialise list for VME bus errors */
208 INIT_LIST_HEAD(&ca91cx42_bridge->vme_errors);
209
210 mutex_init(&ca91cx42_bridge->irq_mtx);
211
212 /* Disable interrupts from PCI to VME */
213 iowrite32(0, bridge->base + VINT_EN);
214
215 /* Disable PCI interrupts */
216 iowrite32(0, bridge->base + LINT_EN);
217 /* Clear Any Pending PCI Interrupts */
218 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
219
220 result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
221 driver_name, ca91cx42_bridge);
222 if (result) {
223 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
224 pdev->irq);
225 return result;
226 }
227
228 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
229 iowrite32(0, bridge->base + LINT_MAP0);
230 iowrite32(0, bridge->base + LINT_MAP1);
231 iowrite32(0, bridge->base + LINT_MAP2);
232
233 /* Enable DMA, mailbox & LM Interrupts */
234 tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
235 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
236 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
237
238 iowrite32(tmp, bridge->base + LINT_EN);
239
240 return 0;
241}
242
243static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
244 struct pci_dev *pdev)
245{
246 /* Disable interrupts from PCI to VME */
247 iowrite32(0, bridge->base + VINT_EN);
248
249 /* Disable PCI interrupts */
250 iowrite32(0, bridge->base + LINT_EN);
251 /* Clear Any Pending PCI Interrupts */
252 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
253
254 free_irq(pdev->irq, pdev);
255}
256
257static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level)
258{
259 u32 tmp;
260
261 tmp = ioread32(bridge->base + LINT_STAT);
262
263 if (tmp & (1 << level))
264 return 0;
265 else
266 return 1;
267}
268
269/*
270 * Set up an VME interrupt
271 */
272static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level,
273 int state, int sync)
274
275{
276 struct pci_dev *pdev;
277 u32 tmp;
278 struct ca91cx42_driver *bridge;
279
280 bridge = ca91cx42_bridge->driver_priv;
281
282 /* Enable IRQ level */
283 tmp = ioread32(bridge->base + LINT_EN);
284
285 if (state == 0)
286 tmp &= ~CA91CX42_LINT_VIRQ[level];
287 else
288 tmp |= CA91CX42_LINT_VIRQ[level];
289
290 iowrite32(tmp, bridge->base + LINT_EN);
291
292 if ((state == 0) && (sync != 0)) {
293 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
294 dev);
295
296 synchronize_irq(pdev->irq);
297 }
298}
299
300static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
301 int statid)
302{
303 u32 tmp;
304 struct ca91cx42_driver *bridge;
305
306 bridge = ca91cx42_bridge->driver_priv;
307
308 /* Universe can only generate even vectors */
309 if (statid & 1)
310 return -EINVAL;
311
312 mutex_lock(&bridge->vme_int);
313
314 tmp = ioread32(bridge->base + VINT_EN);
315
316 /* Set Status/ID */
317 iowrite32(statid << 24, bridge->base + STATID);
318
319 /* Assert VMEbus IRQ */
320 tmp = tmp | (1 << (level + 24));
321 iowrite32(tmp, bridge->base + VINT_EN);
322
323 /* Wait for IACK */
324 wait_event_interruptible(bridge->iack_queue,
325 ca91cx42_iack_received(bridge, level));
326
327 /* Return interrupt to low state */
328 tmp = ioread32(bridge->base + VINT_EN);
329 tmp = tmp & ~(1 << (level + 24));
330 iowrite32(tmp, bridge->base + VINT_EN);
331
332 mutex_unlock(&bridge->vme_int);
333
334 return 0;
335}
336
337static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
338 unsigned long long vme_base, unsigned long long size,
339 dma_addr_t pci_base, u32 aspace, u32 cycle)
340{
341 unsigned int i, addr = 0, granularity;
342 unsigned int temp_ctl = 0;
343 unsigned int vme_bound, pci_offset;
344 struct vme_bridge *ca91cx42_bridge;
345 struct ca91cx42_driver *bridge;
346
347 ca91cx42_bridge = image->parent;
348
349 bridge = ca91cx42_bridge->driver_priv;
350
351 i = image->number;
352
353 switch (aspace) {
354 case VME_A16:
355 addr |= CA91CX42_VSI_CTL_VAS_A16;
356 break;
357 case VME_A24:
358 addr |= CA91CX42_VSI_CTL_VAS_A24;
359 break;
360 case VME_A32:
361 addr |= CA91CX42_VSI_CTL_VAS_A32;
362 break;
363 case VME_USER1:
364 addr |= CA91CX42_VSI_CTL_VAS_USER1;
365 break;
366 case VME_USER2:
367 addr |= CA91CX42_VSI_CTL_VAS_USER2;
368 break;
369 case VME_A64:
370 case VME_CRCSR:
371 case VME_USER3:
372 case VME_USER4:
373 default:
374 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
375 return -EINVAL;
376 break;
377 }
378
379 /*
380 * Bound address is a valid address for the window, adjust
381 * accordingly
382 */
383 vme_bound = vme_base + size;
384 pci_offset = pci_base - vme_base;
385
386 if ((i == 0) || (i == 4))
387 granularity = 0x1000;
388 else
389 granularity = 0x10000;
390
391 if (vme_base & (granularity - 1)) {
392 dev_err(ca91cx42_bridge->parent, "Invalid VME base "
393 "alignment\n");
394 return -EINVAL;
395 }
396 if (vme_bound & (granularity - 1)) {
397 dev_err(ca91cx42_bridge->parent, "Invalid VME bound "
398 "alignment\n");
399 return -EINVAL;
400 }
401 if (pci_offset & (granularity - 1)) {
402 dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset "
403 "alignment\n");
404 return -EINVAL;
405 }
406
407 /* Disable while we are mucking around */
408 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
409 temp_ctl &= ~CA91CX42_VSI_CTL_EN;
410 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
411
412 /* Setup mapping */
413 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
414 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
415 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
416
417 /* Setup address space */
418 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
419 temp_ctl |= addr;
420
421 /* Setup cycle types */
422 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
423 if (cycle & VME_SUPER)
424 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
425 if (cycle & VME_USER)
426 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
427 if (cycle & VME_PROG)
428 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
429 if (cycle & VME_DATA)
430 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
431
432 /* Write ctl reg without enable */
433 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
434
435 if (enabled)
436 temp_ctl |= CA91CX42_VSI_CTL_EN;
437
438 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
439
440 return 0;
441}
442
443static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
444 unsigned long long *vme_base, unsigned long long *size,
445 dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
446{
447 unsigned int i, granularity = 0, ctl = 0;
448 unsigned long long vme_bound, pci_offset;
449 struct ca91cx42_driver *bridge;
450
451 bridge = image->parent->driver_priv;
452
453 i = image->number;
454
455 if ((i == 0) || (i == 4))
456 granularity = 0x1000;
457 else
458 granularity = 0x10000;
459
460 /* Read Registers */
461 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
462
463 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
464 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
465 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
466
467 *pci_base = (dma_addr_t)vme_base + pci_offset;
468 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
469
470 *enabled = 0;
471 *aspace = 0;
472 *cycle = 0;
473
474 if (ctl & CA91CX42_VSI_CTL_EN)
475 *enabled = 1;
476
477 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
478 *aspace = VME_A16;
479 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
480 *aspace = VME_A24;
481 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
482 *aspace = VME_A32;
483 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
484 *aspace = VME_USER1;
485 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
486 *aspace = VME_USER2;
487
488 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
489 *cycle |= VME_SUPER;
490 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
491 *cycle |= VME_USER;
492 if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
493 *cycle |= VME_PROG;
494 if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
495 *cycle |= VME_DATA;
496
497 return 0;
498}
499
500/*
501 * Allocate and map PCI Resource
502 */
503static int ca91cx42_alloc_resource(struct vme_master_resource *image,
504 unsigned long long size)
505{
506 unsigned long long existing_size;
507 int retval = 0;
508 struct pci_dev *pdev;
509 struct vme_bridge *ca91cx42_bridge;
510
511 ca91cx42_bridge = image->parent;
512
513 /* Find pci_dev container of dev */
514 if (ca91cx42_bridge->parent == NULL) {
515 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
516 return -EINVAL;
517 }
518 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
519
520 existing_size = (unsigned long long)(image->bus_resource.end -
521 image->bus_resource.start);
522
523 /* If the existing size is OK, return */
524 if (existing_size == (size - 1))
525 return 0;
526
527 if (existing_size != 0) {
528 iounmap(image->kern_base);
529 image->kern_base = NULL;
530 kfree(image->bus_resource.name);
531 release_resource(&image->bus_resource);
532 memset(&image->bus_resource, 0, sizeof(struct resource));
533 }
534
535 if (image->bus_resource.name == NULL) {
536 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
537 if (image->bus_resource.name == NULL) {
538 dev_err(ca91cx42_bridge->parent, "Unable to allocate "
539 "memory for resource name\n");
540 retval = -ENOMEM;
541 goto err_name;
542 }
543 }
544
545 sprintf((char *)image->bus_resource.name, "%s.%d",
546 ca91cx42_bridge->name, image->number);
547
548 image->bus_resource.start = 0;
549 image->bus_resource.end = (unsigned long)size;
550 image->bus_resource.flags = IORESOURCE_MEM;
551
552 retval = pci_bus_alloc_resource(pdev->bus,
553 &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
554 0, NULL, NULL);
555 if (retval) {
556 dev_err(ca91cx42_bridge->parent, "Failed to allocate mem "
557 "resource for window %d size 0x%lx start 0x%lx\n",
558 image->number, (unsigned long)size,
559 (unsigned long)image->bus_resource.start);
560 goto err_resource;
561 }
562
563 image->kern_base = ioremap_nocache(
564 image->bus_resource.start, size);
565 if (image->kern_base == NULL) {
566 dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n");
567 retval = -ENOMEM;
568 goto err_remap;
569 }
570
571 return 0;
572
573err_remap:
574 release_resource(&image->bus_resource);
575err_resource:
576 kfree(image->bus_resource.name);
577 memset(&image->bus_resource, 0, sizeof(struct resource));
578err_name:
579 return retval;
580}
581
582/*
583 * Free and unmap PCI Resource
584 */
585static void ca91cx42_free_resource(struct vme_master_resource *image)
586{
587 iounmap(image->kern_base);
588 image->kern_base = NULL;
589 release_resource(&image->bus_resource);
590 kfree(image->bus_resource.name);
591 memset(&image->bus_resource, 0, sizeof(struct resource));
592}
593
594
595static int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
596 unsigned long long vme_base, unsigned long long size, u32 aspace,
597 u32 cycle, u32 dwidth)
598{
599 int retval = 0;
600 unsigned int i, granularity = 0;
601 unsigned int temp_ctl = 0;
602 unsigned long long pci_bound, vme_offset, pci_base;
603 struct vme_bridge *ca91cx42_bridge;
604 struct ca91cx42_driver *bridge;
605
606 ca91cx42_bridge = image->parent;
607
608 bridge = ca91cx42_bridge->driver_priv;
609
610 i = image->number;
611
612 if ((i == 0) || (i == 4))
613 granularity = 0x1000;
614 else
615 granularity = 0x10000;
616
617 /* Verify input data */
618 if (vme_base & (granularity - 1)) {
619 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
620 "alignment\n");
621 retval = -EINVAL;
622 goto err_window;
623 }
624 if (size & (granularity - 1)) {
625 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
626 "alignment\n");
627 retval = -EINVAL;
628 goto err_window;
629 }
630
631 spin_lock(&image->lock);
632
633 /*
634 * Let's allocate the resource here rather than further up the stack as
635 * it avoids pushing loads of bus dependent stuff up the stack
636 */
637 retval = ca91cx42_alloc_resource(image, size);
638 if (retval) {
639 spin_unlock(&image->lock);
640 dev_err(ca91cx42_bridge->parent, "Unable to allocate memory "
641 "for resource name\n");
642 retval = -ENOMEM;
643 goto err_res;
644 }
645
646 pci_base = (unsigned long long)image->bus_resource.start;
647
648 /*
649 * Bound address is a valid address for the window, adjust
650 * according to window granularity.
651 */
652 pci_bound = pci_base + size;
653 vme_offset = vme_base - pci_base;
654
655 /* Disable while we are mucking around */
656 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
657 temp_ctl &= ~CA91CX42_LSI_CTL_EN;
658 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
659
660 /* Setup cycle types */
661 temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
662 if (cycle & VME_BLT)
663 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
664 if (cycle & VME_MBLT)
665 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
666
667 /* Setup data width */
668 temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
669 switch (dwidth) {
670 case VME_D8:
671 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
672 break;
673 case VME_D16:
674 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
675 break;
676 case VME_D32:
677 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
678 break;
679 case VME_D64:
680 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
681 break;
682 default:
683 spin_unlock(&image->lock);
684 dev_err(ca91cx42_bridge->parent, "Invalid data width\n");
685 retval = -EINVAL;
686 goto err_dwidth;
687 break;
688 }
689
690 /* Setup address space */
691 temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
692 switch (aspace) {
693 case VME_A16:
694 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
695 break;
696 case VME_A24:
697 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
698 break;
699 case VME_A32:
700 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
701 break;
702 case VME_CRCSR:
703 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
704 break;
705 case VME_USER1:
706 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
707 break;
708 case VME_USER2:
709 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
710 break;
711 case VME_A64:
712 case VME_USER3:
713 case VME_USER4:
714 default:
715 spin_unlock(&image->lock);
716 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
717 retval = -EINVAL;
718 goto err_aspace;
719 break;
720 }
721
722 temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
723 if (cycle & VME_SUPER)
724 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
725 if (cycle & VME_PROG)
726 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
727
728 /* Setup mapping */
729 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
730 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
731 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
732
733 /* Write ctl reg without enable */
734 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
735
736 if (enabled)
737 temp_ctl |= CA91CX42_LSI_CTL_EN;
738
739 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
740
741 spin_unlock(&image->lock);
742 return 0;
743
744err_aspace:
745err_dwidth:
746 ca91cx42_free_resource(image);
747err_res:
748err_window:
749 return retval;
750}
751
752static int __ca91cx42_master_get(struct vme_master_resource *image,
753 int *enabled, unsigned long long *vme_base, unsigned long long *size,
754 u32 *aspace, u32 *cycle, u32 *dwidth)
755{
756 unsigned int i, ctl;
757 unsigned long long pci_base, pci_bound, vme_offset;
758 struct ca91cx42_driver *bridge;
759
760 bridge = image->parent->driver_priv;
761
762 i = image->number;
763
764 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
765
766 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
767 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
768 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
769
770 *vme_base = pci_base + vme_offset;
771 *size = (unsigned long long)(pci_bound - pci_base);
772
773 *enabled = 0;
774 *aspace = 0;
775 *cycle = 0;
776 *dwidth = 0;
777
778 if (ctl & CA91CX42_LSI_CTL_EN)
779 *enabled = 1;
780
781 /* Setup address space */
782 switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
783 case CA91CX42_LSI_CTL_VAS_A16:
784 *aspace = VME_A16;
785 break;
786 case CA91CX42_LSI_CTL_VAS_A24:
787 *aspace = VME_A24;
788 break;
789 case CA91CX42_LSI_CTL_VAS_A32:
790 *aspace = VME_A32;
791 break;
792 case CA91CX42_LSI_CTL_VAS_CRCSR:
793 *aspace = VME_CRCSR;
794 break;
795 case CA91CX42_LSI_CTL_VAS_USER1:
796 *aspace = VME_USER1;
797 break;
798 case CA91CX42_LSI_CTL_VAS_USER2:
799 *aspace = VME_USER2;
800 break;
801 }
802
803 /* XXX Not sure howto check for MBLT */
804 /* Setup cycle types */
805 if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
806 *cycle |= VME_BLT;
807 else
808 *cycle |= VME_SCT;
809
810 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
811 *cycle |= VME_SUPER;
812 else
813 *cycle |= VME_USER;
814
815 if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
816 *cycle = VME_PROG;
817 else
818 *cycle = VME_DATA;
819
820 /* Setup data width */
821 switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
822 case CA91CX42_LSI_CTL_VDW_D8:
823 *dwidth = VME_D8;
824 break;
825 case CA91CX42_LSI_CTL_VDW_D16:
826 *dwidth = VME_D16;
827 break;
828 case CA91CX42_LSI_CTL_VDW_D32:
829 *dwidth = VME_D32;
830 break;
831 case CA91CX42_LSI_CTL_VDW_D64:
832 *dwidth = VME_D64;
833 break;
834 }
835
836 return 0;
837}
838
839static int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
840 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
841 u32 *cycle, u32 *dwidth)
842{
843 int retval;
844
845 spin_lock(&image->lock);
846
847 retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
848 cycle, dwidth);
849
850 spin_unlock(&image->lock);
851
852 return retval;
853}
854
855static ssize_t ca91cx42_master_read(struct vme_master_resource *image,
856 void *buf, size_t count, loff_t offset)
857{
858 ssize_t retval;
859 void *addr = image->kern_base + offset;
860 unsigned int done = 0;
861 unsigned int count32;
862
863 if (count == 0)
864 return 0;
865
866 spin_lock(&image->lock);
867
868 /* The following code handles VME address alignment problem
869 * in order to assure the maximal data width cycle.
870 * We cannot use memcpy_xxx directly here because it
871 * may cut data transfer in 8-bits cycles, thus making
872 * D16 cycle impossible.
873 * From the other hand, the bridge itself assures that
874 * maximal configured data cycle is used and splits it
875 * automatically for non-aligned addresses.
876 */
877 if ((uintptr_t)addr & 0x1) {
878 *(u8 *)buf = ioread8(addr);
879 done += 1;
880 if (done == count)
881 goto out;
882 }
883 if ((uintptr_t)addr & 0x2) {
884 if ((count - done) < 2) {
885 *(u8 *)(buf + done) = ioread8(addr + done);
886 done += 1;
887 goto out;
888 } else {
889 *(u16 *)(buf + done) = ioread16(addr + done);
890 done += 2;
891 }
892 }
893
894 count32 = (count - done) & ~0x3;
895 if (count32 > 0) {
896 memcpy_fromio(buf + done, addr + done, (unsigned int)count);
897 done += count32;
898 }
899
900 if ((count - done) & 0x2) {
901 *(u16 *)(buf + done) = ioread16(addr + done);
902 done += 2;
903 }
904 if ((count - done) & 0x1) {
905 *(u8 *)(buf + done) = ioread8(addr + done);
906 done += 1;
907 }
908out:
909 retval = count;
910 spin_unlock(&image->lock);
911
912 return retval;
913}
914
915static ssize_t ca91cx42_master_write(struct vme_master_resource *image,
916 void *buf, size_t count, loff_t offset)
917{
918 ssize_t retval;
919 void *addr = image->kern_base + offset;
920 unsigned int done = 0;
921 unsigned int count32;
922
923 if (count == 0)
924 return 0;
925
926 spin_lock(&image->lock);
927
928 /* Here we apply for the same strategy we do in master_read
929 * function in order to assure D16 cycle when required.
930 */
931 if ((uintptr_t)addr & 0x1) {
932 iowrite8(*(u8 *)buf, addr);
933 done += 1;
934 if (done == count)
935 goto out;
936 }
937 if ((uintptr_t)addr & 0x2) {
938 if ((count - done) < 2) {
939 iowrite8(*(u8 *)(buf + done), addr + done);
940 done += 1;
941 goto out;
942 } else {
943 iowrite16(*(u16 *)(buf + done), addr + done);
944 done += 2;
945 }
946 }
947
948 count32 = (count - done) & ~0x3;
949 if (count32 > 0) {
950 memcpy_toio(addr + done, buf + done, count32);
951 done += count32;
952 }
953
954 if ((count - done) & 0x2) {
955 iowrite16(*(u16 *)(buf + done), addr + done);
956 done += 2;
957 }
958 if ((count - done) & 0x1) {
959 iowrite8(*(u8 *)(buf + done), addr + done);
960 done += 1;
961 }
962out:
963 retval = count;
964
965 spin_unlock(&image->lock);
966
967 return retval;
968}
969
970static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
971 unsigned int mask, unsigned int compare, unsigned int swap,
972 loff_t offset)
973{
974 u32 result;
975 uintptr_t pci_addr;
976 int i;
977 struct ca91cx42_driver *bridge;
978 struct device *dev;
979
980 bridge = image->parent->driver_priv;
981 dev = image->parent->parent;
982
983 /* Find the PCI address that maps to the desired VME address */
984 i = image->number;
985
986 /* Locking as we can only do one of these at a time */
987 mutex_lock(&bridge->vme_rmw);
988
989 /* Lock image */
990 spin_lock(&image->lock);
991
992 pci_addr = (uintptr_t)image->kern_base + offset;
993
994 /* Address must be 4-byte aligned */
995 if (pci_addr & 0x3) {
996 dev_err(dev, "RMW Address not 4-byte aligned\n");
997 result = -EINVAL;
998 goto out;
999 }
1000
1001 /* Ensure RMW Disabled whilst configuring */
1002 iowrite32(0, bridge->base + SCYC_CTL);
1003
1004 /* Configure registers */
1005 iowrite32(mask, bridge->base + SCYC_EN);
1006 iowrite32(compare, bridge->base + SCYC_CMP);
1007 iowrite32(swap, bridge->base + SCYC_SWP);
1008 iowrite32(pci_addr, bridge->base + SCYC_ADDR);
1009
1010 /* Enable RMW */
1011 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
1012
1013 /* Kick process off with a read to the required address. */
1014 result = ioread32(image->kern_base + offset);
1015
1016 /* Disable RMW */
1017 iowrite32(0, bridge->base + SCYC_CTL);
1018
1019out:
1020 spin_unlock(&image->lock);
1021
1022 mutex_unlock(&bridge->vme_rmw);
1023
1024 return result;
1025}
1026
1027static int ca91cx42_dma_list_add(struct vme_dma_list *list,
1028 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1029{
1030 struct ca91cx42_dma_entry *entry, *prev;
1031 struct vme_dma_pci *pci_attr;
1032 struct vme_dma_vme *vme_attr;
1033 dma_addr_t desc_ptr;
1034 int retval = 0;
1035 struct device *dev;
1036
1037 dev = list->parent->parent->parent;
1038
1039 /* XXX descriptor must be aligned on 64-bit boundaries */
1040 entry = kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
1041 if (entry == NULL) {
1042 dev_err(dev, "Failed to allocate memory for dma resource "
1043 "structure\n");
1044 retval = -ENOMEM;
1045 goto err_mem;
1046 }
1047
1048 /* Test descriptor alignment */
1049 if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {
1050 dev_err(dev, "Descriptor not aligned to 16 byte boundary as "
1051 "required: %p\n", &entry->descriptor);
1052 retval = -EINVAL;
1053 goto err_align;
1054 }
1055
1056 memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor));
1057
1058 if (dest->type == VME_DMA_VME) {
1059 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
1060 vme_attr = dest->private;
1061 pci_attr = src->private;
1062 } else {
1063 vme_attr = src->private;
1064 pci_attr = dest->private;
1065 }
1066
1067 /* Check we can do fulfill required attributes */
1068 if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1069 VME_USER2)) != 0) {
1070
1071 dev_err(dev, "Unsupported cycle type\n");
1072 retval = -EINVAL;
1073 goto err_aspace;
1074 }
1075
1076 if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1077 VME_PROG | VME_DATA)) != 0) {
1078
1079 dev_err(dev, "Unsupported cycle type\n");
1080 retval = -EINVAL;
1081 goto err_cycle;
1082 }
1083
1084 /* Check to see if we can fulfill source and destination */
1085 if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1086 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1087
1088 dev_err(dev, "Cannot perform transfer with this "
1089 "source-destination combination\n");
1090 retval = -EINVAL;
1091 goto err_direct;
1092 }
1093
1094 /* Setup cycle types */
1095 if (vme_attr->cycle & VME_BLT)
1096 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1097
1098 /* Setup data width */
1099 switch (vme_attr->dwidth) {
1100 case VME_D8:
1101 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1102 break;
1103 case VME_D16:
1104 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1105 break;
1106 case VME_D32:
1107 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1108 break;
1109 case VME_D64:
1110 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1111 break;
1112 default:
1113 dev_err(dev, "Invalid data width\n");
1114 return -EINVAL;
1115 }
1116
1117 /* Setup address space */
1118 switch (vme_attr->aspace) {
1119 case VME_A16:
1120 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1121 break;
1122 case VME_A24:
1123 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1124 break;
1125 case VME_A32:
1126 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1127 break;
1128 case VME_USER1:
1129 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1130 break;
1131 case VME_USER2:
1132 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1133 break;
1134 default:
1135 dev_err(dev, "Invalid address space\n");
1136 return -EINVAL;
1137 break;
1138 }
1139
1140 if (vme_attr->cycle & VME_SUPER)
1141 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1142 if (vme_attr->cycle & VME_PROG)
1143 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1144
1145 entry->descriptor.dtbc = count;
1146 entry->descriptor.dla = pci_attr->address;
1147 entry->descriptor.dva = vme_attr->address;
1148 entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1149
1150 /* Add to list */
1151 list_add_tail(&entry->list, &list->entries);
1152
1153 /* Fill out previous descriptors "Next Address" */
1154 if (entry->list.prev != &list->entries) {
1155 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1156 list);
1157 /* We need the bus address for the pointer */
1158 desc_ptr = virt_to_bus(&entry->descriptor);
1159 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1160 }
1161
1162 return 0;
1163
1164err_cycle:
1165err_aspace:
1166err_direct:
1167err_align:
1168 kfree(entry);
1169err_mem:
1170 return retval;
1171}
1172
1173static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1174{
1175 u32 tmp;
1176 struct ca91cx42_driver *bridge;
1177
1178 bridge = ca91cx42_bridge->driver_priv;
1179
1180 tmp = ioread32(bridge->base + DGCS);
1181
1182 if (tmp & CA91CX42_DGCS_ACT)
1183 return 0;
1184 else
1185 return 1;
1186}
1187
1188static int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1189{
1190 struct vme_dma_resource *ctrlr;
1191 struct ca91cx42_dma_entry *entry;
1192 int retval = 0;
1193 dma_addr_t bus_addr;
1194 u32 val;
1195 struct device *dev;
1196 struct ca91cx42_driver *bridge;
1197
1198 ctrlr = list->parent;
1199
1200 bridge = ctrlr->parent->driver_priv;
1201 dev = ctrlr->parent->parent;
1202
1203 mutex_lock(&ctrlr->mtx);
1204
1205 if (!(list_empty(&ctrlr->running))) {
1206 /*
1207 * XXX We have an active DMA transfer and currently haven't
1208 * sorted out the mechanism for "pending" DMA transfers.
1209 * Return busy.
1210 */
1211 /* Need to add to pending here */
1212 mutex_unlock(&ctrlr->mtx);
1213 return -EBUSY;
1214 } else {
1215 list_add(&list->list, &ctrlr->running);
1216 }
1217
1218 /* Get first bus address and write into registers */
1219 entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry,
1220 list);
1221
1222 bus_addr = virt_to_bus(&entry->descriptor);
1223
1224 mutex_unlock(&ctrlr->mtx);
1225
1226 iowrite32(0, bridge->base + DTBC);
1227 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1228
1229 /* Start the operation */
1230 val = ioread32(bridge->base + DGCS);
1231
1232 /* XXX Could set VMEbus On and Off Counters here */
1233 val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1234
1235 val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1236 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1237 CA91CX42_DGCS_PERR);
1238
1239 iowrite32(val, bridge->base + DGCS);
1240
1241 val |= CA91CX42_DGCS_GO;
1242
1243 iowrite32(val, bridge->base + DGCS);
1244
1245 wait_event_interruptible(bridge->dma_queue,
1246 ca91cx42_dma_busy(ctrlr->parent));
1247
1248 /*
1249 * Read status register, this register is valid until we kick off a
1250 * new transfer.
1251 */
1252 val = ioread32(bridge->base + DGCS);
1253
1254 if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1255 CA91CX42_DGCS_PERR)) {
1256
1257 dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val);
1258 val = ioread32(bridge->base + DCTL);
1259 }
1260
1261 /* Remove list from running list */
1262 mutex_lock(&ctrlr->mtx);
1263 list_del(&list->list);
1264 mutex_unlock(&ctrlr->mtx);
1265
1266 return retval;
1267
1268}
1269
1270static int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1271{
1272 struct list_head *pos, *temp;
1273 struct ca91cx42_dma_entry *entry;
1274
1275 /* detach and free each entry */
1276 list_for_each_safe(pos, temp, &list->entries) {
1277 list_del(pos);
1278 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1279 kfree(entry);
1280 }
1281
1282 return 0;
1283}
1284
1285/*
1286 * All 4 location monitors reside at the same base - this is therefore a
1287 * system wide configuration.
1288 *
1289 * This does not enable the LM monitor - that should be done when the first
1290 * callback is attached and disabled when the last callback is removed.
1291 */
1292static int ca91cx42_lm_set(struct vme_lm_resource *lm,
1293 unsigned long long lm_base, u32 aspace, u32 cycle)
1294{
1295 u32 temp_base, lm_ctl = 0;
1296 int i;
1297 struct ca91cx42_driver *bridge;
1298 struct device *dev;
1299
1300 bridge = lm->parent->driver_priv;
1301 dev = lm->parent->parent;
1302
1303 /* Check the alignment of the location monitor */
1304 temp_base = (u32)lm_base;
1305 if (temp_base & 0xffff) {
1306 dev_err(dev, "Location monitor must be aligned to 64KB "
1307 "boundary");
1308 return -EINVAL;
1309 }
1310
1311 mutex_lock(&lm->mtx);
1312
1313 /* If we already have a callback attached, we can't move it! */
1314 for (i = 0; i < lm->monitors; i++) {
1315 if (bridge->lm_callback[i] != NULL) {
1316 mutex_unlock(&lm->mtx);
1317 dev_err(dev, "Location monitor callback attached, "
1318 "can't reset\n");
1319 return -EBUSY;
1320 }
1321 }
1322
1323 switch (aspace) {
1324 case VME_A16:
1325 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1326 break;
1327 case VME_A24:
1328 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1329 break;
1330 case VME_A32:
1331 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1332 break;
1333 default:
1334 mutex_unlock(&lm->mtx);
1335 dev_err(dev, "Invalid address space\n");
1336 return -EINVAL;
1337 break;
1338 }
1339
1340 if (cycle & VME_SUPER)
1341 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1342 if (cycle & VME_USER)
1343 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1344 if (cycle & VME_PROG)
1345 lm_ctl |= CA91CX42_LM_CTL_PGM;
1346 if (cycle & VME_DATA)
1347 lm_ctl |= CA91CX42_LM_CTL_DATA;
1348
1349 iowrite32(lm_base, bridge->base + LM_BS);
1350 iowrite32(lm_ctl, bridge->base + LM_CTL);
1351
1352 mutex_unlock(&lm->mtx);
1353
1354 return 0;
1355}
1356
1357/* Get configuration of the callback monitor and return whether it is enabled
1358 * or disabled.
1359 */
1360static int ca91cx42_lm_get(struct vme_lm_resource *lm,
1361 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
1362{
1363 u32 lm_ctl, enabled = 0;
1364 struct ca91cx42_driver *bridge;
1365
1366 bridge = lm->parent->driver_priv;
1367
1368 mutex_lock(&lm->mtx);
1369
1370 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1371 lm_ctl = ioread32(bridge->base + LM_CTL);
1372
1373 if (lm_ctl & CA91CX42_LM_CTL_EN)
1374 enabled = 1;
1375
1376 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1377 *aspace = VME_A16;
1378 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1379 *aspace = VME_A24;
1380 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1381 *aspace = VME_A32;
1382
1383 *cycle = 0;
1384 if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1385 *cycle |= VME_SUPER;
1386 if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1387 *cycle |= VME_USER;
1388 if (lm_ctl & CA91CX42_LM_CTL_PGM)
1389 *cycle |= VME_PROG;
1390 if (lm_ctl & CA91CX42_LM_CTL_DATA)
1391 *cycle |= VME_DATA;
1392
1393 mutex_unlock(&lm->mtx);
1394
1395 return enabled;
1396}
1397
1398/*
1399 * Attach a callback to a specific location monitor.
1400 *
1401 * Callback will be passed the monitor triggered.
1402 */
1403static int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1404 void (*callback)(int))
1405{
1406 u32 lm_ctl, tmp;
1407 struct ca91cx42_driver *bridge;
1408 struct device *dev;
1409
1410 bridge = lm->parent->driver_priv;
1411 dev = lm->parent->parent;
1412
1413 mutex_lock(&lm->mtx);
1414
1415 /* Ensure that the location monitor is configured - need PGM or DATA */
1416 lm_ctl = ioread32(bridge->base + LM_CTL);
1417 if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1418 mutex_unlock(&lm->mtx);
1419 dev_err(dev, "Location monitor not properly configured\n");
1420 return -EINVAL;
1421 }
1422
1423 /* Check that a callback isn't already attached */
1424 if (bridge->lm_callback[monitor] != NULL) {
1425 mutex_unlock(&lm->mtx);
1426 dev_err(dev, "Existing callback attached\n");
1427 return -EBUSY;
1428 }
1429
1430 /* Attach callback */
1431 bridge->lm_callback[monitor] = callback;
1432
1433 /* Enable Location Monitor interrupt */
1434 tmp = ioread32(bridge->base + LINT_EN);
1435 tmp |= CA91CX42_LINT_LM[monitor];
1436 iowrite32(tmp, bridge->base + LINT_EN);
1437
1438 /* Ensure that global Location Monitor Enable set */
1439 if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1440 lm_ctl |= CA91CX42_LM_CTL_EN;
1441 iowrite32(lm_ctl, bridge->base + LM_CTL);
1442 }
1443
1444 mutex_unlock(&lm->mtx);
1445
1446 return 0;
1447}
1448
1449/*
1450 * Detach a callback function forn a specific location monitor.
1451 */
1452static int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1453{
1454 u32 tmp;
1455 struct ca91cx42_driver *bridge;
1456
1457 bridge = lm->parent->driver_priv;
1458
1459 mutex_lock(&lm->mtx);
1460
1461 /* Disable Location Monitor and ensure previous interrupts are clear */
1462 tmp = ioread32(bridge->base + LINT_EN);
1463 tmp &= ~CA91CX42_LINT_LM[monitor];
1464 iowrite32(tmp, bridge->base + LINT_EN);
1465
1466 iowrite32(CA91CX42_LINT_LM[monitor],
1467 bridge->base + LINT_STAT);
1468
1469 /* Detach callback */
1470 bridge->lm_callback[monitor] = NULL;
1471
1472 /* If all location monitors disabled, disable global Location Monitor */
1473 if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1474 CA91CX42_LINT_LM3)) == 0) {
1475 tmp = ioread32(bridge->base + LM_CTL);
1476 tmp &= ~CA91CX42_LM_CTL_EN;
1477 iowrite32(tmp, bridge->base + LM_CTL);
1478 }
1479
1480 mutex_unlock(&lm->mtx);
1481
1482 return 0;
1483}
1484
1485static int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1486{
1487 u32 slot = 0;
1488 struct ca91cx42_driver *bridge;
1489
1490 bridge = ca91cx42_bridge->driver_priv;
1491
1492 if (!geoid) {
1493 slot = ioread32(bridge->base + VCSR_BS);
1494 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1495 } else
1496 slot = geoid;
1497
1498 return (int)slot;
1499
1500}
1501
1502static void *ca91cx42_alloc_consistent(struct device *parent, size_t size,
1503 dma_addr_t *dma)
1504{
1505 struct pci_dev *pdev;
1506
1507 /* Find pci_dev container of dev */
1508 pdev = container_of(parent, struct pci_dev, dev);
1509
1510 return pci_alloc_consistent(pdev, size, dma);
1511}
1512
1513static void ca91cx42_free_consistent(struct device *parent, size_t size,
1514 void *vaddr, dma_addr_t dma)
1515{
1516 struct pci_dev *pdev;
1517
1518 /* Find pci_dev container of dev */
1519 pdev = container_of(parent, struct pci_dev, dev);
1520
1521 pci_free_consistent(pdev, size, vaddr, dma);
1522}
1523
1524/*
1525 * Configure CR/CSR space
1526 *
1527 * Access to the CR/CSR can be configured at power-up. The location of the
1528 * CR/CSR registers in the CR/CSR address space is determined by the boards
1529 * Auto-ID or Geographic address. This function ensures that the window is
1530 * enabled at an offset consistent with the boards geopgraphic address.
1531 */
1532static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1533 struct pci_dev *pdev)
1534{
1535 unsigned int crcsr_addr;
1536 int tmp, slot;
1537 struct ca91cx42_driver *bridge;
1538
1539 bridge = ca91cx42_bridge->driver_priv;
1540
1541 slot = ca91cx42_slot_get(ca91cx42_bridge);
1542
1543 /* Write CSR Base Address if slot ID is supplied as a module param */
1544 if (geoid)
1545 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1546
1547 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1548 if (slot == 0) {
1549 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1550 "CR/CSR space\n");
1551 return -EINVAL;
1552 }
1553
1554 /* Allocate mem for CR/CSR image */
1555 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1556 &bridge->crcsr_bus);
1557 if (bridge->crcsr_kernel == NULL) {
1558 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1559 "image\n");
1560 return -ENOMEM;
1561 }
1562
1563 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
1564
1565 crcsr_addr = slot * (512 * 1024);
1566 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1567
1568 tmp = ioread32(bridge->base + VCSR_CTL);
1569 tmp |= CA91CX42_VCSR_CTL_EN;
1570 iowrite32(tmp, bridge->base + VCSR_CTL);
1571
1572 return 0;
1573}
1574
1575static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1576 struct pci_dev *pdev)
1577{
1578 u32 tmp;
1579 struct ca91cx42_driver *bridge;
1580
1581 bridge = ca91cx42_bridge->driver_priv;
1582
1583 /* Turn off CR/CSR space */
1584 tmp = ioread32(bridge->base + VCSR_CTL);
1585 tmp &= ~CA91CX42_VCSR_CTL_EN;
1586 iowrite32(tmp, bridge->base + VCSR_CTL);
1587
1588 /* Free image */
1589 iowrite32(0, bridge->base + VCSR_TO);
1590
1591 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1592 bridge->crcsr_bus);
1593}
1594
1595static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1596{
1597 int retval, i;
1598 u32 data;
1599 struct list_head *pos = NULL, *n;
1600 struct vme_bridge *ca91cx42_bridge;
1601 struct ca91cx42_driver *ca91cx42_device;
1602 struct vme_master_resource *master_image;
1603 struct vme_slave_resource *slave_image;
1604 struct vme_dma_resource *dma_ctrlr;
1605 struct vme_lm_resource *lm;
1606
1607 /* We want to support more than one of each bridge so we need to
1608 * dynamically allocate the bridge structure
1609 */
1610 ca91cx42_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1611
1612 if (ca91cx42_bridge == NULL) {
1613 dev_err(&pdev->dev, "Failed to allocate memory for device "
1614 "structure\n");
1615 retval = -ENOMEM;
1616 goto err_struct;
1617 }
1618
1619 ca91cx42_device = kzalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1620
1621 if (ca91cx42_device == NULL) {
1622 dev_err(&pdev->dev, "Failed to allocate memory for device "
1623 "structure\n");
1624 retval = -ENOMEM;
1625 goto err_driver;
1626 }
1627
1628 ca91cx42_bridge->driver_priv = ca91cx42_device;
1629
1630 /* Enable the device */
1631 retval = pci_enable_device(pdev);
1632 if (retval) {
1633 dev_err(&pdev->dev, "Unable to enable device\n");
1634 goto err_enable;
1635 }
1636
1637 /* Map Registers */
1638 retval = pci_request_regions(pdev, driver_name);
1639 if (retval) {
1640 dev_err(&pdev->dev, "Unable to reserve resources\n");
1641 goto err_resource;
1642 }
1643
1644 /* map registers in BAR 0 */
1645 ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1646 4096);
1647 if (!ca91cx42_device->base) {
1648 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1649 retval = -EIO;
1650 goto err_remap;
1651 }
1652
1653 /* Check to see if the mapping worked out */
1654 data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1655 if (data != PCI_VENDOR_ID_TUNDRA) {
1656 dev_err(&pdev->dev, "PCI_ID check failed\n");
1657 retval = -EIO;
1658 goto err_test;
1659 }
1660
1661 /* Initialize wait queues & mutual exclusion flags */
1662 init_waitqueue_head(&ca91cx42_device->dma_queue);
1663 init_waitqueue_head(&ca91cx42_device->iack_queue);
1664 mutex_init(&ca91cx42_device->vme_int);
1665 mutex_init(&ca91cx42_device->vme_rmw);
1666
1667 ca91cx42_bridge->parent = &pdev->dev;
1668 strcpy(ca91cx42_bridge->name, driver_name);
1669
1670 /* Setup IRQ */
1671 retval = ca91cx42_irq_init(ca91cx42_bridge);
1672 if (retval != 0) {
1673 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1674 goto err_irq;
1675 }
1676
1677 /* Add master windows to list */
1678 INIT_LIST_HEAD(&ca91cx42_bridge->master_resources);
1679 for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1680 master_image = kmalloc(sizeof(struct vme_master_resource),
1681 GFP_KERNEL);
1682 if (master_image == NULL) {
1683 dev_err(&pdev->dev, "Failed to allocate memory for "
1684 "master resource structure\n");
1685 retval = -ENOMEM;
1686 goto err_master;
1687 }
1688 master_image->parent = ca91cx42_bridge;
1689 spin_lock_init(&master_image->lock);
1690 master_image->locked = 0;
1691 master_image->number = i;
1692 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1693 VME_CRCSR | VME_USER1 | VME_USER2;
1694 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1695 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1696 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1697 memset(&master_image->bus_resource, 0,
1698 sizeof(struct resource));
1699 master_image->kern_base = NULL;
1700 list_add_tail(&master_image->list,
1701 &ca91cx42_bridge->master_resources);
1702 }
1703
1704 /* Add slave windows to list */
1705 INIT_LIST_HEAD(&ca91cx42_bridge->slave_resources);
1706 for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1707 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1708 GFP_KERNEL);
1709 if (slave_image == NULL) {
1710 dev_err(&pdev->dev, "Failed to allocate memory for "
1711 "slave resource structure\n");
1712 retval = -ENOMEM;
1713 goto err_slave;
1714 }
1715 slave_image->parent = ca91cx42_bridge;
1716 mutex_init(&slave_image->mtx);
1717 slave_image->locked = 0;
1718 slave_image->number = i;
1719 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1720 VME_USER2;
1721
1722 /* Only windows 0 and 4 support A16 */
1723 if (i == 0 || i == 4)
1724 slave_image->address_attr |= VME_A16;
1725
1726 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1727 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1728 list_add_tail(&slave_image->list,
1729 &ca91cx42_bridge->slave_resources);
1730 }
1731
1732 /* Add dma engines to list */
1733 INIT_LIST_HEAD(&ca91cx42_bridge->dma_resources);
1734 for (i = 0; i < CA91C142_MAX_DMA; i++) {
1735 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1736 GFP_KERNEL);
1737 if (dma_ctrlr == NULL) {
1738 dev_err(&pdev->dev, "Failed to allocate memory for "
1739 "dma resource structure\n");
1740 retval = -ENOMEM;
1741 goto err_dma;
1742 }
1743 dma_ctrlr->parent = ca91cx42_bridge;
1744 mutex_init(&dma_ctrlr->mtx);
1745 dma_ctrlr->locked = 0;
1746 dma_ctrlr->number = i;
1747 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1748 VME_DMA_MEM_TO_VME;
1749 INIT_LIST_HEAD(&dma_ctrlr->pending);
1750 INIT_LIST_HEAD(&dma_ctrlr->running);
1751 list_add_tail(&dma_ctrlr->list,
1752 &ca91cx42_bridge->dma_resources);
1753 }
1754
1755 /* Add location monitor to list */
1756 INIT_LIST_HEAD(&ca91cx42_bridge->lm_resources);
1757 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1758 if (lm == NULL) {
1759 dev_err(&pdev->dev, "Failed to allocate memory for "
1760 "location monitor resource structure\n");
1761 retval = -ENOMEM;
1762 goto err_lm;
1763 }
1764 lm->parent = ca91cx42_bridge;
1765 mutex_init(&lm->mtx);
1766 lm->locked = 0;
1767 lm->number = 1;
1768 lm->monitors = 4;
1769 list_add_tail(&lm->list, &ca91cx42_bridge->lm_resources);
1770
1771 ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1772 ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1773 ca91cx42_bridge->master_get = ca91cx42_master_get;
1774 ca91cx42_bridge->master_set = ca91cx42_master_set;
1775 ca91cx42_bridge->master_read = ca91cx42_master_read;
1776 ca91cx42_bridge->master_write = ca91cx42_master_write;
1777 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1778 ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1779 ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1780 ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1781 ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1782 ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1783 ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1784 ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1785 ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1786 ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1787 ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1788 ca91cx42_bridge->alloc_consistent = ca91cx42_alloc_consistent;
1789 ca91cx42_bridge->free_consistent = ca91cx42_free_consistent;
1790
1791 data = ioread32(ca91cx42_device->base + MISC_CTL);
1792 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1793 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1794 dev_info(&pdev->dev, "Slot ID is %d\n",
1795 ca91cx42_slot_get(ca91cx42_bridge));
1796
1797 if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
1798 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1799
1800 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1801 * ca91cx42_remove()
1802 */
1803 retval = vme_register_bridge(ca91cx42_bridge);
1804 if (retval != 0) {
1805 dev_err(&pdev->dev, "Chip Registration failed.\n");
1806 goto err_reg;
1807 }
1808
1809 pci_set_drvdata(pdev, ca91cx42_bridge);
1810
1811 return 0;
1812
1813err_reg:
1814 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1815err_lm:
1816 /* resources are stored in link list */
1817 list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
1818 lm = list_entry(pos, struct vme_lm_resource, list);
1819 list_del(pos);
1820 kfree(lm);
1821 }
1822err_dma:
1823 /* resources are stored in link list */
1824 list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
1825 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1826 list_del(pos);
1827 kfree(dma_ctrlr);
1828 }
1829err_slave:
1830 /* resources are stored in link list */
1831 list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
1832 slave_image = list_entry(pos, struct vme_slave_resource, list);
1833 list_del(pos);
1834 kfree(slave_image);
1835 }
1836err_master:
1837 /* resources are stored in link list */
1838 list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
1839 master_image = list_entry(pos, struct vme_master_resource,
1840 list);
1841 list_del(pos);
1842 kfree(master_image);
1843 }
1844
1845 ca91cx42_irq_exit(ca91cx42_device, pdev);
1846err_irq:
1847err_test:
1848 iounmap(ca91cx42_device->base);
1849err_remap:
1850 pci_release_regions(pdev);
1851err_resource:
1852 pci_disable_device(pdev);
1853err_enable:
1854 kfree(ca91cx42_device);
1855err_driver:
1856 kfree(ca91cx42_bridge);
1857err_struct:
1858 return retval;
1859
1860}
1861
1862static void ca91cx42_remove(struct pci_dev *pdev)
1863{
1864 struct list_head *pos = NULL, *n;
1865 struct vme_master_resource *master_image;
1866 struct vme_slave_resource *slave_image;
1867 struct vme_dma_resource *dma_ctrlr;
1868 struct vme_lm_resource *lm;
1869 struct ca91cx42_driver *bridge;
1870 struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1871
1872 bridge = ca91cx42_bridge->driver_priv;
1873
1874
1875 /* Turn off Ints */
1876 iowrite32(0, bridge->base + LINT_EN);
1877
1878 /* Turn off the windows */
1879 iowrite32(0x00800000, bridge->base + LSI0_CTL);
1880 iowrite32(0x00800000, bridge->base + LSI1_CTL);
1881 iowrite32(0x00800000, bridge->base + LSI2_CTL);
1882 iowrite32(0x00800000, bridge->base + LSI3_CTL);
1883 iowrite32(0x00800000, bridge->base + LSI4_CTL);
1884 iowrite32(0x00800000, bridge->base + LSI5_CTL);
1885 iowrite32(0x00800000, bridge->base + LSI6_CTL);
1886 iowrite32(0x00800000, bridge->base + LSI7_CTL);
1887 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1888 iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1889 iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1890 iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1891 iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1892 iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1893 iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1894 iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1895
1896 vme_unregister_bridge(ca91cx42_bridge);
1897
1898 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1899
1900 /* resources are stored in link list */
1901 list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
1902 lm = list_entry(pos, struct vme_lm_resource, list);
1903 list_del(pos);
1904 kfree(lm);
1905 }
1906
1907 /* resources are stored in link list */
1908 list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
1909 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1910 list_del(pos);
1911 kfree(dma_ctrlr);
1912 }
1913
1914 /* resources are stored in link list */
1915 list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
1916 slave_image = list_entry(pos, struct vme_slave_resource, list);
1917 list_del(pos);
1918 kfree(slave_image);
1919 }
1920
1921 /* resources are stored in link list */
1922 list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
1923 master_image = list_entry(pos, struct vme_master_resource,
1924 list);
1925 list_del(pos);
1926 kfree(master_image);
1927 }
1928
1929 ca91cx42_irq_exit(bridge, pdev);
1930
1931 iounmap(bridge->base);
1932
1933 pci_release_regions(pdev);
1934
1935 pci_disable_device(pdev);
1936
1937 kfree(ca91cx42_bridge);
1938}
1939
1940module_pci_driver(ca91cx42_driver);
1941
1942MODULE_PARM_DESC(geoid, "Override geographical addressing");
1943module_param(geoid, int, 0);
1944
1945MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1946MODULE_LICENSE("GPL");
diff --git a/drivers/vme/bridges/vme_ca91cx42.h b/drivers/vme/bridges/vme_ca91cx42.h
deleted file mode 100644
index 02a7c794db0..00000000000
--- a/drivers/vme/bridges/vme_ca91cx42.h
+++ /dev/null
@@ -1,583 +0,0 @@
1/*
2 * ca91c042.h
3 *
4 * Support for the Tundra Universe 1 and Universe II VME bridge chips
5 *
6 * Author: Tom Armistead
7 * Updated by Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * Further updated by Martyn Welch <martyn.welch@ge.com>
11 * Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc.
12 *
13 * Derived from ca91c042.h by Michael Wyrick
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef _CA91CX42_H
22#define _CA91CX42_H
23
24#ifndef PCI_VENDOR_ID_TUNDRA
25#define PCI_VENDOR_ID_TUNDRA 0x10e3
26#endif
27
28#ifndef PCI_DEVICE_ID_TUNDRA_CA91C142
29#define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000
30#endif
31
32/*
33 * Define the number of each that the CA91C142 supports.
34 */
35#define CA91C142_MAX_MASTER 8 /* Max Master Windows */
36#define CA91C142_MAX_SLAVE 8 /* Max Slave Windows */
37#define CA91C142_MAX_DMA 1 /* Max DMA Controllers */
38#define CA91C142_MAX_MAILBOX 4 /* Max Mail Box registers */
39
40/* Structure used to hold driver specific information */
41struct ca91cx42_driver {
42 void __iomem *base; /* Base Address of device registers */
43 wait_queue_head_t dma_queue;
44 wait_queue_head_t iack_queue;
45 wait_queue_head_t mbox_queue;
46 void (*lm_callback[4])(int); /* Called in interrupt handler */
47 void *crcsr_kernel;
48 dma_addr_t crcsr_bus;
49 struct mutex vme_rmw; /* Only one RMW cycle at a time */
50 struct mutex vme_int; /*
51 * Only one VME interrupt can be
52 * generated at a time, provide locking
53 */
54};
55
56/* See Page 2-77 in the Universe User Manual */
57struct ca91cx42_dma_descriptor {
58 unsigned int dctl; /* DMA Control */
59 unsigned int dtbc; /* Transfer Byte Count */
60 unsigned int dla; /* PCI Address */
61 unsigned int res1; /* Reserved */
62 unsigned int dva; /* Vme Address */
63 unsigned int res2; /* Reserved */
64 unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
65 unsigned int res3; /* Reserved */
66};
67
68struct ca91cx42_dma_entry {
69 struct ca91cx42_dma_descriptor descriptor;
70 struct list_head list;
71};
72
73/* Universe Register Offsets */
74/* general PCI configuration registers */
75#define CA91CX42_PCI_ID 0x000
76#define CA91CX42_PCI_CSR 0x004
77#define CA91CX42_PCI_CLASS 0x008
78#define CA91CX42_PCI_MISC0 0x00C
79#define CA91CX42_PCI_BS 0x010
80#define CA91CX42_PCI_MISC1 0x03C
81
82#define LSI0_CTL 0x0100
83#define LSI0_BS 0x0104
84#define LSI0_BD 0x0108
85#define LSI0_TO 0x010C
86
87#define LSI1_CTL 0x0114
88#define LSI1_BS 0x0118
89#define LSI1_BD 0x011C
90#define LSI1_TO 0x0120
91
92#define LSI2_CTL 0x0128
93#define LSI2_BS 0x012C
94#define LSI2_BD 0x0130
95#define LSI2_TO 0x0134
96
97#define LSI3_CTL 0x013C
98#define LSI3_BS 0x0140
99#define LSI3_BD 0x0144
100#define LSI3_TO 0x0148
101
102#define LSI4_CTL 0x01A0
103#define LSI4_BS 0x01A4
104#define LSI4_BD 0x01A8
105#define LSI4_TO 0x01AC
106
107#define LSI5_CTL 0x01B4
108#define LSI5_BS 0x01B8
109#define LSI5_BD 0x01BC
110#define LSI5_TO 0x01C0
111
112#define LSI6_CTL 0x01C8
113#define LSI6_BS 0x01CC
114#define LSI6_BD 0x01D0
115#define LSI6_TO 0x01D4
116
117#define LSI7_CTL 0x01DC
118#define LSI7_BS 0x01E0
119#define LSI7_BD 0x01E4
120#define LSI7_TO 0x01E8
121
122static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL,
123 LSI4_CTL, LSI5_CTL, LSI6_CTL, LSI7_CTL };
124
125static const int CA91CX42_LSI_BS[] = { LSI0_BS, LSI1_BS, LSI2_BS, LSI3_BS,
126 LSI4_BS, LSI5_BS, LSI6_BS, LSI7_BS };
127
128static const int CA91CX42_LSI_BD[] = { LSI0_BD, LSI1_BD, LSI2_BD, LSI3_BD,
129 LSI4_BD, LSI5_BD, LSI6_BD, LSI7_BD };
130
131static const int CA91CX42_LSI_TO[] = { LSI0_TO, LSI1_TO, LSI2_TO, LSI3_TO,
132 LSI4_TO, LSI5_TO, LSI6_TO, LSI7_TO };
133
134#define SCYC_CTL 0x0170
135#define SCYC_ADDR 0x0174
136#define SCYC_EN 0x0178
137#define SCYC_CMP 0x017C
138#define SCYC_SWP 0x0180
139#define LMISC 0x0184
140#define SLSI 0x0188
141#define L_CMDERR 0x018C
142#define LAERR 0x0190
143
144#define DCTL 0x0200
145#define DTBC 0x0204
146#define DLA 0x0208
147#define DVA 0x0210
148#define DCPP 0x0218
149#define DGCS 0x0220
150#define D_LLUE 0x0224
151
152#define LINT_EN 0x0300
153#define LINT_STAT 0x0304
154#define LINT_MAP0 0x0308
155#define LINT_MAP1 0x030C
156#define VINT_EN 0x0310
157#define VINT_STAT 0x0314
158#define VINT_MAP0 0x0318
159#define VINT_MAP1 0x031C
160#define STATID 0x0320
161
162#define V1_STATID 0x0324
163#define V2_STATID 0x0328
164#define V3_STATID 0x032C
165#define V4_STATID 0x0330
166#define V5_STATID 0x0334
167#define V6_STATID 0x0338
168#define V7_STATID 0x033C
169
170static const int CA91CX42_V_STATID[8] = { 0, V1_STATID, V2_STATID, V3_STATID,
171 V4_STATID, V5_STATID, V6_STATID,
172 V7_STATID };
173
174#define LINT_MAP2 0x0340
175#define VINT_MAP2 0x0344
176
177#define MBOX0 0x0348
178#define MBOX1 0x034C
179#define MBOX2 0x0350
180#define MBOX3 0x0354
181#define SEMA0 0x0358
182#define SEMA1 0x035C
183
184#define MAST_CTL 0x0400
185#define MISC_CTL 0x0404
186#define MISC_STAT 0x0408
187#define USER_AM 0x040C
188
189#define VSI0_CTL 0x0F00
190#define VSI0_BS 0x0F04
191#define VSI0_BD 0x0F08
192#define VSI0_TO 0x0F0C
193
194#define VSI1_CTL 0x0F14
195#define VSI1_BS 0x0F18
196#define VSI1_BD 0x0F1C
197#define VSI1_TO 0x0F20
198
199#define VSI2_CTL 0x0F28
200#define VSI2_BS 0x0F2C
201#define VSI2_BD 0x0F30
202#define VSI2_TO 0x0F34
203
204#define VSI3_CTL 0x0F3C
205#define VSI3_BS 0x0F40
206#define VSI3_BD 0x0F44
207#define VSI3_TO 0x0F48
208
209#define LM_CTL 0x0F64
210#define LM_BS 0x0F68
211
212#define VRAI_CTL 0x0F70
213
214#define VRAI_BS 0x0F74
215#define VCSR_CTL 0x0F80
216#define VCSR_TO 0x0F84
217#define V_AMERR 0x0F88
218#define VAERR 0x0F8C
219
220#define VSI4_CTL 0x0F90
221#define VSI4_BS 0x0F94
222#define VSI4_BD 0x0F98
223#define VSI4_TO 0x0F9C
224
225#define VSI5_CTL 0x0FA4
226#define VSI5_BS 0x0FA8
227#define VSI5_BD 0x0FAC
228#define VSI5_TO 0x0FB0
229
230#define VSI6_CTL 0x0FB8
231#define VSI6_BS 0x0FBC
232#define VSI6_BD 0x0FC0
233#define VSI6_TO 0x0FC4
234
235#define VSI7_CTL 0x0FCC
236#define VSI7_BS 0x0FD0
237#define VSI7_BD 0x0FD4
238#define VSI7_TO 0x0FD8
239
240static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL,
241 VSI4_CTL, VSI5_CTL, VSI6_CTL, VSI7_CTL };
242
243static const int CA91CX42_VSI_BS[] = { VSI0_BS, VSI1_BS, VSI2_BS, VSI3_BS,
244 VSI4_BS, VSI5_BS, VSI6_BS, VSI7_BS };
245
246static const int CA91CX42_VSI_BD[] = { VSI0_BD, VSI1_BD, VSI2_BD, VSI3_BD,
247 VSI4_BD, VSI5_BD, VSI6_BD, VSI7_BD };
248
249static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO,
250 VSI4_TO, VSI5_TO, VSI6_TO, VSI7_TO };
251
252#define VCSR_CLR 0x0FF4
253#define VCSR_SET 0x0FF8
254#define VCSR_BS 0x0FFC
255
256/*
257 * PCI Class Register
258 * offset 008
259 */
260#define CA91CX42_BM_PCI_CLASS_BASE 0xFF000000
261#define CA91CX42_OF_PCI_CLASS_BASE 24
262#define CA91CX42_BM_PCI_CLASS_SUB 0x00FF0000
263#define CA91CX42_OF_PCI_CLASS_SUB 16
264#define CA91CX42_BM_PCI_CLASS_PROG 0x0000FF00
265#define CA91CX42_OF_PCI_CLASS_PROG 8
266#define CA91CX42_BM_PCI_CLASS_RID 0x000000FF
267#define CA91CX42_OF_PCI_CLASS_RID 0
268
269#define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_I 0
270#define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_II 1
271
272/*
273 * PCI Misc Register
274 * offset 00C
275 */
276#define CA91CX42_BM_PCI_MISC0_BISTC 0x80000000
277#define CA91CX42_BM_PCI_MISC0_SBIST 0x60000000
278#define CA91CX42_BM_PCI_MISC0_CCODE 0x0F000000
279#define CA91CX42_BM_PCI_MISC0_MFUNCT 0x00800000
280#define CA91CX42_BM_PCI_MISC0_LAYOUT 0x007F0000
281#define CA91CX42_BM_PCI_MISC0_LTIMER 0x0000FF00
282#define CA91CX42_OF_PCI_MISC0_LTIMER 8
283
284
285/*
286 * LSI Control Register
287 * offset 100
288 */
289#define CA91CX42_LSI_CTL_EN (1<<31)
290#define CA91CX42_LSI_CTL_PWEN (1<<30)
291
292#define CA91CX42_LSI_CTL_VDW_M (3<<22)
293#define CA91CX42_LSI_CTL_VDW_D8 0
294#define CA91CX42_LSI_CTL_VDW_D16 (1<<22)
295#define CA91CX42_LSI_CTL_VDW_D32 (1<<23)
296#define CA91CX42_LSI_CTL_VDW_D64 (3<<22)
297
298#define CA91CX42_LSI_CTL_VAS_M (7<<16)
299#define CA91CX42_LSI_CTL_VAS_A16 0
300#define CA91CX42_LSI_CTL_VAS_A24 (1<<16)
301#define CA91CX42_LSI_CTL_VAS_A32 (1<<17)
302#define CA91CX42_LSI_CTL_VAS_CRCSR (5<<16)
303#define CA91CX42_LSI_CTL_VAS_USER1 (3<<17)
304#define CA91CX42_LSI_CTL_VAS_USER2 (7<<16)
305
306#define CA91CX42_LSI_CTL_PGM_M (1<<14)
307#define CA91CX42_LSI_CTL_PGM_DATA 0
308#define CA91CX42_LSI_CTL_PGM_PGM (1<<14)
309
310#define CA91CX42_LSI_CTL_SUPER_M (1<<12)
311#define CA91CX42_LSI_CTL_SUPER_NPRIV 0
312#define CA91CX42_LSI_CTL_SUPER_SUPR (1<<12)
313
314#define CA91CX42_LSI_CTL_VCT_M (1<<8)
315#define CA91CX42_LSI_CTL_VCT_BLT (1<<8)
316#define CA91CX42_LSI_CTL_VCT_MBLT (1<<8)
317#define CA91CX42_LSI_CTL_LAS (1<<0)
318
319/*
320 * SCYC_CTL Register
321 * offset 178
322 */
323#define CA91CX42_SCYC_CTL_LAS_PCIMEM 0
324#define CA91CX42_SCYC_CTL_LAS_PCIIO (1<<2)
325
326#define CA91CX42_SCYC_CTL_CYC_M (3<<0)
327#define CA91CX42_SCYC_CTL_CYC_RMW (1<<0)
328#define CA91CX42_SCYC_CTL_CYC_ADOH (1<<1)
329
330/*
331 * LMISC Register
332 * offset 184
333 */
334#define CA91CX42_BM_LMISC_CRT 0xF0000000
335#define CA91CX42_OF_LMISC_CRT 28
336#define CA91CX42_BM_LMISC_CWT 0x0F000000
337#define CA91CX42_OF_LMISC_CWT 24
338
339/*
340 * SLSI Register
341 * offset 188
342 */
343#define CA91CX42_BM_SLSI_EN 0x80000000
344#define CA91CX42_BM_SLSI_PWEN 0x40000000
345#define CA91CX42_BM_SLSI_VDW 0x00F00000
346#define CA91CX42_OF_SLSI_VDW 20
347#define CA91CX42_BM_SLSI_PGM 0x0000F000
348#define CA91CX42_OF_SLSI_PGM 12
349#define CA91CX42_BM_SLSI_SUPER 0x00000F00
350#define CA91CX42_OF_SLSI_SUPER 8
351#define CA91CX42_BM_SLSI_BS 0x000000F6
352#define CA91CX42_OF_SLSI_BS 2
353#define CA91CX42_BM_SLSI_LAS 0x00000003
354#define CA91CX42_OF_SLSI_LAS 0
355#define CA91CX42_BM_SLSI_RESERVED 0x3F0F0000
356
357/*
358 * DCTL Register
359 * offset 200
360 */
361#define CA91CX42_DCTL_L2V (1<<31)
362#define CA91CX42_DCTL_VDW_M (3<<22)
363#define CA91CX42_DCTL_VDW_M (3<<22)
364#define CA91CX42_DCTL_VDW_D8 0
365#define CA91CX42_DCTL_VDW_D16 (1<<22)
366#define CA91CX42_DCTL_VDW_D32 (1<<23)
367#define CA91CX42_DCTL_VDW_D64 (3<<22)
368
369#define CA91CX42_DCTL_VAS_M (7<<16)
370#define CA91CX42_DCTL_VAS_A16 0
371#define CA91CX42_DCTL_VAS_A24 (1<<16)
372#define CA91CX42_DCTL_VAS_A32 (1<<17)
373#define CA91CX42_DCTL_VAS_USER1 (3<<17)
374#define CA91CX42_DCTL_VAS_USER2 (7<<16)
375
376#define CA91CX42_DCTL_PGM_M (1<<14)
377#define CA91CX42_DCTL_PGM_DATA 0
378#define CA91CX42_DCTL_PGM_PGM (1<<14)
379
380#define CA91CX42_DCTL_SUPER_M (1<<12)
381#define CA91CX42_DCTL_SUPER_NPRIV 0
382#define CA91CX42_DCTL_SUPER_SUPR (1<<12)
383
384#define CA91CX42_DCTL_VCT_M (1<<8)
385#define CA91CX42_DCTL_VCT_BLT (1<<8)
386#define CA91CX42_DCTL_LD64EN (1<<7)
387
388/*
389 * DCPP Register
390 * offset 218
391 */
392#define CA91CX42_DCPP_M 0xf
393#define CA91CX42_DCPP_NULL (1<<0)
394
395/*
396 * DMA General Control/Status Register (DGCS)
397 * offset 220
398 */
399#define CA91CX42_DGCS_GO (1<<31)
400#define CA91CX42_DGCS_STOP_REQ (1<<30)
401#define CA91CX42_DGCS_HALT_REQ (1<<29)
402#define CA91CX42_DGCS_CHAIN (1<<27)
403
404#define CA91CX42_DGCS_VON_M (7<<20)
405
406#define CA91CX42_DGCS_VOFF_M (0xf<<16)
407
408#define CA91CX42_DGCS_ACT (1<<15)
409#define CA91CX42_DGCS_STOP (1<<14)
410#define CA91CX42_DGCS_HALT (1<<13)
411#define CA91CX42_DGCS_DONE (1<<11)
412#define CA91CX42_DGCS_LERR (1<<10)
413#define CA91CX42_DGCS_VERR (1<<9)
414#define CA91CX42_DGCS_PERR (1<<8)
415#define CA91CX42_DGCS_INT_STOP (1<<6)
416#define CA91CX42_DGCS_INT_HALT (1<<5)
417#define CA91CX42_DGCS_INT_DONE (1<<3)
418#define CA91CX42_DGCS_INT_LERR (1<<2)
419#define CA91CX42_DGCS_INT_VERR (1<<1)
420#define CA91CX42_DGCS_INT_PERR (1<<0)
421
422/*
423 * PCI Interrupt Enable Register
424 * offset 300
425 */
426#define CA91CX42_LINT_LM3 0x00800000
427#define CA91CX42_LINT_LM2 0x00400000
428#define CA91CX42_LINT_LM1 0x00200000
429#define CA91CX42_LINT_LM0 0x00100000
430#define CA91CX42_LINT_MBOX3 0x00080000
431#define CA91CX42_LINT_MBOX2 0x00040000
432#define CA91CX42_LINT_MBOX1 0x00020000
433#define CA91CX42_LINT_MBOX0 0x00010000
434#define CA91CX42_LINT_ACFAIL 0x00008000
435#define CA91CX42_LINT_SYSFAIL 0x00004000
436#define CA91CX42_LINT_SW_INT 0x00002000
437#define CA91CX42_LINT_SW_IACK 0x00001000
438
439#define CA91CX42_LINT_VERR 0x00000400
440#define CA91CX42_LINT_LERR 0x00000200
441#define CA91CX42_LINT_DMA 0x00000100
442#define CA91CX42_LINT_VIRQ7 0x00000080
443#define CA91CX42_LINT_VIRQ6 0x00000040
444#define CA91CX42_LINT_VIRQ5 0x00000020
445#define CA91CX42_LINT_VIRQ4 0x00000010
446#define CA91CX42_LINT_VIRQ3 0x00000008
447#define CA91CX42_LINT_VIRQ2 0x00000004
448#define CA91CX42_LINT_VIRQ1 0x00000002
449#define CA91CX42_LINT_VOWN 0x00000001
450
451static const int CA91CX42_LINT_VIRQ[] = { 0, CA91CX42_LINT_VIRQ1,
452 CA91CX42_LINT_VIRQ2, CA91CX42_LINT_VIRQ3,
453 CA91CX42_LINT_VIRQ4, CA91CX42_LINT_VIRQ5,
454 CA91CX42_LINT_VIRQ6, CA91CX42_LINT_VIRQ7 };
455
456#define CA91CX42_LINT_MBOX 0x000F0000
457
458static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1,
459 CA91CX42_LINT_LM2, CA91CX42_LINT_LM3 };
460
461/*
462 * MAST_CTL Register
463 * offset 400
464 */
465#define CA91CX42_BM_MAST_CTL_MAXRTRY 0xF0000000
466#define CA91CX42_OF_MAST_CTL_MAXRTRY 28
467#define CA91CX42_BM_MAST_CTL_PWON 0x0F000000
468#define CA91CX42_OF_MAST_CTL_PWON 24
469#define CA91CX42_BM_MAST_CTL_VRL 0x00C00000
470#define CA91CX42_OF_MAST_CTL_VRL 22
471#define CA91CX42_BM_MAST_CTL_VRM 0x00200000
472#define CA91CX42_BM_MAST_CTL_VREL 0x00100000
473#define CA91CX42_BM_MAST_CTL_VOWN 0x00080000
474#define CA91CX42_BM_MAST_CTL_VOWN_ACK 0x00040000
475#define CA91CX42_BM_MAST_CTL_PABS 0x00001000
476#define CA91CX42_BM_MAST_CTL_BUS_NO 0x0000000F
477#define CA91CX42_OF_MAST_CTL_BUS_NO 0
478
479/*
480 * MISC_CTL Register
481 * offset 404
482 */
483#define CA91CX42_MISC_CTL_VBTO 0xF0000000
484#define CA91CX42_MISC_CTL_VARB 0x04000000
485#define CA91CX42_MISC_CTL_VARBTO 0x03000000
486#define CA91CX42_MISC_CTL_SW_LRST 0x00800000
487#define CA91CX42_MISC_CTL_SW_SRST 0x00400000
488#define CA91CX42_MISC_CTL_BI 0x00100000
489#define CA91CX42_MISC_CTL_ENGBI 0x00080000
490#define CA91CX42_MISC_CTL_RESCIND 0x00040000
491#define CA91CX42_MISC_CTL_SYSCON 0x00020000
492#define CA91CX42_MISC_CTL_V64AUTO 0x00010000
493#define CA91CX42_MISC_CTL_RESERVED 0x0820FFFF
494
495#define CA91CX42_OF_MISC_CTL_VARBTO 24
496#define CA91CX42_OF_MISC_CTL_VBTO 28
497
498/*
499 * MISC_STAT Register
500 * offset 408
501 */
502#define CA91CX42_BM_MISC_STAT_ENDIAN 0x80000000
503#define CA91CX42_BM_MISC_STAT_LCLSIZE 0x40000000
504#define CA91CX42_BM_MISC_STAT_DY4AUTO 0x08000000
505#define CA91CX42_BM_MISC_STAT_MYBBSY 0x00200000
506#define CA91CX42_BM_MISC_STAT_DY4DONE 0x00080000
507#define CA91CX42_BM_MISC_STAT_TXFE 0x00040000
508#define CA91CX42_BM_MISC_STAT_RXFE 0x00020000
509#define CA91CX42_BM_MISC_STAT_DY4AUTOID 0x0000FF00
510#define CA91CX42_OF_MISC_STAT_DY4AUTOID 8
511
512/*
513 * VSI Control Register
514 * offset F00
515 */
516#define CA91CX42_VSI_CTL_EN (1<<31)
517#define CA91CX42_VSI_CTL_PWEN (1<<30)
518#define CA91CX42_VSI_CTL_PREN (1<<29)
519
520#define CA91CX42_VSI_CTL_PGM_M (3<<22)
521#define CA91CX42_VSI_CTL_PGM_DATA (1<<22)
522#define CA91CX42_VSI_CTL_PGM_PGM (1<<23)
523
524#define CA91CX42_VSI_CTL_SUPER_M (3<<20)
525#define CA91CX42_VSI_CTL_SUPER_NPRIV (1<<20)
526#define CA91CX42_VSI_CTL_SUPER_SUPR (1<<21)
527
528#define CA91CX42_VSI_CTL_VAS_M (7<<16)
529#define CA91CX42_VSI_CTL_VAS_A16 0
530#define CA91CX42_VSI_CTL_VAS_A24 (1<<16)
531#define CA91CX42_VSI_CTL_VAS_A32 (1<<17)
532#define CA91CX42_VSI_CTL_VAS_USER1 (3<<17)
533#define CA91CX42_VSI_CTL_VAS_USER2 (7<<16)
534
535#define CA91CX42_VSI_CTL_LD64EN (1<<7)
536#define CA91CX42_VSI_CTL_LLRMW (1<<6)
537
538#define CA91CX42_VSI_CTL_LAS_M (3<<0)
539#define CA91CX42_VSI_CTL_LAS_PCI_MS 0
540#define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0)
541#define CA91CX42_VSI_CTL_LAS_PCI_CONF (1<<1)
542
543/* LM_CTL Register
544 * offset F64
545 */
546#define CA91CX42_LM_CTL_EN (1<<31)
547#define CA91CX42_LM_CTL_PGM (1<<23)
548#define CA91CX42_LM_CTL_DATA (1<<22)
549#define CA91CX42_LM_CTL_SUPR (1<<21)
550#define CA91CX42_LM_CTL_NPRIV (1<<20)
551#define CA91CX42_LM_CTL_AS_M (5<<16)
552#define CA91CX42_LM_CTL_AS_A16 0
553#define CA91CX42_LM_CTL_AS_A24 (1<<16)
554#define CA91CX42_LM_CTL_AS_A32 (1<<17)
555
556/*
557 * VRAI_CTL Register
558 * offset F70
559 */
560#define CA91CX42_BM_VRAI_CTL_EN 0x80000000
561#define CA91CX42_BM_VRAI_CTL_PGM 0x00C00000
562#define CA91CX42_OF_VRAI_CTL_PGM 22
563#define CA91CX42_BM_VRAI_CTL_SUPER 0x00300000
564#define CA91CX42_OF_VRAI_CTL_SUPER 20
565#define CA91CX42_BM_VRAI_CTL_VAS 0x00030000
566#define CA91CX42_OF_VRAI_CTL_VAS 16
567
568/* VCSR_CTL Register
569 * offset F80
570 */
571#define CA91CX42_VCSR_CTL_EN (1<<31)
572
573#define CA91CX42_VCSR_CTL_LAS_M (3<<0)
574#define CA91CX42_VCSR_CTL_LAS_PCI_MS 0
575#define CA91CX42_VCSR_CTL_LAS_PCI_IO (1<<0)
576#define CA91CX42_VCSR_CTL_LAS_PCI_CONF (1<<1)
577
578/* VCSR_BS Register
579 * offset FFC
580 */
581#define CA91CX42_VCSR_BS_SLOT_M (0x1F<<27)
582
583#endif /* _CA91CX42_H */
diff --git a/drivers/vme/bridges/vme_tsi148.c b/drivers/vme/bridges/vme_tsi148.c
deleted file mode 100644
index 9c1aa4dc39c..00000000000
--- a/drivers/vme/bridges/vme_tsi148.c
+++ /dev/null
@@ -1,2759 +0,0 @@
1/*
2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
3 *
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/mm.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/proc_fs.h>
22#include <linux/pci.h>
23#include <linux/poll.h>
24#include <linux/dma-mapping.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/time.h>
30#include <linux/io.h>
31#include <linux/uaccess.h>
32#include <linux/byteorder/generic.h>
33#include <linux/vme.h>
34
35#include "../vme_bridge.h"
36#include "vme_tsi148.h"
37
38static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
39static void tsi148_remove(struct pci_dev *);
40
41
42/* Module parameter */
43static bool err_chk;
44static int geoid;
45
46static const char driver_name[] = "vme_tsi148";
47
48static DEFINE_PCI_DEVICE_TABLE(tsi148_ids) = {
49 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
50 { },
51};
52
53static struct pci_driver tsi148_driver = {
54 .name = driver_name,
55 .id_table = tsi148_ids,
56 .probe = tsi148_probe,
57 .remove = tsi148_remove,
58};
59
60static void reg_join(unsigned int high, unsigned int low,
61 unsigned long long *variable)
62{
63 *variable = (unsigned long long)high << 32;
64 *variable |= (unsigned long long)low;
65}
66
67static void reg_split(unsigned long long variable, unsigned int *high,
68 unsigned int *low)
69{
70 *low = (unsigned int)variable & 0xFFFFFFFF;
71 *high = (unsigned int)(variable >> 32);
72}
73
74/*
75 * Wakes up DMA queue.
76 */
77static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
78 int channel_mask)
79{
80 u32 serviced = 0;
81
82 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
83 wake_up(&bridge->dma_queue[0]);
84 serviced |= TSI148_LCSR_INTC_DMA0C;
85 }
86 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
87 wake_up(&bridge->dma_queue[1]);
88 serviced |= TSI148_LCSR_INTC_DMA1C;
89 }
90
91 return serviced;
92}
93
94/*
95 * Wake up location monitor queue
96 */
97static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
98{
99 int i;
100 u32 serviced = 0;
101
102 for (i = 0; i < 4; i++) {
103 if (stat & TSI148_LCSR_INTS_LMS[i]) {
104 /* We only enable interrupts if the callback is set */
105 bridge->lm_callback[i](i);
106 serviced |= TSI148_LCSR_INTC_LMC[i];
107 }
108 }
109
110 return serviced;
111}
112
113/*
114 * Wake up mail box queue.
115 *
116 * XXX This functionality is not exposed up though API.
117 */
118static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
119{
120 int i;
121 u32 val;
122 u32 serviced = 0;
123 struct tsi148_driver *bridge;
124
125 bridge = tsi148_bridge->driver_priv;
126
127 for (i = 0; i < 4; i++) {
128 if (stat & TSI148_LCSR_INTS_MBS[i]) {
129 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
130 dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
131 ": 0x%x\n", i, val);
132 serviced |= TSI148_LCSR_INTC_MBC[i];
133 }
134 }
135
136 return serviced;
137}
138
139/*
140 * Display error & status message when PERR (PCI) exception interrupt occurs.
141 */
142static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
143{
144 struct tsi148_driver *bridge;
145
146 bridge = tsi148_bridge->driver_priv;
147
148 dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
149 "attributes: %08x\n",
150 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
151 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
152 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
153
154 dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
155 "completion reg: %08x\n",
156 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
157 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
158
159 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
160
161 return TSI148_LCSR_INTC_PERRC;
162}
163
164/*
165 * Save address and status when VME error interrupt occurs.
166 */
167static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
168{
169 unsigned int error_addr_high, error_addr_low;
170 unsigned long long error_addr;
171 u32 error_attrib;
172 struct vme_bus_error *error;
173 struct tsi148_driver *bridge;
174
175 bridge = tsi148_bridge->driver_priv;
176
177 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
178 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
179 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
180
181 reg_join(error_addr_high, error_addr_low, &error_addr);
182
183 /* Check for exception register overflow (we have lost error data) */
184 if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
185 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
186 "Occurred\n");
187 }
188
189 error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
190 if (error) {
191 error->address = error_addr;
192 error->attributes = error_attrib;
193 list_add_tail(&error->list, &tsi148_bridge->vme_errors);
194 } else {
195 dev_err(tsi148_bridge->parent, "Unable to alloc memory for "
196 "VMEbus Error reporting\n");
197 dev_err(tsi148_bridge->parent, "VME Bus Error at address: "
198 "0x%llx, attributes: %08x\n", error_addr, error_attrib);
199 }
200
201 /* Clear Status */
202 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
203
204 return TSI148_LCSR_INTC_VERRC;
205}
206
207/*
208 * Wake up IACK queue.
209 */
210static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
211{
212 wake_up(&bridge->iack_queue);
213
214 return TSI148_LCSR_INTC_IACKC;
215}
216
217/*
218 * Calling VME bus interrupt callback if provided.
219 */
220static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
221 u32 stat)
222{
223 int vec, i, serviced = 0;
224 struct tsi148_driver *bridge;
225
226 bridge = tsi148_bridge->driver_priv;
227
228 for (i = 7; i > 0; i--) {
229 if (stat & (1 << i)) {
230 /*
231 * Note: Even though the registers are defined as
232 * 32-bits in the spec, we only want to issue 8-bit
233 * IACK cycles on the bus, read from offset 3.
234 */
235 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
236
237 vme_irq_handler(tsi148_bridge, i, vec);
238
239 serviced |= (1 << i);
240 }
241 }
242
243 return serviced;
244}
245
246/*
247 * Top level interrupt handler. Clears appropriate interrupt status bits and
248 * then calls appropriate sub handler(s).
249 */
250static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
251{
252 u32 stat, enable, serviced = 0;
253 struct vme_bridge *tsi148_bridge;
254 struct tsi148_driver *bridge;
255
256 tsi148_bridge = ptr;
257
258 bridge = tsi148_bridge->driver_priv;
259
260 /* Determine which interrupts are unmasked and set */
261 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
262 stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
263
264 /* Only look at unmasked interrupts */
265 stat &= enable;
266
267 if (unlikely(!stat))
268 return IRQ_NONE;
269
270 /* Call subhandlers as appropriate */
271 /* DMA irqs */
272 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
273 serviced |= tsi148_DMA_irqhandler(bridge, stat);
274
275 /* Location monitor irqs */
276 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
277 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
278 serviced |= tsi148_LM_irqhandler(bridge, stat);
279
280 /* Mail box irqs */
281 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
282 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
283 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
284
285 /* PCI bus error */
286 if (stat & TSI148_LCSR_INTS_PERRS)
287 serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
288
289 /* VME bus error */
290 if (stat & TSI148_LCSR_INTS_VERRS)
291 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
292
293 /* IACK irq */
294 if (stat & TSI148_LCSR_INTS_IACKS)
295 serviced |= tsi148_IACK_irqhandler(bridge);
296
297 /* VME bus irqs */
298 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
299 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
300 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
301 TSI148_LCSR_INTS_IRQ1S))
302 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
303
304 /* Clear serviced interrupts */
305 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
306
307 return IRQ_HANDLED;
308}
309
310static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
311{
312 int result;
313 unsigned int tmp;
314 struct pci_dev *pdev;
315 struct tsi148_driver *bridge;
316
317 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
318
319 bridge = tsi148_bridge->driver_priv;
320
321 /* Initialise list for VME bus errors */
322 INIT_LIST_HEAD(&tsi148_bridge->vme_errors);
323
324 mutex_init(&tsi148_bridge->irq_mtx);
325
326 result = request_irq(pdev->irq,
327 tsi148_irqhandler,
328 IRQF_SHARED,
329 driver_name, tsi148_bridge);
330 if (result) {
331 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
332 "vector %02X\n", pdev->irq);
333 return result;
334 }
335
336 /* Enable and unmask interrupts */
337 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
338 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
339 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
340 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
341 TSI148_LCSR_INTEO_IACKEO;
342
343 /* This leaves the following interrupts masked.
344 * TSI148_LCSR_INTEO_VIEEO
345 * TSI148_LCSR_INTEO_SYSFLEO
346 * TSI148_LCSR_INTEO_ACFLEO
347 */
348
349 /* Don't enable Location Monitor interrupts here - they will be
350 * enabled when the location monitors are properly configured and
351 * a callback has been attached.
352 * TSI148_LCSR_INTEO_LM0EO
353 * TSI148_LCSR_INTEO_LM1EO
354 * TSI148_LCSR_INTEO_LM2EO
355 * TSI148_LCSR_INTEO_LM3EO
356 */
357
358 /* Don't enable VME interrupts until we add a handler, else the board
359 * will respond to it and we don't want that unless it knows how to
360 * properly deal with it.
361 * TSI148_LCSR_INTEO_IRQ7EO
362 * TSI148_LCSR_INTEO_IRQ6EO
363 * TSI148_LCSR_INTEO_IRQ5EO
364 * TSI148_LCSR_INTEO_IRQ4EO
365 * TSI148_LCSR_INTEO_IRQ3EO
366 * TSI148_LCSR_INTEO_IRQ2EO
367 * TSI148_LCSR_INTEO_IRQ1EO
368 */
369
370 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
371 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
372
373 return 0;
374}
375
376static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
377 struct pci_dev *pdev)
378{
379 struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
380
381 /* Turn off interrupts */
382 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
383 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
384
385 /* Clear all interrupts */
386 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
387
388 /* Detach interrupt handler */
389 free_irq(pdev->irq, tsi148_bridge);
390}
391
392/*
393 * Check to see if an IACk has been received, return true (1) or false (0).
394 */
395static int tsi148_iack_received(struct tsi148_driver *bridge)
396{
397 u32 tmp;
398
399 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
400
401 if (tmp & TSI148_LCSR_VICR_IRQS)
402 return 0;
403 else
404 return 1;
405}
406
407/*
408 * Configure VME interrupt
409 */
410static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
411 int state, int sync)
412{
413 struct pci_dev *pdev;
414 u32 tmp;
415 struct tsi148_driver *bridge;
416
417 bridge = tsi148_bridge->driver_priv;
418
419 /* We need to do the ordering differently for enabling and disabling */
420 if (state == 0) {
421 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
422 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
423 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
424
425 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
426 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
427 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
428
429 if (sync != 0) {
430 pdev = container_of(tsi148_bridge->parent,
431 struct pci_dev, dev);
432
433 synchronize_irq(pdev->irq);
434 }
435 } else {
436 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
437 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
438 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
439
440 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
441 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
442 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
443 }
444}
445
446/*
447 * Generate a VME bus interrupt at the requested level & vector. Wait for
448 * interrupt to be acked.
449 */
450static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
451 int statid)
452{
453 u32 tmp;
454 struct tsi148_driver *bridge;
455
456 bridge = tsi148_bridge->driver_priv;
457
458 mutex_lock(&bridge->vme_int);
459
460 /* Read VICR register */
461 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
462
463 /* Set Status/ID */
464 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
465 (statid & TSI148_LCSR_VICR_STID_M);
466 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
467
468 /* Assert VMEbus IRQ */
469 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
470 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
471
472 /* XXX Consider implementing a timeout? */
473 wait_event_interruptible(bridge->iack_queue,
474 tsi148_iack_received(bridge));
475
476 mutex_unlock(&bridge->vme_int);
477
478 return 0;
479}
480
481/*
482 * Find the first error in this address range
483 */
484static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
485 u32 aspace, unsigned long long address, size_t count)
486{
487 struct list_head *err_pos;
488 struct vme_bus_error *vme_err, *valid = NULL;
489 unsigned long long bound;
490
491 bound = address + count;
492
493 /*
494 * XXX We are currently not looking at the address space when parsing
495 * for errors. This is because parsing the Address Modifier Codes
496 * is going to be quite resource intensive to do properly. We
497 * should be OK just looking at the addresses and this is certainly
498 * much better than what we had before.
499 */
500 err_pos = NULL;
501 /* Iterate through errors */
502 list_for_each(err_pos, &tsi148_bridge->vme_errors) {
503 vme_err = list_entry(err_pos, struct vme_bus_error, list);
504 if ((vme_err->address >= address) &&
505 (vme_err->address < bound)) {
506
507 valid = vme_err;
508 break;
509 }
510 }
511
512 return valid;
513}
514
515/*
516 * Clear errors in the provided address range.
517 */
518static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
519 u32 aspace, unsigned long long address, size_t count)
520{
521 struct list_head *err_pos, *temp;
522 struct vme_bus_error *vme_err;
523 unsigned long long bound;
524
525 bound = address + count;
526
527 /*
528 * XXX We are currently not looking at the address space when parsing
529 * for errors. This is because parsing the Address Modifier Codes
530 * is going to be quite resource intensive to do properly. We
531 * should be OK just looking at the addresses and this is certainly
532 * much better than what we had before.
533 */
534 err_pos = NULL;
535 /* Iterate through errors */
536 list_for_each_safe(err_pos, temp, &tsi148_bridge->vme_errors) {
537 vme_err = list_entry(err_pos, struct vme_bus_error, list);
538
539 if ((vme_err->address >= address) &&
540 (vme_err->address < bound)) {
541
542 list_del(err_pos);
543 kfree(vme_err);
544 }
545 }
546}
547
548/*
549 * Initialize a slave window with the requested attributes.
550 */
551static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
552 unsigned long long vme_base, unsigned long long size,
553 dma_addr_t pci_base, u32 aspace, u32 cycle)
554{
555 unsigned int i, addr = 0, granularity = 0;
556 unsigned int temp_ctl = 0;
557 unsigned int vme_base_low, vme_base_high;
558 unsigned int vme_bound_low, vme_bound_high;
559 unsigned int pci_offset_low, pci_offset_high;
560 unsigned long long vme_bound, pci_offset;
561 struct vme_bridge *tsi148_bridge;
562 struct tsi148_driver *bridge;
563
564 tsi148_bridge = image->parent;
565 bridge = tsi148_bridge->driver_priv;
566
567 i = image->number;
568
569 switch (aspace) {
570 case VME_A16:
571 granularity = 0x10;
572 addr |= TSI148_LCSR_ITAT_AS_A16;
573 break;
574 case VME_A24:
575 granularity = 0x1000;
576 addr |= TSI148_LCSR_ITAT_AS_A24;
577 break;
578 case VME_A32:
579 granularity = 0x10000;
580 addr |= TSI148_LCSR_ITAT_AS_A32;
581 break;
582 case VME_A64:
583 granularity = 0x10000;
584 addr |= TSI148_LCSR_ITAT_AS_A64;
585 break;
586 case VME_CRCSR:
587 case VME_USER1:
588 case VME_USER2:
589 case VME_USER3:
590 case VME_USER4:
591 default:
592 dev_err(tsi148_bridge->parent, "Invalid address space\n");
593 return -EINVAL;
594 break;
595 }
596
597 /* Convert 64-bit variables to 2x 32-bit variables */
598 reg_split(vme_base, &vme_base_high, &vme_base_low);
599
600 /*
601 * Bound address is a valid address for the window, adjust
602 * accordingly
603 */
604 vme_bound = vme_base + size - granularity;
605 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
606 pci_offset = (unsigned long long)pci_base - vme_base;
607 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
608
609 if (vme_base_low & (granularity - 1)) {
610 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
611 return -EINVAL;
612 }
613 if (vme_bound_low & (granularity - 1)) {
614 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
615 return -EINVAL;
616 }
617 if (pci_offset_low & (granularity - 1)) {
618 dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
619 "alignment\n");
620 return -EINVAL;
621 }
622
623 /* Disable while we are mucking around */
624 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
625 TSI148_LCSR_OFFSET_ITAT);
626 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
627 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
628 TSI148_LCSR_OFFSET_ITAT);
629
630 /* Setup mapping */
631 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
632 TSI148_LCSR_OFFSET_ITSAU);
633 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
634 TSI148_LCSR_OFFSET_ITSAL);
635 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
636 TSI148_LCSR_OFFSET_ITEAU);
637 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
638 TSI148_LCSR_OFFSET_ITEAL);
639 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
640 TSI148_LCSR_OFFSET_ITOFU);
641 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
642 TSI148_LCSR_OFFSET_ITOFL);
643
644 /* Setup 2eSST speeds */
645 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
646 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
647 case VME_2eSST160:
648 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
649 break;
650 case VME_2eSST267:
651 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
652 break;
653 case VME_2eSST320:
654 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
655 break;
656 }
657
658 /* Setup cycle types */
659 temp_ctl &= ~(0x1F << 7);
660 if (cycle & VME_BLT)
661 temp_ctl |= TSI148_LCSR_ITAT_BLT;
662 if (cycle & VME_MBLT)
663 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
664 if (cycle & VME_2eVME)
665 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
666 if (cycle & VME_2eSST)
667 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
668 if (cycle & VME_2eSSTB)
669 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
670
671 /* Setup address space */
672 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
673 temp_ctl |= addr;
674
675 temp_ctl &= ~0xF;
676 if (cycle & VME_SUPER)
677 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
678 if (cycle & VME_USER)
679 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
680 if (cycle & VME_PROG)
681 temp_ctl |= TSI148_LCSR_ITAT_PGM;
682 if (cycle & VME_DATA)
683 temp_ctl |= TSI148_LCSR_ITAT_DATA;
684
685 /* Write ctl reg without enable */
686 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
687 TSI148_LCSR_OFFSET_ITAT);
688
689 if (enabled)
690 temp_ctl |= TSI148_LCSR_ITAT_EN;
691
692 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
693 TSI148_LCSR_OFFSET_ITAT);
694
695 return 0;
696}
697
698/*
699 * Get slave window configuration.
700 */
701static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
702 unsigned long long *vme_base, unsigned long long *size,
703 dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
704{
705 unsigned int i, granularity = 0, ctl = 0;
706 unsigned int vme_base_low, vme_base_high;
707 unsigned int vme_bound_low, vme_bound_high;
708 unsigned int pci_offset_low, pci_offset_high;
709 unsigned long long vme_bound, pci_offset;
710 struct tsi148_driver *bridge;
711
712 bridge = image->parent->driver_priv;
713
714 i = image->number;
715
716 /* Read registers */
717 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
718 TSI148_LCSR_OFFSET_ITAT);
719
720 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
721 TSI148_LCSR_OFFSET_ITSAU);
722 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
723 TSI148_LCSR_OFFSET_ITSAL);
724 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
725 TSI148_LCSR_OFFSET_ITEAU);
726 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
727 TSI148_LCSR_OFFSET_ITEAL);
728 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
729 TSI148_LCSR_OFFSET_ITOFU);
730 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
731 TSI148_LCSR_OFFSET_ITOFL);
732
733 /* Convert 64-bit variables to 2x 32-bit variables */
734 reg_join(vme_base_high, vme_base_low, vme_base);
735 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
736 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
737
738 *pci_base = (dma_addr_t)vme_base + pci_offset;
739
740 *enabled = 0;
741 *aspace = 0;
742 *cycle = 0;
743
744 if (ctl & TSI148_LCSR_ITAT_EN)
745 *enabled = 1;
746
747 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
748 granularity = 0x10;
749 *aspace |= VME_A16;
750 }
751 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
752 granularity = 0x1000;
753 *aspace |= VME_A24;
754 }
755 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
756 granularity = 0x10000;
757 *aspace |= VME_A32;
758 }
759 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
760 granularity = 0x10000;
761 *aspace |= VME_A64;
762 }
763
764 /* Need granularity before we set the size */
765 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
766
767
768 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
769 *cycle |= VME_2eSST160;
770 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
771 *cycle |= VME_2eSST267;
772 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
773 *cycle |= VME_2eSST320;
774
775 if (ctl & TSI148_LCSR_ITAT_BLT)
776 *cycle |= VME_BLT;
777 if (ctl & TSI148_LCSR_ITAT_MBLT)
778 *cycle |= VME_MBLT;
779 if (ctl & TSI148_LCSR_ITAT_2eVME)
780 *cycle |= VME_2eVME;
781 if (ctl & TSI148_LCSR_ITAT_2eSST)
782 *cycle |= VME_2eSST;
783 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
784 *cycle |= VME_2eSSTB;
785
786 if (ctl & TSI148_LCSR_ITAT_SUPR)
787 *cycle |= VME_SUPER;
788 if (ctl & TSI148_LCSR_ITAT_NPRIV)
789 *cycle |= VME_USER;
790 if (ctl & TSI148_LCSR_ITAT_PGM)
791 *cycle |= VME_PROG;
792 if (ctl & TSI148_LCSR_ITAT_DATA)
793 *cycle |= VME_DATA;
794
795 return 0;
796}
797
798/*
799 * Allocate and map PCI Resource
800 */
801static int tsi148_alloc_resource(struct vme_master_resource *image,
802 unsigned long long size)
803{
804 unsigned long long existing_size;
805 int retval = 0;
806 struct pci_dev *pdev;
807 struct vme_bridge *tsi148_bridge;
808
809 tsi148_bridge = image->parent;
810
811 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
812
813 existing_size = (unsigned long long)(image->bus_resource.end -
814 image->bus_resource.start);
815
816 /* If the existing size is OK, return */
817 if ((size != 0) && (existing_size == (size - 1)))
818 return 0;
819
820 if (existing_size != 0) {
821 iounmap(image->kern_base);
822 image->kern_base = NULL;
823 kfree(image->bus_resource.name);
824 release_resource(&image->bus_resource);
825 memset(&image->bus_resource, 0, sizeof(struct resource));
826 }
827
828 /* Exit here if size is zero */
829 if (size == 0)
830 return 0;
831
832 if (image->bus_resource.name == NULL) {
833 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
834 if (image->bus_resource.name == NULL) {
835 dev_err(tsi148_bridge->parent, "Unable to allocate "
836 "memory for resource name\n");
837 retval = -ENOMEM;
838 goto err_name;
839 }
840 }
841
842 sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
843 image->number);
844
845 image->bus_resource.start = 0;
846 image->bus_resource.end = (unsigned long)size;
847 image->bus_resource.flags = IORESOURCE_MEM;
848
849 retval = pci_bus_alloc_resource(pdev->bus,
850 &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
851 0, NULL, NULL);
852 if (retval) {
853 dev_err(tsi148_bridge->parent, "Failed to allocate mem "
854 "resource for window %d size 0x%lx start 0x%lx\n",
855 image->number, (unsigned long)size,
856 (unsigned long)image->bus_resource.start);
857 goto err_resource;
858 }
859
860 image->kern_base = ioremap_nocache(
861 image->bus_resource.start, size);
862 if (image->kern_base == NULL) {
863 dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
864 retval = -ENOMEM;
865 goto err_remap;
866 }
867
868 return 0;
869
870err_remap:
871 release_resource(&image->bus_resource);
872err_resource:
873 kfree(image->bus_resource.name);
874 memset(&image->bus_resource, 0, sizeof(struct resource));
875err_name:
876 return retval;
877}
878
879/*
880 * Free and unmap PCI Resource
881 */
882static void tsi148_free_resource(struct vme_master_resource *image)
883{
884 iounmap(image->kern_base);
885 image->kern_base = NULL;
886 release_resource(&image->bus_resource);
887 kfree(image->bus_resource.name);
888 memset(&image->bus_resource, 0, sizeof(struct resource));
889}
890
891/*
892 * Set the attributes of an outbound window.
893 */
894static int tsi148_master_set(struct vme_master_resource *image, int enabled,
895 unsigned long long vme_base, unsigned long long size, u32 aspace,
896 u32 cycle, u32 dwidth)
897{
898 int retval = 0;
899 unsigned int i;
900 unsigned int temp_ctl = 0;
901 unsigned int pci_base_low, pci_base_high;
902 unsigned int pci_bound_low, pci_bound_high;
903 unsigned int vme_offset_low, vme_offset_high;
904 unsigned long long pci_bound, vme_offset, pci_base;
905 struct vme_bridge *tsi148_bridge;
906 struct tsi148_driver *bridge;
907
908 tsi148_bridge = image->parent;
909
910 bridge = tsi148_bridge->driver_priv;
911
912 /* Verify input data */
913 if (vme_base & 0xFFFF) {
914 dev_err(tsi148_bridge->parent, "Invalid VME Window "
915 "alignment\n");
916 retval = -EINVAL;
917 goto err_window;
918 }
919
920 if ((size == 0) && (enabled != 0)) {
921 dev_err(tsi148_bridge->parent, "Size must be non-zero for "
922 "enabled windows\n");
923 retval = -EINVAL;
924 goto err_window;
925 }
926
927 spin_lock(&image->lock);
928
929 /* Let's allocate the resource here rather than further up the stack as
930 * it avoids pushing loads of bus dependent stuff up the stack. If size
931 * is zero, any existing resource will be freed.
932 */
933 retval = tsi148_alloc_resource(image, size);
934 if (retval) {
935 spin_unlock(&image->lock);
936 dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
937 "resource\n");
938 goto err_res;
939 }
940
941 if (size == 0) {
942 pci_base = 0;
943 pci_bound = 0;
944 vme_offset = 0;
945 } else {
946 pci_base = (unsigned long long)image->bus_resource.start;
947
948 /*
949 * Bound address is a valid address for the window, adjust
950 * according to window granularity.
951 */
952 pci_bound = pci_base + (size - 0x10000);
953 vme_offset = vme_base - pci_base;
954 }
955
956 /* Convert 64-bit variables to 2x 32-bit variables */
957 reg_split(pci_base, &pci_base_high, &pci_base_low);
958 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
959 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
960
961 if (pci_base_low & 0xFFFF) {
962 spin_unlock(&image->lock);
963 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
964 retval = -EINVAL;
965 goto err_gran;
966 }
967 if (pci_bound_low & 0xFFFF) {
968 spin_unlock(&image->lock);
969 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
970 retval = -EINVAL;
971 goto err_gran;
972 }
973 if (vme_offset_low & 0xFFFF) {
974 spin_unlock(&image->lock);
975 dev_err(tsi148_bridge->parent, "Invalid VME Offset "
976 "alignment\n");
977 retval = -EINVAL;
978 goto err_gran;
979 }
980
981 i = image->number;
982
983 /* Disable while we are mucking around */
984 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
985 TSI148_LCSR_OFFSET_OTAT);
986 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
987 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
988 TSI148_LCSR_OFFSET_OTAT);
989
990 /* Setup 2eSST speeds */
991 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
992 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
993 case VME_2eSST160:
994 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
995 break;
996 case VME_2eSST267:
997 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
998 break;
999 case VME_2eSST320:
1000 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1001 break;
1002 }
1003
1004 /* Setup cycle types */
1005 if (cycle & VME_BLT) {
1006 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1007 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1008 }
1009 if (cycle & VME_MBLT) {
1010 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1011 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1012 }
1013 if (cycle & VME_2eVME) {
1014 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1015 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1016 }
1017 if (cycle & VME_2eSST) {
1018 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1019 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1020 }
1021 if (cycle & VME_2eSSTB) {
1022 dev_warn(tsi148_bridge->parent, "Currently not setting "
1023 "Broadcast Select Registers\n");
1024 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1025 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1026 }
1027
1028 /* Setup data width */
1029 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1030 switch (dwidth) {
1031 case VME_D16:
1032 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1033 break;
1034 case VME_D32:
1035 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1036 break;
1037 default:
1038 spin_unlock(&image->lock);
1039 dev_err(tsi148_bridge->parent, "Invalid data width\n");
1040 retval = -EINVAL;
1041 goto err_dwidth;
1042 }
1043
1044 /* Setup address space */
1045 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1046 switch (aspace) {
1047 case VME_A16:
1048 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1049 break;
1050 case VME_A24:
1051 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1052 break;
1053 case VME_A32:
1054 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1055 break;
1056 case VME_A64:
1057 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1058 break;
1059 case VME_CRCSR:
1060 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1061 break;
1062 case VME_USER1:
1063 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1064 break;
1065 case VME_USER2:
1066 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1067 break;
1068 case VME_USER3:
1069 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1070 break;
1071 case VME_USER4:
1072 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1073 break;
1074 default:
1075 spin_unlock(&image->lock);
1076 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1077 retval = -EINVAL;
1078 goto err_aspace;
1079 break;
1080 }
1081
1082 temp_ctl &= ~(3<<4);
1083 if (cycle & VME_SUPER)
1084 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1085 if (cycle & VME_PROG)
1086 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1087
1088 /* Setup mapping */
1089 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1090 TSI148_LCSR_OFFSET_OTSAU);
1091 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1092 TSI148_LCSR_OFFSET_OTSAL);
1093 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1094 TSI148_LCSR_OFFSET_OTEAU);
1095 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1096 TSI148_LCSR_OFFSET_OTEAL);
1097 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1098 TSI148_LCSR_OFFSET_OTOFU);
1099 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1100 TSI148_LCSR_OFFSET_OTOFL);
1101
1102 /* Write ctl reg without enable */
1103 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1104 TSI148_LCSR_OFFSET_OTAT);
1105
1106 if (enabled)
1107 temp_ctl |= TSI148_LCSR_OTAT_EN;
1108
1109 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1110 TSI148_LCSR_OFFSET_OTAT);
1111
1112 spin_unlock(&image->lock);
1113 return 0;
1114
1115err_aspace:
1116err_dwidth:
1117err_gran:
1118 tsi148_free_resource(image);
1119err_res:
1120err_window:
1121 return retval;
1122
1123}
1124
1125/*
1126 * Set the attributes of an outbound window.
1127 *
1128 * XXX Not parsing prefetch information.
1129 */
1130static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
1131 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1132 u32 *cycle, u32 *dwidth)
1133{
1134 unsigned int i, ctl;
1135 unsigned int pci_base_low, pci_base_high;
1136 unsigned int pci_bound_low, pci_bound_high;
1137 unsigned int vme_offset_low, vme_offset_high;
1138
1139 unsigned long long pci_base, pci_bound, vme_offset;
1140 struct tsi148_driver *bridge;
1141
1142 bridge = image->parent->driver_priv;
1143
1144 i = image->number;
1145
1146 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1147 TSI148_LCSR_OFFSET_OTAT);
1148
1149 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1150 TSI148_LCSR_OFFSET_OTSAU);
1151 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1152 TSI148_LCSR_OFFSET_OTSAL);
1153 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1154 TSI148_LCSR_OFFSET_OTEAU);
1155 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1156 TSI148_LCSR_OFFSET_OTEAL);
1157 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1158 TSI148_LCSR_OFFSET_OTOFU);
1159 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1160 TSI148_LCSR_OFFSET_OTOFL);
1161
1162 /* Convert 64-bit variables to 2x 32-bit variables */
1163 reg_join(pci_base_high, pci_base_low, &pci_base);
1164 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1165 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1166
1167 *vme_base = pci_base + vme_offset;
1168 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1169
1170 *enabled = 0;
1171 *aspace = 0;
1172 *cycle = 0;
1173 *dwidth = 0;
1174
1175 if (ctl & TSI148_LCSR_OTAT_EN)
1176 *enabled = 1;
1177
1178 /* Setup address space */
1179 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1180 *aspace |= VME_A16;
1181 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1182 *aspace |= VME_A24;
1183 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1184 *aspace |= VME_A32;
1185 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1186 *aspace |= VME_A64;
1187 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1188 *aspace |= VME_CRCSR;
1189 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1190 *aspace |= VME_USER1;
1191 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1192 *aspace |= VME_USER2;
1193 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1194 *aspace |= VME_USER3;
1195 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1196 *aspace |= VME_USER4;
1197
1198 /* Setup 2eSST speeds */
1199 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1200 *cycle |= VME_2eSST160;
1201 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1202 *cycle |= VME_2eSST267;
1203 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1204 *cycle |= VME_2eSST320;
1205
1206 /* Setup cycle types */
1207 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
1208 *cycle |= VME_SCT;
1209 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
1210 *cycle |= VME_BLT;
1211 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
1212 *cycle |= VME_MBLT;
1213 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
1214 *cycle |= VME_2eVME;
1215 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
1216 *cycle |= VME_2eSST;
1217 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
1218 *cycle |= VME_2eSSTB;
1219
1220 if (ctl & TSI148_LCSR_OTAT_SUP)
1221 *cycle |= VME_SUPER;
1222 else
1223 *cycle |= VME_USER;
1224
1225 if (ctl & TSI148_LCSR_OTAT_PGM)
1226 *cycle |= VME_PROG;
1227 else
1228 *cycle |= VME_DATA;
1229
1230 /* Setup data width */
1231 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1232 *dwidth = VME_D16;
1233 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1234 *dwidth = VME_D32;
1235
1236 return 0;
1237}
1238
1239
1240static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
1241 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1242 u32 *cycle, u32 *dwidth)
1243{
1244 int retval;
1245
1246 spin_lock(&image->lock);
1247
1248 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1249 cycle, dwidth);
1250
1251 spin_unlock(&image->lock);
1252
1253 return retval;
1254}
1255
1256static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1257 size_t count, loff_t offset)
1258{
1259 int retval, enabled;
1260 unsigned long long vme_base, size;
1261 u32 aspace, cycle, dwidth;
1262 struct vme_bus_error *vme_err = NULL;
1263 struct vme_bridge *tsi148_bridge;
1264 void *addr = image->kern_base + offset;
1265 unsigned int done = 0;
1266 unsigned int count32;
1267
1268 tsi148_bridge = image->parent;
1269
1270 spin_lock(&image->lock);
1271
1272 /* The following code handles VME address alignment. We cannot use
1273 * memcpy_xxx directly here because it may cut small data transfers in
1274 * to 8-bit cycles, thus making D16 cycle impossible.
1275 * On the other hand, the bridge itself assures that the maximum data
1276 * cycle configured for the transfer is used and splits it
1277 * automatically for non-aligned addresses, so we don't want the
1278 * overhead of needlessly forcing small transfers for the entire cycle.
1279 */
1280 if ((uintptr_t)addr & 0x1) {
1281 *(u8 *)buf = ioread8(addr);
1282 done += 1;
1283 if (done == count)
1284 goto out;
1285 }
1286 if ((uintptr_t)addr & 0x2) {
1287 if ((count - done) < 2) {
1288 *(u8 *)(buf + done) = ioread8(addr + done);
1289 done += 1;
1290 goto out;
1291 } else {
1292 *(u16 *)(buf + done) = ioread16(addr + done);
1293 done += 2;
1294 }
1295 }
1296
1297 count32 = (count - done) & ~0x3;
1298 if (count32 > 0) {
1299 memcpy_fromio(buf + done, addr + done, count32);
1300 done += count32;
1301 }
1302
1303 if ((count - done) & 0x2) {
1304 *(u16 *)(buf + done) = ioread16(addr + done);
1305 done += 2;
1306 }
1307 if ((count - done) & 0x1) {
1308 *(u8 *)(buf + done) = ioread8(addr + done);
1309 done += 1;
1310 }
1311
1312out:
1313 retval = count;
1314
1315 if (!err_chk)
1316 goto skip_chk;
1317
1318 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1319 &dwidth);
1320
1321 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1322 count);
1323 if (vme_err != NULL) {
1324 dev_err(image->parent->parent, "First VME read error detected "
1325 "an at address 0x%llx\n", vme_err->address);
1326 retval = vme_err->address - (vme_base + offset);
1327 /* Clear down save errors in this address range */
1328 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1329 count);
1330 }
1331
1332skip_chk:
1333 spin_unlock(&image->lock);
1334
1335 return retval;
1336}
1337
1338
1339static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1340 size_t count, loff_t offset)
1341{
1342 int retval = 0, enabled;
1343 unsigned long long vme_base, size;
1344 u32 aspace, cycle, dwidth;
1345 void *addr = image->kern_base + offset;
1346 unsigned int done = 0;
1347 unsigned int count32;
1348
1349 struct vme_bus_error *vme_err = NULL;
1350 struct vme_bridge *tsi148_bridge;
1351 struct tsi148_driver *bridge;
1352
1353 tsi148_bridge = image->parent;
1354
1355 bridge = tsi148_bridge->driver_priv;
1356
1357 spin_lock(&image->lock);
1358
1359 /* Here we apply for the same strategy we do in master_read
1360 * function in order to assure D16 cycle when required.
1361 */
1362 if ((uintptr_t)addr & 0x1) {
1363 iowrite8(*(u8 *)buf, addr);
1364 done += 1;
1365 if (done == count)
1366 goto out;
1367 }
1368 if ((uintptr_t)addr & 0x2) {
1369 if ((count - done) < 2) {
1370 iowrite8(*(u8 *)(buf + done), addr + done);
1371 done += 1;
1372 goto out;
1373 } else {
1374 iowrite16(*(u16 *)(buf + done), addr + done);
1375 done += 2;
1376 }
1377 }
1378
1379 count32 = (count - done) & ~0x3;
1380 if (count32 > 0) {
1381 memcpy_toio(addr + done, buf + done, count32);
1382 done += count32;
1383 }
1384
1385 if ((count - done) & 0x2) {
1386 iowrite16(*(u16 *)(buf + done), addr + done);
1387 done += 2;
1388 }
1389 if ((count - done) & 0x1) {
1390 iowrite8(*(u8 *)(buf + done), addr + done);
1391 done += 1;
1392 }
1393
1394out:
1395 retval = count;
1396
1397 /*
1398 * Writes are posted. We need to do a read on the VME bus to flush out
1399 * all of the writes before we check for errors. We can't guarantee
1400 * that reading the data we have just written is safe. It is believed
1401 * that there isn't any read, write re-ordering, so we can read any
1402 * location in VME space, so lets read the Device ID from the tsi148's
1403 * own registers as mapped into CR/CSR space.
1404 *
1405 * We check for saved errors in the written address range/space.
1406 */
1407
1408 if (!err_chk)
1409 goto skip_chk;
1410
1411 /*
1412 * Get window info first, to maximise the time that the buffers may
1413 * fluch on their own
1414 */
1415 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1416 &dwidth);
1417
1418 ioread16(bridge->flush_image->kern_base + 0x7F000);
1419
1420 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1421 count);
1422 if (vme_err != NULL) {
1423 dev_warn(tsi148_bridge->parent, "First VME write error detected"
1424 " an at address 0x%llx\n", vme_err->address);
1425 retval = vme_err->address - (vme_base + offset);
1426 /* Clear down save errors in this address range */
1427 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1428 count);
1429 }
1430
1431skip_chk:
1432 spin_unlock(&image->lock);
1433
1434 return retval;
1435}
1436
1437/*
1438 * Perform an RMW cycle on the VME bus.
1439 *
1440 * Requires a previously configured master window, returns final value.
1441 */
1442static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1443 unsigned int mask, unsigned int compare, unsigned int swap,
1444 loff_t offset)
1445{
1446 unsigned long long pci_addr;
1447 unsigned int pci_addr_high, pci_addr_low;
1448 u32 tmp, result;
1449 int i;
1450 struct tsi148_driver *bridge;
1451
1452 bridge = image->parent->driver_priv;
1453
1454 /* Find the PCI address that maps to the desired VME address */
1455 i = image->number;
1456
1457 /* Locking as we can only do one of these at a time */
1458 mutex_lock(&bridge->vme_rmw);
1459
1460 /* Lock image */
1461 spin_lock(&image->lock);
1462
1463 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1464 TSI148_LCSR_OFFSET_OTSAU);
1465 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1466 TSI148_LCSR_OFFSET_OTSAL);
1467
1468 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1469 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1470
1471 /* Configure registers */
1472 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1473 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1474 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1475 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1476 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1477
1478 /* Enable RMW */
1479 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1480 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1481 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1482
1483 /* Kick process off with a read to the required address. */
1484 result = ioread32be(image->kern_base + offset);
1485
1486 /* Disable RMW */
1487 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1488 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1489 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1490
1491 spin_unlock(&image->lock);
1492
1493 mutex_unlock(&bridge->vme_rmw);
1494
1495 return result;
1496}
1497
1498static int tsi148_dma_set_vme_src_attributes(struct device *dev, __be32 *attr,
1499 u32 aspace, u32 cycle, u32 dwidth)
1500{
1501 u32 val;
1502
1503 val = be32_to_cpu(*attr);
1504
1505 /* Setup 2eSST speeds */
1506 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1507 case VME_2eSST160:
1508 val |= TSI148_LCSR_DSAT_2eSSTM_160;
1509 break;
1510 case VME_2eSST267:
1511 val |= TSI148_LCSR_DSAT_2eSSTM_267;
1512 break;
1513 case VME_2eSST320:
1514 val |= TSI148_LCSR_DSAT_2eSSTM_320;
1515 break;
1516 }
1517
1518 /* Setup cycle types */
1519 if (cycle & VME_SCT)
1520 val |= TSI148_LCSR_DSAT_TM_SCT;
1521
1522 if (cycle & VME_BLT)
1523 val |= TSI148_LCSR_DSAT_TM_BLT;
1524
1525 if (cycle & VME_MBLT)
1526 val |= TSI148_LCSR_DSAT_TM_MBLT;
1527
1528 if (cycle & VME_2eVME)
1529 val |= TSI148_LCSR_DSAT_TM_2eVME;
1530
1531 if (cycle & VME_2eSST)
1532 val |= TSI148_LCSR_DSAT_TM_2eSST;
1533
1534 if (cycle & VME_2eSSTB) {
1535 dev_err(dev, "Currently not setting Broadcast Select "
1536 "Registers\n");
1537 val |= TSI148_LCSR_DSAT_TM_2eSSTB;
1538 }
1539
1540 /* Setup data width */
1541 switch (dwidth) {
1542 case VME_D16:
1543 val |= TSI148_LCSR_DSAT_DBW_16;
1544 break;
1545 case VME_D32:
1546 val |= TSI148_LCSR_DSAT_DBW_32;
1547 break;
1548 default:
1549 dev_err(dev, "Invalid data width\n");
1550 return -EINVAL;
1551 }
1552
1553 /* Setup address space */
1554 switch (aspace) {
1555 case VME_A16:
1556 val |= TSI148_LCSR_DSAT_AMODE_A16;
1557 break;
1558 case VME_A24:
1559 val |= TSI148_LCSR_DSAT_AMODE_A24;
1560 break;
1561 case VME_A32:
1562 val |= TSI148_LCSR_DSAT_AMODE_A32;
1563 break;
1564 case VME_A64:
1565 val |= TSI148_LCSR_DSAT_AMODE_A64;
1566 break;
1567 case VME_CRCSR:
1568 val |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1569 break;
1570 case VME_USER1:
1571 val |= TSI148_LCSR_DSAT_AMODE_USER1;
1572 break;
1573 case VME_USER2:
1574 val |= TSI148_LCSR_DSAT_AMODE_USER2;
1575 break;
1576 case VME_USER3:
1577 val |= TSI148_LCSR_DSAT_AMODE_USER3;
1578 break;
1579 case VME_USER4:
1580 val |= TSI148_LCSR_DSAT_AMODE_USER4;
1581 break;
1582 default:
1583 dev_err(dev, "Invalid address space\n");
1584 return -EINVAL;
1585 break;
1586 }
1587
1588 if (cycle & VME_SUPER)
1589 val |= TSI148_LCSR_DSAT_SUP;
1590 if (cycle & VME_PROG)
1591 val |= TSI148_LCSR_DSAT_PGM;
1592
1593 *attr = cpu_to_be32(val);
1594
1595 return 0;
1596}
1597
1598static int tsi148_dma_set_vme_dest_attributes(struct device *dev, __be32 *attr,
1599 u32 aspace, u32 cycle, u32 dwidth)
1600{
1601 u32 val;
1602
1603 val = be32_to_cpu(*attr);
1604
1605 /* Setup 2eSST speeds */
1606 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1607 case VME_2eSST160:
1608 val |= TSI148_LCSR_DDAT_2eSSTM_160;
1609 break;
1610 case VME_2eSST267:
1611 val |= TSI148_LCSR_DDAT_2eSSTM_267;
1612 break;
1613 case VME_2eSST320:
1614 val |= TSI148_LCSR_DDAT_2eSSTM_320;
1615 break;
1616 }
1617
1618 /* Setup cycle types */
1619 if (cycle & VME_SCT)
1620 val |= TSI148_LCSR_DDAT_TM_SCT;
1621
1622 if (cycle & VME_BLT)
1623 val |= TSI148_LCSR_DDAT_TM_BLT;
1624
1625 if (cycle & VME_MBLT)
1626 val |= TSI148_LCSR_DDAT_TM_MBLT;
1627
1628 if (cycle & VME_2eVME)
1629 val |= TSI148_LCSR_DDAT_TM_2eVME;
1630
1631 if (cycle & VME_2eSST)
1632 val |= TSI148_LCSR_DDAT_TM_2eSST;
1633
1634 if (cycle & VME_2eSSTB) {
1635 dev_err(dev, "Currently not setting Broadcast Select "
1636 "Registers\n");
1637 val |= TSI148_LCSR_DDAT_TM_2eSSTB;
1638 }
1639
1640 /* Setup data width */
1641 switch (dwidth) {
1642 case VME_D16:
1643 val |= TSI148_LCSR_DDAT_DBW_16;
1644 break;
1645 case VME_D32:
1646 val |= TSI148_LCSR_DDAT_DBW_32;
1647 break;
1648 default:
1649 dev_err(dev, "Invalid data width\n");
1650 return -EINVAL;
1651 }
1652
1653 /* Setup address space */
1654 switch (aspace) {
1655 case VME_A16:
1656 val |= TSI148_LCSR_DDAT_AMODE_A16;
1657 break;
1658 case VME_A24:
1659 val |= TSI148_LCSR_DDAT_AMODE_A24;
1660 break;
1661 case VME_A32:
1662 val |= TSI148_LCSR_DDAT_AMODE_A32;
1663 break;
1664 case VME_A64:
1665 val |= TSI148_LCSR_DDAT_AMODE_A64;
1666 break;
1667 case VME_CRCSR:
1668 val |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1669 break;
1670 case VME_USER1:
1671 val |= TSI148_LCSR_DDAT_AMODE_USER1;
1672 break;
1673 case VME_USER2:
1674 val |= TSI148_LCSR_DDAT_AMODE_USER2;
1675 break;
1676 case VME_USER3:
1677 val |= TSI148_LCSR_DDAT_AMODE_USER3;
1678 break;
1679 case VME_USER4:
1680 val |= TSI148_LCSR_DDAT_AMODE_USER4;
1681 break;
1682 default:
1683 dev_err(dev, "Invalid address space\n");
1684 return -EINVAL;
1685 break;
1686 }
1687
1688 if (cycle & VME_SUPER)
1689 val |= TSI148_LCSR_DDAT_SUP;
1690 if (cycle & VME_PROG)
1691 val |= TSI148_LCSR_DDAT_PGM;
1692
1693 *attr = cpu_to_be32(val);
1694
1695 return 0;
1696}
1697
1698/*
1699 * Add a link list descriptor to the list
1700 *
1701 * Note: DMA engine expects the DMA descriptor to be big endian.
1702 */
1703static int tsi148_dma_list_add(struct vme_dma_list *list,
1704 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1705{
1706 struct tsi148_dma_entry *entry, *prev;
1707 u32 address_high, address_low, val;
1708 struct vme_dma_pattern *pattern_attr;
1709 struct vme_dma_pci *pci_attr;
1710 struct vme_dma_vme *vme_attr;
1711 int retval = 0;
1712 struct vme_bridge *tsi148_bridge;
1713
1714 tsi148_bridge = list->parent->parent;
1715
1716 /* Descriptor must be aligned on 64-bit boundaries */
1717 entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1718 if (entry == NULL) {
1719 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
1720 "dma resource structure\n");
1721 retval = -ENOMEM;
1722 goto err_mem;
1723 }
1724
1725 /* Test descriptor alignment */
1726 if ((unsigned long)&entry->descriptor & 0x7) {
1727 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1728 "byte boundary as required: %p\n",
1729 &entry->descriptor);
1730 retval = -EINVAL;
1731 goto err_align;
1732 }
1733
1734 /* Given we are going to fill out the structure, we probably don't
1735 * need to zero it, but better safe than sorry for now.
1736 */
1737 memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor));
1738
1739 /* Fill out source part */
1740 switch (src->type) {
1741 case VME_DMA_PATTERN:
1742 pattern_attr = src->private;
1743
1744 entry->descriptor.dsal = cpu_to_be32(pattern_attr->pattern);
1745
1746 val = TSI148_LCSR_DSAT_TYP_PAT;
1747
1748 /* Default behaviour is 32 bit pattern */
1749 if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
1750 val |= TSI148_LCSR_DSAT_PSZ;
1751
1752 /* It seems that the default behaviour is to increment */
1753 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
1754 val |= TSI148_LCSR_DSAT_NIN;
1755 entry->descriptor.dsat = cpu_to_be32(val);
1756 break;
1757 case VME_DMA_PCI:
1758 pci_attr = src->private;
1759
1760 reg_split((unsigned long long)pci_attr->address, &address_high,
1761 &address_low);
1762 entry->descriptor.dsau = cpu_to_be32(address_high);
1763 entry->descriptor.dsal = cpu_to_be32(address_low);
1764 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_PCI);
1765 break;
1766 case VME_DMA_VME:
1767 vme_attr = src->private;
1768
1769 reg_split((unsigned long long)vme_attr->address, &address_high,
1770 &address_low);
1771 entry->descriptor.dsau = cpu_to_be32(address_high);
1772 entry->descriptor.dsal = cpu_to_be32(address_low);
1773 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_VME);
1774
1775 retval = tsi148_dma_set_vme_src_attributes(
1776 tsi148_bridge->parent, &entry->descriptor.dsat,
1777 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1778 if (retval < 0)
1779 goto err_source;
1780 break;
1781 default:
1782 dev_err(tsi148_bridge->parent, "Invalid source type\n");
1783 retval = -EINVAL;
1784 goto err_source;
1785 break;
1786 }
1787
1788 /* Assume last link - this will be over-written by adding another */
1789 entry->descriptor.dnlau = cpu_to_be32(0);
1790 entry->descriptor.dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA);
1791
1792 /* Fill out destination part */
1793 switch (dest->type) {
1794 case VME_DMA_PCI:
1795 pci_attr = dest->private;
1796
1797 reg_split((unsigned long long)pci_attr->address, &address_high,
1798 &address_low);
1799 entry->descriptor.ddau = cpu_to_be32(address_high);
1800 entry->descriptor.ddal = cpu_to_be32(address_low);
1801 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_PCI);
1802 break;
1803 case VME_DMA_VME:
1804 vme_attr = dest->private;
1805
1806 reg_split((unsigned long long)vme_attr->address, &address_high,
1807 &address_low);
1808 entry->descriptor.ddau = cpu_to_be32(address_high);
1809 entry->descriptor.ddal = cpu_to_be32(address_low);
1810 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_VME);
1811
1812 retval = tsi148_dma_set_vme_dest_attributes(
1813 tsi148_bridge->parent, &entry->descriptor.ddat,
1814 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1815 if (retval < 0)
1816 goto err_dest;
1817 break;
1818 default:
1819 dev_err(tsi148_bridge->parent, "Invalid destination type\n");
1820 retval = -EINVAL;
1821 goto err_dest;
1822 break;
1823 }
1824
1825 /* Fill out count */
1826 entry->descriptor.dcnt = cpu_to_be32((u32)count);
1827
1828 /* Add to list */
1829 list_add_tail(&entry->list, &list->entries);
1830
1831 /* Fill out previous descriptors "Next Address" */
1832 if (entry->list.prev != &list->entries) {
1833 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1834 list);
1835 /* We need the bus address for the pointer */
1836 entry->dma_handle = dma_map_single(tsi148_bridge->parent,
1837 &entry->descriptor,
1838 sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
1839
1840 reg_split((unsigned long long)entry->dma_handle, &address_high,
1841 &address_low);
1842 entry->descriptor.dnlau = cpu_to_be32(address_high);
1843 entry->descriptor.dnlal = cpu_to_be32(address_low);
1844
1845 }
1846
1847 return 0;
1848
1849err_dest:
1850err_source:
1851err_align:
1852 kfree(entry);
1853err_mem:
1854 return retval;
1855}
1856
1857/*
1858 * Check to see if the provided DMA channel is busy.
1859 */
1860static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
1861{
1862 u32 tmp;
1863 struct tsi148_driver *bridge;
1864
1865 bridge = tsi148_bridge->driver_priv;
1866
1867 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1868 TSI148_LCSR_OFFSET_DSTA);
1869
1870 if (tmp & TSI148_LCSR_DSTA_BSY)
1871 return 0;
1872 else
1873 return 1;
1874
1875}
1876
1877/*
1878 * Execute a previously generated link list
1879 *
1880 * XXX Need to provide control register configuration.
1881 */
1882static int tsi148_dma_list_exec(struct vme_dma_list *list)
1883{
1884 struct vme_dma_resource *ctrlr;
1885 int channel, retval = 0;
1886 struct tsi148_dma_entry *entry;
1887 u32 bus_addr_high, bus_addr_low;
1888 u32 val, dctlreg = 0;
1889 struct vme_bridge *tsi148_bridge;
1890 struct tsi148_driver *bridge;
1891
1892 ctrlr = list->parent;
1893
1894 tsi148_bridge = ctrlr->parent;
1895
1896 bridge = tsi148_bridge->driver_priv;
1897
1898 mutex_lock(&ctrlr->mtx);
1899
1900 channel = ctrlr->number;
1901
1902 if (!list_empty(&ctrlr->running)) {
1903 /*
1904 * XXX We have an active DMA transfer and currently haven't
1905 * sorted out the mechanism for "pending" DMA transfers.
1906 * Return busy.
1907 */
1908 /* Need to add to pending here */
1909 mutex_unlock(&ctrlr->mtx);
1910 return -EBUSY;
1911 } else {
1912 list_add(&list->list, &ctrlr->running);
1913 }
1914
1915 /* Get first bus address and write into registers */
1916 entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
1917 list);
1918
1919 entry->dma_handle = dma_map_single(tsi148_bridge->parent,
1920 &entry->descriptor,
1921 sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
1922
1923 mutex_unlock(&ctrlr->mtx);
1924
1925 reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low);
1926
1927 iowrite32be(bus_addr_high, bridge->base +
1928 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1929 iowrite32be(bus_addr_low, bridge->base +
1930 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1931
1932 dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1933 TSI148_LCSR_OFFSET_DCTL);
1934
1935 /* Start the operation */
1936 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1937 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1938
1939 wait_event_interruptible(bridge->dma_queue[channel],
1940 tsi148_dma_busy(ctrlr->parent, channel));
1941
1942 /*
1943 * Read status register, this register is valid until we kick off a
1944 * new transfer.
1945 */
1946 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1947 TSI148_LCSR_OFFSET_DSTA);
1948
1949 if (val & TSI148_LCSR_DSTA_VBE) {
1950 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
1951 retval = -EIO;
1952 }
1953
1954 /* Remove list from running list */
1955 mutex_lock(&ctrlr->mtx);
1956 list_del(&list->list);
1957 mutex_unlock(&ctrlr->mtx);
1958
1959 return retval;
1960}
1961
1962/*
1963 * Clean up a previously generated link list
1964 *
1965 * We have a separate function, don't assume that the chain can't be reused.
1966 */
1967static int tsi148_dma_list_empty(struct vme_dma_list *list)
1968{
1969 struct list_head *pos, *temp;
1970 struct tsi148_dma_entry *entry;
1971
1972 struct vme_bridge *tsi148_bridge = list->parent->parent;
1973
1974 /* detach and free each entry */
1975 list_for_each_safe(pos, temp, &list->entries) {
1976 list_del(pos);
1977 entry = list_entry(pos, struct tsi148_dma_entry, list);
1978
1979 dma_unmap_single(tsi148_bridge->parent, entry->dma_handle,
1980 sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
1981 kfree(entry);
1982 }
1983
1984 return 0;
1985}
1986
1987/*
1988 * All 4 location monitors reside at the same base - this is therefore a
1989 * system wide configuration.
1990 *
1991 * This does not enable the LM monitor - that should be done when the first
1992 * callback is attached and disabled when the last callback is removed.
1993 */
1994static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1995 u32 aspace, u32 cycle)
1996{
1997 u32 lm_base_high, lm_base_low, lm_ctl = 0;
1998 int i;
1999 struct vme_bridge *tsi148_bridge;
2000 struct tsi148_driver *bridge;
2001
2002 tsi148_bridge = lm->parent;
2003
2004 bridge = tsi148_bridge->driver_priv;
2005
2006 mutex_lock(&lm->mtx);
2007
2008 /* If we already have a callback attached, we can't move it! */
2009 for (i = 0; i < lm->monitors; i++) {
2010 if (bridge->lm_callback[i] != NULL) {
2011 mutex_unlock(&lm->mtx);
2012 dev_err(tsi148_bridge->parent, "Location monitor "
2013 "callback attached, can't reset\n");
2014 return -EBUSY;
2015 }
2016 }
2017
2018 switch (aspace) {
2019 case VME_A16:
2020 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
2021 break;
2022 case VME_A24:
2023 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
2024 break;
2025 case VME_A32:
2026 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
2027 break;
2028 case VME_A64:
2029 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
2030 break;
2031 default:
2032 mutex_unlock(&lm->mtx);
2033 dev_err(tsi148_bridge->parent, "Invalid address space\n");
2034 return -EINVAL;
2035 break;
2036 }
2037
2038 if (cycle & VME_SUPER)
2039 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
2040 if (cycle & VME_USER)
2041 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
2042 if (cycle & VME_PROG)
2043 lm_ctl |= TSI148_LCSR_LMAT_PGM;
2044 if (cycle & VME_DATA)
2045 lm_ctl |= TSI148_LCSR_LMAT_DATA;
2046
2047 reg_split(lm_base, &lm_base_high, &lm_base_low);
2048
2049 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
2050 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
2051 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2052
2053 mutex_unlock(&lm->mtx);
2054
2055 return 0;
2056}
2057
2058/* Get configuration of the callback monitor and return whether it is enabled
2059 * or disabled.
2060 */
2061static int tsi148_lm_get(struct vme_lm_resource *lm,
2062 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
2063{
2064 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
2065 struct tsi148_driver *bridge;
2066
2067 bridge = lm->parent->driver_priv;
2068
2069 mutex_lock(&lm->mtx);
2070
2071 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
2072 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
2073 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2074
2075 reg_join(lm_base_high, lm_base_low, lm_base);
2076
2077 if (lm_ctl & TSI148_LCSR_LMAT_EN)
2078 enabled = 1;
2079
2080 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
2081 *aspace |= VME_A16;
2082
2083 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
2084 *aspace |= VME_A24;
2085
2086 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
2087 *aspace |= VME_A32;
2088
2089 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
2090 *aspace |= VME_A64;
2091
2092
2093 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2094 *cycle |= VME_SUPER;
2095 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2096 *cycle |= VME_USER;
2097 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2098 *cycle |= VME_PROG;
2099 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2100 *cycle |= VME_DATA;
2101
2102 mutex_unlock(&lm->mtx);
2103
2104 return enabled;
2105}
2106
2107/*
2108 * Attach a callback to a specific location monitor.
2109 *
2110 * Callback will be passed the monitor triggered.
2111 */
2112static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2113 void (*callback)(int))
2114{
2115 u32 lm_ctl, tmp;
2116 struct vme_bridge *tsi148_bridge;
2117 struct tsi148_driver *bridge;
2118
2119 tsi148_bridge = lm->parent;
2120
2121 bridge = tsi148_bridge->driver_priv;
2122
2123 mutex_lock(&lm->mtx);
2124
2125 /* Ensure that the location monitor is configured - need PGM or DATA */
2126 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2127 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
2128 mutex_unlock(&lm->mtx);
2129 dev_err(tsi148_bridge->parent, "Location monitor not properly "
2130 "configured\n");
2131 return -EINVAL;
2132 }
2133
2134 /* Check that a callback isn't already attached */
2135 if (bridge->lm_callback[monitor] != NULL) {
2136 mutex_unlock(&lm->mtx);
2137 dev_err(tsi148_bridge->parent, "Existing callback attached\n");
2138 return -EBUSY;
2139 }
2140
2141 /* Attach callback */
2142 bridge->lm_callback[monitor] = callback;
2143
2144 /* Enable Location Monitor interrupt */
2145 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2146 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2147 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2148
2149 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2150 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2151 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2152
2153 /* Ensure that global Location Monitor Enable set */
2154 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2155 lm_ctl |= TSI148_LCSR_LMAT_EN;
2156 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2157 }
2158
2159 mutex_unlock(&lm->mtx);
2160
2161 return 0;
2162}
2163
2164/*
2165 * Detach a callback function forn a specific location monitor.
2166 */
2167static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
2168{
2169 u32 lm_en, tmp;
2170 struct tsi148_driver *bridge;
2171
2172 bridge = lm->parent->driver_priv;
2173
2174 mutex_lock(&lm->mtx);
2175
2176 /* Disable Location Monitor and ensure previous interrupts are clear */
2177 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2178 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2179 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2180
2181 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2182 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2183 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2184
2185 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2186 bridge->base + TSI148_LCSR_INTC);
2187
2188 /* Detach callback */
2189 bridge->lm_callback[monitor] = NULL;
2190
2191 /* If all location monitors disabled, disable global Location Monitor */
2192 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2193 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2194 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2195 tmp &= ~TSI148_LCSR_LMAT_EN;
2196 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2197 }
2198
2199 mutex_unlock(&lm->mtx);
2200
2201 return 0;
2202}
2203
2204/*
2205 * Determine Geographical Addressing
2206 */
2207static int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
2208{
2209 u32 slot = 0;
2210 struct tsi148_driver *bridge;
2211
2212 bridge = tsi148_bridge->driver_priv;
2213
2214 if (!geoid) {
2215 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2216 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2217 } else
2218 slot = geoid;
2219
2220 return (int)slot;
2221}
2222
2223static void *tsi148_alloc_consistent(struct device *parent, size_t size,
2224 dma_addr_t *dma)
2225{
2226 struct pci_dev *pdev;
2227
2228 /* Find pci_dev container of dev */
2229 pdev = container_of(parent, struct pci_dev, dev);
2230
2231 return pci_alloc_consistent(pdev, size, dma);
2232}
2233
2234static void tsi148_free_consistent(struct device *parent, size_t size,
2235 void *vaddr, dma_addr_t dma)
2236{
2237 struct pci_dev *pdev;
2238
2239 /* Find pci_dev container of dev */
2240 pdev = container_of(parent, struct pci_dev, dev);
2241
2242 pci_free_consistent(pdev, size, vaddr, dma);
2243}
2244
2245/*
2246 * Configure CR/CSR space
2247 *
2248 * Access to the CR/CSR can be configured at power-up. The location of the
2249 * CR/CSR registers in the CR/CSR address space is determined by the boards
2250 * Auto-ID or Geographic address. This function ensures that the window is
2251 * enabled at an offset consistent with the boards geopgraphic address.
2252 *
2253 * Each board has a 512kB window, with the highest 4kB being used for the
2254 * boards registers, this means there is a fix length 508kB window which must
2255 * be mapped onto PCI memory.
2256 */
2257static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2258 struct pci_dev *pdev)
2259{
2260 u32 cbar, crat, vstat;
2261 u32 crcsr_bus_high, crcsr_bus_low;
2262 int retval;
2263 struct tsi148_driver *bridge;
2264
2265 bridge = tsi148_bridge->driver_priv;
2266
2267 /* Allocate mem for CR/CSR image */
2268 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2269 &bridge->crcsr_bus);
2270 if (bridge->crcsr_kernel == NULL) {
2271 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
2272 "CR/CSR image\n");
2273 return -ENOMEM;
2274 }
2275
2276 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2277
2278 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2279
2280 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2281 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2282
2283 /* Ensure that the CR/CSR is configured at the correct offset */
2284 cbar = ioread32be(bridge->base + TSI148_CBAR);
2285 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2286
2287 vstat = tsi148_slot_get(tsi148_bridge);
2288
2289 if (cbar != vstat) {
2290 cbar = vstat;
2291 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
2292 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2293 }
2294 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
2295
2296 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2297 if (crat & TSI148_LCSR_CRAT_EN) {
2298 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
2299 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2300 bridge->base + TSI148_LCSR_CRAT);
2301 } else
2302 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2303
2304 /* If we want flushed, error-checked writes, set up a window
2305 * over the CR/CSR registers. We read from here to safely flush
2306 * through VME writes.
2307 */
2308 if (err_chk) {
2309 retval = tsi148_master_set(bridge->flush_image, 1,
2310 (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2311 VME_D16);
2312 if (retval)
2313 dev_err(tsi148_bridge->parent, "Configuring flush image"
2314 " failed\n");
2315 }
2316
2317 return 0;
2318
2319}
2320
2321static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2322 struct pci_dev *pdev)
2323{
2324 u32 crat;
2325 struct tsi148_driver *bridge;
2326
2327 bridge = tsi148_bridge->driver_priv;
2328
2329 /* Turn off CR/CSR space */
2330 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2331 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2332 bridge->base + TSI148_LCSR_CRAT);
2333
2334 /* Free image */
2335 iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2336 iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2337
2338 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2339 bridge->crcsr_bus);
2340}
2341
2342static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2343{
2344 int retval, i, master_num;
2345 u32 data;
2346 struct list_head *pos = NULL, *n;
2347 struct vme_bridge *tsi148_bridge;
2348 struct tsi148_driver *tsi148_device;
2349 struct vme_master_resource *master_image;
2350 struct vme_slave_resource *slave_image;
2351 struct vme_dma_resource *dma_ctrlr;
2352 struct vme_lm_resource *lm;
2353
2354 /* If we want to support more than one of each bridge, we need to
2355 * dynamically generate this so we get one per device
2356 */
2357 tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
2358 if (tsi148_bridge == NULL) {
2359 dev_err(&pdev->dev, "Failed to allocate memory for device "
2360 "structure\n");
2361 retval = -ENOMEM;
2362 goto err_struct;
2363 }
2364
2365 tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL);
2366 if (tsi148_device == NULL) {
2367 dev_err(&pdev->dev, "Failed to allocate memory for device "
2368 "structure\n");
2369 retval = -ENOMEM;
2370 goto err_driver;
2371 }
2372
2373 tsi148_bridge->driver_priv = tsi148_device;
2374
2375 /* Enable the device */
2376 retval = pci_enable_device(pdev);
2377 if (retval) {
2378 dev_err(&pdev->dev, "Unable to enable device\n");
2379 goto err_enable;
2380 }
2381
2382 /* Map Registers */
2383 retval = pci_request_regions(pdev, driver_name);
2384 if (retval) {
2385 dev_err(&pdev->dev, "Unable to reserve resources\n");
2386 goto err_resource;
2387 }
2388
2389 /* map registers in BAR 0 */
2390 tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2391 4096);
2392 if (!tsi148_device->base) {
2393 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2394 retval = -EIO;
2395 goto err_remap;
2396 }
2397
2398 /* Check to see if the mapping worked out */
2399 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
2400 if (data != PCI_VENDOR_ID_TUNDRA) {
2401 dev_err(&pdev->dev, "CRG region check failed\n");
2402 retval = -EIO;
2403 goto err_test;
2404 }
2405
2406 /* Initialize wait queues & mutual exclusion flags */
2407 init_waitqueue_head(&tsi148_device->dma_queue[0]);
2408 init_waitqueue_head(&tsi148_device->dma_queue[1]);
2409 init_waitqueue_head(&tsi148_device->iack_queue);
2410 mutex_init(&tsi148_device->vme_int);
2411 mutex_init(&tsi148_device->vme_rmw);
2412
2413 tsi148_bridge->parent = &pdev->dev;
2414 strcpy(tsi148_bridge->name, driver_name);
2415
2416 /* Setup IRQ */
2417 retval = tsi148_irq_init(tsi148_bridge);
2418 if (retval != 0) {
2419 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2420 goto err_irq;
2421 }
2422
2423 /* If we are going to flush writes, we need to read from the VME bus.
2424 * We need to do this safely, thus we read the devices own CR/CSR
2425 * register. To do this we must set up a window in CR/CSR space and
2426 * hence have one less master window resource available.
2427 */
2428 master_num = TSI148_MAX_MASTER;
2429 if (err_chk) {
2430 master_num--;
2431
2432 tsi148_device->flush_image =
2433 kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL);
2434 if (tsi148_device->flush_image == NULL) {
2435 dev_err(&pdev->dev, "Failed to allocate memory for "
2436 "flush resource structure\n");
2437 retval = -ENOMEM;
2438 goto err_master;
2439 }
2440 tsi148_device->flush_image->parent = tsi148_bridge;
2441 spin_lock_init(&tsi148_device->flush_image->lock);
2442 tsi148_device->flush_image->locked = 1;
2443 tsi148_device->flush_image->number = master_num;
2444 tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 |
2445 VME_A32 | VME_A64;
2446 tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT |
2447 VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB |
2448 VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER |
2449 VME_USER | VME_PROG | VME_DATA;
2450 tsi148_device->flush_image->width_attr = VME_D16 | VME_D32;
2451 memset(&tsi148_device->flush_image->bus_resource, 0,
2452 sizeof(struct resource));
2453 tsi148_device->flush_image->kern_base = NULL;
2454 }
2455
2456 /* Add master windows to list */
2457 INIT_LIST_HEAD(&tsi148_bridge->master_resources);
2458 for (i = 0; i < master_num; i++) {
2459 master_image = kmalloc(sizeof(struct vme_master_resource),
2460 GFP_KERNEL);
2461 if (master_image == NULL) {
2462 dev_err(&pdev->dev, "Failed to allocate memory for "
2463 "master resource structure\n");
2464 retval = -ENOMEM;
2465 goto err_master;
2466 }
2467 master_image->parent = tsi148_bridge;
2468 spin_lock_init(&master_image->lock);
2469 master_image->locked = 0;
2470 master_image->number = i;
2471 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2472 VME_A64;
2473 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2474 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2475 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2476 VME_PROG | VME_DATA;
2477 master_image->width_attr = VME_D16 | VME_D32;
2478 memset(&master_image->bus_resource, 0,
2479 sizeof(struct resource));
2480 master_image->kern_base = NULL;
2481 list_add_tail(&master_image->list,
2482 &tsi148_bridge->master_resources);
2483 }
2484
2485 /* Add slave windows to list */
2486 INIT_LIST_HEAD(&tsi148_bridge->slave_resources);
2487 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2488 slave_image = kmalloc(sizeof(struct vme_slave_resource),
2489 GFP_KERNEL);
2490 if (slave_image == NULL) {
2491 dev_err(&pdev->dev, "Failed to allocate memory for "
2492 "slave resource structure\n");
2493 retval = -ENOMEM;
2494 goto err_slave;
2495 }
2496 slave_image->parent = tsi148_bridge;
2497 mutex_init(&slave_image->mtx);
2498 slave_image->locked = 0;
2499 slave_image->number = i;
2500 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2501 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2502 VME_USER3 | VME_USER4;
2503 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2504 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2505 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2506 VME_PROG | VME_DATA;
2507 list_add_tail(&slave_image->list,
2508 &tsi148_bridge->slave_resources);
2509 }
2510
2511 /* Add dma engines to list */
2512 INIT_LIST_HEAD(&tsi148_bridge->dma_resources);
2513 for (i = 0; i < TSI148_MAX_DMA; i++) {
2514 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
2515 GFP_KERNEL);
2516 if (dma_ctrlr == NULL) {
2517 dev_err(&pdev->dev, "Failed to allocate memory for "
2518 "dma resource structure\n");
2519 retval = -ENOMEM;
2520 goto err_dma;
2521 }
2522 dma_ctrlr->parent = tsi148_bridge;
2523 mutex_init(&dma_ctrlr->mtx);
2524 dma_ctrlr->locked = 0;
2525 dma_ctrlr->number = i;
2526 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2527 VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2528 VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2529 VME_DMA_PATTERN_TO_MEM;
2530 INIT_LIST_HEAD(&dma_ctrlr->pending);
2531 INIT_LIST_HEAD(&dma_ctrlr->running);
2532 list_add_tail(&dma_ctrlr->list,
2533 &tsi148_bridge->dma_resources);
2534 }
2535
2536 /* Add location monitor to list */
2537 INIT_LIST_HEAD(&tsi148_bridge->lm_resources);
2538 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2539 if (lm == NULL) {
2540 dev_err(&pdev->dev, "Failed to allocate memory for "
2541 "location monitor resource structure\n");
2542 retval = -ENOMEM;
2543 goto err_lm;
2544 }
2545 lm->parent = tsi148_bridge;
2546 mutex_init(&lm->mtx);
2547 lm->locked = 0;
2548 lm->number = 1;
2549 lm->monitors = 4;
2550 list_add_tail(&lm->list, &tsi148_bridge->lm_resources);
2551
2552 tsi148_bridge->slave_get = tsi148_slave_get;
2553 tsi148_bridge->slave_set = tsi148_slave_set;
2554 tsi148_bridge->master_get = tsi148_master_get;
2555 tsi148_bridge->master_set = tsi148_master_set;
2556 tsi148_bridge->master_read = tsi148_master_read;
2557 tsi148_bridge->master_write = tsi148_master_write;
2558 tsi148_bridge->master_rmw = tsi148_master_rmw;
2559 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2560 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2561 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2562 tsi148_bridge->irq_set = tsi148_irq_set;
2563 tsi148_bridge->irq_generate = tsi148_irq_generate;
2564 tsi148_bridge->lm_set = tsi148_lm_set;
2565 tsi148_bridge->lm_get = tsi148_lm_get;
2566 tsi148_bridge->lm_attach = tsi148_lm_attach;
2567 tsi148_bridge->lm_detach = tsi148_lm_detach;
2568 tsi148_bridge->slot_get = tsi148_slot_get;
2569 tsi148_bridge->alloc_consistent = tsi148_alloc_consistent;
2570 tsi148_bridge->free_consistent = tsi148_free_consistent;
2571
2572 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2573 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2574 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
2575 if (!geoid)
2576 dev_info(&pdev->dev, "VME geographical address is %d\n",
2577 data & TSI148_LCSR_VSTAT_GA_M);
2578 else
2579 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2580 geoid);
2581
2582 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2583 err_chk ? "enabled" : "disabled");
2584
2585 if (tsi148_crcsr_init(tsi148_bridge, pdev)) {
2586 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2587 goto err_crcsr;
2588 }
2589
2590 retval = vme_register_bridge(tsi148_bridge);
2591 if (retval != 0) {
2592 dev_err(&pdev->dev, "Chip Registration failed.\n");
2593 goto err_reg;
2594 }
2595
2596 pci_set_drvdata(pdev, tsi148_bridge);
2597
2598 /* Clear VME bus "board fail", and "power-up reset" lines */
2599 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2600 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2601 data |= TSI148_LCSR_VSTAT_CPURST;
2602 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
2603
2604 return 0;
2605
2606err_reg:
2607 tsi148_crcsr_exit(tsi148_bridge, pdev);
2608err_crcsr:
2609err_lm:
2610 /* resources are stored in link list */
2611 list_for_each_safe(pos, n, &tsi148_bridge->lm_resources) {
2612 lm = list_entry(pos, struct vme_lm_resource, list);
2613 list_del(pos);
2614 kfree(lm);
2615 }
2616err_dma:
2617 /* resources are stored in link list */
2618 list_for_each_safe(pos, n, &tsi148_bridge->dma_resources) {
2619 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2620 list_del(pos);
2621 kfree(dma_ctrlr);
2622 }
2623err_slave:
2624 /* resources are stored in link list */
2625 list_for_each_safe(pos, n, &tsi148_bridge->slave_resources) {
2626 slave_image = list_entry(pos, struct vme_slave_resource, list);
2627 list_del(pos);
2628 kfree(slave_image);
2629 }
2630err_master:
2631 /* resources are stored in link list */
2632 list_for_each_safe(pos, n, &tsi148_bridge->master_resources) {
2633 master_image = list_entry(pos, struct vme_master_resource,
2634 list);
2635 list_del(pos);
2636 kfree(master_image);
2637 }
2638
2639 tsi148_irq_exit(tsi148_bridge, pdev);
2640err_irq:
2641err_test:
2642 iounmap(tsi148_device->base);
2643err_remap:
2644 pci_release_regions(pdev);
2645err_resource:
2646 pci_disable_device(pdev);
2647err_enable:
2648 kfree(tsi148_device);
2649err_driver:
2650 kfree(tsi148_bridge);
2651err_struct:
2652 return retval;
2653
2654}
2655
2656static void tsi148_remove(struct pci_dev *pdev)
2657{
2658 struct list_head *pos = NULL;
2659 struct list_head *tmplist;
2660 struct vme_master_resource *master_image;
2661 struct vme_slave_resource *slave_image;
2662 struct vme_dma_resource *dma_ctrlr;
2663 int i;
2664 struct tsi148_driver *bridge;
2665 struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2666
2667 bridge = tsi148_bridge->driver_priv;
2668
2669
2670 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2671
2672 /*
2673 * Shutdown all inbound and outbound windows.
2674 */
2675 for (i = 0; i < 8; i++) {
2676 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2677 TSI148_LCSR_OFFSET_ITAT);
2678 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2679 TSI148_LCSR_OFFSET_OTAT);
2680 }
2681
2682 /*
2683 * Shutdown Location monitor.
2684 */
2685 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2686
2687 /*
2688 * Shutdown CRG map.
2689 */
2690 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2691
2692 /*
2693 * Clear error status.
2694 */
2695 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2696 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2697 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2698
2699 /*
2700 * Remove VIRQ interrupt (if any)
2701 */
2702 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2703 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2704
2705 /*
2706 * Map all Interrupts to PCI INTA
2707 */
2708 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2709 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2710
2711 tsi148_irq_exit(tsi148_bridge, pdev);
2712
2713 vme_unregister_bridge(tsi148_bridge);
2714
2715 tsi148_crcsr_exit(tsi148_bridge, pdev);
2716
2717 /* resources are stored in link list */
2718 list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) {
2719 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2720 list_del(pos);
2721 kfree(dma_ctrlr);
2722 }
2723
2724 /* resources are stored in link list */
2725 list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) {
2726 slave_image = list_entry(pos, struct vme_slave_resource, list);
2727 list_del(pos);
2728 kfree(slave_image);
2729 }
2730
2731 /* resources are stored in link list */
2732 list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) {
2733 master_image = list_entry(pos, struct vme_master_resource,
2734 list);
2735 list_del(pos);
2736 kfree(master_image);
2737 }
2738
2739 iounmap(bridge->base);
2740
2741 pci_release_regions(pdev);
2742
2743 pci_disable_device(pdev);
2744
2745 kfree(tsi148_bridge->driver_priv);
2746
2747 kfree(tsi148_bridge);
2748}
2749
2750module_pci_driver(tsi148_driver);
2751
2752MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2753module_param(err_chk, bool, 0);
2754
2755MODULE_PARM_DESC(geoid, "Override geographical addressing");
2756module_param(geoid, int, 0);
2757
2758MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2759MODULE_LICENSE("GPL");
diff --git a/drivers/vme/bridges/vme_tsi148.h b/drivers/vme/bridges/vme_tsi148.h
deleted file mode 100644
index f5ed14382a8..00000000000
--- a/drivers/vme/bridges/vme_tsi148.h
+++ /dev/null
@@ -1,1410 +0,0 @@
1/*
2 * tsi148.h
3 *
4 * Support for the Tundra TSI148 VME Bridge chip
5 *
6 * Author: Tom Armistead
7 * Updated and maintained by Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifndef TSI148_H
17#define TSI148_H
18
19#ifndef PCI_VENDOR_ID_TUNDRA
20#define PCI_VENDOR_ID_TUNDRA 0x10e3
21#endif
22
23#ifndef PCI_DEVICE_ID_TUNDRA_TSI148
24#define PCI_DEVICE_ID_TUNDRA_TSI148 0x148
25#endif
26
27/*
28 * Define the number of each that the Tsi148 supports.
29 */
30#define TSI148_MAX_MASTER 8 /* Max Master Windows */
31#define TSI148_MAX_SLAVE 8 /* Max Slave Windows */
32#define TSI148_MAX_DMA 2 /* Max DMA Controllers */
33#define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */
34#define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */
35
36/* Structure used to hold driver specific information */
37struct tsi148_driver {
38 void __iomem *base; /* Base Address of device registers */
39 wait_queue_head_t dma_queue[2];
40 wait_queue_head_t iack_queue;
41 void (*lm_callback[4])(int); /* Called in interrupt handler */
42 void *crcsr_kernel;
43 dma_addr_t crcsr_bus;
44 struct vme_master_resource *flush_image;
45 struct mutex vme_rmw; /* Only one RMW cycle at a time */
46 struct mutex vme_int; /*
47 * Only one VME interrupt can be
48 * generated at a time, provide locking
49 */
50};
51
52/*
53 * Layout of a DMAC Linked-List Descriptor
54 *
55 * Note: This structure is accessed via the chip and therefore must be
56 * correctly laid out - It must also be aligned on 64-bit boundaries.
57 */
58struct tsi148_dma_descriptor {
59 __be32 dsau; /* Source Address */
60 __be32 dsal;
61 __be32 ddau; /* Destination Address */
62 __be32 ddal;
63 __be32 dsat; /* Source attributes */
64 __be32 ddat; /* Destination attributes */
65 __be32 dnlau; /* Next link address */
66 __be32 dnlal;
67 __be32 dcnt; /* Byte count */
68 __be32 ddbs; /* 2eSST Broadcast select */
69};
70
71struct tsi148_dma_entry {
72 /*
73 * The descriptor needs to be aligned on a 64-bit boundary, we increase
74 * the chance of this by putting it first in the structure.
75 */
76 struct tsi148_dma_descriptor descriptor;
77 struct list_head list;
78 dma_addr_t dma_handle;
79};
80
81/*
82 * TSI148 ASIC register structure overlays and bit field definitions.
83 *
84 * Note: Tsi148 Register Group (CRG) consists of the following
85 * combination of registers:
86 * PCFS - PCI Configuration Space Registers
87 * LCSR - Local Control and Status Registers
88 * GCSR - Global Control and Status Registers
89 * CR/CSR - Subset of Configuration ROM /
90 * Control and Status Registers
91 */
92
93
94/*
95 * Command/Status Registers (CRG + $004)
96 */
97#define TSI148_PCFS_ID 0x0
98#define TSI148_PCFS_CSR 0x4
99#define TSI148_PCFS_CLASS 0x8
100#define TSI148_PCFS_MISC0 0xC
101#define TSI148_PCFS_MBARL 0x10
102#define TSI148_PCFS_MBARU 0x14
103
104#define TSI148_PCFS_SUBID 0x28
105
106#define TSI148_PCFS_CAPP 0x34
107
108#define TSI148_PCFS_MISC1 0x3C
109
110#define TSI148_PCFS_XCAPP 0x40
111#define TSI148_PCFS_XSTAT 0x44
112
113/*
114 * LCSR definitions
115 */
116
117/*
118 * Outbound Translations
119 */
120#define TSI148_LCSR_OT0_OTSAU 0x100
121#define TSI148_LCSR_OT0_OTSAL 0x104
122#define TSI148_LCSR_OT0_OTEAU 0x108
123#define TSI148_LCSR_OT0_OTEAL 0x10C
124#define TSI148_LCSR_OT0_OTOFU 0x110
125#define TSI148_LCSR_OT0_OTOFL 0x114
126#define TSI148_LCSR_OT0_OTBS 0x118
127#define TSI148_LCSR_OT0_OTAT 0x11C
128
129#define TSI148_LCSR_OT1_OTSAU 0x120
130#define TSI148_LCSR_OT1_OTSAL 0x124
131#define TSI148_LCSR_OT1_OTEAU 0x128
132#define TSI148_LCSR_OT1_OTEAL 0x12C
133#define TSI148_LCSR_OT1_OTOFU 0x130
134#define TSI148_LCSR_OT1_OTOFL 0x134
135#define TSI148_LCSR_OT1_OTBS 0x138
136#define TSI148_LCSR_OT1_OTAT 0x13C
137
138#define TSI148_LCSR_OT2_OTSAU 0x140
139#define TSI148_LCSR_OT2_OTSAL 0x144
140#define TSI148_LCSR_OT2_OTEAU 0x148
141#define TSI148_LCSR_OT2_OTEAL 0x14C
142#define TSI148_LCSR_OT2_OTOFU 0x150
143#define TSI148_LCSR_OT2_OTOFL 0x154
144#define TSI148_LCSR_OT2_OTBS 0x158
145#define TSI148_LCSR_OT2_OTAT 0x15C
146
147#define TSI148_LCSR_OT3_OTSAU 0x160
148#define TSI148_LCSR_OT3_OTSAL 0x164
149#define TSI148_LCSR_OT3_OTEAU 0x168
150#define TSI148_LCSR_OT3_OTEAL 0x16C
151#define TSI148_LCSR_OT3_OTOFU 0x170
152#define TSI148_LCSR_OT3_OTOFL 0x174
153#define TSI148_LCSR_OT3_OTBS 0x178
154#define TSI148_LCSR_OT3_OTAT 0x17C
155
156#define TSI148_LCSR_OT4_OTSAU 0x180
157#define TSI148_LCSR_OT4_OTSAL 0x184
158#define TSI148_LCSR_OT4_OTEAU 0x188
159#define TSI148_LCSR_OT4_OTEAL 0x18C
160#define TSI148_LCSR_OT4_OTOFU 0x190
161#define TSI148_LCSR_OT4_OTOFL 0x194
162#define TSI148_LCSR_OT4_OTBS 0x198
163#define TSI148_LCSR_OT4_OTAT 0x19C
164
165#define TSI148_LCSR_OT5_OTSAU 0x1A0
166#define TSI148_LCSR_OT5_OTSAL 0x1A4
167#define TSI148_LCSR_OT5_OTEAU 0x1A8
168#define TSI148_LCSR_OT5_OTEAL 0x1AC
169#define TSI148_LCSR_OT5_OTOFU 0x1B0
170#define TSI148_LCSR_OT5_OTOFL 0x1B4
171#define TSI148_LCSR_OT5_OTBS 0x1B8
172#define TSI148_LCSR_OT5_OTAT 0x1BC
173
174#define TSI148_LCSR_OT6_OTSAU 0x1C0
175#define TSI148_LCSR_OT6_OTSAL 0x1C4
176#define TSI148_LCSR_OT6_OTEAU 0x1C8
177#define TSI148_LCSR_OT6_OTEAL 0x1CC
178#define TSI148_LCSR_OT6_OTOFU 0x1D0
179#define TSI148_LCSR_OT6_OTOFL 0x1D4
180#define TSI148_LCSR_OT6_OTBS 0x1D8
181#define TSI148_LCSR_OT6_OTAT 0x1DC
182
183#define TSI148_LCSR_OT7_OTSAU 0x1E0
184#define TSI148_LCSR_OT7_OTSAL 0x1E4
185#define TSI148_LCSR_OT7_OTEAU 0x1E8
186#define TSI148_LCSR_OT7_OTEAL 0x1EC
187#define TSI148_LCSR_OT7_OTOFU 0x1F0
188#define TSI148_LCSR_OT7_OTOFL 0x1F4
189#define TSI148_LCSR_OT7_OTBS 0x1F8
190#define TSI148_LCSR_OT7_OTAT 0x1FC
191
192#define TSI148_LCSR_OT0 0x100
193#define TSI148_LCSR_OT1 0x120
194#define TSI148_LCSR_OT2 0x140
195#define TSI148_LCSR_OT3 0x160
196#define TSI148_LCSR_OT4 0x180
197#define TSI148_LCSR_OT5 0x1A0
198#define TSI148_LCSR_OT6 0x1C0
199#define TSI148_LCSR_OT7 0x1E0
200
201static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
202 TSI148_LCSR_OT2, TSI148_LCSR_OT3,
203 TSI148_LCSR_OT4, TSI148_LCSR_OT5,
204 TSI148_LCSR_OT6, TSI148_LCSR_OT7 };
205
206#define TSI148_LCSR_OFFSET_OTSAU 0x0
207#define TSI148_LCSR_OFFSET_OTSAL 0x4
208#define TSI148_LCSR_OFFSET_OTEAU 0x8
209#define TSI148_LCSR_OFFSET_OTEAL 0xC
210#define TSI148_LCSR_OFFSET_OTOFU 0x10
211#define TSI148_LCSR_OFFSET_OTOFL 0x14
212#define TSI148_LCSR_OFFSET_OTBS 0x18
213#define TSI148_LCSR_OFFSET_OTAT 0x1C
214
215/*
216 * VMEbus interrupt ack
217 * offset 200
218 */
219#define TSI148_LCSR_VIACK1 0x204
220#define TSI148_LCSR_VIACK2 0x208
221#define TSI148_LCSR_VIACK3 0x20C
222#define TSI148_LCSR_VIACK4 0x210
223#define TSI148_LCSR_VIACK5 0x214
224#define TSI148_LCSR_VIACK6 0x218
225#define TSI148_LCSR_VIACK7 0x21C
226
227static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
228 TSI148_LCSR_VIACK2, TSI148_LCSR_VIACK3,
229 TSI148_LCSR_VIACK4, TSI148_LCSR_VIACK5,
230 TSI148_LCSR_VIACK6, TSI148_LCSR_VIACK7 };
231
232/*
233 * RMW
234 * offset 220
235 */
236#define TSI148_LCSR_RMWAU 0x220
237#define TSI148_LCSR_RMWAL 0x224
238#define TSI148_LCSR_RMWEN 0x228
239#define TSI148_LCSR_RMWC 0x22C
240#define TSI148_LCSR_RMWS 0x230
241
242/*
243 * VMEbus control
244 * offset 234
245 */
246#define TSI148_LCSR_VMCTRL 0x234
247#define TSI148_LCSR_VCTRL 0x238
248#define TSI148_LCSR_VSTAT 0x23C
249
250/*
251 * PCI status
252 * offset 240
253 */
254#define TSI148_LCSR_PSTAT 0x240
255
256/*
257 * VME filter.
258 * offset 250
259 */
260#define TSI148_LCSR_VMEFL 0x250
261
262 /*
263 * VME exception.
264 * offset 260
265 */
266#define TSI148_LCSR_VEAU 0x260
267#define TSI148_LCSR_VEAL 0x264
268#define TSI148_LCSR_VEAT 0x268
269
270 /*
271 * PCI error
272 * offset 270
273 */
274#define TSI148_LCSR_EDPAU 0x270
275#define TSI148_LCSR_EDPAL 0x274
276#define TSI148_LCSR_EDPXA 0x278
277#define TSI148_LCSR_EDPXS 0x27C
278#define TSI148_LCSR_EDPAT 0x280
279
280 /*
281 * Inbound Translations
282 * offset 300
283 */
284#define TSI148_LCSR_IT0_ITSAU 0x300
285#define TSI148_LCSR_IT0_ITSAL 0x304
286#define TSI148_LCSR_IT0_ITEAU 0x308
287#define TSI148_LCSR_IT0_ITEAL 0x30C
288#define TSI148_LCSR_IT0_ITOFU 0x310
289#define TSI148_LCSR_IT0_ITOFL 0x314
290#define TSI148_LCSR_IT0_ITAT 0x318
291
292#define TSI148_LCSR_IT1_ITSAU 0x320
293#define TSI148_LCSR_IT1_ITSAL 0x324
294#define TSI148_LCSR_IT1_ITEAU 0x328
295#define TSI148_LCSR_IT1_ITEAL 0x32C
296#define TSI148_LCSR_IT1_ITOFU 0x330
297#define TSI148_LCSR_IT1_ITOFL 0x334
298#define TSI148_LCSR_IT1_ITAT 0x338
299
300#define TSI148_LCSR_IT2_ITSAU 0x340
301#define TSI148_LCSR_IT2_ITSAL 0x344
302#define TSI148_LCSR_IT2_ITEAU 0x348
303#define TSI148_LCSR_IT2_ITEAL 0x34C
304#define TSI148_LCSR_IT2_ITOFU 0x350
305#define TSI148_LCSR_IT2_ITOFL 0x354
306#define TSI148_LCSR_IT2_ITAT 0x358
307
308#define TSI148_LCSR_IT3_ITSAU 0x360
309#define TSI148_LCSR_IT3_ITSAL 0x364
310#define TSI148_LCSR_IT3_ITEAU 0x368
311#define TSI148_LCSR_IT3_ITEAL 0x36C
312#define TSI148_LCSR_IT3_ITOFU 0x370
313#define TSI148_LCSR_IT3_ITOFL 0x374
314#define TSI148_LCSR_IT3_ITAT 0x378
315
316#define TSI148_LCSR_IT4_ITSAU 0x380
317#define TSI148_LCSR_IT4_ITSAL 0x384
318#define TSI148_LCSR_IT4_ITEAU 0x388
319#define TSI148_LCSR_IT4_ITEAL 0x38C
320#define TSI148_LCSR_IT4_ITOFU 0x390
321#define TSI148_LCSR_IT4_ITOFL 0x394
322#define TSI148_LCSR_IT4_ITAT 0x398
323
324#define TSI148_LCSR_IT5_ITSAU 0x3A0
325#define TSI148_LCSR_IT5_ITSAL 0x3A4
326#define TSI148_LCSR_IT5_ITEAU 0x3A8
327#define TSI148_LCSR_IT5_ITEAL 0x3AC
328#define TSI148_LCSR_IT5_ITOFU 0x3B0
329#define TSI148_LCSR_IT5_ITOFL 0x3B4
330#define TSI148_LCSR_IT5_ITAT 0x3B8
331
332#define TSI148_LCSR_IT6_ITSAU 0x3C0
333#define TSI148_LCSR_IT6_ITSAL 0x3C4
334#define TSI148_LCSR_IT6_ITEAU 0x3C8
335#define TSI148_LCSR_IT6_ITEAL 0x3CC
336#define TSI148_LCSR_IT6_ITOFU 0x3D0
337#define TSI148_LCSR_IT6_ITOFL 0x3D4
338#define TSI148_LCSR_IT6_ITAT 0x3D8
339
340#define TSI148_LCSR_IT7_ITSAU 0x3E0
341#define TSI148_LCSR_IT7_ITSAL 0x3E4
342#define TSI148_LCSR_IT7_ITEAU 0x3E8
343#define TSI148_LCSR_IT7_ITEAL 0x3EC
344#define TSI148_LCSR_IT7_ITOFU 0x3F0
345#define TSI148_LCSR_IT7_ITOFL 0x3F4
346#define TSI148_LCSR_IT7_ITAT 0x3F8
347
348
349#define TSI148_LCSR_IT0 0x300
350#define TSI148_LCSR_IT1 0x320
351#define TSI148_LCSR_IT2 0x340
352#define TSI148_LCSR_IT3 0x360
353#define TSI148_LCSR_IT4 0x380
354#define TSI148_LCSR_IT5 0x3A0
355#define TSI148_LCSR_IT6 0x3C0
356#define TSI148_LCSR_IT7 0x3E0
357
358static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
359 TSI148_LCSR_IT2, TSI148_LCSR_IT3,
360 TSI148_LCSR_IT4, TSI148_LCSR_IT5,
361 TSI148_LCSR_IT6, TSI148_LCSR_IT7 };
362
363#define TSI148_LCSR_OFFSET_ITSAU 0x0
364#define TSI148_LCSR_OFFSET_ITSAL 0x4
365#define TSI148_LCSR_OFFSET_ITEAU 0x8
366#define TSI148_LCSR_OFFSET_ITEAL 0xC
367#define TSI148_LCSR_OFFSET_ITOFU 0x10
368#define TSI148_LCSR_OFFSET_ITOFL 0x14
369#define TSI148_LCSR_OFFSET_ITAT 0x18
370
371 /*
372 * Inbound Translation GCSR
373 * offset 400
374 */
375#define TSI148_LCSR_GBAU 0x400
376#define TSI148_LCSR_GBAL 0x404
377#define TSI148_LCSR_GCSRAT 0x408
378
379 /*
380 * Inbound Translation CRG
381 * offset 40C
382 */
383#define TSI148_LCSR_CBAU 0x40C
384#define TSI148_LCSR_CBAL 0x410
385#define TSI148_LCSR_CSRAT 0x414
386
387 /*
388 * Inbound Translation CR/CSR
389 * CRG
390 * offset 418
391 */
392#define TSI148_LCSR_CROU 0x418
393#define TSI148_LCSR_CROL 0x41C
394#define TSI148_LCSR_CRAT 0x420
395
396 /*
397 * Inbound Translation Location Monitor
398 * offset 424
399 */
400#define TSI148_LCSR_LMBAU 0x424
401#define TSI148_LCSR_LMBAL 0x428
402#define TSI148_LCSR_LMAT 0x42C
403
404 /*
405 * VMEbus Interrupt Control.
406 * offset 430
407 */
408#define TSI148_LCSR_BCU 0x430
409#define TSI148_LCSR_BCL 0x434
410#define TSI148_LCSR_BPGTR 0x438
411#define TSI148_LCSR_BPCTR 0x43C
412#define TSI148_LCSR_VICR 0x440
413
414 /*
415 * Local Bus Interrupt Control.
416 * offset 448
417 */
418#define TSI148_LCSR_INTEN 0x448
419#define TSI148_LCSR_INTEO 0x44C
420#define TSI148_LCSR_INTS 0x450
421#define TSI148_LCSR_INTC 0x454
422#define TSI148_LCSR_INTM1 0x458
423#define TSI148_LCSR_INTM2 0x45C
424
425 /*
426 * DMA Controllers
427 * offset 500
428 */
429#define TSI148_LCSR_DCTL0 0x500
430#define TSI148_LCSR_DSTA0 0x504
431#define TSI148_LCSR_DCSAU0 0x508
432#define TSI148_LCSR_DCSAL0 0x50C
433#define TSI148_LCSR_DCDAU0 0x510
434#define TSI148_LCSR_DCDAL0 0x514
435#define TSI148_LCSR_DCLAU0 0x518
436#define TSI148_LCSR_DCLAL0 0x51C
437#define TSI148_LCSR_DSAU0 0x520
438#define TSI148_LCSR_DSAL0 0x524
439#define TSI148_LCSR_DDAU0 0x528
440#define TSI148_LCSR_DDAL0 0x52C
441#define TSI148_LCSR_DSAT0 0x530
442#define TSI148_LCSR_DDAT0 0x534
443#define TSI148_LCSR_DNLAU0 0x538
444#define TSI148_LCSR_DNLAL0 0x53C
445#define TSI148_LCSR_DCNT0 0x540
446#define TSI148_LCSR_DDBS0 0x544
447
448#define TSI148_LCSR_DCTL1 0x580
449#define TSI148_LCSR_DSTA1 0x584
450#define TSI148_LCSR_DCSAU1 0x588
451#define TSI148_LCSR_DCSAL1 0x58C
452#define TSI148_LCSR_DCDAU1 0x590
453#define TSI148_LCSR_DCDAL1 0x594
454#define TSI148_LCSR_DCLAU1 0x598
455#define TSI148_LCSR_DCLAL1 0x59C
456#define TSI148_LCSR_DSAU1 0x5A0
457#define TSI148_LCSR_DSAL1 0x5A4
458#define TSI148_LCSR_DDAU1 0x5A8
459#define TSI148_LCSR_DDAL1 0x5AC
460#define TSI148_LCSR_DSAT1 0x5B0
461#define TSI148_LCSR_DDAT1 0x5B4
462#define TSI148_LCSR_DNLAU1 0x5B8
463#define TSI148_LCSR_DNLAL1 0x5BC
464#define TSI148_LCSR_DCNT1 0x5C0
465#define TSI148_LCSR_DDBS1 0x5C4
466
467#define TSI148_LCSR_DMA0 0x500
468#define TSI148_LCSR_DMA1 0x580
469
470
471static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0,
472 TSI148_LCSR_DMA1 };
473
474#define TSI148_LCSR_OFFSET_DCTL 0x0
475#define TSI148_LCSR_OFFSET_DSTA 0x4
476#define TSI148_LCSR_OFFSET_DCSAU 0x8
477#define TSI148_LCSR_OFFSET_DCSAL 0xC
478#define TSI148_LCSR_OFFSET_DCDAU 0x10
479#define TSI148_LCSR_OFFSET_DCDAL 0x14
480#define TSI148_LCSR_OFFSET_DCLAU 0x18
481#define TSI148_LCSR_OFFSET_DCLAL 0x1C
482#define TSI148_LCSR_OFFSET_DSAU 0x20
483#define TSI148_LCSR_OFFSET_DSAL 0x24
484#define TSI148_LCSR_OFFSET_DDAU 0x28
485#define TSI148_LCSR_OFFSET_DDAL 0x2C
486#define TSI148_LCSR_OFFSET_DSAT 0x30
487#define TSI148_LCSR_OFFSET_DDAT 0x34
488#define TSI148_LCSR_OFFSET_DNLAU 0x38
489#define TSI148_LCSR_OFFSET_DNLAL 0x3C
490#define TSI148_LCSR_OFFSET_DCNT 0x40
491#define TSI148_LCSR_OFFSET_DDBS 0x44
492
493 /*
494 * GCSR Register Group
495 */
496
497 /*
498 * GCSR CRG
499 * offset 00 600 - DEVI/VENI
500 * offset 04 604 - CTRL/GA/REVID
501 * offset 08 608 - Semaphore3/2/1/0
502 * offset 0C 60C - Seamphore7/6/5/4
503 */
504#define TSI148_GCSR_ID 0x600
505#define TSI148_GCSR_CSR 0x604
506#define TSI148_GCSR_SEMA0 0x608
507#define TSI148_GCSR_SEMA1 0x60C
508
509 /*
510 * Mail Box
511 * GCSR CRG
512 * offset 10 610 - Mailbox0
513 */
514#define TSI148_GCSR_MBOX0 0x610
515#define TSI148_GCSR_MBOX1 0x614
516#define TSI148_GCSR_MBOX2 0x618
517#define TSI148_GCSR_MBOX3 0x61C
518
519static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
520 TSI148_GCSR_MBOX1,
521 TSI148_GCSR_MBOX2,
522 TSI148_GCSR_MBOX3 };
523
524 /*
525 * CR/CSR
526 */
527
528 /*
529 * CR/CSR CRG
530 * offset 7FFF4 FF4 - CSRBCR
531 * offset 7FFF8 FF8 - CSRBSR
532 * offset 7FFFC FFC - CBAR
533 */
534#define TSI148_CSRBCR 0xFF4
535#define TSI148_CSRBSR 0xFF8
536#define TSI148_CBAR 0xFFC
537
538
539
540
541 /*
542 * TSI148 Register Bit Definitions
543 */
544
545 /*
546 * PFCS Register Set
547 */
548#define TSI148_PCFS_CMMD_SERR (1<<8) /* SERR_L out pin ssys err */
549#define TSI148_PCFS_CMMD_PERR (1<<6) /* PERR_L out pin parity */
550#define TSI148_PCFS_CMMD_MSTR (1<<2) /* PCI bus master */
551#define TSI148_PCFS_CMMD_MEMSP (1<<1) /* PCI mem space access */
552#define TSI148_PCFS_CMMD_IOSP (1<<0) /* PCI I/O space enable */
553
554#define TSI148_PCFS_STAT_RCPVE (1<<15) /* Detected Parity Error */
555#define TSI148_PCFS_STAT_SIGSE (1<<14) /* Signalled System Error */
556#define TSI148_PCFS_STAT_RCVMA (1<<13) /* Received Master Abort */
557#define TSI148_PCFS_STAT_RCVTA (1<<12) /* Received Target Abort */
558#define TSI148_PCFS_STAT_SIGTA (1<<11) /* Signalled Target Abort */
559#define TSI148_PCFS_STAT_SELTIM (3<<9) /* DELSEL Timing */
560#define TSI148_PCFS_STAT_DPAR (1<<8) /* Data Parity Err Reported */
561#define TSI148_PCFS_STAT_FAST (1<<7) /* Fast back-to-back Cap */
562#define TSI148_PCFS_STAT_P66M (1<<5) /* 66 MHz Capable */
563#define TSI148_PCFS_STAT_CAPL (1<<4) /* Capab List - address $34 */
564
565/*
566 * Revision ID/Class Code Registers (CRG +$008)
567 */
568#define TSI148_PCFS_CLAS_M (0xFF<<24) /* Class ID */
569#define TSI148_PCFS_SUBCLAS_M (0xFF<<16) /* Sub-Class ID */
570#define TSI148_PCFS_PROGIF_M (0xFF<<8) /* Sub-Class ID */
571#define TSI148_PCFS_REVID_M (0xFF<<0) /* Rev ID */
572
573/*
574 * Cache Line Size/ Master Latency Timer/ Header Type Registers (CRG + $00C)
575 */
576#define TSI148_PCFS_HEAD_M (0xFF<<16) /* Master Lat Timer */
577#define TSI148_PCFS_MLAT_M (0xFF<<8) /* Master Lat Timer */
578#define TSI148_PCFS_CLSZ_M (0xFF<<0) /* Cache Line Size */
579
580/*
581 * Memory Base Address Lower Reg (CRG + $010)
582 */
583#define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12) /* Base Addr Lower Mask */
584#define TSI148_PCFS_MBARL_PRE (1<<3) /* Prefetch */
585#define TSI148_PCFS_MBARL_MTYPE_M (3<<1) /* Memory Type Mask */
586#define TSI148_PCFS_MBARL_IOMEM (1<<0) /* I/O Space Indicator */
587
588/*
589 * Message Signaled Interrupt Capabilities Register (CRG + $040)
590 */
591#define TSI148_PCFS_MSICAP_64BAC (1<<7) /* 64-bit Address Capable */
592#define TSI148_PCFS_MSICAP_MME_M (7<<4) /* Multiple Msg Enable Mask */
593#define TSI148_PCFS_MSICAP_MMC_M (7<<1) /* Multiple Msg Capable Mask */
594#define TSI148_PCFS_MSICAP_MSIEN (1<<0) /* Msg signaled INT Enable */
595
596/*
597 * Message Address Lower Register (CRG +$044)
598 */
599#define TSI148_PCFS_MSIAL_M (0x3FFFFFFF<<2) /* Mask */
600
601/*
602 * Message Data Register (CRG + 4C)
603 */
604#define TSI148_PCFS_MSIMD_M (0xFFFF<<0) /* Mask */
605
606/*
607 * PCI-X Capabilities Register (CRG + $050)
608 */
609#define TSI148_PCFS_PCIXCAP_MOST_M (7<<4) /* Max outstanding Split Tran */
610#define TSI148_PCFS_PCIXCAP_MMRBC_M (3<<2) /* Max Mem Read byte cnt */
611#define TSI148_PCFS_PCIXCAP_ERO (1<<1) /* Enable Relaxed Ordering */
612#define TSI148_PCFS_PCIXCAP_DPERE (1<<0) /* Data Parity Recover Enable */
613
614/*
615 * PCI-X Status Register (CRG +$054)
616 */
617#define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Received Split Comp Error */
618#define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */
619#define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans
620 */
621#define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */
622#define TSI148_PCFS_PCIXSTAT_DC (1<<20) /* Device Complexity */
623#define TSI148_PCFS_PCIXSTAT_USC (1<<19) /* Unexpected Split comp */
624#define TSI148_PCFS_PCIXSTAT_SCD (1<<18) /* Split completion discard */
625#define TSI148_PCFS_PCIXSTAT_133C (1<<17) /* 133MHz capable */
626#define TSI148_PCFS_PCIXSTAT_64D (1<<16) /* 64 bit device */
627#define TSI148_PCFS_PCIXSTAT_BN_M (0xFF<<8) /* Bus number */
628#define TSI148_PCFS_PCIXSTAT_DN_M (0x1F<<3) /* Device number */
629#define TSI148_PCFS_PCIXSTAT_FN_M (7<<0) /* Function Number */
630
631/*
632 * LCSR Registers
633 */
634
635/*
636 * Outbound Translation Starting Address Lower
637 */
638#define TSI148_LCSR_OTSAL_M (0xFFFF<<16) /* Mask */
639
640/*
641 * Outbound Translation Ending Address Lower
642 */
643#define TSI148_LCSR_OTEAL_M (0xFFFF<<16) /* Mask */
644
645/*
646 * Outbound Translation Offset Lower
647 */
648#define TSI148_LCSR_OTOFFL_M (0xFFFF<<16) /* Mask */
649
650/*
651 * Outbound Translation 2eSST Broadcast Select
652 */
653#define TSI148_LCSR_OTBS_M (0xFFFFF<<0) /* Mask */
654
655/*
656 * Outbound Translation Attribute
657 */
658#define TSI148_LCSR_OTAT_EN (1<<31) /* Window Enable */
659#define TSI148_LCSR_OTAT_MRPFD (1<<18) /* Prefetch Disable */
660
661#define TSI148_LCSR_OTAT_PFS_M (3<<16) /* Prefetch Size Mask */
662#define TSI148_LCSR_OTAT_PFS_2 (0<<16) /* 2 Cache Lines P Size */
663#define TSI148_LCSR_OTAT_PFS_4 (1<<16) /* 4 Cache Lines P Size */
664#define TSI148_LCSR_OTAT_PFS_8 (2<<16) /* 8 Cache Lines P Size */
665#define TSI148_LCSR_OTAT_PFS_16 (3<<16) /* 16 Cache Lines P Size */
666
667#define TSI148_LCSR_OTAT_2eSSTM_M (7<<11) /* 2eSST Xfer Rate Mask */
668#define TSI148_LCSR_OTAT_2eSSTM_160 (0<<11) /* 160MB/s 2eSST Xfer Rate */
669#define TSI148_LCSR_OTAT_2eSSTM_267 (1<<11) /* 267MB/s 2eSST Xfer Rate */
670#define TSI148_LCSR_OTAT_2eSSTM_320 (2<<11) /* 320MB/s 2eSST Xfer Rate */
671
672#define TSI148_LCSR_OTAT_TM_M (7<<8) /* Xfer Protocol Mask */
673#define TSI148_LCSR_OTAT_TM_SCT (0<<8) /* SCT Xfer Protocol */
674#define TSI148_LCSR_OTAT_TM_BLT (1<<8) /* BLT Xfer Protocol */
675#define TSI148_LCSR_OTAT_TM_MBLT (2<<8) /* MBLT Xfer Protocol */
676#define TSI148_LCSR_OTAT_TM_2eVME (3<<8) /* 2eVME Xfer Protocol */
677#define TSI148_LCSR_OTAT_TM_2eSST (4<<8) /* 2eSST Xfer Protocol */
678#define TSI148_LCSR_OTAT_TM_2eSSTB (5<<8) /* 2eSST Bcast Xfer Protocol */
679
680#define TSI148_LCSR_OTAT_DBW_M (3<<6) /* Max Data Width */
681#define TSI148_LCSR_OTAT_DBW_16 (0<<6) /* 16-bit Data Width */
682#define TSI148_LCSR_OTAT_DBW_32 (1<<6) /* 32-bit Data Width */
683
684#define TSI148_LCSR_OTAT_SUP (1<<5) /* Supervisory Access */
685#define TSI148_LCSR_OTAT_PGM (1<<4) /* Program Access */
686
687#define TSI148_LCSR_OTAT_AMODE_M (0xf<<0) /* Address Mode Mask */
688#define TSI148_LCSR_OTAT_AMODE_A16 (0<<0) /* A16 Address Space */
689#define TSI148_LCSR_OTAT_AMODE_A24 (1<<0) /* A24 Address Space */
690#define TSI148_LCSR_OTAT_AMODE_A32 (2<<0) /* A32 Address Space */
691#define TSI148_LCSR_OTAT_AMODE_A64 (4<<0) /* A32 Address Space */
692#define TSI148_LCSR_OTAT_AMODE_CRCSR (5<<0) /* CR/CSR Address Space */
693#define TSI148_LCSR_OTAT_AMODE_USER1 (8<<0) /* User1 Address Space */
694#define TSI148_LCSR_OTAT_AMODE_USER2 (9<<0) /* User2 Address Space */
695#define TSI148_LCSR_OTAT_AMODE_USER3 (10<<0) /* User3 Address Space */
696#define TSI148_LCSR_OTAT_AMODE_USER4 (11<<0) /* User4 Address Space */
697
698/*
699 * VME Master Control Register CRG+$234
700 */
701#define TSI148_LCSR_VMCTRL_VSA (1<<27) /* VMEbus Stop Ack */
702#define TSI148_LCSR_VMCTRL_VS (1<<26) /* VMEbus Stop */
703#define TSI148_LCSR_VMCTRL_DHB (1<<25) /* Device Has Bus */
704#define TSI148_LCSR_VMCTRL_DWB (1<<24) /* Device Wants Bus */
705
706#define TSI148_LCSR_VMCTRL_RMWEN (1<<20) /* RMW Enable */
707
708#define TSI148_LCSR_VMCTRL_ATO_M (7<<16) /* Master Access Time-out Mask
709 */
710#define TSI148_LCSR_VMCTRL_ATO_32 (0<<16) /* 32 us */
711#define TSI148_LCSR_VMCTRL_ATO_128 (1<<16) /* 128 us */
712#define TSI148_LCSR_VMCTRL_ATO_512 (2<<16) /* 512 us */
713#define TSI148_LCSR_VMCTRL_ATO_2M (3<<16) /* 2 ms */
714#define TSI148_LCSR_VMCTRL_ATO_8M (4<<16) /* 8 ms */
715#define TSI148_LCSR_VMCTRL_ATO_32M (5<<16) /* 32 ms */
716#define TSI148_LCSR_VMCTRL_ATO_128M (6<<16) /* 128 ms */
717#define TSI148_LCSR_VMCTRL_ATO_DIS (7<<16) /* Disabled */
718
719#define TSI148_LCSR_VMCTRL_VTOFF_M (7<<12) /* VMEbus Master Time off */
720#define TSI148_LCSR_VMCTRL_VTOFF_0 (0<<12) /* 0us */
721#define TSI148_LCSR_VMCTRL_VTOFF_1 (1<<12) /* 1us */
722#define TSI148_LCSR_VMCTRL_VTOFF_2 (2<<12) /* 2us */
723#define TSI148_LCSR_VMCTRL_VTOFF_4 (3<<12) /* 4us */
724#define TSI148_LCSR_VMCTRL_VTOFF_8 (4<<12) /* 8us */
725#define TSI148_LCSR_VMCTRL_VTOFF_16 (5<<12) /* 16us */
726#define TSI148_LCSR_VMCTRL_VTOFF_32 (6<<12) /* 32us */
727#define TSI148_LCSR_VMCTRL_VTOFF_64 (7<<12) /* 64us */
728
729#define TSI148_LCSR_VMCTRL_VTON_M (7<<8) /* VMEbus Master Time On */
730#define TSI148_LCSR_VMCTRL_VTON_4 (0<<8) /* 8us */
731#define TSI148_LCSR_VMCTRL_VTON_8 (1<<8) /* 8us */
732#define TSI148_LCSR_VMCTRL_VTON_16 (2<<8) /* 16us */
733#define TSI148_LCSR_VMCTRL_VTON_32 (3<<8) /* 32us */
734#define TSI148_LCSR_VMCTRL_VTON_64 (4<<8) /* 64us */
735#define TSI148_LCSR_VMCTRL_VTON_128 (5<<8) /* 128us */
736#define TSI148_LCSR_VMCTRL_VTON_256 (6<<8) /* 256us */
737#define TSI148_LCSR_VMCTRL_VTON_512 (7<<8) /* 512us */
738
739#define TSI148_LCSR_VMCTRL_VREL_M (3<<3) /* VMEbus Master Rel Mode Mask
740 */
741#define TSI148_LCSR_VMCTRL_VREL_T_D (0<<3) /* Time on or Done */
742#define TSI148_LCSR_VMCTRL_VREL_T_R_D (1<<3) /* Time on and REQ or Done */
743#define TSI148_LCSR_VMCTRL_VREL_T_B_D (2<<3) /* Time on and BCLR or Done */
744#define TSI148_LCSR_VMCTRL_VREL_T_D_R (3<<3) /* Time on or Done and REQ */
745
746#define TSI148_LCSR_VMCTRL_VFAIR (1<<2) /* VMEbus Master Fair Mode */
747#define TSI148_LCSR_VMCTRL_VREQL_M (3<<0) /* VMEbus Master Req Level Mask
748 */
749
750/*
751 * VMEbus Control Register CRG+$238
752 */
753#define TSI148_LCSR_VCTRL_LRE (1<<31) /* Late Retry Enable */
754
755#define TSI148_LCSR_VCTRL_DLT_M (0xF<<24) /* Deadlock Timer */
756#define TSI148_LCSR_VCTRL_DLT_OFF (0<<24) /* Deadlock Timer Off */
757#define TSI148_LCSR_VCTRL_DLT_16 (1<<24) /* 16 VCLKS */
758#define TSI148_LCSR_VCTRL_DLT_32 (2<<24) /* 32 VCLKS */
759#define TSI148_LCSR_VCTRL_DLT_64 (3<<24) /* 64 VCLKS */
760#define TSI148_LCSR_VCTRL_DLT_128 (4<<24) /* 128 VCLKS */
761#define TSI148_LCSR_VCTRL_DLT_256 (5<<24) /* 256 VCLKS */
762#define TSI148_LCSR_VCTRL_DLT_512 (6<<24) /* 512 VCLKS */
763#define TSI148_LCSR_VCTRL_DLT_1024 (7<<24) /* 1024 VCLKS */
764#define TSI148_LCSR_VCTRL_DLT_2048 (8<<24) /* 2048 VCLKS */
765#define TSI148_LCSR_VCTRL_DLT_4096 (9<<24) /* 4096 VCLKS */
766#define TSI148_LCSR_VCTRL_DLT_8192 (0xA<<24) /* 8192 VCLKS */
767#define TSI148_LCSR_VCTRL_DLT_16384 (0xB<<24) /* 16384 VCLKS */
768#define TSI148_LCSR_VCTRL_DLT_32768 (0xC<<24) /* 32768 VCLKS */
769
770#define TSI148_LCSR_VCTRL_NERBB (1<<20) /* No Early Release of Bus Busy
771 */
772
773#define TSI148_LCSR_VCTRL_SRESET (1<<17) /* System Reset */
774#define TSI148_LCSR_VCTRL_LRESET (1<<16) /* Local Reset */
775
776#define TSI148_LCSR_VCTRL_SFAILAI (1<<15) /* SYSFAIL Auto Slot ID */
777#define TSI148_LCSR_VCTRL_BID_M (0x1F<<8) /* Broadcast ID Mask */
778
779#define TSI148_LCSR_VCTRL_ATOEN (1<<7) /* Arbiter Time-out Enable */
780#define TSI148_LCSR_VCTRL_ROBIN (1<<6) /* VMEbus Round Robin */
781
782#define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask
783 */
784#define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */
785#define TSI148_LCSR_VCTRL_GTO_16 (1<<0) /* 16 us */
786#define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */
787#define TSI148_LCSR_VCTRL_GTO_64 (3<<0) /* 64 us */
788#define TSI148_LCSR_VCTRL_GTO_128 (4<<0) /* 128 us */
789#define TSI148_LCSR_VCTRL_GTO_256 (5<<0) /* 256 us */
790#define TSI148_LCSR_VCTRL_GTO_512 (6<<0) /* 512 us */
791#define TSI148_LCSR_VCTRL_GTO_DIS (7<<0) /* Disabled */
792
793/*
794 * VMEbus Status Register CRG + $23C
795 */
796#define TSI148_LCSR_VSTAT_CPURST (1<<15) /* Clear power up reset */
797#define TSI148_LCSR_VSTAT_BRDFL (1<<14) /* Board fail */
798#define TSI148_LCSR_VSTAT_PURSTS (1<<12) /* Power up reset status */
799#define TSI148_LCSR_VSTAT_BDFAILS (1<<11) /* Board Fail Status */
800#define TSI148_LCSR_VSTAT_SYSFAILS (1<<10) /* System Fail Status */
801#define TSI148_LCSR_VSTAT_ACFAILS (1<<9) /* AC fail status */
802#define TSI148_LCSR_VSTAT_SCONS (1<<8) /* System Cont Status */
803#define TSI148_LCSR_VSTAT_GAP (1<<5) /* Geographic Addr Parity */
804#define TSI148_LCSR_VSTAT_GA_M (0x1F<<0) /* Geographic Addr Mask */
805
806/*
807 * PCI Configuration Status Register CRG+$240
808 */
809#define TSI148_LCSR_PSTAT_REQ64S (1<<6) /* Request 64 status set */
810#define TSI148_LCSR_PSTAT_M66ENS (1<<5) /* M66ENS 66Mhz enable */
811#define TSI148_LCSR_PSTAT_FRAMES (1<<4) /* Frame Status */
812#define TSI148_LCSR_PSTAT_IRDYS (1<<3) /* IRDY status */
813#define TSI148_LCSR_PSTAT_DEVSELS (1<<2) /* DEVL status */
814#define TSI148_LCSR_PSTAT_STOPS (1<<1) /* STOP status */
815#define TSI148_LCSR_PSTAT_TRDYS (1<<0) /* TRDY status */
816
817/*
818 * VMEbus Exception Attributes Register CRG + $268
819 */
820#define TSI148_LCSR_VEAT_VES (1<<31) /* Status */
821#define TSI148_LCSR_VEAT_VEOF (1<<30) /* Overflow */
822#define TSI148_LCSR_VEAT_VESCL (1<<29) /* Status Clear */
823#define TSI148_LCSR_VEAT_2EOT (1<<21) /* 2e Odd Termination */
824#define TSI148_LCSR_VEAT_2EST (1<<20) /* 2e Slave terminated */
825#define TSI148_LCSR_VEAT_BERR (1<<19) /* Bus Error */
826#define TSI148_LCSR_VEAT_LWORD (1<<18) /* LWORD_ signal state */
827#define TSI148_LCSR_VEAT_WRITE (1<<17) /* WRITE_ signal state */
828#define TSI148_LCSR_VEAT_IACK (1<<16) /* IACK_ signal state */
829#define TSI148_LCSR_VEAT_DS1 (1<<15) /* DS1_ signal state */
830#define TSI148_LCSR_VEAT_DS0 (1<<14) /* DS0_ signal state */
831#define TSI148_LCSR_VEAT_AM_M (0x3F<<8) /* Address Mode Mask */
832#define TSI148_LCSR_VEAT_XAM_M (0xFF<<0) /* Master AMode Mask */
833
834
835/*
836 * VMEbus PCI Error Diagnostics PCI/X Attributes Register CRG + $280
837 */
838#define TSI148_LCSR_EDPAT_EDPCL (1<<29)
839
840/*
841 * Inbound Translation Starting Address Lower
842 */
843#define TSI148_LCSR_ITSAL6432_M (0xFFFF<<16) /* Mask */
844#define TSI148_LCSR_ITSAL24_M (0x00FFF<<12) /* Mask */
845#define TSI148_LCSR_ITSAL16_M (0x0000FFF<<4) /* Mask */
846
847/*
848 * Inbound Translation Ending Address Lower
849 */
850#define TSI148_LCSR_ITEAL6432_M (0xFFFF<<16) /* Mask */
851#define TSI148_LCSR_ITEAL24_M (0x00FFF<<12) /* Mask */
852#define TSI148_LCSR_ITEAL16_M (0x0000FFF<<4) /* Mask */
853
854/*
855 * Inbound Translation Offset Lower
856 */
857#define TSI148_LCSR_ITOFFL6432_M (0xFFFF<<16) /* Mask */
858#define TSI148_LCSR_ITOFFL24_M (0xFFFFF<<12) /* Mask */
859#define TSI148_LCSR_ITOFFL16_M (0xFFFFFFF<<4) /* Mask */
860
861/*
862 * Inbound Translation Attribute
863 */
864#define TSI148_LCSR_ITAT_EN (1<<31) /* Window Enable */
865#define TSI148_LCSR_ITAT_TH (1<<18) /* Prefetch Threshold */
866
867#define TSI148_LCSR_ITAT_VFS_M (3<<16) /* Virtual FIFO Size Mask */
868#define TSI148_LCSR_ITAT_VFS_64 (0<<16) /* 64 bytes Virtual FIFO Size */
869#define TSI148_LCSR_ITAT_VFS_128 (1<<16) /* 128 bytes Virtual FIFO Sz */
870#define TSI148_LCSR_ITAT_VFS_256 (2<<16) /* 256 bytes Virtual FIFO Sz */
871#define TSI148_LCSR_ITAT_VFS_512 (3<<16) /* 512 bytes Virtual FIFO Sz */
872
873#define TSI148_LCSR_ITAT_2eSSTM_M (7<<12) /* 2eSST Xfer Rate Mask */
874#define TSI148_LCSR_ITAT_2eSSTM_160 (0<<12) /* 160MB/s 2eSST Xfer Rate */
875#define TSI148_LCSR_ITAT_2eSSTM_267 (1<<12) /* 267MB/s 2eSST Xfer Rate */
876#define TSI148_LCSR_ITAT_2eSSTM_320 (2<<12) /* 320MB/s 2eSST Xfer Rate */
877
878#define TSI148_LCSR_ITAT_2eSSTB (1<<11) /* 2eSST Bcast Xfer Protocol */
879#define TSI148_LCSR_ITAT_2eSST (1<<10) /* 2eSST Xfer Protocol */
880#define TSI148_LCSR_ITAT_2eVME (1<<9) /* 2eVME Xfer Protocol */
881#define TSI148_LCSR_ITAT_MBLT (1<<8) /* MBLT Xfer Protocol */
882#define TSI148_LCSR_ITAT_BLT (1<<7) /* BLT Xfer Protocol */
883
884#define TSI148_LCSR_ITAT_AS_M (7<<4) /* Address Space Mask */
885#define TSI148_LCSR_ITAT_AS_A16 (0<<4) /* A16 Address Space */
886#define TSI148_LCSR_ITAT_AS_A24 (1<<4) /* A24 Address Space */
887#define TSI148_LCSR_ITAT_AS_A32 (2<<4) /* A32 Address Space */
888#define TSI148_LCSR_ITAT_AS_A64 (4<<4) /* A64 Address Space */
889
890#define TSI148_LCSR_ITAT_SUPR (1<<3) /* Supervisor Access */
891#define TSI148_LCSR_ITAT_NPRIV (1<<2) /* Non-Priv (User) Access */
892#define TSI148_LCSR_ITAT_PGM (1<<1) /* Program Access */
893#define TSI148_LCSR_ITAT_DATA (1<<0) /* Data Access */
894
895/*
896 * GCSR Base Address Lower Address CRG +$404
897 */
898#define TSI148_LCSR_GBAL_M (0x7FFFFFF<<5) /* Mask */
899
900/*
901 * GCSR Attribute Register CRG + $408
902 */
903#define TSI148_LCSR_GCSRAT_EN (1<<7) /* Enable access to GCSR */
904
905#define TSI148_LCSR_GCSRAT_AS_M (7<<4) /* Address Space Mask */
906#define TSI148_LCSR_GCSRAT_AS_A16 (0<<4) /* Address Space 16 */
907#define TSI148_LCSR_GCSRAT_AS_A24 (1<<4) /* Address Space 24 */
908#define TSI148_LCSR_GCSRAT_AS_A32 (2<<4) /* Address Space 32 */
909#define TSI148_LCSR_GCSRAT_AS_A64 (4<<4) /* Address Space 64 */
910
911#define TSI148_LCSR_GCSRAT_SUPR (1<<3) /* Sup set -GCSR decoder */
912#define TSI148_LCSR_GCSRAT_NPRIV (1<<2) /* Non-Privliged set - CGSR */
913#define TSI148_LCSR_GCSRAT_PGM (1<<1) /* Program set - GCSR decoder */
914#define TSI148_LCSR_GCSRAT_DATA (1<<0) /* DATA set GCSR decoder */
915
916/*
917 * CRG Base Address Lower Address CRG + $410
918 */
919#define TSI148_LCSR_CBAL_M (0xFFFFF<<12)
920
921/*
922 * CRG Attribute Register CRG + $414
923 */
924#define TSI148_LCSR_CRGAT_EN (1<<7) /* Enable PRG Access */
925
926#define TSI148_LCSR_CRGAT_AS_M (7<<4) /* Address Space */
927#define TSI148_LCSR_CRGAT_AS_A16 (0<<4) /* Address Space 16 */
928#define TSI148_LCSR_CRGAT_AS_A24 (1<<4) /* Address Space 24 */
929#define TSI148_LCSR_CRGAT_AS_A32 (2<<4) /* Address Space 32 */
930#define TSI148_LCSR_CRGAT_AS_A64 (4<<4) /* Address Space 64 */
931
932#define TSI148_LCSR_CRGAT_SUPR (1<<3) /* Supervisor Access */
933#define TSI148_LCSR_CRGAT_NPRIV (1<<2) /* Non-Privliged(User) Access */
934#define TSI148_LCSR_CRGAT_PGM (1<<1) /* Program Access */
935#define TSI148_LCSR_CRGAT_DATA (1<<0) /* Data Access */
936
937/*
938 * CR/CSR Offset Lower Register CRG + $41C
939 */
940#define TSI148_LCSR_CROL_M (0x1FFF<<19) /* Mask */
941
942/*
943 * CR/CSR Attribute register CRG + $420
944 */
945#define TSI148_LCSR_CRAT_EN (1<<7) /* Enable access to CR/CSR */
946
947/*
948 * Location Monitor base address lower register CRG + $428
949 */
950#define TSI148_LCSR_LMBAL_M (0x7FFFFFF<<5) /* Mask */
951
952/*
953 * Location Monitor Attribute Register CRG + $42C
954 */
955#define TSI148_LCSR_LMAT_EN (1<<7) /* Enable Location Monitor */
956
957#define TSI148_LCSR_LMAT_AS_M (7<<4) /* Address Space MASK */
958#define TSI148_LCSR_LMAT_AS_A16 (0<<4) /* A16 */
959#define TSI148_LCSR_LMAT_AS_A24 (1<<4) /* A24 */
960#define TSI148_LCSR_LMAT_AS_A32 (2<<4) /* A32 */
961#define TSI148_LCSR_LMAT_AS_A64 (4<<4) /* A64 */
962
963#define TSI148_LCSR_LMAT_SUPR (1<<3) /* Supervisor Access */
964#define TSI148_LCSR_LMAT_NPRIV (1<<2) /* Non-Priv (User) Access */
965#define TSI148_LCSR_LMAT_PGM (1<<1) /* Program Access */
966#define TSI148_LCSR_LMAT_DATA (1<<0) /* Data Access */
967
968/*
969 * Broadcast Pulse Generator Timer Register CRG + $438
970 */
971#define TSI148_LCSR_BPGTR_BPGT_M (0xFFFF<<0) /* Mask */
972
973/*
974 * Broadcast Programmable Clock Timer Register CRG + $43C
975 */
976#define TSI148_LCSR_BPCTR_BPCT_M (0xFFFFFF<<0) /* Mask */
977
978/*
979 * VMEbus Interrupt Control Register CRG + $43C
980 */
981#define TSI148_LCSR_VICR_CNTS_M (3<<22) /* Cntr Source MASK */
982#define TSI148_LCSR_VICR_CNTS_DIS (1<<22) /* Cntr Disable */
983#define TSI148_LCSR_VICR_CNTS_IRQ1 (2<<22) /* IRQ1 to Cntr */
984#define TSI148_LCSR_VICR_CNTS_IRQ2 (3<<22) /* IRQ2 to Cntr */
985
986#define TSI148_LCSR_VICR_EDGIS_M (3<<20) /* Edge interrupt MASK */
987#define TSI148_LCSR_VICR_EDGIS_DIS (1<<20) /* Edge interrupt Disable */
988#define TSI148_LCSR_VICR_EDGIS_IRQ1 (2<<20) /* IRQ1 to Edge */
989#define TSI148_LCSR_VICR_EDGIS_IRQ2 (3<<20) /* IRQ2 to Edge */
990
991#define TSI148_LCSR_VICR_IRQIF_M (3<<18) /* IRQ1* Function MASK */
992#define TSI148_LCSR_VICR_IRQIF_NORM (1<<18) /* Normal */
993#define TSI148_LCSR_VICR_IRQIF_PULSE (2<<18) /* Pulse Generator */
994#define TSI148_LCSR_VICR_IRQIF_PROG (3<<18) /* Programmable Clock */
995#define TSI148_LCSR_VICR_IRQIF_1U (4<<18) /* 1us Clock */
996
997#define TSI148_LCSR_VICR_IRQ2F_M (3<<16) /* IRQ2* Function MASK */
998#define TSI148_LCSR_VICR_IRQ2F_NORM (1<<16) /* Normal */
999#define TSI148_LCSR_VICR_IRQ2F_PULSE (2<<16) /* Pulse Generator */
1000#define TSI148_LCSR_VICR_IRQ2F_PROG (3<<16) /* Programmable Clock */
1001#define TSI148_LCSR_VICR_IRQ2F_1U (4<<16) /* 1us Clock */
1002
1003#define TSI148_LCSR_VICR_BIP (1<<15) /* Broadcast Interrupt Pulse */
1004
1005#define TSI148_LCSR_VICR_IRQC (1<<12) /* VMEbus IRQ Clear */
1006#define TSI148_LCSR_VICR_IRQS (1<<11) /* VMEbus IRQ Status */
1007
1008#define TSI148_LCSR_VICR_IRQL_M (7<<8) /* VMEbus SW IRQ Level Mask */
1009#define TSI148_LCSR_VICR_IRQL_1 (1<<8) /* VMEbus SW IRQ Level 1 */
1010#define TSI148_LCSR_VICR_IRQL_2 (2<<8) /* VMEbus SW IRQ Level 2 */
1011#define TSI148_LCSR_VICR_IRQL_3 (3<<8) /* VMEbus SW IRQ Level 3 */
1012#define TSI148_LCSR_VICR_IRQL_4 (4<<8) /* VMEbus SW IRQ Level 4 */
1013#define TSI148_LCSR_VICR_IRQL_5 (5<<8) /* VMEbus SW IRQ Level 5 */
1014#define TSI148_LCSR_VICR_IRQL_6 (6<<8) /* VMEbus SW IRQ Level 6 */
1015#define TSI148_LCSR_VICR_IRQL_7 (7<<8) /* VMEbus SW IRQ Level 7 */
1016
1017static const int TSI148_LCSR_VICR_IRQL[8] = { 0, TSI148_LCSR_VICR_IRQL_1,
1018 TSI148_LCSR_VICR_IRQL_2, TSI148_LCSR_VICR_IRQL_3,
1019 TSI148_LCSR_VICR_IRQL_4, TSI148_LCSR_VICR_IRQL_5,
1020 TSI148_LCSR_VICR_IRQL_6, TSI148_LCSR_VICR_IRQL_7 };
1021
1022#define TSI148_LCSR_VICR_STID_M (0xFF<<0) /* Status/ID Mask */
1023
1024/*
1025 * Interrupt Enable Register CRG + $440
1026 */
1027#define TSI148_LCSR_INTEN_DMA1EN (1<<25) /* DMAC 1 */
1028#define TSI148_LCSR_INTEN_DMA0EN (1<<24) /* DMAC 0 */
1029#define TSI148_LCSR_INTEN_LM3EN (1<<23) /* Location Monitor 3 */
1030#define TSI148_LCSR_INTEN_LM2EN (1<<22) /* Location Monitor 2 */
1031#define TSI148_LCSR_INTEN_LM1EN (1<<21) /* Location Monitor 1 */
1032#define TSI148_LCSR_INTEN_LM0EN (1<<20) /* Location Monitor 0 */
1033#define TSI148_LCSR_INTEN_MB3EN (1<<19) /* Mail Box 3 */
1034#define TSI148_LCSR_INTEN_MB2EN (1<<18) /* Mail Box 2 */
1035#define TSI148_LCSR_INTEN_MB1EN (1<<17) /* Mail Box 1 */
1036#define TSI148_LCSR_INTEN_MB0EN (1<<16) /* Mail Box 0 */
1037#define TSI148_LCSR_INTEN_PERREN (1<<13) /* PCI/X Error */
1038#define TSI148_LCSR_INTEN_VERREN (1<<12) /* VMEbus Error */
1039#define TSI148_LCSR_INTEN_VIEEN (1<<11) /* VMEbus IRQ Edge */
1040#define TSI148_LCSR_INTEN_IACKEN (1<<10) /* IACK */
1041#define TSI148_LCSR_INTEN_SYSFLEN (1<<9) /* System Fail */
1042#define TSI148_LCSR_INTEN_ACFLEN (1<<8) /* AC Fail */
1043#define TSI148_LCSR_INTEN_IRQ7EN (1<<7) /* IRQ7 */
1044#define TSI148_LCSR_INTEN_IRQ6EN (1<<6) /* IRQ6 */
1045#define TSI148_LCSR_INTEN_IRQ5EN (1<<5) /* IRQ5 */
1046#define TSI148_LCSR_INTEN_IRQ4EN (1<<4) /* IRQ4 */
1047#define TSI148_LCSR_INTEN_IRQ3EN (1<<3) /* IRQ3 */
1048#define TSI148_LCSR_INTEN_IRQ2EN (1<<2) /* IRQ2 */
1049#define TSI148_LCSR_INTEN_IRQ1EN (1<<1) /* IRQ1 */
1050
1051static const int TSI148_LCSR_INTEN_LMEN[4] = { TSI148_LCSR_INTEN_LM0EN,
1052 TSI148_LCSR_INTEN_LM1EN,
1053 TSI148_LCSR_INTEN_LM2EN,
1054 TSI148_LCSR_INTEN_LM3EN };
1055
1056static const int TSI148_LCSR_INTEN_IRQEN[7] = { TSI148_LCSR_INTEN_IRQ1EN,
1057 TSI148_LCSR_INTEN_IRQ2EN,
1058 TSI148_LCSR_INTEN_IRQ3EN,
1059 TSI148_LCSR_INTEN_IRQ4EN,
1060 TSI148_LCSR_INTEN_IRQ5EN,
1061 TSI148_LCSR_INTEN_IRQ6EN,
1062 TSI148_LCSR_INTEN_IRQ7EN };
1063
1064/*
1065 * Interrupt Enable Out Register CRG + $444
1066 */
1067#define TSI148_LCSR_INTEO_DMA1EO (1<<25) /* DMAC 1 */
1068#define TSI148_LCSR_INTEO_DMA0EO (1<<24) /* DMAC 0 */
1069#define TSI148_LCSR_INTEO_LM3EO (1<<23) /* Loc Monitor 3 */
1070#define TSI148_LCSR_INTEO_LM2EO (1<<22) /* Loc Monitor 2 */
1071#define TSI148_LCSR_INTEO_LM1EO (1<<21) /* Loc Monitor 1 */
1072#define TSI148_LCSR_INTEO_LM0EO (1<<20) /* Location Monitor 0 */
1073#define TSI148_LCSR_INTEO_MB3EO (1<<19) /* Mail Box 3 */
1074#define TSI148_LCSR_INTEO_MB2EO (1<<18) /* Mail Box 2 */
1075#define TSI148_LCSR_INTEO_MB1EO (1<<17) /* Mail Box 1 */
1076#define TSI148_LCSR_INTEO_MB0EO (1<<16) /* Mail Box 0 */
1077#define TSI148_LCSR_INTEO_PERREO (1<<13) /* PCI/X Error */
1078#define TSI148_LCSR_INTEO_VERREO (1<<12) /* VMEbus Error */
1079#define TSI148_LCSR_INTEO_VIEEO (1<<11) /* VMEbus IRQ Edge */
1080#define TSI148_LCSR_INTEO_IACKEO (1<<10) /* IACK */
1081#define TSI148_LCSR_INTEO_SYSFLEO (1<<9) /* System Fail */
1082#define TSI148_LCSR_INTEO_ACFLEO (1<<8) /* AC Fail */
1083#define TSI148_LCSR_INTEO_IRQ7EO (1<<7) /* IRQ7 */
1084#define TSI148_LCSR_INTEO_IRQ6EO (1<<6) /* IRQ6 */
1085#define TSI148_LCSR_INTEO_IRQ5EO (1<<5) /* IRQ5 */
1086#define TSI148_LCSR_INTEO_IRQ4EO (1<<4) /* IRQ4 */
1087#define TSI148_LCSR_INTEO_IRQ3EO (1<<3) /* IRQ3 */
1088#define TSI148_LCSR_INTEO_IRQ2EO (1<<2) /* IRQ2 */
1089#define TSI148_LCSR_INTEO_IRQ1EO (1<<1) /* IRQ1 */
1090
1091static const int TSI148_LCSR_INTEO_LMEO[4] = { TSI148_LCSR_INTEO_LM0EO,
1092 TSI148_LCSR_INTEO_LM1EO,
1093 TSI148_LCSR_INTEO_LM2EO,
1094 TSI148_LCSR_INTEO_LM3EO };
1095
1096static const int TSI148_LCSR_INTEO_IRQEO[7] = { TSI148_LCSR_INTEO_IRQ1EO,
1097 TSI148_LCSR_INTEO_IRQ2EO,
1098 TSI148_LCSR_INTEO_IRQ3EO,
1099 TSI148_LCSR_INTEO_IRQ4EO,
1100 TSI148_LCSR_INTEO_IRQ5EO,
1101 TSI148_LCSR_INTEO_IRQ6EO,
1102 TSI148_LCSR_INTEO_IRQ7EO };
1103
1104/*
1105 * Interrupt Status Register CRG + $448
1106 */
1107#define TSI148_LCSR_INTS_DMA1S (1<<25) /* DMA 1 */
1108#define TSI148_LCSR_INTS_DMA0S (1<<24) /* DMA 0 */
1109#define TSI148_LCSR_INTS_LM3S (1<<23) /* Location Monitor 3 */
1110#define TSI148_LCSR_INTS_LM2S (1<<22) /* Location Monitor 2 */
1111#define TSI148_LCSR_INTS_LM1S (1<<21) /* Location Monitor 1 */
1112#define TSI148_LCSR_INTS_LM0S (1<<20) /* Location Monitor 0 */
1113#define TSI148_LCSR_INTS_MB3S (1<<19) /* Mail Box 3 */
1114#define TSI148_LCSR_INTS_MB2S (1<<18) /* Mail Box 2 */
1115#define TSI148_LCSR_INTS_MB1S (1<<17) /* Mail Box 1 */
1116#define TSI148_LCSR_INTS_MB0S (1<<16) /* Mail Box 0 */
1117#define TSI148_LCSR_INTS_PERRS (1<<13) /* PCI/X Error */
1118#define TSI148_LCSR_INTS_VERRS (1<<12) /* VMEbus Error */
1119#define TSI148_LCSR_INTS_VIES (1<<11) /* VMEbus IRQ Edge */
1120#define TSI148_LCSR_INTS_IACKS (1<<10) /* IACK */
1121#define TSI148_LCSR_INTS_SYSFLS (1<<9) /* System Fail */
1122#define TSI148_LCSR_INTS_ACFLS (1<<8) /* AC Fail */
1123#define TSI148_LCSR_INTS_IRQ7S (1<<7) /* IRQ7 */
1124#define TSI148_LCSR_INTS_IRQ6S (1<<6) /* IRQ6 */
1125#define TSI148_LCSR_INTS_IRQ5S (1<<5) /* IRQ5 */
1126#define TSI148_LCSR_INTS_IRQ4S (1<<4) /* IRQ4 */
1127#define TSI148_LCSR_INTS_IRQ3S (1<<3) /* IRQ3 */
1128#define TSI148_LCSR_INTS_IRQ2S (1<<2) /* IRQ2 */
1129#define TSI148_LCSR_INTS_IRQ1S (1<<1) /* IRQ1 */
1130
1131static const int TSI148_LCSR_INTS_LMS[4] = { TSI148_LCSR_INTS_LM0S,
1132 TSI148_LCSR_INTS_LM1S,
1133 TSI148_LCSR_INTS_LM2S,
1134 TSI148_LCSR_INTS_LM3S };
1135
1136static const int TSI148_LCSR_INTS_MBS[4] = { TSI148_LCSR_INTS_MB0S,
1137 TSI148_LCSR_INTS_MB1S,
1138 TSI148_LCSR_INTS_MB2S,
1139 TSI148_LCSR_INTS_MB3S };
1140
1141/*
1142 * Interrupt Clear Register CRG + $44C
1143 */
1144#define TSI148_LCSR_INTC_DMA1C (1<<25) /* DMA 1 */
1145#define TSI148_LCSR_INTC_DMA0C (1<<24) /* DMA 0 */
1146#define TSI148_LCSR_INTC_LM3C (1<<23) /* Location Monitor 3 */
1147#define TSI148_LCSR_INTC_LM2C (1<<22) /* Location Monitor 2 */
1148#define TSI148_LCSR_INTC_LM1C (1<<21) /* Location Monitor 1 */
1149#define TSI148_LCSR_INTC_LM0C (1<<20) /* Location Monitor 0 */
1150#define TSI148_LCSR_INTC_MB3C (1<<19) /* Mail Box 3 */
1151#define TSI148_LCSR_INTC_MB2C (1<<18) /* Mail Box 2 */
1152#define TSI148_LCSR_INTC_MB1C (1<<17) /* Mail Box 1 */
1153#define TSI148_LCSR_INTC_MB0C (1<<16) /* Mail Box 0 */
1154#define TSI148_LCSR_INTC_PERRC (1<<13) /* VMEbus Error */
1155#define TSI148_LCSR_INTC_VERRC (1<<12) /* VMEbus Access Time-out */
1156#define TSI148_LCSR_INTC_VIEC (1<<11) /* VMEbus IRQ Edge */
1157#define TSI148_LCSR_INTC_IACKC (1<<10) /* IACK */
1158#define TSI148_LCSR_INTC_SYSFLC (1<<9) /* System Fail */
1159#define TSI148_LCSR_INTC_ACFLC (1<<8) /* AC Fail */
1160
1161static const int TSI148_LCSR_INTC_LMC[4] = { TSI148_LCSR_INTC_LM0C,
1162 TSI148_LCSR_INTC_LM1C,
1163 TSI148_LCSR_INTC_LM2C,
1164 TSI148_LCSR_INTC_LM3C };
1165
1166static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
1167 TSI148_LCSR_INTC_MB1C,
1168 TSI148_LCSR_INTC_MB2C,
1169 TSI148_LCSR_INTC_MB3C };
1170
1171/*
1172 * Interrupt Map Register 1 CRG + $458
1173 */
1174#define TSI148_LCSR_INTM1_DMA1M_M (3<<18) /* DMA 1 */
1175#define TSI148_LCSR_INTM1_DMA0M_M (3<<16) /* DMA 0 */
1176#define TSI148_LCSR_INTM1_LM3M_M (3<<14) /* Location Monitor 3 */
1177#define TSI148_LCSR_INTM1_LM2M_M (3<<12) /* Location Monitor 2 */
1178#define TSI148_LCSR_INTM1_LM1M_M (3<<10) /* Location Monitor 1 */
1179#define TSI148_LCSR_INTM1_LM0M_M (3<<8) /* Location Monitor 0 */
1180#define TSI148_LCSR_INTM1_MB3M_M (3<<6) /* Mail Box 3 */
1181#define TSI148_LCSR_INTM1_MB2M_M (3<<4) /* Mail Box 2 */
1182#define TSI148_LCSR_INTM1_MB1M_M (3<<2) /* Mail Box 1 */
1183#define TSI148_LCSR_INTM1_MB0M_M (3<<0) /* Mail Box 0 */
1184
1185/*
1186 * Interrupt Map Register 2 CRG + $45C
1187 */
1188#define TSI148_LCSR_INTM2_PERRM_M (3<<26) /* PCI Bus Error */
1189#define TSI148_LCSR_INTM2_VERRM_M (3<<24) /* VMEbus Error */
1190#define TSI148_LCSR_INTM2_VIEM_M (3<<22) /* VMEbus IRQ Edge */
1191#define TSI148_LCSR_INTM2_IACKM_M (3<<20) /* IACK */
1192#define TSI148_LCSR_INTM2_SYSFLM_M (3<<18) /* System Fail */
1193#define TSI148_LCSR_INTM2_ACFLM_M (3<<16) /* AC Fail */
1194#define TSI148_LCSR_INTM2_IRQ7M_M (3<<14) /* IRQ7 */
1195#define TSI148_LCSR_INTM2_IRQ6M_M (3<<12) /* IRQ6 */
1196#define TSI148_LCSR_INTM2_IRQ5M_M (3<<10) /* IRQ5 */
1197#define TSI148_LCSR_INTM2_IRQ4M_M (3<<8) /* IRQ4 */
1198#define TSI148_LCSR_INTM2_IRQ3M_M (3<<6) /* IRQ3 */
1199#define TSI148_LCSR_INTM2_IRQ2M_M (3<<4) /* IRQ2 */
1200#define TSI148_LCSR_INTM2_IRQ1M_M (3<<2) /* IRQ1 */
1201
1202/*
1203 * DMA Control (0-1) Registers CRG + $500
1204 */
1205#define TSI148_LCSR_DCTL_ABT (1<<27) /* Abort */
1206#define TSI148_LCSR_DCTL_PAU (1<<26) /* Pause */
1207#define TSI148_LCSR_DCTL_DGO (1<<25) /* DMA Go */
1208
1209#define TSI148_LCSR_DCTL_MOD (1<<23) /* Mode */
1210
1211#define TSI148_LCSR_DCTL_VBKS_M (7<<12) /* VMEbus block Size MASK */
1212#define TSI148_LCSR_DCTL_VBKS_32 (0<<12) /* VMEbus block Size 32 */
1213#define TSI148_LCSR_DCTL_VBKS_64 (1<<12) /* VMEbus block Size 64 */
1214#define TSI148_LCSR_DCTL_VBKS_128 (2<<12) /* VMEbus block Size 128 */
1215#define TSI148_LCSR_DCTL_VBKS_256 (3<<12) /* VMEbus block Size 256 */
1216#define TSI148_LCSR_DCTL_VBKS_512 (4<<12) /* VMEbus block Size 512 */
1217#define TSI148_LCSR_DCTL_VBKS_1024 (5<<12) /* VMEbus block Size 1024 */
1218#define TSI148_LCSR_DCTL_VBKS_2048 (6<<12) /* VMEbus block Size 2048 */
1219#define TSI148_LCSR_DCTL_VBKS_4096 (7<<12) /* VMEbus block Size 4096 */
1220
1221#define TSI148_LCSR_DCTL_VBOT_M (7<<8) /* VMEbus back-off MASK */
1222#define TSI148_LCSR_DCTL_VBOT_0 (0<<8) /* VMEbus back-off 0us */
1223#define TSI148_LCSR_DCTL_VBOT_1 (1<<8) /* VMEbus back-off 1us */
1224#define TSI148_LCSR_DCTL_VBOT_2 (2<<8) /* VMEbus back-off 2us */
1225#define TSI148_LCSR_DCTL_VBOT_4 (3<<8) /* VMEbus back-off 4us */
1226#define TSI148_LCSR_DCTL_VBOT_8 (4<<8) /* VMEbus back-off 8us */
1227#define TSI148_LCSR_DCTL_VBOT_16 (5<<8) /* VMEbus back-off 16us */
1228#define TSI148_LCSR_DCTL_VBOT_32 (6<<8) /* VMEbus back-off 32us */
1229#define TSI148_LCSR_DCTL_VBOT_64 (7<<8) /* VMEbus back-off 64us */
1230
1231#define TSI148_LCSR_DCTL_PBKS_M (7<<4) /* PCI block size MASK */
1232#define TSI148_LCSR_DCTL_PBKS_32 (0<<4) /* PCI block size 32 bytes */
1233#define TSI148_LCSR_DCTL_PBKS_64 (1<<4) /* PCI block size 64 bytes */
1234#define TSI148_LCSR_DCTL_PBKS_128 (2<<4) /* PCI block size 128 bytes */
1235#define TSI148_LCSR_DCTL_PBKS_256 (3<<4) /* PCI block size 256 bytes */
1236#define TSI148_LCSR_DCTL_PBKS_512 (4<<4) /* PCI block size 512 bytes */
1237#define TSI148_LCSR_DCTL_PBKS_1024 (5<<4) /* PCI block size 1024 bytes */
1238#define TSI148_LCSR_DCTL_PBKS_2048 (6<<4) /* PCI block size 2048 bytes */
1239#define TSI148_LCSR_DCTL_PBKS_4096 (7<<4) /* PCI block size 4096 bytes */
1240
1241#define TSI148_LCSR_DCTL_PBOT_M (7<<0) /* PCI back off MASK */
1242#define TSI148_LCSR_DCTL_PBOT_0 (0<<0) /* PCI back off 0us */
1243#define TSI148_LCSR_DCTL_PBOT_1 (1<<0) /* PCI back off 1us */
1244#define TSI148_LCSR_DCTL_PBOT_2 (2<<0) /* PCI back off 2us */
1245#define TSI148_LCSR_DCTL_PBOT_4 (3<<0) /* PCI back off 3us */
1246#define TSI148_LCSR_DCTL_PBOT_8 (4<<0) /* PCI back off 4us */
1247#define TSI148_LCSR_DCTL_PBOT_16 (5<<0) /* PCI back off 8us */
1248#define TSI148_LCSR_DCTL_PBOT_32 (6<<0) /* PCI back off 16us */
1249#define TSI148_LCSR_DCTL_PBOT_64 (7<<0) /* PCI back off 32us */
1250
1251/*
1252 * DMA Status Registers (0-1) CRG + $504
1253 */
1254#define TSI148_LCSR_DSTA_SMA (1<<31) /* PCI Signalled Master Abt */
1255#define TSI148_LCSR_DSTA_RTA (1<<30) /* PCI Received Target Abt */
1256#define TSI148_LCSR_DSTA_MRC (1<<29) /* PCI Max Retry Count */
1257#define TSI148_LCSR_DSTA_VBE (1<<28) /* VMEbus error */
1258#define TSI148_LCSR_DSTA_ABT (1<<27) /* Abort */
1259#define TSI148_LCSR_DSTA_PAU (1<<26) /* Pause */
1260#define TSI148_LCSR_DSTA_DON (1<<25) /* Done */
1261#define TSI148_LCSR_DSTA_BSY (1<<24) /* Busy */
1262
1263/*
1264 * DMA Current Link Address Lower (0-1)
1265 */
1266#define TSI148_LCSR_DCLAL_M (0x3FFFFFF<<6) /* Mask */
1267
1268/*
1269 * DMA Source Attribute (0-1) Reg
1270 */
1271#define TSI148_LCSR_DSAT_TYP_M (3<<28) /* Source Bus Type */
1272#define TSI148_LCSR_DSAT_TYP_PCI (0<<28) /* PCI Bus */
1273#define TSI148_LCSR_DSAT_TYP_VME (1<<28) /* VMEbus */
1274#define TSI148_LCSR_DSAT_TYP_PAT (2<<28) /* Data Pattern */
1275
1276#define TSI148_LCSR_DSAT_PSZ (1<<25) /* Pattern Size */
1277#define TSI148_LCSR_DSAT_NIN (1<<24) /* No Increment */
1278
1279#define TSI148_LCSR_DSAT_2eSSTM_M (3<<11) /* 2eSST Trans Rate Mask */
1280#define TSI148_LCSR_DSAT_2eSSTM_160 (0<<11) /* 160 MB/s */
1281#define TSI148_LCSR_DSAT_2eSSTM_267 (1<<11) /* 267 MB/s */
1282#define TSI148_LCSR_DSAT_2eSSTM_320 (2<<11) /* 320 MB/s */
1283
1284#define TSI148_LCSR_DSAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
1285#define TSI148_LCSR_DSAT_TM_SCT (0<<8) /* SCT */
1286#define TSI148_LCSR_DSAT_TM_BLT (1<<8) /* BLT */
1287#define TSI148_LCSR_DSAT_TM_MBLT (2<<8) /* MBLT */
1288#define TSI148_LCSR_DSAT_TM_2eVME (3<<8) /* 2eVME */
1289#define TSI148_LCSR_DSAT_TM_2eSST (4<<8) /* 2eSST */
1290#define TSI148_LCSR_DSAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */
1291
1292#define TSI148_LCSR_DSAT_DBW_M (3<<6) /* Max Data Width MASK */
1293#define TSI148_LCSR_DSAT_DBW_16 (0<<6) /* 16 Bits */
1294#define TSI148_LCSR_DSAT_DBW_32 (1<<6) /* 32 Bits */
1295
1296#define TSI148_LCSR_DSAT_SUP (1<<5) /* Supervisory Mode */
1297#define TSI148_LCSR_DSAT_PGM (1<<4) /* Program Mode */
1298
1299#define TSI148_LCSR_DSAT_AMODE_M (0xf<<0) /* Address Space Mask */
1300#define TSI148_LCSR_DSAT_AMODE_A16 (0<<0) /* A16 */
1301#define TSI148_LCSR_DSAT_AMODE_A24 (1<<0) /* A24 */
1302#define TSI148_LCSR_DSAT_AMODE_A32 (2<<0) /* A32 */
1303#define TSI148_LCSR_DSAT_AMODE_A64 (4<<0) /* A64 */
1304#define TSI148_LCSR_DSAT_AMODE_CRCSR (5<<0) /* CR/CSR */
1305#define TSI148_LCSR_DSAT_AMODE_USER1 (8<<0) /* User1 */
1306#define TSI148_LCSR_DSAT_AMODE_USER2 (9<<0) /* User2 */
1307#define TSI148_LCSR_DSAT_AMODE_USER3 (0xa<<0) /* User3 */
1308#define TSI148_LCSR_DSAT_AMODE_USER4 (0xb<<0) /* User4 */
1309
1310/*
1311 * DMA Destination Attribute Registers (0-1)
1312 */
1313#define TSI148_LCSR_DDAT_TYP_PCI (0<<28) /* Destination PCI Bus */
1314#define TSI148_LCSR_DDAT_TYP_VME (1<<28) /* Destination VMEbus */
1315
1316#define TSI148_LCSR_DDAT_2eSSTM_M (3<<11) /* 2eSST Transfer Rate Mask */
1317#define TSI148_LCSR_DDAT_2eSSTM_160 (0<<11) /* 160 MB/s */
1318#define TSI148_LCSR_DDAT_2eSSTM_267 (1<<11) /* 267 MB/s */
1319#define TSI148_LCSR_DDAT_2eSSTM_320 (2<<11) /* 320 MB/s */
1320
1321#define TSI148_LCSR_DDAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
1322#define TSI148_LCSR_DDAT_TM_SCT (0<<8) /* SCT */
1323#define TSI148_LCSR_DDAT_TM_BLT (1<<8) /* BLT */
1324#define TSI148_LCSR_DDAT_TM_MBLT (2<<8) /* MBLT */
1325#define TSI148_LCSR_DDAT_TM_2eVME (3<<8) /* 2eVME */
1326#define TSI148_LCSR_DDAT_TM_2eSST (4<<8) /* 2eSST */
1327#define TSI148_LCSR_DDAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */
1328
1329#define TSI148_LCSR_DDAT_DBW_M (3<<6) /* Max Data Width MASK */
1330#define TSI148_LCSR_DDAT_DBW_16 (0<<6) /* 16 Bits */
1331#define TSI148_LCSR_DDAT_DBW_32 (1<<6) /* 32 Bits */
1332
1333#define TSI148_LCSR_DDAT_SUP (1<<5) /* Supervisory/User Access */
1334#define TSI148_LCSR_DDAT_PGM (1<<4) /* Program/Data Access */
1335
1336#define TSI148_LCSR_DDAT_AMODE_M (0xf<<0) /* Address Space Mask */
1337#define TSI148_LCSR_DDAT_AMODE_A16 (0<<0) /* A16 */
1338#define TSI148_LCSR_DDAT_AMODE_A24 (1<<0) /* A24 */
1339#define TSI148_LCSR_DDAT_AMODE_A32 (2<<0) /* A32 */
1340#define TSI148_LCSR_DDAT_AMODE_A64 (4<<0) /* A64 */
1341#define TSI148_LCSR_DDAT_AMODE_CRCSR (5<<0) /* CRC/SR */
1342#define TSI148_LCSR_DDAT_AMODE_USER1 (8<<0) /* User1 */
1343#define TSI148_LCSR_DDAT_AMODE_USER2 (9<<0) /* User2 */
1344#define TSI148_LCSR_DDAT_AMODE_USER3 (0xa<<0) /* User3 */
1345#define TSI148_LCSR_DDAT_AMODE_USER4 (0xb<<0) /* User4 */
1346
1347/*
1348 * DMA Next Link Address Lower
1349 */
1350#define TSI148_LCSR_DNLAL_DNLAL_M (0x3FFFFFF<<6) /* Address Mask */
1351#define TSI148_LCSR_DNLAL_LLA (1<<0) /* Last Link Address Indicator */
1352
1353/*
1354 * DMA 2eSST Broadcast Select
1355 */
1356#define TSI148_LCSR_DBS_M (0x1FFFFF<<0) /* Mask */
1357
1358/*
1359 * GCSR Register Group
1360 */
1361
1362/*
1363 * GCSR Control and Status Register CRG + $604
1364 */
1365#define TSI148_GCSR_GCTRL_LRST (1<<15) /* Local Reset */
1366#define TSI148_GCSR_GCTRL_SFAILEN (1<<14) /* System Fail enable */
1367#define TSI148_GCSR_GCTRL_BDFAILS (1<<13) /* Board Fail Status */
1368#define TSI148_GCSR_GCTRL_SCON (1<<12) /* System Copntroller */
1369#define TSI148_GCSR_GCTRL_MEN (1<<11) /* Module Enable (READY) */
1370
1371#define TSI148_GCSR_GCTRL_LMI3S (1<<7) /* Loc Monitor 3 Int Status */
1372#define TSI148_GCSR_GCTRL_LMI2S (1<<6) /* Loc Monitor 2 Int Status */
1373#define TSI148_GCSR_GCTRL_LMI1S (1<<5) /* Loc Monitor 1 Int Status */
1374#define TSI148_GCSR_GCTRL_LMI0S (1<<4) /* Loc Monitor 0 Int Status */
1375#define TSI148_GCSR_GCTRL_MBI3S (1<<3) /* Mail box 3 Int Status */
1376#define TSI148_GCSR_GCTRL_MBI2S (1<<2) /* Mail box 2 Int Status */
1377#define TSI148_GCSR_GCTRL_MBI1S (1<<1) /* Mail box 1 Int Status */
1378#define TSI148_GCSR_GCTRL_MBI0S (1<<0) /* Mail box 0 Int Status */
1379
1380#define TSI148_GCSR_GAP (1<<5) /* Geographic Addr Parity */
1381#define TSI148_GCSR_GA_M (0x1F<<0) /* Geographic Address Mask */
1382
1383/*
1384 * CR/CSR Register Group
1385 */
1386
1387/*
1388 * CR/CSR Bit Clear Register CRG + $FF4
1389 */
1390#define TSI148_CRCSR_CSRBCR_LRSTC (1<<7) /* Local Reset Clear */
1391#define TSI148_CRCSR_CSRBCR_SFAILC (1<<6) /* System Fail Enable Clear */
1392#define TSI148_CRCSR_CSRBCR_BDFAILS (1<<5) /* Board Fail Status */
1393#define TSI148_CRCSR_CSRBCR_MENC (1<<4) /* Module Enable Clear */
1394#define TSI148_CRCSR_CSRBCR_BERRSC (1<<3) /* Bus Error Status Clear */
1395
1396/*
1397 * CR/CSR Bit Set Register CRG+$FF8
1398 */
1399#define TSI148_CRCSR_CSRBSR_LISTS (1<<7) /* Local Reset Clear */
1400#define TSI148_CRCSR_CSRBSR_SFAILS (1<<6) /* System Fail Enable Clear */
1401#define TSI148_CRCSR_CSRBSR_BDFAILS (1<<5) /* Board Fail Status */
1402#define TSI148_CRCSR_CSRBSR_MENS (1<<4) /* Module Enable Clear */
1403#define TSI148_CRCSR_CSRBSR_BERRS (1<<3) /* Bus Error Status Clear */
1404
1405/*
1406 * CR/CSR Base Address Register CRG + FFC
1407 */
1408#define TSI148_CRCSR_CBAR_M (0x1F<<3) /* Mask */
1409
1410#endif /* TSI148_H */
diff --git a/drivers/vme/vme.c b/drivers/vme/vme.c
deleted file mode 100644
index 95a9f71d793..00000000000
--- a/drivers/vme/vme.c
+++ /dev/null
@@ -1,1517 +0,0 @@
1/*
2 * VME Bridge Framework
3 *
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/mm.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/pci.h>
23#include <linux/poll.h>
24#include <linux/highmem.h>
25#include <linux/interrupt.h>
26#include <linux/pagemap.h>
27#include <linux/device.h>
28#include <linux/dma-mapping.h>
29#include <linux/syscalls.h>
30#include <linux/mutex.h>
31#include <linux/spinlock.h>
32#include <linux/slab.h>
33#include <linux/vme.h>
34
35#include "vme_bridge.h"
36
37/* Bitmask and list of registered buses both protected by common mutex */
38static unsigned int vme_bus_numbers;
39static LIST_HEAD(vme_bus_list);
40static DEFINE_MUTEX(vme_buses_lock);
41
42static void __exit vme_exit(void);
43static int __init vme_init(void);
44
45static struct vme_dev *dev_to_vme_dev(struct device *dev)
46{
47 return container_of(dev, struct vme_dev, dev);
48}
49
50/*
51 * Find the bridge that the resource is associated with.
52 */
53static struct vme_bridge *find_bridge(struct vme_resource *resource)
54{
55 /* Get list to search */
56 switch (resource->type) {
57 case VME_MASTER:
58 return list_entry(resource->entry, struct vme_master_resource,
59 list)->parent;
60 break;
61 case VME_SLAVE:
62 return list_entry(resource->entry, struct vme_slave_resource,
63 list)->parent;
64 break;
65 case VME_DMA:
66 return list_entry(resource->entry, struct vme_dma_resource,
67 list)->parent;
68 break;
69 case VME_LM:
70 return list_entry(resource->entry, struct vme_lm_resource,
71 list)->parent;
72 break;
73 default:
74 printk(KERN_ERR "Unknown resource type\n");
75 return NULL;
76 break;
77 }
78}
79
80/*
81 * Allocate a contiguous block of memory for use by the driver. This is used to
82 * create the buffers for the slave windows.
83 */
84void *vme_alloc_consistent(struct vme_resource *resource, size_t size,
85 dma_addr_t *dma)
86{
87 struct vme_bridge *bridge;
88
89 if (resource == NULL) {
90 printk(KERN_ERR "No resource\n");
91 return NULL;
92 }
93
94 bridge = find_bridge(resource);
95 if (bridge == NULL) {
96 printk(KERN_ERR "Can't find bridge\n");
97 return NULL;
98 }
99
100 if (bridge->parent == NULL) {
101 printk(KERN_ERR "Dev entry NULL for bridge %s\n", bridge->name);
102 return NULL;
103 }
104
105 if (bridge->alloc_consistent == NULL) {
106 printk(KERN_ERR "alloc_consistent not supported by bridge %s\n",
107 bridge->name);
108 return NULL;
109 }
110
111 return bridge->alloc_consistent(bridge->parent, size, dma);
112}
113EXPORT_SYMBOL(vme_alloc_consistent);
114
115/*
116 * Free previously allocated contiguous block of memory.
117 */
118void vme_free_consistent(struct vme_resource *resource, size_t size,
119 void *vaddr, dma_addr_t dma)
120{
121 struct vme_bridge *bridge;
122
123 if (resource == NULL) {
124 printk(KERN_ERR "No resource\n");
125 return;
126 }
127
128 bridge = find_bridge(resource);
129 if (bridge == NULL) {
130 printk(KERN_ERR "Can't find bridge\n");
131 return;
132 }
133
134 if (bridge->parent == NULL) {
135 printk(KERN_ERR "Dev entry NULL for bridge %s\n", bridge->name);
136 return;
137 }
138
139 if (bridge->free_consistent == NULL) {
140 printk(KERN_ERR "free_consistent not supported by bridge %s\n",
141 bridge->name);
142 return;
143 }
144
145 bridge->free_consistent(bridge->parent, size, vaddr, dma);
146}
147EXPORT_SYMBOL(vme_free_consistent);
148
149size_t vme_get_size(struct vme_resource *resource)
150{
151 int enabled, retval;
152 unsigned long long base, size;
153 dma_addr_t buf_base;
154 u32 aspace, cycle, dwidth;
155
156 switch (resource->type) {
157 case VME_MASTER:
158 retval = vme_master_get(resource, &enabled, &base, &size,
159 &aspace, &cycle, &dwidth);
160
161 return size;
162 break;
163 case VME_SLAVE:
164 retval = vme_slave_get(resource, &enabled, &base, &size,
165 &buf_base, &aspace, &cycle);
166
167 return size;
168 break;
169 case VME_DMA:
170 return 0;
171 break;
172 default:
173 printk(KERN_ERR "Unknown resource type\n");
174 return 0;
175 break;
176 }
177}
178EXPORT_SYMBOL(vme_get_size);
179
180static int vme_check_window(u32 aspace, unsigned long long vme_base,
181 unsigned long long size)
182{
183 int retval = 0;
184
185 switch (aspace) {
186 case VME_A16:
187 if (((vme_base + size) > VME_A16_MAX) ||
188 (vme_base > VME_A16_MAX))
189 retval = -EFAULT;
190 break;
191 case VME_A24:
192 if (((vme_base + size) > VME_A24_MAX) ||
193 (vme_base > VME_A24_MAX))
194 retval = -EFAULT;
195 break;
196 case VME_A32:
197 if (((vme_base + size) > VME_A32_MAX) ||
198 (vme_base > VME_A32_MAX))
199 retval = -EFAULT;
200 break;
201 case VME_A64:
202 /*
203 * Any value held in an unsigned long long can be used as the
204 * base
205 */
206 break;
207 case VME_CRCSR:
208 if (((vme_base + size) > VME_CRCSR_MAX) ||
209 (vme_base > VME_CRCSR_MAX))
210 retval = -EFAULT;
211 break;
212 case VME_USER1:
213 case VME_USER2:
214 case VME_USER3:
215 case VME_USER4:
216 /* User Defined */
217 break;
218 default:
219 printk(KERN_ERR "Invalid address space\n");
220 retval = -EINVAL;
221 break;
222 }
223
224 return retval;
225}
226
227/*
228 * Request a slave image with specific attributes, return some unique
229 * identifier.
230 */
231struct vme_resource *vme_slave_request(struct vme_dev *vdev, u32 address,
232 u32 cycle)
233{
234 struct vme_bridge *bridge;
235 struct list_head *slave_pos = NULL;
236 struct vme_slave_resource *allocated_image = NULL;
237 struct vme_slave_resource *slave_image = NULL;
238 struct vme_resource *resource = NULL;
239
240 bridge = vdev->bridge;
241 if (bridge == NULL) {
242 printk(KERN_ERR "Can't find VME bus\n");
243 goto err_bus;
244 }
245
246 /* Loop through slave resources */
247 list_for_each(slave_pos, &bridge->slave_resources) {
248 slave_image = list_entry(slave_pos,
249 struct vme_slave_resource, list);
250
251 if (slave_image == NULL) {
252 printk(KERN_ERR "Registered NULL Slave resource\n");
253 continue;
254 }
255
256 /* Find an unlocked and compatible image */
257 mutex_lock(&slave_image->mtx);
258 if (((slave_image->address_attr & address) == address) &&
259 ((slave_image->cycle_attr & cycle) == cycle) &&
260 (slave_image->locked == 0)) {
261
262 slave_image->locked = 1;
263 mutex_unlock(&slave_image->mtx);
264 allocated_image = slave_image;
265 break;
266 }
267 mutex_unlock(&slave_image->mtx);
268 }
269
270 /* No free image */
271 if (allocated_image == NULL)
272 goto err_image;
273
274 resource = kmalloc(sizeof(struct vme_resource), GFP_KERNEL);
275 if (resource == NULL) {
276 printk(KERN_WARNING "Unable to allocate resource structure\n");
277 goto err_alloc;
278 }
279 resource->type = VME_SLAVE;
280 resource->entry = &allocated_image->list;
281
282 return resource;
283
284err_alloc:
285 /* Unlock image */
286 mutex_lock(&slave_image->mtx);
287 slave_image->locked = 0;
288 mutex_unlock(&slave_image->mtx);
289err_image:
290err_bus:
291 return NULL;
292}
293EXPORT_SYMBOL(vme_slave_request);
294
295int vme_slave_set(struct vme_resource *resource, int enabled,
296 unsigned long long vme_base, unsigned long long size,
297 dma_addr_t buf_base, u32 aspace, u32 cycle)
298{
299 struct vme_bridge *bridge = find_bridge(resource);
300 struct vme_slave_resource *image;
301 int retval;
302
303 if (resource->type != VME_SLAVE) {
304 printk(KERN_ERR "Not a slave resource\n");
305 return -EINVAL;
306 }
307
308 image = list_entry(resource->entry, struct vme_slave_resource, list);
309
310 if (bridge->slave_set == NULL) {
311 printk(KERN_ERR "Function not supported\n");
312 return -ENOSYS;
313 }
314
315 if (!(((image->address_attr & aspace) == aspace) &&
316 ((image->cycle_attr & cycle) == cycle))) {
317 printk(KERN_ERR "Invalid attributes\n");
318 return -EINVAL;
319 }
320
321 retval = vme_check_window(aspace, vme_base, size);
322 if (retval)
323 return retval;
324
325 return bridge->slave_set(image, enabled, vme_base, size, buf_base,
326 aspace, cycle);
327}
328EXPORT_SYMBOL(vme_slave_set);
329
330int vme_slave_get(struct vme_resource *resource, int *enabled,
331 unsigned long long *vme_base, unsigned long long *size,
332 dma_addr_t *buf_base, u32 *aspace, u32 *cycle)
333{
334 struct vme_bridge *bridge = find_bridge(resource);
335 struct vme_slave_resource *image;
336
337 if (resource->type != VME_SLAVE) {
338 printk(KERN_ERR "Not a slave resource\n");
339 return -EINVAL;
340 }
341
342 image = list_entry(resource->entry, struct vme_slave_resource, list);
343
344 if (bridge->slave_get == NULL) {
345 printk(KERN_ERR "vme_slave_get not supported\n");
346 return -EINVAL;
347 }
348
349 return bridge->slave_get(image, enabled, vme_base, size, buf_base,
350 aspace, cycle);
351}
352EXPORT_SYMBOL(vme_slave_get);
353
354void vme_slave_free(struct vme_resource *resource)
355{
356 struct vme_slave_resource *slave_image;
357
358 if (resource->type != VME_SLAVE) {
359 printk(KERN_ERR "Not a slave resource\n");
360 return;
361 }
362
363 slave_image = list_entry(resource->entry, struct vme_slave_resource,
364 list);
365 if (slave_image == NULL) {
366 printk(KERN_ERR "Can't find slave resource\n");
367 return;
368 }
369
370 /* Unlock image */
371 mutex_lock(&slave_image->mtx);
372 if (slave_image->locked == 0)
373 printk(KERN_ERR "Image is already free\n");
374
375 slave_image->locked = 0;
376 mutex_unlock(&slave_image->mtx);
377
378 /* Free up resource memory */
379 kfree(resource);
380}
381EXPORT_SYMBOL(vme_slave_free);
382
383/*
384 * Request a master image with specific attributes, return some unique
385 * identifier.
386 */
387struct vme_resource *vme_master_request(struct vme_dev *vdev, u32 address,
388 u32 cycle, u32 dwidth)
389{
390 struct vme_bridge *bridge;
391 struct list_head *master_pos = NULL;
392 struct vme_master_resource *allocated_image = NULL;
393 struct vme_master_resource *master_image = NULL;
394 struct vme_resource *resource = NULL;
395
396 bridge = vdev->bridge;
397 if (bridge == NULL) {
398 printk(KERN_ERR "Can't find VME bus\n");
399 goto err_bus;
400 }
401
402 /* Loop through master resources */
403 list_for_each(master_pos, &bridge->master_resources) {
404 master_image = list_entry(master_pos,
405 struct vme_master_resource, list);
406
407 if (master_image == NULL) {
408 printk(KERN_WARNING "Registered NULL master resource\n");
409 continue;
410 }
411
412 /* Find an unlocked and compatible image */
413 spin_lock(&master_image->lock);
414 if (((master_image->address_attr & address) == address) &&
415 ((master_image->cycle_attr & cycle) == cycle) &&
416 ((master_image->width_attr & dwidth) == dwidth) &&
417 (master_image->locked == 0)) {
418
419 master_image->locked = 1;
420 spin_unlock(&master_image->lock);
421 allocated_image = master_image;
422 break;
423 }
424 spin_unlock(&master_image->lock);
425 }
426
427 /* Check to see if we found a resource */
428 if (allocated_image == NULL) {
429 printk(KERN_ERR "Can't find a suitable resource\n");
430 goto err_image;
431 }
432
433 resource = kmalloc(sizeof(struct vme_resource), GFP_KERNEL);
434 if (resource == NULL) {
435 printk(KERN_ERR "Unable to allocate resource structure\n");
436 goto err_alloc;
437 }
438 resource->type = VME_MASTER;
439 resource->entry = &allocated_image->list;
440
441 return resource;
442
443err_alloc:
444 /* Unlock image */
445 spin_lock(&master_image->lock);
446 master_image->locked = 0;
447 spin_unlock(&master_image->lock);
448err_image:
449err_bus:
450 return NULL;
451}
452EXPORT_SYMBOL(vme_master_request);
453
454int vme_master_set(struct vme_resource *resource, int enabled,
455 unsigned long long vme_base, unsigned long long size, u32 aspace,
456 u32 cycle, u32 dwidth)
457{
458 struct vme_bridge *bridge = find_bridge(resource);
459 struct vme_master_resource *image;
460 int retval;
461
462 if (resource->type != VME_MASTER) {
463 printk(KERN_ERR "Not a master resource\n");
464 return -EINVAL;
465 }
466
467 image = list_entry(resource->entry, struct vme_master_resource, list);
468
469 if (bridge->master_set == NULL) {
470 printk(KERN_WARNING "vme_master_set not supported\n");
471 return -EINVAL;
472 }
473
474 if (!(((image->address_attr & aspace) == aspace) &&
475 ((image->cycle_attr & cycle) == cycle) &&
476 ((image->width_attr & dwidth) == dwidth))) {
477 printk(KERN_WARNING "Invalid attributes\n");
478 return -EINVAL;
479 }
480
481 retval = vme_check_window(aspace, vme_base, size);
482 if (retval)
483 return retval;
484
485 return bridge->master_set(image, enabled, vme_base, size, aspace,
486 cycle, dwidth);
487}
488EXPORT_SYMBOL(vme_master_set);
489
490int vme_master_get(struct vme_resource *resource, int *enabled,
491 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
492 u32 *cycle, u32 *dwidth)
493{
494 struct vme_bridge *bridge = find_bridge(resource);
495 struct vme_master_resource *image;
496
497 if (resource->type != VME_MASTER) {
498 printk(KERN_ERR "Not a master resource\n");
499 return -EINVAL;
500 }
501
502 image = list_entry(resource->entry, struct vme_master_resource, list);
503
504 if (bridge->master_get == NULL) {
505 printk(KERN_WARNING "vme_master_set not supported\n");
506 return -EINVAL;
507 }
508
509 return bridge->master_get(image, enabled, vme_base, size, aspace,
510 cycle, dwidth);
511}
512EXPORT_SYMBOL(vme_master_get);
513
514/*
515 * Read data out of VME space into a buffer.
516 */
517ssize_t vme_master_read(struct vme_resource *resource, void *buf, size_t count,
518 loff_t offset)
519{
520 struct vme_bridge *bridge = find_bridge(resource);
521 struct vme_master_resource *image;
522 size_t length;
523
524 if (bridge->master_read == NULL) {
525 printk(KERN_WARNING "Reading from resource not supported\n");
526 return -EINVAL;
527 }
528
529 if (resource->type != VME_MASTER) {
530 printk(KERN_ERR "Not a master resource\n");
531 return -EINVAL;
532 }
533
534 image = list_entry(resource->entry, struct vme_master_resource, list);
535
536 length = vme_get_size(resource);
537
538 if (offset > length) {
539 printk(KERN_WARNING "Invalid Offset\n");
540 return -EFAULT;
541 }
542
543 if ((offset + count) > length)
544 count = length - offset;
545
546 return bridge->master_read(image, buf, count, offset);
547
548}
549EXPORT_SYMBOL(vme_master_read);
550
551/*
552 * Write data out to VME space from a buffer.
553 */
554ssize_t vme_master_write(struct vme_resource *resource, void *buf,
555 size_t count, loff_t offset)
556{
557 struct vme_bridge *bridge = find_bridge(resource);
558 struct vme_master_resource *image;
559 size_t length;
560
561 if (bridge->master_write == NULL) {
562 printk(KERN_WARNING "Writing to resource not supported\n");
563 return -EINVAL;
564 }
565
566 if (resource->type != VME_MASTER) {
567 printk(KERN_ERR "Not a master resource\n");
568 return -EINVAL;
569 }
570
571 image = list_entry(resource->entry, struct vme_master_resource, list);
572
573 length = vme_get_size(resource);
574
575 if (offset > length) {
576 printk(KERN_WARNING "Invalid Offset\n");
577 return -EFAULT;
578 }
579
580 if ((offset + count) > length)
581 count = length - offset;
582
583 return bridge->master_write(image, buf, count, offset);
584}
585EXPORT_SYMBOL(vme_master_write);
586
587/*
588 * Perform RMW cycle to provided location.
589 */
590unsigned int vme_master_rmw(struct vme_resource *resource, unsigned int mask,
591 unsigned int compare, unsigned int swap, loff_t offset)
592{
593 struct vme_bridge *bridge = find_bridge(resource);
594 struct vme_master_resource *image;
595
596 if (bridge->master_rmw == NULL) {
597 printk(KERN_WARNING "Writing to resource not supported\n");
598 return -EINVAL;
599 }
600
601 if (resource->type != VME_MASTER) {
602 printk(KERN_ERR "Not a master resource\n");
603 return -EINVAL;
604 }
605
606 image = list_entry(resource->entry, struct vme_master_resource, list);
607
608 return bridge->master_rmw(image, mask, compare, swap, offset);
609}
610EXPORT_SYMBOL(vme_master_rmw);
611
612void vme_master_free(struct vme_resource *resource)
613{
614 struct vme_master_resource *master_image;
615
616 if (resource->type != VME_MASTER) {
617 printk(KERN_ERR "Not a master resource\n");
618 return;
619 }
620
621 master_image = list_entry(resource->entry, struct vme_master_resource,
622 list);
623 if (master_image == NULL) {
624 printk(KERN_ERR "Can't find master resource\n");
625 return;
626 }
627
628 /* Unlock image */
629 spin_lock(&master_image->lock);
630 if (master_image->locked == 0)
631 printk(KERN_ERR "Image is already free\n");
632
633 master_image->locked = 0;
634 spin_unlock(&master_image->lock);
635
636 /* Free up resource memory */
637 kfree(resource);
638}
639EXPORT_SYMBOL(vme_master_free);
640
641/*
642 * Request a DMA controller with specific attributes, return some unique
643 * identifier.
644 */
645struct vme_resource *vme_dma_request(struct vme_dev *vdev, u32 route)
646{
647 struct vme_bridge *bridge;
648 struct list_head *dma_pos = NULL;
649 struct vme_dma_resource *allocated_ctrlr = NULL;
650 struct vme_dma_resource *dma_ctrlr = NULL;
651 struct vme_resource *resource = NULL;
652
653 /* XXX Not checking resource attributes */
654 printk(KERN_ERR "No VME resource Attribute tests done\n");
655
656 bridge = vdev->bridge;
657 if (bridge == NULL) {
658 printk(KERN_ERR "Can't find VME bus\n");
659 goto err_bus;
660 }
661
662 /* Loop through DMA resources */
663 list_for_each(dma_pos, &bridge->dma_resources) {
664 dma_ctrlr = list_entry(dma_pos,
665 struct vme_dma_resource, list);
666
667 if (dma_ctrlr == NULL) {
668 printk(KERN_ERR "Registered NULL DMA resource\n");
669 continue;
670 }
671
672 /* Find an unlocked and compatible controller */
673 mutex_lock(&dma_ctrlr->mtx);
674 if (((dma_ctrlr->route_attr & route) == route) &&
675 (dma_ctrlr->locked == 0)) {
676
677 dma_ctrlr->locked = 1;
678 mutex_unlock(&dma_ctrlr->mtx);
679 allocated_ctrlr = dma_ctrlr;
680 break;
681 }
682 mutex_unlock(&dma_ctrlr->mtx);
683 }
684
685 /* Check to see if we found a resource */
686 if (allocated_ctrlr == NULL)
687 goto err_ctrlr;
688
689 resource = kmalloc(sizeof(struct vme_resource), GFP_KERNEL);
690 if (resource == NULL) {
691 printk(KERN_WARNING "Unable to allocate resource structure\n");
692 goto err_alloc;
693 }
694 resource->type = VME_DMA;
695 resource->entry = &allocated_ctrlr->list;
696
697 return resource;
698
699err_alloc:
700 /* Unlock image */
701 mutex_lock(&dma_ctrlr->mtx);
702 dma_ctrlr->locked = 0;
703 mutex_unlock(&dma_ctrlr->mtx);
704err_ctrlr:
705err_bus:
706 return NULL;
707}
708EXPORT_SYMBOL(vme_dma_request);
709
710/*
711 * Start new list
712 */
713struct vme_dma_list *vme_new_dma_list(struct vme_resource *resource)
714{
715 struct vme_dma_resource *ctrlr;
716 struct vme_dma_list *dma_list;
717
718 if (resource->type != VME_DMA) {
719 printk(KERN_ERR "Not a DMA resource\n");
720 return NULL;
721 }
722
723 ctrlr = list_entry(resource->entry, struct vme_dma_resource, list);
724
725 dma_list = kmalloc(sizeof(struct vme_dma_list), GFP_KERNEL);
726 if (dma_list == NULL) {
727 printk(KERN_ERR "Unable to allocate memory for new dma list\n");
728 return NULL;
729 }
730 INIT_LIST_HEAD(&dma_list->entries);
731 dma_list->parent = ctrlr;
732 mutex_init(&dma_list->mtx);
733
734 return dma_list;
735}
736EXPORT_SYMBOL(vme_new_dma_list);
737
738/*
739 * Create "Pattern" type attributes
740 */
741struct vme_dma_attr *vme_dma_pattern_attribute(u32 pattern, u32 type)
742{
743 struct vme_dma_attr *attributes;
744 struct vme_dma_pattern *pattern_attr;
745
746 attributes = kmalloc(sizeof(struct vme_dma_attr), GFP_KERNEL);
747 if (attributes == NULL) {
748 printk(KERN_ERR "Unable to allocate memory for attributes structure\n");
749 goto err_attr;
750 }
751
752 pattern_attr = kmalloc(sizeof(struct vme_dma_pattern), GFP_KERNEL);
753 if (pattern_attr == NULL) {
754 printk(KERN_ERR "Unable to allocate memory for pattern attributes\n");
755 goto err_pat;
756 }
757
758 attributes->type = VME_DMA_PATTERN;
759 attributes->private = (void *)pattern_attr;
760
761 pattern_attr->pattern = pattern;
762 pattern_attr->type = type;
763
764 return attributes;
765
766err_pat:
767 kfree(attributes);
768err_attr:
769 return NULL;
770}
771EXPORT_SYMBOL(vme_dma_pattern_attribute);
772
773/*
774 * Create "PCI" type attributes
775 */
776struct vme_dma_attr *vme_dma_pci_attribute(dma_addr_t address)
777{
778 struct vme_dma_attr *attributes;
779 struct vme_dma_pci *pci_attr;
780
781 /* XXX Run some sanity checks here */
782
783 attributes = kmalloc(sizeof(struct vme_dma_attr), GFP_KERNEL);
784 if (attributes == NULL) {
785 printk(KERN_ERR "Unable to allocate memory for attributes structure\n");
786 goto err_attr;
787 }
788
789 pci_attr = kmalloc(sizeof(struct vme_dma_pci), GFP_KERNEL);
790 if (pci_attr == NULL) {
791 printk(KERN_ERR "Unable to allocate memory for pci attributes\n");
792 goto err_pci;
793 }
794
795
796
797 attributes->type = VME_DMA_PCI;
798 attributes->private = (void *)pci_attr;
799
800 pci_attr->address = address;
801
802 return attributes;
803
804err_pci:
805 kfree(attributes);
806err_attr:
807 return NULL;
808}
809EXPORT_SYMBOL(vme_dma_pci_attribute);
810
811/*
812 * Create "VME" type attributes
813 */
814struct vme_dma_attr *vme_dma_vme_attribute(unsigned long long address,
815 u32 aspace, u32 cycle, u32 dwidth)
816{
817 struct vme_dma_attr *attributes;
818 struct vme_dma_vme *vme_attr;
819
820 attributes = kmalloc(
821 sizeof(struct vme_dma_attr), GFP_KERNEL);
822 if (attributes == NULL) {
823 printk(KERN_ERR "Unable to allocate memory for attributes structure\n");
824 goto err_attr;
825 }
826
827 vme_attr = kmalloc(sizeof(struct vme_dma_vme), GFP_KERNEL);
828 if (vme_attr == NULL) {
829 printk(KERN_ERR "Unable to allocate memory for vme attributes\n");
830 goto err_vme;
831 }
832
833 attributes->type = VME_DMA_VME;
834 attributes->private = (void *)vme_attr;
835
836 vme_attr->address = address;
837 vme_attr->aspace = aspace;
838 vme_attr->cycle = cycle;
839 vme_attr->dwidth = dwidth;
840
841 return attributes;
842
843err_vme:
844 kfree(attributes);
845err_attr:
846 return NULL;
847}
848EXPORT_SYMBOL(vme_dma_vme_attribute);
849
850/*
851 * Free attribute
852 */
853void vme_dma_free_attribute(struct vme_dma_attr *attributes)
854{
855 kfree(attributes->private);
856 kfree(attributes);
857}
858EXPORT_SYMBOL(vme_dma_free_attribute);
859
860int vme_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
861 struct vme_dma_attr *dest, size_t count)
862{
863 struct vme_bridge *bridge = list->parent->parent;
864 int retval;
865
866 if (bridge->dma_list_add == NULL) {
867 printk(KERN_WARNING "Link List DMA generation not supported\n");
868 return -EINVAL;
869 }
870
871 if (!mutex_trylock(&list->mtx)) {
872 printk(KERN_ERR "Link List already submitted\n");
873 return -EINVAL;
874 }
875
876 retval = bridge->dma_list_add(list, src, dest, count);
877
878 mutex_unlock(&list->mtx);
879
880 return retval;
881}
882EXPORT_SYMBOL(vme_dma_list_add);
883
884int vme_dma_list_exec(struct vme_dma_list *list)
885{
886 struct vme_bridge *bridge = list->parent->parent;
887 int retval;
888
889 if (bridge->dma_list_exec == NULL) {
890 printk(KERN_ERR "Link List DMA execution not supported\n");
891 return -EINVAL;
892 }
893
894 mutex_lock(&list->mtx);
895
896 retval = bridge->dma_list_exec(list);
897
898 mutex_unlock(&list->mtx);
899
900 return retval;
901}
902EXPORT_SYMBOL(vme_dma_list_exec);
903
904int vme_dma_list_free(struct vme_dma_list *list)
905{
906 struct vme_bridge *bridge = list->parent->parent;
907 int retval;
908
909 if (bridge->dma_list_empty == NULL) {
910 printk(KERN_WARNING "Emptying of Link Lists not supported\n");
911 return -EINVAL;
912 }
913
914 if (!mutex_trylock(&list->mtx)) {
915 printk(KERN_ERR "Link List in use\n");
916 return -EINVAL;
917 }
918
919 /*
920 * Empty out all of the entries from the dma list. We need to go to the
921 * low level driver as dma entries are driver specific.
922 */
923 retval = bridge->dma_list_empty(list);
924 if (retval) {
925 printk(KERN_ERR "Unable to empty link-list entries\n");
926 mutex_unlock(&list->mtx);
927 return retval;
928 }
929 mutex_unlock(&list->mtx);
930 kfree(list);
931
932 return retval;
933}
934EXPORT_SYMBOL(vme_dma_list_free);
935
936int vme_dma_free(struct vme_resource *resource)
937{
938 struct vme_dma_resource *ctrlr;
939
940 if (resource->type != VME_DMA) {
941 printk(KERN_ERR "Not a DMA resource\n");
942 return -EINVAL;
943 }
944
945 ctrlr = list_entry(resource->entry, struct vme_dma_resource, list);
946
947 if (!mutex_trylock(&ctrlr->mtx)) {
948 printk(KERN_ERR "Resource busy, can't free\n");
949 return -EBUSY;
950 }
951
952 if (!(list_empty(&ctrlr->pending) && list_empty(&ctrlr->running))) {
953 printk(KERN_WARNING "Resource still processing transfers\n");
954 mutex_unlock(&ctrlr->mtx);
955 return -EBUSY;
956 }
957
958 ctrlr->locked = 0;
959
960 mutex_unlock(&ctrlr->mtx);
961
962 return 0;
963}
964EXPORT_SYMBOL(vme_dma_free);
965
966void vme_irq_handler(struct vme_bridge *bridge, int level, int statid)
967{
968 void (*call)(int, int, void *);
969 void *priv_data;
970
971 call = bridge->irq[level - 1].callback[statid].func;
972 priv_data = bridge->irq[level - 1].callback[statid].priv_data;
973
974 if (call != NULL)
975 call(level, statid, priv_data);
976 else
977 printk(KERN_WARNING "Spurilous VME interrupt, level:%x, vector:%x\n",
978 level, statid);
979}
980EXPORT_SYMBOL(vme_irq_handler);
981
982int vme_irq_request(struct vme_dev *vdev, int level, int statid,
983 void (*callback)(int, int, void *),
984 void *priv_data)
985{
986 struct vme_bridge *bridge;
987
988 bridge = vdev->bridge;
989 if (bridge == NULL) {
990 printk(KERN_ERR "Can't find VME bus\n");
991 return -EINVAL;
992 }
993
994 if ((level < 1) || (level > 7)) {
995 printk(KERN_ERR "Invalid interrupt level\n");
996 return -EINVAL;
997 }
998
999 if (bridge->irq_set == NULL) {
1000 printk(KERN_ERR "Configuring interrupts not supported\n");
1001 return -EINVAL;
1002 }
1003
1004 mutex_lock(&bridge->irq_mtx);
1005
1006 if (bridge->irq[level - 1].callback[statid].func) {
1007 mutex_unlock(&bridge->irq_mtx);
1008 printk(KERN_WARNING "VME Interrupt already taken\n");
1009 return -EBUSY;
1010 }
1011
1012 bridge->irq[level - 1].count++;
1013 bridge->irq[level - 1].callback[statid].priv_data = priv_data;
1014 bridge->irq[level - 1].callback[statid].func = callback;
1015
1016 /* Enable IRQ level */
1017 bridge->irq_set(bridge, level, 1, 1);
1018
1019 mutex_unlock(&bridge->irq_mtx);
1020
1021 return 0;
1022}
1023EXPORT_SYMBOL(vme_irq_request);
1024
1025void vme_irq_free(struct vme_dev *vdev, int level, int statid)
1026{
1027 struct vme_bridge *bridge;
1028
1029 bridge = vdev->bridge;
1030 if (bridge == NULL) {
1031 printk(KERN_ERR "Can't find VME bus\n");
1032 return;
1033 }
1034
1035 if ((level < 1) || (level > 7)) {
1036 printk(KERN_ERR "Invalid interrupt level\n");
1037 return;
1038 }
1039
1040 if (bridge->irq_set == NULL) {
1041 printk(KERN_ERR "Configuring interrupts not supported\n");
1042 return;
1043 }
1044
1045 mutex_lock(&bridge->irq_mtx);
1046
1047 bridge->irq[level - 1].count--;
1048
1049 /* Disable IRQ level if no more interrupts attached at this level*/
1050 if (bridge->irq[level - 1].count == 0)
1051 bridge->irq_set(bridge, level, 0, 1);
1052
1053 bridge->irq[level - 1].callback[statid].func = NULL;
1054 bridge->irq[level - 1].callback[statid].priv_data = NULL;
1055
1056 mutex_unlock(&bridge->irq_mtx);
1057}
1058EXPORT_SYMBOL(vme_irq_free);
1059
1060int vme_irq_generate(struct vme_dev *vdev, int level, int statid)
1061{
1062 struct vme_bridge *bridge;
1063
1064 bridge = vdev->bridge;
1065 if (bridge == NULL) {
1066 printk(KERN_ERR "Can't find VME bus\n");
1067 return -EINVAL;
1068 }
1069
1070 if ((level < 1) || (level > 7)) {
1071 printk(KERN_WARNING "Invalid interrupt level\n");
1072 return -EINVAL;
1073 }
1074
1075 if (bridge->irq_generate == NULL) {
1076 printk(KERN_WARNING "Interrupt generation not supported\n");
1077 return -EINVAL;
1078 }
1079
1080 return bridge->irq_generate(bridge, level, statid);
1081}
1082EXPORT_SYMBOL(vme_irq_generate);
1083
1084/*
1085 * Request the location monitor, return resource or NULL
1086 */
1087struct vme_resource *vme_lm_request(struct vme_dev *vdev)
1088{
1089 struct vme_bridge *bridge;
1090 struct list_head *lm_pos = NULL;
1091 struct vme_lm_resource *allocated_lm = NULL;
1092 struct vme_lm_resource *lm = NULL;
1093 struct vme_resource *resource = NULL;
1094
1095 bridge = vdev->bridge;
1096 if (bridge == NULL) {
1097 printk(KERN_ERR "Can't find VME bus\n");
1098 goto err_bus;
1099 }
1100
1101 /* Loop through DMA resources */
1102 list_for_each(lm_pos, &bridge->lm_resources) {
1103 lm = list_entry(lm_pos,
1104 struct vme_lm_resource, list);
1105
1106 if (lm == NULL) {
1107 printk(KERN_ERR "Registered NULL Location Monitor resource\n");
1108 continue;
1109 }
1110
1111 /* Find an unlocked controller */
1112 mutex_lock(&lm->mtx);
1113 if (lm->locked == 0) {
1114 lm->locked = 1;
1115 mutex_unlock(&lm->mtx);
1116 allocated_lm = lm;
1117 break;
1118 }
1119 mutex_unlock(&lm->mtx);
1120 }
1121
1122 /* Check to see if we found a resource */
1123 if (allocated_lm == NULL)
1124 goto err_lm;
1125
1126 resource = kmalloc(sizeof(struct vme_resource), GFP_KERNEL);
1127 if (resource == NULL) {
1128 printk(KERN_ERR "Unable to allocate resource structure\n");
1129 goto err_alloc;
1130 }
1131 resource->type = VME_LM;
1132 resource->entry = &allocated_lm->list;
1133
1134 return resource;
1135
1136err_alloc:
1137 /* Unlock image */
1138 mutex_lock(&lm->mtx);
1139 lm->locked = 0;
1140 mutex_unlock(&lm->mtx);
1141err_lm:
1142err_bus:
1143 return NULL;
1144}
1145EXPORT_SYMBOL(vme_lm_request);
1146
1147int vme_lm_count(struct vme_resource *resource)
1148{
1149 struct vme_lm_resource *lm;
1150
1151 if (resource->type != VME_LM) {
1152 printk(KERN_ERR "Not a Location Monitor resource\n");
1153 return -EINVAL;
1154 }
1155
1156 lm = list_entry(resource->entry, struct vme_lm_resource, list);
1157
1158 return lm->monitors;
1159}
1160EXPORT_SYMBOL(vme_lm_count);
1161
1162int vme_lm_set(struct vme_resource *resource, unsigned long long lm_base,
1163 u32 aspace, u32 cycle)
1164{
1165 struct vme_bridge *bridge = find_bridge(resource);
1166 struct vme_lm_resource *lm;
1167
1168 if (resource->type != VME_LM) {
1169 printk(KERN_ERR "Not a Location Monitor resource\n");
1170 return -EINVAL;
1171 }
1172
1173 lm = list_entry(resource->entry, struct vme_lm_resource, list);
1174
1175 if (bridge->lm_set == NULL) {
1176 printk(KERN_ERR "vme_lm_set not supported\n");
1177 return -EINVAL;
1178 }
1179
1180 return bridge->lm_set(lm, lm_base, aspace, cycle);
1181}
1182EXPORT_SYMBOL(vme_lm_set);
1183
1184int vme_lm_get(struct vme_resource *resource, unsigned long long *lm_base,
1185 u32 *aspace, u32 *cycle)
1186{
1187 struct vme_bridge *bridge = find_bridge(resource);
1188 struct vme_lm_resource *lm;
1189
1190 if (resource->type != VME_LM) {
1191 printk(KERN_ERR "Not a Location Monitor resource\n");
1192 return -EINVAL;
1193 }
1194
1195 lm = list_entry(resource->entry, struct vme_lm_resource, list);
1196
1197 if (bridge->lm_get == NULL) {
1198 printk(KERN_ERR "vme_lm_get not supported\n");
1199 return -EINVAL;
1200 }
1201
1202 return bridge->lm_get(lm, lm_base, aspace, cycle);
1203}
1204EXPORT_SYMBOL(vme_lm_get);
1205
1206int vme_lm_attach(struct vme_resource *resource, int monitor,
1207 void (*callback)(int))
1208{
1209 struct vme_bridge *bridge = find_bridge(resource);
1210 struct vme_lm_resource *lm;
1211
1212 if (resource->type != VME_LM) {
1213 printk(KERN_ERR "Not a Location Monitor resource\n");
1214 return -EINVAL;
1215 }
1216
1217 lm = list_entry(resource->entry, struct vme_lm_resource, list);
1218
1219 if (bridge->lm_attach == NULL) {
1220 printk(KERN_ERR "vme_lm_attach not supported\n");
1221 return -EINVAL;
1222 }
1223
1224 return bridge->lm_attach(lm, monitor, callback);
1225}
1226EXPORT_SYMBOL(vme_lm_attach);
1227
1228int vme_lm_detach(struct vme_resource *resource, int monitor)
1229{
1230 struct vme_bridge *bridge = find_bridge(resource);
1231 struct vme_lm_resource *lm;
1232
1233 if (resource->type != VME_LM) {
1234 printk(KERN_ERR "Not a Location Monitor resource\n");
1235 return -EINVAL;
1236 }
1237
1238 lm = list_entry(resource->entry, struct vme_lm_resource, list);
1239
1240 if (bridge->lm_detach == NULL) {
1241 printk(KERN_ERR "vme_lm_detach not supported\n");
1242 return -EINVAL;
1243 }
1244
1245 return bridge->lm_detach(lm, monitor);
1246}
1247EXPORT_SYMBOL(vme_lm_detach);
1248
1249void vme_lm_free(struct vme_resource *resource)
1250{
1251 struct vme_lm_resource *lm;
1252
1253 if (resource->type != VME_LM) {
1254 printk(KERN_ERR "Not a Location Monitor resource\n");
1255 return;
1256 }
1257
1258 lm = list_entry(resource->entry, struct vme_lm_resource, list);
1259
1260 mutex_lock(&lm->mtx);
1261
1262 /* XXX
1263 * Check to see that there aren't any callbacks still attached, if
1264 * there are we should probably be detaching them!
1265 */
1266
1267 lm->locked = 0;
1268
1269 mutex_unlock(&lm->mtx);
1270
1271 kfree(resource);
1272}
1273EXPORT_SYMBOL(vme_lm_free);
1274
1275int vme_slot_get(struct vme_dev *vdev)
1276{
1277 struct vme_bridge *bridge;
1278
1279 bridge = vdev->bridge;
1280 if (bridge == NULL) {
1281 printk(KERN_ERR "Can't find VME bus\n");
1282 return -EINVAL;
1283 }
1284
1285 if (bridge->slot_get == NULL) {
1286 printk(KERN_WARNING "vme_slot_get not supported\n");
1287 return -EINVAL;
1288 }
1289
1290 return bridge->slot_get(bridge);
1291}
1292EXPORT_SYMBOL(vme_slot_get);
1293
1294
1295/* - Bridge Registration --------------------------------------------------- */
1296
1297static void vme_dev_release(struct device *dev)
1298{
1299 kfree(dev_to_vme_dev(dev));
1300}
1301
1302int vme_register_bridge(struct vme_bridge *bridge)
1303{
1304 int i;
1305 int ret = -1;
1306
1307 mutex_lock(&vme_buses_lock);
1308 for (i = 0; i < sizeof(vme_bus_numbers) * 8; i++) {
1309 if ((vme_bus_numbers & (1 << i)) == 0) {
1310 vme_bus_numbers |= (1 << i);
1311 bridge->num = i;
1312 INIT_LIST_HEAD(&bridge->devices);
1313 list_add_tail(&bridge->bus_list, &vme_bus_list);
1314 ret = 0;
1315 break;
1316 }
1317 }
1318 mutex_unlock(&vme_buses_lock);
1319
1320 return ret;
1321}
1322EXPORT_SYMBOL(vme_register_bridge);
1323
1324void vme_unregister_bridge(struct vme_bridge *bridge)
1325{
1326 struct vme_dev *vdev;
1327 struct vme_dev *tmp;
1328
1329 mutex_lock(&vme_buses_lock);
1330 vme_bus_numbers &= ~(1 << bridge->num);
1331 list_for_each_entry_safe(vdev, tmp, &bridge->devices, bridge_list) {
1332 list_del(&vdev->drv_list);
1333 list_del(&vdev->bridge_list);
1334 device_unregister(&vdev->dev);
1335 }
1336 list_del(&bridge->bus_list);
1337 mutex_unlock(&vme_buses_lock);
1338}
1339EXPORT_SYMBOL(vme_unregister_bridge);
1340
1341/* - Driver Registration --------------------------------------------------- */
1342
1343static int __vme_register_driver_bus(struct vme_driver *drv,
1344 struct vme_bridge *bridge, unsigned int ndevs)
1345{
1346 int err;
1347 unsigned int i;
1348 struct vme_dev *vdev;
1349 struct vme_dev *tmp;
1350
1351 for (i = 0; i < ndevs; i++) {
1352 vdev = kzalloc(sizeof(struct vme_dev), GFP_KERNEL);
1353 if (!vdev) {
1354 err = -ENOMEM;
1355 goto err_devalloc;
1356 }
1357 vdev->num = i;
1358 vdev->bridge = bridge;
1359 vdev->dev.platform_data = drv;
1360 vdev->dev.release = vme_dev_release;
1361 vdev->dev.parent = bridge->parent;
1362 vdev->dev.bus = &vme_bus_type;
1363 dev_set_name(&vdev->dev, "%s.%u-%u", drv->name, bridge->num,
1364 vdev->num);
1365
1366 err = device_register(&vdev->dev);
1367 if (err)
1368 goto err_reg;
1369
1370 if (vdev->dev.platform_data) {
1371 list_add_tail(&vdev->drv_list, &drv->devices);
1372 list_add_tail(&vdev->bridge_list, &bridge->devices);
1373 } else
1374 device_unregister(&vdev->dev);
1375 }
1376 return 0;
1377
1378err_reg:
1379 kfree(vdev);
1380err_devalloc:
1381 list_for_each_entry_safe(vdev, tmp, &drv->devices, drv_list) {
1382 list_del(&vdev->drv_list);
1383 list_del(&vdev->bridge_list);
1384 device_unregister(&vdev->dev);
1385 }
1386 return err;
1387}
1388
1389static int __vme_register_driver(struct vme_driver *drv, unsigned int ndevs)
1390{
1391 struct vme_bridge *bridge;
1392 int err = 0;
1393
1394 mutex_lock(&vme_buses_lock);
1395 list_for_each_entry(bridge, &vme_bus_list, bus_list) {
1396 /*
1397 * This cannot cause trouble as we already have vme_buses_lock
1398 * and if the bridge is removed, it will have to go through
1399 * vme_unregister_bridge() to do it (which calls remove() on
1400 * the bridge which in turn tries to acquire vme_buses_lock and
1401 * will have to wait).
1402 */
1403 err = __vme_register_driver_bus(drv, bridge, ndevs);
1404 if (err)
1405 break;
1406 }
1407 mutex_unlock(&vme_buses_lock);
1408 return err;
1409}
1410
1411int vme_register_driver(struct vme_driver *drv, unsigned int ndevs)
1412{
1413 int err;
1414
1415 drv->driver.name = drv->name;
1416 drv->driver.bus = &vme_bus_type;
1417 INIT_LIST_HEAD(&drv->devices);
1418
1419 err = driver_register(&drv->driver);
1420 if (err)
1421 return err;
1422
1423 err = __vme_register_driver(drv, ndevs);
1424 if (err)
1425 driver_unregister(&drv->driver);
1426
1427 return err;
1428}
1429EXPORT_SYMBOL(vme_register_driver);
1430
1431void vme_unregister_driver(struct vme_driver *drv)
1432{
1433 struct vme_dev *dev, *dev_tmp;
1434
1435 mutex_lock(&vme_buses_lock);
1436 list_for_each_entry_safe(dev, dev_tmp, &drv->devices, drv_list) {
1437 list_del(&dev->drv_list);
1438 list_del(&dev->bridge_list);
1439 device_unregister(&dev->dev);
1440 }
1441 mutex_unlock(&vme_buses_lock);
1442
1443 driver_unregister(&drv->driver);
1444}
1445EXPORT_SYMBOL(vme_unregister_driver);
1446
1447/* - Bus Registration ------------------------------------------------------ */
1448
1449static int vme_bus_match(struct device *dev, struct device_driver *drv)
1450{
1451 struct vme_driver *vme_drv;
1452
1453 vme_drv = container_of(drv, struct vme_driver, driver);
1454
1455 if (dev->platform_data == vme_drv) {
1456 struct vme_dev *vdev = dev_to_vme_dev(dev);
1457
1458 if (vme_drv->match && vme_drv->match(vdev))
1459 return 1;
1460
1461 dev->platform_data = NULL;
1462 }
1463 return 0;
1464}
1465
1466static int vme_bus_probe(struct device *dev)
1467{
1468 int retval = -ENODEV;
1469 struct vme_driver *driver;
1470 struct vme_dev *vdev = dev_to_vme_dev(dev);
1471
1472 driver = dev->platform_data;
1473
1474 if (driver->probe != NULL)
1475 retval = driver->probe(vdev);
1476
1477 return retval;
1478}
1479
1480static int vme_bus_remove(struct device *dev)
1481{
1482 int retval = -ENODEV;
1483 struct vme_driver *driver;
1484 struct vme_dev *vdev = dev_to_vme_dev(dev);
1485
1486 driver = dev->platform_data;
1487
1488 if (driver->remove != NULL)
1489 retval = driver->remove(vdev);
1490
1491 return retval;
1492}
1493
1494struct bus_type vme_bus_type = {
1495 .name = "vme",
1496 .match = vme_bus_match,
1497 .probe = vme_bus_probe,
1498 .remove = vme_bus_remove,
1499};
1500EXPORT_SYMBOL(vme_bus_type);
1501
1502static int __init vme_init(void)
1503{
1504 return bus_register(&vme_bus_type);
1505}
1506
1507static void __exit vme_exit(void)
1508{
1509 bus_unregister(&vme_bus_type);
1510}
1511
1512MODULE_DESCRIPTION("VME bridge driver framework");
1513MODULE_AUTHOR("Martyn Welch <martyn.welch@ge.com");
1514MODULE_LICENSE("GPL");
1515
1516module_init(vme_init);
1517module_exit(vme_exit);
diff --git a/drivers/vme/vme_bridge.h b/drivers/vme/vme_bridge.h
deleted file mode 100644
index 934949abd74..00000000000
--- a/drivers/vme/vme_bridge.h
+++ /dev/null
@@ -1,174 +0,0 @@
1#ifndef _VME_BRIDGE_H_
2#define _VME_BRIDGE_H_
3
4#define VME_CRCSR_BUF_SIZE (508*1024)
5/*
6 * Resource structures
7 */
8struct vme_master_resource {
9 struct list_head list;
10 struct vme_bridge *parent;
11 /*
12 * We are likely to need to access the VME bus in interrupt context, so
13 * protect master routines with a spinlock rather than a mutex.
14 */
15 spinlock_t lock;
16 int locked;
17 int number;
18 u32 address_attr;
19 u32 cycle_attr;
20 u32 width_attr;
21 struct resource bus_resource;
22 void __iomem *kern_base;
23};
24
25struct vme_slave_resource {
26 struct list_head list;
27 struct vme_bridge *parent;
28 struct mutex mtx;
29 int locked;
30 int number;
31 u32 address_attr;
32 u32 cycle_attr;
33};
34
35struct vme_dma_pattern {
36 u32 pattern;
37 u32 type;
38};
39
40struct vme_dma_pci {
41 dma_addr_t address;
42};
43
44struct vme_dma_vme {
45 unsigned long long address;
46 u32 aspace;
47 u32 cycle;
48 u32 dwidth;
49};
50
51struct vme_dma_list {
52 struct list_head list;
53 struct vme_dma_resource *parent;
54 struct list_head entries;
55 struct mutex mtx;
56};
57
58struct vme_dma_resource {
59 struct list_head list;
60 struct vme_bridge *parent;
61 struct mutex mtx;
62 int locked;
63 int number;
64 struct list_head pending;
65 struct list_head running;
66 u32 route_attr;
67};
68
69struct vme_lm_resource {
70 struct list_head list;
71 struct vme_bridge *parent;
72 struct mutex mtx;
73 int locked;
74 int number;
75 int monitors;
76};
77
78struct vme_bus_error {
79 struct list_head list;
80 unsigned long long address;
81 u32 attributes;
82};
83
84struct vme_callback {
85 void (*func)(int, int, void*);
86 void *priv_data;
87};
88
89struct vme_irq {
90 int count;
91 struct vme_callback callback[255];
92};
93
94/* Allow 16 characters for name (including null character) */
95#define VMENAMSIZ 16
96
97/* This structure stores all the information about one bridge
98 * The structure should be dynamically allocated by the driver and one instance
99 * of the structure should be present for each VME chip present in the system.
100 */
101struct vme_bridge {
102 char name[VMENAMSIZ];
103 int num;
104 struct list_head master_resources;
105 struct list_head slave_resources;
106 struct list_head dma_resources;
107 struct list_head lm_resources;
108
109 struct list_head vme_errors; /* List for errors generated on VME */
110 struct list_head devices; /* List of devices on this bridge */
111
112 /* Bridge Info - XXX Move to private structure? */
113 struct device *parent; /* Parent device (eg. pdev->dev for PCI) */
114 void *driver_priv; /* Private pointer for the bridge driver */
115 struct list_head bus_list; /* list of VME buses */
116
117 /* Interrupt callbacks */
118 struct vme_irq irq[7];
119 /* Locking for VME irq callback configuration */
120 struct mutex irq_mtx;
121
122 /* Slave Functions */
123 int (*slave_get) (struct vme_slave_resource *, int *,
124 unsigned long long *, unsigned long long *, dma_addr_t *,
125 u32 *, u32 *);
126 int (*slave_set) (struct vme_slave_resource *, int, unsigned long long,
127 unsigned long long, dma_addr_t, u32, u32);
128
129 /* Master Functions */
130 int (*master_get) (struct vme_master_resource *, int *,
131 unsigned long long *, unsigned long long *, u32 *, u32 *,
132 u32 *);
133 int (*master_set) (struct vme_master_resource *, int,
134 unsigned long long, unsigned long long, u32, u32, u32);
135 ssize_t (*master_read) (struct vme_master_resource *, void *, size_t,
136 loff_t);
137 ssize_t (*master_write) (struct vme_master_resource *, void *, size_t,
138 loff_t);
139 unsigned int (*master_rmw) (struct vme_master_resource *, unsigned int,
140 unsigned int, unsigned int, loff_t);
141
142 /* DMA Functions */
143 int (*dma_list_add) (struct vme_dma_list *, struct vme_dma_attr *,
144 struct vme_dma_attr *, size_t);
145 int (*dma_list_exec) (struct vme_dma_list *);
146 int (*dma_list_empty) (struct vme_dma_list *);
147
148 /* Interrupt Functions */
149 void (*irq_set) (struct vme_bridge *, int, int, int);
150 int (*irq_generate) (struct vme_bridge *, int, int);
151
152 /* Location monitor functions */
153 int (*lm_set) (struct vme_lm_resource *, unsigned long long, u32, u32);
154 int (*lm_get) (struct vme_lm_resource *, unsigned long long *, u32 *,
155 u32 *);
156 int (*lm_attach) (struct vme_lm_resource *, int, void (*callback)(int));
157 int (*lm_detach) (struct vme_lm_resource *, int);
158
159 /* CR/CSR space functions */
160 int (*slot_get) (struct vme_bridge *);
161
162 /* Bridge parent interface */
163 void *(*alloc_consistent)(struct device *dev, size_t size,
164 dma_addr_t *dma);
165 void (*free_consistent)(struct device *dev, size_t size,
166 void *vaddr, dma_addr_t dma);
167};
168
169void vme_irq_handler(struct vme_bridge *, int, int);
170
171int vme_register_bridge(struct vme_bridge *);
172void vme_unregister_bridge(struct vme_bridge *);
173
174#endif /* _VME_BRIDGE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 04:10:56 -0500