diff options
author | Aaro Koskinen <aaro.koskinen@iki.fi> | 2010-12-20 16:50:20 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-12-21 22:57:19 -0500 |
commit | ad78adb4e814104510da421a38cfe89ab018a8b1 (patch) | |
tree | 33bd5334752866f9cc2375bbb26861dd853e446b /drivers/video | |
parent | 667a8b4114641895c90f8c98db1678c0bfa056df (diff) |
sisfb: replace setSISIDXREG with SiS_SetRegANDOR
Replace setSISIDXREG() with SiS_SetRegANDOR().
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Thomas Winischhofer <thomas@winischhofer.net>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/video')
-rw-r--r-- | drivers/video/sis/sis_main.c | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index 65bf57f86a3..793216b5d1a 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c | |||
@@ -930,12 +930,12 @@ sisfb_myblank(struct sis_video_info *ivideo, int blank) | |||
930 | (ivideo->sisfb_thismonitor.feature & 0xe0))) { | 930 | (ivideo->sisfb_thismonitor.feature & 0xe0))) { |
931 | 931 | ||
932 | if(ivideo->sisvga_engine == SIS_315_VGA) { | 932 | if(ivideo->sisvga_engine == SIS_315_VGA) { |
933 | setSISIDXREG(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xbf, cr63); | 933 | SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xbf, cr63); |
934 | } | 934 | } |
935 | 935 | ||
936 | if(!(sisfb_bridgeisslave(ivideo))) { | 936 | if(!(sisfb_bridgeisslave(ivideo))) { |
937 | setSISIDXREG(SISSR, 0x01, ~0x20, sr01); | 937 | SiS_SetRegANDOR(SISSR, 0x01, ~0x20, sr01); |
938 | setSISIDXREG(SISSR, 0x1f, 0x3f, sr1f); | 938 | SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, sr1f); |
939 | } | 939 | } |
940 | } | 940 | } |
941 | 941 | ||
@@ -965,25 +965,25 @@ sisfb_myblank(struct sis_video_info *ivideo, int blank) | |||
965 | (ivideo->vbflags2 & (VB2_301|VB2_30xBDH|VB2_LVDS))) || | 965 | (ivideo->vbflags2 & (VB2_301|VB2_30xBDH|VB2_LVDS))) || |
966 | ((ivideo->sisvga_engine == SIS_315_VGA) && | 966 | ((ivideo->sisvga_engine == SIS_315_VGA) && |
967 | ((ivideo->vbflags2 & (VB2_LVDS | VB2_CHRONTEL)) == VB2_LVDS))) { | 967 | ((ivideo->vbflags2 & (VB2_LVDS | VB2_CHRONTEL)) == VB2_LVDS))) { |
968 | setSISIDXREG(SISSR, 0x11, ~0x0c, sr11); | 968 | SiS_SetRegANDOR(SISSR, 0x11, ~0x0c, sr11); |
969 | } | 969 | } |
970 | 970 | ||
971 | if(ivideo->sisvga_engine == SIS_300_VGA) { | 971 | if(ivideo->sisvga_engine == SIS_300_VGA) { |
972 | if((ivideo->vbflags2 & VB2_30xB) && | 972 | if((ivideo->vbflags2 & VB2_30xB) && |
973 | (!(ivideo->vbflags2 & VB2_30xBDH))) { | 973 | (!(ivideo->vbflags2 & VB2_30xBDH))) { |
974 | setSISIDXREG(SISPART1, 0x13, 0x3f, p1_13); | 974 | SiS_SetRegANDOR(SISPART1, 0x13, 0x3f, p1_13); |
975 | } | 975 | } |
976 | } else if(ivideo->sisvga_engine == SIS_315_VGA) { | 976 | } else if(ivideo->sisvga_engine == SIS_315_VGA) { |
977 | if((ivideo->vbflags2 & VB2_30xB) && | 977 | if((ivideo->vbflags2 & VB2_30xB) && |
978 | (!(ivideo->vbflags2 & VB2_30xBDH))) { | 978 | (!(ivideo->vbflags2 & VB2_30xBDH))) { |
979 | setSISIDXREG(SISPART2, 0x00, 0x1f, p2_0); | 979 | SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0); |
980 | } | 980 | } |
981 | } | 981 | } |
982 | 982 | ||
983 | } else if(ivideo->currentvbflags & CRT2_VGA) { | 983 | } else if(ivideo->currentvbflags & CRT2_VGA) { |
984 | 984 | ||
985 | if(ivideo->vbflags2 & VB2_30xB) { | 985 | if(ivideo->vbflags2 & VB2_30xB) { |
986 | setSISIDXREG(SISPART2, 0x00, 0x1f, p2_0); | 986 | SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0); |
987 | } | 987 | } |
988 | 988 | ||
989 | } | 989 | } |
@@ -1115,14 +1115,14 @@ sisfb_set_pitch(struct sis_video_info *ivideo) | |||
1115 | /* We need to set pitch for CRT1 if bridge is in slave mode, too */ | 1115 | /* We need to set pitch for CRT1 if bridge is in slave mode, too */ |
1116 | if((ivideo->currentvbflags & VB_DISPTYPE_DISP1) || (isslavemode)) { | 1116 | if((ivideo->currentvbflags & VB_DISPTYPE_DISP1) || (isslavemode)) { |
1117 | SiS_SetReg(SISCR, 0x13, (HDisplay1 & 0xFF)); | 1117 | SiS_SetReg(SISCR, 0x13, (HDisplay1 & 0xFF)); |
1118 | setSISIDXREG(SISSR,0x0E,0xF0,(HDisplay1 >> 8)); | 1118 | SiS_SetRegANDOR(SISSR, 0x0E, 0xF0, (HDisplay1 >> 8)); |
1119 | } | 1119 | } |
1120 | 1120 | ||
1121 | /* We must not set the pitch for CRT2 if bridge is in slave mode */ | 1121 | /* We must not set the pitch for CRT2 if bridge is in slave mode */ |
1122 | if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!isslavemode)) { | 1122 | if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!isslavemode)) { |
1123 | SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01); | 1123 | SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01); |
1124 | SiS_SetReg(SISPART1, 0x07, (HDisplay2 & 0xFF)); | 1124 | SiS_SetReg(SISPART1, 0x07, (HDisplay2 & 0xFF)); |
1125 | setSISIDXREG(SISPART1,0x09,0xF0,(HDisplay2 >> 8)); | 1125 | SiS_SetRegANDOR(SISPART1, 0x09, 0xF0, (HDisplay2 >> 8)); |
1126 | } | 1126 | } |
1127 | } | 1127 | } |
1128 | 1128 | ||
@@ -1314,7 +1314,7 @@ sisfb_set_base_CRT1(struct sis_video_info *ivideo, unsigned int base) | |||
1314 | SiS_SetReg(SISCR, 0x0C, (base >> 8) & 0xFF); | 1314 | SiS_SetReg(SISCR, 0x0C, (base >> 8) & 0xFF); |
1315 | SiS_SetReg(SISSR, 0x0D, (base >> 16) & 0xFF); | 1315 | SiS_SetReg(SISSR, 0x0D, (base >> 16) & 0xFF); |
1316 | if(ivideo->sisvga_engine == SIS_315_VGA) { | 1316 | if(ivideo->sisvga_engine == SIS_315_VGA) { |
1317 | setSISIDXREG(SISSR, 0x37, 0xFE, (base >> 24) & 0x01); | 1317 | SiS_SetRegANDOR(SISSR, 0x37, 0xFE, (base >> 24) & 0x01); |
1318 | } | 1318 | } |
1319 | } | 1319 | } |
1320 | 1320 | ||
@@ -1327,7 +1327,7 @@ sisfb_set_base_CRT2(struct sis_video_info *ivideo, unsigned int base) | |||
1327 | SiS_SetReg(SISPART1, 0x05, ((base >> 8) & 0xFF)); | 1327 | SiS_SetReg(SISPART1, 0x05, ((base >> 8) & 0xFF)); |
1328 | SiS_SetReg(SISPART1, 0x04, ((base >> 16) & 0xFF)); | 1328 | SiS_SetReg(SISPART1, 0x04, ((base >> 16) & 0xFF)); |
1329 | if(ivideo->sisvga_engine == SIS_315_VGA) { | 1329 | if(ivideo->sisvga_engine == SIS_315_VGA) { |
1330 | setSISIDXREG(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7); | 1330 | SiS_SetRegANDOR(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7); |
1331 | } | 1331 | } |
1332 | } | 1332 | } |
1333 | } | 1333 | } |
@@ -2259,11 +2259,11 @@ sisfb_sense_crt1(struct sis_video_info *ivideo) | |||
2259 | 2259 | ||
2260 | #ifdef CONFIG_FB_SIS_315 | 2260 | #ifdef CONFIG_FB_SIS_315 |
2261 | if(ivideo->sisvga_engine == SIS_315_VGA) { | 2261 | if(ivideo->sisvga_engine == SIS_315_VGA) { |
2262 | setSISIDXREG(SISCR,ivideo->SiS_Pr.SiS_MyCR63,0xBF,cr63); | 2262 | SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF, cr63); |
2263 | } | 2263 | } |
2264 | #endif | 2264 | #endif |
2265 | 2265 | ||
2266 | setSISIDXREG(SISCR,0x17,0x7F,cr17); | 2266 | SiS_SetRegANDOR(SISCR, 0x17, 0x7F, cr17); |
2267 | 2267 | ||
2268 | SiS_SetReg(SISSR, 0x1F, sr1F); | 2268 | SiS_SetReg(SISSR, 0x1F, sr1F); |
2269 | } | 2269 | } |
@@ -2351,7 +2351,7 @@ SiS_SenseLCD(struct sis_video_info *ivideo) | |||
2351 | 2351 | ||
2352 | SiS_SetReg(SISCR, 0x36, paneltype); | 2352 | SiS_SetReg(SISCR, 0x36, paneltype); |
2353 | cr37 &= 0xf1; | 2353 | cr37 &= 0xf1; |
2354 | setSISIDXREG(SISCR, 0x37, 0x0c, cr37); | 2354 | SiS_SetRegANDOR(SISCR, 0x37, 0x0c, cr37); |
2355 | SiS_SetRegOR(SISCR, 0x32, 0x08); | 2355 | SiS_SetRegOR(SISCR, 0x32, 0x08); |
2356 | 2356 | ||
2357 | ivideo->SiS_Pr.PanelSelfDetected = true; | 2357 | ivideo->SiS_Pr.PanelSelfDetected = true; |
@@ -2368,7 +2368,7 @@ SISDoSense(struct sis_video_info *ivideo, u16 type, u16 test) | |||
2368 | mytest = test; | 2368 | mytest = test; |
2369 | SiS_SetReg(SISPART4, 0x11, (type & 0x00ff)); | 2369 | SiS_SetReg(SISPART4, 0x11, (type & 0x00ff)); |
2370 | temp = (type >> 8) | (mytest & 0x00ff); | 2370 | temp = (type >> 8) | (mytest & 0x00ff); |
2371 | setSISIDXREG(SISPART4,0x10,0xe0,temp); | 2371 | SiS_SetRegANDOR(SISPART4, 0x10, 0xe0, temp); |
2372 | SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1500); | 2372 | SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1500); |
2373 | mytest >>= 8; | 2373 | mytest >>= 8; |
2374 | mytest &= 0x7f; | 2374 | mytest &= 0x7f; |
@@ -2443,7 +2443,7 @@ SiS_Sense30x(struct sis_video_info *ivideo) | |||
2443 | 2443 | ||
2444 | backupP4_0d = SiS_GetReg(SISPART4, 0x0d); | 2444 | backupP4_0d = SiS_GetReg(SISPART4, 0x0d); |
2445 | if(ivideo->vbflags2 & VB2_30xC) { | 2445 | if(ivideo->vbflags2 & VB2_30xC) { |
2446 | setSISIDXREG(SISPART4,0x0d,~0x07,0x01); | 2446 | SiS_SetRegANDOR(SISPART4, 0x0d, ~0x07, 0x01); |
2447 | } else { | 2447 | } else { |
2448 | SiS_SetRegOR(SISPART4, 0x0d, 0x04); | 2448 | SiS_SetRegOR(SISPART4, 0x0d, 0x04); |
2449 | } | 2449 | } |
@@ -2941,8 +2941,8 @@ sisfb_detect_lcd_type(struct sis_video_info *ivideo) | |||
2941 | if(ivideo->CRT2LCDType == LCD_UNKNOWN) { | 2941 | if(ivideo->CRT2LCDType == LCD_UNKNOWN) { |
2942 | /* For broken BIOSes: Assume 1024x768, RGB18 */ | 2942 | /* For broken BIOSes: Assume 1024x768, RGB18 */ |
2943 | ivideo->CRT2LCDType = LCD_1024x768; | 2943 | ivideo->CRT2LCDType = LCD_1024x768; |
2944 | setSISIDXREG(SISCR,0x36,0xf0,0x02); | 2944 | SiS_SetRegANDOR(SISCR, 0x36, 0xf0, 0x02); |
2945 | setSISIDXREG(SISCR,0x37,0xee,0x01); | 2945 | SiS_SetRegANDOR(SISCR, 0x37, 0xee, 0x01); |
2946 | printk(KERN_DEBUG "sisfb: Invalid panel ID (%02x), assuming 1024x768, RGB18\n", reg); | 2946 | printk(KERN_DEBUG "sisfb: Invalid panel ID (%02x), assuming 1024x768, RGB18\n", reg); |
2947 | } | 2947 | } |
2948 | 2948 | ||
@@ -3660,9 +3660,9 @@ sisfb_pre_setmode(struct sis_video_info *ivideo) | |||
3660 | if(ivideo->chip >= SIS_661) { | 3660 | if(ivideo->chip >= SIS_661) { |
3661 | #ifdef CONFIG_FB_SIS_315 | 3661 | #ifdef CONFIG_FB_SIS_315 |
3662 | cr31 &= ~0x01; /* Clear PAL flag (now in CR35) */ | 3662 | cr31 &= ~0x01; /* Clear PAL flag (now in CR35) */ |
3663 | setSISIDXREG(SISCR, 0x35, ~0x10, cr35); /* Leave overscan bit alone */ | 3663 | SiS_SetRegANDOR(SISCR, 0x35, ~0x10, cr35); /* Leave overscan bit alone */ |
3664 | cr38 &= 0x07; /* Use only LCDA and HiVision/YPbPr bits */ | 3664 | cr38 &= 0x07; /* Use only LCDA and HiVision/YPbPr bits */ |
3665 | setSISIDXREG(SISCR, 0x38, 0xf8, cr38); | 3665 | SiS_SetRegANDOR(SISCR, 0x38, 0xf8, cr38); |
3666 | #endif | 3666 | #endif |
3667 | } else if(ivideo->chip != SIS_300) { | 3667 | } else if(ivideo->chip != SIS_300) { |
3668 | SiS_SetReg(SISCR, tvregnum, cr38); | 3668 | SiS_SetReg(SISCR, tvregnum, cr38); |
@@ -3746,9 +3746,9 @@ sisfb_set_TVxposoffset(struct sis_video_info *ivideo, int val) | |||
3746 | p2_43 = temp & 0xff; | 3746 | p2_43 = temp & 0xff; |
3747 | p2_42 = (temp & 0xf00) >> 4; | 3747 | p2_42 = (temp & 0xf00) >> 4; |
3748 | SiS_SetReg(SISPART2, 0x1f, p2_1f); | 3748 | SiS_SetReg(SISPART2, 0x1f, p2_1f); |
3749 | setSISIDXREG(SISPART2,0x20,0x0F,p2_20); | 3749 | SiS_SetRegANDOR(SISPART2, 0x20, 0x0F, p2_20); |
3750 | setSISIDXREG(SISPART2,0x2b,0xF0,p2_2b); | 3750 | SiS_SetRegANDOR(SISPART2, 0x2b, 0xF0, p2_2b); |
3751 | setSISIDXREG(SISPART2,0x42,0x0F,p2_42); | 3751 | SiS_SetRegANDOR(SISPART2, 0x42, 0x0F, p2_42); |
3752 | SiS_SetReg(SISPART2, 0x43, p2_43); | 3752 | SiS_SetReg(SISPART2, 0x43, p2_43); |
3753 | } | 3753 | } |
3754 | } | 3754 | } |
@@ -3840,7 +3840,7 @@ sisfb_post_setmode(struct sis_video_info *ivideo) | |||
3840 | crt1isoff = false; | 3840 | crt1isoff = false; |
3841 | reg = 0x80; | 3841 | reg = 0x80; |
3842 | } | 3842 | } |
3843 | setSISIDXREG(SISCR, 0x17, 0x7f, reg); | 3843 | SiS_SetRegANDOR(SISCR, 0x17, 0x7f, reg); |
3844 | } | 3844 | } |
3845 | #endif | 3845 | #endif |
3846 | #ifdef CONFIG_FB_SIS_315 | 3846 | #ifdef CONFIG_FB_SIS_315 |
@@ -3854,8 +3854,8 @@ sisfb_post_setmode(struct sis_video_info *ivideo) | |||
3854 | reg = 0x00; | 3854 | reg = 0x00; |
3855 | reg1 = 0x00; | 3855 | reg1 = 0x00; |
3856 | } | 3856 | } |
3857 | setSISIDXREG(SISCR, ivideo->SiS_Pr.SiS_MyCR63, ~0x40, reg); | 3857 | SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, ~0x40, reg); |
3858 | setSISIDXREG(SISSR, 0x1f, ~0xc0, reg1); | 3858 | SiS_SetRegANDOR(SISSR, 0x1f, ~0xc0, reg1); |
3859 | } | 3859 | } |
3860 | #endif | 3860 | #endif |
3861 | 3861 | ||
@@ -4830,7 +4830,7 @@ sisfb_post_xgi_ramsize(struct sis_video_info *ivideo) | |||
4830 | } | 4830 | } |
4831 | 4831 | ||
4832 | bail_out: | 4832 | bail_out: |
4833 | setSISIDXREG(SISSR, 0x14, 0xf0, sr14); | 4833 | SiS_SetRegANDOR(SISSR, 0x14, 0xf0, sr14); |
4834 | sisfb_post_xgi_delay(ivideo, 1); | 4834 | sisfb_post_xgi_delay(ivideo, 1); |
4835 | 4835 | ||
4836 | j = (ivideo->chip == XGI_20) ? 5 : 9; | 4836 | j = (ivideo->chip == XGI_20) ? 5 : 9; |
@@ -4840,7 +4840,7 @@ bail_out: | |||
4840 | 4840 | ||
4841 | reg = (ivideo->chip == XGI_20) ? | 4841 | reg = (ivideo->chip == XGI_20) ? |
4842 | dramsr13[(i * 5) + 4] : dramsr13_4[(i * 5) + 4]; | 4842 | dramsr13[(i * 5) + 4] : dramsr13_4[(i * 5) + 4]; |
4843 | setSISIDXREG(SISSR, 0x13, 0x80, reg); | 4843 | SiS_SetRegANDOR(SISSR, 0x13, 0x80, reg); |
4844 | sisfb_post_xgi_delay(ivideo, 50); | 4844 | sisfb_post_xgi_delay(ivideo, 50); |
4845 | 4845 | ||
4846 | ranksize = (ivideo->chip == XGI_20) ? | 4846 | ranksize = (ivideo->chip == XGI_20) ? |
@@ -4865,7 +4865,7 @@ bail_out: | |||
4865 | 4865 | ||
4866 | if(!reg) continue; | 4866 | if(!reg) continue; |
4867 | 4867 | ||
4868 | setSISIDXREG(SISSR, 0x14, 0x0f, (reg & 0xf0)); | 4868 | SiS_SetRegANDOR(SISSR, 0x14, 0x0f, (reg & 0xf0)); |
4869 | sisfb_post_xgi_delay(ivideo, 1); | 4869 | sisfb_post_xgi_delay(ivideo, 1); |
4870 | 4870 | ||
4871 | if(sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize)) | 4871 | if(sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize)) |
@@ -5061,7 +5061,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5061 | 5061 | ||
5062 | if(ivideo->chip == XGI_40) { | 5062 | if(ivideo->chip == XGI_40) { |
5063 | if(ivideo->revision_id == 2) { | 5063 | if(ivideo->revision_id == 2) { |
5064 | setSISIDXREG(SISSR, 0x3b, 0x3f, 0xc0); | 5064 | SiS_SetRegANDOR(SISSR, 0x3b, 0x3f, 0xc0); |
5065 | } | 5065 | } |
5066 | SiS_SetReg(SISCR, 0x7d, 0xfe); | 5066 | SiS_SetReg(SISCR, 0x7d, 0xfe); |
5067 | SiS_SetReg(SISCR, 0x7e, 0x0f); | 5067 | SiS_SetReg(SISCR, 0x7e, 0x0f); |
@@ -5070,12 +5070,12 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5070 | SiS_SetRegAND(SISCR, 0x58, 0xd7); | 5070 | SiS_SetRegAND(SISCR, 0x58, 0xd7); |
5071 | reg = SiS_GetReg(SISCR, 0xcb); | 5071 | reg = SiS_GetReg(SISCR, 0xcb); |
5072 | if(reg & 0x20) { | 5072 | if(reg & 0x20) { |
5073 | setSISIDXREG(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */ | 5073 | SiS_SetRegANDOR(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */ |
5074 | } | 5074 | } |
5075 | } | 5075 | } |
5076 | 5076 | ||
5077 | reg = (ivideo->chip == XGI_40) ? 0x20 : 0x00; | 5077 | reg = (ivideo->chip == XGI_40) ? 0x20 : 0x00; |
5078 | setSISIDXREG(SISCR, 0x38, 0x1f, reg); | 5078 | SiS_SetRegANDOR(SISCR, 0x38, 0x1f, reg); |
5079 | 5079 | ||
5080 | if(ivideo->chip == XGI_20) { | 5080 | if(ivideo->chip == XGI_20) { |
5081 | SiS_SetReg(SISSR, 0x36, 0x70); | 5081 | SiS_SetReg(SISSR, 0x36, 0x70); |
@@ -5109,7 +5109,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5109 | if(reg & 0x20) reg |= 0x40; | 5109 | if(reg & 0x20) reg |= 0x40; |
5110 | SiS_SetReg(SISPART4, 0x23, reg); | 5110 | SiS_SetReg(SISPART4, 0x23, reg); |
5111 | reg = (reg & 0x20) ? 0x02 : 0x00; | 5111 | reg = (reg & 0x20) ? 0x02 : 0x00; |
5112 | setSISIDXREG(SISPART1, 0x1e, 0xfd, reg); | 5112 | SiS_SetRegANDOR(SISPART1, 0x1e, 0xfd, reg); |
5113 | } | 5113 | } |
5114 | } | 5114 | } |
5115 | 5115 | ||
@@ -5153,7 +5153,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5153 | v2 |= 0x08; | 5153 | v2 |= 0x08; |
5154 | } | 5154 | } |
5155 | } | 5155 | } |
5156 | setSISIDXREG(SISCR, 0x5f, 0xf0, v2); | 5156 | SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, v2); |
5157 | } | 5157 | } |
5158 | SiS_SetReg(SISSR, 0x22, v1); | 5158 | SiS_SetReg(SISSR, 0x22, v1); |
5159 | 5159 | ||
@@ -5162,14 +5162,14 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5162 | v2 = SiS_GetReg(SISSR, 0x3a); | 5162 | v2 = SiS_GetReg(SISSR, 0x3a); |
5163 | regd = bios[0x90 + 3] | (bios[0x90 + 4] << 8); | 5163 | regd = bios[0x90 + 3] | (bios[0x90 + 4] << 8); |
5164 | if( (!(v1 & 0x02)) && (v2 & 0x30) && (regd < 0xcf) ) | 5164 | if( (!(v1 & 0x02)) && (v2 & 0x30) && (regd < 0xcf) ) |
5165 | setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01); | 5165 | SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01); |
5166 | 5166 | ||
5167 | if((mypdev = pci_get_device(0x10de, 0x01e0, NULL))) { | 5167 | if((mypdev = pci_get_device(0x10de, 0x01e0, NULL))) { |
5168 | /* TODO: set CR5f &0xf1 | 0x01 for version 6570 | 5168 | /* TODO: set CR5f &0xf1 | 0x01 for version 6570 |
5169 | * of nforce 2 ROM | 5169 | * of nforce 2 ROM |
5170 | */ | 5170 | */ |
5171 | if(0) | 5171 | if(0) |
5172 | setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01); | 5172 | SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01); |
5173 | pci_dev_put(mypdev); | 5173 | pci_dev_put(mypdev); |
5174 | } | 5174 | } |
5175 | } | 5175 | } |
@@ -5182,7 +5182,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5182 | SiS_SetReg(SISSR, 0x27, v1); | 5182 | SiS_SetReg(SISSR, 0x27, v1); |
5183 | 5183 | ||
5184 | if(bios[0x64] & 0x01) { | 5184 | if(bios[0x64] & 0x01) { |
5185 | setSISIDXREG(SISCR, 0x5f, 0xf0, bios[0x64]); | 5185 | SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, bios[0x64]); |
5186 | } | 5186 | } |
5187 | 5187 | ||
5188 | v1 = bios[0x4f7]; | 5188 | v1 = bios[0x4f7]; |
@@ -5194,17 +5194,17 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5194 | } | 5194 | } |
5195 | SiS_SetReg(SISCR, 0x48, v1); | 5195 | SiS_SetReg(SISCR, 0x48, v1); |
5196 | 5196 | ||
5197 | setSISIDXREG(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb); | 5197 | SiS_SetRegANDOR(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb); |
5198 | setSISIDXREG(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f); | 5198 | SiS_SetRegANDOR(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f); |
5199 | setSISIDXREG(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f); | 5199 | SiS_SetRegANDOR(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f); |
5200 | setSISIDXREG(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7); | 5200 | SiS_SetRegANDOR(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7); |
5201 | setSISIDXREG(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f); | 5201 | SiS_SetRegANDOR(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f); |
5202 | SiS_SetReg(SISCR, 0x70, bios[0x4fc]); | 5202 | SiS_SetReg(SISCR, 0x70, bios[0x4fc]); |
5203 | setSISIDXREG(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f); | 5203 | SiS_SetRegANDOR(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f); |
5204 | SiS_SetReg(SISCR, 0x74, 0xd0); | 5204 | SiS_SetReg(SISCR, 0x74, 0xd0); |
5205 | setSISIDXREG(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30); | 5205 | SiS_SetRegANDOR(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30); |
5206 | setSISIDXREG(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f); | 5206 | SiS_SetRegANDOR(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f); |
5207 | setSISIDXREG(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f); | 5207 | SiS_SetRegANDOR(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f); |
5208 | v1 = bios[0x501]; | 5208 | v1 = bios[0x501]; |
5209 | if((mypdev = pci_get_device(0x8086, 0x2530, NULL))) { | 5209 | if((mypdev = pci_get_device(0x8086, 0x2530, NULL))) { |
5210 | v1 = 0xf0; | 5210 | v1 = 0xf0; |
@@ -5267,7 +5267,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
5267 | ptr = (const u8 *)&bios[index]; | 5267 | ptr = (const u8 *)&bios[index]; |
5268 | } | 5268 | } |
5269 | for(i = 0; i < 4; i++) { | 5269 | for(i = 0; i < 4; i++) { |
5270 | setSISIDXREG(SISCR, 0x6e, 0xfc, i); | 5270 | SiS_SetRegANDOR(SISCR, 0x6e, 0xfc, i); |
5271 | reg = 0x00; | 5271 | reg = 0x00; |
5272 | for(j = 0; j < 2; j++) { | 5272 | for(j = 0; j < 2; j++) { |
5273 | regd = 0; | 5273 | regd = 0; |