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authorJonathan Corbet <corbet@lwn.net>2010-03-27 15:08:23 -0400
committerJonathan Corbet <corbet@lwn.net>2010-04-20 16:23:20 -0400
commit1317824376482781200980c6f026ef576d7ed1dd (patch)
tree15a3a3760e32a55079c95dc494e5220d92166fbd /drivers/video/via/accel.c
parent107ea34db4560e6db41a9da90128ccc5e60f6b21 (diff)
viafb: complete support for VX800/VX855 accelerated framebuffer
This patch is a painful merge of change a90bab567ece3e915d0ccd55ab00c9bb333fa8c0 (viafb: Add support for 2D accelerated framebuffer on VX800/VX855) in the OLPC tree, originally by Harald Welte. Harald's changelog read: The VX800/VX820 and the VX855/VX875 chipsets have a different 2D acceleration engine called "M1". The M1 engine has some subtle (and some not-so-subtle) differences to the previous engines, so support for accelerated framebuffer on those chipsets was disabled so far. This merge tries to preserve Harald's changes in the framework of the much-changed 2.6.34 viafb code. Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: ScottFang@viatech.com.cn Cc: JosephChan@via.com.tw Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'drivers/video/via/accel.c')
-rw-r--r--drivers/video/via/accel.c42
1 files changed, 33 insertions, 9 deletions
diff --git a/drivers/video/via/accel.c b/drivers/video/via/accel.c
index 7c1d9c41623..0d90c859cc1 100644
--- a/drivers/video/via/accel.c
+++ b/drivers/video/via/accel.c
@@ -317,6 +317,7 @@ int viafb_init_engine(struct fb_info *info)
317{ 317{
318 struct viafb_par *viapar = info->par; 318 struct viafb_par *viapar = info->par;
319 void __iomem *engine; 319 void __iomem *engine;
320 int highest_reg, i;
320 u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high, 321 u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
321 vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name; 322 vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
322 323
@@ -328,6 +329,18 @@ int viafb_init_engine(struct fb_info *info)
328 return -ENOMEM; 329 return -ENOMEM;
329 } 330 }
330 331
332 /* Initialize registers to reset the 2D engine */
333 switch (viapar->shared->chip_info.twod_engine) {
334 case VIA_2D_ENG_M1:
335 highest_reg = 0x5c;
336 break;
337 default:
338 highest_reg = 0x40;
339 break;
340 }
341 for (i = 0; i <= highest_reg; i += 4)
342 writel(0x0, engine + i);
343
331 switch (chip_name) { 344 switch (chip_name) {
332 case UNICHROME_CLE266: 345 case UNICHROME_CLE266:
333 case UNICHROME_K400: 346 case UNICHROME_K400:
@@ -357,13 +370,12 @@ int viafb_init_engine(struct fb_info *info)
357 viapar->shared->vq_vram_addr = viapar->fbmem_free; 370 viapar->shared->vq_vram_addr = viapar->fbmem_free;
358 viapar->fbmem_used += VQ_SIZE; 371 viapar->fbmem_used += VQ_SIZE;
359 372
360 /* Init 2D engine reg to reset 2D engine */
361 writel(0x0, engine + VIA_REG_KEYCONTROL);
362
363 /* Init AGP and VQ regs */ 373 /* Init AGP and VQ regs */
364 switch (chip_name) { 374 switch (chip_name) {
365 case UNICHROME_K8M890: 375 case UNICHROME_K8M890:
366 case UNICHROME_P4M900: 376 case UNICHROME_P4M900:
377 case UNICHROME_VX800:
378 case UNICHROME_VX855:
367 writel(0x00100000, engine + VIA_REG_CR_TRANSET); 379 writel(0x00100000, engine + VIA_REG_CR_TRANSET);
368 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE); 380 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
369 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE); 381 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
@@ -398,6 +410,8 @@ int viafb_init_engine(struct fb_info *info)
398 switch (chip_name) { 410 switch (chip_name) {
399 case UNICHROME_K8M890: 411 case UNICHROME_K8M890:
400 case UNICHROME_P4M900: 412 case UNICHROME_P4M900:
413 case UNICHROME_VX800:
414 case UNICHROME_VX855:
401 vq_start_low |= 0x20000000; 415 vq_start_low |= 0x20000000;
402 vq_end_low |= 0x20000000; 416 vq_end_low |= 0x20000000;
403 vq_high |= 0x20000000; 417 vq_high |= 0x20000000;
@@ -475,15 +489,25 @@ void viafb_wait_engine_idle(struct fb_info *info)
475{ 489{
476 struct viafb_par *viapar = info->par; 490 struct viafb_par *viapar = info->par;
477 int loop = 0; 491 int loop = 0;
492 u32 mask;
478 493
479 while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) & 494 switch (viapar->shared->chip_info.twod_engine) {
480 VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) { 495 case VIA_2D_ENG_H5:
481 loop++; 496 case VIA_2D_ENG_M1:
482 cpu_relax(); 497 mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |
498 VIA_3D_ENG_BUSY_M1;
499 break;
500 default:
501 while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
502 VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
503 loop++;
504 cpu_relax();
505 }
506 mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;
507 break;
483 } 508 }
484 509
485 while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) & 510 while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) & mask) &&
486 (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
487 (loop < MAXLOOP)) { 511 (loop < MAXLOOP)) {
488 loop++; 512 loop++;
489 cpu_relax(); 513 cpu_relax();