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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/video/tegra/dc/rgb.c
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/video/tegra/dc/rgb.c')
-rw-r--r--drivers/video/tegra/dc/rgb.c160
1 files changed, 160 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/rgb.c b/drivers/video/tegra/dc/rgb.c
new file mode 100644
index 00000000000..2112643058f
--- /dev/null
+++ b/drivers/video/tegra/dc/rgb.c
@@ -0,0 +1,160 @@
1/*
2 * drivers/video/tegra/dc/rgb.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/kernel.h>
19
20#include <mach/dc.h>
21
22#include "dc_reg.h"
23#include "dc_priv.h"
24
25
26static const u32 tegra_dc_rgb_enable_partial_pintable[] = {
27 DC_COM_PIN_OUTPUT_ENABLE0, 0x00000000,
28 DC_COM_PIN_OUTPUT_ENABLE1, 0x00000000,
29 DC_COM_PIN_OUTPUT_ENABLE2, 0x00000000,
30 DC_COM_PIN_OUTPUT_ENABLE3, 0x00000000,
31 DC_COM_PIN_OUTPUT_POLARITY0, 0x00000000,
32 DC_COM_PIN_OUTPUT_POLARITY2, 0x00000000,
33 DC_COM_PIN_OUTPUT_DATA0, 0x00000000,
34 DC_COM_PIN_OUTPUT_DATA1, 0x00000000,
35 DC_COM_PIN_OUTPUT_DATA2, 0x00000000,
36 DC_COM_PIN_OUTPUT_DATA3, 0x00000000,
37};
38
39static const u32 tegra_dc_rgb_enable_pintable[] = {
40 DC_COM_PIN_OUTPUT_ENABLE0, 0x00000000,
41 DC_COM_PIN_OUTPUT_ENABLE1, 0x00000000,
42 DC_COM_PIN_OUTPUT_ENABLE2, 0x00000000,
43 DC_COM_PIN_OUTPUT_ENABLE3, 0x00000000,
44 DC_COM_PIN_OUTPUT_POLARITY0, 0x00000000,
45 DC_COM_PIN_OUTPUT_POLARITY1, 0x01000000,
46 DC_COM_PIN_OUTPUT_POLARITY2, 0x00000000,
47 DC_COM_PIN_OUTPUT_POLARITY3, 0x00000000,
48 DC_COM_PIN_OUTPUT_DATA0, 0x00000000,
49 DC_COM_PIN_OUTPUT_DATA1, 0x00000000,
50 DC_COM_PIN_OUTPUT_DATA2, 0x00000000,
51 DC_COM_PIN_OUTPUT_DATA3, 0x00000000,
52};
53
54static const u32 tegra_dc_rgb_enable_out_sel_pintable[] = {
55 DC_COM_PIN_OUTPUT_SELECT0, 0x00000000,
56 DC_COM_PIN_OUTPUT_SELECT1, 0x00000000,
57 DC_COM_PIN_OUTPUT_SELECT2, 0x00000000,
58#ifdef CONFIG_TEGRA_SILICON_PLATFORM
59 DC_COM_PIN_OUTPUT_SELECT3, 0x00000000,
60#else
61 /* The display panel sub-board used on FPGA platforms (panel 86)
62 is non-standard. It expects the Data Enable signal on the WR
63 pin instead of the DE pin. */
64 DC_COM_PIN_OUTPUT_SELECT3, 0x00200000,
65#endif
66 DC_COM_PIN_OUTPUT_SELECT4, 0x00210222,
67 DC_COM_PIN_OUTPUT_SELECT5, 0x00002200,
68 DC_COM_PIN_OUTPUT_SELECT6, 0x00020000,
69};
70
71static const u32 tegra_dc_rgb_disable_pintable[] = {
72 DC_COM_PIN_OUTPUT_ENABLE0, 0x55555555,
73 DC_COM_PIN_OUTPUT_ENABLE1, 0x55150005,
74 DC_COM_PIN_OUTPUT_ENABLE2, 0x55555555,
75 DC_COM_PIN_OUTPUT_ENABLE3, 0x55555555,
76 DC_COM_PIN_OUTPUT_POLARITY0, 0x00000000,
77 DC_COM_PIN_OUTPUT_POLARITY1, 0x00000000,
78 DC_COM_PIN_OUTPUT_POLARITY2, 0x00000000,
79 DC_COM_PIN_OUTPUT_POLARITY3, 0x00000000,
80 DC_COM_PIN_OUTPUT_DATA0, 0xaaaaaaaa,
81 DC_COM_PIN_OUTPUT_DATA1, 0xaaaaaaaa,
82 DC_COM_PIN_OUTPUT_DATA2, 0xaaaaaaaa,
83 DC_COM_PIN_OUTPUT_DATA3, 0xaaaaaaaa,
84 DC_COM_PIN_OUTPUT_SELECT0, 0x00000000,
85 DC_COM_PIN_OUTPUT_SELECT1, 0x00000000,
86 DC_COM_PIN_OUTPUT_SELECT2, 0x00000000,
87 DC_COM_PIN_OUTPUT_SELECT3, 0x00000000,
88 DC_COM_PIN_OUTPUT_SELECT4, 0x00000000,
89 DC_COM_PIN_OUTPUT_SELECT5, 0x00000000,
90 DC_COM_PIN_OUTPUT_SELECT6, 0x00000000,
91};
92
93void tegra_dc_rgb_enable(struct tegra_dc *dc)
94{
95 int i;
96 u32 out_sel_pintable[ARRAY_SIZE(tegra_dc_rgb_enable_out_sel_pintable)];
97
98 tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
99 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
100 DC_CMD_DISPLAY_POWER_CONTROL);
101
102 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
103
104 if (dc->out->out_pins) {
105 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
106 dc->out->n_out_pins);
107 tegra_dc_write_table(dc, tegra_dc_rgb_enable_partial_pintable);
108 } else {
109 tegra_dc_write_table(dc, tegra_dc_rgb_enable_pintable);
110 }
111
112 memcpy(out_sel_pintable, tegra_dc_rgb_enable_out_sel_pintable,
113 sizeof(tegra_dc_rgb_enable_out_sel_pintable));
114
115 if (dc->out && dc->out->out_sel_configs) {
116 u8 *out_sels = dc->out->out_sel_configs;
117 for (i = 0; i < dc->out->n_out_sel_configs; i++) {
118 switch (out_sels[i]) {
119 case TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1:
120 out_sel_pintable[5*2+1] =
121 (out_sel_pintable[5*2+1] &
122 ~PIN5_LM1_LCD_M1_OUTPUT_MASK) |
123 PIN5_LM1_LCD_M1_OUTPUT_M1;
124 break;
125 case TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21:
126 out_sel_pintable[5*2+1] =
127 (out_sel_pintable[5*2+1] &
128 ~PIN5_LM1_LCD_M1_OUTPUT_MASK) |
129 PIN5_LM1_LCD_M1_OUTPUT_LD21;
130 break;
131 case TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1:
132 out_sel_pintable[5*2+1] =
133 (out_sel_pintable[5*2+1] &
134 ~PIN5_LM1_LCD_M1_OUTPUT_MASK) |
135 PIN5_LM1_LCD_M1_OUTPUT_PM1;
136 break;
137 default:
138 dev_err(&dc->ndev->dev,
139 "Invalid pin config[%d]: %d\n",
140 i, out_sels[i]);
141 break;
142 }
143 }
144 }
145
146 tegra_dc_write_table(dc, out_sel_pintable);
147}
148
149void tegra_dc_rgb_disable(struct tegra_dc *dc)
150{
151 tegra_dc_writel(dc, 0x00000000, DC_CMD_DISPLAY_POWER_CONTROL);
152
153 tegra_dc_write_table(dc, tegra_dc_rgb_disable_pintable);
154}
155
156struct tegra_dc_out_ops tegra_dc_rgb_ops = {
157 .enable = tegra_dc_rgb_enable,
158 .disable = tegra_dc_rgb_disable,
159};
160
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