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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/video/tegra/dc/hdmi.c
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/video/tegra/dc/hdmi.c')
-rw-r--r--drivers/video/tegra/dc/hdmi.c2381
1 files changed, 2381 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/hdmi.c b/drivers/video/tegra/dc/hdmi.c
new file mode 100644
index 00000000000..cb401a167fd
--- /dev/null
+++ b/drivers/video/tegra/dc/hdmi.c
@@ -0,0 +1,2381 @@
1/*
2 * drivers/video/tegra/dc/hdmi.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
6 *
7 * Copyright (C) 2010-2011 NVIDIA Corporation
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/err.h>
23#include <linux/fb.h>
24#include <linux/gpio.h>
25#include <linux/interrupt.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/spinlock.h>
29#ifdef CONFIG_SWITCH
30#include <linux/switch.h>
31#endif
32#include <linux/workqueue.h>
33#include <linux/debugfs.h>
34#include <linux/seq_file.h>
35#include <linux/device.h>
36
37#include <mach/clk.h>
38#include <mach/dc.h>
39#include <mach/fb.h>
40#include <linux/nvhost.h>
41#include <mach/hdmi-audio.h>
42
43#include <video/tegrafb.h>
44
45#include "dc_reg.h"
46#include "dc_priv.h"
47#include "hdmi_reg.h"
48#include "hdmi.h"
49#include "edid.h"
50#include "nvhdcp.h"
51
52/* datasheet claims this will always be 216MHz */
53#define HDMI_AUDIOCLK_FREQ 216000000
54
55#define HDMI_REKEY_DEFAULT 56
56
57#define HDMI_ELD_RESERVED1_INDEX 1
58#define HDMI_ELD_RESERVED2_INDEX 3
59#define HDMI_ELD_VER_INDEX 0
60#define HDMI_ELD_BASELINE_LEN_INDEX 2
61#define HDMI_ELD_CEA_VER_MNL_INDEX 4
62#define HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX 5
63#define HDMI_ELD_AUD_SYNC_DELAY_INDEX 6
64#define HDMI_ELD_SPK_ALLOC_INDEX 7
65#define HDMI_ELD_PORT_ID_INDEX 8
66#define HDMI_ELD_MANF_NAME_INDEX 16
67#define HDMI_ELD_PRODUCT_CODE_INDEX 18
68#define HDMI_ELD_MONITOR_NAME_INDEX 20
69
70struct tegra_dc_hdmi_data {
71 struct tegra_dc *dc;
72 struct tegra_edid *edid;
73 struct tegra_edid_hdmi_eld eld;
74 struct tegra_nvhdcp *nvhdcp;
75 struct delayed_work work;
76
77 struct resource *base_res;
78 void __iomem *base;
79 struct clk *clk;
80
81 struct clk *disp1_clk;
82 struct clk *disp2_clk;
83 struct clk *hda_clk;
84 struct clk *hda2codec_clk;
85 struct clk *hda2hdmi_clk;
86
87#ifdef CONFIG_SWITCH
88 struct switch_dev hpd_switch;
89#endif
90
91 spinlock_t suspend_lock;
92 bool suspended;
93 bool eld_retrieved;
94 bool clk_enabled;
95 unsigned audio_freq;
96 unsigned audio_source;
97
98 bool dvi;
99};
100
101struct tegra_dc_hdmi_data *dc_hdmi;
102
103const struct fb_videomode tegra_dc_hdmi_supported_modes[] = {
104 /* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
105 {
106 .xres = 1280,
107 .yres = 720,
108 .pixclock = KHZ2PICOS(74250),
109 .hsync_len = 40, /* h_sync_width */
110 .vsync_len = 5, /* v_sync_width */
111 .left_margin = 220, /* h_back_porch */
112 .upper_margin = 20, /* v_back_porch */
113 .right_margin = 110, /* h_front_porch */
114 .lower_margin = 5, /* v_front_porch */
115 .vmode = FB_VMODE_NONINTERLACED,
116 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
117 },
118
119 /* 1280x720p 60hz: EIA/CEA-861-B Format 4 (Stereo)*/
120 {
121 .xres = 1280,
122 .yres = 720,
123 .pixclock = KHZ2PICOS(74250),
124 .hsync_len = 40, /* h_sync_width */
125 .vsync_len = 5, /* v_sync_width */
126 .left_margin = 220, /* h_back_porch */
127 .upper_margin = 20, /* v_back_porch */
128 .right_margin = 110, /* h_front_porch */
129 .lower_margin = 5, /* v_front_porch */
130 .vmode = FB_VMODE_NONINTERLACED |
131#ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
132 FB_VMODE_STEREO_FRAME_PACK,
133#else
134 FB_VMODE_STEREO_LEFT_RIGHT,
135#endif
136 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
137 },
138
139 /* 720x480p 59.94hz: EIA/CEA-861-B Formats 2 & 3 */
140 {
141 .xres = 720,
142 .yres = 480,
143 .pixclock = KHZ2PICOS(27000),
144 .hsync_len = 62, /* h_sync_width */
145 .vsync_len = 6, /* v_sync_width */
146 .left_margin = 60, /* h_back_porch */
147 .upper_margin = 30, /* v_back_porch */
148 .right_margin = 16, /* h_front_porch */
149 .lower_margin = 9, /* v_front_porch */
150 .vmode = FB_VMODE_NONINTERLACED,
151 .sync = 0,
152 },
153
154 /* 640x480p 60hz: EIA/CEA-861-B Format 1 */
155 {
156 .xres = 640,
157 .yres = 480,
158 .pixclock = KHZ2PICOS(25200),
159 .hsync_len = 96, /* h_sync_width */
160 .vsync_len = 2, /* v_sync_width */
161 .left_margin = 48, /* h_back_porch */
162 .upper_margin = 33, /* v_back_porch */
163 .right_margin = 16, /* h_front_porch */
164 .lower_margin = 10, /* v_front_porch */
165 .vmode = FB_VMODE_NONINTERLACED,
166 .sync = 0,
167 },
168
169 /* 720x576p 50hz EIA/CEA-861-B Formats 17 & 18 */
170 {
171 .xres = 720,
172 .yres = 576,
173 .pixclock = KHZ2PICOS(27000),
174 .hsync_len = 64, /* h_sync_width */
175 .vsync_len = 5, /* v_sync_width */
176 .left_margin = 68, /* h_back_porch */
177 .upper_margin = 39, /* v_back_porch */
178 .right_margin = 12, /* h_front_porch */
179 .lower_margin = 5, /* v_front_porch */
180 .vmode = FB_VMODE_NONINTERLACED,
181 .sync = 0,
182 },
183
184 /* 1920x1080p 23.98/24hz: EIA/CEA-861-B Format 32 (Stereo)*/
185 {
186 .xres = 1920,
187 .yres = 1080,
188 .pixclock = KHZ2PICOS(74250),
189 .hsync_len = 44, /* h_sync_width */
190 .vsync_len = 5, /* v_sync_width */
191 .left_margin = 148, /* h_back_porch */
192 .upper_margin = 36, /* v_back_porch */
193 .right_margin = 638, /* h_front_porch */
194 .lower_margin = 4, /* v_front_porch */
195 .vmode = FB_VMODE_NONINTERLACED |
196#ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
197 FB_VMODE_STEREO_FRAME_PACK,
198#else
199 FB_VMODE_STEREO_LEFT_RIGHT,
200#endif
201 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
202 },
203
204 /* 1920x1080p 30Hz EIA/CEA-861-B Format 34 */
205 {
206 .xres = 1920,
207 .yres = 1080,
208 .pixclock = KHZ2PICOS(74250),
209 .hsync_len = 44, /* h_sync_width */
210 .vsync_len = 5, /* v_sync_width */
211 .left_margin = 148, /* h_back_porch */
212 .upper_margin = 36, /* v_back_porch */
213 .right_margin = 88, /* h_front_porch */
214 .lower_margin = 4, /* v_front_porch */
215 .vmode = FB_VMODE_NONINTERLACED,
216 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
217 },
218 /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */
219 {
220 .xres = 1920,
221 .yres = 1080,
222 .pixclock = KHZ2PICOS(148500),
223 .hsync_len = 44, /* h_sync_width */
224 .vsync_len = 5, /* v_sync_width */
225 .left_margin = 148, /* h_back_porch */
226 .upper_margin = 36, /* v_back_porch */
227 .right_margin = 88, /* h_front_porch */
228 .lower_margin = 4, /* v_front_porch */
229 .vmode = FB_VMODE_NONINTERLACED,
230 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
231 },
232
233 /*
234 * Few VGA/SVGA modes to support monitors with lower
235 * resolutions or to support HDMI<->DVI connection
236 */
237
238 /* 640x480p 75hz */
239 {
240 .xres = 640,
241 .yres = 480,
242 .pixclock = KHZ2PICOS(31500),
243 .hsync_len = 96, /* h_sync_width */
244 .vsync_len = 2, /* v_sync_width */
245 .left_margin = 48, /* h_back_porch */
246 .upper_margin = 32, /* v_back_porch */
247 .right_margin = 16, /* h_front_porch */
248 .lower_margin = 1, /* v_front_porch */
249 .vmode = FB_VMODE_NONINTERLACED,
250 .sync = 0,
251 },
252 /* 720x400p 59hz */
253 {
254 .xres = 720,
255 .yres = 400,
256 .pixclock = KHZ2PICOS(35500),
257 .hsync_len = 72, /* h_sync_width */
258 .vsync_len = 3, /* v_sync_width */
259 .left_margin = 108, /* h_back_porch */
260 .upper_margin = 42, /* v_back_porch */
261 .right_margin = 36, /* h_front_porch */
262 .lower_margin = 1, /* v_front_porch */
263 .vmode = FB_VMODE_NONINTERLACED,
264 .sync = FB_SYNC_VERT_HIGH_ACT,
265 },
266 /* 800x600p 60hz */
267 {
268 .xres = 800,
269 .yres = 600,
270 .pixclock = KHZ2PICOS(40000),
271 .hsync_len = 128, /* h_sync_width */
272 .vsync_len = 4, /* v_sync_width */
273 .left_margin = 88, /* h_back_porch */
274 .upper_margin = 23, /* v_back_porch */
275 .right_margin = 40, /* h_front_porch */
276 .lower_margin = 1, /* v_front_porch */
277 .vmode = FB_VMODE_NONINTERLACED,
278 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
279 },
280 /* 800x600p 75hz */
281 {
282 .xres = 800,
283 .yres = 600,
284 .pixclock = KHZ2PICOS(49500),
285 .hsync_len = 80, /* h_sync_width */
286 .vsync_len = 2, /* v_sync_width */
287 .left_margin = 160, /* h_back_porch */
288 .upper_margin = 21, /* v_back_porch */
289 .right_margin = 16, /* h_front_porch */
290 .lower_margin = 1, /* v_front_porch */
291 .vmode = FB_VMODE_NONINTERLACED,
292 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
293 },
294 /* 1024x768p 60hz */
295 {
296 .xres = 1024,
297 .yres = 768,
298 .pixclock = KHZ2PICOS(65000),
299 .hsync_len = 136, /* h_sync_width */
300 .vsync_len = 6, /* v_sync_width */
301 .left_margin = 160, /* h_back_porch */
302 .upper_margin = 29, /* v_back_porch */
303 .right_margin = 24, /* h_front_porch */
304 .lower_margin = 3, /* v_front_porch */
305 .vmode = FB_VMODE_NONINTERLACED,
306 .sync = 0,
307 },
308 /* 1024x768p 75hz */
309 {
310 .xres = 1024,
311 .yres = 768,
312 .pixclock = KHZ2PICOS(78800),
313 .hsync_len = 96, /* h_sync_width */
314 .vsync_len = 3, /* v_sync_width */
315 .left_margin = 176, /* h_back_porch */
316 .upper_margin = 28, /* v_back_porch */
317 .right_margin = 16, /* h_front_porch */
318 .lower_margin = 1, /* v_front_porch */
319 .vmode = FB_VMODE_NONINTERLACED,
320 .sync = 0,
321 },
322 /* 1152x864p 75hz */
323 {
324 .xres = 1152,
325 .yres = 864,
326 .pixclock = KHZ2PICOS(108000),
327 .hsync_len = 128, /* h_sync_width */
328 .vsync_len = 3, /* v_sync_width */
329 .left_margin = 256, /* h_back_porch */
330 .upper_margin = 32, /* v_back_porch */
331 .right_margin = 64, /* h_front_porch */
332 .lower_margin = 1, /* v_front_porch */
333 .vmode = FB_VMODE_NONINTERLACED,
334 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
335 },
336 /* 1280x800p 60hz */
337 {
338 .xres = 1280,
339 .yres = 800,
340 .pixclock = KHZ2PICOS(83460),
341 .hsync_len = 136, /* h_sync_width */
342 .vsync_len = 3, /* v_sync_width */
343 .left_margin = 200, /* h_back_porch */
344 .upper_margin = 24, /* v_back_porch */
345 .right_margin = 64, /* h_front_porch */
346 .lower_margin = 1, /* v_front_porch */
347 .vmode = FB_VMODE_NONINTERLACED,
348 .sync = FB_SYNC_VERT_HIGH_ACT,
349 },
350 /* 1280x960p 60hz */
351 {
352 .xres = 1280,
353 .yres = 960,
354 .pixclock = KHZ2PICOS(108000),
355 .hsync_len = 136, /* h_sync_width */
356 .vsync_len = 3, /* v_sync_width */
357 .left_margin = 216, /* h_back_porch */
358 .upper_margin = 30, /* v_back_porch */
359 .right_margin = 80, /* h_front_porch */
360 .lower_margin = 1, /* v_front_porch */
361 .vmode = FB_VMODE_NONINTERLACED,
362 .sync = FB_SYNC_VERT_HIGH_ACT,
363 },
364 /* 1280x1024p 60hz */
365 {
366 .xres = 1280,
367 .yres = 1024,
368 .pixclock = KHZ2PICOS(108000),
369 .hsync_len = 112, /* h_sync_width */
370 .vsync_len = 3, /* v_sync_width */
371 .left_margin = 248, /* h_back_porch */
372 .upper_margin = 38, /* v_back_porch */
373 .right_margin = 48, /* h_front_porch */
374 .lower_margin = 1, /* v_front_porch */
375 .vmode = FB_VMODE_NONINTERLACED,
376 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
377 },
378 /* 1280x1024p 75hz */
379 {
380 .xres = 1280,
381 .yres = 1024,
382 .pixclock = KHZ2PICOS(135000),
383 .hsync_len = 144, /* h_sync_width */
384 .vsync_len = 3, /* v_sync_width */
385 .left_margin = 248, /* h_back_porch */
386 .upper_margin = 38, /* v_back_porch */
387 .right_margin = 16, /* h_front_porch */
388 .lower_margin = 1, /* v_front_porch */
389 .vmode = FB_VMODE_NONINTERLACED,
390 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
391 },
392 /* 1368x768p 60hz */
393 {
394 .xres = 1368,
395 .yres = 768,
396 .pixclock = KHZ2PICOS(85860),
397 .hsync_len = 144, /* h_sync_width */
398 .vsync_len = 3, /* v_sync_width */
399 .left_margin = 216, /* h_back_porch */
400 .upper_margin = 23, /* v_back_porch */
401 .right_margin = 72, /* h_front_porch */
402 .lower_margin = 1, /* v_front_porch */
403 .vmode = FB_VMODE_NONINTERLACED,
404 .sync = FB_SYNC_VERT_HIGH_ACT,
405 },
406 /* 1440x900p 60hz */
407 {
408 .xres = 1440,
409 .yres = 900,
410 .pixclock = KHZ2PICOS(106470),
411 .hsync_len = 152, /* h_sync_width */
412 .vsync_len = 3, /* v_sync_width */
413 .left_margin = 232, /* h_back_porch */
414 .upper_margin = 28, /* v_back_porch */
415 .right_margin = 80, /* h_front_porch */
416 .lower_margin = 1, /* v_front_porch */
417 .vmode = FB_VMODE_NONINTERLACED,
418 .sync = FB_SYNC_VERT_HIGH_ACT,
419 },
420 /* 1600x1200p 60hz */
421 {
422 .xres = 1600,
423 .yres = 1200,
424 .pixclock = KHZ2PICOS(162000),
425 .hsync_len = 192, /* h_sync_width */
426 .vsync_len = 3, /* v_sync_width */
427 .left_margin = 304, /* h_back_porch */
428 .upper_margin = 46, /* v_back_porch */
429 .right_margin = 64, /* h_front_porch */
430 .lower_margin = 1, /* v_front_porch */
431 .vmode = FB_VMODE_NONINTERLACED,
432 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
433 },
434 /* 1600x1200p 75hz */
435 {
436 .xres = 1600,
437 .yres = 1200,
438 .pixclock = KHZ2PICOS(202500),
439 .hsync_len = 192, /* h_sync_width */
440 .vsync_len = 3, /* v_sync_width */
441 .left_margin = 304, /* h_back_porch */
442 .upper_margin = 46, /* v_back_porch */
443 .right_margin = 64, /* h_front_porch */
444 .lower_margin = 1, /* v_front_porch */
445 .vmode = FB_VMODE_NONINTERLACED,
446 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
447 },
448 /* 1680x1050p 59.94/60hz */
449 {
450 .xres = 1680,
451 .yres = 1050,
452 .pixclock = KHZ2PICOS(147140),
453 .hsync_len = 184, /* h_sync_width */
454 .vsync_len = 3, /* v_sync_width */
455 .left_margin = 288, /* h_back_porch */
456 .upper_margin = 33, /* v_back_porch */
457 .right_margin = 104, /* h_front_porch */
458 .lower_margin = 1, /* v_front_porch */
459 .vmode = FB_VMODE_NONINTERLACED,
460 .sync = FB_SYNC_VERT_HIGH_ACT,
461 },
462};
463
464/* CVT timing representation of VESA modes*/
465const struct fb_videomode tegra_dc_hdmi_supported_cvt_modes[] = {
466
467 /* 640x480p 60hz */
468 {
469 .refresh = 60,
470 .xres = 640,
471 .yres = 480,
472 .pixclock = KHZ2PICOS(23750),
473 .hsync_len = 64, /* h_sync_width */
474 .vsync_len = 4, /* v_sync_width */
475 .left_margin = 80, /* h_back_porch */
476 .upper_margin = 17, /* v_back_porch */
477 .right_margin = 16, /* h_front_porch */
478 .lower_margin = 3, /* v_front_porch */
479 .vmode = FB_VMODE_NONINTERLACED,
480 .sync = FB_SYNC_VERT_HIGH_ACT,
481 },
482 /* 640x480p 75hz */
483 {
484 .refresh = 75,
485 .xres = 640,
486 .yres = 480,
487 .pixclock = KHZ2PICOS(30750),
488 .hsync_len = 64, /* h_sync_width */
489 .vsync_len = 4, /* v_sync_width */
490 .left_margin = 88, /* h_back_porch */
491 .upper_margin = 21, /* v_back_porch */
492 .right_margin = 24, /* h_front_porch */
493 .lower_margin = 3, /* v_front_porch */
494 .vmode = FB_VMODE_NONINTERLACED,
495 .sync = FB_SYNC_VERT_HIGH_ACT,
496 },
497 /* 720x400p 59hz */
498 {
499 .refresh = 59,
500 .xres = 720,
501 .yres = 400,
502 .pixclock = KHZ2PICOS(22000),
503 .hsync_len = 64, /* h_sync_width */
504 .vsync_len = 10, /* v_sync_width */
505 .left_margin = 88, /* h_back_porch */
506 .upper_margin = 14, /* v_back_porch */
507 .right_margin = 24, /* h_front_porch */
508 .lower_margin = 3, /* v_front_porch */
509 .vmode = FB_VMODE_NONINTERLACED,
510 .sync = FB_SYNC_VERT_HIGH_ACT,
511 },
512 /* 800x600p 60hz */
513 {
514 .refresh = 60,
515 .xres = 800,
516 .yres = 600,
517 .pixclock = KHZ2PICOS(38250),
518 .hsync_len = 80, /* h_sync_width */
519 .vsync_len = 4, /* v_sync_width */
520 .left_margin = 112, /* h_back_porch */
521 .upper_margin = 21, /* v_back_porch */
522 .right_margin = 32, /* h_front_porch */
523 .lower_margin = 3, /* v_front_porch */
524 .vmode = FB_VMODE_NONINTERLACED,
525 .sync = FB_SYNC_VERT_HIGH_ACT,
526 },
527 /* 800x600p 75hz */
528 {
529 .refresh = 75,
530 .xres = 800,
531 .yres = 600,
532 .pixclock = KHZ2PICOS(49000),
533 .hsync_len = 80, /* h_sync_width */
534 .vsync_len = 4, /* v_sync_width */
535 .left_margin = 120, /* h_back_porch */
536 .upper_margin = 26, /* v_back_porch */
537 .right_margin = 40, /* h_front_porch */
538 .lower_margin = 3, /* v_front_porch */
539 .vmode = FB_VMODE_NONINTERLACED,
540 .sync = FB_SYNC_VERT_HIGH_ACT,
541 },
542 /* 1024x768p 60hz */
543 {
544 .refresh = 60,
545 .xres = 1024,
546 .yres = 768,
547 .pixclock = KHZ2PICOS(63500),
548 .hsync_len = 104, /* h_sync_width */
549 .vsync_len = 4, /* v_sync_width */
550 .left_margin = 152, /* h_back_porch */
551 .upper_margin = 27, /* v_back_porch */
552 .right_margin = 48, /* h_front_porch */
553 .lower_margin = 3, /* v_front_porch */
554 .vmode = FB_VMODE_NONINTERLACED,
555 .sync = FB_SYNC_VERT_HIGH_ACT,
556 },
557 /* 1024x768p 75hz */
558 {
559 .refresh = 75,
560 .xres = 1024,
561 .yres = 768,
562 .pixclock = KHZ2PICOS(82000),
563 .hsync_len = 104, /* h_sync_width */
564 .vsync_len = 4, /* v_sync_width */
565 .left_margin = 168, /* h_back_porch */
566 .upper_margin = 34, /* v_back_porch */
567 .right_margin = 64, /* h_front_porch */
568 .lower_margin = 3, /* v_front_porch */
569 .vmode = FB_VMODE_NONINTERLACED,
570 .sync = FB_SYNC_VERT_HIGH_ACT,
571 },
572 /* 1152x864p 75hz */
573 {
574 .refresh = 75,
575 .xres = 1152,
576 .yres = 864,
577 .pixclock = KHZ2PICOS(104500),
578 .hsync_len = 120, /* h_sync_width */
579 .vsync_len = 10, /* v_sync_width */
580 .left_margin = 192, /* h_back_porch */
581 .upper_margin = 38, /* v_back_porch */
582 .right_margin = 72, /* h_front_porch */
583 .lower_margin = 3, /* v_front_porch */
584 .vmode = FB_VMODE_NONINTERLACED,
585 .sync = FB_SYNC_VERT_HIGH_ACT,
586 },
587 /* 1280x800p 60hz */
588 {
589 .refresh = 60,
590 .xres = 1280,
591 .yres = 800,
592 .pixclock = KHZ2PICOS(83500),
593 .hsync_len = 128, /* h_sync_width */
594 .vsync_len = 6, /* v_sync_width */
595 .left_margin = 200, /* h_back_porch */
596 .upper_margin = 28, /* v_back_porch */
597 .right_margin = 72, /* h_front_porch */
598 .lower_margin = 3, /* v_front_porch */
599 .vmode = FB_VMODE_NONINTERLACED,
600 .sync = FB_SYNC_VERT_HIGH_ACT,
601 },
602 /* 1280x960p 60hz */
603 {
604 .refresh = 60,
605 .xres = 1280,
606 .yres = 960,
607 .pixclock = KHZ2PICOS(101250),
608 .hsync_len = 128, /* h_sync_width */
609 .vsync_len = 4, /* v_sync_width */
610 .left_margin = 208, /* h_back_porch */
611 .upper_margin = 33, /* v_back_porch */
612 .right_margin = 80, /* h_front_porch */
613 .lower_margin = 3, /* v_front_porch */
614 .vmode = FB_VMODE_NONINTERLACED,
615 .sync = FB_SYNC_VERT_HIGH_ACT,
616 },
617 /* 1280x1024p 60hz */
618 {
619 .refresh = 60,
620 .xres = 1280,
621 .yres = 1024,
622 .pixclock = KHZ2PICOS(109000),
623 .hsync_len = 136, /* h_sync_width */
624 .vsync_len = 7, /* v_sync_width */
625 .left_margin = 216, /* h_back_porch */
626 .upper_margin = 36, /* v_back_porch */
627 .right_margin = 80, /* h_front_porch */
628 .lower_margin = 3, /* v_front_porch */
629 .vmode = FB_VMODE_NONINTERLACED,
630 .sync = FB_SYNC_VERT_HIGH_ACT,
631 },
632
633 /* 1280x1024p 75hz */
634 {
635 .refresh = 75,
636 .xres = 1280,
637 .yres = 1024,
638 .pixclock = KHZ2PICOS(138750),
639 .hsync_len = 136, /* h_sync_width */
640 .vsync_len = 7, /* v_sync_width */
641 .left_margin = 224, /* h_back_porch */
642 .upper_margin = 45, /* v_back_porch */
643 .right_margin = 88, /* h_front_porch */
644 .lower_margin = 3, /* v_front_porch */
645 .vmode = FB_VMODE_NONINTERLACED,
646 .sync = FB_SYNC_VERT_HIGH_ACT,
647 },
648 /* 1368x768p 60hz */
649 {
650 .refresh = 60,
651 .xres = 1368,
652 .yres = 768,
653 .pixclock = KHZ2PICOS(85250),
654 .hsync_len = 136, /* h_sync_width */
655 .vsync_len = 10, /* v_sync_width */
656 .left_margin = 208, /* h_back_porch */
657 .upper_margin = 27, /* v_back_porch */
658 .right_margin = 72, /* h_front_porch */
659 .lower_margin = 3, /* v_front_porch */
660 .vmode = FB_VMODE_NONINTERLACED,
661 .sync = FB_SYNC_VERT_HIGH_ACT,
662 },
663 /* 1440x900p 60hz */
664 {
665 .refresh = 60,
666 .xres = 1440,
667 .yres = 900,
668 .pixclock = KHZ2PICOS(106500),
669 .hsync_len = 152, /* h_sync_width */
670 .vsync_len = 6, /* v_sync_width */
671 .left_margin = 232, /* h_back_porch */
672 .upper_margin = 31, /* v_back_porch */
673 .right_margin = 80, /* h_front_porch */
674 .lower_margin = 3, /* v_front_porch */
675 .vmode = FB_VMODE_NONINTERLACED,
676 .sync = FB_SYNC_VERT_HIGH_ACT,
677 },
678 /* 1600x1200p 60hz */
679 {
680 .refresh = 60,
681 .xres = 1600,
682 .yres = 1200,
683 .pixclock = KHZ2PICOS(161000),
684 .hsync_len = 168, /* h_sync_width */
685 .vsync_len = 4, /* v_sync_width */
686 .left_margin = 280, /* h_back_porch */
687 .upper_margin = 42, /* v_back_porch */
688 .right_margin = 112, /* h_front_porch */
689 .lower_margin = 3, /* v_front_porch */
690 .vmode = FB_VMODE_NONINTERLACED,
691 .sync = FB_SYNC_VERT_HIGH_ACT,
692 },
693 /* 1600x1200p 75hz */
694 {
695 .refresh = 75,
696 .xres = 1600,
697 .yres = 1200,
698 .pixclock = KHZ2PICOS(204750),
699 .hsync_len = 168, /* h_sync_width */
700 .vsync_len = 4, /* v_sync_width */
701 .left_margin = 288, /* h_back_porch */
702 .upper_margin = 52, /* v_back_porch */
703 .right_margin = 120, /* h_front_porch */
704 .lower_margin = 3, /* v_front_porch */
705 .vmode = FB_VMODE_NONINTERLACED,
706 .sync = FB_SYNC_VERT_HIGH_ACT,
707 },
708 /* 1680x1050p 59.94/60hz */
709 {
710 .refresh = 60,
711 .xres = 1680,
712 .yres = 1050,
713 .pixclock = KHZ2PICOS(140000),
714 .hsync_len = 168, /* h_sync_width */
715 .vsync_len = 10, /* v_sync_width */
716 .left_margin = 272, /* h_back_porch */
717 .upper_margin = 36, /* v_back_porch */
718 .right_margin = 104, /* h_front_porch */
719 .lower_margin = 3, /* v_front_porch */
720 .vmode = FB_VMODE_NONINTERLACED,
721 .sync = FB_SYNC_VERT_HIGH_ACT,
722 },
723};
724
725/* table of electrical settings, must be in acending order. */
726struct tdms_config {
727 int pclk;
728 u32 pll0;
729 u32 pll1;
730 u32 pe_current; /* pre-emphasis */
731 u32 drive_current;
732};
733
734#ifndef CONFIG_ARCH_TEGRA_2x_SOC
735const struct tdms_config tdms_config[] = {
736 { /* 480p modes */
737 .pclk = 27000000,
738 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
739 SOR_PLL_VCOCAP(0) | SOR_PLL_TX_REG_LOAD(0),
740 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
741 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
742 PE_CURRENT1(PE_CURRENT_0_0_mA) |
743 PE_CURRENT2(PE_CURRENT_0_0_mA) |
744 PE_CURRENT3(PE_CURRENT_0_0_mA),
745 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
746 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
747 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
748 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
749 },
750 { /* 720p modes */
751 .pclk = 74250000,
752 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
753 SOR_PLL_VCOCAP(1) | SOR_PLL_TX_REG_LOAD(0),
754 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
755 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
756 PE_CURRENT1(PE_CURRENT_5_0_mA) |
757 PE_CURRENT2(PE_CURRENT_5_0_mA) |
758 PE_CURRENT3(PE_CURRENT_5_0_mA),
759 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
760 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
761 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
762 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
763 },
764 { /* 1080p modes */
765 .pclk = INT_MAX,
766 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
767 SOR_PLL_VCOCAP(3) | SOR_PLL_TX_REG_LOAD(0),
768 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
769 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
770 PE_CURRENT1(PE_CURRENT_5_0_mA) |
771 PE_CURRENT2(PE_CURRENT_5_0_mA) |
772 PE_CURRENT3(PE_CURRENT_5_0_mA),
773 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
774 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
775 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
776 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
777 },
778};
779#else /* CONFIG_ARCH_TEGRA_2x_SOC */
780const struct tdms_config tdms_config[] = {
781 { /* 480p modes */
782 .pclk = 27000000,
783 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
784 SOR_PLL_VCOCAP(0) | SOR_PLL_TX_REG_LOAD(3),
785 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
786 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
787 PE_CURRENT1(PE_CURRENT_0_0_mA) |
788 PE_CURRENT2(PE_CURRENT_0_0_mA) |
789 PE_CURRENT3(PE_CURRENT_0_0_mA),
790 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
791 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
792 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
793 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
794 },
795 { /* 720p modes */
796 .pclk = 74250000,
797 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
798 SOR_PLL_VCOCAP(1) | SOR_PLL_TX_REG_LOAD(3),
799 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
800 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
801 PE_CURRENT1(PE_CURRENT_6_0_mA) |
802 PE_CURRENT2(PE_CURRENT_6_0_mA) |
803 PE_CURRENT3(PE_CURRENT_6_0_mA),
804 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
805 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
806 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
807 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
808 },
809 { /* 1080p modes */
810 .pclk = INT_MAX,
811 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
812 SOR_PLL_VCOCAP(1) | SOR_PLL_TX_REG_LOAD(3),
813 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
814 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
815 PE_CURRENT1(PE_CURRENT_6_0_mA) |
816 PE_CURRENT2(PE_CURRENT_6_0_mA) |
817 PE_CURRENT3(PE_CURRENT_6_0_mA),
818 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
819 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
820 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
821 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
822 },
823};
824#endif
825
826struct tegra_hdmi_audio_config {
827 unsigned pix_clock;
828 unsigned n;
829 unsigned cts;
830 unsigned aval;
831};
832
833
834const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
835 {25200000, 4096, 25200, 24000},
836 {27000000, 4096, 27000, 24000},
837 {74250000, 4096, 74250, 24000},
838 {148500000, 4096, 148500, 24000},
839 {0, 0, 0},
840};
841
842const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
843 {25200000, 5880, 26250, 25000},
844 {27000000, 5880, 28125, 25000},
845 {74250000, 4704, 61875, 20000},
846 {148500000, 4704, 123750, 20000},
847 {0, 0, 0},
848};
849
850const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
851 {25200000, 6144, 25200, 24000},
852 {27000000, 6144, 27000, 24000},
853 {74250000, 6144, 74250, 24000},
854 {148500000, 6144, 148500, 24000},
855 {0, 0, 0},
856};
857
858const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
859 {25200000, 11760, 26250, 25000},
860 {27000000, 11760, 28125, 25000},
861 {74250000, 9408, 61875, 20000},
862 {148500000, 9408, 123750, 20000},
863 {0, 0, 0},
864};
865
866const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
867 {25200000, 12288, 25200, 24000},
868 {27000000, 12288, 27000, 24000},
869 {74250000, 12288, 74250, 24000},
870 {148500000, 12288, 148500, 24000},
871 {0, 0, 0},
872};
873
874const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
875 {25200000, 23520, 26250, 25000},
876 {27000000, 23520, 28125, 25000},
877 {74250000, 18816, 61875, 20000},
878 {148500000, 18816, 123750, 20000},
879 {0, 0, 0},
880};
881
882const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
883 {25200000, 24576, 25200, 24000},
884 {27000000, 24576, 27000, 24000},
885 {74250000, 24576, 74250, 24000},
886 {148500000, 24576, 148500, 24000},
887 {0, 0, 0},
888};
889
890static const struct tegra_hdmi_audio_config
891*tegra_hdmi_get_audio_config(unsigned audio_freq, unsigned pix_clock)
892{
893 const struct tegra_hdmi_audio_config *table;
894
895 switch (audio_freq) {
896 case AUDIO_FREQ_32K:
897 table = tegra_hdmi_audio_32k;
898 break;
899 case AUDIO_FREQ_44_1K:
900 table = tegra_hdmi_audio_44_1k;
901 break;
902 case AUDIO_FREQ_48K:
903 table = tegra_hdmi_audio_48k;
904 break;
905 case AUDIO_FREQ_88_2K:
906 table = tegra_hdmi_audio_88_2k;
907 break;
908 case AUDIO_FREQ_96K:
909 table = tegra_hdmi_audio_96k;
910 break;
911 case AUDIO_FREQ_176_4K:
912 table = tegra_hdmi_audio_176_4k;
913 break;
914 case AUDIO_FREQ_192K:
915 table = tegra_hdmi_audio_192k;
916 break;
917 default:
918 return NULL;
919 }
920
921 while (table->pix_clock) {
922 if (table->pix_clock == pix_clock)
923 return table;
924 table++;
925 }
926
927 return NULL;
928}
929
930
931unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
932 unsigned long reg)
933{
934 return readl(hdmi->base + reg * 4);
935}
936
937void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
938 unsigned long val, unsigned long reg)
939{
940 writel(val, hdmi->base + reg * 4);
941}
942
943static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
944 unsigned long reg, unsigned long clr,
945 unsigned long set)
946{
947 unsigned long val = tegra_hdmi_readl(hdmi, reg);
948 val &= ~clr;
949 val |= set;
950 tegra_hdmi_writel(hdmi, val, reg);
951}
952
953#ifdef CONFIG_DEBUG_FS
954static int dbg_hdmi_show(struct seq_file *s, void *unused)
955{
956 struct tegra_dc_hdmi_data *hdmi = s->private;
957
958#define DUMP_REG(a) do { \
959 seq_printf(s, "%-32s\t%03x\t%08lx\n", \
960 #a, a, tegra_hdmi_readl(hdmi, a)); \
961 } while (0)
962
963 tegra_dc_io_start(hdmi->dc);
964 clk_enable(hdmi->clk);
965
966 DUMP_REG(HDMI_CTXSW);
967 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
968 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
969 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
970 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
971 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
972 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
973 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
974 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
975 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
976 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
977 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
978 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
979 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
980 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
981 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
982 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
983 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
984 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
985 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
986 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
987 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
988 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
989 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
990 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
991 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
992 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
993 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
994 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
995 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
996 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
997 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
998 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
999 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1000 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1001 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1002 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1003 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1004 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1005 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1006 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1007 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1008 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1009 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1010 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1011 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1012 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1013 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1014 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1015 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1016 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1017 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1018 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1019 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1020 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1021 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1022 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1023 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1024 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1025 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1026 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1027 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1028 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1029 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1030 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1031 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1032 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1033 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1034 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1035 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1036 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1037 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1038 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1039 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1040 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1041 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1042 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1043 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1044 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1045 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1046 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1047 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1048 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_CTRL);
1049 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1050 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1051 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1052 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1053 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1054 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1055 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1056 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1057 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1058 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1059 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1060 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1061 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST0);
1062 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST1);
1063 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST2);
1064 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST3);
1065 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST4);
1066 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST5);
1067 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST6);
1068 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST7);
1069 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST8);
1070 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST9);
1071 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTA);
1072 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTB);
1073 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTC);
1074 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTD);
1075 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTE);
1076 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTF);
1077 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1078 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1079 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1080 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1081 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1082 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1083 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1084 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1085 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1086 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1087 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1088 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1089 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1090 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1091 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1092 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1093 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1094 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1095 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1096 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1097 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1098 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1099 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1100 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1101 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1102 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1103 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1104 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1105 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1106 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1107 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1108 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1109 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1110 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1111 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1112 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1113 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1114 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1115 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1116 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1117 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1118 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1119 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1120#undef DUMP_REG
1121
1122 clk_disable(hdmi->clk);
1123 tegra_dc_io_end(hdmi->dc);
1124
1125 return 0;
1126}
1127
1128static int dbg_hdmi_open(struct inode *inode, struct file *file)
1129{
1130 return single_open(file, dbg_hdmi_show, inode->i_private);
1131}
1132
1133static const struct file_operations dbg_fops = {
1134 .open = dbg_hdmi_open,
1135 .read = seq_read,
1136 .llseek = seq_lseek,
1137 .release = single_release,
1138};
1139
1140static struct dentry *hdmidir;
1141
1142static void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
1143{
1144 struct dentry *retval;
1145
1146 hdmidir = debugfs_create_dir("tegra_hdmi", NULL);
1147 if (!hdmidir)
1148 return;
1149 retval = debugfs_create_file("regs", S_IRUGO, hdmidir, hdmi,
1150 &dbg_fops);
1151 if (!retval)
1152 goto free_out;
1153 return;
1154free_out:
1155 debugfs_remove_recursive(hdmidir);
1156 hdmidir = NULL;
1157 return;
1158}
1159#else
1160static inline void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
1161{ }
1162#endif
1163
1164#define PIXCLOCK_TOLERANCE 200
1165
1166static int tegra_dc_calc_clock_per_frame(const struct fb_videomode *mode)
1167{
1168 return (mode->left_margin + mode->xres +
1169 mode->right_margin + mode->hsync_len) *
1170 (mode->upper_margin + mode->yres +
1171 mode->lower_margin + mode->vsync_len);
1172}
1173static bool tegra_dc_hdmi_mode_equal(const struct fb_videomode *mode1,
1174 const struct fb_videomode *mode2)
1175{
1176 int clock_per_frame1 = tegra_dc_calc_clock_per_frame(mode1);
1177 int clock_per_frame2 = tegra_dc_calc_clock_per_frame(mode2);
1178
1179 /* allows up to 1Hz of pixclock difference */
1180 return (clock_per_frame1 == clock_per_frame2 &&
1181 mode1->xres == mode2->xres &&
1182 mode1->yres == mode2->yres &&
1183 mode1->vmode == mode2->vmode &&
1184 (mode1->pixclock == mode2->pixclock ||
1185 (abs(PICOS2KHZ(mode1->pixclock) -
1186 PICOS2KHZ(mode2->pixclock)) *
1187 1000 / clock_per_frame1 <= 1)));
1188}
1189
1190static bool tegra_dc_hdmi_valid_pixclock(const struct tegra_dc *dc,
1191 const struct fb_videomode *mode)
1192{
1193 unsigned max_pixclock = tegra_dc_get_out_max_pixclock(dc);
1194 if (max_pixclock) {
1195 /* this might look counter-intuitive,
1196 * but pixclock's unit is picos(not Khz)
1197 */
1198 return mode->pixclock >= max_pixclock;
1199 } else {
1200 return true;
1201 }
1202}
1203
1204static bool tegra_dc_cvt_mode_equal(const struct fb_videomode *mode1,
1205 const struct fb_videomode *mode2)
1206{
1207 return (mode1->xres == mode2->xres &&
1208 mode1->yres == mode2->yres &&
1209 mode1->refresh == mode2->refresh &&
1210 mode1->vmode == mode2->vmode);
1211}
1212
1213static bool tegra_dc_reload_mode(struct fb_videomode *mode)
1214{
1215 int i = 0;
1216 for (i = 0; i < ARRAY_SIZE(tegra_dc_hdmi_supported_cvt_modes); i++) {
1217 const struct fb_videomode *cvt_mode
1218 = &tegra_dc_hdmi_supported_cvt_modes[i];
1219 if (tegra_dc_cvt_mode_equal(cvt_mode, mode)) {
1220 memcpy(mode, cvt_mode, sizeof(*mode));
1221 return true;
1222 }
1223 }
1224 return false;
1225}
1226
1227
1228static bool tegra_dc_hdmi_mode_filter(const struct tegra_dc *dc,
1229 struct fb_videomode *mode)
1230{
1231 int i;
1232 int clock_per_frame;
1233
1234 if (!mode->pixclock)
1235 return false;
1236
1237#ifdef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1238 if (PICOS2KHZ(mode->pixclock) > 74250)
1239 return false;
1240#endif
1241
1242 for (i = 0; i < ARRAY_SIZE(tegra_dc_hdmi_supported_modes); i++) {
1243 const struct fb_videomode *supported_mode
1244 = &tegra_dc_hdmi_supported_modes[i];
1245 if (tegra_dc_hdmi_mode_equal(supported_mode, mode) &&
1246 tegra_dc_hdmi_valid_pixclock(dc, supported_mode)) {
1247 if (mode->lower_margin == 1) {
1248 /* This might be the case for HDMI<->DVI
1249 * where std VESA representation will not
1250 * pass constraint V_FRONT_PORCH >=
1251 * V_REF_TO_SYNC + 1.So reload mode in
1252 * CVT timing standards.
1253 */
1254 if (!tegra_dc_reload_mode(mode))
1255 return false;
1256 }
1257 else
1258 memcpy(mode, supported_mode, sizeof(*mode));
1259
1260 mode->flag = FB_MODE_IS_DETAILED;
1261 clock_per_frame = tegra_dc_calc_clock_per_frame(mode);
1262 mode->refresh = (PICOS2KHZ(mode->pixclock) * 1000)
1263 / clock_per_frame;
1264 return true;
1265 }
1266 }
1267
1268 return false;
1269}
1270
1271
1272static bool tegra_dc_hdmi_hpd(struct tegra_dc *dc)
1273{
1274 int sense;
1275 int level;
1276
1277 level = gpio_get_value(dc->out->hotplug_gpio);
1278
1279 sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
1280
1281 return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
1282 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
1283}
1284
1285
1286void tegra_dc_hdmi_detect_config(struct tegra_dc *dc,
1287 struct fb_monspecs *specs)
1288{
1289 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1290
1291 /* monitors like to lie about these but they are still useful for
1292 * detecting aspect ratios
1293 */
1294 dc->out->h_size = specs->max_x * 1000;
1295 dc->out->v_size = specs->max_y * 1000;
1296
1297 hdmi->dvi = !(specs->misc & FB_MISC_HDMI);
1298
1299 tegra_fb_update_monspecs(dc->fb, specs, tegra_dc_hdmi_mode_filter);
1300#ifdef CONFIG_SWITCH
1301 hdmi->hpd_switch.state = 0;
1302 switch_set_state(&hdmi->hpd_switch, 1);
1303#endif
1304 dev_info(&dc->ndev->dev, "display detected\n");
1305
1306 dc->connected = true;
1307 tegra_dc_ext_process_hotplug(dc->ndev->id);
1308}
1309
1310/* This function is used to enable DC1 and HDMI for the purpose of testing. */
1311bool tegra_dc_hdmi_detect_test(struct tegra_dc *dc, unsigned char *edid_ptr)
1312{
1313 int err;
1314 struct fb_monspecs specs;
1315 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1316
1317 if (!hdmi || !edid_ptr) {
1318 dev_err(&dc->ndev->dev, "HDMI test failed to get arguments.\n");
1319 return false;
1320 }
1321
1322 err = tegra_edid_get_monspecs_test(hdmi->edid, &specs, edid_ptr);
1323 if (err < 0) {
1324 dev_err(&dc->ndev->dev, "error reading edid\n");
1325 goto fail;
1326 }
1327
1328 err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
1329 if (err < 0) {
1330 dev_err(&dc->ndev->dev, "error populating eld\n");
1331 goto fail;
1332 }
1333 hdmi->eld_retrieved = true;
1334
1335 tegra_dc_hdmi_detect_config(dc, &specs);
1336
1337 return true;
1338
1339fail:
1340 hdmi->eld_retrieved = false;
1341#ifdef CONFIG_SWITCH
1342 switch_set_state(&hdmi->hpd_switch, 0);
1343#endif
1344 tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
1345 return false;
1346}
1347EXPORT_SYMBOL(tegra_dc_hdmi_detect_test);
1348
1349static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
1350{
1351 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1352 struct fb_monspecs specs;
1353 int err;
1354
1355 if (!tegra_dc_hdmi_hpd(dc))
1356 goto fail;
1357
1358 err = tegra_edid_get_monspecs(hdmi->edid, &specs);
1359 if (err < 0) {
1360 dev_err(&dc->ndev->dev, "error reading edid\n");
1361 goto fail;
1362 }
1363
1364 err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
1365 if (err < 0) {
1366 dev_err(&dc->ndev->dev, "error populating eld\n");
1367 goto fail;
1368 }
1369 hdmi->eld_retrieved = true;
1370
1371 tegra_dc_hdmi_detect_config(dc, &specs);
1372
1373 return true;
1374
1375fail:
1376 hdmi->eld_retrieved = false;
1377#ifdef CONFIG_SWITCH
1378 switch_set_state(&hdmi->hpd_switch, 0);
1379#endif
1380 tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
1381 return false;
1382}
1383
1384
1385static void tegra_dc_hdmi_detect_worker(struct work_struct *work)
1386{
1387 struct tegra_dc_hdmi_data *hdmi =
1388 container_of(to_delayed_work(work), struct tegra_dc_hdmi_data, work);
1389 struct tegra_dc *dc = hdmi->dc;
1390
1391 tegra_dc_enable(dc);
1392 msleep(5);
1393 if (!tegra_dc_hdmi_detect(dc)) {
1394 tegra_dc_disable(dc);
1395 tegra_fb_update_monspecs(dc->fb, NULL, NULL);
1396
1397 dc->connected = false;
1398 tegra_dc_ext_process_hotplug(dc->ndev->id);
1399 }
1400}
1401
1402static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
1403{
1404 struct tegra_dc *dc = ptr;
1405 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1406 unsigned long flags;
1407
1408 spin_lock_irqsave(&hdmi->suspend_lock, flags);
1409 if (!hdmi->suspended) {
1410 __cancel_delayed_work(&hdmi->work);
1411 if (tegra_dc_hdmi_hpd(dc))
1412 queue_delayed_work(system_nrt_wq, &hdmi->work,
1413 msecs_to_jiffies(100));
1414 else
1415 queue_delayed_work(system_nrt_wq, &hdmi->work,
1416 msecs_to_jiffies(30));
1417 }
1418 spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
1419
1420 return IRQ_HANDLED;
1421}
1422
1423static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
1424{
1425 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1426 unsigned long flags;
1427
1428 tegra_nvhdcp_suspend(hdmi->nvhdcp);
1429 spin_lock_irqsave(&hdmi->suspend_lock, flags);
1430 hdmi->suspended = true;
1431 spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
1432}
1433
1434static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
1435{
1436 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1437 unsigned long flags;
1438
1439 spin_lock_irqsave(&hdmi->suspend_lock, flags);
1440 hdmi->suspended = false;
1441
1442 if (tegra_dc_hdmi_hpd(dc))
1443 queue_delayed_work(system_nrt_wq, &hdmi->work,
1444 msecs_to_jiffies(100));
1445 else
1446 queue_delayed_work(system_nrt_wq, &hdmi->work,
1447 msecs_to_jiffies(30));
1448
1449 spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
1450 tegra_nvhdcp_resume(hdmi->nvhdcp);
1451}
1452
1453static ssize_t underscan_show(struct device *dev,
1454 struct device_attribute *attr, char *buf)
1455{
1456#ifdef CONFIG_SWITCH
1457 struct tegra_dc_hdmi_data *hdmi =
1458 container_of(dev_get_drvdata(dev), struct tegra_dc_hdmi_data, hpd_switch);
1459
1460 if (hdmi->edid)
1461 return sprintf(buf, "%d\n", tegra_edid_underscan_supported(hdmi->edid));
1462 else
1463 return 0;
1464#else
1465 return 0;
1466#endif
1467}
1468
1469static DEVICE_ATTR(underscan, S_IRUGO | S_IWUSR, underscan_show, NULL);
1470
1471static int tegra_dc_hdmi_init(struct tegra_dc *dc)
1472{
1473 struct tegra_dc_hdmi_data *hdmi;
1474 struct resource *res;
1475 struct resource *base_res;
1476 int ret;
1477 void __iomem *base;
1478 struct clk *clk = NULL;
1479 struct clk *disp1_clk = NULL;
1480 struct clk *disp2_clk = NULL;
1481 int err;
1482
1483 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1484 if (!hdmi)
1485 return -ENOMEM;
1486
1487 res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "hdmi_regs");
1488 if (!res) {
1489 dev_err(&dc->ndev->dev, "hdmi: no mem resource\n");
1490 err = -ENOENT;
1491 goto err_free_hdmi;
1492 }
1493
1494 base_res = request_mem_region(res->start, resource_size(res), dc->ndev->name);
1495 if (!base_res) {
1496 dev_err(&dc->ndev->dev, "hdmi: request_mem_region failed\n");
1497 err = -EBUSY;
1498 goto err_free_hdmi;
1499 }
1500
1501 base = ioremap(res->start, resource_size(res));
1502 if (!base) {
1503 dev_err(&dc->ndev->dev, "hdmi: registers can't be mapped\n");
1504 err = -EBUSY;
1505 goto err_release_resource_reg;
1506 }
1507
1508 clk = clk_get(&dc->ndev->dev, "hdmi");
1509 if (IS_ERR_OR_NULL(clk)) {
1510 dev_err(&dc->ndev->dev, "hdmi: can't get clock\n");
1511 err = -ENOENT;
1512 goto err_iounmap_reg;
1513 }
1514
1515 disp1_clk = clk_get_sys("tegradc.0", NULL);
1516 if (IS_ERR_OR_NULL(disp1_clk)) {
1517 dev_err(&dc->ndev->dev, "hdmi: can't disp1 clock\n");
1518 err = -ENOENT;
1519 goto err_put_clock;
1520 }
1521
1522 disp2_clk = clk_get_sys("tegradc.1", NULL);
1523 if (IS_ERR_OR_NULL(disp2_clk)) {
1524 dev_err(&dc->ndev->dev, "hdmi: can't disp2 clock\n");
1525 err = -ENOENT;
1526 goto err_put_clock;
1527 }
1528
1529#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1530 hdmi->hda_clk = clk_get_sys("tegra30-hda", "hda");
1531 if (IS_ERR_OR_NULL(hdmi->hda_clk)) {
1532 dev_err(&dc->ndev->dev, "hdmi: can't get hda clock\n");
1533 err = -ENOENT;
1534 goto err_put_clock;
1535 }
1536
1537 hdmi->hda2codec_clk = clk_get_sys("tegra30-hda", "hda2codec");
1538 if (IS_ERR_OR_NULL(hdmi->hda2codec_clk)) {
1539 dev_err(&dc->ndev->dev, "hdmi: can't get hda2codec clock\n");
1540 err = -ENOENT;
1541 goto err_put_clock;
1542 }
1543
1544 hdmi->hda2hdmi_clk = clk_get_sys("tegra30-hda", "hda2hdmi");
1545 if (IS_ERR_OR_NULL(hdmi->hda2hdmi_clk)) {
1546 dev_err(&dc->ndev->dev, "hdmi: can't get hda2hdmi clock\n");
1547 err = -ENOENT;
1548 goto err_put_clock;
1549 }
1550#endif
1551
1552 /* TODO: support non-hotplug */
1553 if (request_irq(gpio_to_irq(dc->out->hotplug_gpio), tegra_dc_hdmi_irq,
1554 IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1555 dev_name(&dc->ndev->dev), dc)) {
1556 dev_err(&dc->ndev->dev, "hdmi: request_irq %d failed\n",
1557 gpio_to_irq(dc->out->hotplug_gpio));
1558 err = -EBUSY;
1559 goto err_put_clock;
1560 }
1561
1562 hdmi->edid = tegra_edid_create(dc->out->dcc_bus);
1563 if (IS_ERR_OR_NULL(hdmi->edid)) {
1564 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
1565 err = PTR_ERR(hdmi->edid);
1566 goto err_free_irq;
1567 }
1568
1569#ifdef CONFIG_TEGRA_NVHDCP
1570 hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
1571 dc->out->dcc_bus);
1572 if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
1573 dev_err(&dc->ndev->dev, "hdmi: can't create nvhdcp\n");
1574 err = PTR_ERR(hdmi->nvhdcp);
1575 goto err_edid_destroy;
1576 }
1577#else
1578 hdmi->nvhdcp = NULL;
1579#endif
1580
1581 INIT_DELAYED_WORK(&hdmi->work, tegra_dc_hdmi_detect_worker);
1582
1583 hdmi->dc = dc;
1584 hdmi->base = base;
1585 hdmi->base_res = base_res;
1586 hdmi->clk = clk;
1587 hdmi->disp1_clk = disp1_clk;
1588 hdmi->disp2_clk = disp2_clk;
1589 hdmi->suspended = false;
1590 hdmi->eld_retrieved= false;
1591 hdmi->clk_enabled = false;
1592 hdmi->audio_freq = 44100;
1593 hdmi->audio_source = AUTO;
1594 spin_lock_init(&hdmi->suspend_lock);
1595
1596#ifdef CONFIG_SWITCH
1597 hdmi->hpd_switch.name = "hdmi";
1598 ret = switch_dev_register(&hdmi->hpd_switch);
1599
1600 if (!ret)
1601 ret = device_create_file(hdmi->hpd_switch.dev,
1602 &dev_attr_underscan);
1603 BUG_ON(ret != 0);
1604#endif
1605
1606 dc->out->depth = 24;
1607
1608 tegra_dc_set_outdata(dc, hdmi);
1609
1610 dc_hdmi = hdmi;
1611 /* boards can select default content protection policy */
1612 if (dc->out->flags & TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND)
1613 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1614 TEGRA_NVHDCP_POLICY_ON_DEMAND);
1615 else
1616 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1617 TEGRA_NVHDCP_POLICY_ALWAYS_ON);
1618
1619 tegra_dc_hdmi_debug_create(hdmi);
1620
1621 return 0;
1622
1623err_edid_destroy:
1624 tegra_edid_destroy(hdmi->edid);
1625err_free_irq:
1626 free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
1627err_put_clock:
1628#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1629 if (!IS_ERR_OR_NULL(hdmi->hda2hdmi_clk))
1630 clk_put(hdmi->hda2hdmi_clk);
1631 if (!IS_ERR_OR_NULL(hdmi->hda2codec_clk))
1632 clk_put(hdmi->hda2codec_clk);
1633 if (!IS_ERR_OR_NULL(hdmi->hda_clk))
1634 clk_put(hdmi->hda_clk);
1635#endif
1636 if (!IS_ERR_OR_NULL(disp2_clk))
1637 clk_put(disp2_clk);
1638 if (!IS_ERR_OR_NULL(disp1_clk))
1639 clk_put(disp1_clk);
1640 if (!IS_ERR_OR_NULL(clk))
1641 clk_put(clk);
1642err_iounmap_reg:
1643 iounmap(base);
1644err_release_resource_reg:
1645 release_resource(base_res);
1646err_free_hdmi:
1647 kfree(hdmi);
1648 return err;
1649}
1650
1651static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
1652{
1653 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1654
1655 free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
1656 cancel_delayed_work_sync(&hdmi->work);
1657#ifdef CONFIG_SWITCH
1658 switch_dev_unregister(&hdmi->hpd_switch);
1659#endif
1660 iounmap(hdmi->base);
1661 release_resource(hdmi->base_res);
1662#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1663 clk_put(hdmi->hda2hdmi_clk);
1664 clk_put(hdmi->hda2codec_clk);
1665 clk_put(hdmi->hda_clk);
1666#endif
1667 clk_put(hdmi->clk);
1668 clk_put(hdmi->disp1_clk);
1669 clk_put(hdmi->disp2_clk);
1670 tegra_edid_destroy(hdmi->edid);
1671 tegra_nvhdcp_destroy(hdmi->nvhdcp);
1672
1673 kfree(hdmi);
1674
1675}
1676
1677static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
1678{
1679 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1680 int i;
1681 unsigned freqs[] = {
1682 32000,
1683 44100,
1684 48000,
1685 88200,
1686 96000,
1687 176400,
1688 192000,
1689 };
1690
1691 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
1692 unsigned f = freqs[i];
1693 unsigned eight_half;
1694 unsigned delta;;
1695
1696 if (f > 96000)
1697 delta = 2;
1698 else if (f > 48000)
1699 delta = 6;
1700 else
1701 delta = 9;
1702
1703 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
1704 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
1705 AUDIO_FS_HIGH(eight_half + delta),
1706 HDMI_NV_PDISP_AUDIO_FS(i));
1707 }
1708}
1709
1710#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1711static void tegra_dc_hdmi_setup_eld_buff(struct tegra_dc *dc)
1712{
1713 int i;
1714 int j;
1715 u8 tmp;
1716
1717 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1718
1719 /* program ELD stuff */
1720 for (i = 0; i < HDMI_ELD_MONITOR_NAME_INDEX; i++) {
1721 switch (i) {
1722 case HDMI_ELD_VER_INDEX:
1723 tmp = (hdmi->eld.eld_ver << 3);
1724 tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1725 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1726 break;
1727 case HDMI_ELD_BASELINE_LEN_INDEX:
1728 break;
1729 case HDMI_ELD_CEA_VER_MNL_INDEX:
1730 tmp = (hdmi->eld.cea_edid_ver << 5);
1731 tmp |= (hdmi->eld.mnl & 0x1f);
1732 tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1733 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1734 break;
1735 case HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX:
1736 tmp = (hdmi->eld.sad_count << 4);
1737 tmp |= (hdmi->eld.conn_type & 0xC);
1738 tmp |= (hdmi->eld.support_ai & 0x2);
1739 tmp |= (hdmi->eld.support_hdcp & 0x1);
1740 tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1741 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1742 break;
1743 case HDMI_ELD_AUD_SYNC_DELAY_INDEX:
1744 tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.aud_synch_delay),
1745 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1746 break;
1747 case HDMI_ELD_SPK_ALLOC_INDEX:
1748 tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.spk_alloc),
1749 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1750 break;
1751 case HDMI_ELD_PORT_ID_INDEX:
1752 for (j = 0; j < 8;j++) {
1753 tegra_hdmi_writel(hdmi, ((i +j) << 8) | (hdmi->eld.port_id[j]),
1754 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1755 }
1756 break;
1757 case HDMI_ELD_MANF_NAME_INDEX:
1758 for (j = 0; j < 2;j++) {
1759 tegra_hdmi_writel(hdmi, ((i +j) << 8) | (hdmi->eld.manufacture_id[j]),
1760 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1761 }
1762 break;
1763 case HDMI_ELD_PRODUCT_CODE_INDEX:
1764 for (j = 0; j < 2;j++) {
1765 tegra_hdmi_writel(hdmi, ((i +j) << 8) | (hdmi->eld.product_id[j]),
1766 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1767 }
1768 break;
1769 }
1770 }
1771 for (j = 0; j < hdmi->eld.mnl;j++) {
1772 tegra_hdmi_writel(hdmi, ((j + HDMI_ELD_MONITOR_NAME_INDEX) << 8) |
1773 (hdmi->eld.monitor_name[j]),
1774 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1775 }
1776 for (j = 0; j < hdmi->eld.sad_count;j++) {
1777 tegra_hdmi_writel(hdmi, ((j + HDMI_ELD_MONITOR_NAME_INDEX + hdmi->eld.mnl) << 8) |
1778 (hdmi->eld.sad[j]),
1779 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1780 }
1781 /* set presence andvalid bit */
1782 tegra_hdmi_writel(hdmi, 3, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
1783}
1784#endif
1785
1786static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc, unsigned audio_freq,
1787 unsigned audio_source)
1788{
1789 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1790 const struct tegra_hdmi_audio_config *config;
1791 unsigned long audio_n;
1792#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1793 unsigned long reg_addr = 0;
1794#endif
1795 unsigned a_source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
1796
1797 if (HDA == audio_source)
1798 a_source = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
1799 else if (SPDIF == audio_source)
1800 a_source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
1801
1802#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1803 tegra_hdmi_writel(hdmi,a_source | AUDIO_CNTRL0_INJECT_NULLSMPL,
1804 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1805 tegra_hdmi_writel(hdmi,
1806 AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1807 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0),
1808 HDMI_NV_PDISP_AUDIO_CNTRL0);
1809#else
1810 tegra_hdmi_writel(hdmi,
1811 AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1812 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
1813 a_source,
1814 HDMI_NV_PDISP_AUDIO_CNTRL0);
1815#endif
1816 config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk);
1817 if (!config) {
1818 dev_err(&dc->ndev->dev,
1819 "hdmi: can't set audio to %d at %d pix_clock",
1820 audio_freq, dc->mode.pclk);
1821 return -EINVAL;
1822 }
1823
1824 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
1825
1826 audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
1827 AUDIO_N_VALUE(config->n - 1);
1828 tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1829
1830 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
1831 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1832
1833 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
1834 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1835
1836 tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
1837 SPARE_CTS_RESET_VAL(1),
1838 HDMI_NV_PDISP_HDMI_SPARE);
1839
1840 audio_n &= ~AUDIO_N_RESETF;
1841 tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1842
1843#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1844 switch (audio_freq) {
1845 case AUDIO_FREQ_32K:
1846 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_0;
1847 break;
1848 case AUDIO_FREQ_44_1K:
1849 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_0;
1850 break;
1851 case AUDIO_FREQ_48K:
1852 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_0;
1853 break;
1854 case AUDIO_FREQ_88_2K:
1855 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_0;
1856 break;
1857 case AUDIO_FREQ_96K:
1858 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_0;
1859 break;
1860 case AUDIO_FREQ_176_4K:
1861 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_0;
1862 break;
1863 case AUDIO_FREQ_192K:
1864 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_0;
1865 break;
1866 }
1867
1868 tegra_hdmi_writel(hdmi, config->aval, reg_addr);
1869#endif
1870 tegra_dc_hdmi_setup_audio_fs_tables(dc);
1871
1872 return 0;
1873}
1874
1875int tegra_hdmi_setup_audio_freq_source(unsigned audio_freq, unsigned audio_source)
1876{
1877 struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1878
1879 if (!hdmi)
1880 return -EAGAIN;
1881
1882 /* check for know freq */
1883 if (AUDIO_FREQ_32K == audio_freq ||
1884 AUDIO_FREQ_44_1K== audio_freq ||
1885 AUDIO_FREQ_48K== audio_freq ||
1886 AUDIO_FREQ_88_2K== audio_freq ||
1887 AUDIO_FREQ_96K== audio_freq ||
1888 AUDIO_FREQ_176_4K== audio_freq ||
1889 AUDIO_FREQ_192K== audio_freq) {
1890 /* If we can program HDMI, then proceed */
1891 if (hdmi->clk_enabled)
1892 tegra_dc_hdmi_setup_audio(hdmi->dc, audio_freq,audio_source);
1893
1894 /* Store it for using it in enable */
1895 hdmi->audio_freq = audio_freq;
1896 hdmi->audio_source = audio_source;
1897 }
1898 else
1899 return -EINVAL;
1900
1901 return 0;
1902}
1903EXPORT_SYMBOL(tegra_hdmi_setup_audio_freq_source);
1904
1905#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1906int tegra_hdmi_setup_hda_presence()
1907{
1908 struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1909
1910 if (!hdmi)
1911 return -EAGAIN;
1912
1913 if (hdmi->clk_enabled && hdmi->eld_retrieved) {
1914 /* If HDA_PRESENCE is already set reset it */
1915 if (tegra_hdmi_readl(hdmi,
1916 HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0))
1917 tegra_hdmi_writel(hdmi, 0,
1918 HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
1919
1920 tegra_dc_hdmi_setup_eld_buff(hdmi->dc);
1921 }
1922 else
1923 return -ENODEV;
1924
1925 return 0;
1926}
1927EXPORT_SYMBOL(tegra_hdmi_setup_hda_presence);
1928#endif
1929
1930static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
1931 u8 type, u8 version, void *data, int len)
1932{
1933 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1934 u32 subpack[2]; /* extra byte for zero padding of subpack */
1935 int i;
1936 u8 csum;
1937
1938 /* first byte of data is the checksum */
1939 csum = type + version + len - 1;
1940 for (i = 1; i < len; i++)
1941 csum +=((u8 *)data)[i];
1942 ((u8 *)data)[0] = 0x100 - csum;
1943
1944 tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
1945 INFOFRAME_HEADER_VERSION(version) |
1946 INFOFRAME_HEADER_LEN(len - 1),
1947 header_reg);
1948
1949 /* The audio inforame only has one set of subpack registers. The hdmi
1950 * block pads the rest of the data as per the spec so we have to fixup
1951 * the length before filling in the subpacks.
1952 */
1953 if (header_reg == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
1954 len = 6;
1955
1956 /* each subpack 7 bytes devided into:
1957 * subpack_low - bytes 0 - 3
1958 * subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
1959 */
1960 for (i = 0; i < len; i++) {
1961 int subpack_idx = i % 7;
1962
1963 if (subpack_idx == 0)
1964 memset(subpack, 0x0, sizeof(subpack));
1965
1966 ((u8 *)subpack)[subpack_idx] = ((u8 *)data)[i];
1967
1968 if (subpack_idx == 6 || (i + 1 == len)) {
1969 int reg = header_reg + 1 + (i / 7) * 2;
1970
1971 tegra_hdmi_writel(hdmi, subpack[0], reg);
1972 tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
1973 }
1974 }
1975}
1976
1977static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
1978{
1979 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1980 struct hdmi_avi_infoframe avi;
1981
1982 if (dvi) {
1983 tegra_hdmi_writel(hdmi, 0x0,
1984 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1985 return;
1986 }
1987
1988 memset(&avi, 0x0, sizeof(avi));
1989
1990 avi.r = HDMI_AVI_R_SAME;
1991
1992 if (dc->mode.v_active == 480) {
1993 if (dc->mode.h_active == 640) {
1994 avi.m = HDMI_AVI_M_4_3;
1995 avi.vic = 1;
1996 } else {
1997 avi.m = HDMI_AVI_M_16_9;
1998 avi.vic = 3;
1999 }
2000 } else if (dc->mode.v_active == 576) {
2001 /* CEC modes 17 and 18 differ only by the pysical size of the
2002 * screen so we have to calculation the physical aspect
2003 * ratio. 4 * 10 / 3 is 13
2004 */
2005 if ((dc->out->h_size * 10) / dc->out->v_size > 14) {
2006 avi.m = HDMI_AVI_M_16_9;
2007 avi.vic = 18;
2008 } else {
2009 avi.m = HDMI_AVI_M_4_3;
2010 avi.vic = 17;
2011 }
2012 } else if (dc->mode.v_active == 720 ||
2013 (dc->mode.v_active == 1470 && dc->mode.stereo_mode)) {
2014 /* VIC for both 720p and 720p 3D mode */
2015 avi.m = HDMI_AVI_M_16_9;
2016 if (dc->mode.h_front_porch == 110)
2017 avi.vic = 4; /* 60 Hz */
2018 else
2019 avi.vic = 19; /* 50 Hz */
2020 } else if (dc->mode.v_active == 1080 ||
2021 (dc->mode.v_active == 2205 && dc->mode.stereo_mode)) {
2022 /* VIC for both 1080p and 1080p 3D mode */
2023 avi.m = HDMI_AVI_M_16_9;
2024 if (dc->mode.h_front_porch == 88)
2025 avi.vic = 16; /* 60 Hz */
2026 else if (dc->mode.h_front_porch == 528)
2027 avi.vic = 31; /* 50 Hz */
2028 else
2029 avi.vic = 32; /* 24 Hz */
2030 } else {
2031 avi.m = HDMI_AVI_M_16_9;
2032 avi.vic = 0;
2033 }
2034
2035
2036 tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
2037 HDMI_INFOFRAME_TYPE_AVI,
2038 HDMI_AVI_VERSION,
2039 &avi, sizeof(avi));
2040
2041 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
2042 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
2043}
2044
2045static void tegra_dc_hdmi_setup_stereo_infoframe(struct tegra_dc *dc)
2046{
2047 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2048 struct hdmi_stereo_infoframe stereo;
2049 u32 val;
2050
2051 if (!dc->mode.stereo_mode) {
2052 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2053 val &= ~GENERIC_CTRL_ENABLE;
2054 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2055 return;
2056 }
2057
2058 memset(&stereo, 0x0, sizeof(stereo));
2059
2060 stereo.regid0 = 0x03;
2061 stereo.regid1 = 0x0c;
2062 stereo.regid2 = 0x00;
2063 stereo.hdmi_video_format = 2; /* 3D_Structure present */
2064#ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
2065 stereo._3d_structure = 0; /* frame packing */
2066#else
2067 stereo._3d_structure = 8; /* side-by-side (half) */
2068 stereo._3d_ext_data = 0; /* something which fits into 00XX bit req */
2069#endif
2070
2071 tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
2072 HDMI_INFOFRAME_TYPE_VENDOR,
2073 HDMI_VENDOR_VERSION,
2074 &stereo, 6);
2075
2076 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2077 val |= GENERIC_CTRL_ENABLE;
2078
2079 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2080}
2081
2082static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
2083{
2084 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2085 struct hdmi_audio_infoframe audio;
2086
2087 if (dvi) {
2088 tegra_hdmi_writel(hdmi, 0x0,
2089 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
2090 return;
2091 }
2092
2093 memset(&audio, 0x0, sizeof(audio));
2094
2095 audio.cc = HDMI_AUDIO_CC_2;
2096 tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
2097 HDMI_INFOFRAME_TYPE_AUDIO,
2098 HDMI_AUDIO_VERSION,
2099 &audio, sizeof(audio));
2100
2101 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
2102 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
2103}
2104
2105static void tegra_dc_hdmi_setup_tdms(struct tegra_dc_hdmi_data *hdmi,
2106 const struct tdms_config *tc)
2107{
2108 tegra_hdmi_writel(hdmi, tc->pll0, HDMI_NV_PDISP_SOR_PLL0);
2109 tegra_hdmi_writel(hdmi, tc->pll1, HDMI_NV_PDISP_SOR_PLL1);
2110
2111 tegra_hdmi_writel(hdmi, tc->pe_current, HDMI_NV_PDISP_PE_CURRENT);
2112
2113 tegra_hdmi_writel(hdmi,
2114 tc->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE,
2115 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
2116}
2117
2118static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
2119{
2120 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2121 int pulse_start;
2122 int dispclk_div_8_2;
2123 int retries;
2124 int rekey;
2125 int err;
2126 unsigned long val;
2127 unsigned i;
2128 unsigned long oldrate;
2129
2130 /* enbale power, clocks, resets, etc. */
2131
2132 /* The upstream DC needs to be clocked for accesses to HDMI to not
2133 * hard lock the system. Because we don't know if HDMI is conencted
2134 * to disp1 or disp2 we need to enable both until we set the DC mux.
2135 */
2136 clk_enable(hdmi->disp1_clk);
2137 clk_enable(hdmi->disp2_clk);
2138
2139#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2140 /* Enabling HDA clocks before asserting HDA PD and ELDV bits */
2141 clk_enable(hdmi->hda_clk);
2142 clk_enable(hdmi->hda2codec_clk);
2143 clk_enable(hdmi->hda2hdmi_clk);
2144#endif
2145
2146 /* back off multiplier before attaching to parent at new rate. */
2147 oldrate = clk_get_rate(hdmi->clk);
2148 clk_set_rate(hdmi->clk, oldrate / 2);
2149
2150 tegra_dc_setup_clk(dc, hdmi->clk);
2151 clk_set_rate(hdmi->clk, dc->mode.pclk);
2152
2153 clk_enable(hdmi->clk);
2154 tegra_periph_reset_assert(hdmi->clk);
2155 mdelay(1);
2156 tegra_periph_reset_deassert(hdmi->clk);
2157
2158 /* TODO: copy HDCP keys from KFUSE to HDMI */
2159
2160 /* Program display timing registers: handled by dc */
2161
2162 /* program HDMI registers and SOR sequencer */
2163
2164 tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
2165 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
2166 DC_DISP_DISP_COLOR_CONTROL);
2167
2168 /* video_preamble uses h_pulse2 */
2169 pulse_start = dc->mode.h_ref_to_sync + dc->mode.h_sync_width +
2170 dc->mode.h_back_porch - 10;
2171 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
2172 tegra_dc_writel(dc,
2173 PULSE_MODE_NORMAL |
2174 PULSE_POLARITY_HIGH |
2175 PULSE_QUAL_VACTIVE |
2176 PULSE_LAST_END_A,
2177 DC_DISP_H_PULSE2_CONTROL);
2178 tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
2179 DC_DISP_H_PULSE2_POSITION_A);
2180
2181 tegra_hdmi_writel(hdmi,
2182 VSYNC_WINDOW_END(0x210) |
2183 VSYNC_WINDOW_START(0x200) |
2184 VSYNC_WINDOW_ENABLE,
2185 HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
2186
2187 tegra_hdmi_writel(hdmi,
2188 (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
2189 ARM_VIDEO_RANGE_LIMITED,
2190 HDMI_NV_PDISP_INPUT_CONTROL);
2191
2192 clk_disable(hdmi->disp1_clk);
2193 clk_disable(hdmi->disp2_clk);
2194
2195 dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
2196 tegra_hdmi_writel(hdmi,
2197 SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
2198 SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
2199 HDMI_NV_PDISP_SOR_REFCLK);
2200
2201 hdmi->clk_enabled = true;
2202
2203 if (!hdmi->dvi) {
2204 err = tegra_dc_hdmi_setup_audio(dc, hdmi->audio_freq,
2205 hdmi->audio_source);
2206
2207 if (err < 0)
2208 hdmi->dvi = true;
2209 }
2210
2211#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2212 if (hdmi->eld_retrieved)
2213 tegra_dc_hdmi_setup_eld_buff(dc);
2214#endif
2215
2216 rekey = HDMI_REKEY_DEFAULT;
2217 val = HDMI_CTRL_REKEY(rekey);
2218 val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width +
2219 dc->mode.h_back_porch +
2220 dc->mode.h_front_porch -
2221 rekey - 18) / 32);
2222 if (!hdmi->dvi)
2223 val |= HDMI_CTRL_ENABLE;
2224 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
2225
2226 if (hdmi->dvi)
2227 tegra_hdmi_writel(hdmi, 0x0,
2228 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2229 else
2230 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
2231 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2232
2233 tegra_dc_hdmi_setup_avi_infoframe(dc, hdmi->dvi);
2234 tegra_dc_hdmi_setup_audio_infoframe(dc, hdmi->dvi);
2235 tegra_dc_hdmi_setup_stereo_infoframe(dc);
2236
2237 /* TMDS CONFIG */
2238 for (i = 0; i < ARRAY_SIZE(tdms_config); i++) {
2239 if (dc->mode.pclk <= tdms_config[i].pclk) {
2240 tegra_dc_hdmi_setup_tdms(hdmi, &tdms_config[i]);
2241 break;
2242 }
2243 }
2244
2245 tegra_hdmi_writel(hdmi,
2246 SOR_SEQ_CTL_PU_PC(0) |
2247 SOR_SEQ_PU_PC_ALT(0) |
2248 SOR_SEQ_PD_PC(8) |
2249 SOR_SEQ_PD_PC_ALT(8),
2250 HDMI_NV_PDISP_SOR_SEQ_CTL);
2251
2252 val = SOR_SEQ_INST_WAIT_TIME(1) |
2253 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
2254 SOR_SEQ_INST_HALT |
2255 SOR_SEQ_INST_PIN_A_LOW |
2256 SOR_SEQ_INST_PIN_B_LOW |
2257 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
2258
2259 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
2260 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
2261
2262 val = 0x1c800;
2263 val &= ~SOR_CSTM_ROTCLK(~0);
2264 val |= SOR_CSTM_ROTCLK(2);
2265 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
2266
2267
2268 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2269 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
2270 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2271
2272
2273 /* start SOR */
2274 tegra_hdmi_writel(hdmi,
2275 SOR_PWR_NORMAL_STATE_PU |
2276 SOR_PWR_NORMAL_START_NORMAL |
2277 SOR_PWR_SAFE_STATE_PD |
2278 SOR_PWR_SETTING_NEW_TRIGGER,
2279 HDMI_NV_PDISP_SOR_PWR);
2280 tegra_hdmi_writel(hdmi,
2281 SOR_PWR_NORMAL_STATE_PU |
2282 SOR_PWR_NORMAL_START_NORMAL |
2283 SOR_PWR_SAFE_STATE_PD |
2284 SOR_PWR_SETTING_NEW_DONE,
2285 HDMI_NV_PDISP_SOR_PWR);
2286
2287 retries = 1000;
2288 do {
2289 BUG_ON(--retries < 0);
2290 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
2291 } while (val & SOR_PWR_SETTING_NEW_PENDING);
2292
2293 val = SOR_STATE_ASY_CRCMODE_COMPLETE |
2294 SOR_STATE_ASY_OWNER_HEAD0 |
2295 SOR_STATE_ASY_SUBOWNER_BOTH |
2296 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
2297 SOR_STATE_ASY_DEPOL_POS;
2298
2299 if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
2300 val |= SOR_STATE_ASY_HSYNCPOL_NEG;
2301 else
2302 val |= SOR_STATE_ASY_HSYNCPOL_POS;
2303
2304 if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
2305 val |= SOR_STATE_ASY_VSYNCPOL_NEG;
2306 else
2307 val |= SOR_STATE_ASY_VSYNCPOL_POS;
2308
2309 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE2);
2310
2311 val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
2312 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
2313
2314 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
2315 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
2316 tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
2317 HDMI_NV_PDISP_SOR_STATE1);
2318 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
2319
2320 tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
2321
2322 tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2323 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
2324 DC_CMD_DISPLAY_POWER_CONTROL);
2325
2326 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
2327 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
2328 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2329
2330 tegra_nvhdcp_set_plug(hdmi->nvhdcp, 1);
2331}
2332
2333static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2334{
2335 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2336
2337 tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
2338
2339#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2340 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
2341 /* sleep 1ms before disabling clocks to ensure HDA gets the interrupt */
2342 msleep(1);
2343 clk_disable(hdmi->hda2hdmi_clk);
2344 clk_disable(hdmi->hda2codec_clk);
2345 clk_disable(hdmi->hda_clk);
2346#endif
2347 tegra_periph_reset_assert(hdmi->clk);
2348 hdmi->clk_enabled = false;
2349 clk_disable(hdmi->clk);
2350 tegra_dvfs_set_rate(hdmi->clk, 0);
2351}
2352
2353struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
2354 .init = tegra_dc_hdmi_init,
2355 .destroy = tegra_dc_hdmi_destroy,
2356 .enable = tegra_dc_hdmi_enable,
2357 .disable = tegra_dc_hdmi_disable,
2358 .detect = tegra_dc_hdmi_detect,
2359 .suspend = tegra_dc_hdmi_suspend,
2360 .resume = tegra_dc_hdmi_resume,
2361};
2362
2363struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc)
2364{
2365 struct tegra_dc_hdmi_data *hdmi;
2366
2367 /* TODO: Support EDID on non-HDMI devices */
2368 if (dc->out->type != TEGRA_DC_OUT_HDMI)
2369 return ERR_PTR(-ENODEV);
2370
2371 hdmi = tegra_dc_get_outdata(dc);
2372
2373 return tegra_edid_get_data(hdmi->edid);
2374}
2375EXPORT_SYMBOL(tegra_dc_get_edid);
2376
2377void tegra_dc_put_edid(struct tegra_dc_edid *edid)
2378{
2379 tegra_edid_put_data(edid);
2380}
2381EXPORT_SYMBOL(tegra_dc_put_edid);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 02:55:06 -0400