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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/video/tegra/dc/dsi.c
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/video/tegra/dc/dsi.c')
-rw-r--r--drivers/video/tegra/dc/dsi.c3042
1 files changed, 3042 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
new file mode 100644
index 00000000000..c33d6e0a58b
--- /dev/null
+++ b/drivers/video/tegra/dc/dsi.c
@@ -0,0 +1,3042 @@
1/*
2 * drivers/video/tegra/dc/dsi.c
3 *
4 * Copyright (c) 2011, NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/fb.h>
21#include <linux/gpio.h>
22#include <linux/interrupt.h>
23#include <linux/kernel.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26#include <linux/workqueue.h>
27
28#include <mach/clk.h>
29#include <mach/dc.h>
30#include <mach/fb.h>
31#include <mach/csi.h>
32#include <linux/nvhost.h>
33
34#include "dc_reg.h"
35#include "dc_priv.h"
36#include "dsi_regs.h"
37#include "dsi.h"
38
39#define DSI_USE_SYNC_POINTS 1
40#define S_TO_MS(x) (1000 * (x))
41
42#define DSI_MODULE_NOT_INIT 0x0
43#define DSI_MODULE_INIT 0x1
44
45#define DSI_LPHS_NOT_INIT 0x0
46#define DSI_LPHS_IN_LP_MODE 0x1
47#define DSI_LPHS_IN_HS_MODE 0x2
48
49#define DSI_VIDEO_TYPE_NOT_INIT 0x0
50#define DSI_VIDEO_TYPE_VIDEO_MODE 0x1
51#define DSI_VIDEO_TYPE_CMD_MODE 0x2
52
53#define DSI_DRIVEN_MODE_NOT_INIT 0x0
54#define DSI_DRIVEN_MODE_DC 0x1
55#define DSI_DRIVEN_MODE_HOST 0x2
56
57#define DSI_PHYCLK_OUT_DIS 0x0
58#define DSI_PHYCLK_OUT_EN 0x1
59
60#define DSI_PHYCLK_NOT_INIT 0x0
61#define DSI_PHYCLK_CONTINUOUS 0x1
62#define DSI_PHYCLK_TX_ONLY 0x2
63
64#define DSI_CLK_BURST_NOT_INIT 0x0
65#define DSI_CLK_BURST_NONE_BURST 0x1
66#define DSI_CLK_BURST_BURST_MODE 0x2
67
68#define DSI_DC_STREAM_DISABLE 0x0
69#define DSI_DC_STREAM_ENABLE 0x1
70
71#define DSI_LP_OP_NOT_INIT 0x0
72#define DSI_LP_OP_WRITE 0x1
73#define DSI_LP_OP_READ 0x2
74
75static bool enable_read_debug;
76module_param(enable_read_debug, bool, 0644);
77MODULE_PARM_DESC(enable_read_debug,
78 "Enable to print read fifo and return packet type");
79
80struct dsi_status {
81 unsigned init:2;
82
83 unsigned lphs:2;
84
85 unsigned vtype:2;
86 unsigned driven:2;
87
88 unsigned clk_out:2;
89 unsigned clk_mode:2;
90 unsigned clk_burst:2;
91
92 unsigned lp_op:2;
93
94 unsigned dc_stream:1;
95};
96
97/* source of video data */
98enum {
99 TEGRA_DSI_DRIVEN_BY_DC,
100 TEGRA_DSI_DRIVEN_BY_HOST,
101};
102
103struct tegra_dc_dsi_data {
104 struct tegra_dc *dc;
105 void __iomem *base;
106 struct resource *base_res;
107
108 struct clk *dc_clk;
109 struct clk *dsi_clk;
110 bool clk_ref;
111
112 struct mutex lock;
113
114 /* data from board info */
115 struct tegra_dsi_out info;
116
117 struct dsi_status status;
118
119 struct dsi_phy_timing_inclk phy_timing;
120
121 u8 driven_mode;
122 u8 controller_index;
123
124 u8 pixel_scaler_mul;
125 u8 pixel_scaler_div;
126
127 u32 default_shift_clk_div;
128 u32 default_pixel_clk_khz;
129 u32 default_hs_clk_khz;
130
131 u32 shift_clk_div;
132 u32 target_hs_clk_khz;
133 u32 target_lp_clk_khz;
134
135 u32 syncpt_id;
136 u32 syncpt_val;
137
138 u16 current_bit_clk_ns;
139 u32 current_dsi_clk_khz;
140
141 u32 dsi_control_val;
142
143 bool ulpm;
144 bool enabled;
145};
146
147const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
148 DSI_PKT_SEQ_0_LO,
149 DSI_PKT_SEQ_0_HI,
150 DSI_PKT_SEQ_1_LO,
151 DSI_PKT_SEQ_1_HI,
152 DSI_PKT_SEQ_2_LO,
153 DSI_PKT_SEQ_2_HI,
154 DSI_PKT_SEQ_3_LO,
155 DSI_PKT_SEQ_3_HI,
156 DSI_PKT_SEQ_4_LO,
157 DSI_PKT_SEQ_4_HI,
158 DSI_PKT_SEQ_5_LO,
159 DSI_PKT_SEQ_5_HI,
160};
161
162const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
163 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
164 0,
165 PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
166 0,
167 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
168 0,
169 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
170 PKT_ID2(CMD_HE) | PKT_LEN2(0),
171 PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
172 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
173 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
174 0,
175 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
176 PKT_ID2(CMD_HE) | PKT_LEN2(0),
177 PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
178 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
179};
180
181const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
182 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
183 0,
184 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
185 0,
186 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
187 0,
188 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
189 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
190 PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
191 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
192 0,
193 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
194 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
195 PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
196};
197
198static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
199 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
200 0,
201 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
202 0,
203 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
204 0,
205 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
206 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
207 PKT_ID0(CMD_EOT) | PKT_LEN0(7),
208 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
209 0,
210 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
211 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
212 PKT_ID0(CMD_EOT) | PKT_LEN0(7),
213};
214
215static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
216 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
217 0,
218 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
219 0,
220 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
221 0,
222 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
223 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
224 PKT_ID0(CMD_EOT) | PKT_LEN0(0),
225 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
226 0,
227 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
228 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
229 PKT_ID0(CMD_EOT) | PKT_LEN0(0),
230};
231
232/* TODO: verify with hw about this format */
233const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
234 0,
235 0,
236 0,
237 0,
238 0,
239 0,
240 PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
241 0,
242 0,
243 0,
244 PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
245 0,
246};
247
248const u32 init_reg[] = {
249 DSI_INT_ENABLE,
250 DSI_INT_STATUS,
251 DSI_INT_MASK,
252 DSI_INIT_SEQ_DATA_0,
253 DSI_INIT_SEQ_DATA_1,
254 DSI_INIT_SEQ_DATA_2,
255 DSI_INIT_SEQ_DATA_3,
256 DSI_INIT_SEQ_DATA_4,
257 DSI_INIT_SEQ_DATA_5,
258 DSI_INIT_SEQ_DATA_6,
259 DSI_INIT_SEQ_DATA_7,
260 DSI_DCS_CMDS,
261 DSI_PKT_SEQ_0_LO,
262 DSI_PKT_SEQ_1_LO,
263 DSI_PKT_SEQ_2_LO,
264 DSI_PKT_SEQ_3_LO,
265 DSI_PKT_SEQ_4_LO,
266 DSI_PKT_SEQ_5_LO,
267 DSI_PKT_SEQ_0_HI,
268 DSI_PKT_SEQ_1_HI,
269 DSI_PKT_SEQ_2_HI,
270 DSI_PKT_SEQ_3_HI,
271 DSI_PKT_SEQ_4_HI,
272 DSI_PKT_SEQ_5_HI,
273 DSI_CONTROL,
274 DSI_HOST_DSI_CONTROL,
275 DSI_PAD_CONTROL,
276 DSI_PAD_CONTROL_CD,
277 DSI_SOL_DELAY,
278 DSI_MAX_THRESHOLD,
279 DSI_TRIGGER,
280 DSI_TX_CRC,
281 DSI_INIT_SEQ_CONTROL,
282 DSI_PKT_LEN_0_1,
283 DSI_PKT_LEN_2_3,
284 DSI_PKT_LEN_4_5,
285 DSI_PKT_LEN_6_7,
286};
287
288inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
289{
290 BUG_ON(!nvhost_module_powered(nvhost_get_host(dsi->dc->ndev)->dev));
291 return readl(dsi->base + reg * 4);
292}
293EXPORT_SYMBOL(tegra_dsi_readl);
294
295inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
296{
297 BUG_ON(!nvhost_module_powered(nvhost_get_host(dsi->dc->ndev)->dev));
298 writel(val, dsi->base + reg * 4);
299}
300EXPORT_SYMBOL(tegra_dsi_writel);
301
302static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
303{
304 u32 val;
305 int ret;
306
307 ret = 0;
308
309 dsi->syncpt_val = nvhost_syncpt_read(
310 &nvhost_get_host(dsi->dc->ndev)->syncpt,
311 dsi->syncpt_id);
312
313 val = DSI_INCR_SYNCPT_COND(OP_DONE) |
314 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
315 tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
316
317 /* TODO: Use interrupt rather than polling */
318 ret = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
319 dsi->syncpt_id, dsi->syncpt_val + 1);
320 if (ret < 0) {
321 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
322 goto fail;
323 }
324
325 (dsi->syncpt_val)++;
326 return 0;
327fail:
328 return ret;
329}
330
331static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
332{
333 u32 dsi_clock_rate_khz;
334
335 switch (dsi->info.video_burst_mode) {
336 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
337 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
338 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
339 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
340 /* Calculate DSI HS clock rate for DSI burst mode */
341 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
342 dsi->shift_clk_div;
343 break;
344 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
345 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
346 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
347 default:
348 /* Clock rate is default DSI clock rate for non-burst mode */
349 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
350 break;
351 }
352
353 return dsi_clock_rate_khz;
354}
355
356static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
357{
358 u32 dsi_clock_rate_khz;
359
360 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
361 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
362 dsi_clock_rate_khz =
363 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
364 else
365 dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
366 else
367 if (lp_op == DSI_LP_OP_READ)
368 dsi_clock_rate_khz =
369 dsi->info.lp_read_cmd_mode_freq_khz;
370 else
371 dsi_clock_rate_khz =
372 dsi->info.lp_cmd_mode_freq_khz;
373
374 return dsi_clock_rate_khz;
375}
376
377static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
378{
379 u32 shift_clk_div;
380 u32 max_shift_clk_div;
381 u32 burst_width;
382 u32 burst_width_max;
383
384 /* Get the real value of default shift_clk_div. default_shift_clk_div
385 * holds the real value of shift_clk_div.
386 */
387 shift_clk_div = dsi->default_shift_clk_div;
388
389 /* Calculate shift_clk_div which can matche the video_burst_mode. */
390 if (dsi->info.video_burst_mode >=
391 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
392 /* The max_shift_clk_div is multiplied by 10 to save the
393 * fraction
394 */
395 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
396 max_shift_clk_div = dsi->info.max_panel_freq_khz
397 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
398 else
399 max_shift_clk_div = shift_clk_div * 10;
400
401 burst_width = dsi->info.video_burst_mode
402 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
403 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
404 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
405
406 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
407 burst_width / (burst_width_max * 10) + shift_clk_div;
408 }
409
410 return shift_clk_div;
411}
412
413static void tegra_dsi_init_sw(struct tegra_dc *dc,
414 struct tegra_dc_dsi_data *dsi)
415{
416 u32 h_width_pixels;
417 u32 v_width_lines;
418 u32 pixel_clk_hz;
419 u32 byte_clk_hz;
420 u32 plld_clk_mhz;
421
422 switch (dsi->info.pixel_format) {
423 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
424 /* 2 bytes per pixel */
425 dsi->pixel_scaler_mul = 2;
426 dsi->pixel_scaler_div = 1;
427 break;
428 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
429 /* 2.25 bytes per pixel */
430 dsi->pixel_scaler_mul = 9;
431 dsi->pixel_scaler_div = 4;
432 break;
433 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
434 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
435 /* 3 bytes per pixel */
436 dsi->pixel_scaler_mul = 3;
437 dsi->pixel_scaler_div = 1;
438 break;
439 default:
440 break;
441 }
442
443 dsi->controller_index = dc->ndev->id;
444 dsi->ulpm = false;
445 dsi->enabled = false;
446 dsi->clk_ref = false;
447
448 dsi->dsi_control_val =
449 DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
450 DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
451 DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
452 DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
453
454 /* Below we are going to calculate dsi and dc clock rate.
455 * Calcuate the horizontal and vertical width.
456 */
457 h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
458 dc->mode.h_sync_width + dc->mode.h_active;
459 v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
460 dc->mode.v_sync_width + dc->mode.v_active;
461
462 /* Calculate minimum required pixel rate. */
463 pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
464 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
465 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
466 dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
467 "should be larger than rated refresh rate.\n");
468 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
469 dsi->info.rated_refresh_rate;
470 }
471
472 /* Calculate minimum byte rate on DSI interface. */
473 byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
474 (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
475
476 /* Round up to multiple of mega hz. */
477 plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
478 1000000);
479
480 /* Calculate default real shift_clk_div. */
481 dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
482 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
483 dsi->info.n_data_lanes);
484 /* Calculate default DSI hs clock. DSI interface is double data rate.
485 * Data is transferred on both rising and falling edge of clk, div by 2
486 * to get the actual clock rate.
487 */
488 dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
489 dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
490 / dsi->default_shift_clk_div;
491
492 /* Get the actual shift_clk_div and clock rates. */
493 dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
494 dsi->target_lp_clk_khz =
495 tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
496 dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
497
498 dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
499 dsi->target_hs_clk_khz);
500
501 dsi->controller_index = dc->ndev->id;
502
503#if DSI_USE_SYNC_POINTS
504 dsi->syncpt_id = NVSYNCPT_DSI;
505#endif
506
507 /*
508 * Force video clock to be continuous mode if
509 * enable_hs_clock_on_lp_cmd_mode is set
510 */
511 if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
512 if (dsi->info.video_clock_mode !=
513 TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
514 dev_warn(&dc->ndev->dev,
515 "Force clock continuous mode\n");
516
517 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
518 }
519
520}
521
522#define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
523(platform_t_phy_ns) ? ( \
524((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
525(DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
526((default_phy) < 0 ? 0 : (default_phy)))
527
528static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
529 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
530{
531 phy_timing_clk->t_tlpx = SELECT_T_PHY(
532 dsi->info.phy_timing.t_tlpx_ns,
533 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
534
535 phy_timing_clk->t_clktrail = SELECT_T_PHY(
536 dsi->info.phy_timing.t_clktrail_ns,
537 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
538
539 phy_timing_clk->t_clkpost = SELECT_T_PHY(
540 dsi->info.phy_timing.t_clkpost_ns,
541 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
542
543 phy_timing_clk->t_clkzero = SELECT_T_PHY(
544 dsi->info.phy_timing.t_clkzero_ns,
545 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
546
547 phy_timing_clk->t_clkprepare = SELECT_T_PHY(
548 dsi->info.phy_timing.t_clkprepare_ns,
549 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
550
551 phy_timing_clk->t_clkpre = SELECT_T_PHY(
552 dsi->info.phy_timing.t_clkpre_ns,
553 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
554}
555
556static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
557 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
558{
559 phy_timing_clk->t_tlpx = SELECT_T_PHY(
560 dsi->info.phy_timing.t_tlpx_ns,
561 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
562
563 phy_timing_clk->t_hsdexit = SELECT_T_PHY(
564 dsi->info.phy_timing.t_hsdexit_ns,
565 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
566
567 phy_timing_clk->t_hstrail = SELECT_T_PHY(
568 dsi->info.phy_timing.t_hstrail_ns,
569 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
570
571 phy_timing_clk->t_datzero = SELECT_T_PHY(
572 dsi->info.phy_timing.t_datzero_ns,
573 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
574
575 phy_timing_clk->t_hsprepare = SELECT_T_PHY(
576 dsi->info.phy_timing.t_hsprepare_ns,
577 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
578}
579
580static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
581 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
582{
583 phy_timing_clk->t_tlpx = SELECT_T_PHY(
584 dsi->info.phy_timing.t_tlpx_ns,
585 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
586}
587
588static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
589 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
590{
591 phy_timing_clk->t_tlpx = SELECT_T_PHY(
592 dsi->info.phy_timing.t_tlpx_ns,
593 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
594
595 phy_timing_clk->t_taget = SELECT_T_PHY(
596 dsi->info.phy_timing.t_taget_ns,
597 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
598
599 phy_timing_clk->t_tasure = SELECT_T_PHY(
600 dsi->info.phy_timing.t_tasure_ns,
601 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
602
603 phy_timing_clk->t_tago = SELECT_T_PHY(
604 dsi->info.phy_timing.t_tago_ns,
605 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
606}
607
608static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
609 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
610{
611 phy_timing_clk->t_tlpx = SELECT_T_PHY(
612 dsi->info.phy_timing.t_tlpx_ns,
613 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
614
615 phy_timing_clk->t_wakeup = SELECT_T_PHY(
616 dsi->info.phy_timing.t_wakeup_ns,
617 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
618}
619
620#undef SELECT_T_PHY
621
622static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
623 struct dsi_phy_timing_inclk *phy_timing_clk,
624 u32 clk_ns, u8 lphs)
625{
626 if (lphs == DSI_LPHS_IN_HS_MODE) {
627 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
628 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
629 } else {
630 /* default is LP mode */
631 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
632 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
633 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
634 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
635 tegra_dsi_get_clk_phy_timing
636 (dsi, phy_timing_clk, clk_ns);
637 }
638}
639
640static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
641 struct dsi_phy_timing_inclk *phy_timing,
642 u32 clk_ns, u8 lphs)
643{
644#define CHECK_RANGE(val, min, max) ( \
645 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
646 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
647
648 int err = 0;
649
650 err = CHECK_RANGE(
651 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
652 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
653 MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
654 if (err < 0) {
655 dev_warn(&dsi->dc->ndev->dev,
656 "dsi: Tlpx mipi range violated\n");
657 goto fail;
658 }
659
660 if (lphs == DSI_LPHS_IN_HS_MODE) {
661 err = CHECK_RANGE(
662 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
663 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
664 MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
665 if (err < 0) {
666 dev_warn(&dsi->dc->ndev->dev,
667 "dsi: HsExit mipi range violated\n");
668 goto fail;
669 }
670
671 err = CHECK_RANGE(
672 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
673 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
674 MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
675 if (err < 0) {
676 dev_warn(&dsi->dc->ndev->dev,
677 "dsi: HsTrail mipi range violated\n");
678 goto fail;
679 }
680
681 err = CHECK_RANGE(
682 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
683 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
684 MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
685 if (err < 0) {
686 dev_warn(&dsi->dc->ndev->dev,
687 "dsi: HsZero mipi range violated\n");
688 goto fail;
689 }
690
691 err = CHECK_RANGE(
692 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
693 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
694 MIPI_T_HSPREPARE_NS_MIN(clk_ns),
695 MIPI_T_HSPREPARE_NS_MAX(clk_ns));
696 if (err < 0) {
697 dev_warn(&dsi->dc->ndev->dev,
698 "dsi: HsPrepare mipi range violated\n");
699 goto fail;
700 }
701
702 err = CHECK_RANGE(
703 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
704 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
705 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
706 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
707 MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
708 MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
709 if (err < 0) {
710 dev_warn(&dsi->dc->ndev->dev,
711 "dsi: HsPrepare + HsZero mipi range violated\n");
712 goto fail;
713 }
714 } else {
715 /* default is LP mode */
716 err = CHECK_RANGE(
717 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
718 phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
719 MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
720 if (err < 0) {
721 dev_warn(&dsi->dc->ndev->dev,
722 "dsi: WakeUp mipi range violated\n");
723 goto fail;
724 }
725
726 err = CHECK_RANGE(
727 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
728 phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
729 MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
730 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
731 MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
732 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
733 if (err < 0) {
734 dev_warn(&dsi->dc->ndev->dev,
735 "dsi: TaSure mipi range violated\n");
736 goto fail;
737 }
738 }
739
740 if (lphs == DSI_LPHS_IN_HS_MODE ||
741 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
742 err = CHECK_RANGE(
743 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
744 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
745 MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
746 if (err < 0) {
747 dev_warn(&dsi->dc->ndev->dev,
748 "dsi: ClkTrail mipi range violated\n");
749 goto fail;
750 }
751
752 err = CHECK_RANGE(
753 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
754 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
755 MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
756 if (err < 0) {
757 dev_warn(&dsi->dc->ndev->dev,
758 "dsi: ClkPost mipi range violated\n");
759 goto fail;
760 }
761
762 err = CHECK_RANGE(
763 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
764 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
765 MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
766 if (err < 0) {
767 dev_warn(&dsi->dc->ndev->dev,
768 "dsi: ClkZero mipi range violated\n");
769 goto fail;
770 }
771
772 err = CHECK_RANGE(
773 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
774 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
775 MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
776 if (err < 0) {
777 dev_warn(&dsi->dc->ndev->dev,
778 "dsi: ClkPrepare mipi range violated\n");
779 goto fail;
780 }
781
782 err = CHECK_RANGE(
783 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
784 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
785 MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
786 if (err < 0) {
787 dev_warn(&dsi->dc->ndev->dev,
788 "dsi: ClkPre mipi range violated\n");
789 goto fail;
790 }
791
792 err = CHECK_RANGE(
793 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
794 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
795 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
796 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
797 MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
798 MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
799 if (err < 0) {
800 dev_warn(&dsi->dc->ndev->dev,
801 "dsi: ClkPrepare + ClkZero mipi range violated\n");
802 goto fail;
803 }
804 }
805fail:
806#undef CHECK_RANGE
807 return err;
808}
809
810static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
811 struct dsi_phy_timing_inclk *phy_timing,
812 u32 clk_ns, u8 lphs)
813{
814 u32 hs_t_phy_ns;
815 u32 clk_t_phy_ns;
816 u32 t_phy_ns;
817 u32 h_blank_ns;
818 struct tegra_dc_mode *modes;
819 u32 t_pix_ns;
820 int err = 0;
821
822 if (!(lphs == DSI_LPHS_IN_HS_MODE))
823 goto fail;
824
825 modes = dsi->dc->out->modes;
826 t_pix_ns = clk_ns * BITS_PER_BYTE *
827 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
828
829 hs_t_phy_ns =
830 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
831 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
832 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
833 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
834 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
835 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
836 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
837 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
838 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
839 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
840
841 clk_t_phy_ns =
842 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
843 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
844 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
845 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
846 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
847 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
848 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
849 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
850 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
851 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
852 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
853 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
854 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
855 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
856
857 h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
858 modes->h_front_porch);
859
860 /* Extra tlpx and byte cycle required by dsi HW */
861 t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
862 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
863 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
864 clk_ns * BITS_PER_BYTE);
865
866 if (h_blank_ns < t_phy_ns) {
867 err = -EINVAL;
868 dev_err(&dsi->dc->ndev->dev,
869 "dsi: Hblank is smaller than HS trans phy timing\n");
870 goto fail;
871 }
872
873 return 0;
874fail:
875 return err;
876}
877
878static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
879 struct dsi_phy_timing_inclk *phy_timing,
880 u32 clk_ns, u8 lphs)
881{
882 int err = 0;
883
884 err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
885 if (err < 0) {
886 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
887 goto fail;
888 }
889
890 err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
891 if (err < 0) {
892 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
893 goto fail;
894 }
895
896 /* TODO: add more contraints */
897fail:
898 return err;
899}
900
901static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
902{
903 u32 val;
904 struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
905
906 tegra_dsi_get_phy_timing
907 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
908
909 tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
910 dsi->current_bit_clk_ns, lphs);
911
912 val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
913 DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
914 DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
915 DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
916 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
917
918 val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
919 DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
920 DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
921 DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
922 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
923
924 val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
925 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
926 DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
927 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
928
929 val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
930 DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
931 DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
932 tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
933
934 dsi->phy_timing = phy_timing;
935}
936
937static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
938 struct tegra_dc_dsi_data *dsi)
939{
940 u32 dsi_to_pixel_clk_ratio;
941 u32 temp;
942 u32 temp1;
943 u32 mipi_clk_adj_kHz;
944 u32 sol_delay;
945 struct tegra_dc_mode *dc_modes = &dc->mode;
946
947 /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
948 dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
949 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
950
951 /* Convert Fdsi to byte format */
952 dsi_to_pixel_clk_ratio *= 1000/8;
953
954 /* Multiplying by 1000 so that we don't loose the fraction part */
955 temp = dc_modes->h_active * 1000;
956 temp1 = dc_modes->h_active + dc_modes->h_back_porch +
957 dc_modes->h_sync_width;
958
959 sol_delay = temp1 * dsi_to_pixel_clk_ratio -
960 temp * dsi->pixel_scaler_mul /
961 (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
962
963 /* Do rounding on sol delay */
964 sol_delay = (sol_delay + 1000 - 1)/1000;
965
966 /* TODO:
967 * 1. find out the correct sol fifo depth to use
968 * 2. verify with hw about the clamping function
969 */
970 if (sol_delay > (480 * 4)) {
971 sol_delay = (480 * 4);
972 mipi_clk_adj_kHz = sol_delay +
973 (dc_modes->h_active * dsi->pixel_scaler_mul) /
974 (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
975
976 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
977
978 mipi_clk_adj_kHz *= 4;
979 }
980
981 dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
982
983 return sol_delay;
984}
985
986static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
987 struct tegra_dc_dsi_data *dsi)
988{
989 u32 sol_delay;
990
991 if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
992 dsi->info.video_burst_mode ==
993 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
994#define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
995 sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
996 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
997#undef VIDEO_FIFO_LATENCY_PIXEL_CLK
998 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
999 } else {
1000 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1001 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1002 }
1003
1004 tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1005 DSI_SOL_DELAY);
1006}
1007
1008static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1009{
1010 u32 val;
1011 u32 bytes_per_frame;
1012 u32 timeout = 0;
1013
1014 /* TODO: verify the following equation */
1015 bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1016 (dsi->info.refresh_rate * 8);
1017 timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1018 timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1019
1020 val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1021 DSI_TIMEOUT_0_HTX_TO(timeout);
1022 tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1023
1024 if (dsi->info.panel_reset_timeout_msec)
1025 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1026 / dsi->current_bit_clk_ns;
1027 else
1028 timeout = DSI_PR_TO_VALUE;
1029
1030 val = DSI_TIMEOUT_1_PR_TO(timeout) |
1031 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1032 tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1033
1034 val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1035 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1036 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1037 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1038 tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1039}
1040
1041static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1042 struct tegra_dc_dsi_data *dsi)
1043{
1044 u32 val;
1045 u32 hact_pkt_len;
1046 u32 hsa_pkt_len;
1047 u32 hbp_pkt_len;
1048 u32 hfp_pkt_len;
1049
1050 hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1051 dsi->pixel_scaler_div;
1052 hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1053 dsi->pixel_scaler_div;
1054 hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1055 dsi->pixel_scaler_div;
1056 hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1057 dsi->pixel_scaler_div;
1058
1059 if (dsi->info.video_burst_mode !=
1060 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1061 hbp_pkt_len += hsa_pkt_len;
1062
1063 hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1064 hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1065 hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1066
1067 val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1068 DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1069 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1070
1071 val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1072 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1073 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1074
1075 val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1076 DSI_PKT_LEN_4_5_LENGTH_5(0);
1077 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1078
1079 val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
1080 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1081}
1082
1083static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1084 struct tegra_dc_dsi_data *dsi)
1085{
1086 unsigned long val;
1087 unsigned long act_bytes;
1088
1089 act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1090 dsi->pixel_scaler_div + 1;
1091
1092 val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1093 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1094
1095 val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1096 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1097
1098 val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1099 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1100
1101 val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1102 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1103}
1104
1105static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1106 struct tegra_dc_dsi_data *dsi)
1107{
1108 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1109 return;
1110
1111 if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
1112 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1113 else
1114 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1115}
1116
1117static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1118 struct tegra_dc_dsi_data *dsi)
1119{
1120 const u32 *pkt_seq;
1121 u32 rgb_info;
1122 u32 pkt_seq_3_5_rgb_lo;
1123 u32 pkt_seq_3_5_rgb_hi;
1124 u32 val;
1125 u32 reg;
1126 u8 i;
1127
1128 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1129 return;
1130
1131 switch (dsi->info.pixel_format) {
1132 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1133 rgb_info = CMD_RGB_16BPP;
1134 break;
1135 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1136 rgb_info = CMD_RGB_18BPP;
1137 break;
1138 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1139 rgb_info = CMD_RGB_18BPPNP;
1140 break;
1141 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1142 default:
1143 rgb_info = CMD_RGB_24BPP;
1144 break;
1145 }
1146
1147 pkt_seq_3_5_rgb_lo = 0;
1148 pkt_seq_3_5_rgb_hi = 0;
1149 if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1150 pkt_seq = dsi_pkt_seq_cmd_mode;
1151 else {
1152 switch (dsi->info.video_burst_mode) {
1153 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1154 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1155 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1156 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1157 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1158 pkt_seq_3_5_rgb_lo =
1159 DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1160 if (!dsi->info.no_pkt_seq_eot)
1161 pkt_seq = dsi_pkt_seq_video_burst;
1162 else
1163 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1164 break;
1165 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1166 pkt_seq_3_5_rgb_hi =
1167 DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1168 pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1169 break;
1170 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1171 default:
1172 pkt_seq_3_5_rgb_lo =
1173 DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1174 pkt_seq = dsi_pkt_seq_video_non_burst;
1175 break;
1176 }
1177 }
1178
1179 for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1180 val = pkt_seq[i];
1181 reg = dsi_pkt_seq_reg[i];
1182 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1183 val |= pkt_seq_3_5_rgb_lo;
1184 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1185 val |= pkt_seq_3_5_rgb_hi;
1186 tegra_dsi_writel(dsi, val, reg);
1187 }
1188}
1189
1190static void tegra_dsi_reset_underflow_overflow
1191 (struct tegra_dc_dsi_data *dsi)
1192{
1193 u32 val;
1194
1195 val = tegra_dsi_readl(dsi, DSI_STATUS);
1196 val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1197 if (val) {
1198 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1199 dev_warn(&dsi->dc->ndev->dev,
1200 "dsi: video fifo overflow. Resetting flag\n");
1201 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1202 dev_warn(&dsi->dc->ndev->dev,
1203 "dsi: video fifo underflow. Resetting flag\n");
1204 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1205 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1206 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1207 udelay(5);
1208 }
1209}
1210
1211static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1212 struct tegra_dc_dsi_data *dsi)
1213{
1214 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1215 tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1216 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1217 tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1218
1219 dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1220}
1221
1222static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1223 struct tegra_dc_dsi_data *dsi)
1224{
1225 int val;
1226 long timeout;
1227 u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1228
1229 /* stop dc */
1230 tegra_dsi_stop_dc_stream(dc, dsi);
1231
1232 /* enable frame end interrupt */
1233 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1234 val |= FRAME_END_INT;
1235 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1236
1237 /* wait for frame_end completion.
1238 * timeout is 2 frame duration to accomodate for
1239 * internal delay.
1240 */
1241 timeout = wait_for_completion_interruptible_timeout(
1242 &dc->frame_end_complete,
1243 msecs_to_jiffies(2 * frame_period));
1244
1245 /* disable frame end interrupt */
1246 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1247 val &= ~FRAME_END_INT;
1248 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1249
1250 if (timeout == 0)
1251 dev_warn(&dc->ndev->dev,
1252 "DC doesn't stop at end of frame.\n");
1253
1254 tegra_dsi_reset_underflow_overflow(dsi);
1255}
1256
1257static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1258 struct tegra_dc_dsi_data *dsi)
1259{
1260 u32 val;
1261
1262 tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1263
1264 /* TODO: clean up */
1265 tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1266 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1267 DC_CMD_DISPLAY_POWER_CONTROL);
1268
1269 /* Configure one-shot mode or continuous mode */
1270 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1271 /* disable LSPI/LCD_DE output */
1272 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1273 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1274
1275 /* enable MSF & set MSF polarity */
1276 val = MSF_ENABLE | MSF_LSPI;
1277 if (!dsi->info.te_polarity_low)
1278 val |= MSF_POLARITY_HIGH;
1279 else
1280 val |= MSF_POLARITY_LOW;
1281 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1282
1283 /* set non-continuous mode */
1284 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1285 DC_CMD_DISPLAY_COMMAND);
1286 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1287 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1288 DC_CMD_STATE_CONTROL);
1289 } else {
1290 /* set continuous mode */
1291 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1292 DC_CMD_DISPLAY_COMMAND);
1293 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1294 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1295 }
1296
1297 dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1298}
1299
1300static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1301 struct tegra_dc_dsi_data *dsi)
1302{
1303 u32 shift_clk_div_register;
1304 u32 val;
1305
1306 /* Get the corresponding register value of shift_clk_div. */
1307 shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
1308
1309#ifndef CONFIG_TEGRA_SILICON_PLATFORM
1310 shift_clk_div_register = 1;
1311#endif
1312
1313 /* TODO: find out if PCD3 option is required */
1314 val = PIXEL_CLK_DIVIDER_PCD1 |
1315 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1316 tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1317}
1318
1319static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1320 struct tegra_dc_dsi_data *dsi, u32 clk)
1321{
1322 u32 rm;
1323
1324 /* Round up to MHz */
1325 rm = clk % 1000;
1326 if (rm != 0)
1327 clk -= rm;
1328
1329 /* Set up pixel clock */
1330 dc->shift_clk_div = dsi->shift_clk_div;
1331 dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
1332 /* TODO: Define one shot work delay in board file. */
1333 /* Since for one-shot mode, refresh rate is usually set larger than
1334 * expected refresh rate, it needs at least 3 frame period. Less
1335 * delay one shot work is, more powering saving we have. */
1336 dc->one_shot_delay_ms = 4 *
1337 DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1338
1339 /* Enable DSI clock */
1340 tegra_dc_setup_clk(dc, dsi->dsi_clk);
1341 if (!dsi->clk_ref) {
1342 dsi->clk_ref = true;
1343 clk_enable(dsi->dsi_clk);
1344 tegra_periph_reset_deassert(dsi->dsi_clk);
1345 }
1346 dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1347 dsi->current_bit_clk_ns = 1000*1000 / (dsi->current_dsi_clk_khz * 2);
1348}
1349
1350static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1351{
1352 u32 val;
1353
1354 val = tegra_dsi_readl(dsi, DSI_CONTROL);
1355 val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1356
1357 if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1358 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1359 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1360 } else {
1361 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1362 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1363 }
1364 tegra_dsi_writel(dsi, val, DSI_CONTROL);
1365
1366 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1367 val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1368 val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1369 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1370
1371 dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1372}
1373
1374static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1375{
1376 u32 val;
1377 tegra_dsi_hs_clk_out_enable(dsi);
1378
1379 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1380 val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1381 val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1382 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1383}
1384
1385static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1386 struct tegra_dc_dsi_data *dsi)
1387{
1388 u32 val;
1389
1390 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1391 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1392
1393 tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1394 /* stabilization delay */
1395 udelay(300);
1396
1397 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1398 val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1399 val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1400 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1401
1402 tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1403 /* stabilization delay */
1404 udelay(300);
1405
1406 dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1407 dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1408}
1409
1410static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1411{
1412 u32 dsi_control;
1413 u32 host_dsi_control;
1414 u32 max_threshold;
1415
1416 dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1417 host_dsi_control = HOST_DSI_CTRL_COMMON |
1418 HOST_DSI_CTRL_HOST_DRIVEN |
1419 DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1420 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1421
1422 tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1423 tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1424 tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1425
1426 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1427 dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1428 dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1429}
1430
1431static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1432{
1433 u32 dsi_control;
1434 u32 host_dsi_control;
1435 u32 max_threshold;
1436 u32 dcs_cmd;
1437
1438 dsi_control = dsi->dsi_control_val;
1439 host_dsi_control = HOST_DSI_CTRL_COMMON;
1440 max_threshold = 0;
1441 dcs_cmd = 0;
1442
1443 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1444 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1445 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1446 max_threshold =
1447 DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1448 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1449 } else {
1450 dsi_control |= DSI_CTRL_DC_DRIVEN;
1451 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1452 max_threshold =
1453 DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1454 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1455 }
1456
1457 if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1458 dsi_control |= DSI_CTRL_CMD_MODE;
1459 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1460 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1461 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1462
1463 } else {
1464 dsi_control |= DSI_CTRL_VIDEO_MODE;
1465 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1466 }
1467
1468 tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1469 tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1470 tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1471 tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1472}
1473
1474static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1475{
1476 u32 val;
1477
1478 val = DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1479 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1480 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1481 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1482 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1483 if (!dsi->ulpm) {
1484 val |= DSI_PAD_CONTROL_PAD_PDIO(0) |
1485 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1486 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1487 } else {
1488 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1489 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1490 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1491 }
1492 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1493
1494 val = MIPI_CAL_TERMOSA(0x4);
1495 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1496
1497 val = MIPI_CAL_TERMOSB(0x4);
1498 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1499
1500 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1501 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1502
1503 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1504 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1505
1506 val = PAD_CIL_PDVREG(0x0);
1507 tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
1508}
1509
1510static int tegra_dsi_init_hw(struct tegra_dc *dc,
1511 struct tegra_dc_dsi_data *dsi)
1512{
1513 u32 i;
1514
1515 tegra_dsi_writel(dsi,
1516 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1517 DSI_POWER_CONTROL);
1518 /* stabilization delay */
1519 udelay(300);
1520
1521 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1522 if (dsi->info.dsi_instance) {
1523 /* TODO:Set the misc register*/
1524 }
1525
1526 /* TODO: only need to change the timing for bta */
1527 tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1528
1529 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1530 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1531
1532 /* Initializing DSI registers */
1533 for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1534 tegra_dsi_writel(dsi, 0, init_reg[i]);
1535
1536 tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1537
1538 tegra_dsi_pad_calibration(dsi);
1539
1540 tegra_dsi_writel(dsi,
1541 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1542 DSI_POWER_CONTROL);
1543 /* stabilization delay */
1544 udelay(300);
1545
1546 dsi->status.init = DSI_MODULE_INIT;
1547 dsi->status.lphs = DSI_LPHS_NOT_INIT;
1548 dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1549 dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1550 dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1551 dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1552 dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1553 dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1554 dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1555
1556 return 0;
1557}
1558
1559static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1560 struct tegra_dc_dsi_data *dsi, u8 lp_op)
1561{
1562 int err;
1563
1564 if (dsi->status.init != DSI_MODULE_INIT) {
1565 err = -EPERM;
1566 goto fail;
1567 }
1568
1569 if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1570 dsi->status.lp_op == lp_op)
1571 goto success;
1572
1573 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1574 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1575
1576 /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1577 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1578 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1579 tegra_dsi_hs_clk_out_disable(dc, dsi);
1580
1581 dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1582 if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1583 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1584 tegra_dsi_set_timeout(dsi);
1585 }
1586
1587 tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1588
1589 tegra_dsi_set_control_reg_lp(dsi);
1590
1591 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1592 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1593 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1594
1595 dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1596 dsi->status.lp_op = lp_op;
1597success:
1598 err = 0;
1599fail:
1600 return err;
1601}
1602
1603static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1604 struct tegra_dc_dsi_data *dsi)
1605{
1606 int err;
1607
1608 if (dsi->status.init != DSI_MODULE_INIT) {
1609 err = -EPERM;
1610 goto fail;
1611 }
1612
1613 if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1614 goto success;
1615
1616 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1617 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1618
1619 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1620 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1621 tegra_dsi_hs_clk_out_disable(dc, dsi);
1622
1623 if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1624 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1625 tegra_dsi_set_timeout(dsi);
1626 }
1627
1628 tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
1629
1630 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1631 tegra_dsi_set_pkt_seq(dc, dsi);
1632 tegra_dsi_set_pkt_length(dc, dsi);
1633 tegra_dsi_set_sol_delay(dc, dsi);
1634 tegra_dsi_set_dc_clk(dc, dsi);
1635 }
1636
1637 tegra_dsi_set_control_reg_hs(dsi);
1638
1639 if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
1640 dsi->info.enable_hs_clock_on_lp_cmd_mode)
1641 tegra_dsi_hs_clk_out_enable(dsi);
1642
1643 dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1644success:
1645 dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1646 err = 0;
1647fail:
1648 return err;
1649}
1650
1651static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1652{
1653 u32 timeout = 0;
1654 bool retVal = true;
1655
1656 while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1657 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1658 tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1659 retVal = false;
1660 break;
1661 }
1662 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1663 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1664 }
1665
1666 return retVal;
1667}
1668
1669static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1670{
1671 u32 timeout = 0;
1672 bool retVal = true;
1673
1674 while (timeout < DSI_STATUS_POLLING_DURATION_USEC) {
1675 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1676 tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1677 retVal = false;
1678 break;
1679 }
1680 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1681 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1682 }
1683
1684 return retVal;
1685}
1686
1687static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1688{
1689 int err = 0;
1690
1691 if (tegra_dsi_write_busy(dsi)) {
1692 err = -EBUSY;
1693 dev_err(&dsi->dc->ndev->dev,
1694 "DSI trigger bit already set\n");
1695 goto fail;
1696 }
1697
1698 if (tegra_dsi_read_busy(dsi)) {
1699 err = -EBUSY;
1700 dev_err(&dsi->dc->ndev->dev,
1701 "DSI immediate bta bit already set\n");
1702 goto fail;
1703 }
1704fail:
1705 return (err < 0 ? true : false);
1706}
1707
1708static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1709{
1710 u32 trigger;
1711 u32 status;
1712
1713 tegra_dsi_writel(dsi,
1714 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1715 DSI_POWER_CONTROL);
1716 /* stabilization delay */
1717 udelay(300);
1718
1719 tegra_dsi_writel(dsi,
1720 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1721 DSI_POWER_CONTROL);
1722 /* stabilization delay */
1723 udelay(300);
1724
1725 /* dsi HW does not clear host trigger bit automatically
1726 * on dsi interface disable if host fifo is empty
1727 */
1728 trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1729 status = tegra_dsi_readl(dsi, DSI_STATUS);
1730 if (trigger & DSI_TRIGGER_HOST_TRIGGER(0x1) &&
1731 status & DSI_STATUS_IDLE(0x1)) {
1732 trigger &= ~(DSI_TRIGGER_HOST_TRIGGER(0x1));
1733 tegra_dsi_writel(dsi, trigger, DSI_TRIGGER);
1734 }
1735}
1736
1737static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1738{
1739 u32 val;
1740
1741 val = tegra_dsi_readl(dsi, DSI_STATUS);
1742 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1743 if (val) {
1744 dev_warn(&dsi->dc->ndev->dev,
1745 "DSI read count not zero, resetting\n");
1746 tegra_dsi_soft_reset(dsi);
1747 }
1748}
1749
1750static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1751 struct tegra_dc_dsi_data *dsi,
1752 struct tegra_dc *dc,
1753 u8 lp_op)
1754{
1755 struct dsi_status *init_status;
1756 int err;
1757
1758 init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1759 if (!init_status)
1760 return ERR_PTR(-ENOMEM);
1761
1762 *init_status = dsi->status;
1763
1764 if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1765 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1766 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1767 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1768 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1769 if (dsi->info.hs_cmd_mode_supported) {
1770 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1771 if (err < 0) {
1772 dev_err(&dc->ndev->dev,
1773 "Switch to HS host mode failed\n");
1774 goto fail;
1775 }
1776 }
1777 }
1778 if (!dsi->info.hs_cmd_mode_supported) {
1779 err =
1780 tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1781 if (err < 0) {
1782 dev_err(&dc->ndev->dev,
1783 "DSI failed to go to LP mode\n");
1784 goto fail;
1785 }
1786 }
1787 } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1788 if (dsi->status.lp_op != lp_op) {
1789 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1790 if (err < 0) {
1791 dev_err(&dc->ndev->dev,
1792 "DSI failed to go to LP mode\n");
1793 goto fail;
1794 }
1795 }
1796 }
1797
1798 return init_status;
1799fail:
1800 kfree(init_status);
1801 return ERR_PTR(err);
1802}
1803
1804static struct dsi_status *tegra_dsi_prepare_host_transmission(
1805 struct tegra_dc *dc,
1806 struct tegra_dc_dsi_data *dsi,
1807 u8 lp_op)
1808{
1809 int err = 0;
1810 struct dsi_status *init_status;
1811
1812 if (dsi->status.init != DSI_MODULE_INIT ||
1813 dsi->ulpm) {
1814 err = -EPERM;
1815 goto fail;
1816 }
1817
1818 if (tegra_dsi_host_busy(dsi)) {
1819 tegra_dsi_soft_reset(dsi);
1820 if (tegra_dsi_host_busy(dsi)) {
1821 err = -EBUSY;
1822 dev_err(&dc->ndev->dev, "DSI host busy\n");
1823 goto fail;
1824 }
1825 }
1826
1827 if (lp_op == DSI_LP_OP_READ)
1828 tegra_dsi_reset_read_count(dsi);
1829
1830 if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1831 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1832 if (err < 0) {
1833 dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1834 goto fail;
1835 }
1836 }
1837
1838 init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1839 (dsi, dc, lp_op);
1840 if (IS_ERR_OR_NULL(init_status)) {
1841 err = PTR_ERR(init_status);
1842 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1843 goto fail;
1844 }
1845
1846 return init_status;
1847fail:
1848 return ERR_PTR(err);
1849}
1850
1851static int tegra_dsi_restore_state(struct tegra_dc *dc,
1852 struct tegra_dc_dsi_data *dsi,
1853 struct dsi_status *init_status)
1854{
1855 bool switch_back_to_dc_mode = false;
1856 bool switch_back_to_hs_mode = false;
1857 bool restart_dc_stream;
1858 int err = 0;
1859
1860 switch_back_to_dc_mode = (dsi->status.driven ==
1861 DSI_DRIVEN_MODE_HOST &&
1862 init_status->driven ==
1863 DSI_DRIVEN_MODE_DC);
1864 switch_back_to_hs_mode = (dsi->status.lphs ==
1865 DSI_LPHS_IN_LP_MODE &&
1866 init_status->lphs ==
1867 DSI_LPHS_IN_HS_MODE);
1868 restart_dc_stream = (dsi->status.dc_stream ==
1869 DSI_DC_STREAM_DISABLE &&
1870 init_status->dc_stream ==
1871 DSI_DC_STREAM_ENABLE);
1872
1873 if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1874 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
1875 if (dsi->status.lp_op != init_status->lp_op) {
1876 err =
1877 tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
1878 if (err < 0) {
1879 dev_err(&dc->ndev->dev,
1880 "Failed to config LP mode\n");
1881 goto fail;
1882 }
1883 }
1884 goto success;
1885 }
1886
1887 if (switch_back_to_dc_mode)
1888 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1889 if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
1890 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1891 if (err < 0) {
1892 dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
1893 goto fail;
1894 }
1895 }
1896 if (restart_dc_stream)
1897 tegra_dsi_start_dc_stream(dc, dsi);
1898
1899success:
1900fail:
1901 kfree(init_status);
1902 return err;
1903}
1904
1905static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1906{
1907 int status = 0;
1908
1909 if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1910 status = -EBUSY;
1911 goto fail;
1912 }
1913
1914 tegra_dsi_writel(dsi,
1915 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1916
1917#if DSI_USE_SYNC_POINTS
1918 status = tegra_dsi_syncpt(dsi);
1919 if (status < 0) {
1920 dev_err(&dsi->dc->ndev->dev,
1921 "DSI syncpt for host trigger failed\n");
1922 goto fail;
1923 }
1924#else
1925 if (tegra_dsi_write_busy(dsi)) {
1926 status = -EBUSY;
1927 dev_err(&dsi->dc->ndev->dev,
1928 "Timeout waiting on write completion\n");
1929 }
1930#endif
1931
1932fail:
1933 return status;
1934}
1935
1936static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1937 u8 *pdata, u8 data_id, u16 data_len)
1938{
1939 u8 virtual_channel;
1940 u8 *pval;
1941 u32 val;
1942 int err;
1943
1944 err = 0;
1945
1946 virtual_channel = dsi->info.virtual_channel <<
1947 DSI_VIR_CHANNEL_BIT_POSITION;
1948
1949 /* always use hw for ecc */
1950 val = (virtual_channel | data_id) << 0 |
1951 data_len << 8;
1952 tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1953
1954 /* if pdata != NULL, pkt type is long pkt */
1955 if (pdata != NULL) {
1956 while (data_len) {
1957 if (data_len >= 4) {
1958 val = ((u32 *) pdata)[0];
1959 data_len -= 4;
1960 pdata += 4;
1961 } else {
1962 val = 0;
1963 pval = (u8 *) &val;
1964 do
1965 *pval++ = *pdata++;
1966 while (--data_len);
1967 }
1968 tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1969 }
1970 }
1971
1972 err = tegra_dsi_host_trigger(dsi);
1973 if (err < 0)
1974 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
1975
1976 return err;
1977}
1978
1979int tegra_dsi_write_data(struct tegra_dc *dc,
1980 struct tegra_dc_dsi_data *dsi,
1981 u8 *pdata, u8 data_id, u16 data_len)
1982{
1983 int err = 0;
1984 struct dsi_status *init_status;
1985
1986 tegra_dc_io_start(dc);
1987
1988 init_status = tegra_dsi_prepare_host_transmission(
1989 dc, dsi, DSI_LP_OP_WRITE);
1990 if (IS_ERR_OR_NULL(init_status)) {
1991 err = PTR_ERR(init_status);
1992 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1993 goto fail;
1994 }
1995
1996 err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1997fail:
1998 err = tegra_dsi_restore_state(dc, dsi, init_status);
1999 if (err < 0)
2000 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2001 tegra_dc_io_end(dc);
2002 return err;
2003}
2004EXPORT_SYMBOL(tegra_dsi_write_data);
2005
2006static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2007 struct tegra_dc_dsi_data *dsi,
2008 struct tegra_dsi_cmd *cmd,
2009 u32 n_cmd)
2010{
2011 u32 i;
2012 int err;
2013
2014 err = 0;
2015 for (i = 0; i < n_cmd; i++) {
2016 struct tegra_dsi_cmd *cur_cmd;
2017 cur_cmd = &cmd[i];
2018
2019 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
2020 mdelay(cur_cmd->sp_len_dly.delay_ms);
2021 else {
2022 err = tegra_dsi_write_data(dc, dsi,
2023 cur_cmd->pdata,
2024 cur_cmd->data_id,
2025 cur_cmd->sp_len_dly.data_len);
2026 if (err < 0)
2027 break;
2028 }
2029 }
2030 return err;
2031}
2032
2033static u8 get_8bit_ecc(u32 header)
2034{
2035 char ecc_parity[24] = {
2036 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2037 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2038 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2039 };
2040 u8 ecc_byte;
2041 int i;
2042
2043 ecc_byte = 0;
2044 for (i = 0; i < 24; i++)
2045 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2046
2047 return ecc_byte;
2048}
2049
2050/* This function is written to send DCS short write (1 parameter) only.
2051 * This means the cmd will contain only 1 byte of index and 1 byte of value.
2052 * The data type ID is fixed at 0x15 and the ECC is calculated based on the
2053 * data in pdata.
2054 * The command will be sent by hardware every frame.
2055 * pdata should contain both the index + value for each cmd.
2056 * data_len will be the total number of bytes in pdata.
2057 */
2058int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
2059{
2060 u8 ecc8bits = 0, data_len_orig = 0;
2061 u32 val = 0, pkthdr = 0;
2062 int err = 0, count = 0;
2063 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2064
2065 data_len_orig = data_len;
2066 if (pdata != NULL) {
2067 while (data_len) {
2068 if (data_len >= 2) {
2069 pkthdr = (CMD_SHORTW |
2070 (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
2071 ecc8bits = get_8bit_ecc(pkthdr);
2072 val = (pkthdr | (ecc8bits << 24));
2073 data_len -= 2;
2074 pdata += 2;
2075 count++;
2076 }
2077 switch (count) {
2078 case 1:
2079 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
2080 break;
2081 case 2:
2082 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
2083 break;
2084 case 3:
2085 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
2086 break;
2087 case 4:
2088 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
2089 break;
2090 case 5:
2091 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
2092 break;
2093 case 6:
2094 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
2095 break;
2096 case 7:
2097 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
2098 break;
2099 case 8:
2100 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
2101 break;
2102 default:
2103 err = 1;
2104 break;
2105 }
2106 }
2107 }
2108
2109 val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
2110 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
2111 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2112
2113 return err;
2114}
2115EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
2116
2117static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2118{
2119 u32 val;
2120 u32 poll_time;
2121 int err;
2122
2123 poll_time = 0;
2124 err = 0;
2125
2126 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2127 val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2128 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2129
2130#if DSI_USE_SYNC_POINTS
2131 /* FIXME: Workaround for nvhost_syncpt_read */
2132 dsi->syncpt_val = nvhost_syncpt_update_min(
2133 &nvhost_get_host(dsi->dc->ndev)->syncpt,
2134 dsi->syncpt_id);
2135
2136 val = DSI_INCR_SYNCPT_COND(OP_DONE) |
2137 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
2138 tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
2139
2140 /* TODO: Use interrupt rather than polling */
2141 err = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
2142 dsi->syncpt_id, dsi->syncpt_val + 1);
2143 if (err < 0)
2144 dev_err(&dsi->dc->ndev->dev,
2145 "DSI sync point failure\n");
2146 else
2147 (dsi->syncpt_val)++;
2148#else
2149 if (tegra_dsi_read_busy(dsi)) {
2150 err = -EBUSY;
2151 dev_err(&dsi->dc->ndev->dev,
2152 "Timeout wating on read completion\n");
2153 }
2154#endif
2155
2156 return err;
2157}
2158
2159static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2160 u32 rd_fifo_cnt, u8 *read_fifo)
2161{
2162 int err;
2163 u32 payload_size;
2164
2165 payload_size = 0;
2166 err = 0;
2167
2168 switch (read_fifo[0]) {
2169 case DSI_ESCAPE_CMD:
2170 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2171 break;
2172 case DSI_ACK_NO_ERR:
2173 dev_info(&dc->ndev->dev,
2174 "Panel ack, no err[0x%x]\n", read_fifo[0]);
2175 return err;
2176 default:
2177 dev_info(&dc->ndev->dev, "Invalid read response\n");
2178 break;
2179 }
2180
2181 switch (read_fifo[4] & 0xff) {
2182 case GEN_LONG_RD_RES:
2183 /* Fall through */
2184 case DCS_LONG_RD_RES:
2185 payload_size = (read_fifo[5] |
2186 (read_fifo[6] << 8)) & 0xFFFF;
2187 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2188 "payload_size[0x%x]\n", payload_size);
2189 break;
2190 case GEN_1_BYTE_SHORT_RD_RES:
2191 /* Fall through */
2192 case DCS_1_BYTE_SHORT_RD_RES:
2193 payload_size = 1;
2194 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2195 "payload_size[0x%x]\n", payload_size);
2196 break;
2197 case GEN_2_BYTE_SHORT_RD_RES:
2198 /* Fall through */
2199 case DCS_2_BYTE_SHORT_RD_RES:
2200 payload_size = 2;
2201 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2202 "payload_size[0x%x]\n", payload_size);
2203 break;
2204 case ACK_ERR_RES:
2205 payload_size = 2;
2206 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2207 "Packet payload_size[0x%x]\n", payload_size);
2208 break;
2209 default:
2210 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2211 err = -EINVAL;
2212 break;
2213 }
2214 return err;
2215}
2216
2217static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2218 struct tegra_dc_dsi_data *dsi,
2219 u8 *read_fifo)
2220{
2221 u32 val;
2222 u32 i;
2223 u32 poll_time = 0;
2224 u32 rd_fifo_cnt;
2225 int err = 0;
2226 u8 *read_fifo_cp = read_fifo;
2227
2228 while (poll_time < DSI_DELAY_FOR_READ_FIFO) {
2229 mdelay(1);
2230 val = tegra_dsi_readl(dsi, DSI_STATUS);
2231 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2232 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
2233 dev_err(&dc->ndev->dev,
2234 "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2235 break;
2236 poll_time++;
2237 }
2238
2239 if (rd_fifo_cnt == 0) {
2240 dev_info(&dc->ndev->dev,
2241 "DSI RD_FIFO_CNT is zero\n");
2242 err = -EINVAL;
2243 goto fail;
2244 }
2245
2246 if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2247 DSI_STATUS_LB_OVERFLOW(0x1))) {
2248 dev_warn(&dc->ndev->dev,
2249 "DSI overflow/underflow error\n");
2250 }
2251
2252 /* Read data from FIFO */
2253 for (i = 0; i < rd_fifo_cnt; i++) {
2254 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2255 if (enable_read_debug)
2256 dev_info(&dc->ndev->dev,
2257 "Read data[%d]: 0x%x\n", i, val);
2258 memcpy(read_fifo, &val, 4);
2259 read_fifo += 4;
2260 }
2261
2262 /* Make sure all the data is read from the FIFO */
2263 val = tegra_dsi_readl(dsi, DSI_STATUS);
2264 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2265 if (val)
2266 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2267 " even after reading FIFO_RD_CNT words from read fifo\n");
2268
2269 if (enable_read_debug) {
2270 err =
2271 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2272 if (err < 0)
2273 dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2274 }
2275fail:
2276 return err;
2277}
2278
2279int tegra_dsi_read_data(struct tegra_dc *dc,
2280 struct tegra_dc_dsi_data *dsi,
2281 u32 max_ret_payload_size,
2282 u32 panel_reg_addr, u8 *read_data)
2283{
2284 int err = 0;
2285 struct dsi_status *init_status;
2286
2287 tegra_dc_io_start(dc);
2288
2289 init_status = tegra_dsi_prepare_host_transmission(
2290 dc, dsi, DSI_LP_OP_WRITE);
2291 if (IS_ERR_OR_NULL(init_status)) {
2292 err = PTR_ERR(init_status);
2293 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2294 goto fail;
2295 }
2296
2297 /* Set max return payload size in words */
2298 err = _tegra_dsi_write_data(dsi, NULL,
2299 dsi_command_max_return_pkt_size,
2300 max_ret_payload_size);
2301 if (err < 0) {
2302 dev_err(&dc->ndev->dev,
2303 "DSI write failed\n");
2304 goto fail;
2305 }
2306
2307 /* DCS to read given panel register */
2308 err = _tegra_dsi_write_data(dsi, NULL,
2309 dsi_command_dcs_read_with_no_params,
2310 panel_reg_addr);
2311 if (err < 0) {
2312 dev_err(&dc->ndev->dev,
2313 "DSI write failed\n");
2314 goto fail;
2315 }
2316
2317 tegra_dsi_reset_read_count(dsi);
2318
2319 if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2320 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2321 if (err < 0) {
2322 dev_err(&dc->ndev->dev,
2323 "DSI failed to go to LP read mode\n");
2324 goto fail;
2325 }
2326 }
2327
2328 err = tegra_dsi_bta(dsi);
2329 if (err < 0) {
2330 dev_err(&dc->ndev->dev,
2331 "DSI IMM BTA timeout\n");
2332 goto fail;
2333 }
2334
2335 err = tegra_dsi_read_fifo(dc, dsi, read_data);
2336 if (err < 0) {
2337 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2338 goto fail;
2339 }
2340fail:
2341 err = tegra_dsi_restore_state(dc, dsi, init_status);
2342 if (err < 0)
2343 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2344 tegra_dc_io_end(dc);
2345 return err;
2346}
2347EXPORT_SYMBOL(tegra_dsi_read_data);
2348
2349int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
2350 struct tegra_dc_dsi_data *dsi)
2351{
2352 int err = 0;
2353 u8 read_fifo[DSI_READ_FIFO_DEPTH];
2354 struct dsi_status *init_status;
2355 static struct tegra_dsi_cmd dsi_nop_cmd =
2356 DSI_CMD_SHORT(0x05, 0x0, 0x0);
2357
2358 tegra_dc_io_start(dc);
2359
2360 init_status = tegra_dsi_prepare_host_transmission(
2361 dc, dsi, DSI_LP_OP_WRITE);
2362 if (IS_ERR_OR_NULL(init_status)) {
2363 err = PTR_ERR(init_status);
2364 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2365 goto fail;
2366 }
2367
2368 err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
2369 if (err < 0) {
2370 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
2371 goto fail;
2372 }
2373
2374 tegra_dsi_reset_read_count(dsi);
2375
2376 if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2377 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2378 if (err < 0) {
2379 dev_err(&dc->ndev->dev,
2380 "DSI failed to go to LP read mode\n");
2381 goto fail;
2382 }
2383 }
2384
2385 err = tegra_dsi_bta(dsi);
2386 if (err < 0) {
2387 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2388 goto fail;
2389 }
2390
2391 err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2392 if (err < 0) {
2393 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2394 goto fail;
2395 }
2396
2397 if (read_fifo[0] != DSI_ACK_NO_ERR) {
2398 dev_warn(&dc->ndev->dev,
2399 "Ack no error trigger message not received\n");
2400 err = -EAGAIN;
2401 }
2402fail:
2403 err = tegra_dsi_restore_state(dc, dsi, init_status);
2404 if (err < 0)
2405 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2406 tegra_dc_io_end(dc);
2407 return err;
2408}
2409EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2410
2411static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2412{
2413 u32 val;
2414 int ret;
2415
2416 ret = 0;
2417
2418 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2419 val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2420 val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2421 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2422
2423#if DSI_USE_SYNC_POINTS
2424 ret = tegra_dsi_syncpt(dsi);
2425 if (ret < 0) {
2426 dev_err(&dsi->dc->ndev->dev,
2427 "DSI syncpt for ulpm enter failed\n");
2428 goto fail;
2429 }
2430#else
2431 /* TODO: Find exact delay required */
2432 mdelay(10);
2433#endif
2434 dsi->ulpm = true;
2435fail:
2436 return ret;
2437}
2438
2439static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2440{
2441 u32 val;
2442 int ret;
2443
2444 ret = 0;
2445
2446 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2447 val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2448 val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2449 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2450
2451#if DSI_USE_SYNC_POINTS
2452 ret = tegra_dsi_syncpt(dsi);
2453 if (ret < 0) {
2454 dev_err(&dsi->dc->ndev->dev,
2455 "DSI syncpt for ulpm exit failed\n");
2456 goto fail;
2457 }
2458#else
2459 /* TODO: Find exact delay required */
2460 mdelay(10);
2461#endif
2462 dsi->ulpm = false;
2463
2464 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2465 val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
2466 val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
2467 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2468fail:
2469 return ret;
2470
2471}
2472
2473static void tegra_dc_dsi_enable(struct tegra_dc *dc)
2474{
2475 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2476 int err;
2477 u32 val;
2478
2479 tegra_dc_io_start(dc);
2480 mutex_lock(&dsi->lock);
2481
2482 /* Stop DC stream before configuring DSI registers
2483 * to avoid visible glitches on panel during transition
2484 * from bootloader to kernel driver
2485 */
2486 tegra_dsi_stop_dc_stream(dc, dsi);
2487
2488 if (dsi->enabled) {
2489 if (dsi->ulpm) {
2490 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2491 dev_err(&dc->ndev->dev,
2492 "DSI failed to exit ulpm\n");
2493 goto fail;
2494 }
2495 }
2496
2497 if (dsi->info.panel_reset) {
2498 err = tegra_dsi_send_panel_cmd(dc, dsi,
2499 dsi->info.dsi_init_cmd,
2500 dsi->info.n_init_cmd);
2501 if (err < 0) {
2502 dev_err(&dc->ndev->dev,
2503 "dsi: error sending dsi init cmd\n");
2504 goto fail;
2505 }
2506 } else if (dsi->info.dsi_late_resume_cmd) {
2507 err = tegra_dsi_send_panel_cmd(dc, dsi,
2508 dsi->info.dsi_late_resume_cmd,
2509 dsi->info.n_late_resume_cmd);
2510 if (err < 0) {
2511 dev_err(&dc->ndev->dev,
2512 "dsi: error sending late resume cmd\n");
2513 goto fail;
2514 }
2515 }
2516 } else {
2517 err = tegra_dsi_init_hw(dc, dsi);
2518 if (err < 0) {
2519 dev_err(&dc->ndev->dev,
2520 "dsi: not able to init dsi hardware\n");
2521 goto fail;
2522 }
2523
2524 if (dsi->ulpm) {
2525 if (tegra_dsi_enter_ulpm(dsi) < 0) {
2526 dev_err(&dc->ndev->dev,
2527 "DSI failed to enter ulpm\n");
2528 goto fail;
2529 }
2530
2531 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2532
2533 /* erase bits we're about to set */
2534 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2535 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2536 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2537
2538 val |= (DSI_PAD_CONTROL_PAD_PDIO(0) |
2539 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
2540 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
2541 (TEGRA_DSI_DISABLE));
2542
2543 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2544 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2545 dev_err(&dc->ndev->dev,
2546 "DSI failed to exit ulpm\n");
2547 goto fail;
2548 }
2549 }
2550
2551 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2552 if (err < 0) {
2553 dev_err(&dc->ndev->dev,
2554 "dsi: not able to set to lp mode\n");
2555 goto fail;
2556 }
2557
2558 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
2559 dsi->info.n_init_cmd);
2560 if (err < 0) {
2561 dev_err(&dc->ndev->dev,
2562 "dsi: error while sending dsi init cmd\n");
2563 goto fail;
2564 }
2565
2566 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2567 if (err < 0) {
2568 dev_err(&dc->ndev->dev,
2569 "dsi: not able to set to hs mode\n");
2570 goto fail;
2571 }
2572
2573 dsi->enabled = true;
2574 }
2575
2576 if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
2577 tegra_dsi_start_dc_stream(dc, dsi);
2578fail:
2579 mutex_unlock(&dsi->lock);
2580 tegra_dc_io_end(dc);
2581}
2582
2583static void _tegra_dc_dsi_init(struct tegra_dc *dc)
2584{
2585 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2586
2587 tegra_dsi_init_sw(dc, dsi);
2588 /* TODO: Configure the CSI pad configuration */
2589}
2590
2591static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
2592 struct tegra_dsi_cmd *dst, u16 n_cmd)
2593{
2594 u16 i;
2595 u16 len;
2596
2597 memcpy(dst, src, sizeof(*dst) * n_cmd);
2598
2599 for (i = 0; i < n_cmd; i++)
2600 if (src[i].pdata) {
2601 len = sizeof(*src[i].pdata) *
2602 src[i].sp_len_dly.data_len;
2603 dst[i].pdata = kzalloc(len, GFP_KERNEL);
2604 if (!dst[i].pdata)
2605 goto free_cmd_pdata;
2606 memcpy(dst[i].pdata, src[i].pdata, len);
2607 }
2608
2609 return 0;
2610
2611free_cmd_pdata:
2612 for (--i; i >= 0; i--)
2613 if (dst[i].pdata)
2614 kfree(dst[i].pdata);
2615 return -ENOMEM;
2616}
2617
2618static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2619 struct tegra_dsi_out *p_dsi)
2620{
2621 struct tegra_dsi_cmd *p_init_cmd;
2622 struct tegra_dsi_cmd *p_early_suspend_cmd;
2623 struct tegra_dsi_cmd *p_late_resume_cmd;
2624 struct tegra_dsi_cmd *p_suspend_cmd;
2625 int err;
2626
2627 if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
2628 return -EINVAL;
2629
2630 p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
2631 p_dsi->n_init_cmd, GFP_KERNEL);
2632 if (!p_init_cmd)
2633 return -ENOMEM;
2634
2635 if (p_dsi->dsi_early_suspend_cmd) {
2636 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2637 p_dsi->n_early_suspend_cmd,
2638 GFP_KERNEL);
2639 if (!p_early_suspend_cmd) {
2640 err = -ENOMEM;
2641 goto err_free_init_cmd;
2642 }
2643 }
2644
2645 if (p_dsi->dsi_late_resume_cmd) {
2646 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2647 p_dsi->n_late_resume_cmd,
2648 GFP_KERNEL);
2649 if (!p_late_resume_cmd) {
2650 err = -ENOMEM;
2651 goto err_free_p_early_suspend_cmd;
2652 }
2653 }
2654
2655 p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2656 GFP_KERNEL);
2657 if (!p_suspend_cmd) {
2658 err = -ENOMEM;
2659 goto err_free_p_late_resume_cmd;
2660 }
2661
2662 memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2663
2664 /* Copy panel init cmd */
2665 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2666 p_init_cmd, p_dsi->n_init_cmd);
2667 if (err < 0)
2668 goto err_free;
2669 dsi->info.dsi_init_cmd = p_init_cmd;
2670
2671 /* Copy panel early suspend cmd */
2672 if (p_dsi->dsi_early_suspend_cmd) {
2673 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2674 p_early_suspend_cmd,
2675 p_dsi->n_early_suspend_cmd);
2676 if (err < 0)
2677 goto err_free;
2678 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2679 }
2680
2681 /* Copy panel late resume cmd */
2682 if (p_dsi->dsi_late_resume_cmd) {
2683 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2684 p_late_resume_cmd,
2685 p_dsi->n_late_resume_cmd);
2686 if (err < 0)
2687 goto err_free;
2688 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2689 }
2690
2691 /* Copy panel suspend cmd */
2692 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2693 p_dsi->n_suspend_cmd);
2694 if (err < 0)
2695 goto err_free;
2696 dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2697
2698 if (!dsi->info.panel_reset_timeout_msec)
2699 dsi->info.panel_reset_timeout_msec =
2700 DEFAULT_PANEL_RESET_TIMEOUT;
2701
2702 if (!dsi->info.panel_buffer_size_byte)
2703 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2704
2705 if (!dsi->info.max_panel_freq_khz) {
2706 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2707
2708 if (dsi->info.video_burst_mode >
2709 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2710 dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2711 "is not set for DSI burst mode.\n");
2712 dsi->info.video_burst_mode =
2713 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2714 }
2715 }
2716
2717 if (!dsi->info.lp_cmd_mode_freq_khz)
2718 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2719
2720 if (!dsi->info.chip_id || !dsi->info.chip_rev)
2721 dev_warn(&dsi->dc->ndev->dev,
2722 "DSI: Failed to get chip info\n");
2723
2724 if (!dsi->info.lp_read_cmd_mode_freq_khz)
2725 dsi->info.lp_read_cmd_mode_freq_khz =
2726 dsi->info.lp_cmd_mode_freq_khz;
2727
2728 /* host mode is for testing only */
2729 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2730 return 0;
2731
2732err_free:
2733 kfree(p_suspend_cmd);
2734err_free_p_late_resume_cmd:
2735 kfree(p_late_resume_cmd);
2736err_free_p_early_suspend_cmd:
2737 kfree(p_early_suspend_cmd);
2738err_free_init_cmd:
2739 kfree(p_init_cmd);
2740 return err;
2741}
2742
2743static int tegra_dc_dsi_init(struct tegra_dc *dc)
2744{
2745 struct tegra_dc_dsi_data *dsi;
2746 struct resource *res;
2747 struct resource *base_res;
2748 void __iomem *base;
2749 struct clk *dc_clk = NULL;
2750 struct clk *dsi_clk = NULL;
2751 struct tegra_dsi_out *dsi_pdata;
2752 int err;
2753
2754 err = 0;
2755
2756 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2757 if (!dsi)
2758 return -ENOMEM;
2759
2760 res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2761 "dsi_regs");
2762 if (!res) {
2763 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2764 err = -ENOENT;
2765 goto err_free_dsi;
2766 }
2767
2768 base_res = request_mem_region(res->start, resource_size(res),
2769 dc->ndev->name);
2770 if (!base_res) {
2771 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2772 err = -EBUSY;
2773 goto err_free_dsi;
2774 }
2775
2776 base = ioremap(res->start, resource_size(res));
2777 if (!base) {
2778 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2779 err = -EBUSY;
2780 goto err_release_regs;
2781 }
2782
2783 dsi_pdata = dc->pdata->default_out->dsi;
2784 if (!dsi_pdata) {
2785 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2786 goto err_release_regs;
2787 }
2788
2789 if (dsi_pdata->dsi_instance)
2790 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2791 else
2792 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2793
2794 if (IS_ERR_OR_NULL(dsi_clk)) {
2795 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2796 err = -EBUSY;
2797 goto err_release_regs;
2798 }
2799
2800 dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2801 if (IS_ERR_OR_NULL(dc_clk)) {
2802 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2803 dev_name(&dc->ndev->dev));
2804 err = -EBUSY;
2805 goto err_clk_put;
2806 }
2807
2808 mutex_init(&dsi->lock);
2809 dsi->dc = dc;
2810 dsi->base = base;
2811 dsi->base_res = base_res;
2812 dsi->dc_clk = dc_clk;
2813 dsi->dsi_clk = dsi_clk;
2814
2815 err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2816 if (err < 0)
2817 goto err_dsi_data;
2818
2819 tegra_dc_set_outdata(dc, dsi);
2820 _tegra_dc_dsi_init(dc);
2821
2822 return 0;
2823
2824err_dsi_data:
2825err_clk_put:
2826 clk_put(dsi_clk);
2827err_release_regs:
2828 release_resource(base_res);
2829err_free_dsi:
2830 kfree(dsi);
2831
2832 return err;
2833}
2834
2835static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2836{
2837 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2838 u16 i;
2839 u32 val;
2840
2841 mutex_lock(&dsi->lock);
2842
2843 /* free up the pdata */
2844 for (i = 0; i < dsi->info.n_init_cmd; i++) {
2845 if (dsi->info.dsi_init_cmd[i].pdata)
2846 kfree(dsi->info.dsi_init_cmd[i].pdata);
2847 }
2848 kfree(dsi->info.dsi_init_cmd);
2849
2850 /* Disable dc stream */
2851 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2852 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2853
2854 /* Disable dsi phy clock */
2855 if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2856 tegra_dsi_hs_clk_out_disable(dc, dsi);
2857
2858 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2859 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2860
2861 iounmap(dsi->base);
2862 release_resource(dsi->base_res);
2863
2864 clk_put(dsi->dc_clk);
2865 clk_put(dsi->dsi_clk);
2866
2867 mutex_unlock(&dsi->lock);
2868
2869 mutex_destroy(&dsi->lock);
2870 kfree(dsi);
2871}
2872
2873static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
2874 struct tegra_dc_dsi_data *dsi)
2875{
2876 int err = 0;
2877 int val;
2878 struct clk *parent_clk = NULL;
2879 struct clk *base_clk = NULL;
2880
2881 if (!dsi->enabled) {
2882 err = -EPERM;
2883 goto fail;
2884 }
2885
2886 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2887 if (err < 0) {
2888 dev_err(&dc->ndev->dev,
2889 "DSI failed to go to LP mode\n");
2890 goto fail;
2891 }
2892
2893 /* Suspend panel */
2894 err = tegra_dsi_send_panel_cmd(dc, dsi,
2895 dsi->info.dsi_suspend_cmd,
2896 dsi->info.n_suspend_cmd);
2897 if (err < 0) {
2898 dev_err(&dc->ndev->dev,
2899 "dsi: Error sending suspend cmd\n");
2900 goto fail;
2901 }
2902
2903 if (!dsi->ulpm) {
2904 err = tegra_dsi_enter_ulpm(dsi);
2905 if (err < 0) {
2906 dev_err(&dc->ndev->dev,
2907 "DSI failed to enter ulpm\n");
2908 goto fail;
2909 }
2910 }
2911
2912 /*
2913 * Suspend pad
2914 * It is ok to overwrite previous value of DSI_PAD_CONTROL reg
2915 * because it will be restored properly in resume sequence
2916 */
2917 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2918 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2919 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2920 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2921
2922 /* Suspend core-logic */
2923 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2924 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2925
2926 /* Disable dsi fast and slow clock */
2927 parent_clk = clk_get_parent(dsi->dsi_clk);
2928 base_clk = clk_get_parent(parent_clk);
2929 if (dsi->info.dsi_instance)
2930 tegra_clk_cfg_ex(base_clk,
2931 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2932 0);
2933 else
2934 tegra_clk_cfg_ex(base_clk,
2935 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2936 0);
2937
2938 /* Disable dsi source clock */
2939 clk_disable(dsi->dsi_clk);
2940
2941 dsi->clk_ref = false;
2942 dsi->enabled = false;
2943
2944 return 0;
2945fail:
2946 return err;
2947}
2948
2949static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2950{
2951 int err;
2952 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2953
2954 tegra_dc_io_start(dc);
2955 mutex_lock(&dsi->lock);
2956
2957 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2958 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2959
2960 if (dsi->info.power_saving_suspend) {
2961 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2962 dev_err(&dc->ndev->dev,
2963 "DSI failed to enter deep sleep\n");
2964 goto fail;
2965 }
2966 } else {
2967 if (dsi->info.dsi_early_suspend_cmd) {
2968 err = tegra_dsi_send_panel_cmd(dc, dsi,
2969 dsi->info.dsi_early_suspend_cmd,
2970 dsi->info.n_early_suspend_cmd);
2971 if (err < 0) {
2972 dev_err(&dc->ndev->dev,
2973 "dsi: Error sending early suspend cmd\n");
2974 goto fail;
2975 }
2976 }
2977
2978 if (!dsi->ulpm) {
2979 if (tegra_dsi_enter_ulpm(dsi) < 0) {
2980 dev_err(&dc->ndev->dev,
2981 "DSI failed to enter ulpm\n");
2982 goto fail;
2983 }
2984 }
2985 }
2986
2987fail:
2988 mutex_unlock(&dsi->lock);
2989 tegra_dc_io_end(dc);
2990}
2991
2992#ifdef CONFIG_PM
2993static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2994{
2995 struct tegra_dc_dsi_data *dsi;
2996
2997 dsi = tegra_dc_get_outdata(dc);
2998
2999 if (!dsi->enabled)
3000 return;
3001
3002 tegra_dc_io_start(dc);
3003 mutex_lock(&dsi->lock);
3004
3005 if (!dsi->info.power_saving_suspend) {
3006 if (dsi->ulpm) {
3007 if (tegra_dsi_exit_ulpm(dsi) < 0) {
3008 dev_err(&dc->ndev->dev,
3009 "DSI failed to exit ulpm");
3010 goto fail;
3011 }
3012 }
3013
3014 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
3015 dev_err(&dc->ndev->dev,
3016 "DSI failed to enter deep sleep\n");
3017 goto fail;
3018 }
3019 }
3020fail:
3021 mutex_unlock(&dsi->lock);
3022 tegra_dc_io_end(dc);
3023}
3024
3025static void tegra_dc_dsi_resume(struct tegra_dc *dc)
3026{
3027 /* Not required since tegra_dc_dsi_enable
3028 * will reconfigure the controller from scratch
3029 */
3030}
3031#endif
3032
3033struct tegra_dc_out_ops tegra_dc_dsi_ops = {
3034 .init = tegra_dc_dsi_init,
3035 .destroy = tegra_dc_dsi_destroy,
3036 .enable = tegra_dc_dsi_enable,
3037 .disable = tegra_dc_dsi_disable,
3038#ifdef CONFIG_PM
3039 .suspend = tegra_dc_dsi_suspend,
3040 .resume = tegra_dc_dsi_resume,
3041#endif
3042};
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-11 13:52:15 -0500