Added missing tegra files.HEAD master

author: Jonathan Herman <hermanjl@cs.unc.edu> 2013-01-22 10:38:37 -0500
committer: Jonathan Herman <hermanjl@cs.unc.edu> 2013-01-22 10:38:37 -0500
commit: fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
tree: a57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/video/tegra/dc/dc_reg.h
parent: 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
1 files changed, 555 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/dc_reg.h b/drivers/video/tegra/dc/dc_reg.h
new file mode 100644
index 00000000000..22379a19408
--- /dev/null
+++ b/drivers/video/tegra/dc/dc_reg.h
@@ -0,0 +1,555 @@
+/*
+ * drivers/video/tegra/dc/dc_reg.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Erik Gilling <konkers@android.com>
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __DRIVERS_VIDEO_TEGRA_DC_DC_REG_H
+#define __DRIVERS_VIDEO_TEGRA_DC_DC_REG_H
+#define DC_CMD_GENERAL_INCR_SYNCPT              0x000
+#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL        0x001
+#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR        0x002
+#define DC_CMD_WIN_A_INCR_SYNCPT                0x008
+#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL          0x009
+#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR          0x00a
+#define DC_CMD_WIN_B_INCR_SYNCPT                0x010
+#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL          0x011
+#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR          0x012
+#define DC_CMD_WIN_C_INCR_SYNCPT                0x018
+#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL          0x019
+#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR          0x01a
+#define DC_CMD_CONT_SYNCPT_VSYNC                0x028
+#define DC_CMD_DISPLAY_COMMAND_OPTION0          0x031
+#define  MSF_POLARITY_HIGH                      (0 << 0)
+#define  MSF_POLARITY_LOW                       (1 << 0)
+#define  MSF_DISABLE                            (0 << 1)
+#define  MSF_ENABLE                             (1 << 1)
+#define  MSF_LSPI                               (0 << 2)
+#define  MSF_LDC                                (1 << 2)
+#define  MSF_LSDI                               (2 << 2)
+#define DC_CMD_DISPLAY_COMMAND                  0x032
+#define  DISP_COMMAND_RAISE             (1 << 0)
+#define  DISP_CTRL_MODE_STOP            (0 << 5)
+#define  DISP_CTRL_MODE_C_DISPLAY       (1 << 5)
+#define  DISP_CTRL_MODE_NC_DISPLAY      (2 << 5)
+#define  DISP_COMMAND_RAISE_VECTOR(x)   (((x) & 0x1f) << 22)
+#define  DISP_COMMAND_RAISE_CHANNEL_ID(x)       (((x) & 0xf) << 27)
+#define DC_CMD_SIGNAL_RAISE                     0x033
+#define DC_CMD_DISPLAY_POWER_CONTROL            0x036
+#define  PW0_ENABLE             (1 << 0)
+#define  PW1_ENABLE             (1 << 2)
+#define  PW2_ENABLE             (1 << 4)
+#define  PW3_ENABLE             (1 << 6)
+#define  PW4_ENABLE             (1 << 8)
+#define  PM0_ENABLE             (1 << 16)
+#define  PM1_ENABLE             (1 << 18)
+#define  SPI_ENABLE             (1 << 24)
+#define  HSPI_ENABLE            (1 << 25)
+#define DC_CMD_INT_STATUS                       0x037
+#define DC_CMD_INT_MASK                         0x038
+#define DC_CMD_INT_ENABLE                       0x039
+#define DC_CMD_INT_TYPE                         0x03a
+#define DC_CMD_INT_POLARITY                     0x03b
+#define  CTXSW_INT              (1 << 0)
+#define  FRAME_END_INT          (1 << 1)
+#define  V_BLANK_INT            (1 << 2)
+#define  H_BLANK_INT            (1 << 3)
+#define  V_PULSE3_INT           (1 << 4)
+#define  SPI_BUSY_INT           (1 << 7)
+#define  WIN_A_UF_INT           (1 << 8)
+#define  WIN_B_UF_INT           (1 << 9)
+#define  WIN_C_UF_INT           (1 << 10)
+#define  MSF_INT                (1 << 12)
+#define  SSF_INT                (1 << 13)
+#define  WIN_A_OF_INT           (1 << 14)
+#define  WIN_B_OF_INT           (1 << 15)
+#define  WIN_C_OF_INT           (1 << 16)
+#define  GPIO_0_INT             (1 << 18)
+#define  GPIO_1_INT             (1 << 19)
+#define  GPIO_2_INT             (1 << 20)
+#define DC_CMD_SIGNAL_RAISE1                    0x03c
+#define DC_CMD_SIGNAL_RAISE2                    0x03d
+#define DC_CMD_SIGNAL_RAISE3                    0x03e
+#define DC_CMD_STATE_ACCESS                     0x040
+#define  READ_MUX_ASSEMBLY      (0 << 0)
+#define  READ_MUX_ACTIVE        (1 << 0)
+#define  WRITE_MUX_ASSEMBLY     (0 << 2)
+#define  WRITE_MUX_ACTIVE       (1 << 2)
+#define DC_CMD_STATE_CONTROL                    0x041
+#define  GENERAL_ACT_REQ        (1 << 0)
+#define  WIN_A_ACT_REQ          (1 << 1)
+#define  WIN_B_ACT_REQ          (1 << 2)
+#define  WIN_C_ACT_REQ          (1 << 3)
+#define  GENERAL_UPDATE         (1 << 8)
+#define  WIN_A_UPDATE           (1 << 9)
+#define  WIN_B_UPDATE           (1 << 10)
+#define  WIN_C_UPDATE           (1 << 11)
+#define  NC_HOST_TRIG           (1 << 24)
+#define DC_CMD_DISPLAY_WINDOW_HEADER            0x042
+#define  WINDOW_A_SELECT                (1 << 4)
+#define  WINDOW_B_SELECT                (1 << 5)
+#define  WINDOW_C_SELECT                (1 << 6)
+#define DC_CMD_REG_ACT_CONTROL                  0x043
+#define DC_COM_CRC_CONTROL                      0x300
+#define  CRC_ALWAYS_ENABLE              (1 << 3)
+#define  CRC_ALWAYS_DISABLE             (0 << 3)
+#define  CRC_INPUT_DATA_ACTIVE_DATA     (1 << 2)
+#define  CRC_INPUT_DATA_FULL_FRAME      (0 << 2)
+#define  CRC_WAIT_TWO_VSYNC             (1 << 1)
+#define  CRC_WAIT_ONE_VSYNC             (0 << 1)
+#define  CRC_ENABLE_ENABLE              (1 << 0)
+#define  CRC_ENABLE_DISABLE             (0 << 0)
+#define DC_COM_CRC_CHECKSUM                     0x301
+#define DC_COM_PIN_OUTPUT_ENABLE0               0x302
+#define DC_COM_PIN_OUTPUT_ENABLE1               0x303
+#define DC_COM_PIN_OUTPUT_ENABLE2               0x304
+#define DC_COM_PIN_OUTPUT_ENABLE3               0x305
+#define  PIN_OUTPUT_LSPI_OUTPUT_EN              (1 << 8)
+#define  PIN_OUTPUT_LSPI_OUTPUT_DIS             (1 << 8)
+#define DC_COM_PIN_OUTPUT_POLARITY0             0x306
+#define DC_COM_PIN_OUTPUT_POLARITY1             0x307
+#define  LHS_OUTPUT_POLARITY_LOW        (1 << 30)
+#define  LVS_OUTPUT_POLARITY_LOW        (1 << 28)
+#define  LSC0_OUTPUT_POLARITY_LOW       (1 << 24)
+#define DC_COM_PIN_OUTPUT_POLARITY2             0x308
+#define DC_COM_PIN_OUTPUT_POLARITY3             0x309
+#define  LSPI_OUTPUT_POLARITY_LOW       (1 << 8)
+#define DC_COM_PIN_OUTPUT_DATA0                 0x30a
+#define DC_COM_PIN_OUTPUT_DATA1                 0x30b
+#define DC_COM_PIN_OUTPUT_DATA2                 0x30c
+#define DC_COM_PIN_OUTPUT_DATA3                 0x30d
+#define DC_COM_PIN_INPUT_ENABLE0                0x30e
+#define DC_COM_PIN_INPUT_ENABLE1                0x30f
+#define DC_COM_PIN_INPUT_ENABLE2                0x310
+#define DC_COM_PIN_INPUT_ENABLE3                0x311
+#define  PIN_INPUT_LSPI_INPUT_EN                (1 << 8)
+#define  PIN_INPUT_LSPI_INPUT_DIS               (1 << 8)
+#define DC_COM_PIN_INPUT_DATA0                  0x312
+#define DC_COM_PIN_INPUT_DATA1                  0x313
+#define DC_COM_PIN_OUTPUT_SELECT0               0x314
+#define DC_COM_PIN_OUTPUT_SELECT1               0x315
+#define DC_COM_PIN_OUTPUT_SELECT2               0x316
+#define DC_COM_PIN_OUTPUT_SELECT3               0x317
+#define DC_COM_PIN_OUTPUT_SELECT4               0x318
+#define DC_COM_PIN_OUTPUT_SELECT5               0x319
+#define DC_COM_PIN_OUTPUT_SELECT6               0x31a
+#define PIN5_LM1_LCD_M1_OUTPUT_MASK     (7 << 4)
+#define PIN5_LM1_LCD_M1_OUTPUT_M1       (0 << 4)
+#define PIN5_LM1_LCD_M1_OUTPUT_LD21     (2 << 4)
+#define PIN5_LM1_LCD_M1_OUTPUT_PM1      (3 << 4)
+#define  PIN1_LHS_OUTPUT                (1 << 30)
+#define  PIN1_LVS_OUTPUT                (1 << 28)
+#define DC_COM_PIN_MISC_CONTROL                 0x31b
+#define DC_COM_PM0_CONTROL                      0x31c
+#define DC_COM_PM0_DUTY_CYCLE                   0x31d
+#define DC_COM_PM1_CONTROL                      0x31e
+#define DC_COM_PM1_DUTY_CYCLE                   0x31f
+#define PM_PERIOD_SHIFT                 18
+#define PM_CLK_DIVIDER_SHIFT            4
+#define DC_COM_SPI_CONTROL                      0x320
+#define DC_COM_SPI_START_BYTE                   0x321
+#define DC_COM_HSPI_WRITE_DATA_AB               0x322
+#define DC_COM_HSPI_WRITE_DATA_CD               0x323
+#define DC_COM_HSPI_CS_DC                       0x324
+#define DC_COM_SCRATCH_REGISTER_A               0x325
+#define DC_COM_SCRATCH_REGISTER_B               0x326
+#define DC_COM_GPIO_CTRL                        0x327
+#define DC_COM_GPIO_DEBOUNCE_COUNTER            0x328
+#define DC_COM_CRC_CHECKSUM_LATCHED             0x329
+#define DC_DISP_DISP_SIGNAL_OPTIONS0            0x400
+#define  H_PULSE_0_ENABLE               (1 << 8)
+#define  H_PULSE_1_ENABLE               (1 << 10)
+#define  H_PULSE_2_ENABLE               (1 << 12)
+#define  V_PULSE_0_ENABLE               (1 << 16)
+#define  V_PULSE_1_ENABLE               (1 << 18)
+#define  V_PULSE_2_ENABLE               (1 << 19)
+#define  V_PULSE_3_ENABLE               (1 << 20)
+#define  M0_ENABLE                      (1 << 24)
+#define  M1_ENABLE                      (1 << 26)
+#define DC_DISP_DISP_SIGNAL_OPTIONS1            0x401
+#define  DI_ENABLE                      (1 << 16)
+#define  PP_ENABLE                      (1 << 18)
+#define DC_DISP_DISP_WIN_OPTIONS                0x402
+#define  CURSOR_ENABLE                  (1 << 16)
+#define  TVO_ENABLE                     (1 << 28)
+#define  DSI_ENABLE                     (1 << 29)
+#define  HDMI_ENABLE                    (1 << 30)
+#define DC_DISP_MEM_HIGH_PRIORITY               0x403
+#define DC_DISP_MEM_HIGH_PRIORITY_TIMER         0x404
+#define DC_DISP_DISP_TIMING_OPTIONS             0x405
+#define  VSYNC_H_POSITION(x)            ((x) & 0xfff)
+#define DC_DISP_REF_TO_SYNC                     0x406
+#define DC_DISP_SYNC_WIDTH                      0x407
+#define DC_DISP_BACK_PORCH                      0x408
+#define DC_DISP_DISP_ACTIVE                     0x409
+#define DC_DISP_FRONT_PORCH                     0x40a
+#define DC_DISP_H_PULSE0_CONTROL                0x40b
+#define DC_DISP_H_PULSE0_POSITION_A             0x40c
+#define DC_DISP_H_PULSE0_POSITION_B             0x40d
+#define DC_DISP_H_PULSE0_POSITION_C             0x40e
+#define DC_DISP_H_PULSE0_POSITION_D             0x40f
+#define DC_DISP_H_PULSE1_CONTROL                0x410
+#define DC_DISP_H_PULSE1_POSITION_A             0x411
+#define DC_DISP_H_PULSE1_POSITION_B             0x412
+#define DC_DISP_H_PULSE1_POSITION_C             0x413
+#define DC_DISP_H_PULSE1_POSITION_D             0x414
+#define DC_DISP_H_PULSE2_CONTROL                0x415
+#define DC_DISP_H_PULSE2_POSITION_A             0x416
+#define DC_DISP_H_PULSE2_POSITION_B             0x417
+#define DC_DISP_H_PULSE2_POSITION_C             0x418
+#define DC_DISP_H_PULSE2_POSITION_D             0x419
+#define DC_DISP_V_PULSE0_CONTROL                0x41a
+#define DC_DISP_V_PULSE0_POSITION_A             0x41b
+#define DC_DISP_V_PULSE0_POSITION_B             0x41c
+#define DC_DISP_V_PULSE0_POSITION_C             0x41d
+#define DC_DISP_V_PULSE1_CONTROL                0x41e
+#define DC_DISP_V_PULSE1_POSITION_A             0x41f
+#define DC_DISP_V_PULSE1_POSITION_B             0x420
+#define DC_DISP_V_PULSE1_POSITION_C             0x421
+#define DC_DISP_V_PULSE2_CONTROL                0x422
+#define DC_DISP_V_PULSE2_POSITION_A             0x423
+#define DC_DISP_V_PULSE3_CONTROL                0x424
+#define DC_DISP_V_PULSE3_POSITION_A             0x425
+#define DC_DISP_M0_CONTROL                      0x426
+#define DC_DISP_M1_CONTROL                      0x427
+#define DC_DISP_DI_CONTROL                      0x428
+#define DC_DISP_PP_CONTROL                      0x429
+#define DC_DISP_PP_SELECT_A                     0x42a
+#define DC_DISP_PP_SELECT_B                     0x42b
+#define DC_DISP_PP_SELECT_C                     0x42c
+#define DC_DISP_PP_SELECT_D                     0x42d
+#define  PULSE_MODE_NORMAL              (0 << 3)
+#define  PULSE_MODE_ONE_CLOCK           (1 << 3)
+#define  PULSE_POLARITY_HIGH            (0 << 4)
+#define  PULSE_POLARITY_LOW             (1 << 4)
+#define  PULSE_QUAL_ALWAYS              (0 << 6)
+#define  PULSE_QUAL_VACTIVE             (2 << 6)
+#define  PULSE_QUAL_VACTIVE1            (3 << 6)
+#define  PULSE_LAST_START_A             (0 << 8)
+#define  PULSE_LAST_END_A               (1 << 8)
+#define  PULSE_LAST_START_B             (2 << 8)
+#define  PULSE_LAST_END_B               (3 << 8)
+#define  PULSE_LAST_START_C             (4 << 8)
+#define  PULSE_LAST_END_C               (5 << 8)
+#define  PULSE_LAST_START_D             (6 << 8)
+#define  PULSE_LAST_END_D               (7 << 8)
+#define  PULSE_START(x)                 ((x) & 0xfff)
+#define  PULSE_END(x)                   (((x) & 0xfff) << 16)
+#define DC_DISP_DISP_CLOCK_CONTROL              0x42e
+#define  PIXEL_CLK_DIVIDER_PCD1         (0 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD1H        (1 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD2         (2 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD3         (3 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD4         (4 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD6         (5 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD8         (6 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD9         (7 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD12        (8 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD16        (9 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD18        (10 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD24        (11 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD13        (12 << 8)
+#define  SHIFT_CLK_DIVIDER(x)           ((x) & 0xff)
+#define DC_DISP_DISP_INTERFACE_CONTROL          0x42f
+#define  DISP_DATA_FORMAT_DF1P1C        (0 << 0)
+#define  DISP_DATA_FORMAT_DF1P2C24B     (1 << 0)
+#define  DISP_DATA_FORMAT_DF1P2C18B     (2 << 0)
+#define  DISP_DATA_FORMAT_DF1P2C16B     (3 << 0)
+#define  DISP_DATA_FORMAT_DF2S          (5 << 0)
+#define  DISP_DATA_FORMAT_DF3S          (6 << 0)
+#define  DISP_DATA_FORMAT_DFSPI         (7 << 0)
+#define  DISP_DATA_FORMAT_DF1P3C24B     (8 << 0)
+#define  DISP_DATA_FORMAT_DF1P3C18B     (9 << 0)
+#define  DISP_DATA_ALIGNMENT_MSB        (0 << 8)
+#define  DISP_DATA_ALIGNMENT_LSB        (1 << 8)
+#define  DISP_DATA_ORDER_RED_BLUE       (0 << 9)
+#define  DISP_DATA_ORDER_BLUE_RED       (1 << 9)
+#define DC_DISP_DISP_COLOR_CONTROL              0x430
+#define  BASE_COLOR_SIZE666             (0 << 0)
+#define  BASE_COLOR_SIZE111             (1 << 0)
+#define  BASE_COLOR_SIZE222             (2 << 0)
+#define  BASE_COLOR_SIZE333             (3 << 0)
+#define  BASE_COLOR_SIZE444             (4 << 0)
+#define  BASE_COLOR_SIZE555             (5 << 0)
+#define  BASE_COLOR_SIZE565             (6 << 0)
+#define  BASE_COLOR_SIZE332             (7 << 0)
+#define  BASE_COLOR_SIZE888             (8 << 0)
+#define  DITHER_CONTROL_DISABLE         (0 << 8)
+#define  DITHER_CONTROL_ORDERED         (2 << 8)
+#define  DITHER_CONTROL_ERRDIFF         (3 << 8)
+#define DC_DISP_SHIFT_CLOCK_OPTIONS             0x431
+#define DC_DISP_DATA_ENABLE_OPTIONS             0x432
+#define   DE_SELECT_ACTIVE_BLANK        0x0
+#define   DE_SELECT_ACTIVE              0x1
+#define   DE_SELECT_ACTIVE_IS           0x2
+#define   DE_CONTROL_ONECLK             (0 << 2)
+#define   DE_CONTROL_NORMAL             (1 << 2)
+#define   DE_CONTROL_EARLY_EXT          (2 << 2)
+#define   DE_CONTROL_EARLY              (3 << 2)
+#define   DE_CONTROL_ACTIVE_BLANK       (4 << 2)
+#define DC_DISP_SERIAL_INTERFACE_OPTIONS        0x433
+#define DC_DISP_LCD_SPI_OPTIONS                 0x434
+#define DC_DISP_BORDER_COLOR                    0x435
+#define DC_DISP_COLOR_KEY0_LOWER                0x436
+#define DC_DISP_COLOR_KEY0_UPPER                0x437
+#define DC_DISP_COLOR_KEY1_LOWER                0x438
+#define DC_DISP_COLOR_KEY1_UPPER                0x439
+#define DC_DISP_CURSOR_FOREGROUND               0x43c
+#define DC_DISP_CURSOR_BACKGROUND               0x43d
+#define   CURSOR_COLOR(_r, _g, _b) ((_r) | ((_g) << 8) | ((_b) << 16))
+#define DC_DISP_CURSOR_START_ADDR               0x43e
+#define DC_DISP_CURSOR_START_ADDR_NS            0x43f
+#define   CURSOR_START_ADDR_MASK        (((1 << 22) - 1) << 10)
+#define   CURSOR_START_ADDR(_addr)      ((_addr) >> 10)
+#define   CURSOR_SIZE_64                (1 << 24)
+#define DC_DISP_CURSOR_POSITION                 0x440
+#define   CURSOR_POSITION(_x, _y)               \
+        (((_x) & ((1 << 16) - 1)) |             \
+        (((_y) & ((1 << 16) - 1)) << 16))
+#define DC_DISP_CURSOR_POSITION_NS              0x441
+#define DC_DISP_INIT_SEQ_CONTROL                0x442
+#define DC_DISP_SPI_INIT_SEQ_DATA_A             0x443
+#define DC_DISP_SPI_INIT_SEQ_DATA_B             0x444
+#define DC_DISP_SPI_INIT_SEQ_DATA_C             0x445
+#define DC_DISP_SPI_INIT_SEQ_DATA_D             0x446
+#define DC_DISP_DC_MCCIF_FIFOCTRL               0x480
+#define DC_DISP_MCCIF_DISPLAY0A_HYST            0x481
+#define DC_DISP_MCCIF_DISPLAY0B_HYST            0x482
+#define DC_DISP_MCCIF_DISPLAY0C_HYST            0x483
+#define DC_DISP_MCCIF_DISPLAY1B_HYST            0x484
+#define DC_DISP_DAC_CRT_CTRL                    0x4c0
+#define DC_DISP_DISP_MISC_CONTROL               0x4c1
+#define DC_WIN_COLOR_PALETTE(x)                 (0x500 + (x))
+#define DC_WIN_PALETTE_COLOR_EXT                0x600
+#define DC_WIN_H_FILTER_P(x)                    (0x601 + (x))
+#define DC_WIN_CSC_YOF                          0x611
+#define DC_WIN_CSC_KYRGB                        0x612
+#define DC_WIN_CSC_KUR                          0x613
+#define DC_WIN_CSC_KVR                          0x614
+#define DC_WIN_CSC_KUG                          0x615
+#define DC_WIN_CSC_KVG                          0x616
+#define DC_WIN_CSC_KUB                          0x617
+#define DC_WIN_CSC_KVB                          0x618
+#define DC_WIN_V_FILTER_P(x)                    (0x619 + (x))
+#define DC_WIN_WIN_OPTIONS                      0x700
+#define  H_DIRECTION_INCREMENT          (0 << 0)
+#define  H_DIRECTION_DECREMENT          (1 << 0)
+#define  V_DIRECTION_INCREMENT          (0 << 2)
+#define  V_DIRECTION_DECREMENT          (1 << 2)
+#define  COLOR_EXPAND                   (1 << 6)
+#define  H_FILTER_ENABLE                (1 << 8)
+#define  V_FILTER_ENABLE                (1 << 10)
+#define  CP_ENABLE                      (1 << 16)
+#define  CSC_ENABLE                     (1 << 18)
+#define  DV_ENABLE                      (1 << 20)
+#define  WIN_ENABLE                     (1 << 30)
+#define DC_WIN_BYTE_SWAP                        0x701
+#define  BYTE_SWAP_NOSWAP               0
+#define  BYTE_SWAP_SWAP2                1
+#define  BYTE_SWAP_SWAP4                2
+#define  BYTE_SWAP_SWAP4HW              3
+#define DC_WIN_BUFFER_CONTROL                   0x702
+#define  BUFFER_CONTROL_HOST            0
+#define  BUFFER_CONTROL_VI              1
+#define  BUFFER_CONTROL_EPP             2
+#define  BUFFER_CONTROL_MPEGE           3
+#define  BUFFER_CONTROL_SB2D            4
+#define DC_WIN_COLOR_DEPTH                      0x703
+#define DC_WIN_POSITION                         0x704
+#define  H_POSITION(x)          (((x) & 0xfff) << 0)
+#define  V_POSITION(x)          (((x) & 0xfff) << 16)
+#define DC_WIN_SIZE                             0x705
+#define  H_SIZE(x)              (((x) & 0xfff) << 0)
+#define  V_SIZE(x)              (((x) & 0xfff) << 16)
+#define DC_WIN_PRESCALED_SIZE                   0x706
+#define  H_PRESCALED_SIZE(x)    (((x) & 0x3fff) << 0)
+#define  V_PRESCALED_SIZE(x)    (((x) & 0xfff) << 16)
+#define DC_WIN_H_INITIAL_DDA                    0x707
+#define DC_WIN_V_INITIAL_DDA                    0x708
+#define DC_WIN_DDA_INCREMENT                    0x709
+#define  H_DDA_INC(x)           (((x) & 0xffff) << 0)
+#define  V_DDA_INC(x)           (((x) & 0xffff) << 16)
+#define DC_WIN_LINE_STRIDE                      0x70a
+#define  LINE_STRIDE(x)         (x)
+#define  UV_LINE_STRIDE(x)      (((x) & 0xffff) << 16)
+#define DC_WIN_BUF_STRIDE                       0x70b
+#define DC_WIN_UV_BUF_STRIDE                    0x70c
+#define DC_WIN_BUFFER_ADDR_MODE                 0x70d
+#define  DC_WIN_BUFFER_ADDR_MODE_LINEAR         (0 << 0)
+#define  DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV      (0 << 16)
+#define  DC_WIN_BUFFER_ADDR_MODE_TILE           (1 << 0)
+#define  DC_WIN_BUFFER_ADDR_MODE_TILE_UV        (1 << 16)
+#define DC_WIN_DV_CONTROL                       0x70e
+#define DC_WIN_BLEND_NOKEY                      0x70f
+#define DC_WIN_BLEND_1WIN                       0x710
+#define DC_WIN_BLEND_2WIN_X                     0x711
+#define DC_WIN_BLEND_2WIN_Y                     0x712
+#define DC_WIN_BLEND_3WIN_XY                    0x713
+#define  CKEY_NOKEY                     (0 << 0)
+#define  CKEY_KEY0                      (1 << 0)
+#define  CKEY_KEY1                      (2 << 0)
+#define  CKEY_KEY01                     (3 << 0)
+#define  BLEND_CONTROL_FIX              (0 << 2)
+#define  BLEND_CONTROL_ALPHA            (1 << 2)
+#define  BLEND_CONTROL_DEPENDANT        (2 << 2)
+#define  BLEND_CONTROL_PREMULT          (3 << 2)
+#define  BLEND_WEIGHT0(x)               (((x) & 0xff) << 8)
+#define  BLEND_WEIGHT1(x)               (((x) & 0xff) << 16)
+#define  BLEND(key, control, weight0, weight1)                  \
+          (CKEY_ ## key | BLEND_CONTROL_ ## control |           \
+           BLEND_WEIGHT0(weight0) | BLEND_WEIGHT1(weight1))
+#define DC_WIN_HP_FETCH_CONTROL                 0x714
+#define DC_WINBUF_START_ADDR                    0x800
+#define DC_WINBUF_START_ADDR_NS                 0x801
+#define DC_WINBUF_START_ADDR_U                  0x802
+#define DC_WINBUF_START_ADDR_U_NS               0x803
+#define DC_WINBUF_START_ADDR_V                  0x804
+#define DC_WINBUF_START_ADDR_V_NS               0x805
+#define DC_WINBUF_ADDR_H_OFFSET                 0x806
+#define DC_WINBUF_ADDR_H_OFFSET_NS              0x807
+#define DC_WINBUF_ADDR_V_OFFSET                 0x808
+#define DC_WINBUF_ADDR_V_OFFSET_NS              0x809
+#define DC_WINBUF_UFLOW_STATUS                  0x80a
+/* direct versions of DC_WINBUF_UFLOW_STATUS */
+#define DC_WINBUF_AD_UFLOW_STATUS               0xbca
+#define DC_WINBUF_BD_UFLOW_STATUS               0xdca
+#define DC_WINBUF_CD_UFLOW_STATUS               0xfca
+#define DC_DISP_SD_CONTROL                      0x4c2
+#define  SD_ENABLE_NORMAL               (1 << 0)
+#define  SD_ENABLE_ONESHOT              (2 << 0)
+#define  SD_USE_VID_LUMA                (1 << 2)
+#define  SD_BIN_WIDTH_ONE               (0 << 3)
+#define  SD_BIN_WIDTH_TWO               (1 << 3)
+#define  SD_BIN_WIDTH_FOUR              (2 << 3)
+#define  SD_BIN_WIDTH_EIGHT             (3 << 3)
+#define  SD_BIN_WIDTH_MASK              (3 << 3)
+#define  SD_AGGRESSIVENESS(x)           (((x) & 0x7) << 5)
+#define  SD_HW_UPDATE_DLY(x)            (((x) & 0x3) << 8)
+#define  SD_ONESHOT_ENABLE              (1 << 10)
+#define  SD_CORRECTION_MODE_AUTO        (0 << 11)
+#define  SD_CORRECTION_MODE_MAN         (1 << 11)
+#define NUM_BIN_WIDTHS 4
+#define STEPS_PER_AGG_LVL 64
+#define STEPS_PER_AGG_CHG_LOG2 5
+#define STEPS_PER_AGG_CHG (1<<STEPS_PER_AGG_CHG_LOG2)
+#define ADJ_PHASE_STEP 8
+#define K_STEP 4
+#define DC_DISP_SD_CSC_COEFF                    0x4c3
+#define  SD_CSC_COEFF_R(x)              (((x) & 0xf) << 4)
+#define  SD_CSC_COEFF_G(x)              (((x) & 0xf) << 12)
+#define  SD_CSC_COEFF_B(x)              (((x) & 0xf) << 20)
+#define DC_DISP_SD_LUT(i)                       (0x4c4 + i)
+#define DC_DISP_SD_LUT_NUM                      9
+#define  SD_LUT_R(x)                    (((x) & 0xff) << 0)
+#define  SD_LUT_G(x)                    (((x) & 0xff) << 8)
+#define  SD_LUT_B(x)                    (((x) & 0xff) << 16)
+#define DC_DISP_SD_FLICKER_CONTROL              0x4cd
+#define  SD_FC_TIME_LIMIT(x)            (((x) & 0xff) << 0)
+#define  SD_FC_THRESHOLD(x)             (((x) & 0xff) << 8)
+#define DC_DISP_SD_PIXEL_COUNT                  0x4ce
+#define DC_DISP_SD_HISTOGRAM(i)                 (0x4cf + i)
+#define DC_DISP_SD_HISTOGRAM_NUM                8
+#define  SD_HISTOGRAM_BIN_0(val)        (((val) & (0xff << 0)) >> 0)
+#define  SD_HISTOGRAM_BIN_1(val)        (((val) & (0xff << 8)) >> 8)
+#define  SD_HISTOGRAM_BIN_2(val)        (((val) & (0xff << 16)) >> 16)
+#define  SD_HISTOGRAM_BIN_3(val)        (((val) & (0xff << 24)) >> 24)
+#define DC_DISP_SD_BL_PARAMETERS                0x4d7
+#define  SD_BLP_TIME_CONSTANT(x)        (((x) & 0x7ff) << 0)
+#define  SD_BLP_STEP(x)                 (((x) & 0xff) << 16)
+#define DC_DISP_SD_BL_TF(i)                     (0x4d8 + i)
+#define DC_DISP_SD_BL_TF_NUM                    4
+#define  SD_BL_TF_POINT_0(x)            (((x) & 0xff) << 0)
+#define  SD_BL_TF_POINT_1(x)            (((x) & 0xff) << 8)
+#define  SD_BL_TF_POINT_2(x)            (((x) & 0xff) << 16)
+#define  SD_BL_TF_POINT_3(x)            (((x) & 0xff) << 24)
+#define DC_DISP_SD_BL_CONTROL                   0x4dc
+#define  SD_BLC_MODE_MAN                (0 << 0)
+#define  SD_BLC_MODE_AUTO               (1 << 1)
+#define  SD_BLC_BRIGHTNESS(val)         (((val) & (0xff << 8)) >> 8)
+#define DC_DISP_SD_HW_K_VALUES                  0x4dd
+#define  SD_HW_K_R(val)                 (((val) & (0x3ff << 0)) >> 0)
+#define  SD_HW_K_G(val)                 (((val) & (0x3ff << 10)) >> 10)
+#define  SD_HW_K_B(val)                 (((val) & (0x3ff << 20)) >> 20)
+#define DC_DISP_SD_MAN_K_VALUES                 0x4de
+#define  SD_MAN_K_R(x)                  (((x) & 0x3ff) << 0)
+#define  SD_MAN_K_G(x)                  (((x) & 0x3ff) << 10)
+#define  SD_MAN_K_B(x)                  (((x) & 0x3ff) << 20)
+#define  NUM_AGG_PRI_LVLS               4
+#define  SD_AGG_PRI_LVL(x)              ((x) >> 3)
+#define  SD_GET_AGG(x)                  ((x) & 0x7)
+#endif
author	Jonathan Herman <hermanjl@cs.unc.edu>	2013-01-22 10:38:37 -0500
committer	Jonathan Herman <hermanjl@cs.unc.edu>	2013-01-22 10:38:37 -0500
commit	fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
tree	a57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/video/tegra/dc/dc_reg.h
parent	8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)

diff --git a/drivers/video/tegra/dc/dc_reg.h b/drivers/video/tegra/dc/dc_reg.h new file mode 100644 index 00000000000..22379a19408 --- /dev/null +++ b/drivers/video/tegra/dc/dc_reg.h
@@ -0,0 +1,555 @@
	1	/*
	2	* drivers/video/tegra/dc/dc_reg.h
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	* Author: Erik Gilling <konkers@android.com>
	6	*
	7	* Copyright (C) 2010-2011 NVIDIA Corporation
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#ifndef __DRIVERS_VIDEO_TEGRA_DC_DC_REG_H
	21	#define __DRIVERS_VIDEO_TEGRA_DC_DC_REG_H
	22
	23	#define DC_CMD_GENERAL_INCR_SYNCPT 0x000
	24	#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
	25	#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
	26	#define DC_CMD_WIN_A_INCR_SYNCPT 0x008
	27	#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
	28	#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
	29	#define DC_CMD_WIN_B_INCR_SYNCPT 0x010
	30	#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
	31	#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
	32	#define DC_CMD_WIN_C_INCR_SYNCPT 0x018
	33	#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
	34	#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
	35	#define DC_CMD_CONT_SYNCPT_VSYNC 0x028
	36	#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
	37	#define MSF_POLARITY_HIGH (0 << 0)
	38	#define MSF_POLARITY_LOW (1 << 0)
	39	#define MSF_DISABLE (0 << 1)
	40	#define MSF_ENABLE (1 << 1)
	41	#define MSF_LSPI (0 << 2)
	42	#define MSF_LDC (1 << 2)
	43	#define MSF_LSDI (2 << 2)
	44
	45	#define DC_CMD_DISPLAY_COMMAND 0x032
	46	#define DISP_COMMAND_RAISE (1 << 0)
	47	#define DISP_CTRL_MODE_STOP (0 << 5)
	48	#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
	49	#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
	50	#define DISP_COMMAND_RAISE_VECTOR(x) (((x) & 0x1f) << 22)
	51	#define DISP_COMMAND_RAISE_CHANNEL_ID(x) (((x) & 0xf) << 27)
	52
	53	#define DC_CMD_SIGNAL_RAISE 0x033
	54	#define DC_CMD_DISPLAY_POWER_CONTROL 0x036
	55	#define PW0_ENABLE (1 << 0)
	56	#define PW1_ENABLE (1 << 2)
	57	#define PW2_ENABLE (1 << 4)
	58	#define PW3_ENABLE (1 << 6)
	59	#define PW4_ENABLE (1 << 8)
	60	#define PM0_ENABLE (1 << 16)
	61	#define PM1_ENABLE (1 << 18)
	62	#define SPI_ENABLE (1 << 24)
	63	#define HSPI_ENABLE (1 << 25)
	64
	65	#define DC_CMD_INT_STATUS 0x037
	66	#define DC_CMD_INT_MASK 0x038
	67	#define DC_CMD_INT_ENABLE 0x039
	68	#define DC_CMD_INT_TYPE 0x03a
	69	#define DC_CMD_INT_POLARITY 0x03b
	70	#define CTXSW_INT (1 << 0)
	71	#define FRAME_END_INT (1 << 1)
	72	#define V_BLANK_INT (1 << 2)
	73	#define H_BLANK_INT (1 << 3)
	74	#define V_PULSE3_INT (1 << 4)
	75	#define SPI_BUSY_INT (1 << 7)
	76	#define WIN_A_UF_INT (1 << 8)
	77	#define WIN_B_UF_INT (1 << 9)
	78	#define WIN_C_UF_INT (1 << 10)
	79	#define MSF_INT (1 << 12)
	80	#define SSF_INT (1 << 13)
	81	#define WIN_A_OF_INT (1 << 14)
	82	#define WIN_B_OF_INT (1 << 15)
	83	#define WIN_C_OF_INT (1 << 16)
	84	#define GPIO_0_INT (1 << 18)
	85	#define GPIO_1_INT (1 << 19)
	86	#define GPIO_2_INT (1 << 20)
	87
	88	#define DC_CMD_SIGNAL_RAISE1 0x03c
	89	#define DC_CMD_SIGNAL_RAISE2 0x03d
	90	#define DC_CMD_SIGNAL_RAISE3 0x03e
	91	#define DC_CMD_STATE_ACCESS 0x040
	92	#define READ_MUX_ASSEMBLY (0 << 0)
	93	#define READ_MUX_ACTIVE (1 << 0)
	94	#define WRITE_MUX_ASSEMBLY (0 << 2)
	95	#define WRITE_MUX_ACTIVE (1 << 2)
	96
	97	#define DC_CMD_STATE_CONTROL 0x041
	98	#define GENERAL_ACT_REQ (1 << 0)
	99	#define WIN_A_ACT_REQ (1 << 1)
	100	#define WIN_B_ACT_REQ (1 << 2)
	101	#define WIN_C_ACT_REQ (1 << 3)
	102	#define GENERAL_UPDATE (1 << 8)
	103	#define WIN_A_UPDATE (1 << 9)
	104	#define WIN_B_UPDATE (1 << 10)
	105	#define WIN_C_UPDATE (1 << 11)
	106	#define NC_HOST_TRIG (1 << 24)
	107
	108	#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
	109	#define WINDOW_A_SELECT (1 << 4)
	110	#define WINDOW_B_SELECT (1 << 5)
	111	#define WINDOW_C_SELECT (1 << 6)
	112
	113	#define DC_CMD_REG_ACT_CONTROL 0x043
	114
	115	#define DC_COM_CRC_CONTROL 0x300
	116	#define CRC_ALWAYS_ENABLE (1 << 3)
	117	#define CRC_ALWAYS_DISABLE (0 << 3)
	118	#define CRC_INPUT_DATA_ACTIVE_DATA (1 << 2)
	119	#define CRC_INPUT_DATA_FULL_FRAME (0 << 2)
	120	#define CRC_WAIT_TWO_VSYNC (1 << 1)
	121	#define CRC_WAIT_ONE_VSYNC (0 << 1)
	122	#define CRC_ENABLE_ENABLE (1 << 0)
	123	#define CRC_ENABLE_DISABLE (0 << 0)
	124	#define DC_COM_CRC_CHECKSUM 0x301
	125	#define DC_COM_PIN_OUTPUT_ENABLE0 0x302
	126	#define DC_COM_PIN_OUTPUT_ENABLE1 0x303
	127	#define DC_COM_PIN_OUTPUT_ENABLE2 0x304
	128	#define DC_COM_PIN_OUTPUT_ENABLE3 0x305
	129	#define PIN_OUTPUT_LSPI_OUTPUT_EN (1 << 8)
	130	#define PIN_OUTPUT_LSPI_OUTPUT_DIS (1 << 8)
	131	#define DC_COM_PIN_OUTPUT_POLARITY0 0x306
	132
	133	#define DC_COM_PIN_OUTPUT_POLARITY1 0x307
	134	#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
	135	#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
	136	#define LSC0_OUTPUT_POLARITY_LOW (1 << 24)
	137
	138	#define DC_COM_PIN_OUTPUT_POLARITY2 0x308
	139
	140	#define DC_COM_PIN_OUTPUT_POLARITY3 0x309
	141	#define LSPI_OUTPUT_POLARITY_LOW (1 << 8)
	142
	143	#define DC_COM_PIN_OUTPUT_DATA0 0x30a
	144	#define DC_COM_PIN_OUTPUT_DATA1 0x30b
	145	#define DC_COM_PIN_OUTPUT_DATA2 0x30c
	146	#define DC_COM_PIN_OUTPUT_DATA3 0x30d
	147	#define DC_COM_PIN_INPUT_ENABLE0 0x30e
	148	#define DC_COM_PIN_INPUT_ENABLE1 0x30f
	149	#define DC_COM_PIN_INPUT_ENABLE2 0x310
	150	#define DC_COM_PIN_INPUT_ENABLE3 0x311
	151	#define PIN_INPUT_LSPI_INPUT_EN (1 << 8)
	152	#define PIN_INPUT_LSPI_INPUT_DIS (1 << 8)
	153	#define DC_COM_PIN_INPUT_DATA0 0x312
	154	#define DC_COM_PIN_INPUT_DATA1 0x313
	155	#define DC_COM_PIN_OUTPUT_SELECT0 0x314
	156	#define DC_COM_PIN_OUTPUT_SELECT1 0x315
	157	#define DC_COM_PIN_OUTPUT_SELECT2 0x316
	158	#define DC_COM_PIN_OUTPUT_SELECT3 0x317
	159	#define DC_COM_PIN_OUTPUT_SELECT4 0x318
	160	#define DC_COM_PIN_OUTPUT_SELECT5 0x319
	161	#define DC_COM_PIN_OUTPUT_SELECT6 0x31a
	162
	163	#define PIN5_LM1_LCD_M1_OUTPUT_MASK (7 << 4)
	164	#define PIN5_LM1_LCD_M1_OUTPUT_M1 (0 << 4)
	165	#define PIN5_LM1_LCD_M1_OUTPUT_LD21 (2 << 4)
	166	#define PIN5_LM1_LCD_M1_OUTPUT_PM1 (3 << 4)
	167
	168	#define PIN1_LHS_OUTPUT (1 << 30)
	169	#define PIN1_LVS_OUTPUT (1 << 28)
	170
	171	#define DC_COM_PIN_MISC_CONTROL 0x31b
	172	#define DC_COM_PM0_CONTROL 0x31c
	173	#define DC_COM_PM0_DUTY_CYCLE 0x31d
	174	#define DC_COM_PM1_CONTROL 0x31e
	175	#define DC_COM_PM1_DUTY_CYCLE 0x31f
	176
	177	#define PM_PERIOD_SHIFT 18
	178	#define PM_CLK_DIVIDER_SHIFT 4
	179
	180	#define DC_COM_SPI_CONTROL 0x320
	181	#define DC_COM_SPI_START_BYTE 0x321
	182	#define DC_COM_HSPI_WRITE_DATA_AB 0x322
	183	#define DC_COM_HSPI_WRITE_DATA_CD 0x323
	184	#define DC_COM_HSPI_CS_DC 0x324
	185	#define DC_COM_SCRATCH_REGISTER_A 0x325
	186	#define DC_COM_SCRATCH_REGISTER_B 0x326
	187	#define DC_COM_GPIO_CTRL 0x327
	188	#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
	189	#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
	190
	191	#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
	192	#define H_PULSE_0_ENABLE (1 << 8)
	193	#define H_PULSE_1_ENABLE (1 << 10)
	194	#define H_PULSE_2_ENABLE (1 << 12)
	195	#define V_PULSE_0_ENABLE (1 << 16)
	196	#define V_PULSE_1_ENABLE (1 << 18)
	197	#define V_PULSE_2_ENABLE (1 << 19)
	198	#define V_PULSE_3_ENABLE (1 << 20)
	199	#define M0_ENABLE (1 << 24)
	200	#define M1_ENABLE (1 << 26)
	201
	202	#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
	203	#define DI_ENABLE (1 << 16)
	204	#define PP_ENABLE (1 << 18)
	205
	206	#define DC_DISP_DISP_WIN_OPTIONS 0x402
	207	#define CURSOR_ENABLE (1 << 16)
	208	#define TVO_ENABLE (1 << 28)
	209	#define DSI_ENABLE (1 << 29)
	210	#define HDMI_ENABLE (1 << 30)
	211
	212	#define DC_DISP_MEM_HIGH_PRIORITY 0x403
	213	#define DC_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
	214	#define DC_DISP_DISP_TIMING_OPTIONS 0x405
	215	#define VSYNC_H_POSITION(x) ((x) & 0xfff)
	216
	217	#define DC_DISP_REF_TO_SYNC 0x406
	218	#define DC_DISP_SYNC_WIDTH 0x407
	219	#define DC_DISP_BACK_PORCH 0x408
	220	#define DC_DISP_DISP_ACTIVE 0x409
	221	#define DC_DISP_FRONT_PORCH 0x40a
	222	#define DC_DISP_H_PULSE0_CONTROL 0x40b
	223	#define DC_DISP_H_PULSE0_POSITION_A 0x40c
	224	#define DC_DISP_H_PULSE0_POSITION_B 0x40d
	225	#define DC_DISP_H_PULSE0_POSITION_C 0x40e
	226	#define DC_DISP_H_PULSE0_POSITION_D 0x40f
	227	#define DC_DISP_H_PULSE1_CONTROL 0x410
	228	#define DC_DISP_H_PULSE1_POSITION_A 0x411
	229	#define DC_DISP_H_PULSE1_POSITION_B 0x412
	230	#define DC_DISP_H_PULSE1_POSITION_C 0x413
	231	#define DC_DISP_H_PULSE1_POSITION_D 0x414
	232	#define DC_DISP_H_PULSE2_CONTROL 0x415
	233	#define DC_DISP_H_PULSE2_POSITION_A 0x416
	234	#define DC_DISP_H_PULSE2_POSITION_B 0x417
	235	#define DC_DISP_H_PULSE2_POSITION_C 0x418
	236	#define DC_DISP_H_PULSE2_POSITION_D 0x419
	237	#define DC_DISP_V_PULSE0_CONTROL 0x41a
	238	#define DC_DISP_V_PULSE0_POSITION_A 0x41b
	239	#define DC_DISP_V_PULSE0_POSITION_B 0x41c
	240	#define DC_DISP_V_PULSE0_POSITION_C 0x41d
	241	#define DC_DISP_V_PULSE1_CONTROL 0x41e
	242	#define DC_DISP_V_PULSE1_POSITION_A 0x41f
	243	#define DC_DISP_V_PULSE1_POSITION_B 0x420
	244	#define DC_DISP_V_PULSE1_POSITION_C 0x421
	245	#define DC_DISP_V_PULSE2_CONTROL 0x422
	246	#define DC_DISP_V_PULSE2_POSITION_A 0x423
	247	#define DC_DISP_V_PULSE3_CONTROL 0x424
	248	#define DC_DISP_V_PULSE3_POSITION_A 0x425
	249	#define DC_DISP_M0_CONTROL 0x426
	250	#define DC_DISP_M1_CONTROL 0x427
	251	#define DC_DISP_DI_CONTROL 0x428
	252	#define DC_DISP_PP_CONTROL 0x429
	253	#define DC_DISP_PP_SELECT_A 0x42a
	254	#define DC_DISP_PP_SELECT_B 0x42b
	255	#define DC_DISP_PP_SELECT_C 0x42c
	256	#define DC_DISP_PP_SELECT_D 0x42d
	257
	258	#define PULSE_MODE_NORMAL (0 << 3)
	259	#define PULSE_MODE_ONE_CLOCK (1 << 3)
	260	#define PULSE_POLARITY_HIGH (0 << 4)
	261	#define PULSE_POLARITY_LOW (1 << 4)
	262	#define PULSE_QUAL_ALWAYS (0 << 6)
	263	#define PULSE_QUAL_VACTIVE (2 << 6)
	264	#define PULSE_QUAL_VACTIVE1 (3 << 6)
	265	#define PULSE_LAST_START_A (0 << 8)
	266	#define PULSE_LAST_END_A (1 << 8)
	267	#define PULSE_LAST_START_B (2 << 8)
	268	#define PULSE_LAST_END_B (3 << 8)
	269	#define PULSE_LAST_START_C (4 << 8)
	270	#define PULSE_LAST_END_C (5 << 8)
	271	#define PULSE_LAST_START_D (6 << 8)
	272	#define PULSE_LAST_END_D (7 << 8)
	273
	274	#define PULSE_START(x) ((x) & 0xfff)
	275	#define PULSE_END(x) (((x) & 0xfff) << 16)
	276
	277	#define DC_DISP_DISP_CLOCK_CONTROL 0x42e
	278	#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
	279	#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
	280	#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
	281	#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
	282	#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
	283	#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
	284	#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
	285	#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
	286	#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
	287	#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
	288	#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
	289	#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
	290	#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
	291	#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
	292
	293	#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
	294	#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
	295	#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
	296	#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
	297	#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
	298	#define DISP_DATA_FORMAT_DF2S (5 << 0)
	299	#define DISP_DATA_FORMAT_DF3S (6 << 0)
	300	#define DISP_DATA_FORMAT_DFSPI (7 << 0)
	301	#define DISP_DATA_FORMAT_DF1P3C24B (8 << 0)
	302	#define DISP_DATA_FORMAT_DF1P3C18B (9 << 0)
	303	#define DISP_DATA_ALIGNMENT_MSB (0 << 8)
	304	#define DISP_DATA_ALIGNMENT_LSB (1 << 8)
	305	#define DISP_DATA_ORDER_RED_BLUE (0 << 9)
	306	#define DISP_DATA_ORDER_BLUE_RED (1 << 9)
	307
	308	#define DC_DISP_DISP_COLOR_CONTROL 0x430
	309	#define BASE_COLOR_SIZE666 (0 << 0)
	310	#define BASE_COLOR_SIZE111 (1 << 0)
	311	#define BASE_COLOR_SIZE222 (2 << 0)
	312	#define BASE_COLOR_SIZE333 (3 << 0)
	313	#define BASE_COLOR_SIZE444 (4 << 0)
	314	#define BASE_COLOR_SIZE555 (5 << 0)
	315	#define BASE_COLOR_SIZE565 (6 << 0)
	316	#define BASE_COLOR_SIZE332 (7 << 0)
	317	#define BASE_COLOR_SIZE888 (8 << 0)
	318
	319	#define DITHER_CONTROL_DISABLE (0 << 8)
	320	#define DITHER_CONTROL_ORDERED (2 << 8)
	321	#define DITHER_CONTROL_ERRDIFF (3 << 8)
	322
	323	#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
	324	#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
	325	#define DE_SELECT_ACTIVE_BLANK 0x0
	326	#define DE_SELECT_ACTIVE 0x1
	327	#define DE_SELECT_ACTIVE_IS 0x2
	328	#define DE_CONTROL_ONECLK (0 << 2)
	329	#define DE_CONTROL_NORMAL (1 << 2)
	330	#define DE_CONTROL_EARLY_EXT (2 << 2)
	331	#define DE_CONTROL_EARLY (3 << 2)
	332	#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
	333
	334	#define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
	335	#define DC_DISP_LCD_SPI_OPTIONS 0x434
	336	#define DC_DISP_BORDER_COLOR 0x435
	337	#define DC_DISP_COLOR_KEY0_LOWER 0x436
	338	#define DC_DISP_COLOR_KEY0_UPPER 0x437
	339	#define DC_DISP_COLOR_KEY1_LOWER 0x438
	340	#define DC_DISP_COLOR_KEY1_UPPER 0x439
	341
	342	#define DC_DISP_CURSOR_FOREGROUND 0x43c
	343	#define DC_DISP_CURSOR_BACKGROUND 0x43d
	344	#define CURSOR_COLOR(_r, _g, _b) ((_r) \| ((_g) << 8) \| ((_b) << 16))
	345
	346	#define DC_DISP_CURSOR_START_ADDR 0x43e
	347	#define DC_DISP_CURSOR_START_ADDR_NS 0x43f
	348	#define CURSOR_START_ADDR_MASK (((1 << 22) - 1) << 10)
	349	#define CURSOR_START_ADDR(_addr) ((_addr) >> 10)
	350	#define CURSOR_SIZE_64 (1 << 24)
	351
	352	#define DC_DISP_CURSOR_POSITION 0x440
	353	#define CURSOR_POSITION(_x, _y) \
	354	(((_x) & ((1 << 16) - 1)) \| \
	355	(((_y) & ((1 << 16) - 1)) << 16))
	356
	357	#define DC_DISP_CURSOR_POSITION_NS 0x441
	358	#define DC_DISP_INIT_SEQ_CONTROL 0x442
	359	#define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
	360	#define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
	361	#define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
	362	#define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
	363	#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
	364	#define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
	365	#define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
	366	#define DC_DISP_MCCIF_DISPLAY0C_HYST 0x483
	367	#define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
	368	#define DC_DISP_DAC_CRT_CTRL 0x4c0
	369	#define DC_DISP_DISP_MISC_CONTROL 0x4c1
	370
	371	#define DC_WIN_COLOR_PALETTE(x) (0x500 + (x))
	372
	373	#define DC_WIN_PALETTE_COLOR_EXT 0x600
	374	#define DC_WIN_H_FILTER_P(x) (0x601 + (x))
	375	#define DC_WIN_CSC_YOF 0x611
	376	#define DC_WIN_CSC_KYRGB 0x612
	377	#define DC_WIN_CSC_KUR 0x613
	378	#define DC_WIN_CSC_KVR 0x614
	379	#define DC_WIN_CSC_KUG 0x615
	380	#define DC_WIN_CSC_KVG 0x616
	381	#define DC_WIN_CSC_KUB 0x617
	382	#define DC_WIN_CSC_KVB 0x618
	383	#define DC_WIN_V_FILTER_P(x) (0x619 + (x))
	384	#define DC_WIN_WIN_OPTIONS 0x700
	385	#define H_DIRECTION_INCREMENT (0 << 0)
	386	#define H_DIRECTION_DECREMENT (1 << 0)
	387	#define V_DIRECTION_INCREMENT (0 << 2)
	388	#define V_DIRECTION_DECREMENT (1 << 2)
	389	#define COLOR_EXPAND (1 << 6)
	390	#define H_FILTER_ENABLE (1 << 8)
	391	#define V_FILTER_ENABLE (1 << 10)
	392	#define CP_ENABLE (1 << 16)
	393	#define CSC_ENABLE (1 << 18)
	394	#define DV_ENABLE (1 << 20)
	395	#define WIN_ENABLE (1 << 30)
	396
	397	#define DC_WIN_BYTE_SWAP 0x701
	398	#define BYTE_SWAP_NOSWAP 0
	399	#define BYTE_SWAP_SWAP2 1
	400	#define BYTE_SWAP_SWAP4 2
	401	#define BYTE_SWAP_SWAP4HW 3
	402
	403	#define DC_WIN_BUFFER_CONTROL 0x702
	404	#define BUFFER_CONTROL_HOST 0
	405	#define BUFFER_CONTROL_VI 1
	406	#define BUFFER_CONTROL_EPP 2
	407	#define BUFFER_CONTROL_MPEGE 3
	408	#define BUFFER_CONTROL_SB2D 4
	409
	410	#define DC_WIN_COLOR_DEPTH 0x703
	411
	412	#define DC_WIN_POSITION 0x704
	413	#define H_POSITION(x) (((x) & 0xfff) << 0)
	414	#define V_POSITION(x) (((x) & 0xfff) << 16)
	415
	416	#define DC_WIN_SIZE 0x705
	417	#define H_SIZE(x) (((x) & 0xfff) << 0)
	418	#define V_SIZE(x) (((x) & 0xfff) << 16)
	419
	420	#define DC_WIN_PRESCALED_SIZE 0x706
	421	#define H_PRESCALED_SIZE(x) (((x) & 0x3fff) << 0)
	422	#define V_PRESCALED_SIZE(x) (((x) & 0xfff) << 16)
	423
	424	#define DC_WIN_H_INITIAL_DDA 0x707
	425	#define DC_WIN_V_INITIAL_DDA 0x708
	426	#define DC_WIN_DDA_INCREMENT 0x709
	427	#define H_DDA_INC(x) (((x) & 0xffff) << 0)
	428	#define V_DDA_INC(x) (((x) & 0xffff) << 16)
	429
	430	#define DC_WIN_LINE_STRIDE 0x70a
	431	#define LINE_STRIDE(x) (x)
	432	#define UV_LINE_STRIDE(x) (((x) & 0xffff) << 16)
	433	#define DC_WIN_BUF_STRIDE 0x70b
	434	#define DC_WIN_UV_BUF_STRIDE 0x70c
	435	#define DC_WIN_BUFFER_ADDR_MODE 0x70d
	436	#define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
	437	#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
	438	#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
	439	#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
	440	#define DC_WIN_DV_CONTROL 0x70e
	441	#define DC_WIN_BLEND_NOKEY 0x70f
	442	#define DC_WIN_BLEND_1WIN 0x710
	443	#define DC_WIN_BLEND_2WIN_X 0x711
	444	#define DC_WIN_BLEND_2WIN_Y 0x712
	445	#define DC_WIN_BLEND_3WIN_XY 0x713
	446	#define CKEY_NOKEY (0 << 0)
	447	#define CKEY_KEY0 (1 << 0)
	448	#define CKEY_KEY1 (2 << 0)
	449	#define CKEY_KEY01 (3 << 0)
	450	#define BLEND_CONTROL_FIX (0 << 2)
	451	#define BLEND_CONTROL_ALPHA (1 << 2)
	452	#define BLEND_CONTROL_DEPENDANT (2 << 2)
	453	#define BLEND_CONTROL_PREMULT (3 << 2)
	454	#define BLEND_WEIGHT0(x) (((x) & 0xff) << 8)
	455	#define BLEND_WEIGHT1(x) (((x) & 0xff) << 16)
	456	#define BLEND(key, control, weight0, weight1) \
	457	(CKEY_ ## key \| BLEND_CONTROL_ ## control \| \
	458	BLEND_WEIGHT0(weight0) \| BLEND_WEIGHT1(weight1))
	459
	460
	461	#define DC_WIN_HP_FETCH_CONTROL 0x714
	462	#define DC_WINBUF_START_ADDR 0x800
	463	#define DC_WINBUF_START_ADDR_NS 0x801
	464	#define DC_WINBUF_START_ADDR_U 0x802
	465	#define DC_WINBUF_START_ADDR_U_NS 0x803
	466	#define DC_WINBUF_START_ADDR_V 0x804
	467	#define DC_WINBUF_START_ADDR_V_NS 0x805
	468	#define DC_WINBUF_ADDR_H_OFFSET 0x806
	469	#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
	470	#define DC_WINBUF_ADDR_V_OFFSET 0x808
	471	#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
	472	#define DC_WINBUF_UFLOW_STATUS 0x80a
	473
	474	/* direct versions of DC_WINBUF_UFLOW_STATUS */
	475	#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
	476	#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
	477	#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
	478
	479	#define DC_DISP_SD_CONTROL 0x4c2
	480	#define SD_ENABLE_NORMAL (1 << 0)
	481	#define SD_ENABLE_ONESHOT (2 << 0)
	482	#define SD_USE_VID_LUMA (1 << 2)
	483	#define SD_BIN_WIDTH_ONE (0 << 3)
	484	#define SD_BIN_WIDTH_TWO (1 << 3)
	485	#define SD_BIN_WIDTH_FOUR (2 << 3)
	486	#define SD_BIN_WIDTH_EIGHT (3 << 3)
	487	#define SD_BIN_WIDTH_MASK (3 << 3)
	488	#define SD_AGGRESSIVENESS(x) (((x) & 0x7) << 5)
	489	#define SD_HW_UPDATE_DLY(x) (((x) & 0x3) << 8)
	490	#define SD_ONESHOT_ENABLE (1 << 10)
	491	#define SD_CORRECTION_MODE_AUTO (0 << 11)
	492	#define SD_CORRECTION_MODE_MAN (1 << 11)
	493
	494	#define NUM_BIN_WIDTHS 4
	495	#define STEPS_PER_AGG_LVL 64
	496	#define STEPS_PER_AGG_CHG_LOG2 5
	497	#define STEPS_PER_AGG_CHG (1<<STEPS_PER_AGG_CHG_LOG2)
	498	#define ADJ_PHASE_STEP 8
	499	#define K_STEP 4
	500
	501	#define DC_DISP_SD_CSC_COEFF 0x4c3
	502	#define SD_CSC_COEFF_R(x) (((x) & 0xf) << 4)
	503	#define SD_CSC_COEFF_G(x) (((x) & 0xf) << 12)
	504	#define SD_CSC_COEFF_B(x) (((x) & 0xf) << 20)
	505
	506	#define DC_DISP_SD_LUT(i) (0x4c4 + i)
	507	#define DC_DISP_SD_LUT_NUM 9
	508	#define SD_LUT_R(x) (((x) & 0xff) << 0)
	509	#define SD_LUT_G(x) (((x) & 0xff) << 8)
	510	#define SD_LUT_B(x) (((x) & 0xff) << 16)
	511
	512	#define DC_DISP_SD_FLICKER_CONTROL 0x4cd
	513	#define SD_FC_TIME_LIMIT(x) (((x) & 0xff) << 0)
	514	#define SD_FC_THRESHOLD(x) (((x) & 0xff) << 8)
	515
	516	#define DC_DISP_SD_PIXEL_COUNT 0x4ce
	517
	518	#define DC_DISP_SD_HISTOGRAM(i) (0x4cf + i)
	519	#define DC_DISP_SD_HISTOGRAM_NUM 8
	520	#define SD_HISTOGRAM_BIN_0(val) (((val) & (0xff << 0)) >> 0)
	521	#define SD_HISTOGRAM_BIN_1(val) (((val) & (0xff << 8)) >> 8)
	522	#define SD_HISTOGRAM_BIN_2(val) (((val) & (0xff << 16)) >> 16)
	523	#define SD_HISTOGRAM_BIN_3(val) (((val) & (0xff << 24)) >> 24)
	524
	525	#define DC_DISP_SD_BL_PARAMETERS 0x4d7
	526	#define SD_BLP_TIME_CONSTANT(x) (((x) & 0x7ff) << 0)
	527	#define SD_BLP_STEP(x) (((x) & 0xff) << 16)
	528
	529	#define DC_DISP_SD_BL_TF(i) (0x4d8 + i)
	530	#define DC_DISP_SD_BL_TF_NUM 4
	531	#define SD_BL_TF_POINT_0(x) (((x) & 0xff) << 0)
	532	#define SD_BL_TF_POINT_1(x) (((x) & 0xff) << 8)
	533	#define SD_BL_TF_POINT_2(x) (((x) & 0xff) << 16)
	534	#define SD_BL_TF_POINT_3(x) (((x) & 0xff) << 24)
	535
	536	#define DC_DISP_SD_BL_CONTROL 0x4dc
	537	#define SD_BLC_MODE_MAN (0 << 0)
	538	#define SD_BLC_MODE_AUTO (1 << 1)
	539	#define SD_BLC_BRIGHTNESS(val) (((val) & (0xff << 8)) >> 8)
	540
	541	#define DC_DISP_SD_HW_K_VALUES 0x4dd
	542	#define SD_HW_K_R(val) (((val) & (0x3ff << 0)) >> 0)
	543	#define SD_HW_K_G(val) (((val) & (0x3ff << 10)) >> 10)
	544	#define SD_HW_K_B(val) (((val) & (0x3ff << 20)) >> 20)
	545
	546	#define DC_DISP_SD_MAN_K_VALUES 0x4de
	547	#define SD_MAN_K_R(x) (((x) & 0x3ff) << 0)
	548	#define SD_MAN_K_G(x) (((x) & 0x3ff) << 10)
	549	#define SD_MAN_K_B(x) (((x) & 0x3ff) << 20)
	550
	551	#define NUM_AGG_PRI_LVLS 4
	552	#define SD_AGG_PRI_LVL(x) ((x) >> 3)
	553	#define SD_GET_AGG(x) ((x) & 0x7)
	554
	555	#endif