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authorAaro Koskinen <aaro.koskinen@iki.fi>2010-12-20 16:50:17 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-12-21 22:57:05 -0500
commit44b751bbe1fb6e7a75bbdee2d0c5f3ee133d6b0f (patch)
tree5a3c2ca09d9961638c468fd1d7ff14d5a6b39355 /drivers/video/sis/sis_main.c
parente57d413681b6d9c3d256eeac1e34f0d1b8b81e26 (diff)
sisfb: replace outSISIDXREG with SiS_SetReg
Replace outSISIDXREG() with SiS_SetReg(). Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Thomas Winischhofer <thomas@winischhofer.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/video/sis/sis_main.c')
-rw-r--r--drivers/video/sis/sis_main.c630
1 files changed, 315 insertions, 315 deletions
diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c
index 6ea71b89b1c..59a567c8f3c 100644
--- a/drivers/video/sis/sis_main.c
+++ b/drivers/video/sis/sis_main.c
@@ -1114,14 +1114,14 @@ sisfb_set_pitch(struct sis_video_info *ivideo)
1114 1114
1115 /* We need to set pitch for CRT1 if bridge is in slave mode, too */ 1115 /* We need to set pitch for CRT1 if bridge is in slave mode, too */
1116 if((ivideo->currentvbflags & VB_DISPTYPE_DISP1) || (isslavemode)) { 1116 if((ivideo->currentvbflags & VB_DISPTYPE_DISP1) || (isslavemode)) {
1117 outSISIDXREG(SISCR,0x13,(HDisplay1 & 0xFF)); 1117 SiS_SetReg(SISCR, 0x13, (HDisplay1 & 0xFF));
1118 setSISIDXREG(SISSR,0x0E,0xF0,(HDisplay1 >> 8)); 1118 setSISIDXREG(SISSR,0x0E,0xF0,(HDisplay1 >> 8));
1119 } 1119 }
1120 1120
1121 /* We must not set the pitch for CRT2 if bridge is in slave mode */ 1121 /* We must not set the pitch for CRT2 if bridge is in slave mode */
1122 if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!isslavemode)) { 1122 if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!isslavemode)) {
1123 orSISIDXREG(SISPART1,ivideo->CRT2_write_enable,0x01); 1123 orSISIDXREG(SISPART1,ivideo->CRT2_write_enable,0x01);
1124 outSISIDXREG(SISPART1,0x07,(HDisplay2 & 0xFF)); 1124 SiS_SetReg(SISPART1, 0x07, (HDisplay2 & 0xFF));
1125 setSISIDXREG(SISPART1,0x09,0xF0,(HDisplay2 >> 8)); 1125 setSISIDXREG(SISPART1,0x09,0xF0,(HDisplay2 >> 8));
1126 } 1126 }
1127} 1127}
@@ -1167,7 +1167,7 @@ sisfb_set_mode(struct sis_video_info *ivideo, int clrscrn)
1167 /* >=2.6.12's fbcon clears the screen anyway */ 1167 /* >=2.6.12's fbcon clears the screen anyway */
1168 modeno |= 0x80; 1168 modeno |= 0x80;
1169 1169
1170 outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD); 1170 SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
1171 1171
1172 sisfb_pre_setmode(ivideo); 1172 sisfb_pre_setmode(ivideo);
1173 1173
@@ -1176,7 +1176,7 @@ sisfb_set_mode(struct sis_video_info *ivideo, int clrscrn)
1176 return -EINVAL; 1176 return -EINVAL;
1177 } 1177 }
1178 1178
1179 outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD); 1179 SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
1180 1180
1181 sisfb_post_setmode(ivideo); 1181 sisfb_post_setmode(ivideo);
1182 1182
@@ -1308,11 +1308,11 @@ sisfb_do_set_var(struct fb_var_screeninfo *var, int isactive, struct fb_info *in
1308static void 1308static void
1309sisfb_set_base_CRT1(struct sis_video_info *ivideo, unsigned int base) 1309sisfb_set_base_CRT1(struct sis_video_info *ivideo, unsigned int base)
1310{ 1310{
1311 outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD); 1311 SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
1312 1312
1313 outSISIDXREG(SISCR, 0x0D, base & 0xFF); 1313 SiS_SetReg(SISCR, 0x0D, base & 0xFF);
1314 outSISIDXREG(SISCR, 0x0C, (base >> 8) & 0xFF); 1314 SiS_SetReg(SISCR, 0x0C, (base >> 8) & 0xFF);
1315 outSISIDXREG(SISSR, 0x0D, (base >> 16) & 0xFF); 1315 SiS_SetReg(SISSR, 0x0D, (base >> 16) & 0xFF);
1316 if(ivideo->sisvga_engine == SIS_315_VGA) { 1316 if(ivideo->sisvga_engine == SIS_315_VGA) {
1317 setSISIDXREG(SISSR, 0x37, 0xFE, (base >> 24) & 0x01); 1317 setSISIDXREG(SISSR, 0x37, 0xFE, (base >> 24) & 0x01);
1318 } 1318 }
@@ -1323,9 +1323,9 @@ sisfb_set_base_CRT2(struct sis_video_info *ivideo, unsigned int base)
1323{ 1323{
1324 if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) { 1324 if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
1325 orSISIDXREG(SISPART1, ivideo->CRT2_write_enable, 0x01); 1325 orSISIDXREG(SISPART1, ivideo->CRT2_write_enable, 0x01);
1326 outSISIDXREG(SISPART1, 0x06, (base & 0xFF)); 1326 SiS_SetReg(SISPART1, 0x06, (base & 0xFF));
1327 outSISIDXREG(SISPART1, 0x05, ((base >> 8) & 0xFF)); 1327 SiS_SetReg(SISPART1, 0x05, ((base >> 8) & 0xFF));
1328 outSISIDXREG(SISPART1, 0x04, ((base >> 16) & 0xFF)); 1328 SiS_SetReg(SISPART1, 0x04, ((base >> 16) & 0xFF));
1329 if(ivideo->sisvga_engine == SIS_315_VGA) { 1329 if(ivideo->sisvga_engine == SIS_315_VGA) {
1330 setSISIDXREG(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7); 1330 setSISIDXREG(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7);
1331 } 1331 }
@@ -2216,8 +2216,8 @@ sisfb_sense_crt1(struct sis_video_info *ivideo)
2216 if(!cr17) { 2216 if(!cr17) {
2217 orSISIDXREG(SISCR,0x17,0x80); 2217 orSISIDXREG(SISCR,0x17,0x80);
2218 mustwait = true; 2218 mustwait = true;
2219 outSISIDXREG(SISSR, 0x00, 0x01); 2219 SiS_SetReg(SISSR, 0x00, 0x01);
2220 outSISIDXREG(SISSR, 0x00, 0x03); 2220 SiS_SetReg(SISSR, 0x00, 0x03);
2221 } 2221 }
2222 2222
2223 if(mustwait) { 2223 if(mustwait) {
@@ -2228,9 +2228,9 @@ sisfb_sense_crt1(struct sis_video_info *ivideo)
2228 if(ivideo->chip >= SIS_330) { 2228 if(ivideo->chip >= SIS_330) {
2229 andSISIDXREG(SISCR,0x32,~0x20); 2229 andSISIDXREG(SISCR,0x32,~0x20);
2230 if(ivideo->chip >= SIS_340) { 2230 if(ivideo->chip >= SIS_340) {
2231 outSISIDXREG(SISCR, 0x57, 0x4a); 2231 SiS_SetReg(SISCR, 0x57, 0x4a);
2232 } else { 2232 } else {
2233 outSISIDXREG(SISCR, 0x57, 0x5f); 2233 SiS_SetReg(SISCR, 0x57, 0x5f);
2234 } 2234 }
2235 orSISIDXREG(SISCR, 0x53, 0x02); 2235 orSISIDXREG(SISCR, 0x53, 0x02);
2236 while ((SiS_GetRegByte(SISINPSTAT)) & 0x01) break; 2236 while ((SiS_GetRegByte(SISINPSTAT)) & 0x01) break;
@@ -2265,7 +2265,7 @@ sisfb_sense_crt1(struct sis_video_info *ivideo)
2265 2265
2266 setSISIDXREG(SISCR,0x17,0x7F,cr17); 2266 setSISIDXREG(SISCR,0x17,0x7F,cr17);
2267 2267
2268 outSISIDXREG(SISSR,0x1F,sr1F); 2268 SiS_SetReg(SISSR, 0x1F, sr1F);
2269} 2269}
2270 2270
2271/* Determine and detect attached devices on SiS30x */ 2271/* Determine and detect attached devices on SiS30x */
@@ -2349,7 +2349,7 @@ SiS_SenseLCD(struct sis_video_info *ivideo)
2349 else 2349 else
2350 cr37 |= 0xc0; 2350 cr37 |= 0xc0;
2351 2351
2352 outSISIDXREG(SISCR, 0x36, paneltype); 2352 SiS_SetReg(SISCR, 0x36, paneltype);
2353 cr37 &= 0xf1; 2353 cr37 &= 0xf1;
2354 setSISIDXREG(SISCR, 0x37, 0x0c, cr37); 2354 setSISIDXREG(SISCR, 0x37, 0x0c, cr37);
2355 orSISIDXREG(SISCR, 0x32, 0x08); 2355 orSISIDXREG(SISCR, 0x32, 0x08);
@@ -2366,7 +2366,7 @@ SISDoSense(struct sis_video_info *ivideo, u16 type, u16 test)
2366 result = 0; 2366 result = 0;
2367 for(i = 0; i < 3; i++) { 2367 for(i = 0; i < 3; i++) {
2368 mytest = test; 2368 mytest = test;
2369 outSISIDXREG(SISPART4,0x11,(type & 0x00ff)); 2369 SiS_SetReg(SISPART4, 0x11, (type & 0x00ff));
2370 temp = (type >> 8) | (mytest & 0x00ff); 2370 temp = (type >> 8) | (mytest & 0x00ff);
2371 setSISIDXREG(SISPART4,0x10,0xe0,temp); 2371 setSISIDXREG(SISPART4,0x10,0xe0,temp);
2372 SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1500); 2372 SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1500);
@@ -2377,7 +2377,7 @@ SISDoSense(struct sis_video_info *ivideo, u16 type, u16 test)
2377 temp &= mytest; 2377 temp &= mytest;
2378 if(temp == mytest) result++; 2378 if(temp == mytest) result++;
2379#if 1 2379#if 1
2380 outSISIDXREG(SISPART4,0x11,0x00); 2380 SiS_SetReg(SISPART4, 0x11, 0x00);
2381 andSISIDXREG(SISPART4,0x10,0xe0); 2381 andSISIDXREG(SISPART4,0x10,0xe0);
2382 SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1000); 2382 SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1000);
2383#endif 2383#endif
@@ -2450,11 +2450,11 @@ SiS_Sense30x(struct sis_video_info *ivideo)
2450 SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000); 2450 SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
2451 2451
2452 backupP2_00 = SiS_GetReg(SISPART2, 0x00); 2452 backupP2_00 = SiS_GetReg(SISPART2, 0x00);
2453 outSISIDXREG(SISPART2,0x00,((backupP2_00 | 0x1c) & 0xfc)); 2453 SiS_SetReg(SISPART2, 0x00, ((backupP2_00 | 0x1c) & 0xfc));
2454 2454
2455 backupP2_4d = SiS_GetReg(SISPART2, 0x4d); 2455 backupP2_4d = SiS_GetReg(SISPART2, 0x4d);
2456 if(ivideo->vbflags2 & VB2_SISYPBPRBRIDGE) { 2456 if(ivideo->vbflags2 & VB2_SISYPBPRBRIDGE) {
2457 outSISIDXREG(SISPART2,0x4d,(backupP2_4d & ~0x10)); 2457 SiS_SetReg(SISPART2, 0x4d, (backupP2_4d & ~0x10));
2458 } 2458 }
2459 2459
2460 if(!(ivideo->vbflags2 & VB2_30xCLV)) { 2460 if(!(ivideo->vbflags2 & VB2_30xCLV)) {
@@ -2482,7 +2482,7 @@ SiS_Sense30x(struct sis_video_info *ivideo)
2482 } 2482 }
2483 2483
2484 if((ivideo->sisvga_engine == SIS_315_VGA) && (ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) { 2484 if((ivideo->sisvga_engine == SIS_315_VGA) && (ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) {
2485 outSISIDXREG(SISPART2,0x4d,(backupP2_4d | 0x10)); 2485 SiS_SetReg(SISPART2, 0x4d, (backupP2_4d | 0x10));
2486 SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000); 2486 SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
2487 if((result = SISDoSense(ivideo, svhs, 0x0604))) { 2487 if((result = SISDoSense(ivideo, svhs, 0x0604))) {
2488 if((result = SISDoSense(ivideo, cvbs, 0x0804))) { 2488 if((result = SISDoSense(ivideo, cvbs, 0x0804))) {
@@ -2490,7 +2490,7 @@ SiS_Sense30x(struct sis_video_info *ivideo)
2490 orSISIDXREG(SISCR,0x32,0x80); 2490 orSISIDXREG(SISCR,0x32,0x80);
2491 } 2491 }
2492 } 2492 }
2493 outSISIDXREG(SISPART2,0x4d,backupP2_4d); 2493 SiS_SetReg(SISPART2, 0x4d, backupP2_4d);
2494 } 2494 }
2495 2495
2496 andSISIDXREG(SISCR, 0x32, ~0x03); 2496 andSISIDXREG(SISCR, 0x32, ~0x03);
@@ -2510,21 +2510,21 @@ SiS_Sense30x(struct sis_video_info *ivideo)
2510 2510
2511 SISDoSense(ivideo, 0, 0); 2511 SISDoSense(ivideo, 0, 0);
2512 2512
2513 outSISIDXREG(SISPART2,0x00,backupP2_00); 2513 SiS_SetReg(SISPART2, 0x00, backupP2_00);
2514 outSISIDXREG(SISPART4,0x0d,backupP4_0d); 2514 SiS_SetReg(SISPART4, 0x0d, backupP4_0d);
2515 outSISIDXREG(SISSR,0x1e,backupSR_1e); 2515 SiS_SetReg(SISSR, 0x1e, backupSR_1e);
2516 2516
2517 if(ivideo->vbflags2 & VB2_30xCLV) { 2517 if(ivideo->vbflags2 & VB2_30xCLV) {
2518 biosflag = SiS_GetReg(SISPART2, 0x00); 2518 biosflag = SiS_GetReg(SISPART2, 0x00);
2519 if(biosflag & 0x20) { 2519 if(biosflag & 0x20) {
2520 for(myflag = 2; myflag > 0; myflag--) { 2520 for(myflag = 2; myflag > 0; myflag--) {
2521 biosflag ^= 0x20; 2521 biosflag ^= 0x20;
2522 outSISIDXREG(SISPART2,0x00,biosflag); 2522 SiS_SetReg(SISPART2, 0x00, biosflag);
2523 } 2523 }
2524 } 2524 }
2525 } 2525 }
2526 2526
2527 outSISIDXREG(SISPART2,0x00,backupP2_00); 2527 SiS_SetReg(SISPART2, 0x00, backupP2_00);
2528} 2528}
2529 2529
2530/* Determine and detect attached TV's on Chrontel */ 2530/* Determine and detect attached TV's on Chrontel */
@@ -2826,9 +2826,9 @@ sisfb_engine_init(struct sis_video_info *ivideo)
2826 tq_state |= 0xf0; 2826 tq_state |= 0xf0;
2827 tq_state &= 0xfc; 2827 tq_state &= 0xfc;
2828 tq_state |= (u8)(tqueue_pos >> 8); 2828 tq_state |= (u8)(tqueue_pos >> 8);
2829 outSISIDXREG(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state); 2829 SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state);
2830 2830
2831 outSISIDXREG(SISSR, IND_SIS_TURBOQUEUE_ADR, (u8)(tqueue_pos & 0xff)); 2831 SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_ADR, (u8)(tqueue_pos & 0xff));
2832 2832
2833 ivideo->caps |= TURBO_QUEUE_CAP; 2833 ivideo->caps |= TURBO_QUEUE_CAP;
2834 } 2834 }
@@ -2865,8 +2865,8 @@ sisfb_engine_init(struct sis_video_info *ivideo)
2865 } 2865 }
2866 } 2866 }
2867 2867
2868 outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_THRESHOLD, COMMAND_QUEUE_THRESHOLD); 2868 SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_THRESHOLD, COMMAND_QUEUE_THRESHOLD);
2869 outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET); 2869 SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
2870 2870
2871 if((ivideo->chip >= XGI_40) && ivideo->modechanged) { 2871 if((ivideo->chip >= XGI_40) && ivideo->modechanged) {
2872 /* Must disable dual pipe on XGI_40. Can't do 2872 /* Must disable dual pipe on XGI_40. Can't do
@@ -2878,7 +2878,7 @@ sisfb_engine_init(struct sis_video_info *ivideo)
2878 2878
2879 MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, 0); 2879 MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, 0);
2880 2880
2881 outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, (temp | SIS_VRAM_CMDQUEUE_ENABLE)); 2881 SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, (temp | SIS_VRAM_CMDQUEUE_ENABLE));
2882 2882
2883 tempq = MMIO_IN32(ivideo->mmio_vbase, Q_READ_PTR); 2883 tempq = MMIO_IN32(ivideo->mmio_vbase, Q_READ_PTR);
2884 MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, tempq); 2884 MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, tempq);
@@ -2895,7 +2895,7 @@ sisfb_engine_init(struct sis_video_info *ivideo)
2895 2895
2896 sisfb_syncaccel(ivideo); 2896 sisfb_syncaccel(ivideo);
2897 2897
2898 outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET); 2898 SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
2899 2899
2900 } 2900 }
2901 } 2901 }
@@ -2904,7 +2904,7 @@ sisfb_engine_init(struct sis_video_info *ivideo)
2904 MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_WRITEPORT, tempq); 2904 MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_WRITEPORT, tempq);
2905 2905
2906 temp |= (SIS_MMIO_CMD_ENABLE | SIS_CMD_AUTO_CORR); 2906 temp |= (SIS_MMIO_CMD_ENABLE | SIS_CMD_AUTO_CORR);
2907 outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, temp); 2907 SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, temp);
2908 2908
2909 tempq = (u32)(ivideo->video_size - ivideo->cmdQueueSize); 2909 tempq = (u32)(ivideo->video_size - ivideo->cmdQueueSize);
2910 MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_PHYBASE, tempq); 2910 MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_PHYBASE, tempq);
@@ -3524,7 +3524,7 @@ sisfb_pre_setmode(struct sis_video_info *ivideo)
3524 3524
3525 ivideo->currentvbflags &= (VB_VIDEOBRIDGE | VB_DISPTYPE_DISP2); 3525 ivideo->currentvbflags &= (VB_VIDEOBRIDGE | VB_DISPTYPE_DISP2);
3526 3526
3527 outSISIDXREG(SISSR, 0x05, 0x86); 3527 SiS_SetReg(SISSR, 0x05, 0x86);
3528 3528
3529 cr31 = SiS_GetReg(SISCR, 0x31); 3529 cr31 = SiS_GetReg(SISCR, 0x31);
3530 cr31 &= ~0x60; 3530 cr31 &= ~0x60;
@@ -3654,8 +3654,8 @@ sisfb_pre_setmode(struct sis_video_info *ivideo)
3654 cr31 |= (SIS_DRIVER_MODE | SIS_VB_OUTPUT_DISABLE); 3654 cr31 |= (SIS_DRIVER_MODE | SIS_VB_OUTPUT_DISABLE);
3655 } 3655 }
3656 3656
3657 outSISIDXREG(SISCR, 0x30, cr30); 3657 SiS_SetReg(SISCR, 0x30, cr30);
3658 outSISIDXREG(SISCR, 0x33, cr33); 3658 SiS_SetReg(SISCR, 0x33, cr33);
3659 3659
3660 if(ivideo->chip >= SIS_661) { 3660 if(ivideo->chip >= SIS_661) {
3661#ifdef CONFIG_FB_SIS_315 3661#ifdef CONFIG_FB_SIS_315
@@ -3665,9 +3665,9 @@ sisfb_pre_setmode(struct sis_video_info *ivideo)
3665 setSISIDXREG(SISCR, 0x38, 0xf8, cr38); 3665 setSISIDXREG(SISCR, 0x38, 0xf8, cr38);
3666#endif 3666#endif
3667 } else if(ivideo->chip != SIS_300) { 3667 } else if(ivideo->chip != SIS_300) {
3668 outSISIDXREG(SISCR, tvregnum, cr38); 3668 SiS_SetReg(SISCR, tvregnum, cr38);
3669 } 3669 }
3670 outSISIDXREG(SISCR, 0x31, cr31); 3670 SiS_SetReg(SISCR, 0x31, cr31);
3671 3671
3672 ivideo->SiS_Pr.SiS_UseOEM = ivideo->sisfb_useoem; 3672 ivideo->SiS_Pr.SiS_UseOEM = ivideo->sisfb_useoem;
3673 3673
@@ -3686,7 +3686,7 @@ sisfb_fixup_SR11(struct sis_video_info *ivideo)
3686 if(tmpreg & 0x20) { 3686 if(tmpreg & 0x20) {
3687 tmpreg = SiS_GetReg(SISSR, 0x3e); 3687 tmpreg = SiS_GetReg(SISSR, 0x3e);
3688 tmpreg = (tmpreg + 1) & 0xff; 3688 tmpreg = (tmpreg + 1) & 0xff;
3689 outSISIDXREG(SISSR,0x3e,tmpreg); 3689 SiS_SetReg(SISSR, 0x3e, tmpreg);
3690 tmpreg = SiS_GetReg(SISSR, 0x11); 3690 tmpreg = SiS_GetReg(SISSR, 0x11);
3691 } 3691 }
3692 if(tmpreg & 0xf0) { 3692 if(tmpreg & 0xf0) {
@@ -3716,7 +3716,7 @@ sisfb_set_TVxposoffset(struct sis_video_info *ivideo, int val)
3716 case 1: 3716 case 1:
3717 x += val; 3717 x += val;
3718 if(x < 0) x = 0; 3718 if(x < 0) x = 0;
3719 outSISIDXREG(SISSR,0x05,0x86); 3719 SiS_SetReg(SISSR, 0x05, 0x86);
3720 SiS_SetCH700x(&ivideo->SiS_Pr, 0x0a, (x & 0xff)); 3720 SiS_SetCH700x(&ivideo->SiS_Pr, 0x0a, (x & 0xff));
3721 SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((x & 0x0100) >> 7), 0xFD); 3721 SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((x & 0x0100) >> 7), 0xFD);
3722 break; 3722 break;
@@ -3745,11 +3745,11 @@ sisfb_set_TVxposoffset(struct sis_video_info *ivideo, int val)
3745 temp += (val * 2); 3745 temp += (val * 2);
3746 p2_43 = temp & 0xff; 3746 p2_43 = temp & 0xff;
3747 p2_42 = (temp & 0xf00) >> 4; 3747 p2_42 = (temp & 0xf00) >> 4;
3748 outSISIDXREG(SISPART2,0x1f,p2_1f); 3748 SiS_SetReg(SISPART2, 0x1f, p2_1f);
3749 setSISIDXREG(SISPART2,0x20,0x0F,p2_20); 3749 setSISIDXREG(SISPART2,0x20,0x0F,p2_20);
3750 setSISIDXREG(SISPART2,0x2b,0xF0,p2_2b); 3750 setSISIDXREG(SISPART2,0x2b,0xF0,p2_2b);
3751 setSISIDXREG(SISPART2,0x42,0x0F,p2_42); 3751 setSISIDXREG(SISPART2,0x42,0x0F,p2_42);
3752 outSISIDXREG(SISPART2,0x43,p2_43); 3752 SiS_SetReg(SISPART2, 0x43, p2_43);
3753 } 3753 }
3754 } 3754 }
3755} 3755}
@@ -3774,7 +3774,7 @@ sisfb_set_TVyposoffset(struct sis_video_info *ivideo, int val)
3774 case 1: 3774 case 1:
3775 y -= val; 3775 y -= val;
3776 if(y < 0) y = 0; 3776 if(y < 0) y = 0;
3777 outSISIDXREG(SISSR,0x05,0x86); 3777 SiS_SetReg(SISSR, 0x05, 0x86);
3778 SiS_SetCH700x(&ivideo->SiS_Pr, 0x0b, (y & 0xff)); 3778 SiS_SetCH700x(&ivideo->SiS_Pr, 0x0b, (y & 0xff));
3779 SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((y & 0x0100) >> 8), 0xFE); 3779 SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((y & 0x0100) >> 8), 0xFE);
3780 break; 3780 break;
@@ -3798,8 +3798,8 @@ sisfb_set_TVyposoffset(struct sis_video_info *ivideo, int val)
3798 p2_02 += 2; 3798 p2_02 += 2;
3799 } 3799 }
3800 } 3800 }
3801 outSISIDXREG(SISPART2,0x01,p2_01); 3801 SiS_SetReg(SISPART2, 0x01, p2_01);
3802 outSISIDXREG(SISPART2,0x02,p2_02); 3802 SiS_SetReg(SISPART2, 0x02, p2_02);
3803 } 3803 }
3804 } 3804 }
3805} 3805}
@@ -3816,7 +3816,7 @@ sisfb_post_setmode(struct sis_video_info *ivideo)
3816 u8 reg1; 3816 u8 reg1;
3817#endif 3817#endif
3818 3818
3819 outSISIDXREG(SISSR, 0x05, 0x86); 3819 SiS_SetReg(SISSR, 0x05, 0x86);
3820 3820
3821#ifdef CONFIG_FB_SIS_315 3821#ifdef CONFIG_FB_SIS_315
3822 sisfb_fixup_SR11(ivideo); 3822 sisfb_fixup_SR11(ivideo);
@@ -4196,8 +4196,8 @@ sisfb_post_300_buswidth(struct sis_video_info *ivideo)
4196 4196
4197 andSISIDXREG(SISSR, 0x15, 0xFB); 4197 andSISIDXREG(SISSR, 0x15, 0xFB);
4198 orSISIDXREG(SISSR, 0x15, 0x04); 4198 orSISIDXREG(SISSR, 0x15, 0x04);
4199 outSISIDXREG(SISSR, 0x13, 0x00); 4199 SiS_SetReg(SISSR, 0x13, 0x00);
4200 outSISIDXREG(SISSR, 0x14, 0xBF); 4200 SiS_SetReg(SISSR, 0x14, 0xBF);
4201 4201
4202 for(i = 0; i < 2; i++) { 4202 for(i = 0; i < 2; i++) {
4203 temp = 0x1234; 4203 temp = 0x1234;
@@ -4288,8 +4288,8 @@ sisfb_post_300_rwtest(struct sis_video_info *ivideo, int iteration, int buswidth
4288 sr14 = (SiS_DRAMType[k][3] * buswidth) - 1; 4288 sr14 = (SiS_DRAMType[k][3] * buswidth) - 1;
4289 if(buswidth == 4) sr14 |= 0x80; 4289 if(buswidth == 4) sr14 |= 0x80;
4290 else if(buswidth == 2) sr14 |= 0x40; 4290 else if(buswidth == 2) sr14 |= 0x40;
4291 outSISIDXREG(SISSR, 0x13, SiS_DRAMType[k][4]); 4291 SiS_SetReg(SISSR, 0x13, SiS_DRAMType[k][4]);
4292 outSISIDXREG(SISSR, 0x14, sr14); 4292 SiS_SetReg(SISSR, 0x14, sr14);
4293 4293
4294 BankNumHigh <<= 16; 4294 BankNumHigh <<= 16;
4295 BankNumMid <<= 16; 4295 BankNumMid <<= 16;
@@ -4356,7 +4356,7 @@ sisfb_post_sis300(struct pci_dev *pdev)
4356 if(!ivideo->SiS_Pr.UseROM) 4356 if(!ivideo->SiS_Pr.UseROM)
4357 bios = NULL; 4357 bios = NULL;
4358 4358
4359 outSISIDXREG(SISSR, 0x05, 0x86); 4359 SiS_SetReg(SISSR, 0x05, 0x86);
4360 4360
4361 if(bios) { 4361 if(bios) {
4362 if(bios[0x52] & 0x80) { 4362 if(bios[0x52] & 0x80) {
@@ -4386,19 +4386,19 @@ sisfb_post_sis300(struct pci_dev *pdev)
4386 v6 = bios[rindex++]; 4386 v6 = bios[rindex++];
4387 } 4387 }
4388 } 4388 }
4389 outSISIDXREG(SISSR, 0x28, v1); 4389 SiS_SetReg(SISSR, 0x28, v1);
4390 outSISIDXREG(SISSR, 0x29, v2); 4390 SiS_SetReg(SISSR, 0x29, v2);
4391 outSISIDXREG(SISSR, 0x2a, v3); 4391 SiS_SetReg(SISSR, 0x2a, v3);
4392 outSISIDXREG(SISSR, 0x2e, v4); 4392 SiS_SetReg(SISSR, 0x2e, v4);
4393 outSISIDXREG(SISSR, 0x2f, v5); 4393 SiS_SetReg(SISSR, 0x2f, v5);
4394 outSISIDXREG(SISSR, 0x30, v6); 4394 SiS_SetReg(SISSR, 0x30, v6);
4395 4395
4396 v1 = 0x10; 4396 v1 = 0x10;
4397 if(bios) 4397 if(bios)
4398 v1 = bios[0xa4]; 4398 v1 = bios[0xa4];
4399 outSISIDXREG(SISSR, 0x07, v1); /* DAC speed */ 4399 SiS_SetReg(SISSR, 0x07, v1); /* DAC speed */
4400 4400
4401 outSISIDXREG(SISSR, 0x11, 0x0f); /* DDC, power save */ 4401 SiS_SetReg(SISSR, 0x11, 0x0f); /* DDC, power save */
4402 4402
4403 v1 = 0x01; v2 = 0x43; v3 = 0x1e; v4 = 0x2a; 4403 v1 = 0x01; v2 = 0x43; v3 = 0x1e; v4 = 0x2a;
4404 v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00; 4404 v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00;
@@ -4415,14 +4415,14 @@ sisfb_post_sis300(struct pci_dev *pdev)
4415 } 4415 }
4416 if(ivideo->revision_id >= 0x80) 4416 if(ivideo->revision_id >= 0x80)
4417 v3 &= 0xfd; 4417 v3 &= 0xfd;
4418 outSISIDXREG(SISSR, 0x15, v1); /* Ram type (assuming 0, BIOS 0xa5 step 8) */ 4418 SiS_SetReg(SISSR, 0x15, v1); /* Ram type (assuming 0, BIOS 0xa5 step 8) */
4419 outSISIDXREG(SISSR, 0x16, v2); 4419 SiS_SetReg(SISSR, 0x16, v2);
4420 outSISIDXREG(SISSR, 0x17, v3); 4420 SiS_SetReg(SISSR, 0x17, v3);
4421 outSISIDXREG(SISSR, 0x18, v4); 4421 SiS_SetReg(SISSR, 0x18, v4);
4422 outSISIDXREG(SISSR, 0x19, v5); 4422 SiS_SetReg(SISSR, 0x19, v5);
4423 outSISIDXREG(SISSR, 0x1a, v6); 4423 SiS_SetReg(SISSR, 0x1a, v6);
4424 outSISIDXREG(SISSR, 0x1b, v7); 4424 SiS_SetReg(SISSR, 0x1b, v7);
4425 outSISIDXREG(SISSR, 0x1c, v8); /* ---- */ 4425 SiS_SetReg(SISSR, 0x1c, v8); /* ---- */
4426 andSISIDXREG(SISSR, 0x15 ,0xfb); 4426 andSISIDXREG(SISSR, 0x15 ,0xfb);
4427 orSISIDXREG(SISSR, 0x15, 0x04); 4427 orSISIDXREG(SISSR, 0x15, 0x04);
4428 if(bios) { 4428 if(bios) {
@@ -4433,69 +4433,69 @@ sisfb_post_sis300(struct pci_dev *pdev)
4433 v1 = 0x04; /* DAC pedestal (BIOS 0xe5) */ 4433 v1 = 0x04; /* DAC pedestal (BIOS 0xe5) */
4434 if(ivideo->revision_id >= 0x80) 4434 if(ivideo->revision_id >= 0x80)
4435 v1 |= 0x01; 4435 v1 |= 0x01;
4436 outSISIDXREG(SISSR, 0x1f, v1); 4436 SiS_SetReg(SISSR, 0x1f, v1);
4437 outSISIDXREG(SISSR, 0x20, 0xa4); /* linear & relocated io & disable a0000 */ 4437 SiS_SetReg(SISSR, 0x20, 0xa4); /* linear & relocated io & disable a0000 */
4438 v1 = 0xf6; v2 = 0x0d; v3 = 0x00; 4438 v1 = 0xf6; v2 = 0x0d; v3 = 0x00;
4439 if(bios) { 4439 if(bios) {
4440 v1 = bios[0xe8]; 4440 v1 = bios[0xe8];
4441 v2 = bios[0xe9]; 4441 v2 = bios[0xe9];
4442 v3 = bios[0xea]; 4442 v3 = bios[0xea];
4443 } 4443 }
4444 outSISIDXREG(SISSR, 0x23, v1); 4444 SiS_SetReg(SISSR, 0x23, v1);
4445 outSISIDXREG(SISSR, 0x24, v2); 4445 SiS_SetReg(SISSR, 0x24, v2);
4446 outSISIDXREG(SISSR, 0x25, v3); 4446 SiS_SetReg(SISSR, 0x25, v3);
4447 outSISIDXREG(SISSR, 0x21, 0x84); 4447 SiS_SetReg(SISSR, 0x21, 0x84);
4448 outSISIDXREG(SISSR, 0x22, 0x00); 4448 SiS_SetReg(SISSR, 0x22, 0x00);
4449 outSISIDXREG(SISCR, 0x37, 0x00); 4449 SiS_SetReg(SISCR, 0x37, 0x00);
4450 orSISIDXREG(SISPART1, 0x24, 0x01); /* unlock crt2 */ 4450 orSISIDXREG(SISPART1, 0x24, 0x01); /* unlock crt2 */
4451 outSISIDXREG(SISPART1, 0x00, 0x00); 4451 SiS_SetReg(SISPART1, 0x00, 0x00);
4452 v1 = 0x40; v2 = 0x11; 4452 v1 = 0x40; v2 = 0x11;
4453 if(bios) { 4453 if(bios) {
4454 v1 = bios[0xec]; 4454 v1 = bios[0xec];
4455 v2 = bios[0xeb]; 4455 v2 = bios[0xeb];
4456 } 4456 }
4457 outSISIDXREG(SISPART1, 0x02, v1); 4457 SiS_SetReg(SISPART1, 0x02, v1);
4458 4458
4459 if(ivideo->revision_id >= 0x80) 4459 if(ivideo->revision_id >= 0x80)
4460 v2 &= ~0x01; 4460 v2 &= ~0x01;
4461 4461
4462 reg = SiS_GetReg(SISPART4, 0x00); 4462 reg = SiS_GetReg(SISPART4, 0x00);
4463 if((reg == 1) || (reg == 2)) { 4463 if((reg == 1) || (reg == 2)) {
4464 outSISIDXREG(SISCR, 0x37, 0x02); 4464 SiS_SetReg(SISCR, 0x37, 0x02);
4465 outSISIDXREG(SISPART2, 0x00, 0x1c); 4465 SiS_SetReg(SISPART2, 0x00, 0x1c);
4466 v4 = 0x00; v5 = 0x00; v6 = 0x10; 4466 v4 = 0x00; v5 = 0x00; v6 = 0x10;
4467 if(ivideo->SiS_Pr.UseROM) { 4467 if(ivideo->SiS_Pr.UseROM) {
4468 v4 = bios[0xf5]; 4468 v4 = bios[0xf5];
4469 v5 = bios[0xf6]; 4469 v5 = bios[0xf6];
4470 v6 = bios[0xf7]; 4470 v6 = bios[0xf7];
4471 } 4471 }
4472 outSISIDXREG(SISPART4, 0x0d, v4); 4472 SiS_SetReg(SISPART4, 0x0d, v4);
4473 outSISIDXREG(SISPART4, 0x0e, v5); 4473 SiS_SetReg(SISPART4, 0x0e, v5);
4474 outSISIDXREG(SISPART4, 0x10, v6); 4474 SiS_SetReg(SISPART4, 0x10, v6);
4475 outSISIDXREG(SISPART4, 0x0f, 0x3f); 4475 SiS_SetReg(SISPART4, 0x0f, 0x3f);
4476 reg = SiS_GetReg(SISPART4, 0x01); 4476 reg = SiS_GetReg(SISPART4, 0x01);
4477 if(reg >= 0xb0) { 4477 if(reg >= 0xb0) {
4478 reg = SiS_GetReg(SISPART4, 0x23); 4478 reg = SiS_GetReg(SISPART4, 0x23);
4479 reg &= 0x20; 4479 reg &= 0x20;
4480 reg <<= 1; 4480 reg <<= 1;
4481 outSISIDXREG(SISPART4, 0x23, reg); 4481 SiS_SetReg(SISPART4, 0x23, reg);
4482 } 4482 }
4483 } else { 4483 } else {
4484 v2 &= ~0x10; 4484 v2 &= ~0x10;
4485 } 4485 }
4486 outSISIDXREG(SISSR, 0x32, v2); 4486 SiS_SetReg(SISSR, 0x32, v2);
4487 4487
4488 andSISIDXREG(SISPART1, 0x24, 0xfe); /* Lock CRT2 */ 4488 andSISIDXREG(SISPART1, 0x24, 0xfe); /* Lock CRT2 */
4489 4489
4490 reg = SiS_GetReg(SISSR, 0x16); 4490 reg = SiS_GetReg(SISSR, 0x16);
4491 reg &= 0xc3; 4491 reg &= 0xc3;
4492 outSISIDXREG(SISCR, 0x35, reg); 4492 SiS_SetReg(SISCR, 0x35, reg);
4493 outSISIDXREG(SISCR, 0x83, 0x00); 4493 SiS_SetReg(SISCR, 0x83, 0x00);
4494#if !defined(__i386__) && !defined(__x86_64__) 4494#if !defined(__i386__) && !defined(__x86_64__)
4495 if(sisfb_videoram) { 4495 if(sisfb_videoram) {
4496 outSISIDXREG(SISSR, 0x13, 0x28); /* ? */ 4496 SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
4497 reg = ((sisfb_videoram >> 10) - 1) | 0x40; 4497 reg = ((sisfb_videoram >> 10) - 1) | 0x40;
4498 outSISIDXREG(SISSR, 0x14, reg); 4498 SiS_SetReg(SISSR, 0x14, reg);
4499 } else { 4499 } else {
4500#endif 4500#endif
4501 /* Need to map max FB size for finding out about RAM size */ 4501 /* Need to map max FB size for finding out about RAM size */
@@ -4508,8 +4508,8 @@ sisfb_post_sis300(struct pci_dev *pdev)
4508 } else { 4508 } else {
4509 printk(KERN_DEBUG 4509 printk(KERN_DEBUG
4510 "sisfb: Failed to map memory for size detection, assuming 8MB\n"); 4510 "sisfb: Failed to map memory for size detection, assuming 8MB\n");
4511 outSISIDXREG(SISSR, 0x13, 0x28); /* ? */ 4511 SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
4512 outSISIDXREG(SISSR, 0x14, 0x47); /* 8MB, 64bit default */ 4512 SiS_SetReg(SISSR, 0x14, 0x47); /* 8MB, 64bit default */
4513 } 4513 }
4514#if !defined(__i386__) && !defined(__x86_64__) 4514#if !defined(__i386__) && !defined(__x86_64__)
4515 } 4515 }
@@ -4527,8 +4527,8 @@ sisfb_post_sis300(struct pci_dev *pdev)
4527 v2 = 0xb2; 4527 v2 = 0xb2;
4528 } 4528 }
4529 } 4529 }
4530 outSISIDXREG(SISSR, 0x21, v1); 4530 SiS_SetReg(SISSR, 0x21, v1);
4531 outSISIDXREG(SISSR, 0x22, v2); 4531 SiS_SetReg(SISSR, 0x22, v2);
4532 4532
4533 /* Sense CRT1 */ 4533 /* Sense CRT1 */
4534 sisfb_sense_crt1(ivideo); 4534 sisfb_sense_crt1(ivideo);
@@ -4541,13 +4541,13 @@ sisfb_post_sis300(struct pci_dev *pdev)
4541 ivideo->SiS_Pr.VideoMemorySize = 8 << 20; 4541 ivideo->SiS_Pr.VideoMemorySize = 8 << 20;
4542 SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80); 4542 SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
4543 4543
4544 outSISIDXREG(SISSR, 0x05, 0x86); 4544 SiS_SetReg(SISSR, 0x05, 0x86);
4545 4545
4546 /* Display off */ 4546 /* Display off */
4547 orSISIDXREG(SISSR, 0x01, 0x20); 4547 orSISIDXREG(SISSR, 0x01, 0x20);
4548 4548
4549 /* Save mode number in CR34 */ 4549 /* Save mode number in CR34 */
4550 outSISIDXREG(SISCR, 0x34, 0x2e); 4550 SiS_SetReg(SISCR, 0x34, 0x2e);
4551 4551
4552 /* Let everyone know what the current mode is */ 4552 /* Let everyone know what the current mode is */
4553 ivideo->modeprechange = 0x2e; 4553 ivideo->modeprechange = 0x2e;
@@ -4670,16 +4670,16 @@ sisfb_post_xgi_ramsize(struct sis_video_info *ivideo)
4670 4670
4671 if(!ivideo->video_vbase) { 4671 if(!ivideo->video_vbase) {
4672 printk(KERN_ERR "sisfb: Unable to detect RAM size. Setting default.\n"); 4672 printk(KERN_ERR "sisfb: Unable to detect RAM size. Setting default.\n");
4673 outSISIDXREG(SISSR, 0x13, 0x35); 4673 SiS_SetReg(SISSR, 0x13, 0x35);
4674 outSISIDXREG(SISSR, 0x14, 0x41); 4674 SiS_SetReg(SISSR, 0x14, 0x41);
4675 /* TODO */ 4675 /* TODO */
4676 return; 4676 return;
4677 } 4677 }
4678 4678
4679 /* Non-interleaving */ 4679 /* Non-interleaving */
4680 outSISIDXREG(SISSR, 0x15, 0x00); 4680 SiS_SetReg(SISSR, 0x15, 0x00);
4681 /* No tiling */ 4681 /* No tiling */
4682 outSISIDXREG(SISSR, 0x1c, 0x00); 4682 SiS_SetReg(SISSR, 0x1c, 0x00);
4683 4683
4684 if(ivideo->chip == XGI_20) { 4684 if(ivideo->chip == XGI_20) {
4685 4685
@@ -4687,52 +4687,52 @@ sisfb_post_xgi_ramsize(struct sis_video_info *ivideo)
4687 reg = SiS_GetReg(SISCR, 0x97); 4687 reg = SiS_GetReg(SISCR, 0x97);
4688 if(!(reg & 0x01)) { /* Single 32/16 */ 4688 if(!(reg & 0x01)) { /* Single 32/16 */
4689 buswidth = 32; 4689 buswidth = 32;
4690 outSISIDXREG(SISSR, 0x13, 0xb1); 4690 SiS_SetReg(SISSR, 0x13, 0xb1);
4691 outSISIDXREG(SISSR, 0x14, 0x52); 4691 SiS_SetReg(SISSR, 0x14, 0x52);
4692 sisfb_post_xgi_delay(ivideo, 1); 4692 sisfb_post_xgi_delay(ivideo, 1);
4693 sr14 = 0x02; 4693 sr14 = 0x02;
4694 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) 4694 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
4695 goto bail_out; 4695 goto bail_out;
4696 4696
4697 outSISIDXREG(SISSR, 0x13, 0x31); 4697 SiS_SetReg(SISSR, 0x13, 0x31);
4698 outSISIDXREG(SISSR, 0x14, 0x42); 4698 SiS_SetReg(SISSR, 0x14, 0x42);
4699 sisfb_post_xgi_delay(ivideo, 1); 4699 sisfb_post_xgi_delay(ivideo, 1);
4700 if(sisfb_post_xgi_rwtest(ivideo, 23, 23, mapsize)) 4700 if(sisfb_post_xgi_rwtest(ivideo, 23, 23, mapsize))
4701 goto bail_out; 4701 goto bail_out;
4702 4702
4703 buswidth = 16; 4703 buswidth = 16;
4704 outSISIDXREG(SISSR, 0x13, 0xb1); 4704 SiS_SetReg(SISSR, 0x13, 0xb1);
4705 outSISIDXREG(SISSR, 0x14, 0x41); 4705 SiS_SetReg(SISSR, 0x14, 0x41);
4706 sisfb_post_xgi_delay(ivideo, 1); 4706 sisfb_post_xgi_delay(ivideo, 1);
4707 sr14 = 0x01; 4707 sr14 = 0x01;
4708 if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize)) 4708 if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
4709 goto bail_out; 4709 goto bail_out;
4710 else 4710 else
4711 outSISIDXREG(SISSR, 0x13, 0x31); 4711 SiS_SetReg(SISSR, 0x13, 0x31);
4712 } else { /* Dual 16/8 */ 4712 } else { /* Dual 16/8 */
4713 buswidth = 16; 4713 buswidth = 16;
4714 outSISIDXREG(SISSR, 0x13, 0xb1); 4714 SiS_SetReg(SISSR, 0x13, 0xb1);
4715 outSISIDXREG(SISSR, 0x14, 0x41); 4715 SiS_SetReg(SISSR, 0x14, 0x41);
4716 sisfb_post_xgi_delay(ivideo, 1); 4716 sisfb_post_xgi_delay(ivideo, 1);
4717 sr14 = 0x01; 4717 sr14 = 0x01;
4718 if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize)) 4718 if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
4719 goto bail_out; 4719 goto bail_out;
4720 4720
4721 outSISIDXREG(SISSR, 0x13, 0x31); 4721 SiS_SetReg(SISSR, 0x13, 0x31);
4722 outSISIDXREG(SISSR, 0x14, 0x31); 4722 SiS_SetReg(SISSR, 0x14, 0x31);
4723 sisfb_post_xgi_delay(ivideo, 1); 4723 sisfb_post_xgi_delay(ivideo, 1);
4724 if(sisfb_post_xgi_rwtest(ivideo, 22, 22, mapsize)) 4724 if(sisfb_post_xgi_rwtest(ivideo, 22, 22, mapsize))
4725 goto bail_out; 4725 goto bail_out;
4726 4726
4727 buswidth = 8; 4727 buswidth = 8;
4728 outSISIDXREG(SISSR, 0x13, 0xb1); 4728 SiS_SetReg(SISSR, 0x13, 0xb1);
4729 outSISIDXREG(SISSR, 0x14, 0x30); 4729 SiS_SetReg(SISSR, 0x14, 0x30);
4730 sisfb_post_xgi_delay(ivideo, 1); 4730 sisfb_post_xgi_delay(ivideo, 1);
4731 sr14 = 0x00; 4731 sr14 = 0x00;
4732 if(sisfb_post_xgi_rwtest(ivideo, 21, 22, mapsize)) 4732 if(sisfb_post_xgi_rwtest(ivideo, 21, 22, mapsize))
4733 goto bail_out; 4733 goto bail_out;
4734 else 4734 else
4735 outSISIDXREG(SISSR, 0x13, 0x31); 4735 SiS_SetReg(SISSR, 0x13, 0x31);
4736 } 4736 }
4737 4737
4738 } else { /* XGI_40 */ 4738 } else { /* XGI_40 */
@@ -4747,52 +4747,52 @@ sisfb_post_xgi_ramsize(struct sis_video_info *ivideo)
4747 buswidth = 32; 4747 buswidth = 32;
4748 if(ivideo->revision_id == 2) { 4748 if(ivideo->revision_id == 2) {
4749 channelab = 2; 4749 channelab = 2;
4750 outSISIDXREG(SISSR, 0x13, 0xa1); 4750 SiS_SetReg(SISSR, 0x13, 0xa1);
4751 outSISIDXREG(SISSR, 0x14, 0x44); 4751 SiS_SetReg(SISSR, 0x14, 0x44);
4752 sr14 = 0x04; 4752 sr14 = 0x04;
4753 sisfb_post_xgi_delay(ivideo, 1); 4753 sisfb_post_xgi_delay(ivideo, 1);
4754 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) 4754 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
4755 goto bail_out; 4755 goto bail_out;
4756 4756
4757 outSISIDXREG(SISSR, 0x13, 0x21); 4757 SiS_SetReg(SISSR, 0x13, 0x21);
4758 outSISIDXREG(SISSR, 0x14, 0x34); 4758 SiS_SetReg(SISSR, 0x14, 0x34);
4759 if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize)) 4759 if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
4760 goto bail_out; 4760 goto bail_out;
4761 4761
4762 channelab = 1; 4762 channelab = 1;
4763 outSISIDXREG(SISSR, 0x13, 0xa1); 4763 SiS_SetReg(SISSR, 0x13, 0xa1);
4764 outSISIDXREG(SISSR, 0x14, 0x40); 4764 SiS_SetReg(SISSR, 0x14, 0x40);
4765 sr14 = 0x00; 4765 sr14 = 0x00;
4766 if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize)) 4766 if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
4767 goto bail_out; 4767 goto bail_out;
4768 4768
4769 outSISIDXREG(SISSR, 0x13, 0x21); 4769 SiS_SetReg(SISSR, 0x13, 0x21);
4770 outSISIDXREG(SISSR, 0x14, 0x30); 4770 SiS_SetReg(SISSR, 0x14, 0x30);
4771 } else { 4771 } else {
4772 channelab = 3; 4772 channelab = 3;
4773 outSISIDXREG(SISSR, 0x13, 0xa1); 4773 SiS_SetReg(SISSR, 0x13, 0xa1);
4774 outSISIDXREG(SISSR, 0x14, 0x4c); 4774 SiS_SetReg(SISSR, 0x14, 0x4c);
4775 sr14 = 0x0c; 4775 sr14 = 0x0c;
4776 sisfb_post_xgi_delay(ivideo, 1); 4776 sisfb_post_xgi_delay(ivideo, 1);
4777 if(sisfb_post_xgi_rwtest(ivideo, 23, 25, mapsize)) 4777 if(sisfb_post_xgi_rwtest(ivideo, 23, 25, mapsize))
4778 goto bail_out; 4778 goto bail_out;
4779 4779
4780 channelab = 2; 4780 channelab = 2;
4781 outSISIDXREG(SISSR, 0x14, 0x48); 4781 SiS_SetReg(SISSR, 0x14, 0x48);
4782 sisfb_post_xgi_delay(ivideo, 1); 4782 sisfb_post_xgi_delay(ivideo, 1);
4783 sr14 = 0x08; 4783 sr14 = 0x08;
4784 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) 4784 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
4785 goto bail_out; 4785 goto bail_out;
4786 4786
4787 outSISIDXREG(SISSR, 0x13, 0x21); 4787 SiS_SetReg(SISSR, 0x13, 0x21);
4788 outSISIDXREG(SISSR, 0x14, 0x3c); 4788 SiS_SetReg(SISSR, 0x14, 0x3c);
4789 sr14 = 0x0c; 4789 sr14 = 0x0c;
4790 4790
4791 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) { 4791 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) {
4792 channelab = 3; 4792 channelab = 3;
4793 } else { 4793 } else {
4794 channelab = 2; 4794 channelab = 2;
4795 outSISIDXREG(SISSR, 0x14, 0x38); 4795 SiS_SetReg(SISSR, 0x14, 0x38);
4796 sr14 = 0x08; 4796 sr14 = 0x08;
4797 } 4797 }
4798 } 4798 }
@@ -4803,26 +4803,26 @@ sisfb_post_xgi_ramsize(struct sis_video_info *ivideo)
4803 buswidth = 64; 4803 buswidth = 64;
4804 if(ivideo->revision_id == 2) { 4804 if(ivideo->revision_id == 2) {
4805 channelab = 1; 4805 channelab = 1;
4806 outSISIDXREG(SISSR, 0x13, 0xa1); 4806 SiS_SetReg(SISSR, 0x13, 0xa1);
4807 outSISIDXREG(SISSR, 0x14, 0x52); 4807 SiS_SetReg(SISSR, 0x14, 0x52);
4808 sisfb_post_xgi_delay(ivideo, 1); 4808 sisfb_post_xgi_delay(ivideo, 1);
4809 sr14 = 0x02; 4809 sr14 = 0x02;
4810 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) 4810 if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
4811 goto bail_out; 4811 goto bail_out;
4812 4812
4813 outSISIDXREG(SISSR, 0x13, 0x21); 4813 SiS_SetReg(SISSR, 0x13, 0x21);
4814 outSISIDXREG(SISSR, 0x14, 0x42); 4814 SiS_SetReg(SISSR, 0x14, 0x42);
4815 } else { 4815 } else {
4816 channelab = 2; 4816 channelab = 2;
4817 outSISIDXREG(SISSR, 0x13, 0xa1); 4817 SiS_SetReg(SISSR, 0x13, 0xa1);
4818 outSISIDXREG(SISSR, 0x14, 0x5a); 4818 SiS_SetReg(SISSR, 0x14, 0x5a);
4819 sisfb_post_xgi_delay(ivideo, 1); 4819 sisfb_post_xgi_delay(ivideo, 1);
4820 sr14 = 0x0a; 4820 sr14 = 0x0a;
4821 if(sisfb_post_xgi_rwtest(ivideo, 24, 25, mapsize)) 4821 if(sisfb_post_xgi_rwtest(ivideo, 24, 25, mapsize))
4822 goto bail_out; 4822 goto bail_out;
4823 4823
4824 outSISIDXREG(SISSR, 0x13, 0x21); 4824 SiS_SetReg(SISSR, 0x13, 0x21);
4825 outSISIDXREG(SISSR, 0x14, 0x4a); 4825 SiS_SetReg(SISSR, 0x14, 0x4a);
4826 } 4826 }
4827 sisfb_post_xgi_delay(ivideo, 1); 4827 sisfb_post_xgi_delay(ivideo, 1);
4828 4828
@@ -4910,9 +4910,9 @@ sisfb_post_xgi_setclocks(struct sis_video_info *ivideo, u8 regb)
4910 v2 = ivideo->bios_abase[0x90 + index + 1]; 4910 v2 = ivideo->bios_abase[0x90 + index + 1];
4911 v3 = ivideo->bios_abase[0x90 + index + 2]; 4911 v3 = ivideo->bios_abase[0x90 + index + 2];
4912 } 4912 }
4913 outSISIDXREG(SISSR, 0x28, v1); 4913 SiS_SetReg(SISSR, 0x28, v1);
4914 outSISIDXREG(SISSR, 0x29, v2); 4914 SiS_SetReg(SISSR, 0x29, v2);
4915 outSISIDXREG(SISSR, 0x2a, v3); 4915 SiS_SetReg(SISSR, 0x2a, v3);
4916 sisfb_post_xgi_delay(ivideo, 0x43); 4916 sisfb_post_xgi_delay(ivideo, 0x43);
4917 sisfb_post_xgi_delay(ivideo, 0x43); 4917 sisfb_post_xgi_delay(ivideo, 0x43);
4918 sisfb_post_xgi_delay(ivideo, 0x43); 4918 sisfb_post_xgi_delay(ivideo, 0x43);
@@ -4923,9 +4923,9 @@ sisfb_post_xgi_setclocks(struct sis_video_info *ivideo, u8 regb)
4923 v2 = ivideo->bios_abase[0xb8 + index + 1]; 4923 v2 = ivideo->bios_abase[0xb8 + index + 1];
4924 v3 = ivideo->bios_abase[0xb8 + index + 2]; 4924 v3 = ivideo->bios_abase[0xb8 + index + 2];
4925 } 4925 }
4926 outSISIDXREG(SISSR, 0x2e, v1); 4926 SiS_SetReg(SISSR, 0x2e, v1);
4927 outSISIDXREG(SISSR, 0x2f, v2); 4927 SiS_SetReg(SISSR, 0x2f, v2);
4928 outSISIDXREG(SISSR, 0x30, v3); 4928 SiS_SetReg(SISSR, 0x30, v3);
4929 sisfb_post_xgi_delay(ivideo, 0x43); 4929 sisfb_post_xgi_delay(ivideo, 0x43);
4930 sisfb_post_xgi_delay(ivideo, 0x43); 4930 sisfb_post_xgi_delay(ivideo, 0x43);
4931 sisfb_post_xgi_delay(ivideo, 0x43); 4931 sisfb_post_xgi_delay(ivideo, 0x43);
@@ -5006,7 +5006,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5006 SiS_SetRegByte(SISMISCW, reg); 5006 SiS_SetRegByte(SISMISCW, reg);
5007 5007
5008 /* Unlock SR */ 5008 /* Unlock SR */
5009 outSISIDXREG(SISSR, 0x05, 0x86); 5009 SiS_SetReg(SISSR, 0x05, 0x86);
5010 reg = SiS_GetReg(SISSR, 0x05); 5010 reg = SiS_GetReg(SISSR, 0x05);
5011 if(reg != 0xa1) 5011 if(reg != 0xa1)
5012 return 0; 5012 return 0;
@@ -5014,13 +5014,13 @@ sisfb_post_xgi(struct pci_dev *pdev)
5014 /* Clear some regs */ 5014 /* Clear some regs */
5015 for(i = 0; i < 0x22; i++) { 5015 for(i = 0; i < 0x22; i++) {
5016 if(0x06 + i == 0x20) continue; 5016 if(0x06 + i == 0x20) continue;
5017 outSISIDXREG(SISSR, 0x06 + i, 0x00); 5017 SiS_SetReg(SISSR, 0x06 + i, 0x00);
5018 } 5018 }
5019 for(i = 0; i < 0x0b; i++) { 5019 for(i = 0; i < 0x0b; i++) {
5020 outSISIDXREG(SISSR, 0x31 + i, 0x00); 5020 SiS_SetReg(SISSR, 0x31 + i, 0x00);
5021 } 5021 }
5022 for(i = 0; i < 0x10; i++) { 5022 for(i = 0; i < 0x10; i++) {
5023 outSISIDXREG(SISCR, 0x30 + i, 0x00); 5023 SiS_SetReg(SISCR, 0x30 + i, 0x00);
5024 } 5024 }
5025 5025
5026 ptr = cs78; 5026 ptr = cs78;
@@ -5028,7 +5028,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5028 ptr = (const u8 *)&bios[0x78]; 5028 ptr = (const u8 *)&bios[0x78];
5029 } 5029 }
5030 for(i = 0; i < 3; i++) { 5030 for(i = 0; i < 3; i++) {
5031 outSISIDXREG(SISSR, 0x23 + i, ptr[i]); 5031 SiS_SetReg(SISSR, 0x23 + i, ptr[i]);
5032 } 5032 }
5033 5033
5034 ptr = cs76; 5034 ptr = cs76;
@@ -5036,7 +5036,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5036 ptr = (const u8 *)&bios[0x76]; 5036 ptr = (const u8 *)&bios[0x76];
5037 } 5037 }
5038 for(i = 0; i < 2; i++) { 5038 for(i = 0; i < 2; i++) {
5039 outSISIDXREG(SISSR, 0x21 + i, ptr[i]); 5039 SiS_SetReg(SISSR, 0x21 + i, ptr[i]);
5040 } 5040 }
5041 5041
5042 v1 = 0x18; v2 = 0x00; 5042 v1 = 0x18; v2 = 0x00;
@@ -5044,27 +5044,27 @@ sisfb_post_xgi(struct pci_dev *pdev)
5044 v1 = bios[0x74]; 5044 v1 = bios[0x74];
5045 v2 = bios[0x75]; 5045 v2 = bios[0x75];
5046 } 5046 }
5047 outSISIDXREG(SISSR, 0x07, v1); 5047 SiS_SetReg(SISSR, 0x07, v1);
5048 outSISIDXREG(SISSR, 0x11, 0x0f); 5048 SiS_SetReg(SISSR, 0x11, 0x0f);
5049 outSISIDXREG(SISSR, 0x1f, v2); 5049 SiS_SetReg(SISSR, 0x1f, v2);
5050 /* PCI linear mode, RelIO enabled, A0000 decoding disabled */ 5050 /* PCI linear mode, RelIO enabled, A0000 decoding disabled */
5051 outSISIDXREG(SISSR, 0x20, 0x80 | 0x20 | 0x04); 5051 SiS_SetReg(SISSR, 0x20, 0x80 | 0x20 | 0x04);
5052 outSISIDXREG(SISSR, 0x27, 0x74); 5052 SiS_SetReg(SISSR, 0x27, 0x74);
5053 5053
5054 ptr = cs7b; 5054 ptr = cs7b;
5055 if(ivideo->haveXGIROM) { 5055 if(ivideo->haveXGIROM) {
5056 ptr = (const u8 *)&bios[0x7b]; 5056 ptr = (const u8 *)&bios[0x7b];
5057 } 5057 }
5058 for(i = 0; i < 3; i++) { 5058 for(i = 0; i < 3; i++) {
5059 outSISIDXREG(SISSR, 0x31 + i, ptr[i]); 5059 SiS_SetReg(SISSR, 0x31 + i, ptr[i]);
5060 } 5060 }
5061 5061
5062 if(ivideo->chip == XGI_40) { 5062 if(ivideo->chip == XGI_40) {
5063 if(ivideo->revision_id == 2) { 5063 if(ivideo->revision_id == 2) {
5064 setSISIDXREG(SISSR, 0x3b, 0x3f, 0xc0); 5064 setSISIDXREG(SISSR, 0x3b, 0x3f, 0xc0);
5065 } 5065 }
5066 outSISIDXREG(SISCR, 0x7d, 0xfe); 5066 SiS_SetReg(SISCR, 0x7d, 0xfe);
5067 outSISIDXREG(SISCR, 0x7e, 0x0f); 5067 SiS_SetReg(SISCR, 0x7e, 0x0f);
5068 } 5068 }
5069 if(ivideo->revision_id == 0) { /* 40 *and* 20? */ 5069 if(ivideo->revision_id == 0) { /* 40 *and* 20? */
5070 andSISIDXREG(SISCR, 0x58, 0xd7); 5070 andSISIDXREG(SISCR, 0x58, 0xd7);
@@ -5078,36 +5078,36 @@ sisfb_post_xgi(struct pci_dev *pdev)
5078 setSISIDXREG(SISCR, 0x38, 0x1f, reg); 5078 setSISIDXREG(SISCR, 0x38, 0x1f, reg);
5079 5079
5080 if(ivideo->chip == XGI_20) { 5080 if(ivideo->chip == XGI_20) {
5081 outSISIDXREG(SISSR, 0x36, 0x70); 5081 SiS_SetReg(SISSR, 0x36, 0x70);
5082 } else { 5082 } else {
5083 outSISIDXREG(SISVID, 0x00, 0x86); 5083 SiS_SetReg(SISVID, 0x00, 0x86);
5084 outSISIDXREG(SISVID, 0x32, 0x00); 5084 SiS_SetReg(SISVID, 0x32, 0x00);
5085 outSISIDXREG(SISVID, 0x30, 0x00); 5085 SiS_SetReg(SISVID, 0x30, 0x00);
5086 outSISIDXREG(SISVID, 0x32, 0x01); 5086 SiS_SetReg(SISVID, 0x32, 0x01);
5087 outSISIDXREG(SISVID, 0x30, 0x00); 5087 SiS_SetReg(SISVID, 0x30, 0x00);
5088 andSISIDXREG(SISVID, 0x2f, 0xdf); 5088 andSISIDXREG(SISVID, 0x2f, 0xdf);
5089 andSISIDXREG(SISCAP, 0x00, 0x3f); 5089 andSISIDXREG(SISCAP, 0x00, 0x3f);
5090 5090
5091 outSISIDXREG(SISPART1, 0x2f, 0x01); 5091 SiS_SetReg(SISPART1, 0x2f, 0x01);
5092 outSISIDXREG(SISPART1, 0x00, 0x00); 5092 SiS_SetReg(SISPART1, 0x00, 0x00);
5093 outSISIDXREG(SISPART1, 0x02, bios[0x7e]); 5093 SiS_SetReg(SISPART1, 0x02, bios[0x7e]);
5094 outSISIDXREG(SISPART1, 0x2e, 0x08); 5094 SiS_SetReg(SISPART1, 0x2e, 0x08);
5095 andSISIDXREG(SISPART1, 0x35, 0x7f); 5095 andSISIDXREG(SISPART1, 0x35, 0x7f);
5096 andSISIDXREG(SISPART1, 0x50, 0xfe); 5096 andSISIDXREG(SISPART1, 0x50, 0xfe);
5097 5097
5098 reg = SiS_GetReg(SISPART4, 0x00); 5098 reg = SiS_GetReg(SISPART4, 0x00);
5099 if(reg == 1 || reg == 2) { 5099 if(reg == 1 || reg == 2) {
5100 outSISIDXREG(SISPART2, 0x00, 0x1c); 5100 SiS_SetReg(SISPART2, 0x00, 0x1c);
5101 outSISIDXREG(SISPART4, 0x0d, bios[0x7f]); 5101 SiS_SetReg(SISPART4, 0x0d, bios[0x7f]);
5102 outSISIDXREG(SISPART4, 0x0e, bios[0x80]); 5102 SiS_SetReg(SISPART4, 0x0e, bios[0x80]);
5103 outSISIDXREG(SISPART4, 0x10, bios[0x81]); 5103 SiS_SetReg(SISPART4, 0x10, bios[0x81]);
5104 andSISIDXREG(SISPART4, 0x0f, 0x3f); 5104 andSISIDXREG(SISPART4, 0x0f, 0x3f);
5105 5105
5106 reg = SiS_GetReg(SISPART4, 0x01); 5106 reg = SiS_GetReg(SISPART4, 0x01);
5107 if((reg & 0xf0) >= 0xb0) { 5107 if((reg & 0xf0) >= 0xb0) {
5108 reg = SiS_GetReg(SISPART4, 0x23); 5108 reg = SiS_GetReg(SISPART4, 0x23);
5109 if(reg & 0x20) reg |= 0x40; 5109 if(reg & 0x20) reg |= 0x40;
5110 outSISIDXREG(SISPART4, 0x23, reg); 5110 SiS_SetReg(SISPART4, 0x23, reg);
5111 reg = (reg & 0x20) ? 0x02 : 0x00; 5111 reg = (reg & 0x20) ? 0x02 : 0x00;
5112 setSISIDXREG(SISPART1, 0x1e, 0xfd, reg); 5112 setSISIDXREG(SISPART1, 0x1e, 0xfd, reg);
5113 } 5113 }
@@ -5155,7 +5155,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5155 } 5155 }
5156 setSISIDXREG(SISCR, 0x5f, 0xf0, v2); 5156 setSISIDXREG(SISCR, 0x5f, 0xf0, v2);
5157 } 5157 }
5158 outSISIDXREG(SISSR, 0x22, v1); 5158 SiS_SetReg(SISSR, 0x22, v1);
5159 5159
5160 if(ivideo->revision_id == 2) { 5160 if(ivideo->revision_id == 2) {
5161 v1 = SiS_GetReg(SISSR, 0x3b); 5161 v1 = SiS_GetReg(SISSR, 0x3b);
@@ -5179,7 +5179,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5179 v2 = SiS_GetReg(SISCR, 0x5f); 5179 v2 = SiS_GetReg(SISCR, 0x5f);
5180 if((!(reg & 0x02)) && (v2 & 0x0e)) 5180 if((!(reg & 0x02)) && (v2 & 0x0e))
5181 v1 |= 0x08; 5181 v1 |= 0x08;
5182 outSISIDXREG(SISSR, 0x27, v1); 5182 SiS_SetReg(SISSR, 0x27, v1);
5183 5183
5184 if(bios[0x64] & 0x01) { 5184 if(bios[0x64] & 0x01) {
5185 setSISIDXREG(SISCR, 0x5f, 0xf0, bios[0x64]); 5185 setSISIDXREG(SISCR, 0x5f, 0xf0, bios[0x64]);
@@ -5192,16 +5192,16 @@ sisfb_post_xgi(struct pci_dev *pdev)
5192 v1 &= 0xfc; 5192 v1 &= 0xfc;
5193 orSISIDXREG(SISCR, 0x5f, 0x08); 5193 orSISIDXREG(SISCR, 0x5f, 0x08);
5194 } 5194 }
5195 outSISIDXREG(SISCR, 0x48, v1); 5195 SiS_SetReg(SISCR, 0x48, v1);
5196 5196
5197 setSISIDXREG(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb); 5197 setSISIDXREG(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb);
5198 setSISIDXREG(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f); 5198 setSISIDXREG(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f);
5199 setSISIDXREG(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f); 5199 setSISIDXREG(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f);
5200 setSISIDXREG(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7); 5200 setSISIDXREG(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7);
5201 setSISIDXREG(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f); 5201 setSISIDXREG(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f);
5202 outSISIDXREG(SISCR, 0x70, bios[0x4fc]); 5202 SiS_SetReg(SISCR, 0x70, bios[0x4fc]);
5203 setSISIDXREG(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f); 5203 setSISIDXREG(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f);
5204 outSISIDXREG(SISCR, 0x74, 0xd0); 5204 SiS_SetReg(SISCR, 0x74, 0xd0);
5205 setSISIDXREG(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30); 5205 setSISIDXREG(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30);
5206 setSISIDXREG(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f); 5206 setSISIDXREG(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f);
5207 setSISIDXREG(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f); 5207 setSISIDXREG(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f);
@@ -5210,7 +5210,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5210 v1 = 0xf0; 5210 v1 = 0xf0;
5211 pci_dev_put(mypdev); 5211 pci_dev_put(mypdev);
5212 } 5212 }
5213 outSISIDXREG(SISCR, 0x77, v1); 5213 SiS_SetReg(SISCR, 0x77, v1);
5214 } 5214 }
5215 5215
5216 /* RAM type */ 5216 /* RAM type */
@@ -5221,14 +5221,14 @@ sisfb_post_xgi(struct pci_dev *pdev)
5221 if(ivideo->haveXGIROM) { 5221 if(ivideo->haveXGIROM) {
5222 v1 = bios[0x140 + regb]; 5222 v1 = bios[0x140 + regb];
5223 } 5223 }
5224 outSISIDXREG(SISCR, 0x6d, v1); 5224 SiS_SetReg(SISCR, 0x6d, v1);
5225 5225
5226 ptr = cs128; 5226 ptr = cs128;
5227 if(ivideo->haveXGIROM) { 5227 if(ivideo->haveXGIROM) {
5228 ptr = (const u8 *)&bios[0x128]; 5228 ptr = (const u8 *)&bios[0x128];
5229 } 5229 }
5230 for(i = 0, j = 0; i < 3; i++, j += 8) { 5230 for(i = 0, j = 0; i < 3; i++, j += 8) {
5231 outSISIDXREG(SISCR, 0x68 + i, ptr[j + regb]); 5231 SiS_SetReg(SISCR, 0x68 + i, ptr[j + regb]);
5232 } 5232 }
5233 5233
5234 ptr = cs31a; 5234 ptr = cs31a;
@@ -5252,7 +5252,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5252 if(regd & 0x01) reg |= 0x04; 5252 if(regd & 0x01) reg |= 0x04;
5253 if(regd & 0x02) reg |= 0x08; 5253 if(regd & 0x02) reg |= 0x08;
5254 regd >>= 2; 5254 regd >>= 2;
5255 outSISIDXREG(SISCR, rega, reg); 5255 SiS_SetReg(SISCR, rega, reg);
5256 reg = SiS_GetReg(SISCR, rega); 5256 reg = SiS_GetReg(SISCR, rega);
5257 reg = SiS_GetReg(SISCR, rega); 5257 reg = SiS_GetReg(SISCR, rega);
5258 reg += 0x10; 5258 reg += 0x10;
@@ -5281,7 +5281,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5281 if(regd & 0x01) reg |= 0x01; 5281 if(regd & 0x01) reg |= 0x01;
5282 if(regd & 0x02) reg |= 0x02; 5282 if(regd & 0x02) reg |= 0x02;
5283 regd >>= 2; 5283 regd >>= 2;
5284 outSISIDXREG(SISCR, 0x6f, reg); 5284 SiS_SetReg(SISCR, 0x6f, reg);
5285 reg = SiS_GetReg(SISCR, 0x6f); 5285 reg = SiS_GetReg(SISCR, 0x6f);
5286 reg = SiS_GetReg(SISCR, 0x6f); 5286 reg = SiS_GetReg(SISCR, 0x6f);
5287 reg += 0x08; 5287 reg += 0x08;
@@ -5294,7 +5294,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5294 ptr = (const u8 *)&bios[0x148]; 5294 ptr = (const u8 *)&bios[0x148];
5295 } 5295 }
5296 for(i = 0, j = 0; i < 2; i++, j += 8) { 5296 for(i = 0, j = 0; i < 2; i++, j += 8) {
5297 outSISIDXREG(SISCR, 0x80 + i, ptr[j + regb]); 5297 SiS_SetReg(SISCR, 0x80 + i, ptr[j + regb]);
5298 } 5298 }
5299 5299
5300 andSISIDXREG(SISCR, 0x89, 0x8f); 5300 andSISIDXREG(SISCR, 0x89, 0x8f);
@@ -5311,7 +5311,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5311 if(regd & 0x01) reg |= 0x01; 5311 if(regd & 0x01) reg |= 0x01;
5312 if(regd & 0x02) reg |= 0x02; 5312 if(regd & 0x02) reg |= 0x02;
5313 regd >>= 2; 5313 regd >>= 2;
5314 outSISIDXREG(SISCR, 0x89, reg); 5314 SiS_SetReg(SISCR, 0x89, reg);
5315 reg = SiS_GetReg(SISCR, 0x89); 5315 reg = SiS_GetReg(SISCR, 0x89);
5316 reg = SiS_GetReg(SISCR, 0x89); 5316 reg = SiS_GetReg(SISCR, 0x89);
5317 reg += 0x10; 5317 reg += 0x10;
@@ -5324,27 +5324,27 @@ sisfb_post_xgi(struct pci_dev *pdev)
5324 v3 = bios[0x120 + regb]; 5324 v3 = bios[0x120 + regb];
5325 v4 = bios[0x1ca]; 5325 v4 = bios[0x1ca];
5326 } 5326 }
5327 outSISIDXREG(SISCR, 0x45, v1 & 0x0f); 5327 SiS_SetReg(SISCR, 0x45, v1 & 0x0f);
5328 outSISIDXREG(SISCR, 0x99, (v1 >> 4) & 0x07); 5328 SiS_SetReg(SISCR, 0x99, (v1 >> 4) & 0x07);
5329 orSISIDXREG(SISCR, 0x40, v1 & 0x80); 5329 orSISIDXREG(SISCR, 0x40, v1 & 0x80);
5330 outSISIDXREG(SISCR, 0x41, v2); 5330 SiS_SetReg(SISCR, 0x41, v2);
5331 5331
5332 ptr = cs170; 5332 ptr = cs170;
5333 if(ivideo->haveXGIROM) { 5333 if(ivideo->haveXGIROM) {
5334 ptr = (const u8 *)&bios[0x170]; 5334 ptr = (const u8 *)&bios[0x170];
5335 } 5335 }
5336 for(i = 0, j = 0; i < 7; i++, j += 8) { 5336 for(i = 0, j = 0; i < 7; i++, j += 8) {
5337 outSISIDXREG(SISCR, 0x90 + i, ptr[j + regb]); 5337 SiS_SetReg(SISCR, 0x90 + i, ptr[j + regb]);
5338 } 5338 }
5339 5339
5340 outSISIDXREG(SISCR, 0x59, v3); 5340 SiS_SetReg(SISCR, 0x59, v3);
5341 5341
5342 ptr = cs1a8; 5342 ptr = cs1a8;
5343 if(ivideo->haveXGIROM) { 5343 if(ivideo->haveXGIROM) {
5344 ptr = (const u8 *)&bios[0x1a8]; 5344 ptr = (const u8 *)&bios[0x1a8];
5345 } 5345 }
5346 for(i = 0, j = 0; i < 3; i++, j += 8) { 5346 for(i = 0, j = 0; i < 3; i++, j += 8) {
5347 outSISIDXREG(SISCR, 0xc3 + i, ptr[j + regb]); 5347 SiS_SetReg(SISCR, 0xc3 + i, ptr[j + regb]);
5348 } 5348 }
5349 5349
5350 ptr = cs100; 5350 ptr = cs100;
@@ -5352,27 +5352,27 @@ sisfb_post_xgi(struct pci_dev *pdev)
5352 ptr = (const u8 *)&bios[0x100]; 5352 ptr = (const u8 *)&bios[0x100];
5353 } 5353 }
5354 for(i = 0, j = 0; i < 2; i++, j += 8) { 5354 for(i = 0, j = 0; i < 2; i++, j += 8) {
5355 outSISIDXREG(SISCR, 0x8a + i, ptr[j + regb]); 5355 SiS_SetReg(SISCR, 0x8a + i, ptr[j + regb]);
5356 } 5356 }
5357 5357
5358 outSISIDXREG(SISCR, 0xcf, v4); 5358 SiS_SetReg(SISCR, 0xcf, v4);
5359 5359
5360 outSISIDXREG(SISCR, 0x83, 0x09); 5360 SiS_SetReg(SISCR, 0x83, 0x09);
5361 outSISIDXREG(SISCR, 0x87, 0x00); 5361 SiS_SetReg(SISCR, 0x87, 0x00);
5362 5362
5363 if(ivideo->chip == XGI_40) { 5363 if(ivideo->chip == XGI_40) {
5364 if( (ivideo->revision_id == 1) || 5364 if( (ivideo->revision_id == 1) ||
5365 (ivideo->revision_id == 2) ) { 5365 (ivideo->revision_id == 2) ) {
5366 outSISIDXREG(SISCR, 0x8c, 0x87); 5366 SiS_SetReg(SISCR, 0x8c, 0x87);
5367 } 5367 }
5368 } 5368 }
5369 5369
5370 outSISIDXREG(SISSR, 0x17, 0x00); 5370 SiS_SetReg(SISSR, 0x17, 0x00);
5371 outSISIDXREG(SISSR, 0x1a, 0x87); 5371 SiS_SetReg(SISSR, 0x1a, 0x87);
5372 5372
5373 if(ivideo->chip == XGI_20) { 5373 if(ivideo->chip == XGI_20) {
5374 outSISIDXREG(SISSR, 0x15, 0x00); 5374 SiS_SetReg(SISSR, 0x15, 0x00);
5375 outSISIDXREG(SISSR, 0x1c, 0x00); 5375 SiS_SetReg(SISSR, 0x1c, 0x00);
5376 } 5376 }
5377 5377
5378 ramtype = 0x00; v1 = 0x10; 5378 ramtype = 0x00; v1 = 0x10;
@@ -5382,7 +5382,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5382 } 5382 }
5383 if(!(ramtype & 0x80)) { 5383 if(!(ramtype & 0x80)) {
5384 if(ivideo->chip == XGI_20) { 5384 if(ivideo->chip == XGI_20) {
5385 outSISIDXREG(SISCR, 0x97, v1); 5385 SiS_SetReg(SISCR, 0x97, v1);
5386 reg = SiS_GetReg(SISCR, 0x97); 5386 reg = SiS_GetReg(SISCR, 0x97);
5387 if(reg & 0x10) { 5387 if(reg & 0x10) {
5388 ramtype = (reg & 0x01) << 1; 5388 ramtype = (reg & 0x01) << 1;
@@ -5412,55 +5412,55 @@ sisfb_post_xgi(struct pci_dev *pdev)
5412 v2 = bios[regb + 0x160]; 5412 v2 = bios[regb + 0x160];
5413 v3 = bios[regb + 0x168]; 5413 v3 = bios[regb + 0x168];
5414 } 5414 }
5415 outSISIDXREG(SISCR, 0x82, v1); 5415 SiS_SetReg(SISCR, 0x82, v1);
5416 outSISIDXREG(SISCR, 0x85, v2); 5416 SiS_SetReg(SISCR, 0x85, v2);
5417 outSISIDXREG(SISCR, 0x86, v3); 5417 SiS_SetReg(SISCR, 0x86, v3);
5418 } else { 5418 } else {
5419 outSISIDXREG(SISCR, 0x82, 0x88); 5419 SiS_SetReg(SISCR, 0x82, 0x88);
5420 outSISIDXREG(SISCR, 0x86, 0x00); 5420 SiS_SetReg(SISCR, 0x86, 0x00);
5421 reg = SiS_GetReg(SISCR, 0x86); 5421 reg = SiS_GetReg(SISCR, 0x86);
5422 outSISIDXREG(SISCR, 0x86, 0x88); 5422 SiS_SetReg(SISCR, 0x86, 0x88);
5423 reg = SiS_GetReg(SISCR, 0x86); 5423 reg = SiS_GetReg(SISCR, 0x86);
5424 outSISIDXREG(SISCR, 0x86, bios[regb + 0x168]); 5424 SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
5425 outSISIDXREG(SISCR, 0x82, 0x77); 5425 SiS_SetReg(SISCR, 0x82, 0x77);
5426 outSISIDXREG(SISCR, 0x85, 0x00); 5426 SiS_SetReg(SISCR, 0x85, 0x00);
5427 reg = SiS_GetReg(SISCR, 0x85); 5427 reg = SiS_GetReg(SISCR, 0x85);
5428 outSISIDXREG(SISCR, 0x85, 0x88); 5428 SiS_SetReg(SISCR, 0x85, 0x88);
5429 reg = SiS_GetReg(SISCR, 0x85); 5429 reg = SiS_GetReg(SISCR, 0x85);
5430 outSISIDXREG(SISCR, 0x85, bios[regb + 0x160]); 5430 SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
5431 outSISIDXREG(SISCR, 0x82, bios[regb + 0x158]); 5431 SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
5432 } 5432 }
5433 if(ivideo->chip == XGI_40) { 5433 if(ivideo->chip == XGI_40) {
5434 outSISIDXREG(SISCR, 0x97, 0x00); 5434 SiS_SetReg(SISCR, 0x97, 0x00);
5435 } 5435 }
5436 outSISIDXREG(SISCR, 0x98, 0x01); 5436 SiS_SetReg(SISCR, 0x98, 0x01);
5437 outSISIDXREG(SISCR, 0x9a, 0x02); 5437 SiS_SetReg(SISCR, 0x9a, 0x02);
5438 5438
5439 outSISIDXREG(SISSR, 0x18, 0x01); 5439 SiS_SetReg(SISSR, 0x18, 0x01);
5440 if((ivideo->chip == XGI_20) || 5440 if((ivideo->chip == XGI_20) ||
5441 (ivideo->revision_id == 2)) { 5441 (ivideo->revision_id == 2)) {
5442 outSISIDXREG(SISSR, 0x19, 0x40); 5442 SiS_SetReg(SISSR, 0x19, 0x40);
5443 } else { 5443 } else {
5444 outSISIDXREG(SISSR, 0x19, 0x20); 5444 SiS_SetReg(SISSR, 0x19, 0x20);
5445 } 5445 }
5446 outSISIDXREG(SISSR, 0x16, 0x00); 5446 SiS_SetReg(SISSR, 0x16, 0x00);
5447 outSISIDXREG(SISSR, 0x16, 0x80); 5447 SiS_SetReg(SISSR, 0x16, 0x80);
5448 if((ivideo->chip == XGI_20) || (bios[0x1cb] != 0x0c)) { 5448 if((ivideo->chip == XGI_20) || (bios[0x1cb] != 0x0c)) {
5449 sisfb_post_xgi_delay(ivideo, 0x43); 5449 sisfb_post_xgi_delay(ivideo, 0x43);
5450 sisfb_post_xgi_delay(ivideo, 0x43); 5450 sisfb_post_xgi_delay(ivideo, 0x43);
5451 sisfb_post_xgi_delay(ivideo, 0x43); 5451 sisfb_post_xgi_delay(ivideo, 0x43);
5452 outSISIDXREG(SISSR, 0x18, 0x00); 5452 SiS_SetReg(SISSR, 0x18, 0x00);
5453 if((ivideo->chip == XGI_20) || 5453 if((ivideo->chip == XGI_20) ||
5454 (ivideo->revision_id == 2)) { 5454 (ivideo->revision_id == 2)) {
5455 outSISIDXREG(SISSR, 0x19, 0x40); 5455 SiS_SetReg(SISSR, 0x19, 0x40);
5456 } else { 5456 } else {
5457 outSISIDXREG(SISSR, 0x19, 0x20); 5457 SiS_SetReg(SISSR, 0x19, 0x20);
5458 } 5458 }
5459 } else if((ivideo->chip == XGI_40) && (bios[0x1cb] == 0x0c)) { 5459 } else if((ivideo->chip == XGI_40) && (bios[0x1cb] == 0x0c)) {
5460 /* outSISIDXREG(SISSR, 0x16, 0x0c); */ /* ? */ 5460 /* SiS_SetReg(SISSR, 0x16, 0x0c); */ /* ? */
5461 } 5461 }
5462 outSISIDXREG(SISSR, 0x16, 0x00); 5462 SiS_SetReg(SISSR, 0x16, 0x00);
5463 outSISIDXREG(SISSR, 0x16, 0x80); 5463 SiS_SetReg(SISSR, 0x16, 0x80);
5464 sisfb_post_xgi_delay(ivideo, 4); 5464 sisfb_post_xgi_delay(ivideo, 4);
5465 v1 = 0x31; v2 = 0x03; v3 = 0x83; v4 = 0x03; v5 = 0x83; 5465 v1 = 0x31; v2 = 0x03; v3 = 0x83; v4 = 0x03; v5 = 0x83;
5466 if(ivideo->haveXGIROM) { 5466 if(ivideo->haveXGIROM) {
@@ -5471,24 +5471,24 @@ sisfb_post_xgi(struct pci_dev *pdev)
5471 v4 = bios[index + 2]; 5471 v4 = bios[index + 2];
5472 v5 = bios[index + 3]; 5472 v5 = bios[index + 3];
5473 } 5473 }
5474 outSISIDXREG(SISSR, 0x18, v1); 5474 SiS_SetReg(SISSR, 0x18, v1);
5475 outSISIDXREG(SISSR, 0x19, ((ivideo->chip == XGI_20) ? 0x02 : 0x01)); 5475 SiS_SetReg(SISSR, 0x19, ((ivideo->chip == XGI_20) ? 0x02 : 0x01));
5476 outSISIDXREG(SISSR, 0x16, v2); 5476 SiS_SetReg(SISSR, 0x16, v2);
5477 outSISIDXREG(SISSR, 0x16, v3); 5477 SiS_SetReg(SISSR, 0x16, v3);
5478 sisfb_post_xgi_delay(ivideo, 0x43); 5478 sisfb_post_xgi_delay(ivideo, 0x43);
5479 outSISIDXREG(SISSR, 0x1b, 0x03); 5479 SiS_SetReg(SISSR, 0x1b, 0x03);
5480 sisfb_post_xgi_delay(ivideo, 0x22); 5480 sisfb_post_xgi_delay(ivideo, 0x22);
5481 outSISIDXREG(SISSR, 0x18, v1); 5481 SiS_SetReg(SISSR, 0x18, v1);
5482 outSISIDXREG(SISSR, 0x19, 0x00); 5482 SiS_SetReg(SISSR, 0x19, 0x00);
5483 outSISIDXREG(SISSR, 0x16, v4); 5483 SiS_SetReg(SISSR, 0x16, v4);
5484 outSISIDXREG(SISSR, 0x16, v5); 5484 SiS_SetReg(SISSR, 0x16, v5);
5485 outSISIDXREG(SISSR, 0x1b, 0x00); 5485 SiS_SetReg(SISSR, 0x1b, 0x00);
5486 break; 5486 break;
5487 case 1: 5487 case 1:
5488 outSISIDXREG(SISCR, 0x82, 0x77); 5488 SiS_SetReg(SISCR, 0x82, 0x77);
5489 outSISIDXREG(SISCR, 0x86, 0x00); 5489 SiS_SetReg(SISCR, 0x86, 0x00);
5490 reg = SiS_GetReg(SISCR, 0x86); 5490 reg = SiS_GetReg(SISCR, 0x86);
5491 outSISIDXREG(SISCR, 0x86, 0x88); 5491 SiS_SetReg(SISCR, 0x86, 0x88);
5492 reg = SiS_GetReg(SISCR, 0x86); 5492 reg = SiS_GetReg(SISCR, 0x86);
5493 v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb]; 5493 v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb];
5494 if(ivideo->haveXGIROM) { 5494 if(ivideo->haveXGIROM) {
@@ -5496,49 +5496,49 @@ sisfb_post_xgi(struct pci_dev *pdev)
5496 v2 = bios[regb + 0x160]; 5496 v2 = bios[regb + 0x160];
5497 v3 = bios[regb + 0x158]; 5497 v3 = bios[regb + 0x158];
5498 } 5498 }
5499 outSISIDXREG(SISCR, 0x86, v1); 5499 SiS_SetReg(SISCR, 0x86, v1);
5500 outSISIDXREG(SISCR, 0x82, 0x77); 5500 SiS_SetReg(SISCR, 0x82, 0x77);
5501 outSISIDXREG(SISCR, 0x85, 0x00); 5501 SiS_SetReg(SISCR, 0x85, 0x00);
5502 reg = SiS_GetReg(SISCR, 0x85); 5502 reg = SiS_GetReg(SISCR, 0x85);
5503 outSISIDXREG(SISCR, 0x85, 0x88); 5503 SiS_SetReg(SISCR, 0x85, 0x88);
5504 reg = SiS_GetReg(SISCR, 0x85); 5504 reg = SiS_GetReg(SISCR, 0x85);
5505 outSISIDXREG(SISCR, 0x85, v2); 5505 SiS_SetReg(SISCR, 0x85, v2);
5506 outSISIDXREG(SISCR, 0x82, v3); 5506 SiS_SetReg(SISCR, 0x82, v3);
5507 outSISIDXREG(SISCR, 0x98, 0x01); 5507 SiS_SetReg(SISCR, 0x98, 0x01);
5508 outSISIDXREG(SISCR, 0x9a, 0x02); 5508 SiS_SetReg(SISCR, 0x9a, 0x02);
5509 5509
5510 outSISIDXREG(SISSR, 0x28, 0x64); 5510 SiS_SetReg(SISSR, 0x28, 0x64);
5511 outSISIDXREG(SISSR, 0x29, 0x63); 5511 SiS_SetReg(SISSR, 0x29, 0x63);
5512 sisfb_post_xgi_delay(ivideo, 15); 5512 sisfb_post_xgi_delay(ivideo, 15);
5513 outSISIDXREG(SISSR, 0x18, 0x00); 5513 SiS_SetReg(SISSR, 0x18, 0x00);
5514 outSISIDXREG(SISSR, 0x19, 0x20); 5514 SiS_SetReg(SISSR, 0x19, 0x20);
5515 outSISIDXREG(SISSR, 0x16, 0x00); 5515 SiS_SetReg(SISSR, 0x16, 0x00);
5516 outSISIDXREG(SISSR, 0x16, 0x80); 5516 SiS_SetReg(SISSR, 0x16, 0x80);
5517 outSISIDXREG(SISSR, 0x18, 0xc5); 5517 SiS_SetReg(SISSR, 0x18, 0xc5);
5518 outSISIDXREG(SISSR, 0x19, 0x23); 5518 SiS_SetReg(SISSR, 0x19, 0x23);
5519 outSISIDXREG(SISSR, 0x16, 0x00); 5519 SiS_SetReg(SISSR, 0x16, 0x00);
5520 outSISIDXREG(SISSR, 0x16, 0x80); 5520 SiS_SetReg(SISSR, 0x16, 0x80);
5521 sisfb_post_xgi_delay(ivideo, 1); 5521 sisfb_post_xgi_delay(ivideo, 1);
5522 outSISIDXREG(SISCR, 0x97,0x11); 5522 SiS_SetReg(SISCR, 0x97, 0x11);
5523 sisfb_post_xgi_setclocks(ivideo, regb); 5523 sisfb_post_xgi_setclocks(ivideo, regb);
5524 sisfb_post_xgi_delay(ivideo, 0x46); 5524 sisfb_post_xgi_delay(ivideo, 0x46);
5525 outSISIDXREG(SISSR, 0x18, 0xc5); 5525 SiS_SetReg(SISSR, 0x18, 0xc5);
5526 outSISIDXREG(SISSR, 0x19, 0x23); 5526 SiS_SetReg(SISSR, 0x19, 0x23);
5527 outSISIDXREG(SISSR, 0x16, 0x00); 5527 SiS_SetReg(SISSR, 0x16, 0x00);
5528 outSISIDXREG(SISSR, 0x16, 0x80); 5528 SiS_SetReg(SISSR, 0x16, 0x80);
5529 sisfb_post_xgi_delay(ivideo, 1); 5529 sisfb_post_xgi_delay(ivideo, 1);
5530 outSISIDXREG(SISSR, 0x1b, 0x04); 5530 SiS_SetReg(SISSR, 0x1b, 0x04);
5531 sisfb_post_xgi_delay(ivideo, 1); 5531 sisfb_post_xgi_delay(ivideo, 1);
5532 outSISIDXREG(SISSR, 0x1b, 0x00); 5532 SiS_SetReg(SISSR, 0x1b, 0x00);
5533 sisfb_post_xgi_delay(ivideo, 1); 5533 sisfb_post_xgi_delay(ivideo, 1);
5534 v1 = 0x31; 5534 v1 = 0x31;
5535 if(ivideo->haveXGIROM) { 5535 if(ivideo->haveXGIROM) {
5536 v1 = bios[0xf0]; 5536 v1 = bios[0xf0];
5537 } 5537 }
5538 outSISIDXREG(SISSR, 0x18, v1); 5538 SiS_SetReg(SISSR, 0x18, v1);
5539 outSISIDXREG(SISSR, 0x19, 0x06); 5539 SiS_SetReg(SISSR, 0x19, 0x06);
5540 outSISIDXREG(SISSR, 0x16, 0x04); 5540 SiS_SetReg(SISSR, 0x16, 0x04);
5541 outSISIDXREG(SISSR, 0x16, 0x84); 5541 SiS_SetReg(SISSR, 0x16, 0x84);
5542 sisfb_post_xgi_delay(ivideo, 1); 5542 sisfb_post_xgi_delay(ivideo, 1);
5543 break; 5543 break;
5544 default: 5544 default:
@@ -5546,85 +5546,85 @@ sisfb_post_xgi(struct pci_dev *pdev)
5546 if((ivideo->chip == XGI_40) && 5546 if((ivideo->chip == XGI_40) &&
5547 ((ivideo->revision_id == 1) || 5547 ((ivideo->revision_id == 1) ||
5548 (ivideo->revision_id == 2))) { 5548 (ivideo->revision_id == 2))) {
5549 outSISIDXREG(SISCR, 0x82, bios[regb + 0x158]); 5549 SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
5550 outSISIDXREG(SISCR, 0x85, bios[regb + 0x160]); 5550 SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
5551 outSISIDXREG(SISCR, 0x86, bios[regb + 0x168]); 5551 SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
5552 } else { 5552 } else {
5553 outSISIDXREG(SISCR, 0x82, 0x88); 5553 SiS_SetReg(SISCR, 0x82, 0x88);
5554 outSISIDXREG(SISCR, 0x86, 0x00); 5554 SiS_SetReg(SISCR, 0x86, 0x00);
5555 reg = SiS_GetReg(SISCR, 0x86); 5555 reg = SiS_GetReg(SISCR, 0x86);
5556 outSISIDXREG(SISCR, 0x86, 0x88); 5556 SiS_SetReg(SISCR, 0x86, 0x88);
5557 outSISIDXREG(SISCR, 0x82, 0x77); 5557 SiS_SetReg(SISCR, 0x82, 0x77);
5558 outSISIDXREG(SISCR, 0x85, 0x00); 5558 SiS_SetReg(SISCR, 0x85, 0x00);
5559 reg = SiS_GetReg(SISCR, 0x85); 5559 reg = SiS_GetReg(SISCR, 0x85);
5560 outSISIDXREG(SISCR, 0x85, 0x88); 5560 SiS_SetReg(SISCR, 0x85, 0x88);
5561 reg = SiS_GetReg(SISCR, 0x85); 5561 reg = SiS_GetReg(SISCR, 0x85);
5562 v1 = cs160[regb]; v2 = cs158[regb]; 5562 v1 = cs160[regb]; v2 = cs158[regb];
5563 if(ivideo->haveXGIROM) { 5563 if(ivideo->haveXGIROM) {
5564 v1 = bios[regb + 0x160]; 5564 v1 = bios[regb + 0x160];
5565 v2 = bios[regb + 0x158]; 5565 v2 = bios[regb + 0x158];
5566 } 5566 }
5567 outSISIDXREG(SISCR, 0x85, v1); 5567 SiS_SetReg(SISCR, 0x85, v1);
5568 outSISIDXREG(SISCR, 0x82, v2); 5568 SiS_SetReg(SISCR, 0x82, v2);
5569 } 5569 }
5570 if(ivideo->chip == XGI_40) { 5570 if(ivideo->chip == XGI_40) {
5571 outSISIDXREG(SISCR, 0x97, 0x11); 5571 SiS_SetReg(SISCR, 0x97, 0x11);
5572 } 5572 }
5573 if((ivideo->chip == XGI_40) && (ivideo->revision_id == 2)) { 5573 if((ivideo->chip == XGI_40) && (ivideo->revision_id == 2)) {
5574 outSISIDXREG(SISCR, 0x98, 0x01); 5574 SiS_SetReg(SISCR, 0x98, 0x01);
5575 } else { 5575 } else {
5576 outSISIDXREG(SISCR, 0x98, 0x03); 5576 SiS_SetReg(SISCR, 0x98, 0x03);
5577 } 5577 }
5578 outSISIDXREG(SISCR, 0x9a, 0x02); 5578 SiS_SetReg(SISCR, 0x9a, 0x02);
5579 5579
5580 if(ivideo->chip == XGI_40) { 5580 if(ivideo->chip == XGI_40) {
5581 outSISIDXREG(SISSR, 0x18, 0x01); 5581 SiS_SetReg(SISSR, 0x18, 0x01);
5582 } else { 5582 } else {
5583 outSISIDXREG(SISSR, 0x18, 0x00); 5583 SiS_SetReg(SISSR, 0x18, 0x00);
5584 } 5584 }
5585 outSISIDXREG(SISSR, 0x19, 0x40); 5585 SiS_SetReg(SISSR, 0x19, 0x40);
5586 outSISIDXREG(SISSR, 0x16, 0x00); 5586 SiS_SetReg(SISSR, 0x16, 0x00);
5587 outSISIDXREG(SISSR, 0x16, 0x80); 5587 SiS_SetReg(SISSR, 0x16, 0x80);
5588 if((ivideo->chip == XGI_40) && (bios[0x1cb] != 0x0c)) { 5588 if((ivideo->chip == XGI_40) && (bios[0x1cb] != 0x0c)) {
5589 sisfb_post_xgi_delay(ivideo, 0x43); 5589 sisfb_post_xgi_delay(ivideo, 0x43);
5590 sisfb_post_xgi_delay(ivideo, 0x43); 5590 sisfb_post_xgi_delay(ivideo, 0x43);
5591 sisfb_post_xgi_delay(ivideo, 0x43); 5591 sisfb_post_xgi_delay(ivideo, 0x43);
5592 outSISIDXREG(SISSR, 0x18, 0x00); 5592 SiS_SetReg(SISSR, 0x18, 0x00);
5593 outSISIDXREG(SISSR, 0x19, 0x40); 5593 SiS_SetReg(SISSR, 0x19, 0x40);
5594 outSISIDXREG(SISSR, 0x16, 0x00); 5594 SiS_SetReg(SISSR, 0x16, 0x00);
5595 outSISIDXREG(SISSR, 0x16, 0x80); 5595 SiS_SetReg(SISSR, 0x16, 0x80);
5596 } 5596 }
5597 sisfb_post_xgi_delay(ivideo, 4); 5597 sisfb_post_xgi_delay(ivideo, 4);
5598 v1 = 0x31; 5598 v1 = 0x31;
5599 if(ivideo->haveXGIROM) { 5599 if(ivideo->haveXGIROM) {
5600 v1 = bios[0xf0]; 5600 v1 = bios[0xf0];
5601 } 5601 }
5602 outSISIDXREG(SISSR, 0x18, v1); 5602 SiS_SetReg(SISSR, 0x18, v1);
5603 outSISIDXREG(SISSR, 0x19, 0x01); 5603 SiS_SetReg(SISSR, 0x19, 0x01);
5604 if(ivideo->chip == XGI_40) { 5604 if(ivideo->chip == XGI_40) {
5605 outSISIDXREG(SISSR, 0x16, bios[0x53e]); 5605 SiS_SetReg(SISSR, 0x16, bios[0x53e]);
5606 outSISIDXREG(SISSR, 0x16, bios[0x53f]); 5606 SiS_SetReg(SISSR, 0x16, bios[0x53f]);
5607 } else { 5607 } else {
5608 outSISIDXREG(SISSR, 0x16, 0x05); 5608 SiS_SetReg(SISSR, 0x16, 0x05);
5609 outSISIDXREG(SISSR, 0x16, 0x85); 5609 SiS_SetReg(SISSR, 0x16, 0x85);
5610 } 5610 }
5611 sisfb_post_xgi_delay(ivideo, 0x43); 5611 sisfb_post_xgi_delay(ivideo, 0x43);
5612 if(ivideo->chip == XGI_40) { 5612 if(ivideo->chip == XGI_40) {
5613 outSISIDXREG(SISSR, 0x1b, 0x01); 5613 SiS_SetReg(SISSR, 0x1b, 0x01);
5614 } else { 5614 } else {
5615 outSISIDXREG(SISSR, 0x1b, 0x03); 5615 SiS_SetReg(SISSR, 0x1b, 0x03);
5616 } 5616 }
5617 sisfb_post_xgi_delay(ivideo, 0x22); 5617 sisfb_post_xgi_delay(ivideo, 0x22);
5618 outSISIDXREG(SISSR, 0x18, v1); 5618 SiS_SetReg(SISSR, 0x18, v1);
5619 outSISIDXREG(SISSR, 0x19, 0x00); 5619 SiS_SetReg(SISSR, 0x19, 0x00);
5620 if(ivideo->chip == XGI_40) { 5620 if(ivideo->chip == XGI_40) {
5621 outSISIDXREG(SISSR, 0x16, bios[0x540]); 5621 SiS_SetReg(SISSR, 0x16, bios[0x540]);
5622 outSISIDXREG(SISSR, 0x16, bios[0x541]); 5622 SiS_SetReg(SISSR, 0x16, bios[0x541]);
5623 } else { 5623 } else {
5624 outSISIDXREG(SISSR, 0x16, 0x05); 5624 SiS_SetReg(SISSR, 0x16, 0x05);
5625 outSISIDXREG(SISSR, 0x16, 0x85); 5625 SiS_SetReg(SISSR, 0x16, 0x85);
5626 } 5626 }
5627 outSISIDXREG(SISSR, 0x1b, 0x00); 5627 SiS_SetReg(SISSR, 0x1b, 0x00);
5628 } 5628 }
5629 5629
5630 regb = 0; /* ! */ 5630 regb = 0; /* ! */
@@ -5632,7 +5632,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5632 if(ivideo->haveXGIROM) { 5632 if(ivideo->haveXGIROM) {
5633 v1 = bios[0x110 + regb]; 5633 v1 = bios[0x110 + regb];
5634 } 5634 }
5635 outSISIDXREG(SISSR, 0x1b, v1); 5635 SiS_SetReg(SISSR, 0x1b, v1);
5636 5636
5637 /* RAM size */ 5637 /* RAM size */
5638 v1 = 0x00; v2 = 0x00; 5638 v1 = 0x00; v2 = 0x00;
@@ -5644,8 +5644,8 @@ sisfb_post_xgi(struct pci_dev *pdev)
5644 regd = 1 << regb; 5644 regd = 1 << regb;
5645 if((v1 & 0x40) && (v2 & regd) && ivideo->haveXGIROM) { 5645 if((v1 & 0x40) && (v2 & regd) && ivideo->haveXGIROM) {
5646 5646
5647 outSISIDXREG(SISSR, 0x13, bios[regb + 0xe0]); 5647 SiS_SetReg(SISSR, 0x13, bios[regb + 0xe0]);
5648 outSISIDXREG(SISSR, 0x14, bios[regb + 0xe0 + 8]); 5648 SiS_SetReg(SISSR, 0x14, bios[regb + 0xe0 + 8]);
5649 5649
5650 } else { 5650 } else {
5651 5651
@@ -5657,7 +5657,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5657 ivideo->SiS_Pr.VideoMemorySize = 8 << 20; 5657 ivideo->SiS_Pr.VideoMemorySize = 8 << 20;
5658 SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80); 5658 SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
5659 5659
5660 outSISIDXREG(SISSR, 0x05, 0x86); 5660 SiS_SetReg(SISSR, 0x05, 0x86);
5661 5661
5662 /* Disable read-cache */ 5662 /* Disable read-cache */
5663 andSISIDXREG(SISSR, 0x21, 0xdf); 5663 andSISIDXREG(SISSR, 0x21, 0xdf);
@@ -5699,13 +5699,13 @@ sisfb_post_xgi(struct pci_dev *pdev)
5699 ivideo->curFSTN = ivideo->curDSTN = 0; 5699 ivideo->curFSTN = ivideo->curDSTN = 0;
5700 SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80); 5700 SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
5701 5701
5702 outSISIDXREG(SISSR, 0x05, 0x86); 5702 SiS_SetReg(SISSR, 0x05, 0x86);
5703 5703
5704 /* Display off */ 5704 /* Display off */
5705 orSISIDXREG(SISSR, 0x01, 0x20); 5705 orSISIDXREG(SISSR, 0x01, 0x20);
5706 5706
5707 /* Save mode number in CR34 */ 5707 /* Save mode number in CR34 */
5708 outSISIDXREG(SISCR, 0x34, 0x2e); 5708 SiS_SetReg(SISCR, 0x34, 0x2e);
5709 5709
5710 /* Let everyone know what the current mode is */ 5710 /* Let everyone know what the current mode is */
5711 ivideo->modeprechange = 0x2e; 5711 ivideo->modeprechange = 0x2e;
@@ -5955,7 +5955,7 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5955 } 5955 }
5956#endif 5956#endif
5957 5957
5958 outSISIDXREG(SISSR, 0x05, 0x86); 5958 SiS_SetReg(SISSR, 0x05, 0x86);
5959 5959
5960 if( (!ivideo->sisvga_enabled) 5960 if( (!ivideo->sisvga_enabled)
5961#if !defined(__i386__) && !defined(__x86_64__) 5961#if !defined(__i386__) && !defined(__x86_64__)
@@ -5963,7 +5963,7 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5963#endif 5963#endif
5964 ) { 5964 ) {
5965 for(i = 0x30; i <= 0x3f; i++) { 5965 for(i = 0x30; i <= 0x3f; i++) {
5966 outSISIDXREG(SISCR, i, 0x00); 5966 SiS_SetReg(SISCR, i, 0x00);
5967 } 5967 }
5968 } 5968 }
5969 5969
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 05:29:55 -0400