diff options
author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2012-05-08 00:08:17 -0400 |
---|---|---|
committer | Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | 2012-05-13 09:07:59 -0400 |
commit | c932b2731116f99a660817e8fa718c9da0798a9c (patch) | |
tree | 9a4970488c0ac8f6becd9377a80bb89275e33565 /drivers/video/sh_mobile_hdmi.c | |
parent | db6668d83a265a15ffd79dbc8432598808b34bb4 (diff) |
fbdev: sh_mobile_hdmi: add HDMI Control Register support
Latest SuperH HDMI uses not only HDMI Core Register (HTOP0)
but also HDMI Control Register (HTOP1).
This patch adds HDMI Control Register support.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Diffstat (limited to 'drivers/video/sh_mobile_hdmi.c')
-rw-r--r-- | drivers/video/sh_mobile_hdmi.c | 152 |
1 files changed, 151 insertions, 1 deletions
diff --git a/drivers/video/sh_mobile_hdmi.c b/drivers/video/sh_mobile_hdmi.c index 4d48a805dfe..930e550e752 100644 --- a/drivers/video/sh_mobile_hdmi.c +++ b/drivers/video/sh_mobile_hdmi.c | |||
@@ -31,6 +31,7 @@ | |||
31 | 31 | ||
32 | #include "sh_mobile_lcdcfb.h" | 32 | #include "sh_mobile_lcdcfb.h" |
33 | 33 | ||
34 | /* HDMI Core Control Register (HTOP0) */ | ||
34 | #define HDMI_SYSTEM_CTRL 0x00 /* System control */ | 35 | #define HDMI_SYSTEM_CTRL 0x00 /* System control */ |
35 | #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control, | 36 | #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control, |
36 | bits 19..16 of 20-bit N for Audio Clock Regeneration packet */ | 37 | bits 19..16 of 20-bit N for Audio Clock Regeneration packet */ |
@@ -201,6 +202,68 @@ | |||
201 | #define HDMI_REVISION_ID 0xF1 /* Revision ID */ | 202 | #define HDMI_REVISION_ID 0xF1 /* Revision ID */ |
202 | #define HDMI_TEST_MODE 0xFE /* Test mode */ | 203 | #define HDMI_TEST_MODE 0xFE /* Test mode */ |
203 | 204 | ||
205 | /* HDMI Control Register (HTOP1) */ | ||
206 | #define HDMI_HTOP1_TEST_MODE 0x0000 /* Test mode */ | ||
207 | #define HDMI_HTOP1_VIDEO_INPUT 0x0008 /* VideoInput */ | ||
208 | #define HDMI_HTOP1_CORE_RSTN 0x000C /* CoreResetn */ | ||
209 | #define HDMI_HTOP1_PLLBW 0x0018 /* PLLBW */ | ||
210 | #define HDMI_HTOP1_CLK_TO_PHY 0x001C /* Clk to Phy */ | ||
211 | #define HDMI_HTOP1_VIDEO_INPUT2 0x0020 /* VideoInput2 */ | ||
212 | #define HDMI_HTOP1_TISEMP0_1 0x0024 /* tisemp0-1 */ | ||
213 | #define HDMI_HTOP1_TISEMP2_C 0x0028 /* tisemp2-c */ | ||
214 | #define HDMI_HTOP1_TISIDRV 0x002C /* tisidrv */ | ||
215 | #define HDMI_HTOP1_TISEN 0x0034 /* tisen */ | ||
216 | #define HDMI_HTOP1_TISDREN 0x0038 /* tisdren */ | ||
217 | #define HDMI_HTOP1_CISRANGE 0x003C /* cisrange */ | ||
218 | #define HDMI_HTOP1_ENABLE_SELECTOR 0x0040 /* Enable Selector */ | ||
219 | #define HDMI_HTOP1_MACRO_RESET 0x0044 /* Macro reset */ | ||
220 | #define HDMI_HTOP1_PLL_CALIBRATION 0x0048 /* PLL calibration */ | ||
221 | #define HDMI_HTOP1_RE_CALIBRATION 0x004C /* Re-calibration */ | ||
222 | #define HDMI_HTOP1_CURRENT 0x0050 /* Current */ | ||
223 | #define HDMI_HTOP1_PLL_LOCK_DETECT 0x0054 /* PLL lock detect */ | ||
224 | #define HDMI_HTOP1_PHY_TEST_MODE 0x0058 /* PHY Test Mode */ | ||
225 | #define HDMI_HTOP1_CLK_SET 0x0080 /* Clock Set */ | ||
226 | #define HDMI_HTOP1_DDC_FAIL_SAFE 0x0084 /* DDC fail safe */ | ||
227 | #define HDMI_HTOP1_PRBS 0x0088 /* PRBS */ | ||
228 | #define HDMI_HTOP1_EDID_AINC_CONTROL 0x008C /* EDID ainc Control */ | ||
229 | #define HDMI_HTOP1_HTOP_DCL_MODE 0x00FC /* Deep Coloer Mode */ | ||
230 | #define HDMI_HTOP1_HTOP_DCL_FRC_COEF0 0x0100 /* Deep Color:FRC COEF0 */ | ||
231 | #define HDMI_HTOP1_HTOP_DCL_FRC_COEF1 0x0104 /* Deep Color:FRC COEF1 */ | ||
232 | #define HDMI_HTOP1_HTOP_DCL_FRC_COEF2 0x0108 /* Deep Color:FRC COEF2 */ | ||
233 | #define HDMI_HTOP1_HTOP_DCL_FRC_COEF3 0x010C /* Deep Color:FRC COEF3 */ | ||
234 | #define HDMI_HTOP1_HTOP_DCL_FRC_COEF0_C 0x0110 /* Deep Color:FRC COEF0C */ | ||
235 | #define HDMI_HTOP1_HTOP_DCL_FRC_COEF1_C 0x0114 /* Deep Color:FRC COEF1C */ | ||
236 | #define HDMI_HTOP1_HTOP_DCL_FRC_COEF2_C 0x0118 /* Deep Color:FRC COEF2C */ | ||
237 | #define HDMI_HTOP1_HTOP_DCL_FRC_COEF3_C 0x011C /* Deep Color:FRC COEF3C */ | ||
238 | #define HDMI_HTOP1_HTOP_DCL_FRC_MODE 0x0120 /* Deep Color:FRC Mode */ | ||
239 | #define HDMI_HTOP1_HTOP_DCL_RECT_START1 0x0124 /* Deep Color:Rect Start1 */ | ||
240 | #define HDMI_HTOP1_HTOP_DCL_RECT_SIZE1 0x0128 /* Deep Color:Rect Size1 */ | ||
241 | #define HDMI_HTOP1_HTOP_DCL_RECT_START2 0x012C /* Deep Color:Rect Start2 */ | ||
242 | #define HDMI_HTOP1_HTOP_DCL_RECT_SIZE2 0x0130 /* Deep Color:Rect Size2 */ | ||
243 | #define HDMI_HTOP1_HTOP_DCL_RECT_START3 0x0134 /* Deep Color:Rect Start3 */ | ||
244 | #define HDMI_HTOP1_HTOP_DCL_RECT_SIZE3 0x0138 /* Deep Color:Rect Size3 */ | ||
245 | #define HDMI_HTOP1_HTOP_DCL_RECT_START4 0x013C /* Deep Color:Rect Start4 */ | ||
246 | #define HDMI_HTOP1_HTOP_DCL_RECT_SIZE4 0x0140 /* Deep Color:Rect Size4 */ | ||
247 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y1_1 0x0144 /* Deep Color:Fil Para Y1_1 */ | ||
248 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y1_2 0x0148 /* Deep Color:Fil Para Y1_2 */ | ||
249 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB1_1 0x014C /* Deep Color:Fil Para CB1_1 */ | ||
250 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB1_2 0x0150 /* Deep Color:Fil Para CB1_2 */ | ||
251 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR1_1 0x0154 /* Deep Color:Fil Para CR1_1 */ | ||
252 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR1_2 0x0158 /* Deep Color:Fil Para CR1_2 */ | ||
253 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y2_1 0x015C /* Deep Color:Fil Para Y2_1 */ | ||
254 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y2_2 0x0160 /* Deep Color:Fil Para Y2_2 */ | ||
255 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB2_1 0x0164 /* Deep Color:Fil Para CB2_1 */ | ||
256 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB2_2 0x0168 /* Deep Color:Fil Para CB2_2 */ | ||
257 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR2_1 0x016C /* Deep Color:Fil Para CR2_1 */ | ||
258 | #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR2_2 0x0170 /* Deep Color:Fil Para CR2_2 */ | ||
259 | #define HDMI_HTOP1_HTOP_DCL_COR_PARA_Y1 0x0174 /* Deep Color:Cor Para Y1 */ | ||
260 | #define HDMI_HTOP1_HTOP_DCL_COR_PARA_CB1 0x0178 /* Deep Color:Cor Para CB1 */ | ||
261 | #define HDMI_HTOP1_HTOP_DCL_COR_PARA_CR1 0x017C /* Deep Color:Cor Para CR1 */ | ||
262 | #define HDMI_HTOP1_HTOP_DCL_COR_PARA_Y2 0x0180 /* Deep Color:Cor Para Y2 */ | ||
263 | #define HDMI_HTOP1_HTOP_DCL_COR_PARA_CB2 0x0184 /* Deep Color:Cor Para CB2 */ | ||
264 | #define HDMI_HTOP1_HTOP_DCL_COR_PARA_CR2 0x0188 /* Deep Color:Cor Para CR2 */ | ||
265 | #define HDMI_HTOP1_EDID_DATA_READ 0x0200 /* EDID Data Read 128Byte:0x03FC */ | ||
266 | |||
204 | enum hotplug_state { | 267 | enum hotplug_state { |
205 | HDMI_HOTPLUG_DISCONNECTED, | 268 | HDMI_HOTPLUG_DISCONNECTED, |
206 | HDMI_HOTPLUG_CONNECTED, | 269 | HDMI_HOTPLUG_CONNECTED, |
@@ -211,6 +274,7 @@ struct sh_hdmi { | |||
211 | struct sh_mobile_lcdc_entity entity; | 274 | struct sh_mobile_lcdc_entity entity; |
212 | 275 | ||
213 | void __iomem *base; | 276 | void __iomem *base; |
277 | void __iomem *htop1; | ||
214 | enum hotplug_state hp_state; /* hot-plug status */ | 278 | enum hotplug_state hp_state; /* hot-plug status */ |
215 | u8 preprogrammed_vic; /* use a pre-programmed VIC or | 279 | u8 preprogrammed_vic; /* use a pre-programmed VIC or |
216 | the external mode */ | 280 | the external mode */ |
@@ -271,6 +335,17 @@ static void hdmi_bit_set(struct sh_hdmi *hdmi, u8 mask, u8 data, u8 reg) | |||
271 | hdmi_write(hdmi, val, reg); | 335 | hdmi_write(hdmi, val, reg); |
272 | } | 336 | } |
273 | 337 | ||
338 | static void hdmi_htop1_write(struct sh_hdmi *hdmi, u32 data, u32 reg) | ||
339 | { | ||
340 | iowrite32(data, hdmi->htop1 + reg); | ||
341 | udelay(100); | ||
342 | } | ||
343 | |||
344 | static u32 hdmi_htop1_read(struct sh_hdmi *hdmi, u32 reg) | ||
345 | { | ||
346 | return ioread32(hdmi->htop1 + reg); | ||
347 | } | ||
348 | |||
274 | /* | 349 | /* |
275 | * HDMI sound | 350 | * HDMI sound |
276 | */ | 351 | */ |
@@ -781,7 +856,9 @@ static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate, | |||
781 | /* Read EDID */ | 856 | /* Read EDID */ |
782 | dev_dbg(hdmi->dev, "Read back EDID code:"); | 857 | dev_dbg(hdmi->dev, "Read back EDID code:"); |
783 | for (i = 0; i < 128; i++) { | 858 | for (i = 0; i < 128; i++) { |
784 | edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW); | 859 | edid[i] = (hdmi->htop1) ? |
860 | (u8)hdmi_htop1_read(hdmi, HDMI_HTOP1_EDID_DATA_READ + (i * 4)) : | ||
861 | hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW); | ||
785 | #ifdef DEBUG | 862 | #ifdef DEBUG |
786 | if ((i % 16) == 0) { | 863 | if ((i % 16) == 0) { |
787 | printk(KERN_CONT "\n"); | 864 | printk(KERN_CONT "\n"); |
@@ -1145,10 +1222,58 @@ out: | |||
1145 | dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, hdmi); | 1222 | dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, hdmi); |
1146 | } | 1223 | } |
1147 | 1224 | ||
1225 | static void sh_hdmi_htop1_init(struct sh_hdmi *hdmi) | ||
1226 | { | ||
1227 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_MODE); | ||
1228 | hdmi_htop1_write(hdmi, 0x0000000b, 0x0010); | ||
1229 | hdmi_htop1_write(hdmi, 0x00006710, HDMI_HTOP1_HTOP_DCL_FRC_MODE); | ||
1230 | hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y1_1); | ||
1231 | hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y1_2); | ||
1232 | hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB1_1); | ||
1233 | hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB1_2); | ||
1234 | hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR1_1); | ||
1235 | hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR1_2); | ||
1236 | hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y2_1); | ||
1237 | hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y2_2); | ||
1238 | hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB2_1); | ||
1239 | hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB2_2); | ||
1240 | hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR2_1); | ||
1241 | hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR2_2); | ||
1242 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_Y1); | ||
1243 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_CB1); | ||
1244 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_CR1); | ||
1245 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_Y2); | ||
1246 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_CB2); | ||
1247 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_CR2); | ||
1248 | hdmi_htop1_write(hdmi, 0x00000008, HDMI_HTOP1_CURRENT); | ||
1249 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_TISEMP0_1); | ||
1250 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_TISEMP2_C); | ||
1251 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_PHY_TEST_MODE); | ||
1252 | hdmi_htop1_write(hdmi, 0x00000081, HDMI_HTOP1_TISIDRV); | ||
1253 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_PLLBW); | ||
1254 | hdmi_htop1_write(hdmi, 0x0000000f, HDMI_HTOP1_TISEN); | ||
1255 | hdmi_htop1_write(hdmi, 0x0000000f, HDMI_HTOP1_TISDREN); | ||
1256 | hdmi_htop1_write(hdmi, 0x00000003, HDMI_HTOP1_ENABLE_SELECTOR); | ||
1257 | hdmi_htop1_write(hdmi, 0x00000001, HDMI_HTOP1_MACRO_RESET); | ||
1258 | hdmi_htop1_write(hdmi, 0x00000016, HDMI_HTOP1_CISRANGE); | ||
1259 | msleep(100); | ||
1260 | hdmi_htop1_write(hdmi, 0x00000001, HDMI_HTOP1_ENABLE_SELECTOR); | ||
1261 | msleep(100); | ||
1262 | hdmi_htop1_write(hdmi, 0x00000003, HDMI_HTOP1_ENABLE_SELECTOR); | ||
1263 | hdmi_htop1_write(hdmi, 0x00000001, HDMI_HTOP1_MACRO_RESET); | ||
1264 | hdmi_htop1_write(hdmi, 0x0000000f, HDMI_HTOP1_TISEN); | ||
1265 | hdmi_htop1_write(hdmi, 0x0000000f, HDMI_HTOP1_TISDREN); | ||
1266 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_VIDEO_INPUT); | ||
1267 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_CLK_TO_PHY); | ||
1268 | hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_VIDEO_INPUT2); | ||
1269 | hdmi_htop1_write(hdmi, 0x0000000a, HDMI_HTOP1_CLK_SET); | ||
1270 | } | ||
1271 | |||
1148 | static int __init sh_hdmi_probe(struct platform_device *pdev) | 1272 | static int __init sh_hdmi_probe(struct platform_device *pdev) |
1149 | { | 1273 | { |
1150 | struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data; | 1274 | struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data; |
1151 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1275 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1276 | struct resource *htop1_res; | ||
1152 | int irq = platform_get_irq(pdev, 0), ret; | 1277 | int irq = platform_get_irq(pdev, 0), ret; |
1153 | struct sh_hdmi *hdmi; | 1278 | struct sh_hdmi *hdmi; |
1154 | long rate; | 1279 | long rate; |
@@ -1156,6 +1281,15 @@ static int __init sh_hdmi_probe(struct platform_device *pdev) | |||
1156 | if (!res || !pdata || irq < 0) | 1281 | if (!res || !pdata || irq < 0) |
1157 | return -ENODEV; | 1282 | return -ENODEV; |
1158 | 1283 | ||
1284 | htop1_res = NULL; | ||
1285 | if (pdata->flags & HDMI_HAS_HTOP1) { | ||
1286 | htop1_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
1287 | if (!htop1_res) { | ||
1288 | dev_err(&pdev->dev, "htop1 needs register base\n"); | ||
1289 | return -EINVAL; | ||
1290 | } | ||
1291 | } | ||
1292 | |||
1159 | hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL); | 1293 | hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL); |
1160 | if (!hdmi) { | 1294 | if (!hdmi) { |
1161 | dev_err(&pdev->dev, "Cannot allocate device data\n"); | 1295 | dev_err(&pdev->dev, "Cannot allocate device data\n"); |
@@ -1227,6 +1361,17 @@ static int __init sh_hdmi_probe(struct platform_device *pdev) | |||
1227 | if (pdata->flags & HDMI_OUTPUT_POLARITY_HI) | 1361 | if (pdata->flags & HDMI_OUTPUT_POLARITY_HI) |
1228 | hdmi_bit_set(hdmi, 0x01, 0x01, HDMI_SYSTEM_CTRL); | 1362 | hdmi_bit_set(hdmi, 0x01, 0x01, HDMI_SYSTEM_CTRL); |
1229 | 1363 | ||
1364 | /* enable htop1 register if needed */ | ||
1365 | if (htop1_res) { | ||
1366 | hdmi->htop1 = ioremap(htop1_res->start, resource_size(htop1_res)); | ||
1367 | if (!hdmi->htop1) { | ||
1368 | dev_err(&pdev->dev, "control register region already claimed\n"); | ||
1369 | ret = -ENOMEM; | ||
1370 | goto emap_htop1; | ||
1371 | } | ||
1372 | sh_hdmi_htop1_init(hdmi); | ||
1373 | } | ||
1374 | |||
1230 | /* Product and revision IDs are 0 in sh-mobile version */ | 1375 | /* Product and revision IDs are 0 in sh-mobile version */ |
1231 | dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n", | 1376 | dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n", |
1232 | hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID)); | 1377 | hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID)); |
@@ -1250,6 +1395,9 @@ static int __init sh_hdmi_probe(struct platform_device *pdev) | |||
1250 | ecodec: | 1395 | ecodec: |
1251 | free_irq(irq, hdmi); | 1396 | free_irq(irq, hdmi); |
1252 | ereqirq: | 1397 | ereqirq: |
1398 | if (hdmi->htop1) | ||
1399 | iounmap(hdmi->htop1); | ||
1400 | emap_htop1: | ||
1253 | pm_runtime_put(&pdev->dev); | 1401 | pm_runtime_put(&pdev->dev); |
1254 | pm_runtime_disable(&pdev->dev); | 1402 | pm_runtime_disable(&pdev->dev); |
1255 | iounmap(hdmi->base); | 1403 | iounmap(hdmi->base); |
@@ -1281,6 +1429,8 @@ static int __exit sh_hdmi_remove(struct platform_device *pdev) | |||
1281 | pm_runtime_disable(&pdev->dev); | 1429 | pm_runtime_disable(&pdev->dev); |
1282 | clk_disable(hdmi->hdmi_clk); | 1430 | clk_disable(hdmi->hdmi_clk); |
1283 | clk_put(hdmi->hdmi_clk); | 1431 | clk_put(hdmi->hdmi_clk); |
1432 | if (hdmi->htop1) | ||
1433 | iounmap(hdmi->htop1); | ||
1284 | iounmap(hdmi->base); | 1434 | iounmap(hdmi->base); |
1285 | release_mem_region(res->start, resource_size(res)); | 1435 | release_mem_region(res->start, resource_size(res)); |
1286 | kfree(hdmi); | 1436 | kfree(hdmi); |