Added missing tegra files.HEADmaster

3 files changed, 1512 insertions, 0 deletions

diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h
new file mode 100644
index 00000000000..c885f9cb065
--- /dev/null
+++ b/drivers/video/omap2/dss/hdmi.h
@@ -0,0 +1,631 @@
+/*
+ * hdmi.h
+ *
+ * HDMI driver definition for TI OMAP4 processors.
+ *
+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _OMAP4_DSS_HDMI_H_
+#define _OMAP4_DSS_HDMI_H_
+
+#include <linux/string.h>
+#include <video/omapdss.h>
+
+#define HDMI_WP         0x0
+#define HDMI_CORE_SYS           0x400
+#define HDMI_CORE_AV            0x900
+#define HDMI_PLLCTRL            0x200
+#define HDMI_PHY                0x300
+
+struct hdmi_reg { u16 idx; };
+
+#define HDMI_REG(idx)                   ((const struct hdmi_reg) { idx })
+
+/* HDMI Wrapper */
+#define HDMI_WP_REG(idx)                        HDMI_REG(HDMI_WP + idx)
+
+#define HDMI_WP_REVISION                        HDMI_WP_REG(0x0)
+#define HDMI_WP_SYSCONFIG                       HDMI_WP_REG(0x10)
+#define HDMI_WP_IRQSTATUS_RAW                   HDMI_WP_REG(0x24)
+#define HDMI_WP_IRQSTATUS                       HDMI_WP_REG(0x28)
+#define HDMI_WP_PWR_CTRL                        HDMI_WP_REG(0x40)
+#define HDMI_WP_IRQENABLE_SET                   HDMI_WP_REG(0x2C)
+#define HDMI_WP_VIDEO_CFG                       HDMI_WP_REG(0x50)
+#define HDMI_WP_VIDEO_SIZE                      HDMI_WP_REG(0x60)
+#define HDMI_WP_VIDEO_TIMING_H                  HDMI_WP_REG(0x68)
+#define HDMI_WP_VIDEO_TIMING_V                  HDMI_WP_REG(0x6C)
+#define HDMI_WP_WP_CLK                          HDMI_WP_REG(0x70)
+#define HDMI_WP_AUDIO_CFG                       HDMI_WP_REG(0x80)
+#define HDMI_WP_AUDIO_CFG2                      HDMI_WP_REG(0x84)
+#define HDMI_WP_AUDIO_CTRL                      HDMI_WP_REG(0x88)
+#define HDMI_WP_AUDIO_DATA                      HDMI_WP_REG(0x8C)
+
+/* HDMI IP Core System */
+#define HDMI_CORE_SYS_REG(idx)                  HDMI_REG(HDMI_CORE_SYS + idx)
+
+#define HDMI_CORE_SYS_VND_IDL                   HDMI_CORE_SYS_REG(0x0)
+#define HDMI_CORE_SYS_DEV_IDL                   HDMI_CORE_SYS_REG(0x8)
+#define HDMI_CORE_SYS_DEV_IDH                   HDMI_CORE_SYS_REG(0xC)
+#define HDMI_CORE_SYS_DEV_REV                   HDMI_CORE_SYS_REG(0x10)
+#define HDMI_CORE_SYS_SRST                      HDMI_CORE_SYS_REG(0x14)
+#define HDMI_CORE_CTRL1                 HDMI_CORE_SYS_REG(0x20)
+#define HDMI_CORE_SYS_SYS_STAT                  HDMI_CORE_SYS_REG(0x24)
+#define HDMI_CORE_SYS_VID_ACEN                  HDMI_CORE_SYS_REG(0x124)
+#define HDMI_CORE_SYS_VID_MODE                  HDMI_CORE_SYS_REG(0x128)
+#define HDMI_CORE_SYS_INTR_STATE                HDMI_CORE_SYS_REG(0x1C0)
+#define HDMI_CORE_SYS_INTR1                     HDMI_CORE_SYS_REG(0x1C4)
+#define HDMI_CORE_SYS_INTR2                     HDMI_CORE_SYS_REG(0x1C8)
+#define HDMI_CORE_SYS_INTR3                     HDMI_CORE_SYS_REG(0x1CC)
+#define HDMI_CORE_SYS_INTR4                     HDMI_CORE_SYS_REG(0x1D0)
+#define HDMI_CORE_SYS_UMASK1                    HDMI_CORE_SYS_REG(0x1D4)
+#define HDMI_CORE_SYS_TMDS_CTRL         HDMI_CORE_SYS_REG(0x208)
+#define HDMI_CORE_SYS_DE_DLY                    HDMI_CORE_SYS_REG(0xC8)
+#define HDMI_CORE_SYS_DE_CTRL                   HDMI_CORE_SYS_REG(0xCC)
+#define HDMI_CORE_SYS_DE_TOP                    HDMI_CORE_SYS_REG(0xD0)
+#define HDMI_CORE_SYS_DE_CNTL                   HDMI_CORE_SYS_REG(0xD8)
+#define HDMI_CORE_SYS_DE_CNTH                   HDMI_CORE_SYS_REG(0xDC)
+#define HDMI_CORE_SYS_DE_LINL                   HDMI_CORE_SYS_REG(0xE0)
+#define HDMI_CORE_SYS_DE_LINH_1         HDMI_CORE_SYS_REG(0xE4)
+#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
+#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
+#define HDMI_CORE_CTRL1_BSEL_24BITBUS           0x1
+#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
+
+/* HDMI DDC E-DID */
+#define HDMI_CORE_DDC_CMD                       HDMI_CORE_SYS_REG(0x3CC)
+#define HDMI_CORE_DDC_STATUS                    HDMI_CORE_SYS_REG(0x3C8)
+#define HDMI_CORE_DDC_ADDR                      HDMI_CORE_SYS_REG(0x3B4)
+#define HDMI_CORE_DDC_OFFSET                    HDMI_CORE_SYS_REG(0x3BC)
+#define HDMI_CORE_DDC_COUNT1                    HDMI_CORE_SYS_REG(0x3C0)
+#define HDMI_CORE_DDC_COUNT2                    HDMI_CORE_SYS_REG(0x3C4)
+#define HDMI_CORE_DDC_DATA                      HDMI_CORE_SYS_REG(0x3D0)
+#define HDMI_CORE_DDC_SEGM                      HDMI_CORE_SYS_REG(0x3B8)
+
+/* HDMI IP Core Audio Video */
+#define HDMI_CORE_AV_REG(idx)                   HDMI_REG(HDMI_CORE_AV + idx)
+
+#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
+#define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
+#define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
+#define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
+#define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
+#define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
+#define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
+#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
+#define HDMI_CORE_AV_AVI_DBYTE(n)               HDMI_CORE_AV_REG(n * 4 + 0x110)
+#define HDMI_CORE_AV_AVI_DBYTE_NELEMS           HDMI_CORE_AV_REG(15)
+#define HDMI_CORE_AV_SPD_DBYTE                  HDMI_CORE_AV_REG(0x190)
+#define HDMI_CORE_AV_SPD_DBYTE_NELEMS           HDMI_CORE_AV_REG(27)
+#define HDMI_CORE_AV_AUD_DBYTE(n)               HDMI_CORE_AV_REG(n * 4 + 0x210)
+#define HDMI_CORE_AV_AUD_DBYTE_NELEMS           HDMI_CORE_AV_REG(10)
+#define HDMI_CORE_AV_MPEG_DBYTE         HDMI_CORE_AV_REG(0x290)
+#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS          HDMI_CORE_AV_REG(27)
+#define HDMI_CORE_AV_GEN_DBYTE                  HDMI_CORE_AV_REG(0x300)
+#define HDMI_CORE_AV_GEN_DBYTE_NELEMS           HDMI_CORE_AV_REG(31)
+#define HDMI_CORE_AV_GEN2_DBYTE         HDMI_CORE_AV_REG(0x380)
+#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS          HDMI_CORE_AV_REG(31)
+#define HDMI_CORE_AV_ACR_CTRL                   HDMI_CORE_AV_REG(0x4)
+#define HDMI_CORE_AV_FREQ_SVAL                  HDMI_CORE_AV_REG(0x8)
+#define HDMI_CORE_AV_N_SVAL1                    HDMI_CORE_AV_REG(0xC)
+#define HDMI_CORE_AV_N_SVAL2                    HDMI_CORE_AV_REG(0x10)
+#define HDMI_CORE_AV_N_SVAL3                    HDMI_CORE_AV_REG(0x14)
+#define HDMI_CORE_AV_CTS_SVAL1                  HDMI_CORE_AV_REG(0x18)
+#define HDMI_CORE_AV_CTS_SVAL2                  HDMI_CORE_AV_REG(0x1C)
+#define HDMI_CORE_AV_CTS_SVAL3                  HDMI_CORE_AV_REG(0x20)
+#define HDMI_CORE_AV_CTS_HVAL1                  HDMI_CORE_AV_REG(0x24)
+#define HDMI_CORE_AV_CTS_HVAL2                  HDMI_CORE_AV_REG(0x28)
+#define HDMI_CORE_AV_CTS_HVAL3                  HDMI_CORE_AV_REG(0x2C)
+#define HDMI_CORE_AV_AUD_MODE                   HDMI_CORE_AV_REG(0x50)
+#define HDMI_CORE_AV_SPDIF_CTRL         HDMI_CORE_AV_REG(0x54)
+#define HDMI_CORE_AV_HW_SPDIF_FS                HDMI_CORE_AV_REG(0x60)
+#define HDMI_CORE_AV_SWAP_I2S                   HDMI_CORE_AV_REG(0x64)
+#define HDMI_CORE_AV_SPDIF_ERTH         HDMI_CORE_AV_REG(0x6C)
+#define HDMI_CORE_AV_I2S_IN_MAP         HDMI_CORE_AV_REG(0x70)
+#define HDMI_CORE_AV_I2S_IN_CTRL                HDMI_CORE_AV_REG(0x74)
+#define HDMI_CORE_AV_I2S_CHST0                  HDMI_CORE_AV_REG(0x78)
+#define HDMI_CORE_AV_I2S_CHST1                  HDMI_CORE_AV_REG(0x7C)
+#define HDMI_CORE_AV_I2S_CHST2                  HDMI_CORE_AV_REG(0x80)
+#define HDMI_CORE_AV_I2S_CHST4                  HDMI_CORE_AV_REG(0x84)
+#define HDMI_CORE_AV_I2S_CHST5                  HDMI_CORE_AV_REG(0x88)
+#define HDMI_CORE_AV_ASRC                       HDMI_CORE_AV_REG(0x8C)
+#define HDMI_CORE_AV_I2S_IN_LEN         HDMI_CORE_AV_REG(0x90)
+#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
+#define HDMI_CORE_AV_AUDO_TXSTAT                HDMI_CORE_AV_REG(0xC0)
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1           HDMI_CORE_AV_REG(0xCC)
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2           HDMI_CORE_AV_REG(0xD0)
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3           HDMI_CORE_AV_REG(0xD4)
+#define HDMI_CORE_AV_TEST_TXCTRL                HDMI_CORE_AV_REG(0xF0)
+#define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
+#define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
+#define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
+#define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
+#define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
+#define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
+#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
+#define HDMI_CORE_AV_SPD_TYPE                   HDMI_CORE_AV_REG(0x180)
+#define HDMI_CORE_AV_SPD_VERS                   HDMI_CORE_AV_REG(0x184)
+#define HDMI_CORE_AV_SPD_LEN                    HDMI_CORE_AV_REG(0x188)
+#define HDMI_CORE_AV_SPD_CHSUM                  HDMI_CORE_AV_REG(0x18C)
+#define HDMI_CORE_AV_AUDIO_TYPE         HDMI_CORE_AV_REG(0x200)
+#define HDMI_CORE_AV_AUDIO_VERS         HDMI_CORE_AV_REG(0x204)
+#define HDMI_CORE_AV_AUDIO_LEN                  HDMI_CORE_AV_REG(0x208)
+#define HDMI_CORE_AV_AUDIO_CHSUM                HDMI_CORE_AV_REG(0x20C)
+#define HDMI_CORE_AV_MPEG_TYPE                  HDMI_CORE_AV_REG(0x280)
+#define HDMI_CORE_AV_MPEG_VERS                  HDMI_CORE_AV_REG(0x284)
+#define HDMI_CORE_AV_MPEG_LEN                   HDMI_CORE_AV_REG(0x288)
+#define HDMI_CORE_AV_MPEG_CHSUM         HDMI_CORE_AV_REG(0x28C)
+#define HDMI_CORE_AV_CP_BYTE1                   HDMI_CORE_AV_REG(0x37C)
+#define HDMI_CORE_AV_CEC_ADDR_ID                HDMI_CORE_AV_REG(0x3FC)
+#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE           0x4
+#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE          0x4
+#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE          0x4
+#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE           0x4
+
+/* PLL */
+#define HDMI_PLL_REG(idx)                       HDMI_REG(HDMI_PLLCTRL + idx)
+
+#define PLLCTRL_PLL_CONTROL                     HDMI_PLL_REG(0x0)
+#define PLLCTRL_PLL_STATUS                      HDMI_PLL_REG(0x4)
+#define PLLCTRL_PLL_GO                          HDMI_PLL_REG(0x8)
+#define PLLCTRL_CFG1                            HDMI_PLL_REG(0xC)
+#define PLLCTRL_CFG2                            HDMI_PLL_REG(0x10)
+#define PLLCTRL_CFG3                            HDMI_PLL_REG(0x14)
+#define PLLCTRL_CFG4                            HDMI_PLL_REG(0x20)
+
+/* HDMI PHY */
+#define HDMI_PHY_REG(idx)                       HDMI_REG(HDMI_PHY + idx)
+
+#define HDMI_TXPHY_TX_CTRL                      HDMI_PHY_REG(0x0)
+#define HDMI_TXPHY_DIGITAL_CTRL         HDMI_PHY_REG(0x4)
+#define HDMI_TXPHY_POWER_CTRL                   HDMI_PHY_REG(0x8)
+#define HDMI_TXPHY_PAD_CFG_CTRL         HDMI_PHY_REG(0xC)
+
+/* HDMI EDID Length  */
+#define HDMI_EDID_MAX_LENGTH                    256
+#define EDID_TIMING_DESCRIPTOR_SIZE             0x12
+#define EDID_DESCRIPTOR_BLOCK0_ADDRESS          0x36
+#define EDID_DESCRIPTOR_BLOCK1_ADDRESS          0x80
+#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR      4
+#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR      4
+
+#define OMAP_HDMI_TIMINGS_NB                    34
+
+#define REG_FLD_MOD(idx, val, start, end) \
+        hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end))
+#define REG_GET(idx, start, end) \
+        FLD_GET(hdmi_read_reg(idx), start, end)
+
+/* HDMI timing structure */
+struct hdmi_timings {
+        struct omap_video_timings timings;
+        int vsync_pol;
+        int hsync_pol;
+};
+
+enum hdmi_phy_pwr {
+        HDMI_PHYPWRCMD_OFF = 0,
+        HDMI_PHYPWRCMD_LDOON = 1,
+        HDMI_PHYPWRCMD_TXON = 2
+};
+
+enum hdmi_pll_pwr {
+        HDMI_PLLPWRCMD_ALLOFF = 0,
+        HDMI_PLLPWRCMD_PLLONLY = 1,
+        HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
+        HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
+};
+
+enum hdmi_clk_refsel {
+        HDMI_REFSEL_PCLK = 0,
+        HDMI_REFSEL_REF1 = 1,
+        HDMI_REFSEL_REF2 = 2,
+        HDMI_REFSEL_SYSCLK = 3
+};
+
+enum hdmi_core_inputbus_width {
+        HDMI_INPUT_8BIT = 0,
+        HDMI_INPUT_10BIT = 1,
+        HDMI_INPUT_12BIT = 2
+};
+
+enum hdmi_core_dither_trunc {
+        HDMI_OUTPUTTRUNCATION_8BIT = 0,
+        HDMI_OUTPUTTRUNCATION_10BIT = 1,
+        HDMI_OUTPUTTRUNCATION_12BIT = 2,
+        HDMI_OUTPUTDITHER_8BIT = 3,
+        HDMI_OUTPUTDITHER_10BIT = 4,
+        HDMI_OUTPUTDITHER_12BIT = 5
+};
+
+enum hdmi_core_deepcolor_ed {
+        HDMI_DEEPCOLORPACKECTDISABLE = 0,
+        HDMI_DEEPCOLORPACKECTENABLE = 1
+};
+
+enum hdmi_core_packet_mode {
+        HDMI_PACKETMODERESERVEDVALUE = 0,
+        HDMI_PACKETMODE24BITPERPIXEL = 4,
+        HDMI_PACKETMODE30BITPERPIXEL = 5,
+        HDMI_PACKETMODE36BITPERPIXEL = 6,
+        HDMI_PACKETMODE48BITPERPIXEL = 7
+};
+
+enum hdmi_core_hdmi_dvi {
+        HDMI_DVI = 0,
+        HDMI_HDMI = 1
+};
+
+enum hdmi_core_tclkselclkmult {
+        HDMI_FPLL05IDCK = 0,
+        HDMI_FPLL10IDCK = 1,
+        HDMI_FPLL20IDCK = 2,
+        HDMI_FPLL40IDCK = 3
+};
+
+enum hdmi_core_packet_ctrl {
+        HDMI_PACKETENABLE = 1,
+        HDMI_PACKETDISABLE = 0,
+        HDMI_PACKETREPEATON = 1,
+        HDMI_PACKETREPEATOFF = 0
+};
+
+/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
+enum hdmi_core_infoframe {
+        HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
+        HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
+        HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
+        HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
+        HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
+        HDMI_INFOFRAME_AVI_DB1B_NO = 0,
+        HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
+        HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
+        HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
+        HDMI_INFOFRAME_AVI_DB1S_0 = 0,
+        HDMI_INFOFRAME_AVI_DB1S_1 = 1,
+        HDMI_INFOFRAME_AVI_DB1S_2 = 2,
+        HDMI_INFOFRAME_AVI_DB2C_NO = 0,
+        HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
+        HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
+        HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
+        HDMI_INFOFRAME_AVI_DB2M_NO = 0,
+        HDMI_INFOFRAME_AVI_DB2M_43 = 1,
+        HDMI_INFOFRAME_AVI_DB2M_169 = 2,
+        HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
+        HDMI_INFOFRAME_AVI_DB2R_43 = 9,
+        HDMI_INFOFRAME_AVI_DB2R_169 = 10,
+        HDMI_INFOFRAME_AVI_DB2R_149 = 11,
+        HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
+        HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
+        HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
+        HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
+        HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
+        HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
+        HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
+        HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
+        HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
+        HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
+        HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
+        HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
+        HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
+        HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
+        HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
+        HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
+        HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
+        HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
+        HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
+        HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
+        HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
+        HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM = 0,
+        HDMI_INFOFRAME_AUDIO_DB1CT_IEC60958 = 1,
+        HDMI_INFOFRAME_AUDIO_DB1CT_AC3 = 2,
+        HDMI_INFOFRAME_AUDIO_DB1CT_MPEG1 = 3,
+        HDMI_INFOFRAME_AUDIO_DB1CT_MP3 = 4,
+        HDMI_INFOFRAME_AUDIO_DB1CT_MPEG2_MULTICH = 5,
+        HDMI_INFOFRAME_AUDIO_DB1CT_AAC = 6,
+        HDMI_INFOFRAME_AUDIO_DB1CT_DTS = 7,
+        HDMI_INFOFRAME_AUDIO_DB1CT_ATRAC = 8,
+        HDMI_INFOFRAME_AUDIO_DB1CT_ONEBIT = 9,
+        HDMI_INFOFRAME_AUDIO_DB1CT_DOLBY_DIGITAL_PLUS = 10,
+        HDMI_INFOFRAME_AUDIO_DB1CT_DTS_HD = 11,
+        HDMI_INFOFRAME_AUDIO_DB1CT_MAT = 12,
+        HDMI_INFOFRAME_AUDIO_DB1CT_DST = 13,
+        HDMI_INFOFRAME_AUDIO_DB1CT_WMA_PRO = 14,
+        HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM = 0,
+        HDMI_INFOFRAME_AUDIO_DB2SF_32000 = 1,
+        HDMI_INFOFRAME_AUDIO_DB2SF_44100 = 2,
+        HDMI_INFOFRAME_AUDIO_DB2SF_48000 = 3,
+        HDMI_INFOFRAME_AUDIO_DB2SF_88200 = 4,
+        HDMI_INFOFRAME_AUDIO_DB2SF_96000 = 5,
+        HDMI_INFOFRAME_AUDIO_DB2SF_176400 = 6,
+        HDMI_INFOFRAME_AUDIO_DB2SF_192000 = 7,
+        HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM = 0,
+        HDMI_INFOFRAME_AUDIO_DB2SS_16BIT = 1,
+        HDMI_INFOFRAME_AUDIO_DB2SS_20BIT = 2,
+        HDMI_INFOFRAME_AUDIO_DB2SS_24BIT = 3,
+        HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PERMITTED = 0,
+        HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PROHIBITED = 1
+};
+
+enum hdmi_packing_mode {
+        HDMI_PACK_10b_RGB_YUV444 = 0,
+        HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
+        HDMI_PACK_20b_YUV422 = 2,
+        HDMI_PACK_ALREADYPACKED = 7
+};
+
+enum hdmi_core_audio_sample_freq {
+        HDMI_AUDIO_FS_32000 = 0x3,
+        HDMI_AUDIO_FS_44100 = 0x0,
+        HDMI_AUDIO_FS_48000 = 0x2,
+        HDMI_AUDIO_FS_88200 = 0x8,
+        HDMI_AUDIO_FS_96000 = 0xA,
+        HDMI_AUDIO_FS_176400 = 0xC,
+        HDMI_AUDIO_FS_192000 = 0xE,
+        HDMI_AUDIO_FS_NOT_INDICATED = 0x1
+};
+
+enum hdmi_core_audio_layout {
+        HDMI_AUDIO_LAYOUT_2CH = 0,
+        HDMI_AUDIO_LAYOUT_8CH = 1
+};
+
+enum hdmi_core_cts_mode {
+        HDMI_AUDIO_CTS_MODE_HW = 0,
+        HDMI_AUDIO_CTS_MODE_SW = 1
+};
+
+enum hdmi_stereo_channels {
+        HDMI_AUDIO_STEREO_NOCHANNELS = 0,
+        HDMI_AUDIO_STEREO_ONECHANNEL = 1,
+        HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
+        HDMI_AUDIO_STEREO_THREECHANNELS = 3,
+        HDMI_AUDIO_STEREO_FOURCHANNELS = 4
+};
+
+enum hdmi_audio_type {
+        HDMI_AUDIO_TYPE_LPCM = 0,
+        HDMI_AUDIO_TYPE_IEC = 1
+};
+
+enum hdmi_audio_justify {
+        HDMI_AUDIO_JUSTIFY_LEFT = 0,
+        HDMI_AUDIO_JUSTIFY_RIGHT = 1
+};
+
+enum hdmi_audio_sample_order {
+        HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
+        HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
+};
+
+enum hdmi_audio_samples_perword {
+        HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
+        HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
+};
+
+enum hdmi_audio_sample_size {
+        HDMI_AUDIO_SAMPLE_16BITS = 0,
+        HDMI_AUDIO_SAMPLE_24BITS = 1
+};
+
+enum hdmi_audio_transf_mode {
+        HDMI_AUDIO_TRANSF_DMA = 0,
+        HDMI_AUDIO_TRANSF_IRQ = 1
+};
+
+enum hdmi_audio_blk_strt_end_sig {
+        HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
+        HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
+};
+
+enum hdmi_audio_i2s_config {
+        HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT = 0,
+        HDMI_AUDIO_I2S_WS_POLARIT_YLOW_IS_RIGHT = 1,
+        HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
+        HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
+        HDMI_AUDIO_I2S_MAX_WORD_20BITS = 0,
+        HDMI_AUDIO_I2S_MAX_WORD_24BITS = 1,
+        HDMI_AUDIO_I2S_CHST_WORD_NOT_SPECIFIED = 0,
+        HDMI_AUDIO_I2S_CHST_WORD_16_BITS = 1,
+        HDMI_AUDIO_I2S_CHST_WORD_17_BITS = 6,
+        HDMI_AUDIO_I2S_CHST_WORD_18_BITS = 2,
+        HDMI_AUDIO_I2S_CHST_WORD_19_BITS = 4,
+        HDMI_AUDIO_I2S_CHST_WORD_20_BITS_20MAX = 5,
+        HDMI_AUDIO_I2S_CHST_WORD_20_BITS_24MAX = 1,
+        HDMI_AUDIO_I2S_CHST_WORD_21_BITS = 6,
+        HDMI_AUDIO_I2S_CHST_WORD_22_BITS = 2,
+        HDMI_AUDIO_I2S_CHST_WORD_23_BITS = 4,
+        HDMI_AUDIO_I2S_CHST_WORD_24_BITS = 5,
+        HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
+        HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
+        HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
+        HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_NA = 0,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_16 = 2,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_17 = 12,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_18 = 4,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_19 = 8,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_20 = 10,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_21 = 13,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_22 = 5,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_23 = 9,
+        HDMI_AUDIO_I2S_INPUT_LENGTH_24 = 11,
+        HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
+        HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
+        HDMI_AUDIO_I2S_SD0_EN = 1,
+        HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
+        HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
+        HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
+};
+
+enum hdmi_audio_mclk_mode {
+        HDMI_AUDIO_MCLK_128FS = 0,
+        HDMI_AUDIO_MCLK_256FS = 1,
+        HDMI_AUDIO_MCLK_384FS = 2,
+        HDMI_AUDIO_MCLK_512FS = 3,
+        HDMI_AUDIO_MCLK_768FS = 4,
+        HDMI_AUDIO_MCLK_1024FS = 5,
+        HDMI_AUDIO_MCLK_1152FS = 6,
+        HDMI_AUDIO_MCLK_192FS = 7
+};
+
+struct hdmi_core_video_config {
+        enum hdmi_core_inputbus_width   ip_bus_width;
+        enum hdmi_core_dither_trunc     op_dither_truc;
+        enum hdmi_core_deepcolor_ed     deep_color_pkt;
+        enum hdmi_core_packet_mode      pkt_mode;
+        enum hdmi_core_hdmi_dvi         hdmi_dvi;
+        enum hdmi_core_tclkselclkmult   tclk_sel_clkmult;
+};
+
+/*
+ * Refer to section 8.2 in HDMI 1.3 specification for
+ * details about infoframe databytes
+ */
+struct hdmi_core_infoframe_avi {
+        u8      db1_format;
+                /* Y0, Y1 rgb,yCbCr */
+        u8      db1_active_info;
+                /* A0  Active information Present */
+        u8      db1_bar_info_dv;
+                /* B0, B1 Bar info data valid */
+        u8      db1_scan_info;
+                /* S0, S1 scan information */
+        u8      db2_colorimetry;
+                /* C0, C1 colorimetry */
+        u8      db2_aspect_ratio;
+                /* M0, M1 Aspect ratio (4:3, 16:9) */
+        u8      db2_active_fmt_ar;
+                /* R0...R3 Active format aspect ratio */
+        u8      db3_itc;
+                /* ITC IT content. */
+        u8      db3_ec;
+                /* EC0, EC1, EC2 Extended colorimetry */
+        u8      db3_q_range;
+                /* Q1, Q0 Quantization range */
+        u8      db3_nup_scaling;
+                /* SC1, SC0 Non-uniform picture scaling */
+        u8      db4_videocode;
+                /* VIC0..6 Video format identification */
+        u8      db5_pixel_repeat;
+                /* PR0..PR3 Pixel repetition factor */
+        u16     db6_7_line_eoftop;
+                /* Line number end of top bar */
+        u16     db8_9_line_sofbottom;
+                /* Line number start of bottom bar */
+        u16     db10_11_pixel_eofleft;
+                /* Pixel number end of left bar */
+        u16     db12_13_pixel_sofright;
+                /* Pixel number start of right bar */
+};
+/*
+ * Refer to section 8.2 in HDMI 1.3 specification for
+ * details about infoframe databytes
+ */
+struct hdmi_core_infoframe_audio {
+        u8 db1_coding_type;
+        u8 db1_channel_count;
+        u8 db2_sample_freq;
+        u8 db2_sample_size;
+        u8 db4_channel_alloc;
+        bool db5_downmix_inh;
+        u8 db5_lsv;     /* Level shift values for downmix */
+};
+
+struct hdmi_core_packet_enable_repeat {
+        u32     audio_pkt;
+        u32     audio_pkt_repeat;
+        u32     avi_infoframe;
+        u32     avi_infoframe_repeat;
+        u32     gen_cntrl_pkt;
+        u32     gen_cntrl_pkt_repeat;
+        u32     generic_pkt;
+        u32     generic_pkt_repeat;
+};
+
+struct hdmi_video_format {
+        enum hdmi_packing_mode  packing_mode;
+        u32                     y_res;  /* Line per panel */
+        u32                     x_res;  /* pixel per line */
+};
+
+struct hdmi_video_interface {
+        int     vsp;    /* Vsync polarity */
+        int     hsp;    /* Hsync polarity */
+        int     interlacing;
+        int     tm;     /* Timing mode */
+};
+
+struct hdmi_cm {
+        int     code;
+        int     mode;
+};
+
+struct hdmi_config {
+        struct hdmi_timings timings;
+        u16     interlace;
+        struct hdmi_cm cm;
+};
+
+struct hdmi_audio_format {
+        enum hdmi_stereo_channels               stereo_channels;
+        u8                                      active_chnnls_msk;
+        enum hdmi_audio_type                    type;
+        enum hdmi_audio_justify                 justification;
+        enum hdmi_audio_sample_order            sample_order;
+        enum hdmi_audio_samples_perword         samples_per_word;
+        enum hdmi_audio_sample_size             sample_size;
+        enum hdmi_audio_blk_strt_end_sig        en_sig_blk_strt_end;
+};
+
+struct hdmi_audio_dma {
+        u8                              transfer_size;
+        u8                              block_size;
+        enum hdmi_audio_transf_mode     mode;
+        u16                             fifo_threshold;
+};
+
+struct hdmi_core_audio_i2s_config {
+        u8 word_max_length;
+        u8 word_length;
+        u8 in_length_bits;
+        u8 justification;
+        u8 en_high_bitrate_aud;
+        u8 sck_edge_mode;
+        u8 cbit_order;
+        u8 vbit;
+        u8 ws_polarity;
+        u8 direction;
+        u8 shift;
+        u8 active_sds;
+};
+
+struct hdmi_core_audio_config {
+        struct hdmi_core_audio_i2s_config       i2s_cfg;
+        enum hdmi_core_audio_sample_freq        freq_sample;
+        bool                                    fs_override;
+        u32                                     n;
+        u32                                     cts;
+        u32                                     aud_par_busclk;
+        enum hdmi_core_audio_layout             layout;
+        enum hdmi_core_cts_mode                 cts_mode;
+        bool                                    use_mclk;
+        enum hdmi_audio_mclk_mode               mclk_mode;
+        bool                                    en_acr_pkt;
+        bool                                    en_dsd_audio;
+        bool                                    en_parallel_aud_input;
+        bool                                    en_spdif;
+};
+#endif
diff --git a/drivers/video/omap2/dss/hdmi_omap4_panel.c b/drivers/video/omap2/dss/hdmi_omap4_panel.c
new file mode 100644
index 00000000000..7d4f2bd7c50
--- /dev/null
+++ b/drivers/video/omap2/dss/hdmi_omap4_panel.c
@@ -0,0 +1,222 @@
+/*
+ * hdmi_omap4_panel.c
+ *
+ * HDMI library support functions for TI OMAP4 processors.
+ *
+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Authors:     Mythri P k <mythripk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/module.h>
+#include <video/omapdss.h>
+
+#include "dss.h"
+
+static struct {
+        struct mutex hdmi_lock;
+} hdmi;
+
+
+static int hdmi_panel_probe(struct omap_dss_device *dssdev)
+{
+        DSSDBG("ENTER hdmi_panel_probe\n");
+
+        dssdev->panel.config = OMAP_DSS_LCD_TFT |
+                        OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS;
+
+        /*
+         * Initialize the timings to 640 * 480
+         * This is only for framebuffer update not for TV timing setting
+         * Setting TV timing will be done only on enable
+         */
+        dssdev->panel.timings.x_res = 640;
+        dssdev->panel.timings.y_res = 480;
+
+        DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n",
+                dssdev->panel.timings.x_res,
+                dssdev->panel.timings.y_res);
+        return 0;
+}
+
+static void hdmi_panel_remove(struct omap_dss_device *dssdev)
+{
+
+}
+
+static int hdmi_panel_enable(struct omap_dss_device *dssdev)
+{
+        int r = 0;
+        DSSDBG("ENTER hdmi_panel_enable\n");
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
+                r = -EINVAL;
+                goto err;
+        }
+
+        r = omapdss_hdmi_display_enable(dssdev);
+        if (r) {
+                DSSERR("failed to power on\n");
+                goto err;
+        }
+
+        dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+err:
+        mutex_unlock(&hdmi.hdmi_lock);
+
+        return r;
+}
+
+static void hdmi_panel_disable(struct omap_dss_device *dssdev)
+{
+        mutex_lock(&hdmi.hdmi_lock);
+
+        if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
+                omapdss_hdmi_display_disable(dssdev);
+
+        dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+
+        mutex_unlock(&hdmi.hdmi_lock);
+}
+
+static int hdmi_panel_suspend(struct omap_dss_device *dssdev)
+{
+        int r = 0;
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) {
+                r = -EINVAL;
+                goto err;
+        }
+
+        dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
+
+        omapdss_hdmi_display_disable(dssdev);
+
+err:
+        mutex_unlock(&hdmi.hdmi_lock);
+
+        return r;
+}
+
+static int hdmi_panel_resume(struct omap_dss_device *dssdev)
+{
+        int r = 0;
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
+                r = -EINVAL;
+                goto err;
+        }
+
+        r = omapdss_hdmi_display_enable(dssdev);
+        if (r) {
+                DSSERR("failed to power on\n");
+                goto err;
+        }
+
+        dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+err:
+        mutex_unlock(&hdmi.hdmi_lock);
+
+        return r;
+}
+
+static void hdmi_get_timings(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings)
+{
+        mutex_lock(&hdmi.hdmi_lock);
+
+        *timings = dssdev->panel.timings;
+
+        mutex_unlock(&hdmi.hdmi_lock);
+}
+
+static void hdmi_set_timings(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings)
+{
+        DSSDBG("hdmi_set_timings\n");
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        dssdev->panel.timings = *timings;
+
+        if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
+                /* turn the hdmi off and on to get new timings to use */
+                omapdss_hdmi_display_disable(dssdev);
+                omapdss_hdmi_display_set_timing(dssdev);
+        }
+
+        mutex_unlock(&hdmi.hdmi_lock);
+}
+
+static int hdmi_check_timings(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings)
+{
+        int r = 0;
+
+        DSSDBG("hdmi_check_timings\n");
+
+        mutex_lock(&hdmi.hdmi_lock);
+
+        r = omapdss_hdmi_display_check_timing(dssdev, timings);
+        if (r) {
+                DSSERR("Timing cannot be applied\n");
+                goto err;
+        }
+err:
+        mutex_unlock(&hdmi.hdmi_lock);
+        return r;
+}
+
+static struct omap_dss_driver hdmi_driver = {
+        .probe          = hdmi_panel_probe,
+        .remove         = hdmi_panel_remove,
+        .enable         = hdmi_panel_enable,
+        .disable        = hdmi_panel_disable,
+        .suspend        = hdmi_panel_suspend,
+        .resume         = hdmi_panel_resume,
+        .get_timings    = hdmi_get_timings,
+        .set_timings    = hdmi_set_timings,
+        .check_timings  = hdmi_check_timings,
+        .driver                 = {
+                .name   = "hdmi_panel",
+                .owner  = THIS_MODULE,
+        },
+};
+
+int hdmi_panel_init(void)
+{
+        mutex_init(&hdmi.hdmi_lock);
+
+        omap_dss_register_driver(&hdmi_driver);
+
+        return 0;
+}
+
+void hdmi_panel_exit(void)
+{
+        omap_dss_unregister_driver(&hdmi_driver);
+
+}
diff --git a/drivers/video/omap2/vram.c b/drivers/video/omap2/vram.c
new file mode 100644
index 00000000000..9441e2eb3de
--- /dev/null
+++ b/drivers/video/omap2/vram.c
@@ -0,0 +1,659 @@
+/*
+ * VRAM manager for OMAP
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+/*#define DEBUG*/
+
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+#include <linux/memblock.h>
+#include <linux/completion.h>
+#include <linux/debugfs.h>
+#include <linux/jiffies.h>
+#include <linux/module.h>
+
+#include <asm/setup.h>
+
+#include <plat/sram.h>
+#include <plat/vram.h>
+#include <plat/dma.h>
+
+#ifdef DEBUG
+#define DBG(format, ...) pr_debug("VRAM: " format, ## __VA_ARGS__)
+#else
+#define DBG(format, ...)
+#endif
+
+#define OMAP2_SRAM_START                0x40200000
+/* Maximum size, in reality this is smaller if SRAM is partially locked. */
+#define OMAP2_SRAM_SIZE                 0xa0000         /* 640k */
+
+/* postponed regions are used to temporarily store region information at boot
+ * time when we cannot yet allocate the region list */
+#define MAX_POSTPONED_REGIONS 10
+
+static bool vram_initialized;
+static int postponed_cnt;
+static struct {
+        unsigned long paddr;
+        size_t size;
+} postponed_regions[MAX_POSTPONED_REGIONS];
+
+struct vram_alloc {
+        struct list_head list;
+        unsigned long paddr;
+        unsigned pages;
+};
+
+struct vram_region {
+        struct list_head list;
+        struct list_head alloc_list;
+        unsigned long paddr;
+        unsigned pages;
+};
+
+static DEFINE_MUTEX(region_mutex);
+static LIST_HEAD(region_list);
+
+static inline int region_mem_type(unsigned long paddr)
+{
+        if (paddr >= OMAP2_SRAM_START &&
+            paddr < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
+                return OMAP_VRAM_MEMTYPE_SRAM;
+        else
+                return OMAP_VRAM_MEMTYPE_SDRAM;
+}
+
+static struct vram_region *omap_vram_create_region(unsigned long paddr,
+                unsigned pages)
+{
+        struct vram_region *rm;
+
+        rm = kzalloc(sizeof(*rm), GFP_KERNEL);
+
+        if (rm) {
+                INIT_LIST_HEAD(&rm->alloc_list);
+                rm->paddr = paddr;
+                rm->pages = pages;
+        }
+
+        return rm;
+}
+
+#if 0
+static void omap_vram_free_region(struct vram_region *vr)
+{
+        list_del(&vr->list);
+        kfree(vr);
+}
+#endif
+
+static struct vram_alloc *omap_vram_create_allocation(struct vram_region *vr,
+                unsigned long paddr, unsigned pages)
+{
+        struct vram_alloc *va;
+        struct vram_alloc *new;
+
+        new = kzalloc(sizeof(*va), GFP_KERNEL);
+
+        if (!new)
+                return NULL;
+
+        new->paddr = paddr;
+        new->pages = pages;
+
+        list_for_each_entry(va, &vr->alloc_list, list) {
+                if (va->paddr > new->paddr)
+                        break;
+        }
+
+        list_add_tail(&new->list, &va->list);
+
+        return new;
+}
+
+static void omap_vram_free_allocation(struct vram_alloc *va)
+{
+        list_del(&va->list);
+        kfree(va);
+}
+
+int omap_vram_add_region(unsigned long paddr, size_t size)
+{
+        struct vram_region *rm;
+        unsigned pages;
+
+        if (vram_initialized) {
+                DBG("adding region paddr %08lx size %d\n",
+                                paddr, size);
+
+                size &= PAGE_MASK;
+                pages = size >> PAGE_SHIFT;
+
+                rm = omap_vram_create_region(paddr, pages);
+                if (rm == NULL)
+                        return -ENOMEM;
+
+                list_add(&rm->list, &region_list);
+        } else {
+                if (postponed_cnt == MAX_POSTPONED_REGIONS)
+                        return -ENOMEM;
+
+                postponed_regions[postponed_cnt].paddr = paddr;
+                postponed_regions[postponed_cnt].size = size;
+
+                ++postponed_cnt;
+        }
+        return 0;
+}
+
+int omap_vram_free(unsigned long paddr, size_t size)
+{
+        struct vram_region *rm;
+        struct vram_alloc *alloc;
+        unsigned start, end;
+
+        DBG("free mem paddr %08lx size %d\n", paddr, size);
+
+        size = PAGE_ALIGN(size);
+
+        mutex_lock(&region_mutex);
+
+        list_for_each_entry(rm, &region_list, list) {
+                list_for_each_entry(alloc, &rm->alloc_list, list) {
+                        start = alloc->paddr;
+                        end = alloc->paddr + (alloc->pages >> PAGE_SHIFT);
+
+                        if (start >= paddr && end < paddr + size)
+                                goto found;
+                }
+        }
+
+        mutex_unlock(&region_mutex);
+        return -EINVAL;
+
+found:
+        omap_vram_free_allocation(alloc);
+
+        mutex_unlock(&region_mutex);
+        return 0;
+}
+EXPORT_SYMBOL(omap_vram_free);
+
+static int _omap_vram_reserve(unsigned long paddr, unsigned pages)
+{
+        struct vram_region *rm;
+        struct vram_alloc *alloc;
+        size_t size;
+
+        size = pages << PAGE_SHIFT;
+
+        list_for_each_entry(rm, &region_list, list) {
+                unsigned long start, end;
+
+                DBG("checking region %lx %d\n", rm->paddr, rm->pages);
+
+                if (region_mem_type(rm->paddr) != region_mem_type(paddr))
+                        continue;
+
+                start = rm->paddr;
+                end = start + (rm->pages << PAGE_SHIFT) - 1;
+                if (start > paddr || end < paddr + size - 1)
+                        continue;
+
+                DBG("block ok, checking allocs\n");
+
+                list_for_each_entry(alloc, &rm->alloc_list, list) {
+                        end = alloc->paddr - 1;
+
+                        if (start <= paddr && end >= paddr + size - 1)
+                                goto found;
+
+                        start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
+                }
+
+                end = rm->paddr + (rm->pages << PAGE_SHIFT) - 1;
+
+                if (!(start <= paddr && end >= paddr + size - 1))
+                        continue;
+found:
+                DBG("found area start %lx, end %lx\n", start, end);
+
+                if (omap_vram_create_allocation(rm, paddr, pages) == NULL)
+                        return -ENOMEM;
+
+                return 0;
+        }
+
+        return -ENOMEM;
+}
+
+int omap_vram_reserve(unsigned long paddr, size_t size)
+{
+        unsigned pages;
+        int r;
+
+        DBG("reserve mem paddr %08lx size %d\n", paddr, size);
+
+        size = PAGE_ALIGN(size);
+        pages = size >> PAGE_SHIFT;
+
+        mutex_lock(&region_mutex);
+
+        r = _omap_vram_reserve(paddr, pages);
+
+        mutex_unlock(&region_mutex);
+
+        return r;
+}
+EXPORT_SYMBOL(omap_vram_reserve);
+
+static void _omap_vram_dma_cb(int lch, u16 ch_status, void *data)
+{
+        struct completion *compl = data;
+        complete(compl);
+}
+
+static int _omap_vram_clear(u32 paddr, unsigned pages)
+{
+        struct completion compl;
+        unsigned elem_count;
+        unsigned frame_count;
+        int r;
+        int lch;
+
+        init_completion(&compl);
+
+        r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA",
+                        _omap_vram_dma_cb,
+                        &compl, &lch);
+        if (r) {
+                pr_err("VRAM: request_dma failed for memory clear\n");
+                return -EBUSY;
+        }
+
+        elem_count = pages * PAGE_SIZE / 4;
+        frame_count = 1;
+
+        omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32,
+                        elem_count, frame_count,
+                        OMAP_DMA_SYNC_ELEMENT,
+                        0, 0);
+
+        omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC,
+                        paddr, 0, 0);
+
+        omap_set_dma_color_mode(lch, OMAP_DMA_CONSTANT_FILL, 0x000000);
+
+        omap_start_dma(lch);
+
+        if (wait_for_completion_timeout(&compl, msecs_to_jiffies(1000)) == 0) {
+                omap_stop_dma(lch);
+                pr_err("VRAM: dma timeout while clearing memory\n");
+                r = -EIO;
+                goto err;
+        }
+
+        r = 0;
+err:
+        omap_free_dma(lch);
+
+        return r;
+}
+
+static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
+{
+        struct vram_region *rm;
+        struct vram_alloc *alloc;
+
+        list_for_each_entry(rm, &region_list, list) {
+                unsigned long start, end;
+
+                DBG("checking region %lx %d\n", rm->paddr, rm->pages);
+
+                if (region_mem_type(rm->paddr) != mtype)
+                        continue;
+
+                start = rm->paddr;
+
+                list_for_each_entry(alloc, &rm->alloc_list, list) {
+                        end = alloc->paddr;
+
+                        if (end - start >= pages << PAGE_SHIFT)
+                                goto found;
+
+                        start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
+                }
+
+                end = rm->paddr + (rm->pages << PAGE_SHIFT);
+found:
+                if (end - start < pages << PAGE_SHIFT)
+                        continue;
+
+                DBG("found %lx, end %lx\n", start, end);
+
+                alloc = omap_vram_create_allocation(rm, start, pages);
+                if (alloc == NULL)
+                        return -ENOMEM;
+
+                *paddr = start;
+
+                _omap_vram_clear(start, pages);
+
+                return 0;
+        }
+
+        return -ENOMEM;
+}
+
+int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
+{
+        unsigned pages;
+        int r;
+
+        BUG_ON(mtype > OMAP_VRAM_MEMTYPE_MAX || !size);
+
+        DBG("alloc mem type %d size %d\n", mtype, size);
+
+        size = PAGE_ALIGN(size);
+        pages = size >> PAGE_SHIFT;
+
+        mutex_lock(&region_mutex);
+
+        r = _omap_vram_alloc(mtype, pages, paddr);
+
+        mutex_unlock(&region_mutex);
+
+        return r;
+}
+EXPORT_SYMBOL(omap_vram_alloc);
+
+void omap_vram_get_info(unsigned long *vram,
+                unsigned long *free_vram,
+                unsigned long *largest_free_block)
+{
+        struct vram_region *vr;
+        struct vram_alloc *va;
+
+        *vram = 0;
+        *free_vram = 0;
+        *largest_free_block = 0;
+
+        mutex_lock(&region_mutex);
+
+        list_for_each_entry(vr, &region_list, list) {
+                unsigned free;
+                unsigned long pa;
+
+                pa = vr->paddr;
+                *vram += vr->pages << PAGE_SHIFT;
+
+                list_for_each_entry(va, &vr->alloc_list, list) {
+                        free = va->paddr - pa;
+                        *free_vram += free;
+                        if (free > *largest_free_block)
+                                *largest_free_block = free;
+                        pa = va->paddr + (va->pages << PAGE_SHIFT);
+                }
+
+                free = vr->paddr + (vr->pages << PAGE_SHIFT) - pa;
+                *free_vram += free;
+                if (free > *largest_free_block)
+                        *largest_free_block = free;
+        }
+
+        mutex_unlock(&region_mutex);
+}
+EXPORT_SYMBOL(omap_vram_get_info);
+
+#if defined(CONFIG_DEBUG_FS)
+static int vram_debug_show(struct seq_file *s, void *unused)
+{
+        struct vram_region *vr;
+        struct vram_alloc *va;
+        unsigned size;
+
+        mutex_lock(&region_mutex);
+
+        list_for_each_entry(vr, &region_list, list) {
+                size = vr->pages << PAGE_SHIFT;
+                seq_printf(s, "%08lx-%08lx (%d bytes)\n",
+                                vr->paddr, vr->paddr + size - 1,
+                                size);
+
+                list_for_each_entry(va, &vr->alloc_list, list) {
+                        size = va->pages << PAGE_SHIFT;
+                        seq_printf(s, "    %08lx-%08lx (%d bytes)\n",
+                                        va->paddr, va->paddr + size - 1,
+                                        size);
+                }
+        }
+
+        mutex_unlock(&region_mutex);
+
+        return 0;
+}
+
+static int vram_debug_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, vram_debug_show, inode->i_private);
+}
+
+static const struct file_operations vram_debug_fops = {
+        .open           = vram_debug_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int __init omap_vram_create_debugfs(void)
+{
+        struct dentry *d;
+
+        d = debugfs_create_file("vram", S_IRUGO, NULL,
+                        NULL, &vram_debug_fops);
+        if (IS_ERR(d))
+                return PTR_ERR(d);
+
+        return 0;
+}
+#endif
+
+static __init int omap_vram_init(void)
+{
+        int i;
+
+        vram_initialized = 1;
+
+        for (i = 0; i < postponed_cnt; i++)
+                omap_vram_add_region(postponed_regions[i].paddr,
+                                postponed_regions[i].size);
+
+#ifdef CONFIG_DEBUG_FS
+        if (omap_vram_create_debugfs())
+                pr_err("VRAM: Failed to create debugfs file\n");
+#endif
+
+        return 0;
+}
+
+arch_initcall(omap_vram_init);
+
+/* boottime vram alloc stuff */
+
+/* set from board file */
+static u32 omap_vram_sram_start __initdata;
+static u32 omap_vram_sram_size __initdata;
+
+/* set from board file */
+static u32 omap_vram_sdram_start __initdata;
+static u32 omap_vram_sdram_size __initdata;
+
+/* set from kernel cmdline */
+static u32 omap_vram_def_sdram_size __initdata;
+static u32 omap_vram_def_sdram_start __initdata;
+
+static int __init omap_vram_early_vram(char *p)
+{
+        omap_vram_def_sdram_size = memparse(p, &p);
+        if (*p == ',')
+                omap_vram_def_sdram_start = simple_strtoul(p + 1, &p, 16);
+        return 0;
+}
+early_param("vram", omap_vram_early_vram);
+
+/*
+ * Called from map_io. We need to call to this early enough so that we
+ * can reserve the fixed SDRAM regions before VM could get hold of them.
+ */
+void __init omap_vram_reserve_sdram_memblock(void)
+{
+        u32 paddr;
+        u32 size = 0;
+
+        /* cmdline arg overrides the board file definition */
+        if (omap_vram_def_sdram_size) {
+                size = omap_vram_def_sdram_size;
+                paddr = omap_vram_def_sdram_start;
+        }
+
+        if (!size) {
+                size = omap_vram_sdram_size;
+                paddr = omap_vram_sdram_start;
+        }
+
+#ifdef CONFIG_OMAP2_VRAM_SIZE
+        if (!size) {
+                size = CONFIG_OMAP2_VRAM_SIZE * 1024 * 1024;
+                paddr = 0;
+        }
+#endif
+
+        if (!size)
+                return;
+
+        size = ALIGN(size, SZ_2M);
+
+        if (paddr) {
+                if (paddr & ~PAGE_MASK) {
+                        pr_err("VRAM start address 0x%08x not page aligned\n",
+                                        paddr);
+                        return;
+                }
+
+                if (!memblock_is_region_memory(paddr, size)) {
+                        pr_err("Illegal SDRAM region 0x%08x..0x%08x for VRAM\n",
+                                        paddr, paddr + size - 1);
+                        return;
+                }
+
+                if (memblock_is_region_reserved(paddr, size)) {
+                        pr_err("FB: failed to reserve VRAM - busy\n");
+                        return;
+                }
+
+                if (memblock_reserve(paddr, size) < 0) {
+                        pr_err("FB: failed to reserve VRAM - no memory\n");
+                        return;
+                }
+        } else {
+                paddr = memblock_alloc(size, SZ_2M);
+        }
+
+        memblock_free(paddr, size);
+        memblock_remove(paddr, size);
+
+        omap_vram_add_region(paddr, size);
+
+        pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
+}
+
+/*
+ * Called at sram init time, before anything is pushed to the SRAM stack.
+ * Because of the stack scheme, we will allocate everything from the
+ * start of the lowest address region to the end of SRAM. This will also
+ * include padding for page alignment and possible holes between regions.
+ *
+ * As opposed to the SDRAM case, we'll also do any dynamic allocations at
+ * this point, since the driver built as a module would have problem with
+ * freeing / reallocating the regions.
+ */
+unsigned long __init omap_vram_reserve_sram(unsigned long sram_pstart,
+                                  unsigned long sram_vstart,
+                                  unsigned long sram_size,
+                                  unsigned long pstart_avail,
+                                  unsigned long size_avail)
+{
+        unsigned long                   pend_avail;
+        unsigned long                   reserved;
+        u32 paddr;
+        u32 size;
+
+        paddr = omap_vram_sram_start;
+        size = omap_vram_sram_size;
+
+        if (!size)
+                return 0;
+
+        reserved = 0;
+        pend_avail = pstart_avail + size_avail;
+
+        if (!paddr) {
+                /* Dynamic allocation */
+                if ((size_avail & PAGE_MASK) < size) {
+                        pr_err("Not enough SRAM for VRAM\n");
+                        return 0;
+                }
+                size_avail = (size_avail - size) & PAGE_MASK;
+                paddr = pstart_avail + size_avail;
+        }
+
+        if (paddr < sram_pstart ||
+                        paddr + size > sram_pstart + sram_size) {
+                pr_err("Illegal SRAM region for VRAM\n");
+                return 0;
+        }
+
+        /* Reserve everything above the start of the region. */
+        if (pend_avail - paddr > reserved)
+                reserved = pend_avail - paddr;
+        size_avail = pend_avail - reserved - pstart_avail;
+
+        omap_vram_add_region(paddr, size);
+
+        if (reserved)
+                pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
+
+        return reserved;
+}
+
+void __init omap_vram_set_sdram_vram(u32 size, u32 start)
+{
+        omap_vram_sdram_start = start;
+        omap_vram_sdram_size = size;
+}
+
+void __init omap_vram_set_sram_vram(u32 size, u32 start)
+{
+        omap_vram_sram_start = start;
+        omap_vram_sram_size = size;
+}