OMAP4: DSS2: HDMI: HDMI clean up to pass base_address

As the base_address of the HDMI might differ across SoC's, offset of the HDMI
logical blocks(PHY, PLL and Core) and base address procured from the platform
data are passed dynamically to the functions that modify HDMI IP registers.

Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

1 files changed, 145 insertions, 147 deletions

diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h
index c885f9cb065..ee37bd93211 100644
--- a/drivers/video/omap2/dss/hdmi.h
+++ b/drivers/video/omap2/dss/hdmi.h
@@ -24,174 +24,163 @@
 #include <linux/string.h>
 #include <video/omapdss.h>
 
-#define HDMI_WP         0x0
-#define HDMI_CORE_SYS           0x400
-#define HDMI_CORE_AV            0x900
-#define HDMI_PLLCTRL            0x200
-#define HDMI_PHY                0x300
-
 struct hdmi_reg { u16 idx; };
 
 #define HDMI_REG(idx)                   ((const struct hdmi_reg) { idx })
 
 /* HDMI Wrapper */
-#define HDMI_WP_REG(idx)                        HDMI_REG(HDMI_WP + idx)
-
-#define HDMI_WP_REVISION                        HDMI_WP_REG(0x0)
-#define HDMI_WP_SYSCONFIG                       HDMI_WP_REG(0x10)
-#define HDMI_WP_IRQSTATUS_RAW                   HDMI_WP_REG(0x24)
-#define HDMI_WP_IRQSTATUS                       HDMI_WP_REG(0x28)
-#define HDMI_WP_PWR_CTRL                        HDMI_WP_REG(0x40)
-#define HDMI_WP_IRQENABLE_SET                   HDMI_WP_REG(0x2C)
-#define HDMI_WP_VIDEO_CFG                       HDMI_WP_REG(0x50)
-#define HDMI_WP_VIDEO_SIZE                      HDMI_WP_REG(0x60)
-#define HDMI_WP_VIDEO_TIMING_H                  HDMI_WP_REG(0x68)
-#define HDMI_WP_VIDEO_TIMING_V                  HDMI_WP_REG(0x6C)
-#define HDMI_WP_WP_CLK                          HDMI_WP_REG(0x70)
-#define HDMI_WP_AUDIO_CFG                       HDMI_WP_REG(0x80)
-#define HDMI_WP_AUDIO_CFG2                      HDMI_WP_REG(0x84)
-#define HDMI_WP_AUDIO_CTRL                      HDMI_WP_REG(0x88)
-#define HDMI_WP_AUDIO_DATA                      HDMI_WP_REG(0x8C)
+
+#define HDMI_WP_REVISION                        HDMI_REG(0x0)
+#define HDMI_WP_SYSCONFIG                       HDMI_REG(0x10)
+#define HDMI_WP_IRQSTATUS_RAW                   HDMI_REG(0x24)
+#define HDMI_WP_IRQSTATUS                       HDMI_REG(0x28)
+#define HDMI_WP_PWR_CTRL                        HDMI_REG(0x40)
+#define HDMI_WP_IRQENABLE_SET                   HDMI_REG(0x2C)
+#define HDMI_WP_VIDEO_CFG                       HDMI_REG(0x50)
+#define HDMI_WP_VIDEO_SIZE                      HDMI_REG(0x60)
+#define HDMI_WP_VIDEO_TIMING_H                  HDMI_REG(0x68)
+#define HDMI_WP_VIDEO_TIMING_V                  HDMI_REG(0x6C)
+#define HDMI_WP_WP_CLK                          HDMI_REG(0x70)
+#define HDMI_WP_AUDIO_CFG                       HDMI_REG(0x80)
+#define HDMI_WP_AUDIO_CFG2                      HDMI_REG(0x84)
+#define HDMI_WP_AUDIO_CTRL                      HDMI_REG(0x88)
+#define HDMI_WP_AUDIO_DATA                      HDMI_REG(0x8C)
 
 /* HDMI IP Core System */
-#define HDMI_CORE_SYS_REG(idx)                  HDMI_REG(HDMI_CORE_SYS + idx)
-
-#define HDMI_CORE_SYS_VND_IDL                   HDMI_CORE_SYS_REG(0x0)
-#define HDMI_CORE_SYS_DEV_IDL                   HDMI_CORE_SYS_REG(0x8)
-#define HDMI_CORE_SYS_DEV_IDH                   HDMI_CORE_SYS_REG(0xC)
-#define HDMI_CORE_SYS_DEV_REV                   HDMI_CORE_SYS_REG(0x10)
-#define HDMI_CORE_SYS_SRST                      HDMI_CORE_SYS_REG(0x14)
-#define HDMI_CORE_CTRL1                 HDMI_CORE_SYS_REG(0x20)
-#define HDMI_CORE_SYS_SYS_STAT                  HDMI_CORE_SYS_REG(0x24)
-#define HDMI_CORE_SYS_VID_ACEN                  HDMI_CORE_SYS_REG(0x124)
-#define HDMI_CORE_SYS_VID_MODE                  HDMI_CORE_SYS_REG(0x128)
-#define HDMI_CORE_SYS_INTR_STATE                HDMI_CORE_SYS_REG(0x1C0)
-#define HDMI_CORE_SYS_INTR1                     HDMI_CORE_SYS_REG(0x1C4)
-#define HDMI_CORE_SYS_INTR2                     HDMI_CORE_SYS_REG(0x1C8)
-#define HDMI_CORE_SYS_INTR3                     HDMI_CORE_SYS_REG(0x1CC)
-#define HDMI_CORE_SYS_INTR4                     HDMI_CORE_SYS_REG(0x1D0)
-#define HDMI_CORE_SYS_UMASK1                    HDMI_CORE_SYS_REG(0x1D4)
-#define HDMI_CORE_SYS_TMDS_CTRL         HDMI_CORE_SYS_REG(0x208)
-#define HDMI_CORE_SYS_DE_DLY                    HDMI_CORE_SYS_REG(0xC8)
-#define HDMI_CORE_SYS_DE_CTRL                   HDMI_CORE_SYS_REG(0xCC)
-#define HDMI_CORE_SYS_DE_TOP                    HDMI_CORE_SYS_REG(0xD0)
-#define HDMI_CORE_SYS_DE_CNTL                   HDMI_CORE_SYS_REG(0xD8)
-#define HDMI_CORE_SYS_DE_CNTH                   HDMI_CORE_SYS_REG(0xDC)
-#define HDMI_CORE_SYS_DE_LINL                   HDMI_CORE_SYS_REG(0xE0)
-#define HDMI_CORE_SYS_DE_LINH_1         HDMI_CORE_SYS_REG(0xE4)
+
+#define HDMI_CORE_SYS_VND_IDL                   HDMI_REG(0x0)
+#define HDMI_CORE_SYS_DEV_IDL                   HDMI_REG(0x8)
+#define HDMI_CORE_SYS_DEV_IDH                   HDMI_REG(0xC)
+#define HDMI_CORE_SYS_DEV_REV                   HDMI_REG(0x10)
+#define HDMI_CORE_SYS_SRST                      HDMI_REG(0x14)
+#define HDMI_CORE_CTRL1                         HDMI_REG(0x20)
+#define HDMI_CORE_SYS_SYS_STAT                  HDMI_REG(0x24)
+#define HDMI_CORE_SYS_VID_ACEN                  HDMI_REG(0x124)
+#define HDMI_CORE_SYS_VID_MODE                  HDMI_REG(0x128)
+#define HDMI_CORE_SYS_INTR_STATE                HDMI_REG(0x1C0)
+#define HDMI_CORE_SYS_INTR1                     HDMI_REG(0x1C4)
+#define HDMI_CORE_SYS_INTR2                     HDMI_REG(0x1C8)
+#define HDMI_CORE_SYS_INTR3                     HDMI_REG(0x1CC)
+#define HDMI_CORE_SYS_INTR4                     HDMI_REG(0x1D0)
+#define HDMI_CORE_SYS_UMASK1                    HDMI_REG(0x1D4)
+#define HDMI_CORE_SYS_TMDS_CTRL                 HDMI_REG(0x208)
+#define HDMI_CORE_SYS_DE_DLY                    HDMI_REG(0xC8)
+#define HDMI_CORE_SYS_DE_CTRL                   HDMI_REG(0xCC)
+#define HDMI_CORE_SYS_DE_TOP                    HDMI_REG(0xD0)
+#define HDMI_CORE_SYS_DE_CNTL                   HDMI_REG(0xD8)
+#define HDMI_CORE_SYS_DE_CNTH                   HDMI_REG(0xDC)
+#define HDMI_CORE_SYS_DE_LINL                   HDMI_REG(0xE0)
+#define HDMI_CORE_SYS_DE_LINH_1                 HDMI_REG(0xE4)
 #define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
 #define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
 #define HDMI_CORE_CTRL1_BSEL_24BITBUS           0x1
 #define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
 
 /* HDMI DDC E-DID */
-#define HDMI_CORE_DDC_CMD                       HDMI_CORE_SYS_REG(0x3CC)
-#define HDMI_CORE_DDC_STATUS                    HDMI_CORE_SYS_REG(0x3C8)
-#define HDMI_CORE_DDC_ADDR                      HDMI_CORE_SYS_REG(0x3B4)
-#define HDMI_CORE_DDC_OFFSET                    HDMI_CORE_SYS_REG(0x3BC)
-#define HDMI_CORE_DDC_COUNT1                    HDMI_CORE_SYS_REG(0x3C0)
-#define HDMI_CORE_DDC_COUNT2                    HDMI_CORE_SYS_REG(0x3C4)
-#define HDMI_CORE_DDC_DATA                      HDMI_CORE_SYS_REG(0x3D0)
-#define HDMI_CORE_DDC_SEGM                      HDMI_CORE_SYS_REG(0x3B8)
+#define HDMI_CORE_DDC_CMD                       HDMI_REG(0x3CC)
+#define HDMI_CORE_DDC_STATUS                    HDMI_REG(0x3C8)
+#define HDMI_CORE_DDC_ADDR                      HDMI_REG(0x3B4)
+#define HDMI_CORE_DDC_OFFSET                    HDMI_REG(0x3BC)
+#define HDMI_CORE_DDC_COUNT1                    HDMI_REG(0x3C0)
+#define HDMI_CORE_DDC_COUNT2                    HDMI_REG(0x3C4)
+#define HDMI_CORE_DDC_DATA                      HDMI_REG(0x3D0)
+#define HDMI_CORE_DDC_SEGM                      HDMI_REG(0x3B8)
 
 /* HDMI IP Core Audio Video */
-#define HDMI_CORE_AV_REG(idx)                   HDMI_REG(HDMI_CORE_AV + idx)
-
-#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
-#define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
-#define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
-#define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
-#define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
-#define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
-#define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
-#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
-#define HDMI_CORE_AV_AVI_DBYTE(n)               HDMI_CORE_AV_REG(n * 4 + 0x110)
-#define HDMI_CORE_AV_AVI_DBYTE_NELEMS           HDMI_CORE_AV_REG(15)
-#define HDMI_CORE_AV_SPD_DBYTE                  HDMI_CORE_AV_REG(0x190)
-#define HDMI_CORE_AV_SPD_DBYTE_NELEMS           HDMI_CORE_AV_REG(27)
-#define HDMI_CORE_AV_AUD_DBYTE(n)               HDMI_CORE_AV_REG(n * 4 + 0x210)
-#define HDMI_CORE_AV_AUD_DBYTE_NELEMS           HDMI_CORE_AV_REG(10)
-#define HDMI_CORE_AV_MPEG_DBYTE         HDMI_CORE_AV_REG(0x290)
-#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS          HDMI_CORE_AV_REG(27)
-#define HDMI_CORE_AV_GEN_DBYTE                  HDMI_CORE_AV_REG(0x300)
-#define HDMI_CORE_AV_GEN_DBYTE_NELEMS           HDMI_CORE_AV_REG(31)
-#define HDMI_CORE_AV_GEN2_DBYTE         HDMI_CORE_AV_REG(0x380)
-#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS          HDMI_CORE_AV_REG(31)
-#define HDMI_CORE_AV_ACR_CTRL                   HDMI_CORE_AV_REG(0x4)
-#define HDMI_CORE_AV_FREQ_SVAL                  HDMI_CORE_AV_REG(0x8)
-#define HDMI_CORE_AV_N_SVAL1                    HDMI_CORE_AV_REG(0xC)
-#define HDMI_CORE_AV_N_SVAL2                    HDMI_CORE_AV_REG(0x10)
-#define HDMI_CORE_AV_N_SVAL3                    HDMI_CORE_AV_REG(0x14)
-#define HDMI_CORE_AV_CTS_SVAL1                  HDMI_CORE_AV_REG(0x18)
-#define HDMI_CORE_AV_CTS_SVAL2                  HDMI_CORE_AV_REG(0x1C)
-#define HDMI_CORE_AV_CTS_SVAL3                  HDMI_CORE_AV_REG(0x20)
-#define HDMI_CORE_AV_CTS_HVAL1                  HDMI_CORE_AV_REG(0x24)
-#define HDMI_CORE_AV_CTS_HVAL2                  HDMI_CORE_AV_REG(0x28)
-#define HDMI_CORE_AV_CTS_HVAL3                  HDMI_CORE_AV_REG(0x2C)
-#define HDMI_CORE_AV_AUD_MODE                   HDMI_CORE_AV_REG(0x50)
-#define HDMI_CORE_AV_SPDIF_CTRL         HDMI_CORE_AV_REG(0x54)
-#define HDMI_CORE_AV_HW_SPDIF_FS                HDMI_CORE_AV_REG(0x60)
-#define HDMI_CORE_AV_SWAP_I2S                   HDMI_CORE_AV_REG(0x64)
-#define HDMI_CORE_AV_SPDIF_ERTH         HDMI_CORE_AV_REG(0x6C)
-#define HDMI_CORE_AV_I2S_IN_MAP         HDMI_CORE_AV_REG(0x70)
-#define HDMI_CORE_AV_I2S_IN_CTRL                HDMI_CORE_AV_REG(0x74)
-#define HDMI_CORE_AV_I2S_CHST0                  HDMI_CORE_AV_REG(0x78)
-#define HDMI_CORE_AV_I2S_CHST1                  HDMI_CORE_AV_REG(0x7C)
-#define HDMI_CORE_AV_I2S_CHST2                  HDMI_CORE_AV_REG(0x80)
-#define HDMI_CORE_AV_I2S_CHST4                  HDMI_CORE_AV_REG(0x84)
-#define HDMI_CORE_AV_I2S_CHST5                  HDMI_CORE_AV_REG(0x88)
-#define HDMI_CORE_AV_ASRC                       HDMI_CORE_AV_REG(0x8C)
-#define HDMI_CORE_AV_I2S_IN_LEN         HDMI_CORE_AV_REG(0x90)
-#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_CORE_AV_REG(0xBC)
-#define HDMI_CORE_AV_AUDO_TXSTAT                HDMI_CORE_AV_REG(0xC0)
-#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1           HDMI_CORE_AV_REG(0xCC)
-#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2           HDMI_CORE_AV_REG(0xD0)
-#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3           HDMI_CORE_AV_REG(0xD4)
-#define HDMI_CORE_AV_TEST_TXCTRL                HDMI_CORE_AV_REG(0xF0)
-#define HDMI_CORE_AV_DPD                        HDMI_CORE_AV_REG(0xF4)
-#define HDMI_CORE_AV_PB_CTRL1                   HDMI_CORE_AV_REG(0xF8)
-#define HDMI_CORE_AV_PB_CTRL2                   HDMI_CORE_AV_REG(0xFC)
-#define HDMI_CORE_AV_AVI_TYPE                   HDMI_CORE_AV_REG(0x100)
-#define HDMI_CORE_AV_AVI_VERS                   HDMI_CORE_AV_REG(0x104)
-#define HDMI_CORE_AV_AVI_LEN                    HDMI_CORE_AV_REG(0x108)
-#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_CORE_AV_REG(0x10C)
-#define HDMI_CORE_AV_SPD_TYPE                   HDMI_CORE_AV_REG(0x180)
-#define HDMI_CORE_AV_SPD_VERS                   HDMI_CORE_AV_REG(0x184)
-#define HDMI_CORE_AV_SPD_LEN                    HDMI_CORE_AV_REG(0x188)
-#define HDMI_CORE_AV_SPD_CHSUM                  HDMI_CORE_AV_REG(0x18C)
-#define HDMI_CORE_AV_AUDIO_TYPE         HDMI_CORE_AV_REG(0x200)
-#define HDMI_CORE_AV_AUDIO_VERS         HDMI_CORE_AV_REG(0x204)
-#define HDMI_CORE_AV_AUDIO_LEN                  HDMI_CORE_AV_REG(0x208)
-#define HDMI_CORE_AV_AUDIO_CHSUM                HDMI_CORE_AV_REG(0x20C)
-#define HDMI_CORE_AV_MPEG_TYPE                  HDMI_CORE_AV_REG(0x280)
-#define HDMI_CORE_AV_MPEG_VERS                  HDMI_CORE_AV_REG(0x284)
-#define HDMI_CORE_AV_MPEG_LEN                   HDMI_CORE_AV_REG(0x288)
-#define HDMI_CORE_AV_MPEG_CHSUM         HDMI_CORE_AV_REG(0x28C)
-#define HDMI_CORE_AV_CP_BYTE1                   HDMI_CORE_AV_REG(0x37C)
-#define HDMI_CORE_AV_CEC_ADDR_ID                HDMI_CORE_AV_REG(0x3FC)
+
+#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_REG(0xBC)
+#define HDMI_CORE_AV_DPD                        HDMI_REG(0xF4)
+#define HDMI_CORE_AV_PB_CTRL1                   HDMI_REG(0xF8)
+#define HDMI_CORE_AV_PB_CTRL2                   HDMI_REG(0xFC)
+#define HDMI_CORE_AV_AVI_TYPE                   HDMI_REG(0x100)
+#define HDMI_CORE_AV_AVI_VERS                   HDMI_REG(0x104)
+#define HDMI_CORE_AV_AVI_LEN                    HDMI_REG(0x108)
+#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_REG(0x10C)
+#define HDMI_CORE_AV_AVI_DBYTE(n)               HDMI_REG(n * 4 + 0x110)
+#define HDMI_CORE_AV_AVI_DBYTE_NELEMS           HDMI_REG(15)
+#define HDMI_CORE_AV_SPD_DBYTE                  HDMI_REG(0x190)
+#define HDMI_CORE_AV_SPD_DBYTE_NELEMS           HDMI_REG(27)
+#define HDMI_CORE_AV_AUD_DBYTE(n)               HDMI_REG(n * 4 + 0x210)
+#define HDMI_CORE_AV_AUD_DBYTE_NELEMS           HDMI_REG(10)
+#define HDMI_CORE_AV_MPEG_DBYTE                 HDMI_REG(0x290)
+#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS          HDMI_REG(27)
+#define HDMI_CORE_AV_GEN_DBYTE                  HDMI_REG(0x300)
+#define HDMI_CORE_AV_GEN_DBYTE_NELEMS           HDMI_REG(31)
+#define HDMI_CORE_AV_GEN2_DBYTE                 HDMI_REG(0x380)
+#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS          HDMI_REG(31)
+#define HDMI_CORE_AV_ACR_CTRL                   HDMI_REG(0x4)
+#define HDMI_CORE_AV_FREQ_SVAL                  HDMI_REG(0x8)
+#define HDMI_CORE_AV_N_SVAL1                    HDMI_REG(0xC)
+#define HDMI_CORE_AV_N_SVAL2                    HDMI_REG(0x10)
+#define HDMI_CORE_AV_N_SVAL3                    HDMI_REG(0x14)
+#define HDMI_CORE_AV_CTS_SVAL1                  HDMI_REG(0x18)
+#define HDMI_CORE_AV_CTS_SVAL2                  HDMI_REG(0x1C)
+#define HDMI_CORE_AV_CTS_SVAL3                  HDMI_REG(0x20)
+#define HDMI_CORE_AV_CTS_HVAL1                  HDMI_REG(0x24)
+#define HDMI_CORE_AV_CTS_HVAL2                  HDMI_REG(0x28)
+#define HDMI_CORE_AV_CTS_HVAL3                  HDMI_REG(0x2C)
+#define HDMI_CORE_AV_AUD_MODE                   HDMI_REG(0x50)
+#define HDMI_CORE_AV_SPDIF_CTRL                 HDMI_REG(0x54)
+#define HDMI_CORE_AV_HW_SPDIF_FS                HDMI_REG(0x60)
+#define HDMI_CORE_AV_SWAP_I2S                   HDMI_REG(0x64)
+#define HDMI_CORE_AV_SPDIF_ERTH                 HDMI_REG(0x6C)
+#define HDMI_CORE_AV_I2S_IN_MAP                 HDMI_REG(0x70)
+#define HDMI_CORE_AV_I2S_IN_CTRL                HDMI_REG(0x74)
+#define HDMI_CORE_AV_I2S_CHST0                  HDMI_REG(0x78)
+#define HDMI_CORE_AV_I2S_CHST1                  HDMI_REG(0x7C)
+#define HDMI_CORE_AV_I2S_CHST2                  HDMI_REG(0x80)
+#define HDMI_CORE_AV_I2S_CHST4                  HDMI_REG(0x84)
+#define HDMI_CORE_AV_I2S_CHST5                  HDMI_REG(0x88)
+#define HDMI_CORE_AV_ASRC                       HDMI_REG(0x8C)
+#define HDMI_CORE_AV_I2S_IN_LEN                 HDMI_REG(0x90)
+#define HDMI_CORE_AV_HDMI_CTRL                  HDMI_REG(0xBC)
+#define HDMI_CORE_AV_AUDO_TXSTAT                HDMI_REG(0xC0)
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1           HDMI_REG(0xCC)
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2           HDMI_REG(0xD0)
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3           HDMI_REG(0xD4)
+#define HDMI_CORE_AV_TEST_TXCTRL                HDMI_REG(0xF0)
+#define HDMI_CORE_AV_DPD                        HDMI_REG(0xF4)
+#define HDMI_CORE_AV_PB_CTRL1                   HDMI_REG(0xF8)
+#define HDMI_CORE_AV_PB_CTRL2                   HDMI_REG(0xFC)
+#define HDMI_CORE_AV_AVI_TYPE                   HDMI_REG(0x100)
+#define HDMI_CORE_AV_AVI_VERS                   HDMI_REG(0x104)
+#define HDMI_CORE_AV_AVI_LEN                    HDMI_REG(0x108)
+#define HDMI_CORE_AV_AVI_CHSUM                  HDMI_REG(0x10C)
+#define HDMI_CORE_AV_SPD_TYPE                   HDMI_REG(0x180)
+#define HDMI_CORE_AV_SPD_VERS                   HDMI_REG(0x184)
+#define HDMI_CORE_AV_SPD_LEN                    HDMI_REG(0x188)
+#define HDMI_CORE_AV_SPD_CHSUM                  HDMI_REG(0x18C)
+#define HDMI_CORE_AV_AUDIO_TYPE                 HDMI_REG(0x200)
+#define HDMI_CORE_AV_AUDIO_VERS                 HDMI_REG(0x204)
+#define HDMI_CORE_AV_AUDIO_LEN                  HDMI_REG(0x208)
+#define HDMI_CORE_AV_AUDIO_CHSUM                HDMI_REG(0x20C)
+#define HDMI_CORE_AV_MPEG_TYPE                  HDMI_REG(0x280)
+#define HDMI_CORE_AV_MPEG_VERS                  HDMI_REG(0x284)
+#define HDMI_CORE_AV_MPEG_LEN                   HDMI_REG(0x288)
+#define HDMI_CORE_AV_MPEG_CHSUM                 HDMI_REG(0x28C)
+#define HDMI_CORE_AV_CP_BYTE1                   HDMI_REG(0x37C)
+#define HDMI_CORE_AV_CEC_ADDR_ID                HDMI_REG(0x3FC)
 #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE           0x4
 #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE          0x4
 #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE          0x4
 #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE           0x4
 
 /* PLL */
-#define HDMI_PLL_REG(idx)                       HDMI_REG(HDMI_PLLCTRL + idx)
 
-#define PLLCTRL_PLL_CONTROL                     HDMI_PLL_REG(0x0)
-#define PLLCTRL_PLL_STATUS                      HDMI_PLL_REG(0x4)
-#define PLLCTRL_PLL_GO                          HDMI_PLL_REG(0x8)
-#define PLLCTRL_CFG1                            HDMI_PLL_REG(0xC)
-#define PLLCTRL_CFG2                            HDMI_PLL_REG(0x10)
-#define PLLCTRL_CFG3                            HDMI_PLL_REG(0x14)
-#define PLLCTRL_CFG4                            HDMI_PLL_REG(0x20)
+#define PLLCTRL_PLL_CONTROL                     HDMI_REG(0x0)
+#define PLLCTRL_PLL_STATUS                      HDMI_REG(0x4)
+#define PLLCTRL_PLL_GO                          HDMI_REG(0x8)
+#define PLLCTRL_CFG1                            HDMI_REG(0xC)
+#define PLLCTRL_CFG2                            HDMI_REG(0x10)
+#define PLLCTRL_CFG3                            HDMI_REG(0x14)
+#define PLLCTRL_CFG4                            HDMI_REG(0x20)
 
 /* HDMI PHY */
-#define HDMI_PHY_REG(idx)                       HDMI_REG(HDMI_PHY + idx)
 
-#define HDMI_TXPHY_TX_CTRL                      HDMI_PHY_REG(0x0)
-#define HDMI_TXPHY_DIGITAL_CTRL         HDMI_PHY_REG(0x4)
-#define HDMI_TXPHY_POWER_CTRL                   HDMI_PHY_REG(0x8)
-#define HDMI_TXPHY_PAD_CFG_CTRL         HDMI_PHY_REG(0xC)
+#define HDMI_TXPHY_TX_CTRL                      HDMI_REG(0x0)
+#define HDMI_TXPHY_DIGITAL_CTRL                 HDMI_REG(0x4)
+#define HDMI_TXPHY_POWER_CTRL                   HDMI_REG(0x8)
+#define HDMI_TXPHY_PAD_CFG_CTRL                 HDMI_REG(0xC)
 
 /* HDMI EDID Length  */
 #define HDMI_EDID_MAX_LENGTH                    256
@@ -203,10 +192,11 @@ struct hdmi_reg { u16 idx; };
 
 #define OMAP_HDMI_TIMINGS_NB                    34
 
-#define REG_FLD_MOD(idx, val, start, end) \
-        hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end))
-#define REG_GET(idx, start, end) \
-        FLD_GET(hdmi_read_reg(idx), start, end)
+#define REG_FLD_MOD(base, idx, val, start, end) \
+        hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
+                                                        val, start, end))
+#define REG_GET(base, idx, start, end) \
+        FLD_GET(hdmi_read_reg(base, idx), start, end)
 
 /* HDMI timing structure */
 struct hdmi_timings {
@@ -568,6 +558,14 @@ struct hdmi_video_interface {
         int     tm;     /* Timing mode */
 };
 
+struct hdmi_ip_data {
+        void __iomem    *base_wp;       /* HDMI wrapper */
+        unsigned long   core_sys_offset;
+        unsigned long   core_av_offset;
+        unsigned long   pll_offset;
+        unsigned long   phy_offset;
+};
+
 struct hdmi_cm {
         int     code;
         int     mode;