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authorTomi Valkeinen <tomi.valkeinen@ti.com>2011-05-19 07:12:26 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-07-25 03:22:05 -0400
commite6d80f950a77ca48eada6457a290dc5471e1dd73 (patch)
tree79ccbe680e6d777375282e318b3fe19dd40f9c2b /drivers/video/omap2/dss/dispc.c
parentaea4eb9590c6fa36e1b68b9cf5c3e4ddea402812 (diff)
OMAP: DSS2: DISPC: remove finegrained clk enables/disables
dispc.c enables and disables clocks in almost every function to make sure the clocks are enabled when the function is called. This is rather unoptimal way to handle the problem. With pm_runtime other components have to call dispc_runtime_get() to enable dispc clocks before calling any other dispc functions. Thus the finegrained clk enables/disables can be removed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dispc.c')
-rw-r--r--drivers/video/omap2/dss/dispc.c165
1 files changed, 19 insertions, 146 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 5b095a38b20..7c1b7c1e4b6 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -610,8 +610,6 @@ void dispc_go(enum omap_channel channel)
610 int bit; 610 int bit;
611 bool enable_bit, go_bit; 611 bool enable_bit, go_bit;
612 612
613 dispc_runtime_get();
614
615 if (channel == OMAP_DSS_CHANNEL_LCD || 613 if (channel == OMAP_DSS_CHANNEL_LCD ||
616 channel == OMAP_DSS_CHANNEL_LCD2) 614 channel == OMAP_DSS_CHANNEL_LCD2)
617 bit = 0; /* LCDENABLE */ 615 bit = 0; /* LCDENABLE */
@@ -625,7 +623,7 @@ void dispc_go(enum omap_channel channel)
625 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1; 623 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
626 624
627 if (!enable_bit) 625 if (!enable_bit)
628 goto end; 626 return;
629 627
630 if (channel == OMAP_DSS_CHANNEL_LCD || 628 if (channel == OMAP_DSS_CHANNEL_LCD ||
631 channel == OMAP_DSS_CHANNEL_LCD2) 629 channel == OMAP_DSS_CHANNEL_LCD2)
@@ -640,7 +638,7 @@ void dispc_go(enum omap_channel channel)
640 638
641 if (go_bit) { 639 if (go_bit) {
642 DSSERR("GO bit not down for channel %d\n", channel); 640 DSSERR("GO bit not down for channel %d\n", channel);
643 goto end; 641 return;
644 } 642 }
645 643
646 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : 644 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
@@ -650,8 +648,6 @@ void dispc_go(enum omap_channel channel)
650 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit); 648 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
651 else 649 else
652 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit); 650 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
653end:
654 dispc_runtime_put();
655} 651}
656 652
657static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value) 653static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
@@ -1025,7 +1021,7 @@ static void _dispc_set_color_mode(enum omap_plane plane,
1025 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 1021 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
1026} 1022}
1027 1023
1028static void _dispc_set_channel_out(enum omap_plane plane, 1024void dispc_set_channel_out(enum omap_plane plane,
1029 enum omap_channel channel) 1025 enum omap_channel channel)
1030{ 1026{
1031 int shift; 1027 int shift;
@@ -1077,8 +1073,6 @@ static void dispc_set_burst_size(enum omap_plane plane,
1077{ 1073{
1078 int shift; 1074 int shift;
1079 1075
1080 dispc_runtime_get();
1081
1082 switch (plane) { 1076 switch (plane) {
1083 case OMAP_DSS_GFX: 1077 case OMAP_DSS_GFX:
1084 shift = 6; 1078 shift = 6;
@@ -1093,8 +1087,6 @@ static void dispc_set_burst_size(enum omap_plane plane,
1093 } 1087 }
1094 1088
1095 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); 1089 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1096
1097 dispc_runtime_put();
1098} 1090}
1099 1091
1100static void dispc_configure_burst_sizes(void) 1092static void dispc_configure_burst_sizes(void)
@@ -1182,9 +1174,7 @@ void dispc_enable_replication(enum omap_plane plane, bool enable)
1182 else 1174 else
1183 bit = 10; 1175 bit = 10;
1184 1176
1185 dispc_runtime_get();
1186 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); 1177 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1187 dispc_runtime_put();
1188} 1178}
1189 1179
1190void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height) 1180void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
@@ -1192,9 +1182,7 @@ void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1192 u32 val; 1182 u32 val;
1193 BUG_ON((width > (1 << 11)) || (height > (1 << 11))); 1183 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1194 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 1184 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1195 dispc_runtime_get();
1196 dispc_write_reg(DISPC_SIZE_MGR(channel), val); 1185 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1197 dispc_runtime_put();
1198} 1186}
1199 1187
1200void dispc_set_digit_size(u16 width, u16 height) 1188void dispc_set_digit_size(u16 width, u16 height)
@@ -1202,9 +1190,7 @@ void dispc_set_digit_size(u16 width, u16 height)
1202 u32 val; 1190 u32 val;
1203 BUG_ON((width > (1 << 11)) || (height > (1 << 11))); 1191 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1204 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 1192 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1205 dispc_runtime_get();
1206 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val); 1193 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1207 dispc_runtime_put();
1208} 1194}
1209 1195
1210static void dispc_read_plane_fifo_sizes(void) 1196static void dispc_read_plane_fifo_sizes(void)
@@ -1216,8 +1202,6 @@ static void dispc_read_plane_fifo_sizes(void)
1216 1202
1217 unit = dss_feat_get_buffer_size_unit(); 1203 unit = dss_feat_get_buffer_size_unit();
1218 1204
1219 dispc_runtime_get();
1220
1221 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); 1205 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1222 1206
1223 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) { 1207 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
@@ -1225,8 +1209,6 @@ static void dispc_read_plane_fifo_sizes(void)
1225 size *= unit; 1209 size *= unit;
1226 dispc.fifo_size[plane] = size; 1210 dispc.fifo_size[plane] = size;
1227 } 1211 }
1228
1229 dispc_runtime_put();
1230} 1212}
1231 1213
1232u32 dispc_get_plane_fifo_size(enum omap_plane plane) 1214u32 dispc_get_plane_fifo_size(enum omap_plane plane)
@@ -1250,8 +1232,6 @@ void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1250 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); 1232 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1251 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); 1233 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1252 1234
1253 dispc_runtime_get();
1254
1255 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n", 1235 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1256 plane, 1236 plane,
1257 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1237 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
@@ -1263,18 +1243,12 @@ void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1263 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), 1243 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1264 FLD_VAL(high, hi_start, hi_end) | 1244 FLD_VAL(high, hi_start, hi_end) |
1265 FLD_VAL(low, lo_start, lo_end)); 1245 FLD_VAL(low, lo_start, lo_end));
1266
1267 dispc_runtime_put();
1268} 1246}
1269 1247
1270void dispc_enable_fifomerge(bool enable) 1248void dispc_enable_fifomerge(bool enable)
1271{ 1249{
1272 dispc_runtime_get();
1273
1274 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); 1250 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1275 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1251 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1276
1277 dispc_runtime_put();
1278} 1252}
1279 1253
1280static void _dispc_set_fir(enum omap_plane plane, 1254static void _dispc_set_fir(enum omap_plane plane,
@@ -1894,14 +1868,7 @@ static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1894 return dispc_pclk_rate(channel) * vf * hf; 1868 return dispc_pclk_rate(channel) * vf * hf;
1895} 1869}
1896 1870
1897void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out) 1871int dispc_setup_plane(enum omap_plane plane,
1898{
1899 dispc_runtime_get();
1900 _dispc_set_channel_out(plane, channel_out);
1901 dispc_runtime_put();
1902}
1903
1904static int _dispc_setup_plane(enum omap_plane plane,
1905 u32 paddr, u16 screen_width, 1872 u32 paddr, u16 screen_width,
1906 u16 pos_x, u16 pos_y, 1873 u16 pos_x, u16 pos_y,
1907 u16 width, u16 height, 1874 u16 width, u16 height,
@@ -1909,7 +1876,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
1909 enum omap_color_mode color_mode, 1876 enum omap_color_mode color_mode,
1910 bool ilace, 1877 bool ilace,
1911 enum omap_dss_rotation_type rotation_type, 1878 enum omap_dss_rotation_type rotation_type,
1912 u8 rotation, int mirror, 1879 u8 rotation, bool mirror,
1913 u8 global_alpha, u8 pre_mult_alpha, 1880 u8 global_alpha, u8 pre_mult_alpha,
1914 enum omap_channel channel, u32 puv_addr) 1881 enum omap_channel channel, u32 puv_addr)
1915{ 1882{
@@ -1923,6 +1890,14 @@ static int _dispc_setup_plane(enum omap_plane plane,
1923 u16 frame_height = height; 1890 u16 frame_height = height;
1924 unsigned int field_offset = 0; 1891 unsigned int field_offset = 0;
1925 1892
1893 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
1894 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
1895 plane, paddr, screen_width, pos_x, pos_y,
1896 width, height,
1897 out_width, out_height,
1898 ilace, color_mode,
1899 rotation, mirror, channel);
1900
1926 if (paddr == 0) 1901 if (paddr == 0)
1927 return -EINVAL; 1902 return -EINVAL;
1928 1903
@@ -2068,9 +2043,13 @@ static int _dispc_setup_plane(enum omap_plane plane,
2068 return 0; 2043 return 0;
2069} 2044}
2070 2045
2071static void _dispc_enable_plane(enum omap_plane plane, bool enable) 2046int dispc_enable_plane(enum omap_plane plane, bool enable)
2072{ 2047{
2048 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2049
2073 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); 2050 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2051
2052 return 0;
2074} 2053}
2075 2054
2076static void dispc_disable_isr(void *data, u32 mask) 2055static void dispc_disable_isr(void *data, u32 mask)
@@ -2094,8 +2073,6 @@ static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
2094 int r; 2073 int r;
2095 u32 irq; 2074 u32 irq;
2096 2075
2097 dispc_runtime_get();
2098
2099 /* When we disable LCD output, we need to wait until frame is done. 2076 /* When we disable LCD output, we need to wait until frame is done.
2100 * Otherwise the DSS is still working, and turning off the clocks 2077 * Otherwise the DSS is still working, and turning off the clocks
2101 * prevents DSS from going to OFF mode */ 2078 * prevents DSS from going to OFF mode */
@@ -2129,8 +2106,6 @@ static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
2129 if (r) 2106 if (r)
2130 DSSERR("failed to unregister FRAMEDONE isr\n"); 2107 DSSERR("failed to unregister FRAMEDONE isr\n");
2131 } 2108 }
2132
2133 dispc_runtime_put();
2134} 2109}
2135 2110
2136static void _enable_digit_out(bool enable) 2111static void _enable_digit_out(bool enable)
@@ -2143,12 +2118,8 @@ static void dispc_enable_digit_out(bool enable)
2143 struct completion frame_done_completion; 2118 struct completion frame_done_completion;
2144 int r; 2119 int r;
2145 2120
2146 dispc_runtime_get(); 2121 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2147
2148 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
2149 dispc_runtime_put();
2150 return; 2122 return;
2151 }
2152 2123
2153 if (enable) { 2124 if (enable) {
2154 unsigned long flags; 2125 unsigned long flags;
@@ -2200,8 +2171,6 @@ static void dispc_enable_digit_out(bool enable)
2200 _omap_dispc_set_irqs(); 2171 _omap_dispc_set_irqs();
2201 spin_unlock_irqrestore(&dispc.irq_lock, flags); 2172 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2202 } 2173 }
2203
2204 dispc_runtime_put();
2205} 2174}
2206 2175
2207bool dispc_is_channel_enabled(enum omap_channel channel) 2176bool dispc_is_channel_enabled(enum omap_channel channel)
@@ -2232,9 +2201,7 @@ void dispc_lcd_enable_signal_polarity(bool act_high)
2232 if (!dss_has_feature(FEAT_LCDENABLEPOL)) 2201 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2233 return; 2202 return;
2234 2203
2235 dispc_runtime_get();
2236 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); 2204 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2237 dispc_runtime_put();
2238} 2205}
2239 2206
2240void dispc_lcd_enable_signal(bool enable) 2207void dispc_lcd_enable_signal(bool enable)
@@ -2242,9 +2209,7 @@ void dispc_lcd_enable_signal(bool enable)
2242 if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) 2209 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2243 return; 2210 return;
2244 2211
2245 dispc_runtime_get();
2246 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); 2212 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2247 dispc_runtime_put();
2248} 2213}
2249 2214
2250void dispc_pck_free_enable(bool enable) 2215void dispc_pck_free_enable(bool enable)
@@ -2252,19 +2217,15 @@ void dispc_pck_free_enable(bool enable)
2252 if (!dss_has_feature(FEAT_PCKFREEENABLE)) 2217 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2253 return; 2218 return;
2254 2219
2255 dispc_runtime_get();
2256 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); 2220 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2257 dispc_runtime_put();
2258} 2221}
2259 2222
2260void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable) 2223void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
2261{ 2224{
2262 dispc_runtime_get();
2263 if (channel == OMAP_DSS_CHANNEL_LCD2) 2225 if (channel == OMAP_DSS_CHANNEL_LCD2)
2264 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16); 2226 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2265 else 2227 else
2266 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16); 2228 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2267 dispc_runtime_put();
2268} 2229}
2269 2230
2270 2231
@@ -2287,27 +2248,21 @@ void dispc_set_lcd_display_type(enum omap_channel channel,
2287 return; 2248 return;
2288 } 2249 }
2289 2250
2290 dispc_runtime_get();
2291 if (channel == OMAP_DSS_CHANNEL_LCD2) 2251 if (channel == OMAP_DSS_CHANNEL_LCD2)
2292 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3); 2252 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2293 else 2253 else
2294 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3); 2254 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2295 dispc_runtime_put();
2296} 2255}
2297 2256
2298void dispc_set_loadmode(enum omap_dss_load_mode mode) 2257void dispc_set_loadmode(enum omap_dss_load_mode mode)
2299{ 2258{
2300 dispc_runtime_get();
2301 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); 2259 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2302 dispc_runtime_put();
2303} 2260}
2304 2261
2305 2262
2306void dispc_set_default_color(enum omap_channel channel, u32 color) 2263void dispc_set_default_color(enum omap_channel channel, u32 color)
2307{ 2264{
2308 dispc_runtime_get();
2309 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); 2265 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2310 dispc_runtime_put();
2311} 2266}
2312 2267
2313u32 dispc_get_default_color(enum omap_channel channel) 2268u32 dispc_get_default_color(enum omap_channel channel)
@@ -2318,9 +2273,7 @@ u32 dispc_get_default_color(enum omap_channel channel)
2318 channel != OMAP_DSS_CHANNEL_LCD && 2273 channel != OMAP_DSS_CHANNEL_LCD &&
2319 channel != OMAP_DSS_CHANNEL_LCD2); 2274 channel != OMAP_DSS_CHANNEL_LCD2);
2320 2275
2321 dispc_runtime_get();
2322 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel)); 2276 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2323 dispc_runtime_put();
2324 2277
2325 return l; 2278 return l;
2326} 2279}
@@ -2329,7 +2282,6 @@ void dispc_set_trans_key(enum omap_channel ch,
2329 enum omap_dss_trans_key_type type, 2282 enum omap_dss_trans_key_type type,
2330 u32 trans_key) 2283 u32 trans_key)
2331{ 2284{
2332 dispc_runtime_get();
2333 if (ch == OMAP_DSS_CHANNEL_LCD) 2285 if (ch == OMAP_DSS_CHANNEL_LCD)
2334 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11); 2286 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2335 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2287 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
@@ -2338,14 +2290,12 @@ void dispc_set_trans_key(enum omap_channel ch,
2338 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11); 2290 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2339 2291
2340 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); 2292 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2341 dispc_runtime_put();
2342} 2293}
2343 2294
2344void dispc_get_trans_key(enum omap_channel ch, 2295void dispc_get_trans_key(enum omap_channel ch,
2345 enum omap_dss_trans_key_type *type, 2296 enum omap_dss_trans_key_type *type,
2346 u32 *trans_key) 2297 u32 *trans_key)
2347{ 2298{
2348 dispc_runtime_get();
2349 if (type) { 2299 if (type) {
2350 if (ch == OMAP_DSS_CHANNEL_LCD) 2300 if (ch == OMAP_DSS_CHANNEL_LCD)
2351 *type = REG_GET(DISPC_CONFIG, 11, 11); 2301 *type = REG_GET(DISPC_CONFIG, 11, 11);
@@ -2359,33 +2309,28 @@ void dispc_get_trans_key(enum omap_channel ch,
2359 2309
2360 if (trans_key) 2310 if (trans_key)
2361 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch)); 2311 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2362 dispc_runtime_put();
2363} 2312}
2364 2313
2365void dispc_enable_trans_key(enum omap_channel ch, bool enable) 2314void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2366{ 2315{
2367 dispc_runtime_get();
2368 if (ch == OMAP_DSS_CHANNEL_LCD) 2316 if (ch == OMAP_DSS_CHANNEL_LCD)
2369 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10); 2317 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2370 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2318 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2371 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12); 2319 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2372 else /* OMAP_DSS_CHANNEL_LCD2 */ 2320 else /* OMAP_DSS_CHANNEL_LCD2 */
2373 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10); 2321 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2374 dispc_runtime_put();
2375} 2322}
2376void dispc_enable_alpha_blending(enum omap_channel ch, bool enable) 2323void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2377{ 2324{
2378 if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) 2325 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2379 return; 2326 return;
2380 2327
2381 dispc_runtime_get();
2382 if (ch == OMAP_DSS_CHANNEL_LCD) 2328 if (ch == OMAP_DSS_CHANNEL_LCD)
2383 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); 2329 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2384 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2330 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2385 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); 2331 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2386 else /* OMAP_DSS_CHANNEL_LCD2 */ 2332 else /* OMAP_DSS_CHANNEL_LCD2 */
2387 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18); 2333 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2388 dispc_runtime_put();
2389} 2334}
2390bool dispc_alpha_blending_enabled(enum omap_channel ch) 2335bool dispc_alpha_blending_enabled(enum omap_channel ch)
2391{ 2336{
@@ -2394,7 +2339,6 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
2394 if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) 2339 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2395 return false; 2340 return false;
2396 2341
2397 dispc_runtime_get();
2398 if (ch == OMAP_DSS_CHANNEL_LCD) 2342 if (ch == OMAP_DSS_CHANNEL_LCD)
2399 enabled = REG_GET(DISPC_CONFIG, 18, 18); 2343 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2400 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2344 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
@@ -2403,7 +2347,6 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
2403 enabled = REG_GET(DISPC_CONFIG2, 18, 18); 2347 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2404 else 2348 else
2405 BUG(); 2349 BUG();
2406 dispc_runtime_put();
2407 2350
2408 return enabled; 2351 return enabled;
2409} 2352}
@@ -2413,7 +2356,6 @@ bool dispc_trans_key_enabled(enum omap_channel ch)
2413{ 2356{
2414 bool enabled; 2357 bool enabled;
2415 2358
2416 dispc_runtime_get();
2417 if (ch == OMAP_DSS_CHANNEL_LCD) 2359 if (ch == OMAP_DSS_CHANNEL_LCD)
2418 enabled = REG_GET(DISPC_CONFIG, 10, 10); 2360 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2419 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2361 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
@@ -2422,7 +2364,6 @@ bool dispc_trans_key_enabled(enum omap_channel ch)
2422 enabled = REG_GET(DISPC_CONFIG2, 10, 10); 2364 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2423 else 2365 else
2424 BUG(); 2366 BUG();
2425 dispc_runtime_put();
2426 2367
2427 return enabled; 2368 return enabled;
2428} 2369}
@@ -2450,12 +2391,10 @@ void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2450 return; 2391 return;
2451 } 2392 }
2452 2393
2453 dispc_runtime_get();
2454 if (channel == OMAP_DSS_CHANNEL_LCD2) 2394 if (channel == OMAP_DSS_CHANNEL_LCD2)
2455 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8); 2395 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2456 else 2396 else
2457 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8); 2397 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2458 dispc_runtime_put();
2459} 2398}
2460 2399
2461void dispc_set_parallel_interface_mode(enum omap_channel channel, 2400void dispc_set_parallel_interface_mode(enum omap_channel channel,
@@ -2487,8 +2426,6 @@ void dispc_set_parallel_interface_mode(enum omap_channel channel,
2487 return; 2426 return;
2488 } 2427 }
2489 2428
2490 dispc_runtime_get();
2491
2492 if (channel == OMAP_DSS_CHANNEL_LCD2) { 2429 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2493 l = dispc_read_reg(DISPC_CONTROL2); 2430 l = dispc_read_reg(DISPC_CONTROL2);
2494 l = FLD_MOD(l, stallmode, 11, 11); 2431 l = FLD_MOD(l, stallmode, 11, 11);
@@ -2500,8 +2437,6 @@ void dispc_set_parallel_interface_mode(enum omap_channel channel,
2500 l = FLD_MOD(l, gpout1, 16, 16); 2437 l = FLD_MOD(l, gpout1, 16, 16);
2501 dispc_write_reg(DISPC_CONTROL, l); 2438 dispc_write_reg(DISPC_CONTROL, l);
2502 } 2439 }
2503
2504 dispc_runtime_put();
2505} 2440}
2506 2441
2507static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, 2442static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
@@ -2554,10 +2489,8 @@ static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2554 FLD_VAL(vbp, 31, 20); 2489 FLD_VAL(vbp, 31, 20);
2555 } 2490 }
2556 2491
2557 dispc_runtime_get();
2558 dispc_write_reg(DISPC_TIMING_H(channel), timing_h); 2492 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2559 dispc_write_reg(DISPC_TIMING_V(channel), timing_v); 2493 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2560 dispc_runtime_put();
2561} 2494}
2562 2495
2563/* change name to mode? */ 2496/* change name to mode? */
@@ -2600,10 +2533,8 @@ static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2600 BUG_ON(lck_div < 1); 2533 BUG_ON(lck_div < 1);
2601 BUG_ON(pck_div < 2); 2534 BUG_ON(pck_div < 2);
2602 2535
2603 dispc_runtime_get();
2604 dispc_write_reg(DISPC_DIVISORo(channel), 2536 dispc_write_reg(DISPC_DIVISORo(channel),
2605 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); 2537 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2606 dispc_runtime_put();
2607} 2538}
2608 2539
2609static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div, 2540static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
@@ -3063,9 +2994,7 @@ static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
3063 l |= FLD_VAL(acbi, 11, 8); 2994 l |= FLD_VAL(acbi, 11, 8);
3064 l |= FLD_VAL(acb, 7, 0); 2995 l |= FLD_VAL(acb, 7, 0);
3065 2996
3066 dispc_runtime_get();
3067 dispc_write_reg(DISPC_POL_FREQ(channel), l); 2997 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3068 dispc_runtime_put();
3069} 2998}
3070 2999
3071void dispc_set_pol_freq(enum omap_channel channel, 3000void dispc_set_pol_freq(enum omap_channel channel,
@@ -3186,15 +3115,11 @@ static void _omap_dispc_set_irqs(void)
3186 mask |= isr_data->mask; 3115 mask |= isr_data->mask;
3187 } 3116 }
3188 3117
3189 dispc_runtime_get();
3190
3191 old_mask = dispc_read_reg(DISPC_IRQENABLE); 3118 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3192 /* clear the irqstatus for newly enabled irqs */ 3119 /* clear the irqstatus for newly enabled irqs */
3193 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask); 3120 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3194 3121
3195 dispc_write_reg(DISPC_IRQENABLE, mask); 3122 dispc_write_reg(DISPC_IRQENABLE, mask);
3196
3197 dispc_runtime_put();
3198} 3123}
3199 3124
3200int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) 3125int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
@@ -3730,58 +3655,6 @@ static void _omap_dispc_initial_config(void)
3730 dispc_configure_burst_sizes(); 3655 dispc_configure_burst_sizes();
3731} 3656}
3732 3657
3733int dispc_enable_plane(enum omap_plane plane, bool enable)
3734{
3735 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3736
3737 dispc_runtime_get();
3738 _dispc_enable_plane(plane, enable);
3739 dispc_runtime_put();
3740
3741 return 0;
3742}
3743
3744int dispc_setup_plane(enum omap_plane plane,
3745 u32 paddr, u16 screen_width,
3746 u16 pos_x, u16 pos_y,
3747 u16 width, u16 height,
3748 u16 out_width, u16 out_height,
3749 enum omap_color_mode color_mode,
3750 bool ilace,
3751 enum omap_dss_rotation_type rotation_type,
3752 u8 rotation, bool mirror, u8 global_alpha,
3753 u8 pre_mult_alpha, enum omap_channel channel,
3754 u32 puv_addr)
3755{
3756 int r = 0;
3757
3758 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d, %d, %dx%d -> "
3759 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
3760 plane, paddr, screen_width, pos_x, pos_y,
3761 width, height,
3762 out_width, out_height,
3763 ilace, color_mode,
3764 rotation, mirror, channel);
3765
3766 dispc_runtime_get();
3767
3768 r = _dispc_setup_plane(plane,
3769 paddr, screen_width,
3770 pos_x, pos_y,
3771 width, height,
3772 out_width, out_height,
3773 color_mode, ilace,
3774 rotation_type,
3775 rotation, mirror,
3776 global_alpha,
3777 pre_mult_alpha,
3778 channel, puv_addr);
3779
3780 dispc_runtime_put();
3781
3782 return r;
3783}
3784
3785/* DISPC HW IP initialisation */ 3658/* DISPC HW IP initialisation */
3786static int omap_dispchw_probe(struct platform_device *pdev) 3659static int omap_dispchw_probe(struct platform_device *pdev)
3787{ 3660{