diff options
author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-11-15 04:18:12 -0500 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-12-02 01:54:35 -0500 |
commit | dbce0160af31d2ea323656c201d8debf5af789bf (patch) | |
tree | ca30677b8dfbdccca1c6a72d54e2c9bde3c2ccda /drivers/video/omap2/dss/apply.c | |
parent | 07e327c9c18b382656bf455051759be8182627ae (diff) |
OMAPDSS: APPLY: separate vsync isr register/unregister
Create separate functions for the vsync isr register/unregister code for
cleaner code.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/apply.c')
-rw-r--r-- | drivers/video/omap2/dss/apply.c | 61 |
1 files changed, 37 insertions, 24 deletions
diff --git a/drivers/video/omap2/dss/apply.c b/drivers/video/omap2/dss/apply.c index 34879d0628b..dfce82e11a3 100644 --- a/drivers/video/omap2/dss/apply.c +++ b/drivers/video/omap2/dss/apply.c | |||
@@ -417,6 +417,40 @@ void dss_mgr_start_update(struct omap_overlay_manager *mgr) | |||
417 | dispc_mgr_enable(mgr->id, true); | 417 | dispc_mgr_enable(mgr->id, true); |
418 | } | 418 | } |
419 | 419 | ||
420 | static void dss_apply_irq_handler(void *data, u32 mask); | ||
421 | |||
422 | static void dss_register_vsync_isr(void) | ||
423 | { | ||
424 | u32 mask; | ||
425 | int r; | ||
426 | |||
427 | mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD | | ||
428 | DISPC_IRQ_EVSYNC_EVEN; | ||
429 | if (dss_has_feature(FEAT_MGR_LCD2)) | ||
430 | mask |= DISPC_IRQ_VSYNC2; | ||
431 | |||
432 | r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask); | ||
433 | WARN_ON(r); | ||
434 | |||
435 | dss_cache.irq_enabled = true; | ||
436 | } | ||
437 | |||
438 | static void dss_unregister_vsync_isr(void) | ||
439 | { | ||
440 | u32 mask; | ||
441 | int r; | ||
442 | |||
443 | mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD | | ||
444 | DISPC_IRQ_EVSYNC_EVEN; | ||
445 | if (dss_has_feature(FEAT_MGR_LCD2)) | ||
446 | mask |= DISPC_IRQ_VSYNC2; | ||
447 | |||
448 | r = omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, mask); | ||
449 | WARN_ON(r); | ||
450 | |||
451 | dss_cache.irq_enabled = false; | ||
452 | } | ||
453 | |||
420 | static void dss_apply_irq_handler(void *data, u32 mask) | 454 | static void dss_apply_irq_handler(void *data, u32 mask) |
421 | { | 455 | { |
422 | struct manager_cache_data *mc; | 456 | struct manager_cache_data *mc; |
@@ -425,7 +459,6 @@ static void dss_apply_irq_handler(void *data, u32 mask) | |||
425 | const int num_mgrs = dss_feat_get_num_mgrs(); | 459 | const int num_mgrs = dss_feat_get_num_mgrs(); |
426 | int i, r; | 460 | int i, r; |
427 | bool mgr_busy[MAX_DSS_MANAGERS]; | 461 | bool mgr_busy[MAX_DSS_MANAGERS]; |
428 | u32 irq_mask; | ||
429 | 462 | ||
430 | for (i = 0; i < num_mgrs; i++) | 463 | for (i = 0; i < num_mgrs; i++) |
431 | mgr_busy[i] = dispc_mgr_go_busy(i); | 464 | mgr_busy[i] = dispc_mgr_go_busy(i); |
@@ -459,13 +492,7 @@ static void dss_apply_irq_handler(void *data, u32 mask) | |||
459 | goto end; | 492 | goto end; |
460 | } | 493 | } |
461 | 494 | ||
462 | irq_mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD | | 495 | dss_unregister_vsync_isr(); |
463 | DISPC_IRQ_EVSYNC_EVEN; | ||
464 | if (dss_has_feature(FEAT_MGR_LCD2)) | ||
465 | irq_mask |= DISPC_IRQ_VSYNC2; | ||
466 | |||
467 | omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, irq_mask); | ||
468 | dss_cache.irq_enabled = false; | ||
469 | 496 | ||
470 | end: | 497 | end: |
471 | spin_unlock(&dss_cache.lock); | 498 | spin_unlock(&dss_cache.lock); |
@@ -605,22 +632,8 @@ int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) | |||
605 | 632 | ||
606 | r = 0; | 633 | r = 0; |
607 | if (mgr->enabled && !mgr_manual_update(mgr)) { | 634 | if (mgr->enabled && !mgr_manual_update(mgr)) { |
608 | if (!dss_cache.irq_enabled) { | 635 | if (!dss_cache.irq_enabled) |
609 | u32 mask; | 636 | dss_register_vsync_isr(); |
610 | |||
611 | mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD | | ||
612 | DISPC_IRQ_EVSYNC_EVEN; | ||
613 | if (dss_has_feature(FEAT_MGR_LCD2)) | ||
614 | mask |= DISPC_IRQ_VSYNC2; | ||
615 | |||
616 | r = omap_dispc_register_isr(dss_apply_irq_handler, | ||
617 | NULL, mask); | ||
618 | |||
619 | if (r) | ||
620 | DSSERR("failed to register apply isr\n"); | ||
621 | |||
622 | dss_cache.irq_enabled = true; | ||
623 | } | ||
624 | 637 | ||
625 | configure_dispc(); | 638 | configure_dispc(); |
626 | } | 639 | } |