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authorFelipe Balbi <balbi@ti.com>2011-08-19 11:10:58 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-08-22 19:03:11 -0400
commit72246da40f3719af3bfd104a2365b32537c27d83 (patch)
treedb6a4b139c24340e0d5dccab8d9df0b23ab509ef /drivers/usb
parent500fdf8becb9c8d51970c7ac6a4fa308a5481ebe (diff)
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/Kconfig2
-rw-r--r--drivers/usb/Makefile2
-rw-r--r--drivers/usb/dwc3/Kconfig25
-rw-r--r--drivers/usb/dwc3/Makefile36
-rw-r--r--drivers/usb/dwc3/core.c467
-rw-r--r--drivers/usb/dwc3/core.h709
-rw-r--r--drivers/usb/dwc3/debug.h51
-rw-r--r--drivers/usb/dwc3/debugfs.c534
-rw-r--r--drivers/usb/dwc3/dwc3-omap.c410
-rw-r--r--drivers/usb/dwc3/dwc3-pci.c219
-rw-r--r--drivers/usb/dwc3/ep0.c782
-rw-r--r--drivers/usb/dwc3/gadget.c2063
-rw-r--r--drivers/usb/dwc3/gadget.h292
-rw-r--r--drivers/usb/dwc3/io.h55
-rw-r--r--drivers/usb/gadget/Kconfig12
15 files changed, 5659 insertions, 0 deletions
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 7e7f42baa93..2651852952b 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -111,6 +111,8 @@ config USB
111 111
112source "drivers/usb/core/Kconfig" 112source "drivers/usb/core/Kconfig"
113 113
114source "drivers/usb/dwc3/Kconfig"
115
114source "drivers/usb/mon/Kconfig" 116source "drivers/usb/mon/Kconfig"
115 117
116source "drivers/usb/wusbcore/Kconfig" 118source "drivers/usb/wusbcore/Kconfig"
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 30ddf8dc4f7..969b0a50bc9 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -6,6 +6,8 @@
6 6
7obj-$(CONFIG_USB) += core/ 7obj-$(CONFIG_USB) += core/
8 8
9obj-$(CONFIG_USB_DWC3) += dwc3/
10
9obj-$(CONFIG_USB_MON) += mon/ 11obj-$(CONFIG_USB_MON) += mon/
10 12
11obj-$(CONFIG_PCI) += host/ 13obj-$(CONFIG_PCI) += host/
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
new file mode 100644
index 00000000000..3c1d67d324f
--- /dev/null
+++ b/drivers/usb/dwc3/Kconfig
@@ -0,0 +1,25 @@
1config USB_DWC3
2 tristate "DesignWare USB3 DRD Core Support"
3 depends on (USB || USB_GADGET)
4 select USB_OTG_UTILS
5 help
6 Say Y or M here if your system has a Dual Role SuperSpeed
7 USB controller based on the DesignWare USB3 IP Core.
8
9 If you choose to build this driver is a dynamically linked
10 module, the module will be called dwc3.ko.
11
12if USB_DWC3
13
14config USB_DWC3_DEBUG
15 bool "Enable Debugging Messages"
16 help
17 Say Y here to enable debugging messages on DWC3 Driver.
18
19config USB_DWC3_VERBOSE
20 bool "Enable Verbose Debugging Messages"
21 depends on USB_DWC3_DEBUG
22 help
23 Say Y here to enable verbose debugging messages on DWC3 Driver.
24
25endif
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
new file mode 100644
index 00000000000..593d1dbc465
--- /dev/null
+++ b/drivers/usb/dwc3/Makefile
@@ -0,0 +1,36 @@
1ccflags-$(CONFIG_USB_DWC3_DEBUG) := -DDEBUG
2ccflags-$(CONFIG_USB_DWC3_VERBOSE) += -DVERBOSE_DEBUG
3
4obj-$(CONFIG_USB_DWC3) += dwc3.o
5
6dwc3-y := core.o
7
8ifneq ($(CONFIG_USB_GADGET_DWC3),)
9 dwc3-y += gadget.o ep0.o
10endif
11
12ifneq ($(CONFIG_DEBUG_FS),)
13 dwc3-y += debugfs.o
14endif
15
16##
17# Platform-specific glue layers go here
18#
19# NOTICE: Make sure your glue layer doesn't depend on anything
20# which is arch-specific and that it compiles on all situations.
21#
22# We want to keep this requirement in order to be able to compile
23# the entire driver (with all its glue layers) on several architectures
24# and make sure it compiles fine. This will also help with allmodconfig
25# and allyesconfig builds.
26#
27# The only exception is the PCI glue layer, but that's only because
28# PCI doesn't provide nops if CONFIG_PCI isn't enabled.
29##
30
31obj-$(CONFIG_USB_DWC3) += dwc3-omap.o
32
33ifneq ($(CONFIG_PCI),)
34 obj-$(CONFIG_USB_DWC3) += dwc3-pci.o
35endif
36
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
new file mode 100644
index 00000000000..443e4fb9b8f
--- /dev/null
+++ b/drivers/usb/dwc3/core.c
@@ -0,0 +1,467 @@
1/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/ioport.h>
47#include <linux/io.h>
48#include <linux/list.h>
49#include <linux/delay.h>
50#include <linux/dma-mapping.h>
51
52#include <linux/usb/ch9.h>
53#include <linux/usb/gadget.h>
54
55#include "core.h"
56#include "gadget.h"
57#include "io.h"
58
59#include "debug.h"
60
61/**
62 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
63 * @dwc: pointer to our context structure
64 */
65static void dwc3_core_soft_reset(struct dwc3 *dwc)
66{
67 u32 reg;
68
69 /* Before Resetting PHY, put Core in Reset */
70 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
71 reg |= DWC3_GCTL_CORESOFTRESET;
72 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
73
74 /* Assert USB3 PHY reset */
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
76 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
78
79 /* Assert USB2 PHY reset */
80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
81 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
83
84 mdelay(100);
85
86 /* Clear USB3 PHY reset */
87 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
88 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
89 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
90
91 /* Clear USB2 PHY reset */
92 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
93 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
94 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
95
96 /* After PHYs are stable we can take Core out of reset state */
97 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
98 reg &= ~DWC3_GCTL_CORESOFTRESET;
99 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
100}
101
102/**
103 * dwc3_free_one_event_buffer - Frees one event buffer
104 * @dwc: Pointer to our controller context structure
105 * @evt: Pointer to event buffer to be freed
106 */
107static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
108 struct dwc3_event_buffer *evt)
109{
110 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
111 kfree(evt);
112}
113
114/**
115 * dwc3_alloc_one_event_buffer - Allocated one event buffer structure
116 * @dwc: Pointer to our controller context structure
117 * @length: size of the event buffer
118 *
119 * Returns a pointer to the allocated event buffer structure on succes
120 * otherwise ERR_PTR(errno).
121 */
122static struct dwc3_event_buffer *__devinit
123dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
124{
125 struct dwc3_event_buffer *evt;
126
127 evt = kzalloc(sizeof(*evt), GFP_KERNEL);
128 if (!evt)
129 return ERR_PTR(-ENOMEM);
130
131 evt->dwc = dwc;
132 evt->length = length;
133 evt->buf = dma_alloc_coherent(dwc->dev, length,
134 &evt->dma, GFP_KERNEL);
135 if (!evt->buf) {
136 kfree(evt);
137 return ERR_PTR(-ENOMEM);
138 }
139
140 return evt;
141}
142
143/**
144 * dwc3_free_event_buffers - frees all allocated event buffers
145 * @dwc: Pointer to our controller context structure
146 */
147static void dwc3_free_event_buffers(struct dwc3 *dwc)
148{
149 struct dwc3_event_buffer *evt;
150 int i;
151
152 for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
153 evt = dwc->ev_buffs[i];
154 if (evt) {
155 dwc3_free_one_event_buffer(dwc, evt);
156 dwc->ev_buffs[i] = NULL;
157 }
158 }
159}
160
161/**
162 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
163 * @dwc: Pointer to out controller context structure
164 * @num: number of event buffers to allocate
165 * @length: size of event buffer
166 *
167 * Returns 0 on success otherwise negative errno. In error the case, dwc
168 * may contain some buffers allocated but not all which were requested.
169 */
170static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned num,
171 unsigned length)
172{
173 int i;
174
175 for (i = 0; i < num; i++) {
176 struct dwc3_event_buffer *evt;
177
178 evt = dwc3_alloc_one_event_buffer(dwc, length);
179 if (IS_ERR(evt)) {
180 dev_err(dwc->dev, "can't allocate event buffer\n");
181 return PTR_ERR(evt);
182 }
183 dwc->ev_buffs[i] = evt;
184 }
185
186 return 0;
187}
188
189/**
190 * dwc3_event_buffers_setup - setup our allocated event buffers
191 * @dwc: Pointer to out controller context structure
192 *
193 * Returns 0 on success otherwise negative errno.
194 */
195static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
196{
197 struct dwc3_event_buffer *evt;
198 int n;
199
200 for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
201 evt = dwc->ev_buffs[n];
202 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
203 evt->buf, (unsigned long long) evt->dma,
204 evt->length);
205
206 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
207 lower_32_bits(evt->dma));
208 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
209 upper_32_bits(evt->dma));
210 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
211 evt->length & 0xffff);
212 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
213 }
214
215 return 0;
216}
217
218static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
219{
220 struct dwc3_event_buffer *evt;
221 int n;
222
223 for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
224 evt = dwc->ev_buffs[n];
225 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
226 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
227 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
228 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
229 }
230}
231
232/**
233 * dwc3_core_init - Low-level initialization of DWC3 Core
234 * @dwc: Pointer to our controller context structure
235 *
236 * Returns 0 on success otherwise negative errno.
237 */
238static int __devinit dwc3_core_init(struct dwc3 *dwc)
239{
240 unsigned long timeout;
241 u32 reg;
242 int ret;
243
244 dwc3_core_soft_reset(dwc);
245
246 /* issue device SoftReset too */
247 timeout = jiffies + msecs_to_jiffies(500);
248 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
249 do {
250 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
251 if (!(reg & DWC3_DCTL_CSFTRST))
252 break;
253
254 if (time_after(jiffies, timeout)) {
255 dev_err(dwc->dev, "Reset Timed Out\n");
256 ret = -ETIMEDOUT;
257 goto err0;
258 }
259
260 cpu_relax();
261 } while (true);
262
263 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
264 /* This should read as U3 followed by revision number */
265 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
266 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
267 ret = -ENODEV;
268 goto err0;
269 }
270
271 dwc->revision = reg & DWC3_GSNPSREV_MASK;
272
273 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_NUM,
274 DWC3_EVENT_BUFFERS_SIZE);
275 if (ret) {
276 dev_err(dwc->dev, "failed to allocate event buffers\n");
277 ret = -ENOMEM;
278 goto err1;
279 }
280
281 ret = dwc3_event_buffers_setup(dwc);
282 if (ret) {
283 dev_err(dwc->dev, "failed to setup event buffers\n");
284 goto err1;
285 }
286
287 return 0;
288
289err1:
290 dwc3_free_event_buffers(dwc);
291
292err0:
293 return ret;
294}
295
296static void dwc3_core_exit(struct dwc3 *dwc)
297{
298 dwc3_event_buffers_cleanup(dwc);
299 dwc3_free_event_buffers(dwc);
300}
301
302#define DWC3_ALIGN_MASK (16 - 1)
303
304static int __devinit dwc3_probe(struct platform_device *pdev)
305{
306 const struct platform_device_id *id = platform_get_device_id(pdev);
307 struct resource *res;
308 struct dwc3 *dwc;
309 void __iomem *regs;
310 unsigned int features = id->driver_data;
311 int ret = -ENOMEM;
312 int irq;
313 void *mem;
314
315 mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
316 if (!mem) {
317 dev_err(&pdev->dev, "not enough memory\n");
318 goto err0;
319 }
320 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
321 dwc->mem = mem;
322
323 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
324 if (!res) {
325 dev_err(&pdev->dev, "missing resource\n");
326 goto err1;
327 }
328
329 res = request_mem_region(res->start, resource_size(res),
330 dev_name(&pdev->dev));
331 if (!res) {
332 dev_err(&pdev->dev, "can't request mem region\n");
333 goto err1;
334 }
335
336 regs = ioremap(res->start, resource_size(res));
337 if (!regs) {
338 dev_err(&pdev->dev, "ioremap failed\n");
339 goto err2;
340 }
341
342 irq = platform_get_irq(pdev, 0);
343 if (irq < 0) {
344 dev_err(&pdev->dev, "missing IRQ\n");
345 goto err3;
346 }
347
348 spin_lock_init(&dwc->lock);
349 platform_set_drvdata(pdev, dwc);
350
351 dwc->regs = regs;
352 dwc->regs_size = resource_size(res);
353 dwc->dev = &pdev->dev;
354 dwc->irq = irq;
355
356 pm_runtime_enable(&pdev->dev);
357 pm_runtime_get_sync(&pdev->dev);
358 pm_runtime_forbid(&pdev->dev);
359
360 ret = dwc3_core_init(dwc);
361 if (ret) {
362 dev_err(&pdev->dev, "failed to initialize core\n");
363 goto err3;
364 }
365
366 if (features & DWC3_HAS_PERIPHERAL) {
367 ret = dwc3_gadget_init(dwc);
368 if (ret) {
369 dev_err(&pdev->dev, "failed to initialized gadget\n");
370 goto err4;
371 }
372 }
373
374 ret = dwc3_debugfs_init(dwc);
375 if (ret) {
376 dev_err(&pdev->dev, "failed to initialize debugfs\n");
377 goto err5;
378 }
379
380 pm_runtime_allow(&pdev->dev);
381
382 return 0;
383
384err5:
385 if (features & DWC3_HAS_PERIPHERAL)
386 dwc3_gadget_exit(dwc);
387
388err4:
389 dwc3_core_exit(dwc);
390
391err3:
392 iounmap(regs);
393
394err2:
395 release_mem_region(res->start, resource_size(res));
396
397err1:
398 kfree(dwc->mem);
399
400err0:
401 return ret;
402}
403
404static int __devexit dwc3_remove(struct platform_device *pdev)
405{
406 const struct platform_device_id *id = platform_get_device_id(pdev);
407 struct dwc3 *dwc = platform_get_drvdata(pdev);
408 struct resource *res;
409 unsigned int features = id->driver_data;
410
411 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
412
413 pm_runtime_put(&pdev->dev);
414 pm_runtime_disable(&pdev->dev);
415
416 dwc3_debugfs_exit(dwc);
417
418 if (features & DWC3_HAS_PERIPHERAL)
419 dwc3_gadget_exit(dwc);
420
421 dwc3_core_exit(dwc);
422 release_mem_region(res->start, resource_size(res));
423 iounmap(dwc->regs);
424 kfree(dwc->mem);
425
426 return 0;
427}
428
429static const struct platform_device_id dwc3_id_table[] __devinitconst = {
430 {
431 .name = "dwc3-omap",
432 .driver_data = (DWC3_HAS_PERIPHERAL
433 | DWC3_HAS_XHCI
434 | DWC3_HAS_OTG),
435 },
436 {
437 .name = "dwc3-pci",
438 .driver_data = DWC3_HAS_PERIPHERAL,
439 },
440 { }, /* Terminating Entry */
441};
442MODULE_DEVICE_TABLE(platform, dwc3_id_table);
443
444static struct platform_driver dwc3_driver = {
445 .probe = dwc3_probe,
446 .remove = __devexit_p(dwc3_remove),
447 .driver = {
448 .name = "dwc3",
449 },
450 .id_table = dwc3_id_table,
451};
452
453MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
454MODULE_LICENSE("Dual BSD/GPL");
455MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
456
457static int __devinit dwc3_init(void)
458{
459 return platform_driver_register(&dwc3_driver);
460}
461module_init(dwc3_init);
462
463static void __exit dwc3_exit(void)
464{
465 platform_driver_unregister(&dwc3_driver);
466}
467module_exit(dwc3_exit);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
new file mode 100644
index 00000000000..83b2960cccd
--- /dev/null
+++ b/drivers/usb/dwc3/core.h
@@ -0,0 +1,709 @@
1/**
2 * core.h - DesignWare USB3 DRD Core Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#ifndef __DRIVERS_USB_DWC3_CORE_H
41#define __DRIVERS_USB_DWC3_CORE_H
42
43#include <linux/device.h>
44#include <linux/spinlock.h>
45#include <linux/list.h>
46#include <linux/dma-mapping.h>
47#include <linux/mm.h>
48#include <linux/debugfs.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53/* Global constants */
54#define DWC3_ENDPOINTS_NUM 32
55
56#define DWC3_EVENT_BUFFERS_NUM 2
57#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
58#define DWC3_EVENT_TYPE_MASK 0xfe
59
60#define DWC3_EVENT_TYPE_DEV 0
61#define DWC3_EVENT_TYPE_CARKIT 3
62#define DWC3_EVENT_TYPE_I2C 4
63
64#define DWC3_DEVICE_EVENT_DISCONNECT 0
65#define DWC3_DEVICE_EVENT_RESET 1
66#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
67#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
68#define DWC3_DEVICE_EVENT_WAKEUP 4
69#define DWC3_DEVICE_EVENT_EOPF 6
70#define DWC3_DEVICE_EVENT_SOF 7
71#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
72#define DWC3_DEVICE_EVENT_CMD_CMPL 10
73#define DWC3_DEVICE_EVENT_OVERFLOW 11
74
75#define DWC3_GEVNTCOUNT_MASK 0xfffc
76#define DWC3_GSNPSID_MASK 0xffff0000
77#define DWC3_GSNPSREV_MASK 0xffff
78
79/* Global Registers */
80#define DWC3_GSBUSCFG0 0xc100
81#define DWC3_GSBUSCFG1 0xc104
82#define DWC3_GTXTHRCFG 0xc108
83#define DWC3_GRXTHRCFG 0xc10c
84#define DWC3_GCTL 0xc110
85#define DWC3_GEVTEN 0xc114
86#define DWC3_GSTS 0xc118
87#define DWC3_GSNPSID 0xc120
88#define DWC3_GGPIO 0xc124
89#define DWC3_GUID 0xc128
90#define DWC3_GUCTL 0xc12c
91#define DWC3_GBUSERRADDR0 0xc130
92#define DWC3_GBUSERRADDR1 0xc134
93#define DWC3_GPRTBIMAP0 0xc138
94#define DWC3_GPRTBIMAP1 0xc13c
95#define DWC3_GHWPARAMS0 0xc140
96#define DWC3_GHWPARAMS1 0xc144
97#define DWC3_GHWPARAMS2 0xc148
98#define DWC3_GHWPARAMS3 0xc14c
99#define DWC3_GHWPARAMS4 0xc150
100#define DWC3_GHWPARAMS5 0xc154
101#define DWC3_GHWPARAMS6 0xc158
102#define DWC3_GHWPARAMS7 0xc15c
103#define DWC3_GDBGFIFOSPACE 0xc160
104#define DWC3_GDBGLTSSM 0xc164
105#define DWC3_GPRTBIMAP_HS0 0xc180
106#define DWC3_GPRTBIMAP_HS1 0xc184
107#define DWC3_GPRTBIMAP_FS0 0xc188
108#define DWC3_GPRTBIMAP_FS1 0xc18c
109
110#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
111#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
112
113#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
114
115#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
116
117#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
118#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
119
120#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
121#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
122#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
123#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
124
125#define DWC3_GHWPARAMS8 0xc600
126
127/* Device Registers */
128#define DWC3_DCFG 0xc700
129#define DWC3_DCTL 0xc704
130#define DWC3_DEVTEN 0xc708
131#define DWC3_DSTS 0xc70c
132#define DWC3_DGCMDPAR 0xc710
133#define DWC3_DGCMD 0xc714
134#define DWC3_DALEPENA 0xc720
135#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
136#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
137#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
138#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
139
140/* OTG Registers */
141#define DWC3_OCFG 0xcc00
142#define DWC3_OCTL 0xcc04
143#define DWC3_OEVTEN 0xcc08
144#define DWC3_OSTS 0xcc0C
145
146/* Bit fields */
147
148/* Global Configuration Register */
149#define DWC3_GCTL_PWRDNSCALE(n) (n << 19)
150#define DWC3_GCTL_U2RSTECN 16
151#define DWC3_GCTL_RAMCLKSEL(x) ((x & DWC3_GCTL_CLK_MASK) << 6)
152#define DWC3_GCTL_CLK_BUS (0)
153#define DWC3_GCTL_CLK_PIPE (1)
154#define DWC3_GCTL_CLK_PIPEHALF (2)
155#define DWC3_GCTL_CLK_MASK (3)
156
157#define DWC3_GCTL_PRTCAPDIR(n) (n << 12)
158#define DWC3_GCTL_PRTCAP_HOST 1
159#define DWC3_GCTL_PRTCAP_DEVICE 2
160#define DWC3_GCTL_PRTCAP_OTG 3
161
162#define DWC3_GCTL_CORESOFTRESET (1 << 11)
163#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
164
165/* Global USB2 PHY Configuration Register */
166#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
167#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
168
169/* Global USB3 PIPE Control Register */
170#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
171#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
172
173/* Device Configuration Register */
174#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
175#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
176
177#define DWC3_DCFG_SPEED_MASK (7 << 0)
178#define DWC3_DCFG_SUPERSPEED (4 << 0)
179#define DWC3_DCFG_HIGHSPEED (0 << 0)
180#define DWC3_DCFG_FULLSPEED2 (1 << 0)
181#define DWC3_DCFG_LOWSPEED (2 << 0)
182#define DWC3_DCFG_FULLSPEED1 (3 << 0)
183
184/* Device Control Register */
185#define DWC3_DCTL_RUN_STOP (1 << 31)
186#define DWC3_DCTL_CSFTRST (1 << 30)
187#define DWC3_DCTL_LSFTRST (1 << 29)
188
189#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
190#define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24)
191
192#define DWC3_DCTL_APPL1RES (1 << 23)
193
194#define DWC3_DCTL_INITU2ENA (1 << 12)
195#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
196#define DWC3_DCTL_INITU1ENA (1 << 10)
197#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
198#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
199
200#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
201#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
202
203#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
204#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
205#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
206#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
207#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
208#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
209#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
210
211/* Device Event Enable Register */
212#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
213#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
214#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
215#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
216#define DWC3_DEVTEN_SOFEN (1 << 7)
217#define DWC3_DEVTEN_EOPFEN (1 << 6)
218#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
219#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
220#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
221#define DWC3_DEVTEN_USBRSTEN (1 << 1)
222#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
223
224/* Device Status Register */
225#define DWC3_DSTS_PWRUPREQ (1 << 24)
226#define DWC3_DSTS_COREIDLE (1 << 23)
227#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
228
229#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
230#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
231
232#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
233
234#define DWC3_DSTS_SOFFN_MASK (0x3ff << 3)
235#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
236
237#define DWC3_DSTS_CONNECTSPD (7 << 0)
238
239#define DWC3_DSTS_SUPERSPEED (4 << 0)
240#define DWC3_DSTS_HIGHSPEED (0 << 0)
241#define DWC3_DSTS_FULLSPEED2 (1 << 0)
242#define DWC3_DSTS_LOWSPEED (2 << 0)
243#define DWC3_DSTS_FULLSPEED1 (3 << 0)
244
245/* Device Generic Command Register */
246#define DWC3_DGCMD_SET_LMP 0x01
247#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
248#define DWC3_DGCMD_XMIT_FUNCTION 0x03
249#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
250#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
251#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
252#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
253
254/* Device Endpoint Command Register */
255#define DWC3_DEPCMD_PARAM_SHIFT 16
256#define DWC3_DEPCMD_PARAM(x) (x << DWC3_DEPCMD_PARAM_SHIFT)
257#define DWC3_DEPCMD_GET_RSC_IDX(x) ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
258#define DWC3_DEPCMD_STATUS_MASK (0x0f << 12)
259#define DWC3_DEPCMD_STATUS(x) ((x & DWC3_DEPCMD_STATUS_MASK) >> 12)
260#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
261#define DWC3_DEPCMD_CMDACT (1 << 10)
262#define DWC3_DEPCMD_CMDIOC (1 << 8)
263
264#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
265#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
266#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
267#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
268#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
269#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
270#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
271#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
272#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
273
274/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
275#define DWC3_DALEPENA_EP(n) (1 << n)
276
277#define DWC3_DEPCMD_TYPE_CONTROL 0
278#define DWC3_DEPCMD_TYPE_ISOC 1
279#define DWC3_DEPCMD_TYPE_BULK 2
280#define DWC3_DEPCMD_TYPE_INTR 3
281
282/* Structures */
283
284struct dwc3_trb_hw;
285
286/**
287 * struct dwc3_event_buffer - Software event buffer representation
288 * @list: a list of event buffers
289 * @buf: _THE_ buffer
290 * @length: size of this buffer
291 * @dma: dma_addr_t
292 * @dwc: pointer to DWC controller
293 */
294struct dwc3_event_buffer {
295 void *buf;
296 unsigned length;
297 unsigned int lpos;
298
299 dma_addr_t dma;
300
301 struct dwc3 *dwc;
302};
303
304#define DWC3_EP_FLAG_STALLED (1 << 0)
305#define DWC3_EP_FLAG_WEDGED (1 << 1)
306
307#define DWC3_EP_DIRECTION_TX true
308#define DWC3_EP_DIRECTION_RX false
309
310#define DWC3_TRB_NUM 32
311#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
312
313/**
314 * struct dwc3_ep - device side endpoint representation
315 * @endpoint: usb endpoint
316 * @request_list: list of requests for this endpoint
317 * @req_queued: list of requests on this ep which have TRBs setup
318 * @trb_pool: array of transaction buffers
319 * @trb_pool_dma: dma address of @trb_pool
320 * @free_slot: next slot which is going to be used
321 * @busy_slot: first slot which is owned by HW
322 * @desc: usb_endpoint_descriptor pointer
323 * @dwc: pointer to DWC controller
324 * @flags: endpoint flags (wedged, stalled, ...)
325 * @current_trb: index of current used trb
326 * @number: endpoint number (1 - 15)
327 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
328 * @res_trans_idx: Resource transfer index
329 * @interval: the intervall on which the ISOC transfer is started
330 * @name: a human readable name e.g. ep1out-bulk
331 * @direction: true for TX, false for RX
332 */
333struct dwc3_ep {
334 struct usb_ep endpoint;
335 struct list_head request_list;
336 struct list_head req_queued;
337
338 struct dwc3_trb_hw *trb_pool;
339 dma_addr_t trb_pool_dma;
340 u32 free_slot;
341 u32 busy_slot;
342 const struct usb_endpoint_descriptor *desc;
343 struct dwc3 *dwc;
344
345 unsigned flags;
346#define DWC3_EP_ENABLED (1 << 0)
347#define DWC3_EP_STALL (1 << 1)
348#define DWC3_EP_WEDGE (1 << 2)
349#define DWC3_EP_BUSY (1 << 4)
350#define DWC3_EP_PENDING_REQUEST (1 << 5)
351#define DWC3_EP_WILL_SHUTDOWN (1 << 6)
352
353 unsigned current_trb;
354
355 u8 number;
356 u8 type;
357 u8 res_trans_idx;
358 u32 interval;
359
360 char name[20];
361
362 unsigned direction:1;
363};
364
365enum dwc3_phy {
366 DWC3_PHY_UNKNOWN = 0,
367 DWC3_PHY_USB3,
368 DWC3_PHY_USB2,
369};
370
371enum dwc3_ep0_state {
372 EP0_UNCONNECTED = 0,
373 EP0_IDLE,
374 EP0_IN_DATA_PHASE,
375 EP0_OUT_DATA_PHASE,
376 EP0_IN_WAIT_GADGET,
377 EP0_OUT_WAIT_GADGET,
378 EP0_IN_WAIT_NRDY,
379 EP0_OUT_WAIT_NRDY,
380 EP0_IN_STATUS_PHASE,
381 EP0_OUT_STATUS_PHASE,
382 EP0_STALL,
383};
384
385enum dwc3_link_state {
386 /* In SuperSpeed */
387 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
388 DWC3_LINK_STATE_U1 = 0x01,
389 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
390 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
391 DWC3_LINK_STATE_SS_DIS = 0x04,
392 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
393 DWC3_LINK_STATE_SS_INACT = 0x06,
394 DWC3_LINK_STATE_POLL = 0x07,
395 DWC3_LINK_STATE_RECOV = 0x08,
396 DWC3_LINK_STATE_HRESET = 0x09,
397 DWC3_LINK_STATE_CMPLY = 0x0a,
398 DWC3_LINK_STATE_LPBK = 0x0b,
399 DWC3_LINK_STATE_MASK = 0x0f,
400};
401
402enum dwc3_device_state {
403 DWC3_DEFAULT_STATE,
404 DWC3_ADDRESS_STATE,
405 DWC3_CONFIGURED_STATE,
406};
407
408/**
409 * struct dwc3_trb - transfer request block
410 * @bpl: lower 32bit of the buffer
411 * @bph: higher 32bit of the buffer
412 * @length: buffer size (up to 16mb - 1)
413 * @pcm1: packet count m1
414 * @trbsts: trb status
415 * 0 = ok
416 * 1 = missed isoc
417 * 2 = setup pending
418 * @hwo: hardware owner of descriptor
419 * @lst: last trb
420 * @chn: chain buffers
421 * @csp: continue on short packets (only supported on isoc eps)
422 * @trbctl: trb control
423 * 1 = normal
424 * 2 = control-setup
425 * 3 = control-status-2
426 * 4 = control-status-3
427 * 5 = control-data (first trb of data stage)
428 * 6 = isochronous-first (first trb of service interval)
429 * 7 = isochronous
430 * 8 = link trb
431 * others = reserved
432 * @isp_imi: interrupt on short packet / interrupt on missed isoc
433 * @ioc: interrupt on complete
434 * @sid_sofn: Stream ID / SOF Number
435 */
436struct dwc3_trb {
437 u64 bplh;
438
439 union {
440 struct {
441 u32 length:24;
442 u32 pcm1:2;
443 u32 reserved27_26:2;
444 u32 trbsts:4;
445#define DWC3_TRB_STS_OKAY 0
446#define DWC3_TRB_STS_MISSED_ISOC 1
447#define DWC3_TRB_STS_SETUP_PENDING 2
448 };
449 u32 len_pcm;
450 };
451
452 union {
453 struct {
454 u32 hwo:1;
455 u32 lst:1;
456 u32 chn:1;
457 u32 csp:1;
458 u32 trbctl:6;
459 u32 isp_imi:1;
460 u32 ioc:1;
461 u32 reserved13_12:2;
462 u32 sid_sofn:16;
463 u32 reserved31_30:2;
464 };
465 u32 control;
466 };
467} __packed;
468
469/**
470 * struct dwc3_trb_hw - transfer request block (hw format)
471 * @bpl: DW0-3
472 * @bph: DW4-7
473 * @size: DW8-B
474 * @trl: DWC-F
475 */
476struct dwc3_trb_hw {
477 __le32 bpl;
478 __le32 bph;
479 __le32 size;
480 __le32 ctrl;
481} __packed;
482
483static inline void dwc3_trb_to_hw(struct dwc3_trb *nat, struct dwc3_trb_hw *hw)
484{
485 hw->bpl = cpu_to_le32(lower_32_bits(nat->bplh));
486 hw->bph = cpu_to_le32(upper_32_bits(nat->bplh));
487 hw->size = cpu_to_le32p(&nat->len_pcm);
488 /* HWO is written last */
489 hw->ctrl = cpu_to_le32p(&nat->control);
490}
491
492static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat)
493{
494 u64 bplh;
495
496 bplh = le32_to_cpup(&hw->bpl);
497 bplh |= (u64) le32_to_cpup(&hw->bph) << 32;
498 nat->bplh = bplh;
499
500 nat->len_pcm = le32_to_cpup(&hw->size);
501 nat->control = le32_to_cpup(&hw->ctrl);
502}
503
504/**
505 * struct dwc3 - representation of our controller
506 * ctrl_req: usb control request which is used for ep0
507 * ep0_trb: trb which is used for the ctrl_req
508 * setup_buf: used while precessing STD USB requests
509 * ctrl_req_addr: dma address of ctrl_req
510 * ep0_trb: dma address of ep0_trb
511 * ep0_usb_req: dummy req used while handling STD USB requests
512 * setup_buf_addr: dma address of setup_buf
513 * @lock: for synchronizing
514 * @dev: pointer to our struct device
515 * @event_buffer_list: a list of event buffers
516 * @gadget: device side representation of the peripheral controller
517 * @gadget_driver: pointer to the gadget driver
518 * @regs: base address for our registers
519 * @regs_size: address space size
520 * @irq: IRQ number
521 * @revision: revision register contents
522 * @is_selfpowered: true when we are selfpowered
523 * @three_stage_setup: set if we perform a three phase setup
524 * @ep0_status_pending: ep0 status response without a req is pending
525 * @ep0state: state of endpoint zero
526 * @link_state: link state
527 * @speed: device speed (super, high, full, low)
528 * @mem: points to start of memory which is used for this struct.
529 * @root: debugfs root folder pointer
530 */
531struct dwc3 {
532 struct usb_ctrlrequest *ctrl_req;
533 struct dwc3_trb_hw *ep0_trb;
534 u8 *setup_buf;
535 dma_addr_t ctrl_req_addr;
536 dma_addr_t ep0_trb_addr;
537 dma_addr_t setup_buf_addr;
538 struct usb_request ep0_usb_req;
539 /* device lock */
540 spinlock_t lock;
541 struct device *dev;
542
543 struct dwc3_event_buffer *ev_buffs[DWC3_EVENT_BUFFERS_NUM];
544 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
545
546 struct usb_gadget gadget;
547 struct usb_gadget_driver *gadget_driver;
548
549 void __iomem *regs;
550 size_t regs_size;
551
552 int irq;
553
554 u32 revision;
555
556#define DWC3_REVISION_173A 0x5533173a
557#define DWC3_REVISION_175A 0x5533175a
558#define DWC3_REVISION_180A 0x5533180a
559#define DWC3_REVISION_183A 0x5533183a
560#define DWC3_REVISION_185A 0x5533185a
561#define DWC3_REVISION_188A 0x5533188a
562#define DWC3_REVISION_190A 0x5533190a
563
564 unsigned is_selfpowered:1;
565 unsigned three_stage_setup:1;
566 unsigned ep0_status_pending:1;
567
568 enum dwc3_ep0_state ep0state;
569 enum dwc3_link_state link_state;
570 enum dwc3_device_state dev_state;
571
572 u8 speed;
573 void *mem;
574
575 struct dentry *root;
576};
577
578/* -------------------------------------------------------------------------- */
579
580#define DWC3_TRBSTS_OK 0
581#define DWC3_TRBSTS_MISSED_ISOC 1
582#define DWC3_TRBSTS_SETUP_PENDING 2
583
584#define DWC3_TRBCTL_NORMAL 1
585#define DWC3_TRBCTL_CONTROL_SETUP 2
586#define DWC3_TRBCTL_CONTROL_STATUS2 3
587#define DWC3_TRBCTL_CONTROL_STATUS3 4
588#define DWC3_TRBCTL_CONTROL_DATA 5
589#define DWC3_TRBCTL_ISOCHRONOUS_FIRST 6
590#define DWC3_TRBCTL_ISOCHRONOUS 7
591#define DWC3_TRBCTL_LINK_TRB 8
592
593/* -------------------------------------------------------------------------- */
594
595struct dwc3_event_type {
596 u32 is_devspec:1;
597 u32 type:6;
598 u32 reserved8_31:25;
599} __packed;
600
601#define DWC3_DEPEVT_XFERCOMPLETE 0x01
602#define DWC3_DEPEVT_XFERINPROGRESS 0x02
603#define DWC3_DEPEVT_XFERNOTREADY 0x03
604#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
605#define DWC3_DEPEVT_STREAMEVT 0x06
606#define DWC3_DEPEVT_EPCMDCMPLT 0x07
607
608/**
609 * struct dwc3_event_depvt - Device Endpoint Events
610 * @one_bit: indicates this is an endpoint event (not used)
611 * @endpoint_number: number of the endpoint
612 * @endpoint_event: The event we have:
613 * 0x00 - Reserved
614 * 0x01 - XferComplete
615 * 0x02 - XferInProgress
616 * 0x03 - XferNotReady
617 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
618 * 0x05 - Reserved
619 * 0x06 - StreamEvt
620 * 0x07 - EPCmdCmplt
621 * @reserved11_10: Reserved, don't use.
622 * @status: Indicates the status of the event. Refer to databook for
623 * more information.
624 * @parameters: Parameters of the current event. Refer to databook for
625 * more information.
626 */
627struct dwc3_event_depevt {
628 u32 one_bit:1;
629 u32 endpoint_number:5;
630 u32 endpoint_event:4;
631 u32 reserved11_10:2;
632 u32 status:4;
633#define DEPEVT_STATUS_BUSERR (1 << 0)
634#define DEPEVT_STATUS_SHORT (1 << 1)
635#define DEPEVT_STATUS_IOC (1 << 2)
636#define DEPEVT_STATUS_LST (1 << 3)
637 u32 parameters:16;
638} __packed;
639
640/**
641 * struct dwc3_event_devt - Device Events
642 * @one_bit: indicates this is a non-endpoint event (not used)
643 * @device_event: indicates it's a device event. Should read as 0x00
644 * @type: indicates the type of device event.
645 * 0 - DisconnEvt
646 * 1 - USBRst
647 * 2 - ConnectDone
648 * 3 - ULStChng
649 * 4 - WkUpEvt
650 * 5 - Reserved
651 * 6 - EOPF
652 * 7 - SOF
653 * 8 - Reserved
654 * 9 - ErrticErr
655 * 10 - CmdCmplt
656 * 11 - EvntOverflow
657 * 12 - VndrDevTstRcved
658 * @reserved15_12: Reserved, not used
659 * @event_info: Information about this event
660 * @reserved31_24: Reserved, not used
661 */
662struct dwc3_event_devt {
663 u32 one_bit:1;
664 u32 device_event:7;
665 u32 type:4;
666 u32 reserved15_12:4;
667 u32 event_info:8;
668 u32 reserved31_24:8;
669} __packed;
670
671/**
672 * struct dwc3_event_gevt - Other Core Events
673 * @one_bit: indicates this is a non-endpoint event (not used)
674 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
675 * @phy_port_number: self-explanatory
676 * @reserved31_12: Reserved, not used.
677 */
678struct dwc3_event_gevt {
679 u32 one_bit:1;
680 u32 device_event:7;
681 u32 phy_port_number:4;
682 u32 reserved31_12:20;
683} __packed;
684
685/**
686 * union dwc3_event - representation of Event Buffer contents
687 * @raw: raw 32-bit event
688 * @type: the type of the event
689 * @depevt: Device Endpoint Event
690 * @devt: Device Event
691 * @gevt: Global Event
692 */
693union dwc3_event {
694 u32 raw;
695 struct dwc3_event_type type;
696 struct dwc3_event_depevt depevt;
697 struct dwc3_event_devt devt;
698 struct dwc3_event_gevt gevt;
699};
700
701/*
702 * DWC3 Features to be used as Driver Data
703 */
704
705#define DWC3_HAS_PERIPHERAL BIT(0)
706#define DWC3_HAS_XHCI BIT(1)
707#define DWC3_HAS_OTG BIT(3)
708
709#endif /* __DRIVERS_USB_DWC3_CORE_H */
diff --git a/drivers/usb/dwc3/debug.h b/drivers/usb/dwc3/debug.h
new file mode 100644
index 00000000000..ee3ba734676
--- /dev/null
+++ b/drivers/usb/dwc3/debug.h
@@ -0,0 +1,51 @@
1/**
2 * debug.h - DesignWare USB3 DRD Controller Debug Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#include "core.h"
41
42#ifdef CONFIG_DEBUG_FS
43extern int dwc3_debugfs_init(struct dwc3 *);
44extern void dwc3_debugfs_exit(struct dwc3 *);
45#else
46static inline int dwc3_debugfs_init(struct dwc3 *d)
47{ return 0; }
48static inline void dwc3_debugfs_exit(struct dwc3 *d)
49{ }
50#endif
51
diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c
new file mode 100644
index 00000000000..432df539372
--- /dev/null
+++ b/drivers/usb/dwc3/debugfs.c
@@ -0,0 +1,534 @@
1/**
2 * debugfs.c - DesignWare USB3 DRD Controller DebugFS file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/ptrace.h>
43#include <linux/types.h>
44#include <linux/spinlock.h>
45#include <linux/debugfs.h>
46#include <linux/seq_file.h>
47#include <linux/delay.h>
48
49#include <asm/uaccess.h>
50
51#include "core.h"
52#include "gadget.h"
53#include "io.h"
54
55struct dwc3_register {
56 const char *name;
57 u32 offset;
58};
59
60#define dump_register(nm) \
61{ \
62 .name = __stringify(nm), \
63 .offset = DWC3_ ##nm, \
64}
65
66static const struct dwc3_register dwc3_regs[] = {
67 dump_register(GSBUSCFG0),
68 dump_register(GSBUSCFG1),
69 dump_register(GTXTHRCFG),
70 dump_register(GRXTHRCFG),
71 dump_register(GCTL),
72 dump_register(GEVTEN),
73 dump_register(GSTS),
74 dump_register(GSNPSID),
75 dump_register(GGPIO),
76 dump_register(GUID),
77 dump_register(GUCTL),
78 dump_register(GBUSERRADDR0),
79 dump_register(GBUSERRADDR1),
80 dump_register(GPRTBIMAP0),
81 dump_register(GPRTBIMAP1),
82 dump_register(GHWPARAMS0),
83 dump_register(GHWPARAMS1),
84 dump_register(GHWPARAMS2),
85 dump_register(GHWPARAMS3),
86 dump_register(GHWPARAMS4),
87 dump_register(GHWPARAMS5),
88 dump_register(GHWPARAMS6),
89 dump_register(GHWPARAMS7),
90 dump_register(GDBGFIFOSPACE),
91 dump_register(GDBGLTSSM),
92 dump_register(GPRTBIMAP_HS0),
93 dump_register(GPRTBIMAP_HS1),
94 dump_register(GPRTBIMAP_FS0),
95 dump_register(GPRTBIMAP_FS1),
96
97 dump_register(GUSB2PHYCFG(0)),
98 dump_register(GUSB2PHYCFG(1)),
99 dump_register(GUSB2PHYCFG(2)),
100 dump_register(GUSB2PHYCFG(3)),
101 dump_register(GUSB2PHYCFG(4)),
102 dump_register(GUSB2PHYCFG(5)),
103 dump_register(GUSB2PHYCFG(6)),
104 dump_register(GUSB2PHYCFG(7)),
105 dump_register(GUSB2PHYCFG(8)),
106 dump_register(GUSB2PHYCFG(9)),
107 dump_register(GUSB2PHYCFG(10)),
108 dump_register(GUSB2PHYCFG(11)),
109 dump_register(GUSB2PHYCFG(12)),
110 dump_register(GUSB2PHYCFG(13)),
111 dump_register(GUSB2PHYCFG(14)),
112 dump_register(GUSB2PHYCFG(15)),
113
114 dump_register(GUSB2I2CCTL(0)),
115 dump_register(GUSB2I2CCTL(1)),
116 dump_register(GUSB2I2CCTL(2)),
117 dump_register(GUSB2I2CCTL(3)),
118 dump_register(GUSB2I2CCTL(4)),
119 dump_register(GUSB2I2CCTL(5)),
120 dump_register(GUSB2I2CCTL(6)),
121 dump_register(GUSB2I2CCTL(7)),
122 dump_register(GUSB2I2CCTL(8)),
123 dump_register(GUSB2I2CCTL(9)),
124 dump_register(GUSB2I2CCTL(10)),
125 dump_register(GUSB2I2CCTL(11)),
126 dump_register(GUSB2I2CCTL(12)),
127 dump_register(GUSB2I2CCTL(13)),
128 dump_register(GUSB2I2CCTL(14)),
129 dump_register(GUSB2I2CCTL(15)),
130
131 dump_register(GUSB2PHYACC(0)),
132 dump_register(GUSB2PHYACC(1)),
133 dump_register(GUSB2PHYACC(2)),
134 dump_register(GUSB2PHYACC(3)),
135 dump_register(GUSB2PHYACC(4)),
136 dump_register(GUSB2PHYACC(5)),
137 dump_register(GUSB2PHYACC(6)),
138 dump_register(GUSB2PHYACC(7)),
139 dump_register(GUSB2PHYACC(8)),
140 dump_register(GUSB2PHYACC(9)),
141 dump_register(GUSB2PHYACC(10)),
142 dump_register(GUSB2PHYACC(11)),
143 dump_register(GUSB2PHYACC(12)),
144 dump_register(GUSB2PHYACC(13)),
145 dump_register(GUSB2PHYACC(14)),
146 dump_register(GUSB2PHYACC(15)),
147
148 dump_register(GUSB3PIPECTL(0)),
149 dump_register(GUSB3PIPECTL(1)),
150 dump_register(GUSB3PIPECTL(2)),
151 dump_register(GUSB3PIPECTL(3)),
152 dump_register(GUSB3PIPECTL(4)),
153 dump_register(GUSB3PIPECTL(5)),
154 dump_register(GUSB3PIPECTL(6)),
155 dump_register(GUSB3PIPECTL(7)),
156 dump_register(GUSB3PIPECTL(8)),
157 dump_register(GUSB3PIPECTL(9)),
158 dump_register(GUSB3PIPECTL(10)),
159 dump_register(GUSB3PIPECTL(11)),
160 dump_register(GUSB3PIPECTL(12)),
161 dump_register(GUSB3PIPECTL(13)),
162 dump_register(GUSB3PIPECTL(14)),
163 dump_register(GUSB3PIPECTL(15)),
164
165 dump_register(GTXFIFOSIZ(0)),
166 dump_register(GTXFIFOSIZ(1)),
167 dump_register(GTXFIFOSIZ(2)),
168 dump_register(GTXFIFOSIZ(3)),
169 dump_register(GTXFIFOSIZ(4)),
170 dump_register(GTXFIFOSIZ(5)),
171 dump_register(GTXFIFOSIZ(6)),
172 dump_register(GTXFIFOSIZ(7)),
173 dump_register(GTXFIFOSIZ(8)),
174 dump_register(GTXFIFOSIZ(9)),
175 dump_register(GTXFIFOSIZ(10)),
176 dump_register(GTXFIFOSIZ(11)),
177 dump_register(GTXFIFOSIZ(12)),
178 dump_register(GTXFIFOSIZ(13)),
179 dump_register(GTXFIFOSIZ(14)),
180 dump_register(GTXFIFOSIZ(15)),
181 dump_register(GTXFIFOSIZ(16)),
182 dump_register(GTXFIFOSIZ(17)),
183 dump_register(GTXFIFOSIZ(18)),
184 dump_register(GTXFIFOSIZ(19)),
185 dump_register(GTXFIFOSIZ(20)),
186 dump_register(GTXFIFOSIZ(21)),
187 dump_register(GTXFIFOSIZ(22)),
188 dump_register(GTXFIFOSIZ(23)),
189 dump_register(GTXFIFOSIZ(24)),
190 dump_register(GTXFIFOSIZ(25)),
191 dump_register(GTXFIFOSIZ(26)),
192 dump_register(GTXFIFOSIZ(27)),
193 dump_register(GTXFIFOSIZ(28)),
194 dump_register(GTXFIFOSIZ(29)),
195 dump_register(GTXFIFOSIZ(30)),
196 dump_register(GTXFIFOSIZ(31)),
197
198 dump_register(GRXFIFOSIZ(0)),
199 dump_register(GRXFIFOSIZ(1)),
200 dump_register(GRXFIFOSIZ(2)),
201 dump_register(GRXFIFOSIZ(3)),
202 dump_register(GRXFIFOSIZ(4)),
203 dump_register(GRXFIFOSIZ(5)),
204 dump_register(GRXFIFOSIZ(6)),
205 dump_register(GRXFIFOSIZ(7)),
206 dump_register(GRXFIFOSIZ(8)),
207 dump_register(GRXFIFOSIZ(9)),
208 dump_register(GRXFIFOSIZ(10)),
209 dump_register(GRXFIFOSIZ(11)),
210 dump_register(GRXFIFOSIZ(12)),
211 dump_register(GRXFIFOSIZ(13)),
212 dump_register(GRXFIFOSIZ(14)),
213 dump_register(GRXFIFOSIZ(15)),
214 dump_register(GRXFIFOSIZ(16)),
215 dump_register(GRXFIFOSIZ(17)),
216 dump_register(GRXFIFOSIZ(18)),
217 dump_register(GRXFIFOSIZ(19)),
218 dump_register(GRXFIFOSIZ(20)),
219 dump_register(GRXFIFOSIZ(21)),
220 dump_register(GRXFIFOSIZ(22)),
221 dump_register(GRXFIFOSIZ(23)),
222 dump_register(GRXFIFOSIZ(24)),
223 dump_register(GRXFIFOSIZ(25)),
224 dump_register(GRXFIFOSIZ(26)),
225 dump_register(GRXFIFOSIZ(27)),
226 dump_register(GRXFIFOSIZ(28)),
227 dump_register(GRXFIFOSIZ(29)),
228 dump_register(GRXFIFOSIZ(30)),
229 dump_register(GRXFIFOSIZ(31)),
230
231 dump_register(GEVNTADRLO(0)),
232 dump_register(GEVNTADRHI(0)),
233 dump_register(GEVNTSIZ(0)),
234 dump_register(GEVNTCOUNT(0)),
235
236 dump_register(GHWPARAMS8),
237 dump_register(DCFG),
238 dump_register(DCTL),
239 dump_register(DEVTEN),
240 dump_register(DSTS),
241 dump_register(DGCMDPAR),
242 dump_register(DGCMD),
243 dump_register(DALEPENA),
244
245 dump_register(DEPCMDPAR2(0)),
246 dump_register(DEPCMDPAR2(1)),
247 dump_register(DEPCMDPAR2(2)),
248 dump_register(DEPCMDPAR2(3)),
249 dump_register(DEPCMDPAR2(4)),
250 dump_register(DEPCMDPAR2(5)),
251 dump_register(DEPCMDPAR2(6)),
252 dump_register(DEPCMDPAR2(7)),
253 dump_register(DEPCMDPAR2(8)),
254 dump_register(DEPCMDPAR2(9)),
255 dump_register(DEPCMDPAR2(10)),
256 dump_register(DEPCMDPAR2(11)),
257 dump_register(DEPCMDPAR2(12)),
258 dump_register(DEPCMDPAR2(13)),
259 dump_register(DEPCMDPAR2(14)),
260 dump_register(DEPCMDPAR2(15)),
261 dump_register(DEPCMDPAR2(16)),
262 dump_register(DEPCMDPAR2(17)),
263 dump_register(DEPCMDPAR2(18)),
264 dump_register(DEPCMDPAR2(19)),
265 dump_register(DEPCMDPAR2(20)),
266 dump_register(DEPCMDPAR2(21)),
267 dump_register(DEPCMDPAR2(22)),
268 dump_register(DEPCMDPAR2(23)),
269 dump_register(DEPCMDPAR2(24)),
270 dump_register(DEPCMDPAR2(25)),
271 dump_register(DEPCMDPAR2(26)),
272 dump_register(DEPCMDPAR2(27)),
273 dump_register(DEPCMDPAR2(28)),
274 dump_register(DEPCMDPAR2(29)),
275 dump_register(DEPCMDPAR2(30)),
276 dump_register(DEPCMDPAR2(31)),
277
278 dump_register(DEPCMDPAR1(0)),
279 dump_register(DEPCMDPAR1(1)),
280 dump_register(DEPCMDPAR1(2)),
281 dump_register(DEPCMDPAR1(3)),
282 dump_register(DEPCMDPAR1(4)),
283 dump_register(DEPCMDPAR1(5)),
284 dump_register(DEPCMDPAR1(6)),
285 dump_register(DEPCMDPAR1(7)),
286 dump_register(DEPCMDPAR1(8)),
287 dump_register(DEPCMDPAR1(9)),
288 dump_register(DEPCMDPAR1(10)),
289 dump_register(DEPCMDPAR1(11)),
290 dump_register(DEPCMDPAR1(12)),
291 dump_register(DEPCMDPAR1(13)),
292 dump_register(DEPCMDPAR1(14)),
293 dump_register(DEPCMDPAR1(15)),
294 dump_register(DEPCMDPAR1(16)),
295 dump_register(DEPCMDPAR1(17)),
296 dump_register(DEPCMDPAR1(18)),
297 dump_register(DEPCMDPAR1(19)),
298 dump_register(DEPCMDPAR1(20)),
299 dump_register(DEPCMDPAR1(21)),
300 dump_register(DEPCMDPAR1(22)),
301 dump_register(DEPCMDPAR1(23)),
302 dump_register(DEPCMDPAR1(24)),
303 dump_register(DEPCMDPAR1(25)),
304 dump_register(DEPCMDPAR1(26)),
305 dump_register(DEPCMDPAR1(27)),
306 dump_register(DEPCMDPAR1(28)),
307 dump_register(DEPCMDPAR1(29)),
308 dump_register(DEPCMDPAR1(30)),
309 dump_register(DEPCMDPAR1(31)),
310
311 dump_register(DEPCMDPAR0(0)),
312 dump_register(DEPCMDPAR0(1)),
313 dump_register(DEPCMDPAR0(2)),
314 dump_register(DEPCMDPAR0(3)),
315 dump_register(DEPCMDPAR0(4)),
316 dump_register(DEPCMDPAR0(5)),
317 dump_register(DEPCMDPAR0(6)),
318 dump_register(DEPCMDPAR0(7)),
319 dump_register(DEPCMDPAR0(8)),
320 dump_register(DEPCMDPAR0(9)),
321 dump_register(DEPCMDPAR0(10)),
322 dump_register(DEPCMDPAR0(11)),
323 dump_register(DEPCMDPAR0(12)),
324 dump_register(DEPCMDPAR0(13)),
325 dump_register(DEPCMDPAR0(14)),
326 dump_register(DEPCMDPAR0(15)),
327 dump_register(DEPCMDPAR0(16)),
328 dump_register(DEPCMDPAR0(17)),
329 dump_register(DEPCMDPAR0(18)),
330 dump_register(DEPCMDPAR0(19)),
331 dump_register(DEPCMDPAR0(20)),
332 dump_register(DEPCMDPAR0(21)),
333 dump_register(DEPCMDPAR0(22)),
334 dump_register(DEPCMDPAR0(23)),
335 dump_register(DEPCMDPAR0(24)),
336 dump_register(DEPCMDPAR0(25)),
337 dump_register(DEPCMDPAR0(26)),
338 dump_register(DEPCMDPAR0(27)),
339 dump_register(DEPCMDPAR0(28)),
340 dump_register(DEPCMDPAR0(29)),
341 dump_register(DEPCMDPAR0(30)),
342 dump_register(DEPCMDPAR0(31)),
343
344 dump_register(DEPCMD(0)),
345 dump_register(DEPCMD(1)),
346 dump_register(DEPCMD(2)),
347 dump_register(DEPCMD(3)),
348 dump_register(DEPCMD(4)),
349 dump_register(DEPCMD(5)),
350 dump_register(DEPCMD(6)),
351 dump_register(DEPCMD(7)),
352 dump_register(DEPCMD(8)),
353 dump_register(DEPCMD(9)),
354 dump_register(DEPCMD(10)),
355 dump_register(DEPCMD(11)),
356 dump_register(DEPCMD(12)),
357 dump_register(DEPCMD(13)),
358 dump_register(DEPCMD(14)),
359 dump_register(DEPCMD(15)),
360 dump_register(DEPCMD(16)),
361 dump_register(DEPCMD(17)),
362 dump_register(DEPCMD(18)),
363 dump_register(DEPCMD(19)),
364 dump_register(DEPCMD(20)),
365 dump_register(DEPCMD(21)),
366 dump_register(DEPCMD(22)),
367 dump_register(DEPCMD(23)),
368 dump_register(DEPCMD(24)),
369 dump_register(DEPCMD(25)),
370 dump_register(DEPCMD(26)),
371 dump_register(DEPCMD(27)),
372 dump_register(DEPCMD(28)),
373 dump_register(DEPCMD(29)),
374 dump_register(DEPCMD(30)),
375 dump_register(DEPCMD(31)),
376
377 dump_register(OCFG),
378 dump_register(OCTL),
379 dump_register(OEVTEN),
380 dump_register(OSTS),
381};
382
383static int dwc3_regdump_show(struct seq_file *s, void *unused)
384{
385 struct dwc3 *dwc = s->private;
386 int i;
387
388 seq_printf(s, "DesignWare USB3 Core Register Dump\n");
389
390 for (i = 0; i < ARRAY_SIZE(dwc3_regs); i++) {
391 seq_printf(s, "%-20s : %08x\n", dwc3_regs[i].name,
392 dwc3_readl(dwc->regs, dwc3_regs[i].offset));
393 }
394
395 return 0;
396}
397
398static int dwc3_regdump_open(struct inode *inode, struct file *file)
399{
400 return single_open(file, dwc3_regdump_show, inode->i_private);
401}
402
403static const struct file_operations dwc3_regdump_fops = {
404 .open = dwc3_regdump_open,
405 .read = seq_read,
406 .release = single_release,
407};
408
409
410static int dwc3_send_testmode_cmd(struct dwc3 *dwc, int mode)
411{
412 u32 timeout = 250;
413
414 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, mode);
415 dwc3_writel(dwc->regs, DWC3_DGCMD, DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK |
416 DWC3_DEPCMD_CMDACT);
417 do {
418 u32 reg;
419
420 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
421 if (!(reg & DWC3_DEPCMD_CMDACT))
422 return 0;
423 timeout--;
424 if (!timeout)
425 return -ETIMEDOUT;
426 mdelay(1);
427 } while (1);
428}
429
430static struct dwc3_trb_hw trb_0 __aligned(16);
431static struct dwc3_trb_hw trb_1 __aligned(16);
432
433#define BUF_SIZE 4096
434static int dwc3_testmode_open(struct inode *inode, struct file *file)
435{
436 struct dwc3 *dwc = inode->i_private;
437 struct dwc3_gadget_ep_cmd_params par0;
438 struct dwc3_gadget_ep_cmd_params par1;
439 struct dwc3_trb trb;
440 int ret;
441 u8 *buf0;
442 u8 *buf1;
443
444 buf0 = kmalloc(BUF_SIZE, GFP_KERNEL);
445 if (!buf0)
446 return -ENOMEM;
447 buf1 = kmalloc(BUF_SIZE, GFP_KERNEL);
448 if (!buf1)
449 return -ENOMEM;
450
451 memset(buf0, 0xaa, BUF_SIZE);
452 memset(buf1, 0x33, BUF_SIZE);
453
454 memset(&trb, 0, sizeof(trb));
455 memset(&par0, 0, sizeof(par0));
456 memset(&par1, 0, sizeof(par1));
457
458 trb.lst = 1;
459 trb.trbctl = DWC3_TRBCTL_NORMAL;
460 trb.length = BUF_SIZE;
461 trb.hwo = 1;
462
463 trb.bplh = virt_to_phys(buf0);
464 dwc3_trb_to_hw(&trb, &trb_0);
465
466 trb.bplh = virt_to_phys(buf1);
467 dwc3_trb_to_hw(&trb, &trb_1);
468
469 par0.param0.depstrtxfer.transfer_desc_addr_high =
470 upper_32_bits(virt_to_phys(&trb_0));
471 par0.param1.depstrtxfer.transfer_desc_addr_low =
472 lower_32_bits(virt_to_phys(&trb_0));
473
474 par1.param0.depstrtxfer.transfer_desc_addr_high =
475 upper_32_bits(virt_to_phys(&trb_1));
476 par1.param1.depstrtxfer.transfer_desc_addr_low =
477 lower_32_bits(virt_to_phys(&trb_1));
478
479 dwc3_send_testmode_cmd(dwc, 1);
480
481 ret = dwc3_send_gadget_ep_cmd(dwc, 0, DWC3_DEPCMD_STARTTRANSFER, &par0);
482 ret = dwc3_send_gadget_ep_cmd(dwc, 1, DWC3_DEPCMD_STARTTRANSFER, &par1);
483
484 dwc3_send_testmode_cmd(dwc, 0);
485 return -EBUSY;
486}
487
488static const struct file_operations dwc3_testmode_fops = {
489 .open = dwc3_testmode_open,
490 .read = seq_read,
491 .release = single_release,
492};
493
494int __devinit dwc3_debugfs_init(struct dwc3 *dwc)
495{
496 struct dentry *root;
497 struct dentry *file;
498 int ret;
499
500 root = debugfs_create_dir(dev_name(dwc->dev), NULL);
501 if (IS_ERR(root)){
502 ret = PTR_ERR(root);
503 goto err0;
504 }
505
506 dwc->root = root;
507
508 file = debugfs_create_file("regdump", S_IRUGO, root, dwc,
509 &dwc3_regdump_fops);
510 if (IS_ERR(file)) {
511 ret = PTR_ERR(file);
512 goto err1;
513 }
514 file = debugfs_create_file("testmode", S_IRUGO, root, dwc,
515 &dwc3_testmode_fops);
516 if (IS_ERR(file)) {
517 ret = PTR_ERR(file);
518 goto err1;
519 }
520
521 return 0;
522
523err1:
524 debugfs_remove_recursive(root);
525
526err0:
527 return ret;
528}
529
530void __devexit dwc3_debugfs_exit(struct dwc3 *dwc)
531{
532 debugfs_remove_recursive(dwc->root);
533 dwc->root = NULL;
534}
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
new file mode 100644
index 00000000000..08fffe6d1a9
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -0,0 +1,410 @@
1/**
2 * dwc3-omap.c - OMAP Specific Glue layer
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/interrupt.h>
43#include <linux/spinlock.h>
44#include <linux/platform_device.h>
45#include <linux/dma-mapping.h>
46#include <linux/ioport.h>
47#include <linux/io.h>
48
49#include "io.h"
50
51/*
52 * All these registers belong to OMAP's Wrapper around the
53 * DesignWare USB3 Core.
54 */
55
56#define USBOTGSS_REVISION 0x0000
57#define USBOTGSS_SYSCONFIG 0x0010
58#define USBOTGSS_IRQ_EOI 0x0020
59#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
60#define USBOTGSS_IRQSTATUS_0 0x0028
61#define USBOTGSS_IRQENABLE_SET_0 0x002c
62#define USBOTGSS_IRQENABLE_CLR_0 0x0030
63#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
64#define USBOTGSS_IRQSTATUS_1 0x0038
65#define USBOTGSS_IRQENABLE_SET_1 0x003c
66#define USBOTGSS_IRQENABLE_CLR_1 0x0040
67#define USBOTGSS_UTMI_OTG_CTRL 0x0080
68#define USBOTGSS_UTMI_OTG_STATUS 0x0084
69#define USBOTGSS_MMRAM_OFFSET 0x0100
70#define USBOTGSS_FLADJ 0x0104
71#define USBOTGSS_DEBUG_CFG 0x0108
72#define USBOTGSS_DEBUG_DATA 0x010c
73
74/* SYSCONFIG REGISTER */
75#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
76#define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
77#define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
78
79/* IRQ_EOI REGISTER */
80#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
81
82/* IRQS0 BITS */
83#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
84
85/* IRQ1 BITS */
86#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
87#define USBOTGSS_IRQ1_OEVT (1 << 16)
88#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
89#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
90#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
91#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
92#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
93#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
94#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
95#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
96
97/* UTMI_OTG_CTRL REGISTER */
98#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
99#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
100#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
101#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
102
103/* UTMI_OTG_STATUS REGISTER */
104#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
105#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
106#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
107#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
108#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
109#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
110#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
111
112struct dwc3_omap {
113 /* device lock */
114 spinlock_t lock;
115
116 struct platform_device *dwc3;
117 struct device *dev;
118
119 int irq;
120 void __iomem *base;
121
122 void *context;
123 u32 resource_size;
124
125 u32 dma_status:1;
126};
127
128#ifdef CONFIG_PM
129static int dwc3_omap_suspend(struct device *dev)
130{
131 struct dwc3_omap *omap = dev_get_drvdata(dev);
132
133 memcpy_fromio(omap->context, omap->base, omap->resource_size);
134
135 return 0;
136}
137
138static int dwc3_omap_resume(struct device *dev)
139{
140 struct dwc3_omap *omap = dev_get_drvdata(dev);
141
142 memcpy_toio(omap->base, omap->context, omap->resource_size);
143
144 return 0;
145}
146
147static int dwc3_omap_idle(struct device *dev)
148{
149 struct dwc3_omap *omap = dev_get_drvdata(dev);
150 u32 reg;
151
152 /* stop DMA Engine */
153 reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
154 reg &= ~(USBOTGSS_SYSCONFIG_DMADISABLE);
155 dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
156
157 return 0;
158}
159
160static UNIVERSAL_DEV_PM_OPS(dwc3_omap_pm_ops, dwc3_omap_suspend,
161 dwc3_omap_resume, dwc3_omap_idle);
162
163#define DEV_PM_OPS (&dwc3_omap_pm_ops)
164#else
165#define DEV_PM_OPS NULL
166#endif
167
168static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
169{
170 struct dwc3_omap *omap = _omap;
171 u32 reg;
172 u32 ctrl;
173
174 spin_lock(&omap->lock);
175
176 reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);
177 ctrl = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL);
178
179 if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
180 dev_dbg(omap->base, "DMA Disable was Cleared\n");
181 omap->dma_status = false;
182 }
183
184 if (reg & USBOTGSS_IRQ1_OEVT)
185 dev_dbg(omap->base, "OTG Event\n");
186
187 if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE) {
188 dev_dbg(omap->base, "DRVVBUS Rise\n");
189 ctrl |= USBOTGSS_UTMI_OTG_CTRL_DRVVBUS;
190 }
191
192 if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE) {
193 dev_dbg(omap->base, "CHRGVBUS Rise\n");
194 ctrl |= USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS;
195 }
196
197 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE) {
198 dev_dbg(omap->base, "DISCHRGVBUS Rise\n");
199 ctrl |= USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS;
200 }
201
202 if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE) {
203 dev_dbg(omap->base, "IDPULLUP Rise\n");
204 ctrl |= USBOTGSS_UTMI_OTG_CTRL_IDPULLUP;
205 }
206
207 if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL) {
208 dev_dbg(omap->base, "DRVVBUS Fall\n");
209 ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_DRVVBUS;
210 }
211
212 if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL) {
213 dev_dbg(omap->base, "CHRGVBUS Fall\n");
214 ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS;
215 }
216
217 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL) {
218 dev_dbg(omap->base, "DISCHRGVBUS Fall\n");
219 ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS;
220 }
221
222 if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL) {
223 dev_dbg(omap->base, "IDPULLUP Fall\n");
224 ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_IDPULLUP;
225 }
226
227 dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL, ctrl);
228
229 spin_unlock(&omap->lock);
230
231 return IRQ_HANDLED;
232}
233
234static int __devinit dwc3_omap_probe(struct platform_device *pdev)
235{
236 struct platform_device *dwc3;
237 struct dwc3_omap *omap;
238 struct resource *res;
239
240 int ret = -ENOMEM;
241 int irq;
242
243 u32 reg;
244
245 void __iomem *base;
246 void *context;
247
248 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
249 if (!omap) {
250 dev_err(&pdev->dev, "not enough memory\n");
251 goto err0;
252 }
253
254 platform_set_drvdata(pdev, omap);
255
256 irq = platform_get_irq(pdev, 1);
257 if (irq < 0) {
258 dev_err(&pdev->dev, "missing IRQ resource\n");
259 ret = -EINVAL;
260 goto err1;
261 }
262
263 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
264 if (!res) {
265 dev_err(&pdev->dev, "missing memory base resource\n");
266 ret = -EINVAL;
267 goto err1;
268 }
269
270 base = ioremap_nocache(res->start, resource_size(res));
271 if (!base) {
272 dev_err(&pdev->dev, "ioremap failed\n");
273 goto err1;
274 }
275
276 dwc3 = platform_device_alloc("dwc3-omap", -1);
277 if (!dwc3) {
278 dev_err(&pdev->dev, "couldn't allocate dwc3 device\n");
279 goto err2;
280 }
281
282 context = kzalloc(resource_size(res), GFP_KERNEL);
283 if (!context) {
284 dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n");
285 goto err3;
286 }
287
288 spin_lock_init(&omap->lock);
289 dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask);
290
291 dwc3->dev.parent = &pdev->dev;
292 dwc3->dev.dma_mask = pdev->dev.dma_mask;
293 dwc3->dev.dma_parms = pdev->dev.dma_parms;
294 omap->resource_size = resource_size(res);
295 omap->context = context;
296 omap->dev = &pdev->dev;
297 omap->irq = irq;
298 omap->base = base;
299 omap->dwc3 = dwc3;
300
301 /* check the DMA Status */
302 reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
303 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
304
305 ret = request_irq(omap->irq, dwc3_omap_interrupt, 0,
306 "dwc3-wrapper", omap);
307 if (ret) {
308 dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n",
309 omap->irq, ret);
310 goto err4;
311 }
312
313 /* enable all IRQs */
314 dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, 0x01);
315
316 reg = (USBOTGSS_IRQ1_DMADISABLECLR |
317 USBOTGSS_IRQ1_OEVT |
318 USBOTGSS_IRQ1_DRVVBUS_RISE |
319 USBOTGSS_IRQ1_CHRGVBUS_RISE |
320 USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
321 USBOTGSS_IRQ1_IDPULLUP_RISE |
322 USBOTGSS_IRQ1_DRVVBUS_FALL |
323 USBOTGSS_IRQ1_CHRGVBUS_FALL |
324 USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
325 USBOTGSS_IRQ1_IDPULLUP_FALL);
326
327 dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
328
329 ret = platform_device_add_resources(dwc3, pdev->resource,
330 pdev->num_resources);
331 if (ret) {
332 dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n");
333 goto err5;
334 }
335
336 ret = platform_device_add(dwc3);
337 if (ret) {
338 dev_err(&pdev->dev, "failed to register dwc3 device\n");
339 goto err5;
340 }
341
342 return 0;
343
344err5:
345 free_irq(omap->irq, omap);
346
347err4:
348 kfree(omap->context);
349
350err3:
351 platform_device_put(dwc3);
352
353err2:
354 iounmap(base);
355
356err1:
357 kfree(omap);
358
359err0:
360 return ret;
361}
362
363static int __devexit dwc3_omap_remove(struct platform_device *pdev)
364{
365 struct dwc3_omap *omap = platform_get_drvdata(pdev);
366
367 platform_device_unregister(omap->dwc3);
368
369 free_irq(omap->irq, omap);
370 iounmap(omap->base);
371
372 kfree(omap->context);
373 kfree(omap);
374
375 return 0;
376}
377
378static const struct of_device_id of_dwc3_matach[] = {
379 {
380 "ti,dwc3",
381 },
382 { },
383};
384MODULE_DEVICE_TABLE(of, of_dwc3_matach);
385
386static struct platform_driver dwc3_omap_driver = {
387 .probe = dwc3_omap_probe,
388 .remove = __devexit_p(dwc3_omap_remove),
389 .driver = {
390 .name = "omap-dwc3",
391 .pm = DEV_PM_OPS,
392 .of_match_table = of_dwc3_matach,
393 },
394};
395
396MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
397MODULE_LICENSE("Dual BSD/GPL");
398MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
399
400static int __devinit dwc3_omap_init(void)
401{
402 return platform_driver_register(&dwc3_omap_driver);
403}
404module_init(dwc3_omap_init);
405
406static void __exit dwc3_omap_exit(void)
407{
408 platform_driver_unregister(&dwc3_omap_driver);
409}
410module_exit(dwc3_omap_exit);
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
new file mode 100644
index 00000000000..257859564f9
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -0,0 +1,219 @@
1/**
2 * dwc3-pci.c - PCI Specific glue layer
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/pci.h>
43#include <linux/platform_device.h>
44
45/* FIXME define these in <linux/pci_ids.h> */
46#define PCI_VENDOR_ID_SYNOPSYS 0x16c3
47#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
48
49#define DWC3_PCI_DEVS_POSSIBLE 32
50
51struct dwc3_pci {
52 struct device *dev;
53 struct platform_device *dwc3;
54};
55
56static DECLARE_BITMAP(dwc3_pci_devs, DWC3_PCI_DEVS_POSSIBLE);
57
58static int dwc3_pci_get_device_id(struct dwc3_pci *glue)
59{
60 int id;
61
62again:
63 id = find_first_zero_bit(dwc3_pci_devs, DWC3_PCI_DEVS_POSSIBLE);
64 if (id < DWC3_PCI_DEVS_POSSIBLE) {
65 int old;
66
67 old = test_and_set_bit(id, dwc3_pci_devs);
68 if (old)
69 goto again;
70 } else {
71 dev_err(glue->dev, "no space for new device\n");
72 id = -ENOMEM;
73 }
74
75 return 0;
76}
77
78static void dwc3_pci_put_device_id(struct dwc3_pci *glue, int id)
79{
80 int ret;
81
82 if (id < 0)
83 return;
84
85 ret = test_bit(id, dwc3_pci_devs);
86 WARN(!ret, "Device: %s\nID %d not in use\n",
87 dev_driver_string(glue->dev), id);
88 clear_bit(id, dwc3_pci_devs);
89}
90
91static int __devinit dwc3_pci_probe(struct pci_dev *pci,
92 const struct pci_device_id *id)
93{
94 struct resource res[2];
95 struct platform_device *dwc3;
96 struct dwc3_pci *glue;
97 int ret = -ENOMEM;
98 int devid;
99
100 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
101 if (!glue) {
102 dev_err(&pci->dev, "not enough memory\n");
103 goto err0;
104 }
105
106 glue->dev = &pci->dev;
107
108 ret = pci_enable_device(pci);
109 if (ret) {
110 dev_err(&pci->dev, "failed to enable pci device\n");
111 goto err1;
112 }
113
114 pci_set_power_state(pci, PCI_D0);
115 pci_set_master(pci);
116
117 devid = dwc3_pci_get_device_id(glue);
118 if (devid < 0)
119 goto err2;
120
121 dwc3 = platform_device_alloc("dwc3-pci", devid);
122 if (!dwc3) {
123 dev_err(&pci->dev, "couldn't allocate dwc3 device\n");
124 goto err3;
125 }
126
127 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
128
129 res[0].start = pci_resource_start(pci, 0);
130 res[0].end = pci_resource_end(pci, 0);
131 res[0].name = "dwc_usb3";
132 res[0].flags = IORESOURCE_MEM;
133
134 res[1].start = pci->irq;
135 res[1].name = "dwc_usb3";
136 res[1].flags = IORESOURCE_IRQ;
137
138 ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
139 if (ret) {
140 dev_err(&pci->dev, "couldn't add resources to dwc3 device\n");
141 goto err4;
142 }
143
144 pci_set_drvdata(pci, glue);
145
146 dma_set_coherent_mask(&dwc3->dev, pci->dev.coherent_dma_mask);
147
148 dwc3->dev.dma_mask = pci->dev.dma_mask;
149 dwc3->dev.dma_parms = pci->dev.dma_parms;
150 dwc3->dev.parent = &pci->dev;
151 glue->dwc3 = dwc3;
152
153 ret = platform_device_add(dwc3);
154 if (ret) {
155 dev_err(&pci->dev, "failed to register dwc3 device\n");
156 goto err4;
157 }
158
159 return 0;
160
161err4:
162 pci_set_drvdata(pci, NULL);
163 platform_device_put(dwc3);
164
165err3:
166 dwc3_pci_put_device_id(glue, devid);
167
168err2:
169 pci_disable_device(pci);
170
171err1:
172 kfree(pci);
173
174err0:
175 return ret;
176}
177
178static void __devexit dwc3_pci_remove(struct pci_dev *pci)
179{
180 struct dwc3_pci *glue = pci_get_drvdata(pci);
181
182 dwc3_pci_put_device_id(glue, glue->dwc3->id);
183 platform_device_unregister(glue->dwc3);
184 pci_set_drvdata(pci, NULL);
185 pci_disable_device(pci);
186 kfree(glue);
187}
188
189static DEFINE_PCI_DEVICE_TABLE(dwc3_pci_id_table) = {
190 {
191 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
192 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
193 },
194 { } /* Terminating Entry */
195};
196MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
197
198static struct pci_driver dwc3_pci_driver = {
199 .name = "pci-dwc3",
200 .id_table = dwc3_pci_id_table,
201 .probe = dwc3_pci_probe,
202 .remove = __devexit_p(dwc3_pci_remove),
203};
204
205MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
206MODULE_LICENSE("Dual BSD/GPL");
207MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
208
209static int __devinit dwc3_pci_init(void)
210{
211 return pci_register_driver(&dwc3_pci_driver);
212}
213module_init(dwc3_pci_init);
214
215static void __exit dwc3_pci_exit(void)
216{
217 pci_unregister_driver(&dwc3_pci_driver);
218}
219module_exit(dwc3_pci_exit);
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
new file mode 100644
index 00000000000..4698fe01376
--- /dev/null
+++ b/drivers/usb/dwc3/ep0.c
@@ -0,0 +1,782 @@
1/**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
58 const struct dwc3_event_depevt *event);
59
60static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
61{
62 switch (state) {
63 case EP0_UNCONNECTED:
64 return "Unconnected";
65 case EP0_IDLE:
66 return "Idle";
67 case EP0_IN_DATA_PHASE:
68 return "IN Data Phase";
69 case EP0_OUT_DATA_PHASE:
70 return "OUT Data Phase";
71 case EP0_IN_WAIT_GADGET:
72 return "IN Wait Gadget";
73 case EP0_OUT_WAIT_GADGET:
74 return "OUT Wait Gadget";
75 case EP0_IN_WAIT_NRDY:
76 return "IN Wait NRDY";
77 case EP0_OUT_WAIT_NRDY:
78 return "OUT Wait NRDY";
79 case EP0_IN_STATUS_PHASE:
80 return "IN Status Phase";
81 case EP0_OUT_STATUS_PHASE:
82 return "OUT Status Phase";
83 case EP0_STALL:
84 return "Stall";
85 default:
86 return "UNKNOWN";
87 }
88}
89
90static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
91 u32 len)
92{
93 struct dwc3_gadget_ep_cmd_params params;
94 struct dwc3_trb_hw *trb_hw;
95 struct dwc3_trb trb;
96 struct dwc3_ep *dep;
97
98 int ret;
99
100 dep = dwc->eps[epnum];
101
102 trb_hw = dwc->ep0_trb;
103 memset(&trb, 0, sizeof(trb));
104
105 switch (dwc->ep0state) {
106 case EP0_IDLE:
107 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
108 break;
109
110 case EP0_IN_WAIT_NRDY:
111 case EP0_OUT_WAIT_NRDY:
112 case EP0_IN_STATUS_PHASE:
113 case EP0_OUT_STATUS_PHASE:
114 if (dwc->three_stage_setup)
115 trb.trbctl = DWC3_TRBCTL_CONTROL_STATUS3;
116 else
117 trb.trbctl = DWC3_TRBCTL_CONTROL_STATUS2;
118
119 if (dwc->ep0state == EP0_IN_WAIT_NRDY)
120 dwc->ep0state = EP0_IN_STATUS_PHASE;
121 else if (dwc->ep0state == EP0_OUT_WAIT_NRDY)
122 dwc->ep0state = EP0_OUT_STATUS_PHASE;
123 break;
124
125 case EP0_IN_WAIT_GADGET:
126 dwc->ep0state = EP0_IN_WAIT_NRDY;
127 return 0;
128 break;
129
130 case EP0_OUT_WAIT_GADGET:
131 dwc->ep0state = EP0_OUT_WAIT_NRDY;
132 return 0;
133
134 break;
135
136 case EP0_IN_DATA_PHASE:
137 case EP0_OUT_DATA_PHASE:
138 trb.trbctl = DWC3_TRBCTL_CONTROL_DATA;
139 break;
140
141 default:
142 dev_err(dwc->dev, "%s() can't in state %d\n", __func__,
143 dwc->ep0state);
144 return -EINVAL;
145 }
146
147 trb.bplh = buf_dma;
148 trb.length = len;
149
150 trb.hwo = 1;
151 trb.lst = 1;
152 trb.ioc = 1;
153 trb.isp_imi = 1;
154
155 dwc3_trb_to_hw(&trb, trb_hw);
156
157 memset(&params, 0, sizeof(params));
158 params.param0.depstrtxfer.transfer_desc_addr_high =
159 upper_32_bits(dwc->ep0_trb_addr);
160 params.param1.depstrtxfer.transfer_desc_addr_low =
161 lower_32_bits(dwc->ep0_trb_addr);
162
163 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
164 DWC3_DEPCMD_STARTTRANSFER, &params);
165 if (ret < 0) {
166 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
167 return ret;
168 }
169
170 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
171 dep->number);
172
173 return 0;
174}
175
176static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
177 struct dwc3_request *req)
178{
179 struct dwc3 *dwc = dep->dwc;
180 int ret;
181
182 req->request.actual = 0;
183 req->request.status = -EINPROGRESS;
184 req->direction = dep->direction;
185 req->epnum = dep->number;
186
187 list_add_tail(&req->list, &dep->request_list);
188 dwc3_map_buffer_to_dma(req);
189
190 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
191 req->request.length);
192 if (ret < 0) {
193 list_del(&req->list);
194 dwc3_unmap_buffer_from_dma(req);
195 }
196
197 return ret;
198}
199
200int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
201 gfp_t gfp_flags)
202{
203 struct dwc3_request *req = to_dwc3_request(request);
204 struct dwc3_ep *dep = to_dwc3_ep(ep);
205 struct dwc3 *dwc = dep->dwc;
206
207 unsigned long flags;
208
209 int ret;
210
211 switch (dwc->ep0state) {
212 case EP0_IN_DATA_PHASE:
213 case EP0_IN_WAIT_GADGET:
214 case EP0_IN_WAIT_NRDY:
215 case EP0_IN_STATUS_PHASE:
216 dep = dwc->eps[1];
217 break;
218
219 case EP0_OUT_DATA_PHASE:
220 case EP0_OUT_WAIT_GADGET:
221 case EP0_OUT_WAIT_NRDY:
222 case EP0_OUT_STATUS_PHASE:
223 dep = dwc->eps[0];
224 break;
225 default:
226 return -EINVAL;
227 }
228
229 spin_lock_irqsave(&dwc->lock, flags);
230 if (!dep->desc) {
231 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
232 request, dep->name);
233 ret = -ESHUTDOWN;
234 goto out;
235 }
236
237 /* we share one TRB for ep0/1 */
238 if (!list_empty(&dwc->eps[0]->request_list) ||
239 !list_empty(&dwc->eps[1]->request_list) ||
240 dwc->ep0_status_pending) {
241 ret = -EBUSY;
242 goto out;
243 }
244
245 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
246 request, dep->name, request->length,
247 dwc3_ep0_state_string(dwc->ep0state));
248
249 ret = __dwc3_gadget_ep0_queue(dep, req);
250
251out:
252 spin_unlock_irqrestore(&dwc->lock, flags);
253
254 return ret;
255}
256
257static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
258{
259 /* stall is always issued on EP0 */
260 __dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
261 dwc->eps[0]->flags &= ~DWC3_EP_STALL;
262 dwc->ep0state = EP0_IDLE;
263 dwc3_ep0_out_start(dwc);
264}
265
266void dwc3_ep0_out_start(struct dwc3 *dwc)
267{
268 struct dwc3_ep *dep;
269 int ret;
270
271 dep = dwc->eps[0];
272
273 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8);
274 WARN_ON(ret < 0);
275}
276
277/*
278 * Send a zero length packet for the status phase of the control transfer
279 */
280static void dwc3_ep0_do_setup_status(struct dwc3 *dwc,
281 const struct dwc3_event_depevt *event)
282{
283 struct dwc3_ep *dep;
284 int ret;
285 u32 epnum;
286
287 epnum = event->endpoint_number;
288 dep = dwc->eps[epnum];
289
290 if (epnum)
291 dwc->ep0state = EP0_IN_STATUS_PHASE;
292 else
293 dwc->ep0state = EP0_OUT_STATUS_PHASE;
294
295 /*
296 * Not sure Why I need a buffer for a zero transfer. Maybe the
297 * HW reacts strange on a NULL pointer
298 */
299 ret = dwc3_ep0_start_trans(dwc, epnum, dwc->ctrl_req_addr, 0);
300 if (ret) {
301 dev_dbg(dwc->dev, "failed to start transfer, stalling\n");
302 dwc3_ep0_stall_and_restart(dwc);
303 }
304}
305
306static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
307{
308 struct dwc3_ep *dep;
309 u32 windex = le16_to_cpu(wIndex_le);
310 u32 epnum;
311
312 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
313 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
314 epnum |= 1;
315
316 dep = dwc->eps[epnum];
317 if (dep->flags & DWC3_EP_ENABLED)
318 return dep;
319
320 return NULL;
321}
322
323static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
324{
325 u32 epnum;
326
327 if (dwc->ep0state == EP0_IN_DATA_PHASE)
328 epnum = 1;
329 else
330 epnum = 0;
331
332 dwc3_ep0_start_trans(dwc, epnum, dwc->ctrl_req_addr,
333 dwc->ep0_usb_req.length);
334 dwc->ep0_status_pending = 1;
335}
336
337/*
338 * ch 9.4.5
339 */
340static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
341{
342 struct dwc3_ep *dep;
343 u32 recip;
344 u16 usb_status = 0;
345 __le16 *response_pkt;
346
347 recip = ctrl->bRequestType & USB_RECIP_MASK;
348 switch (recip) {
349 case USB_RECIP_DEVICE:
350 /*
351 * We are self-powered. U1/U2/LTM will be set later
352 * once we handle this states. RemoteWakeup is 0 on SS
353 */
354 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
355 break;
356
357 case USB_RECIP_INTERFACE:
358 /*
359 * Function Remote Wake Capable D0
360 * Function Remote Wakeup D1
361 */
362 break;
363
364 case USB_RECIP_ENDPOINT:
365 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
366 if (!dep)
367 return -EINVAL;
368
369 if (dep->flags & DWC3_EP_STALL)
370 usb_status = 1 << USB_ENDPOINT_HALT;
371 break;
372 default:
373 return -EINVAL;
374 };
375
376 response_pkt = (__le16 *) dwc->setup_buf;
377 *response_pkt = cpu_to_le16(usb_status);
378 dwc->ep0_usb_req.length = sizeof(*response_pkt);
379 dwc3_ep0_send_status_response(dwc);
380
381 return 0;
382}
383
384static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
385 struct usb_ctrlrequest *ctrl, int set)
386{
387 struct dwc3_ep *dep;
388 u32 recip;
389 u32 wValue;
390 u32 wIndex;
391 u32 reg;
392 int ret;
393 u32 mode;
394
395 wValue = le16_to_cpu(ctrl->wValue);
396 wIndex = le16_to_cpu(ctrl->wIndex);
397 recip = ctrl->bRequestType & USB_RECIP_MASK;
398 switch (recip) {
399 case USB_RECIP_DEVICE:
400
401 /*
402 * 9.4.1 says only only for SS, in AddressState only for
403 * default control pipe
404 */
405 switch (wValue) {
406 case USB_DEVICE_U1_ENABLE:
407 case USB_DEVICE_U2_ENABLE:
408 case USB_DEVICE_LTM_ENABLE:
409 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
410 return -EINVAL;
411 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
412 return -EINVAL;
413 }
414
415 /* XXX add U[12] & LTM */
416 switch (wValue) {
417 case USB_DEVICE_REMOTE_WAKEUP:
418 break;
419 case USB_DEVICE_U1_ENABLE:
420 break;
421 case USB_DEVICE_U2_ENABLE:
422 break;
423 case USB_DEVICE_LTM_ENABLE:
424 break;
425
426 case USB_DEVICE_TEST_MODE:
427 if ((wIndex & 0xff) != 0)
428 return -EINVAL;
429 if (!set)
430 return -EINVAL;
431
432 mode = wIndex >> 8;
433 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
434 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
435
436 switch (mode) {
437 case TEST_J:
438 case TEST_K:
439 case TEST_SE0_NAK:
440 case TEST_PACKET:
441 case TEST_FORCE_EN:
442 reg |= mode << 1;
443 break;
444 default:
445 return -EINVAL;
446 }
447 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
448 break;
449 default:
450 return -EINVAL;
451 }
452 break;
453
454 case USB_RECIP_INTERFACE:
455 switch (wValue) {
456 case USB_INTRF_FUNC_SUSPEND:
457 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
458 /* XXX enable Low power suspend */
459 ;
460 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
461 /* XXX enable remote wakeup */
462 ;
463 break;
464 default:
465 return -EINVAL;
466 }
467 break;
468
469 case USB_RECIP_ENDPOINT:
470 switch (wValue) {
471 case USB_ENDPOINT_HALT:
472
473 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
474 if (!dep)
475 return -EINVAL;
476 ret = __dwc3_gadget_ep_set_halt(dep, set);
477 if (ret)
478 return -EINVAL;
479 break;
480 default:
481 return -EINVAL;
482 }
483 break;
484
485 default:
486 return -EINVAL;
487 };
488
489 dwc->ep0state = EP0_IN_WAIT_NRDY;
490
491 return 0;
492}
493
494static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
495{
496 int ret = 0;
497 u32 addr;
498 u32 reg;
499
500 addr = le16_to_cpu(ctrl->wValue);
501 if (addr > 127)
502 return -EINVAL;
503
504 switch (dwc->dev_state) {
505 case DWC3_DEFAULT_STATE:
506 case DWC3_ADDRESS_STATE:
507 /*
508 * Not sure if we should program DevAddr now or later
509 */
510 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
511 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
512 reg |= DWC3_DCFG_DEVADDR(addr);
513 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
514
515 if (addr)
516 dwc->dev_state = DWC3_ADDRESS_STATE;
517 else
518 dwc->dev_state = DWC3_DEFAULT_STATE;
519 break;
520
521 case DWC3_CONFIGURED_STATE:
522 ret = -EINVAL;
523 break;
524 }
525 dwc->ep0state = EP0_IN_WAIT_NRDY;
526 return ret;
527}
528
529static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
530{
531 int ret;
532
533 spin_unlock(&dwc->lock);
534 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
535 spin_lock(&dwc->lock);
536 return ret;
537}
538
539static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
540{
541 u32 cfg;
542 int ret;
543
544 cfg = le16_to_cpu(ctrl->wValue);
545
546 switch (dwc->dev_state) {
547 case DWC3_DEFAULT_STATE:
548 return -EINVAL;
549 break;
550
551 case DWC3_ADDRESS_STATE:
552 ret = dwc3_ep0_delegate_req(dwc, ctrl);
553 /* if the cfg matches and the cfg is non zero */
554 if (!ret && cfg)
555 dwc->dev_state = DWC3_CONFIGURED_STATE;
556 break;
557
558 case DWC3_CONFIGURED_STATE:
559 ret = dwc3_ep0_delegate_req(dwc, ctrl);
560 if (!cfg)
561 dwc->dev_state = DWC3_ADDRESS_STATE;
562 break;
563 }
564 return 0;
565}
566
567static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
568{
569 int ret;
570
571 switch (ctrl->bRequest) {
572 case USB_REQ_GET_STATUS:
573 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
574 ret = dwc3_ep0_handle_status(dwc, ctrl);
575 break;
576 case USB_REQ_CLEAR_FEATURE:
577 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
578 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
579 break;
580 case USB_REQ_SET_FEATURE:
581 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
582 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
583 break;
584 case USB_REQ_SET_ADDRESS:
585 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
586 ret = dwc3_ep0_set_address(dwc, ctrl);
587 break;
588 case USB_REQ_SET_CONFIGURATION:
589 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
590 ret = dwc3_ep0_set_config(dwc, ctrl);
591 break;
592 default:
593 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
594 ret = dwc3_ep0_delegate_req(dwc, ctrl);
595 break;
596 };
597
598 return ret;
599}
600
601static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
602 const struct dwc3_event_depevt *event)
603{
604 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
605 int ret;
606 u32 len;
607
608 if (!dwc->gadget_driver)
609 goto err;
610
611 len = le16_to_cpu(ctrl->wLength);
612 if (!len) {
613 dwc->ep0state = EP0_IN_WAIT_GADGET;
614 dwc->three_stage_setup = 0;
615 } else {
616 dwc->three_stage_setup = 1;
617 if (ctrl->bRequestType & USB_DIR_IN)
618 dwc->ep0state = EP0_IN_DATA_PHASE;
619 else
620 dwc->ep0state = EP0_OUT_DATA_PHASE;
621 }
622
623 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
624 ret = dwc3_ep0_std_request(dwc, ctrl);
625 else
626 ret = dwc3_ep0_delegate_req(dwc, ctrl);
627
628 if (ret >= 0)
629 return;
630
631err:
632 dwc3_ep0_stall_and_restart(dwc);
633}
634
635static void dwc3_ep0_complete_data(struct dwc3 *dwc,
636 const struct dwc3_event_depevt *event)
637{
638 struct dwc3_request *r = NULL;
639 struct usb_request *ur;
640 struct dwc3_trb trb;
641 struct dwc3_ep *dep;
642 u32 transfered;
643 u8 epnum;
644
645 epnum = event->endpoint_number;
646 dep = dwc->eps[epnum];
647
648 if (!dwc->ep0_status_pending) {
649 r = next_request(&dep->request_list);
650 ur = &r->request;
651 } else {
652 ur = &dwc->ep0_usb_req;
653 dwc->ep0_status_pending = 0;
654 }
655
656 dwc3_trb_to_nat(dwc->ep0_trb, &trb);
657
658 transfered = ur->length - trb.length;
659 ur->actual += transfered;
660
661 if ((epnum & 1) && ur->actual < ur->length) {
662 /* for some reason we did not get everything out */
663
664 dwc3_ep0_stall_and_restart(dwc);
665 dwc3_gadget_giveback(dep, r, -ECONNRESET);
666 } else {
667 /*
668 * handle the case where we have to send a zero packet. This
669 * seems to be case when req.length > maxpacket. Could it be?
670 */
671 /* The transfer is complete, wait for HOST */
672 if (epnum & 1)
673 dwc->ep0state = EP0_IN_WAIT_NRDY;
674 else
675 dwc->ep0state = EP0_OUT_WAIT_NRDY;
676
677 if (r)
678 dwc3_gadget_giveback(dep, r, 0);
679 }
680}
681
682static void dwc3_ep0_complete_req(struct dwc3 *dwc,
683 const struct dwc3_event_depevt *event)
684{
685 struct dwc3_request *r;
686 struct dwc3_ep *dep;
687 u8 epnum;
688
689 epnum = event->endpoint_number;
690 dep = dwc->eps[epnum];
691
692 if (!list_empty(&dep->request_list)) {
693 r = next_request(&dep->request_list);
694
695 dwc3_gadget_giveback(dep, r, 0);
696 }
697
698 dwc->ep0state = EP0_IDLE;
699 dwc3_ep0_out_start(dwc);
700}
701
702static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
703 const struct dwc3_event_depevt *event)
704{
705 switch (dwc->ep0state) {
706 case EP0_IDLE:
707 dwc3_ep0_inspect_setup(dwc, event);
708 break;
709
710 case EP0_IN_DATA_PHASE:
711 case EP0_OUT_DATA_PHASE:
712 dwc3_ep0_complete_data(dwc, event);
713 break;
714
715 case EP0_IN_STATUS_PHASE:
716 case EP0_OUT_STATUS_PHASE:
717 dwc3_ep0_complete_req(dwc, event);
718 break;
719
720 case EP0_IN_WAIT_NRDY:
721 case EP0_OUT_WAIT_NRDY:
722 case EP0_IN_WAIT_GADGET:
723 case EP0_OUT_WAIT_GADGET:
724 case EP0_UNCONNECTED:
725 case EP0_STALL:
726 break;
727 }
728}
729
730static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
731 const struct dwc3_event_depevt *event)
732{
733 switch (dwc->ep0state) {
734 case EP0_IN_WAIT_GADGET:
735 dwc->ep0state = EP0_IN_WAIT_NRDY;
736 break;
737 case EP0_OUT_WAIT_GADGET:
738 dwc->ep0state = EP0_OUT_WAIT_NRDY;
739 break;
740
741 case EP0_IN_WAIT_NRDY:
742 case EP0_OUT_WAIT_NRDY:
743 dwc3_ep0_do_setup_status(dwc, event);
744 break;
745
746 case EP0_IDLE:
747 case EP0_IN_STATUS_PHASE:
748 case EP0_OUT_STATUS_PHASE:
749 case EP0_IN_DATA_PHASE:
750 case EP0_OUT_DATA_PHASE:
751 case EP0_UNCONNECTED:
752 case EP0_STALL:
753 break;
754 }
755}
756
757void dwc3_ep0_interrupt(struct dwc3 *dwc,
758 const const struct dwc3_event_depevt *event)
759{
760 u8 epnum = event->endpoint_number;
761
762 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
763 dwc3_ep_event_string(event->endpoint_event),
764 epnum, (epnum & 1) ? "in" : "out",
765 dwc3_ep0_state_string(dwc->ep0state));
766
767 switch (event->endpoint_event) {
768 case DWC3_DEPEVT_XFERCOMPLETE:
769 dwc3_ep0_xfer_complete(dwc, event);
770 break;
771
772 case DWC3_DEPEVT_XFERNOTREADY:
773 dwc3_ep0_xfernotready(dwc, event);
774 break;
775
776 case DWC3_DEPEVT_XFERINPROGRESS:
777 case DWC3_DEPEVT_RXTXFIFOEVT:
778 case DWC3_DEPEVT_STREAMEVT:
779 case DWC3_DEPEVT_EPCMDCMPLT:
780 break;
781 }
782}
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
new file mode 100644
index 00000000000..de5f0afa890
--- /dev/null
+++ b/drivers/usb/dwc3/gadget.c
@@ -0,0 +1,2063 @@
1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#include <linux/kernel.h>
41#include <linux/delay.h>
42#include <linux/slab.h>
43#include <linux/spinlock.h>
44#include <linux/platform_device.h>
45#include <linux/pm_runtime.h>
46#include <linux/interrupt.h>
47#include <linux/io.h>
48#include <linux/list.h>
49#include <linux/dma-mapping.h>
50
51#include <linux/usb/ch9.h>
52#include <linux/usb/gadget.h>
53
54#include "core.h"
55#include "gadget.h"
56#include "io.h"
57
58#define DMA_ADDR_INVALID (~(dma_addr_t)0)
59
60void dwc3_map_buffer_to_dma(struct dwc3_request *req)
61{
62 struct dwc3 *dwc = req->dep->dwc;
63
64 if (req->request.dma == DMA_ADDR_INVALID) {
65 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
66 req->request.length, req->direction
67 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
68 req->mapped = true;
69 } else {
70 dma_sync_single_for_device(dwc->dev, req->request.dma,
71 req->request.length, req->direction
72 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
73 req->mapped = false;
74 }
75}
76
77void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
78{
79 struct dwc3 *dwc = req->dep->dwc;
80
81 if (req->mapped) {
82 dma_unmap_single(dwc->dev, req->request.dma,
83 req->request.length, req->direction
84 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
85 req->mapped = 0;
86 } else {
87 dma_sync_single_for_cpu(dwc->dev, req->request.dma,
88 req->request.length, req->direction
89 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
90 }
91}
92
93void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
94 int status)
95{
96 struct dwc3 *dwc = dep->dwc;
97
98 if (req->queued) {
99 dep->busy_slot++;
100 /*
101 * Skip LINK TRB. We can't use req->trb and check for
102 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
103 * completed (not the LINK TRB).
104 */
105 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
106 usb_endpoint_xfer_isoc(dep->desc))
107 dep->busy_slot++;
108 }
109 list_del(&req->list);
110
111 if (req->request.status == -EINPROGRESS)
112 req->request.status = status;
113
114 dwc3_unmap_buffer_from_dma(req);
115
116 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
117 req, dep->name, req->request.actual,
118 req->request.length, status);
119
120 spin_unlock(&dwc->lock);
121 req->request.complete(&req->dep->endpoint, &req->request);
122 spin_lock(&dwc->lock);
123}
124
125static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
126{
127 switch (cmd) {
128 case DWC3_DEPCMD_DEPSTARTCFG:
129 return "Start New Configuration";
130 case DWC3_DEPCMD_ENDTRANSFER:
131 return "End Transfer";
132 case DWC3_DEPCMD_UPDATETRANSFER:
133 return "Update Transfer";
134 case DWC3_DEPCMD_STARTTRANSFER:
135 return "Start Transfer";
136 case DWC3_DEPCMD_CLEARSTALL:
137 return "Clear Stall";
138 case DWC3_DEPCMD_SETSTALL:
139 return "Set Stall";
140 case DWC3_DEPCMD_GETSEQNUMBER:
141 return "Get Data Sequence Number";
142 case DWC3_DEPCMD_SETTRANSFRESOURCE:
143 return "Set Endpoint Transfer Resource";
144 case DWC3_DEPCMD_SETEPCONFIG:
145 return "Set Endpoint Configuration";
146 default:
147 return "UNKNOWN command";
148 }
149}
150
151int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
152 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
153{
154 struct dwc3_ep *dep = dwc->eps[ep];
155 unsigned long timeout = 500;
156 u32 reg;
157
158 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
159 dep->name,
160 dwc3_gadget_ep_cmd_string(cmd), params->param0.raw,
161 params->param1.raw, params->param2.raw);
162
163 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0.raw);
164 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1.raw);
165 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2.raw);
166
167 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
168 do {
169 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
170 if (!(reg & DWC3_DEPCMD_CMDACT)) {
171 dev_vdbg(dwc->dev, "CMD Compl Status %d DEPCMD %04x\n",
172 ((reg & 0xf000) >> 12), reg);
173 return 0;
174 }
175
176 /*
177 * XXX Figure out a sane timeout here. 500ms is way too much.
178 * We can't sleep here, because it is also called from
179 * interrupt context.
180 */
181 timeout--;
182 if (!timeout)
183 return -ETIMEDOUT;
184
185 mdelay(1);
186 } while (1);
187}
188
189static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
190 struct dwc3_trb_hw *trb)
191{
192 u32 offset = trb - dep->trb_pool;
193
194 return dep->trb_pool_dma + offset;
195}
196
197static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
198{
199 struct dwc3 *dwc = dep->dwc;
200
201 if (dep->trb_pool)
202 return 0;
203
204 if (dep->number == 0 || dep->number == 1)
205 return 0;
206
207 dep->trb_pool = dma_alloc_coherent(dwc->dev,
208 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
209 &dep->trb_pool_dma, GFP_KERNEL);
210 if (!dep->trb_pool) {
211 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
212 dep->name);
213 return -ENOMEM;
214 }
215
216 return 0;
217}
218
219static void dwc3_free_trb_pool(struct dwc3_ep *dep)
220{
221 struct dwc3 *dwc = dep->dwc;
222
223 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
224 dep->trb_pool, dep->trb_pool_dma);
225
226 dep->trb_pool = NULL;
227 dep->trb_pool_dma = 0;
228}
229
230static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
231{
232 struct dwc3_gadget_ep_cmd_params params;
233 u32 cmd;
234
235 memset(&params, 0x00, sizeof(params));
236
237 if (dep->number != 1) {
238 cmd = DWC3_DEPCMD_DEPSTARTCFG;
239 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
240 if (dep->number > 1)
241 cmd |= DWC3_DEPCMD_PARAM(2);
242
243 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
244 }
245
246 return 0;
247}
248
249static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
250 const struct usb_endpoint_descriptor *desc)
251{
252 struct dwc3_gadget_ep_cmd_params params;
253
254 memset(&params, 0x00, sizeof(params));
255
256 params.param0.depcfg.ep_type = usb_endpoint_type(desc);
257 params.param0.depcfg.max_packet_size =
258 le16_to_cpu(desc->wMaxPacketSize);
259
260 params.param1.depcfg.xfer_complete_enable = true;
261 params.param1.depcfg.xfer_not_ready_enable = true;
262
263 if (usb_endpoint_xfer_isoc(desc))
264 params.param1.depcfg.xfer_in_progress_enable = true;
265
266 /*
267 * We are doing 1:1 mapping for endpoints, meaning
268 * Physical Endpoints 2 maps to Logical Endpoint 2 and
269 * so on. We consider the direction bit as part of the physical
270 * endpoint number. So USB endpoint 0x81 is 0x03.
271 */
272 params.param1.depcfg.ep_number = dep->number;
273
274 /*
275 * We must use the lower 16 TX FIFOs even though
276 * HW might have more
277 */
278 if (dep->direction)
279 params.param0.depcfg.fifo_number = dep->number >> 1;
280
281 if (desc->bInterval) {
282 params.param1.depcfg.binterval_m1 = desc->bInterval - 1;
283 dep->interval = 1 << (desc->bInterval - 1);
284 }
285
286 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
287 DWC3_DEPCMD_SETEPCONFIG, &params);
288}
289
290static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
291{
292 struct dwc3_gadget_ep_cmd_params params;
293
294 memset(&params, 0x00, sizeof(params));
295
296 params.param0.depxfercfg.number_xfer_resources = 1;
297
298 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
299 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
300}
301
302/**
303 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
304 * @dep: endpoint to be initialized
305 * @desc: USB Endpoint Descriptor
306 *
307 * Caller should take care of locking
308 */
309static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
310 const struct usb_endpoint_descriptor *desc)
311{
312 struct dwc3 *dwc = dep->dwc;
313 u32 reg;
314 int ret = -ENOMEM;
315
316 if (!(dep->flags & DWC3_EP_ENABLED)) {
317 ret = dwc3_gadget_start_config(dwc, dep);
318 if (ret)
319 return ret;
320 }
321
322 ret = dwc3_gadget_set_ep_config(dwc, dep, desc);
323 if (ret)
324 return ret;
325
326 if (!(dep->flags & DWC3_EP_ENABLED)) {
327 struct dwc3_trb_hw *trb_st_hw;
328 struct dwc3_trb_hw *trb_link_hw;
329 struct dwc3_trb trb_link;
330
331 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
332 if (ret)
333 return ret;
334
335 dep->desc = desc;
336 dep->type = usb_endpoint_type(desc);
337 dep->flags |= DWC3_EP_ENABLED;
338
339 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
340 reg |= DWC3_DALEPENA_EP(dep->number);
341 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
342
343 if (!usb_endpoint_xfer_isoc(desc))
344 return 0;
345
346 memset(&trb_link, 0, sizeof(trb_link));
347
348 /* Link TRB for ISOC. The HWO but is never reset */
349 trb_st_hw = &dep->trb_pool[0];
350
351 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
352 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
353 trb_link.hwo = true;
354
355 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
356 dwc3_trb_to_hw(&trb_link, trb_link_hw);
357 }
358
359 return 0;
360}
361
362static void dwc3_gadget_nuke_reqs(struct dwc3_ep *dep, const int status)
363{
364 struct dwc3_request *req;
365
366 while (!list_empty(&dep->request_list)) {
367 req = next_request(&dep->request_list);
368
369 dwc3_gadget_giveback(dep, req, status);
370 }
371 /* nuke queued TRBs as well on command complete */
372 dep->flags |= DWC3_EP_WILL_SHUTDOWN;
373}
374
375/**
376 * __dwc3_gadget_ep_disable - Disables a HW endpoint
377 * @dep: the endpoint to disable
378 *
379 * Caller should take care of locking
380 */
381static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
382static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
383{
384 struct dwc3 *dwc = dep->dwc;
385 u32 reg;
386
387 dep->flags &= ~DWC3_EP_ENABLED;
388 dwc3_stop_active_transfer(dwc, dep->number);
389 dwc3_gadget_nuke_reqs(dep, -ESHUTDOWN);
390
391 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
392 reg &= ~DWC3_DALEPENA_EP(dep->number);
393 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
394
395 dep->desc = NULL;
396 dep->type = 0;
397
398 return 0;
399}
400
401/* -------------------------------------------------------------------------- */
402
403static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
404 const struct usb_endpoint_descriptor *desc)
405{
406 return -EINVAL;
407}
408
409static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
410{
411 return -EINVAL;
412}
413
414/* -------------------------------------------------------------------------- */
415
416static int dwc3_gadget_ep_enable(struct usb_ep *ep,
417 const struct usb_endpoint_descriptor *desc)
418{
419 struct dwc3_ep *dep;
420 struct dwc3 *dwc;
421 unsigned long flags;
422 int ret;
423
424 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
425 pr_debug("dwc3: invalid parameters\n");
426 return -EINVAL;
427 }
428
429 if (!desc->wMaxPacketSize) {
430 pr_debug("dwc3: missing wMaxPacketSize\n");
431 return -EINVAL;
432 }
433
434 dep = to_dwc3_ep(ep);
435 dwc = dep->dwc;
436
437 switch (usb_endpoint_type(desc)) {
438 case USB_ENDPOINT_XFER_CONTROL:
439 strncat(dep->name, "-control", sizeof(dep->name));
440 break;
441 case USB_ENDPOINT_XFER_ISOC:
442 strncat(dep->name, "-isoc", sizeof(dep->name));
443 break;
444 case USB_ENDPOINT_XFER_BULK:
445 strncat(dep->name, "-bulk", sizeof(dep->name));
446 break;
447 case USB_ENDPOINT_XFER_INT:
448 strncat(dep->name, "-int", sizeof(dep->name));
449 break;
450 default:
451 dev_err(dwc->dev, "invalid endpoint transfer type\n");
452 }
453
454 if (dep->flags & DWC3_EP_ENABLED) {
455 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
456 dep->name);
457 return 0;
458 }
459
460 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
461
462 spin_lock_irqsave(&dwc->lock, flags);
463 ret = __dwc3_gadget_ep_enable(dep, desc);
464 spin_unlock_irqrestore(&dwc->lock, flags);
465
466 return ret;
467}
468
469static int dwc3_gadget_ep_disable(struct usb_ep *ep)
470{
471 struct dwc3_ep *dep;
472 struct dwc3 *dwc;
473 unsigned long flags;
474 int ret;
475
476 if (!ep) {
477 pr_debug("dwc3: invalid parameters\n");
478 return -EINVAL;
479 }
480
481 dep = to_dwc3_ep(ep);
482 dwc = dep->dwc;
483
484 if (!(dep->flags & DWC3_EP_ENABLED)) {
485 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
486 dep->name);
487 return 0;
488 }
489
490 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
491 dep->number >> 1,
492 (dep->number & 1) ? "in" : "out");
493
494 spin_lock_irqsave(&dwc->lock, flags);
495 ret = __dwc3_gadget_ep_disable(dep);
496 spin_unlock_irqrestore(&dwc->lock, flags);
497
498 return ret;
499}
500
501static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
502 gfp_t gfp_flags)
503{
504 struct dwc3_request *req;
505 struct dwc3_ep *dep = to_dwc3_ep(ep);
506 struct dwc3 *dwc = dep->dwc;
507
508 req = kzalloc(sizeof(*req), gfp_flags);
509 if (!req) {
510 dev_err(dwc->dev, "not enough memory\n");
511 return NULL;
512 }
513
514 req->epnum = dep->number;
515 req->dep = dep;
516 req->request.dma = DMA_ADDR_INVALID;
517
518 return &req->request;
519}
520
521static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
522 struct usb_request *request)
523{
524 struct dwc3_request *req = to_dwc3_request(request);
525
526 kfree(req);
527}
528
529/*
530 * dwc3_prepare_trbs - setup TRBs from requests
531 * @dep: endpoint for which requests are being prepared
532 * @starting: true if the endpoint is idle and no requests are queued.
533 *
534 * The functions goes through the requests list and setups TRBs for the
535 * transfers. The functions returns once there are not more TRBs available or
536 * it run out of requests.
537 */
538static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
539 bool starting)
540{
541 struct dwc3_request *req, *n, *ret = NULL;
542 struct dwc3_trb_hw *trb_hw;
543 struct dwc3_trb trb;
544 u32 trbs_left;
545
546 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
547
548 /* the first request must not be queued */
549 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
550 /*
551 * if busy & slot are equal than it is either full or empty. If we are
552 * starting to proceed requests then we are empty. Otherwise we ar
553 * full and don't do anything
554 */
555 if (!trbs_left) {
556 if (!starting)
557 return NULL;
558 trbs_left = DWC3_TRB_NUM;
559 /*
560 * In case we start from scratch, we queue the ISOC requests
561 * starting from slot 1. This is done because we use ring
562 * buffer and have no LST bit to stop us. Instead, we place
563 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
564 * after the first request so we start at slot 1 and have
565 * 7 requests proceed before we hit the first IOC.
566 * Other transfer types don't use the ring buffer and are
567 * processed from the first TRB until the last one. Since we
568 * don't wrap around we have to start at the beginning.
569 */
570 if (usb_endpoint_xfer_isoc(dep->desc)) {
571 dep->busy_slot = 1;
572 dep->free_slot = 1;
573 } else {
574 dep->busy_slot = 0;
575 dep->free_slot = 0;
576 }
577 }
578
579 /* The last TRB is a link TRB, not used for xfer */
580 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
581 return NULL;
582
583 list_for_each_entry_safe(req, n, &dep->request_list, list) {
584 unsigned int last_one = 0;
585 unsigned int cur_slot;
586
587 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
588 cur_slot = dep->free_slot;
589 dep->free_slot++;
590
591 /* Skip the LINK-TRB on ISOC */
592 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
593 usb_endpoint_xfer_isoc(dep->desc))
594 continue;
595
596 dwc3_gadget_move_request_queued(req);
597 memset(&trb, 0, sizeof(trb));
598 trbs_left--;
599
600 /* Is our TRB pool empty? */
601 if (!trbs_left)
602 last_one = 1;
603 /* Is this the last request? */
604 if (list_empty(&dep->request_list))
605 last_one = 1;
606
607 /*
608 * FIXME we shouldn't need to set LST bit always but we are
609 * facing some weird problem with the Hardware where it doesn't
610 * complete even though it has been previously started.
611 *
612 * While we're debugging the problem, as a workaround to
613 * multiple TRBs handling, use only one TRB at a time.
614 */
615 last_one = 1;
616
617 req->trb = trb_hw;
618 if (!ret)
619 ret = req;
620
621 trb.bplh = req->request.dma;
622
623 if (usb_endpoint_xfer_isoc(dep->desc)) {
624 trb.isp_imi = true;
625 trb.csp = true;
626 } else {
627 trb.lst = last_one;
628 }
629
630 switch (usb_endpoint_type(dep->desc)) {
631 case USB_ENDPOINT_XFER_CONTROL:
632 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
633 break;
634
635 case USB_ENDPOINT_XFER_ISOC:
636 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS;
637
638 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
639 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
640 trb.ioc = last_one;
641 break;
642
643 case USB_ENDPOINT_XFER_BULK:
644 case USB_ENDPOINT_XFER_INT:
645 trb.trbctl = DWC3_TRBCTL_NORMAL;
646 break;
647 default:
648 /*
649 * This is only possible with faulty memory because we
650 * checked it already :)
651 */
652 BUG();
653 }
654
655 trb.length = req->request.length;
656 trb.hwo = true;
657
658 dwc3_trb_to_hw(&trb, trb_hw);
659 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
660
661 if (last_one)
662 break;
663 }
664
665 return ret;
666}
667
668static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
669 int start_new)
670{
671 struct dwc3_gadget_ep_cmd_params params;
672 struct dwc3_request *req;
673 struct dwc3 *dwc = dep->dwc;
674 int ret;
675 u32 cmd;
676
677 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
678 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
679 return -EBUSY;
680 }
681 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
682
683 /*
684 * If we are getting here after a short-out-packet we don't enqueue any
685 * new requests as we try to set the IOC bit only on the last request.
686 */
687 if (start_new) {
688 if (list_empty(&dep->req_queued))
689 dwc3_prepare_trbs(dep, start_new);
690
691 /* req points to the first request which will be sent */
692 req = next_request(&dep->req_queued);
693 } else {
694 /*
695 * req points to the first request where HWO changed
696 * from 0 to 1
697 */
698 req = dwc3_prepare_trbs(dep, start_new);
699 }
700 if (!req) {
701 dep->flags |= DWC3_EP_PENDING_REQUEST;
702 return 0;
703 }
704
705 memset(&params, 0, sizeof(params));
706 params.param0.depstrtxfer.transfer_desc_addr_high =
707 upper_32_bits(req->trb_dma);
708 params.param1.depstrtxfer.transfer_desc_addr_low =
709 lower_32_bits(req->trb_dma);
710
711 if (start_new)
712 cmd = DWC3_DEPCMD_STARTTRANSFER;
713 else
714 cmd = DWC3_DEPCMD_UPDATETRANSFER;
715
716 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
717 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
718 if (ret < 0) {
719 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
720
721 /*
722 * FIXME we need to iterate over the list of requests
723 * here and stop, unmap, free and del each of the linked
724 * requests instead of we do now.
725 */
726 dwc3_unmap_buffer_from_dma(req);
727 list_del(&req->list);
728 return ret;
729 }
730
731 dep->flags |= DWC3_EP_BUSY;
732 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
733 dep->number);
734 if (!dep->res_trans_idx)
735 printk_once(KERN_ERR "%s() res_trans_idx is invalid\n", __func__);
736 return 0;
737}
738
739static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
740{
741 req->request.actual = 0;
742 req->request.status = -EINPROGRESS;
743 req->direction = dep->direction;
744 req->epnum = dep->number;
745
746 /*
747 * We only add to our list of requests now and
748 * start consuming the list once we get XferNotReady
749 * IRQ.
750 *
751 * That way, we avoid doing anything that we don't need
752 * to do now and defer it until the point we receive a
753 * particular token from the Host side.
754 *
755 * This will also avoid Host cancelling URBs due to too
756 * many NACKs.
757 */
758 dwc3_map_buffer_to_dma(req);
759 list_add_tail(&req->list, &dep->request_list);
760
761 /*
762 * There is one special case: XferNotReady with
763 * empty list of requests. We need to kick the
764 * transfer here in that situation, otherwise
765 * we will be NAKing forever.
766 *
767 * If we get XferNotReady before gadget driver
768 * has a chance to queue a request, we will ACK
769 * the IRQ but won't be able to receive the data
770 * until the next request is queued. The following
771 * code is handling exactly that.
772 */
773 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
774 int ret;
775 int start_trans;
776
777 start_trans = 1;
778 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
779 dep->flags & DWC3_EP_BUSY)
780 start_trans = 0;
781
782 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
783 if (ret && ret != -EBUSY) {
784 struct dwc3 *dwc = dep->dwc;
785
786 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
787 dep->name);
788 }
789 };
790
791 return 0;
792}
793
794static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
795 gfp_t gfp_flags)
796{
797 struct dwc3_request *req = to_dwc3_request(request);
798 struct dwc3_ep *dep = to_dwc3_ep(ep);
799 struct dwc3 *dwc = dep->dwc;
800
801 unsigned long flags;
802
803 int ret;
804
805 if (!dep->desc) {
806 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
807 request, ep->name);
808 return -ESHUTDOWN;
809 }
810
811 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
812 request, ep->name, request->length);
813
814 spin_lock_irqsave(&dwc->lock, flags);
815 ret = __dwc3_gadget_ep_queue(dep, req);
816 spin_unlock_irqrestore(&dwc->lock, flags);
817
818 return ret;
819}
820
821static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
822 struct usb_request *request)
823{
824 struct dwc3_request *req = to_dwc3_request(request);
825 struct dwc3_request *r = NULL;
826
827 struct dwc3_ep *dep = to_dwc3_ep(ep);
828 struct dwc3 *dwc = dep->dwc;
829
830 unsigned long flags;
831 int ret = 0;
832
833 spin_lock_irqsave(&dwc->lock, flags);
834
835 list_for_each_entry(r, &dep->request_list, list) {
836 if (r == req)
837 break;
838 }
839
840 if (r != req) {
841 list_for_each_entry(r, &dep->req_queued, list) {
842 if (r == req)
843 break;
844 }
845 if (r == req) {
846 /* wait until it is processed */
847 dwc3_stop_active_transfer(dwc, dep->number);
848 goto out0;
849 }
850 dev_err(dwc->dev, "request %p was not queued to %s\n",
851 request, ep->name);
852 ret = -EINVAL;
853 goto out0;
854 }
855
856 /* giveback the request */
857 dwc3_gadget_giveback(dep, req, -ECONNRESET);
858
859out0:
860 spin_unlock_irqrestore(&dwc->lock, flags);
861
862 return ret;
863}
864
865int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
866{
867 struct dwc3_gadget_ep_cmd_params params;
868 struct dwc3 *dwc = dep->dwc;
869 int ret;
870
871 memset(&params, 0x00, sizeof(params));
872
873 if (value) {
874 if (dep->number == 0 || dep->number == 1)
875 dwc->ep0state = EP0_STALL;
876
877 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
878 DWC3_DEPCMD_SETSTALL, &params);
879 if (ret)
880 dev_err(dwc->dev, "failed to %s STALL on %s\n",
881 value ? "set" : "clear",
882 dep->name);
883 else
884 dep->flags |= DWC3_EP_STALL;
885 } else {
886 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
887 DWC3_DEPCMD_CLEARSTALL, &params);
888 if (ret)
889 dev_err(dwc->dev, "failed to %s STALL on %s\n",
890 value ? "set" : "clear",
891 dep->name);
892 else
893 dep->flags &= ~DWC3_EP_STALL;
894 }
895 return ret;
896}
897
898static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
899{
900 struct dwc3_ep *dep = to_dwc3_ep(ep);
901 struct dwc3 *dwc = dep->dwc;
902
903 unsigned long flags;
904
905 int ret;
906
907 spin_lock_irqsave(&dwc->lock, flags);
908
909 if (usb_endpoint_xfer_isoc(dep->desc)) {
910 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
911 ret = -EINVAL;
912 goto out;
913 }
914
915 ret = __dwc3_gadget_ep_set_halt(dep, value);
916out:
917 spin_unlock_irqrestore(&dwc->lock, flags);
918
919 return ret;
920}
921
922static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
923{
924 struct dwc3_ep *dep = to_dwc3_ep(ep);
925
926 dep->flags |= DWC3_EP_WEDGE;
927
928 return usb_ep_set_halt(ep);
929}
930
931/* -------------------------------------------------------------------------- */
932
933static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
934 .bLength = USB_DT_ENDPOINT_SIZE,
935 .bDescriptorType = USB_DT_ENDPOINT,
936 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
937};
938
939static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
940 .enable = dwc3_gadget_ep0_enable,
941 .disable = dwc3_gadget_ep0_disable,
942 .alloc_request = dwc3_gadget_ep_alloc_request,
943 .free_request = dwc3_gadget_ep_free_request,
944 .queue = dwc3_gadget_ep0_queue,
945 .dequeue = dwc3_gadget_ep_dequeue,
946 .set_halt = dwc3_gadget_ep_set_halt,
947 .set_wedge = dwc3_gadget_ep_set_wedge,
948};
949
950static const struct usb_ep_ops dwc3_gadget_ep_ops = {
951 .enable = dwc3_gadget_ep_enable,
952 .disable = dwc3_gadget_ep_disable,
953 .alloc_request = dwc3_gadget_ep_alloc_request,
954 .free_request = dwc3_gadget_ep_free_request,
955 .queue = dwc3_gadget_ep_queue,
956 .dequeue = dwc3_gadget_ep_dequeue,
957 .set_halt = dwc3_gadget_ep_set_halt,
958 .set_wedge = dwc3_gadget_ep_set_wedge,
959};
960
961/* -------------------------------------------------------------------------- */
962
963static int dwc3_gadget_get_frame(struct usb_gadget *g)
964{
965 struct dwc3 *dwc = gadget_to_dwc(g);
966 u32 reg;
967
968 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
969 return DWC3_DSTS_SOFFN(reg);
970}
971
972static int dwc3_gadget_wakeup(struct usb_gadget *g)
973{
974 struct dwc3 *dwc = gadget_to_dwc(g);
975
976 unsigned long timeout;
977 unsigned long flags;
978
979 u32 reg;
980
981 int ret = 0;
982
983 u8 link_state;
984 u8 speed;
985
986 spin_lock_irqsave(&dwc->lock, flags);
987
988 /*
989 * According to the Databook Remote wakeup request should
990 * be issued only when the device is in early suspend state.
991 *
992 * We can check that via USB Link State bits in DSTS register.
993 */
994 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
995
996 speed = reg & DWC3_DSTS_CONNECTSPD;
997 if (speed == DWC3_DSTS_SUPERSPEED) {
998 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
999 ret = -EINVAL;
1000 goto out;
1001 }
1002
1003 link_state = DWC3_DSTS_USBLNKST(reg);
1004
1005 switch (link_state) {
1006 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1007 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1008 break;
1009 default:
1010 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1011 link_state);
1012 ret = -EINVAL;
1013 goto out;
1014 }
1015
1016 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1017
1018 /*
1019 * Switch link state to Recovery. In HS/FS/LS this means
1020 * RemoteWakeup Request
1021 */
1022 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1023 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1024
1025 /* wait for at least 2000us */
1026 usleep_range(2000, 2500);
1027
1028 /* write zeroes to Link Change Request */
1029 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1030 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1031
1032 /* pool until Link State change to ON */
1033 timeout = jiffies + msecs_to_jiffies(100);
1034
1035 while (!(time_after(jiffies, timeout))) {
1036 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1037
1038 /* in HS, means ON */
1039 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1040 break;
1041 }
1042
1043 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1044 dev_err(dwc->dev, "failed to send remote wakeup\n");
1045 ret = -EINVAL;
1046 }
1047
1048out:
1049 spin_unlock_irqrestore(&dwc->lock, flags);
1050
1051 return ret;
1052}
1053
1054static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1055 int is_selfpowered)
1056{
1057 struct dwc3 *dwc = gadget_to_dwc(g);
1058
1059 dwc->is_selfpowered = !!is_selfpowered;
1060
1061 return 0;
1062}
1063
1064static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1065{
1066 u32 reg;
1067 unsigned long timeout = 500;
1068
1069 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1070 if (is_on)
1071 reg |= DWC3_DCTL_RUN_STOP;
1072 else
1073 reg &= ~DWC3_DCTL_RUN_STOP;
1074
1075 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1076
1077 do {
1078 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1079 if (is_on) {
1080 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1081 break;
1082 } else {
1083 if (reg & DWC3_DSTS_DEVCTRLHLT)
1084 break;
1085 }
1086 /*
1087 * XXX reduce the 500ms delay
1088 */
1089 timeout--;
1090 if (!timeout)
1091 break;
1092 mdelay(1);
1093 } while (1);
1094
1095 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1096 dwc->gadget_driver
1097 ? dwc->gadget_driver->function : "no-function",
1098 is_on ? "connect" : "disconnect");
1099}
1100
1101static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1102{
1103 struct dwc3 *dwc = gadget_to_dwc(g);
1104 unsigned long flags;
1105
1106 is_on = !!is_on;
1107
1108 spin_lock_irqsave(&dwc->lock, flags);
1109 dwc3_gadget_run_stop(dwc, is_on);
1110 spin_unlock_irqrestore(&dwc->lock, flags);
1111
1112 return 0;
1113}
1114
1115static int dwc3_gadget_start(struct usb_gadget *g,
1116 struct usb_gadget_driver *driver)
1117{
1118 struct dwc3 *dwc = gadget_to_dwc(g);
1119 struct dwc3_ep *dep;
1120 unsigned long flags;
1121 int ret = 0;
1122 u32 reg;
1123
1124 spin_lock_irqsave(&dwc->lock, flags);
1125
1126 if (dwc->gadget_driver) {
1127 dev_err(dwc->dev, "%s is already bound to %s\n",
1128 dwc->gadget.name,
1129 dwc->gadget_driver->driver.name);
1130 ret = -EBUSY;
1131 goto err0;
1132 }
1133
1134 dwc->gadget_driver = driver;
1135 dwc->gadget.dev.driver = &driver->driver;
1136
1137 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1138
1139 /*
1140 * REVISIT: power down scale might be different
1141 * depending on PHY used, need to pass that via platform_data
1142 */
1143 reg |= DWC3_GCTL_PWRDNSCALE(0x61a)
1144 | DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE);
1145 reg &= ~DWC3_GCTL_DISSCRAMBLE;
1146
1147 /*
1148 * WORKAROUND: DWC3 revisions <1.90a have a bug
1149 * when The device fails to connect at SuperSpeed
1150 * and falls back to high-speed mode which causes
1151 * the device to enter in a Connect/Disconnect loop
1152 */
1153 if (dwc->revision < DWC3_REVISION_190A)
1154 reg |= DWC3_GCTL_U2RSTECN;
1155
1156 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1157
1158 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1159 reg &= ~(DWC3_DCFG_SPEED_MASK);
1160 reg |= DWC3_DCFG_SUPERSPEED;
1161 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1162
1163 /* Start with SuperSpeed Default */
1164 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1165
1166 dep = dwc->eps[0];
1167 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1168 if (ret) {
1169 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1170 goto err0;
1171 }
1172
1173 dep = dwc->eps[1];
1174 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1175 if (ret) {
1176 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1177 goto err1;
1178 }
1179
1180 /* begin to receive SETUP packets */
1181 dwc->ep0state = EP0_IDLE;
1182 dwc3_ep0_out_start(dwc);
1183
1184 spin_unlock_irqrestore(&dwc->lock, flags);
1185
1186 return 0;
1187
1188err1:
1189 __dwc3_gadget_ep_disable(dwc->eps[0]);
1190
1191err0:
1192 spin_unlock_irqrestore(&dwc->lock, flags);
1193
1194 return ret;
1195}
1196
1197static int dwc3_gadget_stop(struct usb_gadget *g,
1198 struct usb_gadget_driver *driver)
1199{
1200 struct dwc3 *dwc = gadget_to_dwc(g);
1201 unsigned long flags;
1202
1203 spin_lock_irqsave(&dwc->lock, flags);
1204
1205 __dwc3_gadget_ep_disable(dwc->eps[0]);
1206 __dwc3_gadget_ep_disable(dwc->eps[1]);
1207
1208 dwc->gadget_driver = NULL;
1209 dwc->gadget.dev.driver = NULL;
1210
1211 spin_unlock_irqrestore(&dwc->lock, flags);
1212
1213 return 0;
1214}
1215static const struct usb_gadget_ops dwc3_gadget_ops = {
1216 .get_frame = dwc3_gadget_get_frame,
1217 .wakeup = dwc3_gadget_wakeup,
1218 .set_selfpowered = dwc3_gadget_set_selfpowered,
1219 .pullup = dwc3_gadget_pullup,
1220 .udc_start = dwc3_gadget_start,
1221 .udc_stop = dwc3_gadget_stop,
1222};
1223
1224/* -------------------------------------------------------------------------- */
1225
1226static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1227{
1228 struct dwc3_ep *dep;
1229 u8 epnum;
1230
1231 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1232
1233 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1234 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1235 if (!dep) {
1236 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1237 epnum);
1238 return -ENOMEM;
1239 }
1240
1241 dep->dwc = dwc;
1242 dep->number = epnum;
1243 dwc->eps[epnum] = dep;
1244
1245 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1246 (epnum & 1) ? "in" : "out");
1247 dep->endpoint.name = dep->name;
1248 dep->direction = (epnum & 1);
1249
1250 if (epnum == 0 || epnum == 1) {
1251 dep->endpoint.maxpacket = 512;
1252 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1253 if (!epnum)
1254 dwc->gadget.ep0 = &dep->endpoint;
1255 } else {
1256 int ret;
1257
1258 dep->endpoint.maxpacket = 1024;
1259 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1260 list_add_tail(&dep->endpoint.ep_list,
1261 &dwc->gadget.ep_list);
1262
1263 ret = dwc3_alloc_trb_pool(dep);
1264 if (ret) {
1265 dev_err(dwc->dev, "%s: failed to allocate TRB pool\n", dep->name);
1266 return ret;
1267 }
1268 }
1269 INIT_LIST_HEAD(&dep->request_list);
1270 INIT_LIST_HEAD(&dep->req_queued);
1271 }
1272
1273 return 0;
1274}
1275
1276static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1277{
1278 struct dwc3_ep *dep;
1279 u8 epnum;
1280
1281 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1282 dep = dwc->eps[epnum];
1283 dwc3_free_trb_pool(dep);
1284
1285 if (epnum != 0 && epnum != 1)
1286 list_del(&dep->endpoint.ep_list);
1287
1288 kfree(dep);
1289 }
1290}
1291
1292static void dwc3_gadget_release(struct device *dev)
1293{
1294 dev_dbg(dev, "%s\n", __func__);
1295}
1296
1297/* -------------------------------------------------------------------------- */
1298static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1299 const struct dwc3_event_depevt *event, int status)
1300{
1301 struct dwc3_request *req;
1302 struct dwc3_trb trb;
1303 unsigned int count;
1304 unsigned int s_pkt = 0;
1305
1306 do {
1307 req = next_request(&dep->req_queued);
1308 if (!req)
1309 break;
1310
1311 dwc3_trb_to_nat(req->trb, &trb);
1312
1313 if (trb.hwo) {
1314 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1315 dep->name, req->trb);
1316 continue;
1317 }
1318 count = trb.length;
1319
1320 if (dep->direction) {
1321 if (count) {
1322 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1323 dep->name);
1324 status = -ECONNRESET;
1325 }
1326 } else {
1327 if (count && (event->status & DEPEVT_STATUS_SHORT))
1328 s_pkt = 1;
1329 }
1330
1331 /*
1332 * We assume here we will always receive the entire data block
1333 * which we should receive. Meaning, if we program RX to
1334 * receive 4K but we receive only 2K, we assume that's all we
1335 * should receive and we simply bounce the request back to the
1336 * gadget driver for further processing.
1337 */
1338 req->request.actual += req->request.length - count;
1339 dwc3_gadget_giveback(dep, req, status);
1340 if (s_pkt)
1341 break;
1342 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1343 break;
1344 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1345 break;
1346 } while (1);
1347
1348 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1349 return 0;
1350 return 1;
1351}
1352
1353static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1354 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1355 int start_new)
1356{
1357 unsigned status = 0;
1358 int clean_busy;
1359
1360 if (event->status & DEPEVT_STATUS_BUSERR)
1361 status = -ECONNRESET;
1362
1363 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1364 if (clean_busy)
1365 dep->flags &= ~DWC3_EP_BUSY;
1366}
1367
1368static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1369 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1370{
1371 u32 uf;
1372
1373 if (list_empty(&dep->request_list)) {
1374 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1375 dep->name);
1376 return;
1377 }
1378
1379 if (event->parameters) {
1380 u32 mask;
1381
1382 mask = ~(dep->interval - 1);
1383 uf = event->parameters & mask;
1384 /* 4 micro frames in the future */
1385 uf += dep->interval * 4;
1386 } else {
1387 uf = 0;
1388 }
1389
1390 __dwc3_gadget_kick_transfer(dep, uf, 1);
1391}
1392
1393static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1394 const struct dwc3_event_depevt *event)
1395{
1396 struct dwc3 *dwc = dep->dwc;
1397 struct dwc3_event_depevt mod_ev = *event;
1398
1399 /*
1400 * We were asked to remove one requests. It is possible that this
1401 * request and a few other were started together and have the same
1402 * transfer index. Since we stopped the complete endpoint we don't
1403 * know how many requests were already completed (and not yet)
1404 * reported and how could be done (later). We purge them all until
1405 * the end of the list.
1406 */
1407 mod_ev.status = DEPEVT_STATUS_LST;
1408 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1409 dep->flags &= ~DWC3_EP_BUSY;
1410 /* pending requets are ignored and are queued on XferNotReady */
1411
1412 if (dep->flags & DWC3_EP_WILL_SHUTDOWN) {
1413 while (!list_empty(&dep->req_queued)) {
1414 struct dwc3_request *req;
1415
1416 req = next_request(&dep->req_queued);
1417 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1418 }
1419 dep->flags &= DWC3_EP_WILL_SHUTDOWN;
1420 }
1421}
1422
1423static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1424 const struct dwc3_event_depevt *event)
1425{
1426 u32 param = event->parameters;
1427 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1428
1429 switch (cmd_type) {
1430 case DWC3_DEPCMD_ENDTRANSFER:
1431 dwc3_process_ep_cmd_complete(dep, event);
1432 break;
1433 case DWC3_DEPCMD_STARTTRANSFER:
1434 dep->res_trans_idx = param & 0x7f;
1435 break;
1436 default:
1437 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1438 __func__, cmd_type);
1439 break;
1440 };
1441}
1442
1443static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1444 const struct dwc3_event_depevt *event)
1445{
1446 struct dwc3_ep *dep;
1447 u8 epnum = event->endpoint_number;
1448
1449 dep = dwc->eps[epnum];
1450
1451 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1452 dwc3_ep_event_string(event->endpoint_event));
1453
1454 if (epnum == 0 || epnum == 1) {
1455 dwc3_ep0_interrupt(dwc, event);
1456 return;
1457 }
1458
1459 switch (event->endpoint_event) {
1460 case DWC3_DEPEVT_XFERCOMPLETE:
1461 if (usb_endpoint_xfer_isoc(dep->desc)) {
1462 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1463 dep->name);
1464 return;
1465 }
1466
1467 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1468 break;
1469 case DWC3_DEPEVT_XFERINPROGRESS:
1470 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1471 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1472 dep->name);
1473 return;
1474 }
1475
1476 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1477 break;
1478 case DWC3_DEPEVT_XFERNOTREADY:
1479 if (usb_endpoint_xfer_isoc(dep->desc)) {
1480 dwc3_gadget_start_isoc(dwc, dep, event);
1481 } else {
1482 int ret;
1483
1484 dev_vdbg(dwc->dev, "%s: reason %s\n",
1485 dep->name, event->status
1486 ? "Transfer Active"
1487 : "Transfer Not Active");
1488
1489 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1490 if (!ret || ret == -EBUSY)
1491 return;
1492
1493 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1494 dep->name);
1495 }
1496
1497 break;
1498 case DWC3_DEPEVT_RXTXFIFOEVT:
1499 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1500 break;
1501 case DWC3_DEPEVT_STREAMEVT:
1502 dev_dbg(dwc->dev, "%s Stream Event\n", dep->name);
1503 break;
1504 case DWC3_DEPEVT_EPCMDCMPLT:
1505 dwc3_ep_cmd_compl(dep, event);
1506 break;
1507 }
1508}
1509
1510static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1511{
1512 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1513 spin_unlock(&dwc->lock);
1514 dwc->gadget_driver->disconnect(&dwc->gadget);
1515 spin_lock(&dwc->lock);
1516 }
1517}
1518
1519static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1520{
1521 struct dwc3_ep *dep;
1522 struct dwc3_gadget_ep_cmd_params params;
1523 u32 cmd;
1524 int ret;
1525
1526 dep = dwc->eps[epnum];
1527
1528 if (dep->res_trans_idx) {
1529 cmd = DWC3_DEPCMD_ENDTRANSFER;
1530 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1531 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1532 memset(&params, 0, sizeof(params));
1533 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1534 WARN_ON_ONCE(ret);
1535 }
1536}
1537
1538static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1539{
1540 u32 epnum;
1541
1542 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1543 struct dwc3_ep *dep;
1544
1545 dep = dwc->eps[epnum];
1546 if (!(dep->flags & DWC3_EP_ENABLED))
1547 continue;
1548
1549 __dwc3_gadget_ep_disable(dep);
1550 }
1551}
1552
1553static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1554{
1555 u32 epnum;
1556
1557 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1558 struct dwc3_ep *dep;
1559 struct dwc3_gadget_ep_cmd_params params;
1560 int ret;
1561
1562 dep = dwc->eps[epnum];
1563
1564 if (!(dep->flags & DWC3_EP_STALL))
1565 continue;
1566
1567 dep->flags &= ~DWC3_EP_STALL;
1568
1569 memset(&params, 0, sizeof(params));
1570 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1571 DWC3_DEPCMD_CLEARSTALL, &params);
1572 WARN_ON_ONCE(ret);
1573 }
1574}
1575
1576static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1577{
1578 dev_vdbg(dwc->dev, "%s\n", __func__);
1579#if 0
1580 XXX
1581 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1582 enable it before we can disable it.
1583
1584 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1585 reg &= ~DWC3_DCTL_INITU1ENA;
1586 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1587
1588 reg &= ~DWC3_DCTL_INITU2ENA;
1589 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1590#endif
1591
1592 dwc3_stop_active_transfers(dwc);
1593 dwc3_disconnect_gadget(dwc);
1594
1595 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1596}
1597
1598static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1599{
1600 u32 reg;
1601
1602 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1603
1604 if (on)
1605 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1606 else
1607 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1608
1609 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1610}
1611
1612static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1613{
1614 u32 reg;
1615
1616 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1617
1618 if (on)
1619 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1620 else
1621 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1622
1623 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1624}
1625
1626static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1627{
1628 u32 reg;
1629
1630 dev_vdbg(dwc->dev, "%s\n", __func__);
1631
1632 /* Enable PHYs */
1633 dwc3_gadget_usb2_phy_power(dwc, true);
1634 dwc3_gadget_usb3_phy_power(dwc, true);
1635
1636 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1637 dwc3_disconnect_gadget(dwc);
1638
1639 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1640 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1641 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1642
1643 dwc3_stop_active_transfers(dwc);
1644 dwc3_clear_stall_all_ep(dwc);
1645
1646 /* Reset device address to zero */
1647 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1648 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1649 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1650
1651 /*
1652 * Wait for RxFifo to drain
1653 *
1654 * REVISIT probably shouldn't wait forever.
1655 * In case Hardware ends up in a screwed up
1656 * case, we error out, notify the user and,
1657 * maybe, WARN() or BUG() but leave the rest
1658 * of the kernel working fine.
1659 *
1660 * REVISIT the below is rather CPU intensive,
1661 * maybe we should read and if it doesn't work
1662 * sleep (not busy wait) for a few useconds.
1663 *
1664 * REVISIT why wait until the RXFIFO is empty anyway?
1665 */
1666 while (!(dwc3_readl(dwc->regs, DWC3_DSTS)
1667 & DWC3_DSTS_RXFIFOEMPTY))
1668 cpu_relax();
1669}
1670
1671static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1672{
1673 u32 reg;
1674 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1675
1676 /*
1677 * We change the clock only at SS but I dunno why I would want to do
1678 * this. Maybe it becomes part of the power saving plan.
1679 */
1680
1681 if (speed != DWC3_DSTS_SUPERSPEED)
1682 return;
1683
1684 /*
1685 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1686 * each time on Connect Done.
1687 */
1688 if (!usb30_clock)
1689 return;
1690
1691 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1692 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1693 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1694}
1695
1696static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1697{
1698 switch (speed) {
1699 case USB_SPEED_SUPER:
1700 dwc3_gadget_usb2_phy_power(dwc, false);
1701 break;
1702 case USB_SPEED_HIGH:
1703 case USB_SPEED_FULL:
1704 case USB_SPEED_LOW:
1705 dwc3_gadget_usb3_phy_power(dwc, false);
1706 break;
1707 }
1708}
1709
1710static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1711{
1712 struct dwc3_gadget_ep_cmd_params params;
1713 struct dwc3_ep *dep;
1714 int ret;
1715 u32 reg;
1716 u8 speed;
1717
1718 dev_vdbg(dwc->dev, "%s\n", __func__);
1719
1720 memset(&params, 0x00, sizeof(params));
1721
1722 dwc->ep0state = EP0_IDLE;
1723 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1724 speed = reg & DWC3_DSTS_CONNECTSPD;
1725 dwc->speed = speed;
1726
1727 dwc3_update_ram_clk_sel(dwc, speed);
1728
1729 switch (speed) {
1730 case DWC3_DCFG_SUPERSPEED:
1731 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1732 dwc->gadget.ep0->maxpacket = 512;
1733 dwc->gadget.speed = USB_SPEED_SUPER;
1734 break;
1735 case DWC3_DCFG_HIGHSPEED:
1736 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1737 dwc->gadget.ep0->maxpacket = 64;
1738 dwc->gadget.speed = USB_SPEED_HIGH;
1739 break;
1740 case DWC3_DCFG_FULLSPEED2:
1741 case DWC3_DCFG_FULLSPEED1:
1742 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1743 dwc->gadget.ep0->maxpacket = 64;
1744 dwc->gadget.speed = USB_SPEED_FULL;
1745 break;
1746 case DWC3_DCFG_LOWSPEED:
1747 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1748 dwc->gadget.ep0->maxpacket = 8;
1749 dwc->gadget.speed = USB_SPEED_LOW;
1750 break;
1751 }
1752
1753 /* Disable unneded PHY */
1754 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1755
1756 dep = dwc->eps[0];
1757 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1758 if (ret) {
1759 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1760 return;
1761 }
1762
1763 dep = dwc->eps[1];
1764 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1765 if (ret) {
1766 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1767 return;
1768 }
1769
1770 /*
1771 * Configure PHY via GUSB3PIPECTLn if required.
1772 *
1773 * Update GTXFIFOSIZn
1774 *
1775 * In both cases reset values should be sufficient.
1776 */
1777}
1778
1779static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
1780{
1781 dev_vdbg(dwc->dev, "%s\n", __func__);
1782
1783 /*
1784 * TODO take core out of low power mode when that's
1785 * implemented.
1786 */
1787
1788 dwc->gadget_driver->resume(&dwc->gadget);
1789}
1790
1791static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
1792 unsigned int evtinfo)
1793{
1794 dev_vdbg(dwc->dev, "%s\n", __func__);
1795
1796 /* The fith bit says SuperSpeed yes or no. */
1797 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
1798}
1799
1800static void dwc3_gadget_interrupt(struct dwc3 *dwc,
1801 const struct dwc3_event_devt *event)
1802{
1803 switch (event->type) {
1804 case DWC3_DEVICE_EVENT_DISCONNECT:
1805 dwc3_gadget_disconnect_interrupt(dwc);
1806 break;
1807 case DWC3_DEVICE_EVENT_RESET:
1808 dwc3_gadget_reset_interrupt(dwc);
1809 break;
1810 case DWC3_DEVICE_EVENT_CONNECT_DONE:
1811 dwc3_gadget_conndone_interrupt(dwc);
1812 break;
1813 case DWC3_DEVICE_EVENT_WAKEUP:
1814 dwc3_gadget_wakeup_interrupt(dwc);
1815 break;
1816 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
1817 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
1818 break;
1819 case DWC3_DEVICE_EVENT_EOPF:
1820 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
1821 break;
1822 case DWC3_DEVICE_EVENT_SOF:
1823 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
1824 break;
1825 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
1826 dev_vdbg(dwc->dev, "Erratic Error\n");
1827 break;
1828 case DWC3_DEVICE_EVENT_CMD_CMPL:
1829 dev_vdbg(dwc->dev, "Command Complete\n");
1830 break;
1831 case DWC3_DEVICE_EVENT_OVERFLOW:
1832 dev_vdbg(dwc->dev, "Overflow\n");
1833 break;
1834 default:
1835 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
1836 }
1837}
1838
1839static void dwc3_process_event_entry(struct dwc3 *dwc,
1840 const union dwc3_event *event)
1841{
1842 /* Endpoint IRQ, handle it and return early */
1843 if (event->type.is_devspec == 0) {
1844 /* depevt */
1845 return dwc3_endpoint_interrupt(dwc, &event->depevt);
1846 }
1847
1848 switch (event->type.type) {
1849 case DWC3_EVENT_TYPE_DEV:
1850 dwc3_gadget_interrupt(dwc, &event->devt);
1851 break;
1852 /* REVISIT what to do with Carkit and I2C events ? */
1853 default:
1854 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
1855 }
1856}
1857
1858static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
1859{
1860 struct dwc3_event_buffer *evt;
1861 int left;
1862 u32 count;
1863
1864 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
1865 count &= DWC3_GEVNTCOUNT_MASK;
1866 if (!count)
1867 return IRQ_NONE;
1868
1869 evt = dwc->ev_buffs[buf];
1870 left = count;
1871
1872 while (left > 0) {
1873 union dwc3_event event;
1874
1875 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
1876 dwc3_process_event_entry(dwc, &event);
1877 /*
1878 * XXX we wrap around correctly to the next entry as almost all
1879 * entries are 4 bytes in size. There is one entry which has 12
1880 * bytes which is a regular entry followed by 8 bytes data. ATM
1881 * I don't know how things are organized if were get next to the
1882 * a boundary so I worry about that once we try to handle that.
1883 */
1884 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
1885 left -= 4;
1886
1887 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
1888 }
1889
1890 return IRQ_HANDLED;
1891}
1892
1893static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
1894{
1895 struct dwc3 *dwc = _dwc;
1896 int i;
1897 irqreturn_t ret = IRQ_NONE;
1898
1899 spin_lock(&dwc->lock);
1900
1901 for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
1902 irqreturn_t status;
1903
1904 status = dwc3_process_event_buf(dwc, i);
1905 if (status == IRQ_HANDLED)
1906 ret = status;
1907 }
1908
1909 spin_unlock(&dwc->lock);
1910
1911 return ret;
1912}
1913
1914/**
1915 * dwc3_gadget_init - Initializes gadget related registers
1916 * @dwc: Pointer to out controller context structure
1917 *
1918 * Returns 0 on success otherwise negative errno.
1919 */
1920int __devinit dwc3_gadget_init(struct dwc3 *dwc)
1921{
1922 u32 reg;
1923 int ret;
1924 int irq;
1925
1926 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
1927 &dwc->ctrl_req_addr, GFP_KERNEL);
1928 if (!dwc->ctrl_req) {
1929 dev_err(dwc->dev, "failed to allocate ctrl request\n");
1930 ret = -ENOMEM;
1931 goto err0;
1932 }
1933
1934 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
1935 &dwc->ep0_trb_addr, GFP_KERNEL);
1936 if (!dwc->ep0_trb) {
1937 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
1938 ret = -ENOMEM;
1939 goto err1;
1940 }
1941
1942 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
1943 sizeof(*dwc->setup_buf) * 2,
1944 &dwc->setup_buf_addr, GFP_KERNEL);
1945 if (!dwc->setup_buf) {
1946 dev_err(dwc->dev, "failed to allocate setup buffer\n");
1947 ret = -ENOMEM;
1948 goto err2;
1949 }
1950
1951 dev_set_name(&dwc->gadget.dev, "gadget");
1952
1953 dwc->gadget.ops = &dwc3_gadget_ops;
1954 dwc->gadget.is_dualspeed = true;
1955 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1956 dwc->gadget.dev.parent = dwc->dev;
1957
1958 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
1959
1960 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
1961 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
1962 dwc->gadget.dev.release = dwc3_gadget_release;
1963 dwc->gadget.name = "dwc3-gadget";
1964
1965 /*
1966 * REVISIT: Here we should clear all pending IRQs to be
1967 * sure we're starting from a well known location.
1968 */
1969
1970 ret = dwc3_gadget_init_endpoints(dwc);
1971 if (ret)
1972 goto err3;
1973
1974 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1975
1976 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
1977 "dwc3", dwc);
1978 if (ret) {
1979 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1980 irq, ret);
1981 goto err4;
1982 }
1983
1984 /* Enable all but Start and End of Frame IRQs */
1985 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1986 DWC3_DEVTEN_EVNTOVERFLOWEN |
1987 DWC3_DEVTEN_CMDCMPLTEN |
1988 DWC3_DEVTEN_ERRTICERREN |
1989 DWC3_DEVTEN_WKUPEVTEN |
1990 DWC3_DEVTEN_ULSTCNGEN |
1991 DWC3_DEVTEN_CONNECTDONEEN |
1992 DWC3_DEVTEN_USBRSTEN |
1993 DWC3_DEVTEN_DISCONNEVTEN);
1994 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1995
1996 ret = device_register(&dwc->gadget.dev);
1997 if (ret) {
1998 dev_err(dwc->dev, "failed to register gadget device\n");
1999 put_device(&dwc->gadget.dev);
2000 goto err5;
2001 }
2002
2003 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2004 if (ret) {
2005 dev_err(dwc->dev, "failed to register udc\n");
2006 goto err6;
2007 }
2008
2009 return 0;
2010
2011err6:
2012 device_unregister(&dwc->gadget.dev);
2013
2014err5:
2015 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2016 free_irq(irq, dwc);
2017
2018err4:
2019 dwc3_gadget_free_endpoints(dwc);
2020
2021err3:
2022 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2023 dwc->setup_buf, dwc->setup_buf_addr);
2024
2025err2:
2026 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2027 dwc->ep0_trb, dwc->ep0_trb_addr);
2028
2029err1:
2030 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2031 dwc->ctrl_req, dwc->ctrl_req_addr);
2032
2033err0:
2034 return ret;
2035}
2036
2037void dwc3_gadget_exit(struct dwc3 *dwc)
2038{
2039 int irq;
2040 int i;
2041
2042 usb_del_gadget_udc(&dwc->gadget);
2043 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2044
2045 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2046 free_irq(irq, dwc);
2047
2048 for (i = 0; i < ARRAY_SIZE(dwc->eps); i++)
2049 __dwc3_gadget_ep_disable(dwc->eps[i]);
2050
2051 dwc3_gadget_free_endpoints(dwc);
2052
2053 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2054 dwc->setup_buf, dwc->setup_buf_addr);
2055
2056 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2057 dwc->ep0_trb, dwc->ep0_trb_addr);
2058
2059 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2060 dwc->ctrl_req, dwc->ctrl_req_addr);
2061
2062 device_unregister(&dwc->gadget.dev);
2063}
diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
new file mode 100644
index 00000000000..ccfc109f090
--- /dev/null
+++ b/drivers/usb/dwc3/gadget.h
@@ -0,0 +1,292 @@
1/**
2 * gadget.h - DesignWare USB3 DRD Gadget Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#ifndef __DRIVERS_USB_DWC3_GADGET_H
41#define __DRIVERS_USB_DWC3_GADGET_H
42
43#include <linux/list.h>
44#include <linux/usb/gadget.h>
45#include "io.h"
46
47struct dwc3;
48#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
49#define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget))
50
51/**
52 * struct dwc3_gadget_ep_depcfg_param1 - DEPCMDPAR0 for DEPCFG command
53 * @interrupt_number: self-explanatory
54 * @reserved7_5: set to zero
55 * @xfer_complete_enable: event generated when transfer completed
56 * @xfer_in_progress_enable: event generated when transfer in progress
57 * @xfer_not_ready_enable: event generated when transfer not read
58 * @fifo_error_enable: generates events when FIFO Underrun (IN eps)
59 * or FIFO Overrun (OUT) eps
60 * @reserved_12: set to zero
61 * @stream_event_enable: event generated on stream
62 * @reserved14_15: set to zero
63 * @binterval_m1: bInterval minus 1
64 * @stream_capable: this EP is capable of handling streams
65 * @ep_number: self-explanatory
66 * @bulk_based: Set to ‘1’ if this isochronous endpoint represents a bulk
67 * data stream that ignores the relationship of bus time to the
68 * intervals programmed in TRBs.
69 * @fifo_based: Set to ‘1’ if this isochronous endpoint represents a
70 * FIFO-based data stream where TRBs have fixed values and are never
71 * written back by the core.
72 */
73struct dwc3_gadget_ep_depcfg_param1 {
74 u32 interrupt_number:5;
75 u32 reserved7_5:3; /* set to zero */
76 u32 xfer_complete_enable:1;
77 u32 xfer_in_progress_enable:1;
78 u32 xfer_not_ready_enable:1;
79 u32 fifo_error_enable:1; /* IN-underrun, OUT-overrun */
80 u32 reserved12:1; /* set to zero */
81 u32 stream_event_enable:1;
82 u32 reserved14_15:2;
83 u32 binterval_m1:8; /* bInterval minus 1 */
84 u32 stream_capable:1;
85 u32 ep_number:5;
86 u32 bulk_based:1;
87 u32 fifo_based:1;
88} __packed;
89
90/**
91 * struct dwc3_gadget_ep_depcfg_param0 - Parameter 0 for DEPCFG
92 * @reserved0: set to zero
93 * @ep_type: Endpoint Type (control, bulk, iso, interrupt)
94 * @max_packet_size: max packet size in bytes
95 * @reserved16_14: set to zero
96 * @fifo_number: self-explanatory
97 * @burst_size: burst size minus 1
98 * @data_sequence_number: Must be 0 when an endpoint is initially configured
99 * May be non-zero when an endpoint is configured after a power transition
100 * that requires a save/restore.
101 * @ignore_sequence_number: Set to ‘1’ to avoid resetting the sequence
102 * number. This setting is used by software to modify the DEPEVTEN
103 * event enable bits without modifying other endpoint settings.
104 */
105struct dwc3_gadget_ep_depcfg_param0 {
106 u32 reserved0:1;
107 u32 ep_type:2;
108 u32 max_packet_size:11;
109 u32 reserved16_14:3;
110 u32 fifo_number:5;
111 u32 burst_size:4;
112 u32 data_sequence_number:5;
113 u32 ignore_sequence_number:1;
114} __packed;
115
116/**
117 * struct dwc3_gadget_ep_depxfercfg_param0 - Parameter 0 of DEPXFERCFG
118 * @number_xfer_resources: Defines the number of Transfer Resources allocated
119 * to this endpoint. This field must be set to 1.
120 * @reserved16_31: set to zero;
121 */
122struct dwc3_gadget_ep_depxfercfg_param0 {
123 u32 number_xfer_resources:16;
124 u32 reserved16_31:16;
125} __packed;
126
127/**
128 * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER
129 * @transfer_desc_addr_low: Indicates the lower 32 bits of the external
130 * memory's start address for the transfer descriptor. Because TRBs
131 * must be aligned to a 16-byte boundary, the lower 4 bits of this
132 * address must be 0.
133 */
134struct dwc3_gadget_ep_depstrtxfer_param1 {
135 u32 transfer_desc_addr_low;
136} __packed;
137
138/**
139 * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER
140 * @transfer_desc_addr_high: Indicates the higher 32 bits of the external
141 * memory’s start address for the transfer descriptor.
142 */
143struct dwc3_gadget_ep_depstrtxfer_param0 {
144 u32 transfer_desc_addr_high;
145} __packed;
146
147struct dwc3_gadget_ep_cmd_params {
148 union {
149 u32 raw;
150 } param2;
151
152 union {
153 u32 raw;
154 struct dwc3_gadget_ep_depcfg_param1 depcfg;
155 struct dwc3_gadget_ep_depstrtxfer_param1 depstrtxfer;
156 } param1;
157
158 union {
159 u32 raw;
160 struct dwc3_gadget_ep_depcfg_param0 depcfg;
161 struct dwc3_gadget_ep_depxfercfg_param0 depxfercfg;
162 struct dwc3_gadget_ep_depstrtxfer_param0 depstrtxfer;
163 } param0;
164} __packed;
165
166/* -------------------------------------------------------------------------- */
167
168struct dwc3_request {
169 struct usb_request request;
170 struct list_head list;
171 struct dwc3_ep *dep;
172
173 u8 epnum;
174 struct dwc3_trb_hw *trb;
175 dma_addr_t trb_dma;
176
177 unsigned direction:1;
178 unsigned mapped:1;
179 unsigned queued:1;
180};
181#define to_dwc3_request(r) (container_of(r, struct dwc3_request, request))
182
183static inline struct dwc3_request *next_request(struct list_head *list)
184{
185 if (list_empty(list))
186 return NULL;
187
188 return list_first_entry(list, struct dwc3_request, list);
189}
190
191static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req)
192{
193 struct dwc3_ep *dep = req->dep;
194
195 req->queued = true;
196 list_move_tail(&req->list, &dep->req_queued);
197}
198
199#if defined(CONFIG_USB_GADGET_DWC3) || defined(CONFIG_USB_GADGET_DWC3_MODULE)
200int dwc3_gadget_init(struct dwc3 *dwc);
201void dwc3_gadget_exit(struct dwc3 *dwc);
202#else
203static inline int dwc3_gadget_init(struct dwc3 *dwc) { return 0; }
204static inline void dwc3_gadget_exit(struct dwc3 *dwc) { }
205#endif
206
207void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
208 int status);
209
210void dwc3_ep0_interrupt(struct dwc3 *dwc, const struct dwc3_event_depevt *event);
211void dwc3_ep0_out_start(struct dwc3 *dwc);
212int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
213 gfp_t gfp_flags);
214int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value);
215int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
216 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
217void dwc3_map_buffer_to_dma(struct dwc3_request *req);
218void dwc3_unmap_buffer_from_dma(struct dwc3_request *req);
219
220/**
221 * dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
222 * @dwc: DesignWare USB3 Pointer
223 * @number: DWC endpoint number
224 *
225 * Caller should take care of locking
226 */
227static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number)
228{
229 u32 res_id;
230
231 res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number));
232
233 return DWC3_DEPCMD_GET_RSC_IDX(res_id);
234}
235
236/**
237 * dwc3_gadget_event_string - returns event name
238 * @event: the event code
239 */
240static inline const char *dwc3_gadget_event_string(u8 event)
241{
242 switch (event) {
243 case DWC3_DEVICE_EVENT_DISCONNECT:
244 return "Disconnect";
245 case DWC3_DEVICE_EVENT_RESET:
246 return "Reset";
247 case DWC3_DEVICE_EVENT_CONNECT_DONE:
248 return "Connection Done";
249 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
250 return "Link Status Change";
251 case DWC3_DEVICE_EVENT_WAKEUP:
252 return "WakeUp";
253 case DWC3_DEVICE_EVENT_EOPF:
254 return "End-Of-Frame";
255 case DWC3_DEVICE_EVENT_SOF:
256 return "Start-Of-Frame";
257 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
258 return "Erratic Error";
259 case DWC3_DEVICE_EVENT_CMD_CMPL:
260 return "Command Complete";
261 case DWC3_DEVICE_EVENT_OVERFLOW:
262 return "Overflow";
263 }
264
265 return "UNKNOWN";
266}
267
268/**
269 * dwc3_ep_event_string - returns event name
270 * @event: then event code
271 */
272static inline const char *dwc3_ep_event_string(u8 event)
273{
274 switch (event) {
275 case DWC3_DEPEVT_XFERCOMPLETE:
276 return "Transfer Complete";
277 case DWC3_DEPEVT_XFERINPROGRESS:
278 return "Transfer In-Progress";
279 case DWC3_DEPEVT_XFERNOTREADY:
280 return "Transfer Not Ready";
281 case DWC3_DEPEVT_RXTXFIFOEVT:
282 return "FIFO";
283 case DWC3_DEPEVT_STREAMEVT:
284 return "Stream";
285 case DWC3_DEPEVT_EPCMDCMPLT:
286 return "Endpoint Command Complete";
287 }
288
289 return "UNKNOWN";
290}
291
292#endif /* __DRIVERS_USB_DWC3_GADGET_H */
diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
new file mode 100644
index 00000000000..0c4e2a9b0b8
--- /dev/null
+++ b/drivers/usb/dwc3/io.h
@@ -0,0 +1,55 @@
1/**
2 * io.h - DesignWare USB3 DRD IO Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#ifndef __DRIVERS_USB_DWC3_IO_H
41#define __DRIVERS_USB_DWC3_IO_H
42
43#include <asm/io.h>
44
45static inline u32 dwc3_readl(void __iomem *base, u32 offset)
46{
47 return readl(base + offset);
48}
49
50static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
51{
52 writel(value, base + offset);
53}
54
55#endif /* __DRIVERS_USB_DWC3_IO_H */
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 5a084b9cfa3..bb799d5b9ab 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -303,6 +303,18 @@ config USB_PXA_U2O
303 PXA9xx Processor series include a high speed USB2.0 device 303 PXA9xx Processor series include a high speed USB2.0 device
304 controller, which support high speed and full speed USB peripheral. 304 controller, which support high speed and full speed USB peripheral.
305 305
306config USB_GADGET_DWC3
307 tristate "DesignWare USB3.0 (DRD) Controller"
308 depends on USB_DWC3
309 select USB_GADGET_DUALSPEED
310 select USB_GADGET_SUPERSPEED
311 help
312 DesignWare USB3.0 controller is a SuperSpeed USB3.0 Controller
313 which can be configured for peripheral-only, host-only, hub-only
314 and Dual-Role operation. This Controller was first integrated into
315 the OMAP5 series of processors. More information about the OMAP5
316 version of this controller, refer to http://www.ti.com/omap5.
317
306# 318#
307# Controllers available in both integrated and discrete versions 319# Controllers available in both integrated and discrete versions
308# 320#
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 03:32:21 -0400