aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/usb/gadget/fsl_udc_core.c
diff options
context:
space:
mode:
authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /drivers/usb/gadget/fsl_udc_core.c
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'drivers/usb/gadget/fsl_udc_core.c')
-rw-r--r--drivers/usb/gadget/fsl_udc_core.c1143
1 files changed, 807 insertions, 336 deletions
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index c19f7f13790..a406e32645d 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -1,10 +1,12 @@
1/* 1/*
2 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc. 2 * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
3 * All rights reserved. 3 * All rights reserved.
4 * 4 *
5 * Author: Li Yang <leoli@freescale.com> 5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com> 6 * Jiang Bo <tanya.jiang@freescale.com>
7 * 7 *
8 * Copyright (C) 2010-2012 NVIDIA Corporation
9 *
8 * Description: 10 * Description:
9 * Freescale high-speed USB SOC DR module device controller driver. 11 * Freescale high-speed USB SOC DR module device controller driver.
10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus. 12 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
@@ -24,7 +26,6 @@
24#include <linux/ioport.h> 26#include <linux/ioport.h>
25#include <linux/types.h> 27#include <linux/types.h>
26#include <linux/errno.h> 28#include <linux/errno.h>
27#include <linux/err.h>
28#include <linux/slab.h> 29#include <linux/slab.h>
29#include <linux/init.h> 30#include <linux/init.h>
30#include <linux/list.h> 31#include <linux/list.h>
@@ -41,26 +42,46 @@
41#include <linux/fsl_devices.h> 42#include <linux/fsl_devices.h>
42#include <linux/dmapool.h> 43#include <linux/dmapool.h>
43#include <linux/delay.h> 44#include <linux/delay.h>
45#include <linux/regulator/consumer.h>
46#include <linux/workqueue.h>
44 47
45#include <asm/byteorder.h> 48#include <asm/byteorder.h>
46#include <asm/io.h> 49#include <asm/io.h>
50#include <asm/system.h>
47#include <asm/unaligned.h> 51#include <asm/unaligned.h>
48#include <asm/dma.h> 52#include <asm/dma.h>
49 53
54#include <mach/iomap.h>
55
50#include "fsl_usb2_udc.h" 56#include "fsl_usb2_udc.h"
51 57
58#ifdef CONFIG_ARCH_TEGRA
59#define DRIVER_DESC "NVidia Tegra High-Speed USB SOC Device Controller driver"
60#else
52#define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver" 61#define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
62#endif
53#define DRIVER_AUTHOR "Li Yang/Jiang Bo" 63#define DRIVER_AUTHOR "Li Yang/Jiang Bo"
54#define DRIVER_VERSION "Apr 20, 2007" 64#define DRIVER_VERSION "Apr 20, 2007"
55 65
56#define DMA_ADDR_INVALID (~(dma_addr_t)0) 66#define DMA_ADDR_INVALID (~(dma_addr_t)0)
67#define USB1_PREFETCH_ID 6
57 68
69#ifdef CONFIG_ARCH_TEGRA
70static const char driver_name[] = "fsl-tegra-udc";
71#else
58static const char driver_name[] = "fsl-usb2-udc"; 72static const char driver_name[] = "fsl-usb2-udc";
73#endif
59static const char driver_desc[] = DRIVER_DESC; 74static const char driver_desc[] = DRIVER_DESC;
60 75
61static struct usb_dr_device *dr_regs; 76static struct usb_dr_device *dr_regs;
62 77#ifndef CONFIG_ARCH_MXC
63static struct usb_sys_interface *usb_sys_regs; 78static struct usb_sys_interface *usb_sys_regs;
79#endif
80
81/* Charger current limit=1800mA, as per the USB charger spec */
82#define USB_CHARGING_CURRENT_LIMIT_MA 1800
83/* 1 sec wait time for charger detection after vbus is detected */
84#define USB_CHARGER_DETECTION_WAIT_TIME_MS 1000
64 85
65/* it is initialized in probe() */ 86/* it is initialized in probe() */
66static struct fsl_udc *udc_controller = NULL; 87static struct fsl_udc *udc_controller = NULL;
@@ -74,7 +95,9 @@ fsl_ep0_desc = {
74 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD, 95 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
75}; 96};
76 97
98static u32 *control_reg = NULL;
77static void fsl_ep_fifo_flush(struct usb_ep *_ep); 99static void fsl_ep_fifo_flush(struct usb_ep *_ep);
100static int reset_queues(struct fsl_udc *udc);
78 101
79#ifdef CONFIG_PPC32 102#ifdef CONFIG_PPC32
80/* 103/*
@@ -149,10 +172,44 @@ static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
149#define hc32_to_cpu(x) le32_to_cpu(x) 172#define hc32_to_cpu(x) le32_to_cpu(x)
150#endif /* CONFIG_PPC32 */ 173#endif /* CONFIG_PPC32 */
151 174
175/*
176 * High speed test mode packet(53 bytes).
177 * See USB 2.0 spec, section 7.1.20.
178 */
179static const u8 fsl_udc_test_packet[53] = {
180 /* JKJKJKJK x9 */
181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
182 /* JJKKJJKK x8 */
183 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
184 /* JJJJKKKK x8 */
185 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
186 /* JJJJJJJKKKKKKK x8 */
187 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
188 /* JJJJJJJK x8 */
189 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
190 /* JKKKKKKK x10, JK */
191 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
192};
193
152/******************************************************************** 194/********************************************************************
153 * Internal Used Function 195 * Internal Used Function
154********************************************************************/ 196********************************************************************/
155/*----------------------------------------------------------------- 197/*-----------------------------------------------------------------
198 * vbus_enabled() - checks vbus status
199 *--------------------------------------------------------------*/
200static inline bool vbus_enabled(void)
201{
202 bool status = false;
203#ifdef CONFIG_TEGRA_SILICON_PLATFORM
204 status = (fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS);
205#else
206 /*On FPGA VBUS is detected through VBUS A Session instead of VBUS status. */
207 status = (fsl_readl(&usb_sys_regs->vbus_sensors) & USB_SYS_VBUS_ASESSION);
208#endif
209 return status;
210}
211
212/*-----------------------------------------------------------------
156 * done() - retire a request; caller blocked irqs 213 * done() - retire a request; caller blocked irqs
157 * @status : request status to be set, only works when 214 * @status : request status to be set, only works when
158 * request is still in progress. 215 * request is still in progress.
@@ -240,46 +297,56 @@ static void nuke(struct fsl_ep *ep, int status)
240 Internal Hardware related function 297 Internal Hardware related function
241 ------------------------------------------------------------------*/ 298 ------------------------------------------------------------------*/
242 299
300#define FSL_UDC_RESET_TIMEOUT 1000
301static int dr_controller_reset(struct fsl_udc *udc)
302{
303 unsigned int tmp;
304 unsigned long timeout;
305
306 /* Stop and reset the usb controller */
307 tmp = fsl_readl(&dr_regs->usbcmd);
308 tmp &= ~USB_CMD_RUN_STOP;
309 fsl_writel(tmp, &dr_regs->usbcmd);
310
311 tmp = fsl_readl(&dr_regs->usbcmd);
312 tmp |= USB_CMD_CTRL_RESET;
313 fsl_writel(tmp, &dr_regs->usbcmd);
314
315 /* Wait for reset to complete */
316 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
317 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
318 if (time_after(jiffies, timeout)) {
319 ERR("udc reset timeout!\n");
320 return -ETIMEDOUT;
321 }
322 cpu_relax();
323 }
324 return 0;
325}
326
243static int dr_controller_setup(struct fsl_udc *udc) 327static int dr_controller_setup(struct fsl_udc *udc)
244{ 328{
245 unsigned int tmp, portctrl, ep_num; 329 unsigned int tmp, portctrl, ep_num;
246 unsigned int max_no_of_ep; 330 unsigned int max_no_of_ep;
331#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
247 unsigned int ctrl; 332 unsigned int ctrl;
333#endif
334#ifdef CONFIG_ARCH_TEGRA
248 unsigned long timeout; 335 unsigned long timeout;
249 336#endif
250#define FSL_UDC_RESET_TIMEOUT 1000 337 int status;
251 338
252 /* Config PHY interface */ 339 /* Config PHY interface */
253 portctrl = fsl_readl(&dr_regs->portsc1); 340 portctrl = fsl_readl(control_reg);
254 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH); 341 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
255 switch (udc->phy_mode) { 342 switch (udc->phy_mode) {
256 case FSL_USB2_PHY_ULPI: 343 case FSL_USB2_PHY_ULPI:
257 if (udc->pdata->have_sysif_regs) {
258 if (udc->pdata->controller_ver) {
259 /* controller version 1.6 or above */
260 ctrl = __raw_readl(&usb_sys_regs->control);
261 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
262 ctrl |= USB_CTRL_USB_EN;
263 __raw_writel(ctrl, &usb_sys_regs->control);
264 }
265 }
266 portctrl |= PORTSCX_PTS_ULPI; 344 portctrl |= PORTSCX_PTS_ULPI;
267 break; 345 break;
268 case FSL_USB2_PHY_UTMI_WIDE: 346 case FSL_USB2_PHY_UTMI_WIDE:
269 portctrl |= PORTSCX_PTW_16BIT; 347 portctrl |= PORTSCX_PTW_16BIT;
270 /* fall through */ 348 /* fall through */
271 case FSL_USB2_PHY_UTMI: 349 case FSL_USB2_PHY_UTMI:
272 if (udc->pdata->have_sysif_regs) {
273 if (udc->pdata->controller_ver) {
274 /* controller version 1.6 or above */
275 ctrl = __raw_readl(&usb_sys_regs->control);
276 ctrl |= (USB_CTRL_UTMI_PHY_EN |
277 USB_CTRL_USB_EN);
278 __raw_writel(ctrl, &usb_sys_regs->control);
279 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
280 PHY CLK to become stable - 10ms*/
281 }
282 }
283 portctrl |= PORTSCX_PTS_UTMI; 350 portctrl |= PORTSCX_PTS_UTMI;
284 break; 351 break;
285 case FSL_USB2_PHY_SERIAL: 352 case FSL_USB2_PHY_SERIAL:
@@ -288,26 +355,11 @@ static int dr_controller_setup(struct fsl_udc *udc)
288 default: 355 default:
289 return -EINVAL; 356 return -EINVAL;
290 } 357 }
291 fsl_writel(portctrl, &dr_regs->portsc1); 358 fsl_writel(portctrl, control_reg);
292 359
293 /* Stop and reset the usb controller */ 360 status = dr_controller_reset(udc);
294 tmp = fsl_readl(&dr_regs->usbcmd); 361 if (status)
295 tmp &= ~USB_CMD_RUN_STOP; 362 return status;
296 fsl_writel(tmp, &dr_regs->usbcmd);
297
298 tmp = fsl_readl(&dr_regs->usbcmd);
299 tmp |= USB_CMD_CTRL_RESET;
300 fsl_writel(tmp, &dr_regs->usbcmd);
301
302 /* Wait for reset to complete */
303 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
304 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
305 if (time_after(jiffies, timeout)) {
306 ERR("udc reset timeout!\n");
307 return -ETIMEDOUT;
308 }
309 cpu_relax();
310 }
311 363
312 /* Set the controller as device mode */ 364 /* Set the controller as device mode */
313 tmp = fsl_readl(&dr_regs->usbmode); 365 tmp = fsl_readl(&dr_regs->usbmode);
@@ -319,6 +371,19 @@ static int dr_controller_setup(struct fsl_udc *udc)
319 tmp |= USB_MODE_ES; 371 tmp |= USB_MODE_ES;
320 fsl_writel(tmp, &dr_regs->usbmode); 372 fsl_writel(tmp, &dr_regs->usbmode);
321 373
374#ifdef CONFIG_ARCH_TEGRA
375 /* Wait for controller to switch to device mode */
376 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
377 while ((fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_DEVICE) !=
378 USB_MODE_CTRL_MODE_DEVICE) {
379 if (time_after(jiffies, timeout)) {
380 ERR("udc device mode setup timeout!\n");
381 return -ETIMEDOUT;
382 }
383 cpu_relax();
384 }
385#endif
386
322 /* Clear the setup status */ 387 /* Clear the setup status */
323 fsl_writel(0, &dr_regs->usbsts); 388 fsl_writel(0, &dr_regs->usbsts);
324 389
@@ -339,7 +404,7 @@ static int dr_controller_setup(struct fsl_udc *udc)
339 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]); 404 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
340 } 405 }
341 /* Config control enable i/o output, cpu endian register */ 406 /* Config control enable i/o output, cpu endian register */
342#ifndef CONFIG_ARCH_MXC 407#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
343 if (udc->pdata->have_sysif_regs) { 408 if (udc->pdata->have_sysif_regs) {
344 ctrl = __raw_readl(&usb_sys_regs->control); 409 ctrl = __raw_readl(&usb_sys_regs->control);
345 ctrl |= USB_CTRL_IOENB; 410 ctrl |= USB_CTRL_IOENB;
@@ -367,7 +432,32 @@ static int dr_controller_setup(struct fsl_udc *udc)
367static void dr_controller_run(struct fsl_udc *udc) 432static void dr_controller_run(struct fsl_udc *udc)
368{ 433{
369 u32 temp; 434 u32 temp;
435#ifdef CONFIG_ARCH_TEGRA
436 unsigned long timeout;
437#define FSL_UDC_RUN_TIMEOUT 1000
438#endif
439 /* Clear stopped bit */
440 udc->stopped = 0;
370 441
442/* If OTG transceiver is available, then it handles the VBUS detection */
443 if (!udc_controller->transceiver) {
444#ifdef CONFIG_TEGRA_SILICON_PLATFORM
445 /* Enable cable detection interrupt, without setting the
446 * USB_SYS_VBUS_WAKEUP_INT bit. USB_SYS_VBUS_WAKEUP_INT is
447 * clear on write */
448 temp = fsl_readl(&usb_sys_regs->vbus_wakeup);
449 temp |= (USB_SYS_VBUS_WAKEUP_INT_ENABLE | USB_SYS_VBUS_WAKEUP_ENABLE);
450 temp &= ~USB_SYS_VBUS_WAKEUP_INT_STATUS;
451 fsl_writel(temp, &usb_sys_regs->vbus_wakeup);
452#else
453 /*On FPGA VBUS is detected through VBUS A Session instead of VBUS
454 * status. */
455 temp = fsl_readl(&usb_sys_regs->vbus_sensors);
456 temp |= USB_SYS_VBUS_ASESSION_INT_EN;
457 temp &= ~USB_SYS_VBUS_ASESSION_CHANGED;
458 fsl_writel(temp, &usb_sys_regs->vbus_sensors);
459#endif
460 }
371 /* Enable DR irq reg */ 461 /* Enable DR irq reg */
372 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN 462 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
373 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN 463 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
@@ -375,9 +465,6 @@ static void dr_controller_run(struct fsl_udc *udc)
375 465
376 fsl_writel(temp, &dr_regs->usbintr); 466 fsl_writel(temp, &dr_regs->usbintr);
377 467
378 /* Clear stopped bit */
379 udc->stopped = 0;
380
381 /* Set the controller as device mode */ 468 /* Set the controller as device mode */
382 temp = fsl_readl(&dr_regs->usbmode); 469 temp = fsl_readl(&dr_regs->usbmode);
383 temp |= USB_MODE_CTRL_MODE_DEVICE; 470 temp |= USB_MODE_CTRL_MODE_DEVICE;
@@ -387,24 +474,30 @@ static void dr_controller_run(struct fsl_udc *udc)
387 temp = fsl_readl(&dr_regs->usbcmd); 474 temp = fsl_readl(&dr_regs->usbcmd);
388 temp |= USB_CMD_RUN_STOP; 475 temp |= USB_CMD_RUN_STOP;
389 fsl_writel(temp, &dr_regs->usbcmd); 476 fsl_writel(temp, &dr_regs->usbcmd);
477
478#ifdef CONFIG_ARCH_TEGRA
479 /* Wait for controller to start */
480 timeout = jiffies + FSL_UDC_RUN_TIMEOUT;
481 while ((fsl_readl(&dr_regs->usbcmd) & USB_CMD_RUN_STOP) !=
482 USB_CMD_RUN_STOP) {
483 if (time_after(jiffies, timeout)) {
484 ERR("udc start timeout!\n");
485 return;
486 }
487 cpu_relax();
488 }
489#endif
490
491 return;
390} 492}
391 493
392static void dr_controller_stop(struct fsl_udc *udc) 494static void dr_controller_stop(struct fsl_udc *udc)
393{ 495{
394 unsigned int tmp; 496 unsigned int tmp;
395 497
396 pr_debug("%s\n", __func__); 498 /* Clear pending interrupt status bits */
397 499 tmp = fsl_readl(&dr_regs->usbsts);
398 /* if we're in OTG mode, and the Host is currently using the port, 500 fsl_writel(tmp, &dr_regs->usbsts);
399 * stop now and don't rip the controller out from under the
400 * ehci driver
401 */
402 if (udc->gadget.is_otg) {
403 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
404 pr_debug("udc: Leaving early\n");
405 return;
406 }
407 }
408 501
409 /* disable all INTR */ 502 /* disable all INTR */
410 fsl_writel(0, &dr_regs->usbintr); 503 fsl_writel(0, &dr_regs->usbintr);
@@ -535,9 +628,9 @@ static void ep0_setup(struct fsl_udc *udc)
535 /* the intialization of an ep includes: fields in QH, Regs, 628 /* the intialization of an ep includes: fields in QH, Regs,
536 * fsl_ep struct */ 629 * fsl_ep struct */
537 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL, 630 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
538 USB_MAX_CTRL_PAYLOAD, 0, 0); 631 USB_MAX_CTRL_PAYLOAD, 1, 0);
539 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL, 632 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
540 USB_MAX_CTRL_PAYLOAD, 0, 0); 633 USB_MAX_CTRL_PAYLOAD, 1, 0);
541 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL); 634 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
542 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL); 635 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
543 636
@@ -568,7 +661,7 @@ static int fsl_ep_enable(struct usb_ep *_ep,
568 ep = container_of(_ep, struct fsl_ep, ep); 661 ep = container_of(_ep, struct fsl_ep, ep);
569 662
570 /* catch various bogus parameters */ 663 /* catch various bogus parameters */
571 if (!_ep || !desc 664 if (!_ep || !desc || ep->desc
572 || (desc->bDescriptorType != USB_DT_ENDPOINT)) 665 || (desc->bDescriptorType != USB_DT_ENDPOINT))
573 return -EINVAL; 666 return -EINVAL;
574 667
@@ -577,7 +670,7 @@ static int fsl_ep_enable(struct usb_ep *_ep,
577 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) 670 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
578 return -ESHUTDOWN; 671 return -ESHUTDOWN;
579 672
580 max = usb_endpoint_maxp(desc); 673 max = le16_to_cpu(desc->wMaxPacketSize);
581 674
582 /* Disable automatic zlp generation. Driver is responsible to indicate 675 /* Disable automatic zlp generation. Driver is responsible to indicate
583 * explicitly through req->req.zero. This is needed to enable multi-td 676 * explicitly through req->req.zero. This is needed to enable multi-td
@@ -609,7 +702,7 @@ static int fsl_ep_enable(struct usb_ep *_ep,
609 702
610 spin_lock_irqsave(&udc->lock, flags); 703 spin_lock_irqsave(&udc->lock, flags);
611 ep->ep.maxpacket = max; 704 ep->ep.maxpacket = max;
612 ep->ep.desc = desc; 705 ep->desc = desc;
613 ep->stopped = 0; 706 ep->stopped = 0;
614 707
615 /* Controller related setup */ 708 /* Controller related setup */
@@ -633,7 +726,7 @@ static int fsl_ep_enable(struct usb_ep *_ep,
633 retval = 0; 726 retval = 0;
634 727
635 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name, 728 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
636 ep->ep.desc->bEndpointAddress & 0x0f, 729 ep->desc->bEndpointAddress & 0x0f,
637 (desc->bEndpointAddress & USB_DIR_IN) 730 (desc->bEndpointAddress & USB_DIR_IN)
638 ? "in" : "out", max); 731 ? "in" : "out", max);
639en_done: 732en_done:
@@ -653,22 +746,28 @@ static int fsl_ep_disable(struct usb_ep *_ep)
653 int ep_num; 746 int ep_num;
654 747
655 ep = container_of(_ep, struct fsl_ep, ep); 748 ep = container_of(_ep, struct fsl_ep, ep);
656 if (!_ep || !ep->ep.desc) { 749 if (!_ep || !ep->desc) {
657 VDBG("%s not enabled", _ep ? ep->ep.name : NULL); 750 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
658 return -EINVAL; 751 return -EINVAL;
659 } 752 }
660 753
661 /* disable ep on controller */ 754 /* disable ep on controller */
662 ep_num = ep_index(ep); 755 ep_num = ep_index(ep);
663 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 756#if defined(CONFIG_ARCH_TEGRA)
664 if (ep_is_in(ep)) { 757 /* Touch the registers if cable is connected and phy is on */
665 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE); 758 if (vbus_enabled())
666 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT; 759#endif
667 } else { 760 {
668 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE); 761 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
669 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT; 762 if (ep_is_in(ep)) {
763 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
764 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
765 } else {
766 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
767 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
768 }
769 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
670 } 770 }
671 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
672 771
673 udc = (struct fsl_udc *)ep->udc; 772 udc = (struct fsl_udc *)ep->udc;
674 spin_lock_irqsave(&udc->lock, flags); 773 spin_lock_irqsave(&udc->lock, flags);
@@ -676,7 +775,7 @@ static int fsl_ep_disable(struct usb_ep *_ep)
676 /* nuke all pending requests (does flush) */ 775 /* nuke all pending requests (does flush) */
677 nuke(ep, -ESHUTDOWN); 776 nuke(ep, -ESHUTDOWN);
678 777
679 ep->ep.desc = NULL; 778 ep->desc = NULL;
680 ep->stopped = 1; 779 ep->stopped = 1;
681 spin_unlock_irqrestore(&udc->lock, flags); 780 spin_unlock_irqrestore(&udc->lock, flags);
682 781
@@ -714,31 +813,12 @@ static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
714 kfree(req); 813 kfree(req);
715} 814}
716 815
717/* Actually add a dTD chain to an empty dQH and let go */ 816/*-------------------------------------------------------------------------*/
718static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
719{
720 struct ep_queue_head *qh = get_qh_by_ep(ep);
721
722 /* Write dQH next pointer and terminate bit to 0 */
723 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
724 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
725
726 /* Clear active and halt bit */
727 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
728 | EP_QUEUE_HEAD_STATUS_HALT));
729
730 /* Ensure that updates to the QH will occur before priming. */
731 wmb();
732
733 /* Prime endpoint by writing correct bit to ENDPTPRIME */
734 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
735 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
736}
737
738/* Add dTD chain to the dQH of an EP */
739static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req) 817static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
740{ 818{
819 int i = ep_index(ep) * 2 + ep_is_in(ep);
741 u32 temp, bitmask, tmp_stat; 820 u32 temp, bitmask, tmp_stat;
821 struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
742 822
743 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr); 823 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
744 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */ 824 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
@@ -747,18 +827,20 @@ static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
747 ? (1 << (ep_index(ep) + 16)) 827 ? (1 << (ep_index(ep) + 16))
748 : (1 << (ep_index(ep))); 828 : (1 << (ep_index(ep)));
749 829
830 /* Flush all the dTD structs out to memory */
831 wmb();
832
750 /* check if the pipe is empty */ 833 /* check if the pipe is empty */
751 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) { 834 if (!(list_empty(&ep->queue))) {
752 /* Add td to the end */ 835 /* Add td to the end */
753 struct fsl_req *lastreq; 836 struct fsl_req *lastreq;
754 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); 837 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
755 lastreq->tail->next_td_ptr = 838 lastreq->tail->next_td_ptr =
756 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK); 839 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
757 /* Ensure dTD's next dtd pointer to be updated */
758 wmb(); 840 wmb();
759 /* Read prime bit, if 1 goto done */ 841 /* Read prime bit, if 1 goto done */
760 if (fsl_readl(&dr_regs->endpointprime) & bitmask) 842 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
761 return; 843 goto out;
762 844
763 do { 845 do {
764 /* Set ATDTW bit in USBCMD */ 846 /* Set ATDTW bit in USBCMD */
@@ -775,10 +857,28 @@ static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
775 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd); 857 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
776 858
777 if (tmp_stat) 859 if (tmp_stat)
778 return; 860 goto out;
779 } 861 }
780 862
781 fsl_prime_ep(ep, req->head); 863 /* Write dQH next pointer and terminate bit to 0 */
864 temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
865 dQH->next_dtd_ptr = cpu_to_hc32(temp);
866
867 /* Clear active and halt bit */
868 temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
869 | EP_QUEUE_HEAD_STATUS_HALT));
870 dQH->size_ioc_int_sts &= temp;
871
872 /* Ensure that updates to the QH will occur before priming. */
873 wmb();
874
875 /* Prime endpoint by writing 1 to ENDPTPRIME */
876 temp = ep_is_in(ep)
877 ? (1 << (ep_index(ep) + 16))
878 : (1 << (ep_index(ep)));
879 fsl_writel(temp, &dr_regs->endpointprime);
880out:
881 return;
782} 882}
783 883
784/* Fill in the dTD structure 884/* Fill in the dTD structure
@@ -885,8 +985,10 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
885{ 985{
886 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); 986 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
887 struct fsl_req *req = container_of(_req, struct fsl_req, req); 987 struct fsl_req *req = container_of(_req, struct fsl_req, req);
888 struct fsl_udc *udc; 988 struct fsl_udc *udc = ep->udc;
889 unsigned long flags; 989 unsigned long flags;
990 enum dma_data_direction dir;
991 int status;
890 992
891 /* catch various bogus parameters */ 993 /* catch various bogus parameters */
892 if (!_req || !req->req.complete || !req->req.buf 994 if (!_req || !req->req.complete || !req->req.buf
@@ -894,16 +996,26 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
894 VDBG("%s, bad params", __func__); 996 VDBG("%s, bad params", __func__);
895 return -EINVAL; 997 return -EINVAL;
896 } 998 }
897 if (unlikely(!_ep || !ep->ep.desc)) { 999
1000 spin_lock_irqsave(&udc->lock, flags);
1001
1002 if (unlikely(!ep->desc)) {
898 VDBG("%s, bad ep", __func__); 1003 VDBG("%s, bad ep", __func__);
1004 spin_unlock_irqrestore(&udc->lock, flags);
899 return -EINVAL; 1005 return -EINVAL;
900 } 1006 }
901 if (usb_endpoint_xfer_isoc(ep->ep.desc)) { 1007
902 if (req->req.length > ep->ep.maxpacket) 1008 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1009 if (req->req.length > ep->ep.maxpacket) {
1010 spin_unlock_irqrestore(&udc->lock, flags);
903 return -EMSGSIZE; 1011 return -EMSGSIZE;
1012 }
904 } 1013 }
905 1014
906 udc = ep->udc; 1015 dir = ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
1016
1017 spin_unlock_irqrestore(&udc->lock, flags);
1018
907 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) 1019 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
908 return -ESHUTDOWN; 1020 return -ESHUTDOWN;
909 1021
@@ -911,18 +1023,12 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
911 1023
912 /* map virtual address to hardware */ 1024 /* map virtual address to hardware */
913 if (req->req.dma == DMA_ADDR_INVALID) { 1025 if (req->req.dma == DMA_ADDR_INVALID) {
914 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, 1026 req->req.dma = dma_map_single(udc->gadget.dev.parent,
915 req->req.buf, 1027 req->req.buf, req->req.length, dir);
916 req->req.length, ep_is_in(ep)
917 ? DMA_TO_DEVICE
918 : DMA_FROM_DEVICE);
919 req->mapped = 1; 1028 req->mapped = 1;
920 } else { 1029 } else {
921 dma_sync_single_for_device(ep->udc->gadget.dev.parent, 1030 dma_sync_single_for_device(udc->gadget.dev.parent,
922 req->req.dma, req->req.length, 1031 req->req.dma, req->req.length, dir);
923 ep_is_in(ep)
924 ? DMA_TO_DEVICE
925 : DMA_FROM_DEVICE);
926 req->mapped = 0; 1032 req->mapped = 0;
927 } 1033 }
928 1034
@@ -930,20 +1036,42 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
930 req->req.actual = 0; 1036 req->req.actual = 0;
931 req->dtd_count = 0; 1037 req->dtd_count = 0;
932 1038
1039
933 /* build dtds and push them to device queue */ 1040 /* build dtds and push them to device queue */
934 if (!fsl_req_to_dtd(req, gfp_flags)) { 1041 status = fsl_req_to_dtd(req, gfp_flags);
935 spin_lock_irqsave(&udc->lock, flags); 1042 if (status)
936 fsl_queue_td(ep, req); 1043 goto err_unmap;
937 } else { 1044
938 return -ENOMEM; 1045 spin_lock_irqsave(&udc->lock, flags);
1046
1047 /* re-check if the ep has not been disabled */
1048 if (unlikely(!ep->desc)) {
1049 spin_unlock_irqrestore(&udc->lock, flags);
1050 status = -EINVAL;
1051 goto err_unmap;
939 } 1052 }
940 1053
1054 fsl_queue_td(ep, req);
1055
1056 /* Update ep0 state */
1057 if ((ep_index(ep) == 0))
1058 udc->ep0_state = DATA_STATE_XMIT;
1059
941 /* irq handler advances the queue */ 1060 /* irq handler advances the queue */
942 if (req != NULL) 1061 if (req != NULL)
943 list_add_tail(&req->queue, &ep->queue); 1062 list_add_tail(&req->queue, &ep->queue);
944 spin_unlock_irqrestore(&udc->lock, flags); 1063 spin_unlock_irqrestore(&udc->lock, flags);
945 1064
946 return 0; 1065 return 0;
1066
1067err_unmap:
1068 if (req->mapped) {
1069 dma_unmap_single(udc->gadget.dev.parent,
1070 req->req.dma, req->req.length, dir);
1071 req->req.dma = DMA_ADDR_INVALID;
1072 req->mapped = 0;
1073 }
1074 return status;
947} 1075}
948 1076
949/* dequeues (cancels, unlinks) an I/O request from an endpoint */ 1077/* dequeues (cancels, unlinks) an I/O request from an endpoint */
@@ -964,12 +1092,19 @@ static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
964 /* Stop the ep before we deal with the queue */ 1092 /* Stop the ep before we deal with the queue */
965 ep->stopped = 1; 1093 ep->stopped = 1;
966 ep_num = ep_index(ep); 1094 ep_num = ep_index(ep);
967 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 1095
968 if (ep_is_in(ep)) 1096#if defined(CONFIG_ARCH_TEGRA)
969 epctrl &= ~EPCTRL_TX_ENABLE; 1097 /* Touch the registers if cable is connected and phy is on */
970 else 1098 if(vbus_enabled())
971 epctrl &= ~EPCTRL_RX_ENABLE; 1099#endif
972 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); 1100 {
1101 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1102 if (ep_is_in(ep))
1103 epctrl &= ~EPCTRL_TX_ENABLE;
1104 else
1105 epctrl &= ~EPCTRL_RX_ENABLE;
1106 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1107 }
973 1108
974 /* make sure it's actually queued on this endpoint */ 1109 /* make sure it's actually queued on this endpoint */
975 list_for_each_entry(req, &ep->queue, queue) { 1110 list_for_each_entry(req, &ep->queue, queue) {
@@ -988,31 +1123,43 @@ static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
988 1123
989 /* The request isn't the last request in this ep queue */ 1124 /* The request isn't the last request in this ep queue */
990 if (req->queue.next != &ep->queue) { 1125 if (req->queue.next != &ep->queue) {
1126 struct ep_queue_head *qh;
991 struct fsl_req *next_req; 1127 struct fsl_req *next_req;
992 1128
1129 qh = ep->qh;
993 next_req = list_entry(req->queue.next, struct fsl_req, 1130 next_req = list_entry(req->queue.next, struct fsl_req,
994 queue); 1131 queue);
995 1132
996 /* prime with dTD of next request */ 1133 /* Point the QH to the first TD of next request */
997 fsl_prime_ep(ep, next_req->head); 1134 fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
998 } 1135 }
999 /* The request hasn't been processed, patch up the TD chain */ 1136
1137 /* The request hasn't been processed, patch up the TD chain */
1000 } else { 1138 } else {
1001 struct fsl_req *prev_req; 1139 struct fsl_req *prev_req;
1002 1140
1003 prev_req = list_entry(req->queue.prev, struct fsl_req, queue); 1141 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
1004 prev_req->tail->next_td_ptr = req->tail->next_td_ptr; 1142 fsl_writel(fsl_readl(&req->tail->next_td_ptr),
1143 &prev_req->tail->next_td_ptr);
1144
1005 } 1145 }
1006 1146
1007 done(ep, req, -ECONNRESET); 1147 done(ep, req, -ECONNRESET);
1008 1148
1009 /* Enable EP */ 1149 /* Enable EP */
1010out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 1150out:
1011 if (ep_is_in(ep)) 1151#if defined(CONFIG_ARCH_TEGRA)
1012 epctrl |= EPCTRL_TX_ENABLE; 1152 /* Touch the registers if cable is connected and phy is on */
1013 else 1153 if(vbus_enabled())
1014 epctrl |= EPCTRL_RX_ENABLE; 1154#endif
1015 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); 1155 {
1156 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1157 if (ep_is_in(ep))
1158 epctrl |= EPCTRL_TX_ENABLE;
1159 else
1160 epctrl |= EPCTRL_RX_ENABLE;
1161 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1162 }
1016 ep->stopped = stopped; 1163 ep->stopped = stopped;
1017 1164
1018 spin_unlock_irqrestore(&ep->udc->lock, flags); 1165 spin_unlock_irqrestore(&ep->udc->lock, flags);
@@ -1037,12 +1184,12 @@ static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1037 1184
1038 ep = container_of(_ep, struct fsl_ep, ep); 1185 ep = container_of(_ep, struct fsl_ep, ep);
1039 udc = ep->udc; 1186 udc = ep->udc;
1040 if (!_ep || !ep->ep.desc) { 1187 if (!_ep || !ep->desc) {
1041 status = -EINVAL; 1188 status = -EINVAL;
1042 goto out; 1189 goto out;
1043 } 1190 }
1044 1191
1045 if (usb_endpoint_xfer_isoc(ep->ep.desc)) { 1192 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1046 status = -EOPNOTSUPP; 1193 status = -EOPNOTSUPP;
1047 goto out; 1194 goto out;
1048 } 1195 }
@@ -1078,10 +1225,10 @@ static int fsl_ep_fifo_status(struct usb_ep *_ep)
1078 struct fsl_udc *udc; 1225 struct fsl_udc *udc;
1079 int size = 0; 1226 int size = 0;
1080 u32 bitmask; 1227 u32 bitmask;
1081 struct ep_queue_head *qh; 1228 struct ep_queue_head *d_qh;
1082 1229
1083 ep = container_of(_ep, struct fsl_ep, ep); 1230 ep = container_of(_ep, struct fsl_ep, ep);
1084 if (!_ep || (!ep->ep.desc && ep_index(ep) != 0)) 1231 if (!_ep || (!ep->desc && ep_index(ep) != 0))
1085 return -ENODEV; 1232 return -ENODEV;
1086 1233
1087 udc = (struct fsl_udc *)ep->udc; 1234 udc = (struct fsl_udc *)ep->udc;
@@ -1089,13 +1236,13 @@ static int fsl_ep_fifo_status(struct usb_ep *_ep)
1089 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) 1236 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1090 return -ESHUTDOWN; 1237 return -ESHUTDOWN;
1091 1238
1092 qh = get_qh_by_ep(ep); 1239 d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
1093 1240
1094 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) : 1241 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1095 (1 << (ep_index(ep))); 1242 (1 << (ep_index(ep)));
1096 1243
1097 if (fsl_readl(&dr_regs->endptstatus) & bitmask) 1244 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1098 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE) 1245 size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1099 >> DTD_LENGTH_BIT_POS; 1246 >> DTD_LENGTH_BIT_POS;
1100 1247
1101 pr_debug("%s %u\n", __func__, size); 1248 pr_debug("%s %u\n", __func__, size);
@@ -1110,11 +1257,17 @@ static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1110 unsigned long timeout; 1257 unsigned long timeout;
1111#define FSL_UDC_FLUSH_TIMEOUT 1000 1258#define FSL_UDC_FLUSH_TIMEOUT 1000
1112 1259
1260#if defined(CONFIG_ARCH_TEGRA)
1261 /* Touch the registers if cable is connected and phy is on */
1262 if (!vbus_enabled())
1263 return;
1264#endif
1265
1113 if (!_ep) { 1266 if (!_ep) {
1114 return; 1267 return;
1115 } else { 1268 } else {
1116 ep = container_of(_ep, struct fsl_ep, ep); 1269 ep = container_of(_ep, struct fsl_ep, ep);
1117 if (!ep->ep.desc) 1270 if (!ep->desc)
1118 return; 1271 return;
1119 } 1272 }
1120 ep_num = ep_index(ep); 1273 ep_num = ep_index(ep);
@@ -1173,6 +1326,7 @@ static int fsl_get_frame(struct usb_gadget *gadget)
1173/*----------------------------------------------------------------------- 1326/*-----------------------------------------------------------------------
1174 * Tries to wake up the host connected to this gadget 1327 * Tries to wake up the host connected to this gadget
1175 -----------------------------------------------------------------------*/ 1328 -----------------------------------------------------------------------*/
1329#ifndef CONFIG_USB_ANDROID
1176static int fsl_wakeup(struct usb_gadget *gadget) 1330static int fsl_wakeup(struct usb_gadget *gadget)
1177{ 1331{
1178 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget); 1332 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
@@ -1191,12 +1345,21 @@ static int fsl_wakeup(struct usb_gadget *gadget)
1191 fsl_writel(portsc, &dr_regs->portsc1); 1345 fsl_writel(portsc, &dr_regs->portsc1);
1192 return 0; 1346 return 0;
1193} 1347}
1348#endif
1194 1349
1195static int can_pullup(struct fsl_udc *udc) 1350static int can_pullup(struct fsl_udc *udc)
1196{ 1351{
1197 return udc->driver && udc->softconnect && udc->vbus_active; 1352 return udc->driver && udc->softconnect && udc->vbus_active;
1198} 1353}
1199 1354
1355static int fsl_set_selfpowered(struct usb_gadget * gadget, int is_on)
1356{
1357 struct fsl_udc *udc;
1358 udc = container_of(gadget, struct fsl_udc, gadget);
1359 udc->selfpowered = (is_on != 0);
1360 return 0;
1361}
1362
1200/* Notify controller that VBUS is powered, Called by whatever 1363/* Notify controller that VBUS is powered, Called by whatever
1201 detects VBUS sessions */ 1364 detects VBUS sessions */
1202static int fsl_vbus_session(struct usb_gadget *gadget, int is_active) 1365static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
@@ -1205,8 +1368,58 @@ static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1205 unsigned long flags; 1368 unsigned long flags;
1206 1369
1207 udc = container_of(gadget, struct fsl_udc, gadget); 1370 udc = container_of(gadget, struct fsl_udc, gadget);
1208 spin_lock_irqsave(&udc->lock, flags); 1371
1209 VDBG("VBUS %s", is_active ? "on" : "off"); 1372 VDBG("VBUS %s", is_active ? "on" : "off");
1373
1374 if (udc->transceiver) {
1375 if (udc->vbus_active && !is_active) {
1376 /* If cable disconnected, cancel any delayed work */
1377 cancel_delayed_work(&udc->work);
1378 spin_lock_irqsave(&udc->lock, flags);
1379 /* reset all internal Queues and inform client driver */
1380 reset_queues(udc);
1381 /* stop the controller and turn off the clocks */
1382 dr_controller_stop(udc);
1383 dr_controller_reset(udc);
1384 udc->vbus_active = 0;
1385 udc->usb_state = USB_STATE_DEFAULT;
1386 spin_unlock_irqrestore(&udc->lock, flags);
1387 fsl_udc_clk_suspend(false);
1388 if (udc->vbus_regulator) {
1389 /* set the current limit to 0mA */
1390 regulator_set_current_limit(
1391 udc->vbus_regulator, 0, 0);
1392 }
1393 } else if (!udc->vbus_active && is_active) {
1394 fsl_udc_clk_resume(false);
1395 /* setup the controller in the device mode */
1396 dr_controller_setup(udc);
1397 /* setup EP0 for setup packet */
1398 ep0_setup(udc);
1399 /* initialize the USB and EP states */
1400 udc->usb_state = USB_STATE_ATTACHED;
1401 udc->ep0_state = WAIT_FOR_SETUP;
1402 udc->ep0_dir = 0;
1403 udc->vbus_active = 1;
1404 /* start the controller */
1405 dr_controller_run(udc);
1406 if (udc->vbus_regulator) {
1407 /* set the current limit to 100mA */
1408 regulator_set_current_limit(
1409 udc->vbus_regulator, 0, 100);
1410 }
1411 /* Schedule work to wait for 1000 msec and check for
1412 * charger if setup packet is not received */
1413 schedule_delayed_work(&udc->work,
1414 USB_CHARGER_DETECTION_WAIT_TIME_MS);
1415 }
1416
1417#ifndef CONFIG_USB_G_ANDROID
1418 return 0;
1419#endif
1420 }
1421
1422 spin_lock_irqsave(&udc->lock, flags);
1210 udc->vbus_active = (is_active != 0); 1423 udc->vbus_active = (is_active != 0);
1211 if (can_pullup(udc)) 1424 if (can_pullup(udc))
1212 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), 1425 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
@@ -1230,8 +1443,14 @@ static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1230 struct fsl_udc *udc; 1443 struct fsl_udc *udc;
1231 1444
1232 udc = container_of(gadget, struct fsl_udc, gadget); 1445 udc = container_of(gadget, struct fsl_udc, gadget);
1233 if (!IS_ERR_OR_NULL(udc->transceiver)) 1446 /* check udc regulator is available for drawing the vbus current */
1234 return usb_phy_set_power(udc->transceiver, mA); 1447 if (udc->vbus_regulator) {
1448 udc->current_limit = mA;
1449 schedule_work(&udc->charger_work);
1450 }
1451
1452 if (udc->transceiver)
1453 return otg_set_power(udc->transceiver, mA);
1235 return -ENOTSUPP; 1454 return -ENOTSUPP;
1236} 1455}
1237 1456
@@ -1244,24 +1463,29 @@ static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1244 1463
1245 udc = container_of(gadget, struct fsl_udc, gadget); 1464 udc = container_of(gadget, struct fsl_udc, gadget);
1246 udc->softconnect = (is_on != 0); 1465 udc->softconnect = (is_on != 0);
1247 if (can_pullup(udc)) 1466 if (udc_controller->transceiver) {
1248 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), 1467 if (udc_controller->transceiver->state == OTG_STATE_B_PERIPHERAL) {
1249 &dr_regs->usbcmd); 1468 if (can_pullup(udc))
1250 else 1469 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1251 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), 1470 &dr_regs->usbcmd);
1252 &dr_regs->usbcmd); 1471 else
1253 1472 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1473 &dr_regs->usbcmd);
1474 }
1475 }
1254 return 0; 1476 return 0;
1255} 1477}
1256 1478
1257static int fsl_start(struct usb_gadget_driver *driver, 1479static int fsl_start(struct usb_gadget_driver *driver,
1258 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *)); 1480 int (*bind)(struct usb_gadget *));
1259static int fsl_stop(struct usb_gadget_driver *driver); 1481static int fsl_stop(struct usb_gadget_driver *driver);
1260/* defined in gadget.h */ 1482/* defined in gadget.h */
1261static struct usb_gadget_ops fsl_gadget_ops = { 1483static struct usb_gadget_ops fsl_gadget_ops = {
1262 .get_frame = fsl_get_frame, 1484 .get_frame = fsl_get_frame,
1485#ifndef CONFIG_USB_ANDROID
1263 .wakeup = fsl_wakeup, 1486 .wakeup = fsl_wakeup,
1264/* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */ 1487#endif
1488 .set_selfpowered = fsl_set_selfpowered,
1265 .vbus_session = fsl_vbus_session, 1489 .vbus_session = fsl_vbus_session,
1266 .vbus_draw = fsl_vbus_draw, 1490 .vbus_draw = fsl_vbus_draw,
1267 .pullup = fsl_pullup, 1491 .pullup = fsl_pullup,
@@ -1295,8 +1519,7 @@ static int ep0_prime_status(struct fsl_udc *udc, int direction)
1295 udc->ep0_dir = USB_DIR_OUT; 1519 udc->ep0_dir = USB_DIR_OUT;
1296 1520
1297 ep = &udc->eps[0]; 1521 ep = &udc->eps[0];
1298 if (udc->ep0_state != DATA_STATE_XMIT) 1522 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1299 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1300 1523
1301 req->ep = ep; 1524 req->ep = ep;
1302 req->req.length = 0; 1525 req->req.length = 0;
@@ -1356,7 +1579,8 @@ static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1356 1579
1357 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) { 1580 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1358 /* Get device status */ 1581 /* Get device status */
1359 tmp = 1 << USB_DEVICE_SELF_POWERED; 1582 if (udc->selfpowered)
1583 tmp = 1 << USB_DEVICE_SELF_POWERED;
1360 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP; 1584 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1361 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { 1585 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1362 /* Get interface status */ 1586 /* Get interface status */
@@ -1369,7 +1593,7 @@ static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1369 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index)); 1593 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1370 1594
1371 /* stall if endpoint doesn't exist */ 1595 /* stall if endpoint doesn't exist */
1372 if (!target_ep->ep.desc) 1596 if (!target_ep->desc)
1373 goto stall; 1597 goto stall;
1374 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep)) 1598 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1375 << USB_ENDPOINT_HALT; 1599 << USB_ENDPOINT_HALT;
@@ -1388,10 +1612,22 @@ static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1388 req->req.complete = NULL; 1612 req->req.complete = NULL;
1389 req->dtd_count = 0; 1613 req->dtd_count = 0;
1390 1614
1391 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, 1615 /* map virtual address to hardware */
1392 req->req.buf, req->req.length, 1616 if (req->req.dma == DMA_ADDR_INVALID) {
1393 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 1617 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1394 req->mapped = 1; 1618 req->req.buf,
1619 req->req.length, ep_is_in(ep)
1620 ? DMA_TO_DEVICE
1621 : DMA_FROM_DEVICE);
1622 req->mapped = 1;
1623 } else {
1624 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
1625 req->req.dma, req->req.length,
1626 ep_is_in(ep)
1627 ? DMA_TO_DEVICE
1628 : DMA_FROM_DEVICE);
1629 req->mapped = 0;
1630 }
1395 1631
1396 /* prime the data phase */ 1632 /* prime the data phase */
1397 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0)) 1633 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
@@ -1401,9 +1637,107 @@ static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1401 1637
1402 list_add_tail(&req->queue, &ep->queue); 1638 list_add_tail(&req->queue, &ep->queue);
1403 udc->ep0_state = DATA_STATE_XMIT; 1639 udc->ep0_state = DATA_STATE_XMIT;
1404 if (ep0_prime_status(udc, EP_DIR_OUT)) 1640 return;
1641stall:
1642 ep0stall(udc);
1643}
1644
1645static void udc_test_mode(struct fsl_udc *udc, u32 test_mode)
1646{
1647 struct fsl_req *req;
1648 struct fsl_ep *ep;
1649 u32 portsc, bitmask;
1650 unsigned long timeout;
1651
1652 /* Ack the ep0 IN */
1653 if (ep0_prime_status(udc, EP_DIR_IN))
1405 ep0stall(udc); 1654 ep0stall(udc);
1406 1655
1656 /* get the ep0 */
1657 ep = &udc->eps[0];
1658 bitmask = ep_is_in(ep)
1659 ? (1 << (ep_index(ep) + 16))
1660 : (1 << (ep_index(ep)));
1661
1662 timeout = jiffies + HZ;
1663 /* Wait until ep0 IN endpoint txfr is complete */
1664 while (!(fsl_readl(&dr_regs->endptcomplete) & bitmask)) {
1665 if (time_after(jiffies, timeout)) {
1666 pr_err("Timeout for Ep0 IN Ack\n");
1667 break;
1668 }
1669 cpu_relax();
1670 }
1671
1672 switch (test_mode << PORTSCX_PTC_BIT_POS) {
1673 case PORTSCX_PTC_JSTATE:
1674 VDBG("TEST_J\n");
1675 break;
1676 case PORTSCX_PTC_KSTATE:
1677 VDBG("TEST_K\n");
1678 break;
1679 case PORTSCX_PTC_SEQNAK:
1680 VDBG("TEST_SE0_NAK\n");
1681 break;
1682 case PORTSCX_PTC_PACKET:
1683 VDBG("TEST_PACKET\n");
1684
1685 /* get the ep and configure for IN direction */
1686 ep = &udc->eps[0];
1687 udc->ep0_dir = USB_DIR_IN;
1688
1689 /* Initialize ep0 status request structure */
1690 req = container_of(fsl_alloc_request(NULL, GFP_ATOMIC),
1691 struct fsl_req, req);
1692 /* allocate a small amount of memory to get valid address */
1693 req->req.buf = kmalloc(sizeof(fsl_udc_test_packet), GFP_ATOMIC);
1694 req->req.dma = virt_to_phys(req->req.buf);
1695
1696 /* Fill in the reqest structure */
1697 memcpy(req->req.buf, fsl_udc_test_packet, sizeof(fsl_udc_test_packet));
1698 req->ep = ep;
1699 req->req.length = sizeof(fsl_udc_test_packet);
1700 req->req.status = -EINPROGRESS;
1701 req->req.actual = 0;
1702 req->req.complete = NULL;
1703 req->dtd_count = 0;
1704 req->mapped = 0;
1705
1706 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
1707 req->req.dma, req->req.length,
1708 ep_is_in(ep)
1709 ? DMA_TO_DEVICE
1710 : DMA_FROM_DEVICE);
1711
1712 /* prime the data phase */
1713 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1714 fsl_queue_td(ep, req);
1715 else /* no mem */
1716 goto stall;
1717
1718 list_add_tail(&req->queue, &ep->queue);
1719 udc->ep0_state = DATA_STATE_XMIT;
1720 break;
1721 case PORTSCX_PTC_FORCE_EN:
1722 VDBG("TEST_FORCE_EN\n");
1723 break;
1724 default:
1725 ERR("udc unknown test mode[%d]!\n", test_mode);
1726 goto stall;
1727 }
1728
1729 /* read the portsc register */
1730 portsc = fsl_readl(&dr_regs->portsc1);
1731 /* set the test mode selector */
1732 portsc |= test_mode << PORTSCX_PTC_BIT_POS;
1733 fsl_writel(portsc, &dr_regs->portsc1);
1734
1735 /*
1736 * The device must have its power cycled to exit test mode.
1737 * See USB 2.0 spec, section 9.4.9 for test modes operation in "Set Feature"
1738 * See USB 2.0 spec, section 7.1.20 for test modes.
1739 */
1740 pr_info("udc entering the test mode, power cycle to exit test mode\n");
1407 return; 1741 return;
1408stall: 1742stall:
1409 ep0stall(udc); 1743 ep0stall(udc);
@@ -1433,6 +1767,11 @@ static void setup_received_irq(struct fsl_udc *udc,
1433 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD 1767 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1434 | USB_RECIP_DEVICE)) 1768 | USB_RECIP_DEVICE))
1435 break; 1769 break;
1770#ifdef CONFIG_ARCH_TEGRA
1771 /* This delay is necessary for some windows drivers to
1772 * properly recognize the device */
1773 mdelay(1);
1774#endif
1436 ch9setaddress(udc, wValue, wIndex, wLength); 1775 ch9setaddress(udc, wValue, wIndex, wLength);
1437 return; 1776 return;
1438 1777
@@ -1443,12 +1782,22 @@ static void setup_received_irq(struct fsl_udc *udc,
1443 int rc = -EOPNOTSUPP; 1782 int rc = -EOPNOTSUPP;
1444 u16 ptc = 0; 1783 u16 ptc = 0;
1445 1784
1446 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) 1785 if (setup->bRequestType == USB_RECIP_DEVICE &&
1786 wValue == USB_DEVICE_TEST_MODE) {
1787 /*
1788 * If the feature selector is TEST_MODE, then the most
1789 * significant byte of wIndex is used to specify the specific
1790 * test mode and the lower byte of wIndex must be zero.
1791 */
1792 udc_test_mode(udc, wIndex >> 8);
1793 return;
1794
1795 } else if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1447 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) { 1796 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1448 int pipe = get_pipe_by_windex(wIndex); 1797 int pipe = get_pipe_by_windex(wIndex);
1449 struct fsl_ep *ep; 1798 struct fsl_ep *ep;
1450 1799
1451 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep) 1800 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1452 break; 1801 break;
1453 ep = get_ep_by_pipe(udc, pipe); 1802 ep = get_ep_by_pipe(udc, pipe);
1454 1803
@@ -1506,25 +1855,17 @@ static void setup_received_irq(struct fsl_udc *udc,
1506 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN) 1855 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1507 ? USB_DIR_IN : USB_DIR_OUT; 1856 ? USB_DIR_IN : USB_DIR_OUT;
1508 spin_unlock(&udc->lock); 1857 spin_unlock(&udc->lock);
1509 if (udc->driver->setup(&udc->gadget, 1858 if (udc->driver && udc->driver->setup(&udc->gadget,
1510 &udc->local_setup_buff) < 0) 1859 &udc->local_setup_buff) < 0)
1511 ep0stall(udc); 1860 ep0stall(udc);
1512 spin_lock(&udc->lock); 1861 spin_lock(&udc->lock);
1513 udc->ep0_state = (setup->bRequestType & USB_DIR_IN) 1862 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1514 ? DATA_STATE_XMIT : DATA_STATE_RECV; 1863 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1515 /*
1516 * If the data stage is IN, send status prime immediately.
1517 * See 2.0 Spec chapter 8.5.3.3 for detail.
1518 */
1519 if (udc->ep0_state == DATA_STATE_XMIT)
1520 if (ep0_prime_status(udc, EP_DIR_OUT))
1521 ep0stall(udc);
1522
1523 } else { 1864 } else {
1524 /* No data phase, IN status from gadget */ 1865 /* No data phase, IN status from gadget */
1525 udc->ep0_dir = USB_DIR_IN; 1866 udc->ep0_dir = USB_DIR_IN;
1526 spin_unlock(&udc->lock); 1867 spin_unlock(&udc->lock);
1527 if (udc->driver->setup(&udc->gadget, 1868 if (udc->driver && udc->driver->setup(&udc->gadget,
1528 &udc->local_setup_buff) < 0) 1869 &udc->local_setup_buff) < 0)
1529 ep0stall(udc); 1870 ep0stall(udc);
1530 spin_lock(&udc->lock); 1871 spin_lock(&udc->lock);
@@ -1548,8 +1889,9 @@ static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1548 1889
1549 switch (udc->ep0_state) { 1890 switch (udc->ep0_state) {
1550 case DATA_STATE_XMIT: 1891 case DATA_STATE_XMIT:
1551 /* already primed at setup_received_irq */ 1892 /* receive status phase */
1552 udc->ep0_state = WAIT_FOR_OUT_STATUS; 1893 if (ep0_prime_status(udc, EP_DIR_OUT))
1894 ep0stall(udc);
1553 break; 1895 break;
1554 case DATA_STATE_RECV: 1896 case DATA_STATE_RECV:
1555 /* send status phase */ 1897 /* send status phase */
@@ -1698,7 +2040,12 @@ static void dtd_complete_irq(struct fsl_udc *udc)
1698 if (!bit_pos) 2040 if (!bit_pos)
1699 return; 2041 return;
1700 2042
2043#ifdef CONFIG_ARCH_TEGRA
2044 /* XXX what's going on here */
1701 for (i = 0; i < udc->max_ep; i++) { 2045 for (i = 0; i < udc->max_ep; i++) {
2046#else
2047 for (i = 0; i < udc->max_ep * 2; i++) {
2048#endif
1702 ep_num = i >> 1; 2049 ep_num = i >> 1;
1703 direction = i % 2; 2050 direction = i % 2;
1704 2051
@@ -1736,31 +2083,31 @@ static void dtd_complete_irq(struct fsl_udc *udc)
1736 } 2083 }
1737} 2084}
1738 2085
1739static inline enum usb_device_speed portscx_device_speed(u32 reg)
1740{
1741 switch (reg & PORTSCX_PORT_SPEED_MASK) {
1742 case PORTSCX_PORT_SPEED_HIGH:
1743 return USB_SPEED_HIGH;
1744 case PORTSCX_PORT_SPEED_FULL:
1745 return USB_SPEED_FULL;
1746 case PORTSCX_PORT_SPEED_LOW:
1747 return USB_SPEED_LOW;
1748 default:
1749 return USB_SPEED_UNKNOWN;
1750 }
1751}
1752
1753/* Process a port change interrupt */ 2086/* Process a port change interrupt */
1754static void port_change_irq(struct fsl_udc *udc) 2087static void port_change_irq(struct fsl_udc *udc)
1755{ 2088{
1756 if (udc->bus_reset) 2089 u32 speed;
1757 udc->bus_reset = 0;
1758 2090
1759 /* Bus resetting is finished */ 2091 /* Bus resetting is finished */
1760 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) 2092 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
1761 /* Get the speed */ 2093 /* Get the speed */
1762 udc->gadget.speed = 2094 speed = (fsl_readl(control_reg)
1763 portscx_device_speed(fsl_readl(&dr_regs->portsc1)); 2095 & PORTSCX_PORT_SPEED_MASK);
2096 switch (speed) {
2097 case PORTSCX_PORT_SPEED_HIGH:
2098 udc->gadget.speed = USB_SPEED_HIGH;
2099 break;
2100 case PORTSCX_PORT_SPEED_FULL:
2101 udc->gadget.speed = USB_SPEED_FULL;
2102 break;
2103 case PORTSCX_PORT_SPEED_LOW:
2104 udc->gadget.speed = USB_SPEED_LOW;
2105 break;
2106 default:
2107 udc->gadget.speed = USB_SPEED_UNKNOWN;
2108 break;
2109 }
2110 }
1764 2111
1765 /* Update USB state */ 2112 /* Update USB state */
1766 if (!udc->resume_state) 2113 if (!udc->resume_state)
@@ -1774,7 +2121,7 @@ static void suspend_irq(struct fsl_udc *udc)
1774 udc->usb_state = USB_STATE_SUSPENDED; 2121 udc->usb_state = USB_STATE_SUSPENDED;
1775 2122
1776 /* report suspend to the driver, serial.c does not support this */ 2123 /* report suspend to the driver, serial.c does not support this */
1777 if (udc->driver->suspend) 2124 if (udc->driver && udc->driver->suspend)
1778 udc->driver->suspend(&udc->gadget); 2125 udc->driver->suspend(&udc->gadget);
1779} 2126}
1780 2127
@@ -1784,7 +2131,7 @@ static void bus_resume(struct fsl_udc *udc)
1784 udc->resume_state = 0; 2131 udc->resume_state = 0;
1785 2132
1786 /* report resume to the driver, serial.c does not support this */ 2133 /* report resume to the driver, serial.c does not support this */
1787 if (udc->driver->resume) 2134 if (udc->driver && udc->driver->resume)
1788 udc->driver->resume(&udc->gadget); 2135 udc->driver->resume(&udc->gadget);
1789} 2136}
1790 2137
@@ -1798,7 +2145,8 @@ static int reset_queues(struct fsl_udc *udc)
1798 2145
1799 /* report disconnect; the driver is already quiesced */ 2146 /* report disconnect; the driver is already quiesced */
1800 spin_unlock(&udc->lock); 2147 spin_unlock(&udc->lock);
1801 udc->driver->disconnect(&udc->gadget); 2148 if (udc->driver && udc->driver->disconnect)
2149 udc->driver->disconnect(&udc->gadget);
1802 spin_lock(&udc->lock); 2150 spin_lock(&udc->lock);
1803 2151
1804 return 0; 2152 return 0;
@@ -1846,10 +2194,17 @@ static void reset_irq(struct fsl_udc *udc)
1846 /* Write 1s to the flush register */ 2194 /* Write 1s to the flush register */
1847 fsl_writel(0xffffffff, &dr_regs->endptflush); 2195 fsl_writel(0xffffffff, &dr_regs->endptflush);
1848 2196
2197#if defined(CONFIG_ARCH_TEGRA)
2198 /* When the bus reset is seen on Tegra, the PORTSCX_PORT_RESET bit
2199 * is not set */
2200 VDBG("Bus reset");
2201 /* Reset all the queues, include XD, dTD, EP queue
2202 * head and TR Queue */
2203 reset_queues(udc);
2204 udc->usb_state = USB_STATE_DEFAULT;
2205#else
1849 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) { 2206 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1850 VDBG("Bus reset"); 2207 VDBG("Bus reset");
1851 /* Bus is reseting */
1852 udc->bus_reset = 1;
1853 /* Reset all the queues, include XD, dTD, EP queue 2208 /* Reset all the queues, include XD, dTD, EP queue
1854 * head and TR Queue */ 2209 * head and TR Queue */
1855 reset_queues(udc); 2210 reset_queues(udc);
@@ -1869,8 +2224,63 @@ static void reset_irq(struct fsl_udc *udc)
1869 dr_controller_run(udc); 2224 dr_controller_run(udc);
1870 udc->usb_state = USB_STATE_ATTACHED; 2225 udc->usb_state = USB_STATE_ATTACHED;
1871 } 2226 }
2227#endif
2228}
2229
2230static void fsl_udc_set_current_limit_work(struct work_struct* work)
2231{
2232 struct fsl_udc *udc = container_of (work, struct fsl_udc, charger_work);
2233
2234 /* check udc regulator is available for drawing vbus current*/
2235 if (udc->vbus_regulator) {
2236 /* set the current limit in uA */
2237 regulator_set_current_limit(
2238 udc->vbus_regulator, 0,
2239 udc->current_limit *1000);
2240 }
2241}
2242
2243/*
2244 * If VBUS is detected and setup packet is not received in 100ms then
2245 * work thread starts and checks for the USB charger detection.
2246 */
2247static void fsl_udc_charger_detect_work(struct work_struct* work)
2248{
2249 struct fsl_udc *udc = container_of (work, struct fsl_udc, work.work);
2250
2251 /* check for the platform charger detection */
2252 if (fsl_udc_charger_detect()) {
2253 printk(KERN_INFO "USB compliant charger detected\n");
2254 /* check udc regulator is available for drawing vbus current*/
2255 if (udc->vbus_regulator) {
2256 /* set the current limit in uA */
2257 regulator_set_current_limit(
2258 udc->vbus_regulator, 0,
2259 USB_CHARGING_CURRENT_LIMIT_MA*1000);
2260 }
2261 }
1872} 2262}
1873 2263
2264#if defined(CONFIG_ARCH_TEGRA)
2265/*
2266 * Restart device controller in the OTG mode on VBUS detection
2267 */
2268static void fsl_udc_restart(struct fsl_udc *udc)
2269{
2270 /* setup the controller in the device mode */
2271 dr_controller_setup(udc);
2272 /* setup EP0 for setup packet */
2273 ep0_setup(udc);
2274 /* start the controller */
2275 dr_controller_run(udc);
2276 /* initialize the USB and EP states */
2277 udc->usb_state = USB_STATE_ATTACHED;
2278 udc->ep0_state = WAIT_FOR_SETUP;
2279 udc->ep0_dir = 0;
2280 udc->vbus_active = 1;
2281}
2282#endif
2283
1874/* 2284/*
1875 * USB device controller interrupt handler 2285 * USB device controller interrupt handler
1876 */ 2286 */
@@ -1881,10 +2291,26 @@ static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1881 irqreturn_t status = IRQ_NONE; 2291 irqreturn_t status = IRQ_NONE;
1882 unsigned long flags; 2292 unsigned long flags;
1883 2293
2294 spin_lock_irqsave(&udc->lock, flags);
2295
1884 /* Disable ISR for OTG host mode */ 2296 /* Disable ISR for OTG host mode */
1885 if (udc->stopped) 2297 if (udc->stopped) {
2298 spin_unlock_irqrestore(&udc->lock, flags);
1886 return IRQ_NONE; 2299 return IRQ_NONE;
1887 spin_lock_irqsave(&udc->lock, flags); 2300 }
2301
2302#ifdef CONFIG_ARCH_TEGRA
2303 /* Fence read for coherency of AHB master intiated writes */
2304 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
2305#endif
2306#ifndef CONFIG_TEGRA_SILICON_PLATFORM
2307 {
2308 u32 temp = fsl_readl(&usb_sys_regs->vbus_sensors);
2309 udc->vbus_active = (temp & USB_SYS_VBUS_ASESSION) ? true : false;
2310 /* write back the register to clear the interrupt */
2311 fsl_writel(temp, &usb_sys_regs->vbus_sensors);
2312 }
2313#endif
1888 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr); 2314 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1889 /* Clear notification bits */ 2315 /* Clear notification bits */
1890 fsl_writel(irq_src, &dr_regs->usbsts); 2316 fsl_writel(irq_src, &dr_regs->usbsts);
@@ -1901,6 +2327,9 @@ static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1901 VDBG("Packet int"); 2327 VDBG("Packet int");
1902 /* Setup package, we only support ep0 as control ep */ 2328 /* Setup package, we only support ep0 as control ep */
1903 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) { 2329 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
2330 /* Setup packet received, we are connected to host and
2331 * not charger. Cancel any delayed work */
2332 __cancel_delayed_work(&udc->work);
1904 tripwire_handler(udc, 0, 2333 tripwire_handler(udc, 0,
1905 (u8 *) (&udc->local_setup_buff)); 2334 (u8 *) (&udc->local_setup_buff));
1906 setup_received_irq(udc, &udc->local_setup_buff); 2335 setup_received_irq(udc, &udc->local_setup_buff);
@@ -1927,7 +2356,6 @@ static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1927 2356
1928 /* Reset Received */ 2357 /* Reset Received */
1929 if (irq_src & USB_STS_RESET) { 2358 if (irq_src & USB_STS_RESET) {
1930 VDBG("reset int");
1931 reset_irq(udc); 2359 reset_irq(udc);
1932 status = IRQ_HANDLED; 2360 status = IRQ_HANDLED;
1933 } 2361 }
@@ -1951,7 +2379,7 @@ static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1951 * Called by initialization code of gadget drivers 2379 * Called by initialization code of gadget drivers
1952*----------------------------------------------------------------*/ 2380*----------------------------------------------------------------*/
1953static int fsl_start(struct usb_gadget_driver *driver, 2381static int fsl_start(struct usb_gadget_driver *driver,
1954 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *)) 2382 int (*bind)(struct usb_gadget *))
1955{ 2383{
1956 int retval = -ENODEV; 2384 int retval = -ENODEV;
1957 unsigned long flags = 0; 2385 unsigned long flags = 0;
@@ -1959,7 +2387,8 @@ static int fsl_start(struct usb_gadget_driver *driver,
1959 if (!udc_controller) 2387 if (!udc_controller)
1960 return -ENODEV; 2388 return -ENODEV;
1961 2389
1962 if (!driver || driver->max_speed < USB_SPEED_FULL 2390 if (!driver || (driver->speed != USB_SPEED_FULL
2391 && driver->speed != USB_SPEED_HIGH)
1963 || !bind || !driver->disconnect || !driver->setup) 2392 || !bind || !driver->disconnect || !driver->setup)
1964 return -EINVAL; 2393 return -EINVAL;
1965 2394
@@ -1976,7 +2405,7 @@ static int fsl_start(struct usb_gadget_driver *driver,
1976 spin_unlock_irqrestore(&udc_controller->lock, flags); 2405 spin_unlock_irqrestore(&udc_controller->lock, flags);
1977 2406
1978 /* bind udc driver to gadget driver */ 2407 /* bind udc driver to gadget driver */
1979 retval = bind(&udc_controller->gadget, driver); 2408 retval = bind(&udc_controller->gadget);
1980 if (retval) { 2409 if (retval) {
1981 VDBG("bind to %s --> %d", driver->driver.name, retval); 2410 VDBG("bind to %s --> %d", driver->driver.name, retval);
1982 udc_controller->gadget.dev.driver = NULL; 2411 udc_controller->gadget.dev.driver = NULL;
@@ -1984,31 +2413,14 @@ static int fsl_start(struct usb_gadget_driver *driver,
1984 goto out; 2413 goto out;
1985 } 2414 }
1986 2415
1987 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) { 2416 /* Enable DR IRQ reg and Set usbcmd reg Run bit */
1988 /* Suspend the controller until OTG enable it */ 2417 if (!udc_controller->transceiver) {
1989 udc_controller->stopped = 1;
1990 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1991
1992 /* connect to bus through transceiver */
1993 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1994 retval = otg_set_peripheral(
1995 udc_controller->transceiver->otg,
1996 &udc_controller->gadget);
1997 if (retval < 0) {
1998 ERR("can't bind to transceiver\n");
1999 driver->unbind(&udc_controller->gadget);
2000 udc_controller->gadget.dev.driver = 0;
2001 udc_controller->driver = 0;
2002 return retval;
2003 }
2004 }
2005 } else {
2006 /* Enable DR IRQ reg and set USBCMD reg Run bit */
2007 dr_controller_run(udc_controller); 2418 dr_controller_run(udc_controller);
2008 udc_controller->usb_state = USB_STATE_ATTACHED; 2419 udc_controller->usb_state = USB_STATE_ATTACHED;
2009 udc_controller->ep0_state = WAIT_FOR_SETUP; 2420 udc_controller->ep0_state = WAIT_FOR_SETUP;
2010 udc_controller->ep0_dir = 0; 2421 udc_controller->ep0_dir = 0;
2011 } 2422 }
2423
2012 printk(KERN_INFO "%s: bind to driver %s\n", 2424 printk(KERN_INFO "%s: bind to driver %s\n",
2013 udc_controller->gadget.name, driver->driver.name); 2425 udc_controller->gadget.name, driver->driver.name);
2014 2426
@@ -2031,9 +2443,6 @@ static int fsl_stop(struct usb_gadget_driver *driver)
2031 if (!driver || driver != udc_controller->driver || !driver->unbind) 2443 if (!driver || driver != udc_controller->driver || !driver->unbind)
2032 return -EINVAL; 2444 return -EINVAL;
2033 2445
2034 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2035 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
2036
2037 /* stop DR, disable intr */ 2446 /* stop DR, disable intr */
2038 dr_controller_stop(udc_controller); 2447 dr_controller_stop(udc_controller);
2039 2448
@@ -2071,7 +2480,11 @@ static int fsl_stop(struct usb_gadget_driver *driver)
2071 2480
2072#include <linux/seq_file.h> 2481#include <linux/seq_file.h>
2073 2482
2483#ifdef CONFIG_ARCH_TEGRA
2484static const char proc_filename[] = "driver/fsl_tegra_udc";
2485#else
2074static const char proc_filename[] = "driver/fsl_usb2_udc"; 2486static const char proc_filename[] = "driver/fsl_usb2_udc";
2487#endif
2075 2488
2076static int fsl_proc_read(char *page, char **start, off_t off, int count, 2489static int fsl_proc_read(char *page, char **start, off_t off, int count,
2077 int *eof, void *_dev) 2490 int *eof, void *_dev)
@@ -2082,6 +2495,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
2082 unsigned long flags; 2495 unsigned long flags;
2083 int t, i; 2496 int t, i;
2084 u32 tmp_reg; 2497 u32 tmp_reg;
2498 u32 tmp_reg2;
2085 struct fsl_ep *ep = NULL; 2499 struct fsl_ep *ep = NULL;
2086 struct fsl_req *req; 2500 struct fsl_req *req;
2087 2501
@@ -2126,7 +2540,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
2126 2540
2127 tmp_reg = fsl_readl(&dr_regs->usbintr); 2541 tmp_reg = fsl_readl(&dr_regs->usbintr);
2128 t = scnprintf(next, size, 2542 t = scnprintf(next, size,
2129 "USB Interrupt Enable Reg:\n" 2543 "USB Intrrupt Enable Reg:\n"
2130 "Sleep Enable: %d SOF Received Enable: %d " 2544 "Sleep Enable: %d SOF Received Enable: %d "
2131 "Reset Enable: %d\n" 2545 "Reset Enable: %d\n"
2132 "System Error Enable: %d " 2546 "System Error Enable: %d "
@@ -2165,6 +2579,13 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
2165 next += t; 2579 next += t;
2166 2580
2167 tmp_reg = fsl_readl(&dr_regs->portsc1); 2581 tmp_reg = fsl_readl(&dr_regs->portsc1);
2582#ifdef CONFIG_ARCH_TEGRA_2x_SOC
2583 tmp_reg2 = tmp_reg;
2584#else
2585 /* In Tegra3 the Phy Type Select(PTS) and Port Speed fields are specified in
2586 * hostpc1devlc register instead of portsc1 register. */
2587 tmp_reg2 = fsl_readl(&dr_regs->hostpc1devlc);
2588#endif
2168 t = scnprintf(next, size, 2589 t = scnprintf(next, size,
2169 "USB Port Status&Control Reg:\n" 2590 "USB Port Status&Control Reg:\n"
2170 "Port Transceiver Type : %s Port Speed: %s\n" 2591 "Port Transceiver Type : %s Port Speed: %s\n"
@@ -2175,7 +2596,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
2175 "Port Enabled/Disabled: %s " 2596 "Port Enabled/Disabled: %s "
2176 "Current Connect Status: %s\n\n", ( { 2597 "Current Connect Status: %s\n\n", ( {
2177 char *s; 2598 char *s;
2178 switch (tmp_reg & PORTSCX_PTS_FSLS) { 2599 switch (tmp_reg2 & PORTSCX_PTS_FSLS) {
2179 case PORTSCX_PTS_UTMI: 2600 case PORTSCX_PTS_UTMI:
2180 s = "UTMI"; break; 2601 s = "UTMI"; break;
2181 case PORTSCX_PTS_ULPI: 2602 case PORTSCX_PTS_ULPI:
@@ -2185,8 +2606,20 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
2185 default: 2606 default:
2186 s = "None"; break; 2607 s = "None"; break;
2187 } 2608 }
2188 s;} ), 2609 s;} ), ( {
2189 usb_speed_string(portscx_device_speed(tmp_reg)), 2610 char *s;
2611 switch (tmp_reg2 & PORTSCX_PORT_SPEED_UNDEF) {
2612 case PORTSCX_PORT_SPEED_FULL:
2613 s = "Full Speed"; break;
2614 case PORTSCX_PORT_SPEED_LOW:
2615 s = "Low Speed"; break;
2616 case PORTSCX_PORT_SPEED_HIGH:
2617 s = "High Speed"; break;
2618 default:
2619 s = "Undefined"; break;
2620 }
2621 s;
2622 } ),
2190 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ? 2623 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2191 "Normal PHY mode" : "Low power mode", 2624 "Normal PHY mode" : "Low power mode",
2192 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" : 2625 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
@@ -2241,7 +2674,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
2241 size -= t; 2674 size -= t;
2242 next += t; 2675 next += t;
2243 2676
2244#ifndef CONFIG_ARCH_MXC 2677#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
2245 if (udc->pdata->have_sysif_regs) { 2678 if (udc->pdata->have_sysif_regs) {
2246 tmp_reg = usb_sys_regs->snoop1; 2679 tmp_reg = usb_sys_regs->snoop1;
2247 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg); 2680 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
@@ -2279,7 +2712,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
2279 } 2712 }
2280 /* other gadget->eplist ep */ 2713 /* other gadget->eplist ep */
2281 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { 2714 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2282 if (ep->ep.desc) { 2715 if (ep->desc) {
2283 t = scnprintf(next, size, 2716 t = scnprintf(next, size,
2284 "\nFor %s Maxpkt is 0x%x " 2717 "\nFor %s Maxpkt is 0x%x "
2285 "index is 0x%x\n", 2718 "index is 0x%x\n",
@@ -2358,6 +2791,13 @@ static int __init struct_udc_setup(struct fsl_udc *udc,
2358 return -1; 2791 return -1;
2359 } 2792 }
2360 2793
2794#ifdef CONFIG_ARCH_TEGRA
2795 /* Tegra uses hardware queue heads */
2796 size = udc->max_ep * sizeof(struct ep_queue_head);
2797 udc->ep_qh = (struct ep_queue_head *)((u8 *)dr_regs + QH_OFFSET);
2798 udc->ep_qh_dma = platform_get_resource(pdev, IORESOURCE_MEM, 0)->start +
2799 QH_OFFSET;
2800#else
2361 /* initialized QHs, take care of alignment */ 2801 /* initialized QHs, take care of alignment */
2362 size = udc->max_ep * sizeof(struct ep_queue_head); 2802 size = udc->max_ep * sizeof(struct ep_queue_head);
2363 if (size < QH_ALIGNMENT) 2803 if (size < QH_ALIGNMENT)
@@ -2373,6 +2813,7 @@ static int __init struct_udc_setup(struct fsl_udc *udc,
2373 kfree(udc->eps); 2813 kfree(udc->eps);
2374 return -1; 2814 return -1;
2375 } 2815 }
2816#endif
2376 2817
2377 udc->ep_qh_size = size; 2818 udc->ep_qh_size = size;
2378 2819
@@ -2437,6 +2878,9 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
2437 int ret = -ENODEV; 2878 int ret = -ENODEV;
2438 unsigned int i; 2879 unsigned int i;
2439 u32 dccparams; 2880 u32 dccparams;
2881#if defined(CONFIG_ARCH_TEGRA)
2882 struct resource *res_sys = NULL;
2883#endif
2440 2884
2441 if (strcmp(pdev->name, driver_name)) { 2885 if (strcmp(pdev->name, driver_name)) {
2442 VDBG("Wrong device"); 2886 VDBG("Wrong device");
@@ -2454,30 +2898,17 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
2454 spin_lock_init(&udc_controller->lock); 2898 spin_lock_init(&udc_controller->lock);
2455 udc_controller->stopped = 1; 2899 udc_controller->stopped = 1;
2456 2900
2457#ifdef CONFIG_USB_OTG
2458 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2459 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2460 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2461 ERR("Can't find OTG driver!\n");
2462 ret = -ENODEV;
2463 goto err_kfree;
2464 }
2465 }
2466#endif
2467
2468 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2901 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2469 if (!res) { 2902 if (!res) {
2470 ret = -ENXIO; 2903 ret = -ENXIO;
2471 goto err_kfree; 2904 goto err_kfree;
2472 } 2905 }
2473 2906
2474 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) { 2907 if (!request_mem_region(res->start, resource_size(res),
2475 if (!request_mem_region(res->start, resource_size(res), 2908 driver_name)) {
2476 driver_name)) { 2909 ERR("request mem region for %s failed\n", pdev->name);
2477 ERR("request mem region for %s failed\n", pdev->name); 2910 ret = -EBUSY;
2478 ret = -EBUSY; 2911 goto err_kfree;
2479 goto err_kfree;
2480 }
2481 } 2912 }
2482 2913
2483 dr_regs = ioremap(res->start, resource_size(res)); 2914 dr_regs = ioremap(res->start, resource_size(res));
@@ -2499,9 +2930,29 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
2499 /* Set accessors only after pdata->init() ! */ 2930 /* Set accessors only after pdata->init() ! */
2500 fsl_set_accessors(pdata); 2931 fsl_set_accessors(pdata);
2501 2932
2502#ifndef CONFIG_ARCH_MXC 2933#if defined(CONFIG_ARCH_TEGRA)
2934 /* If the PHY registers are NOT provided as a seperate aperture, then
2935 * we should be using the registers inside the controller aperture. */
2936 res_sys = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2937 if (res_sys) {
2938 usb_sys_regs = ioremap(res_sys->start, resource_size(res_sys));
2939 if (!usb_sys_regs)
2940 goto err_release_mem_region;
2941 } else {
2942 usb_sys_regs = (struct usb_sys_interface *)
2943 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2944 }
2945#endif
2946
2947#ifdef CONFIG_ARCH_TEGRA_2x_SOC
2948 control_reg = &dr_regs->portsc1;
2949#else
2950 control_reg = &dr_regs->hostpc1devlc;
2951#endif
2952#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
2503 if (pdata->have_sysif_regs) 2953 if (pdata->have_sysif_regs)
2504 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET; 2954 usb_sys_regs = (struct usb_sys_interface *)
2955 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2505#endif 2956#endif
2506 2957
2507 /* Initialize USB clocks */ 2958 /* Initialize USB clocks */
@@ -2541,17 +2992,15 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
2541 goto err_free_irq; 2992 goto err_free_irq;
2542 } 2993 }
2543 2994
2544 if (IS_ERR_OR_NULL(udc_controller->transceiver)) { 2995 /* initialize usb hw reg except for regs for EP,
2545 /* initialize usb hw reg except for regs for EP, 2996 * leave usbintr reg untouched */
2546 * leave usbintr reg untouched */ 2997 dr_controller_setup(udc_controller);
2547 dr_controller_setup(udc_controller);
2548 }
2549 2998
2550 fsl_udc_clk_finalize(pdev); 2999 fsl_udc_clk_finalize(pdev);
2551 3000
2552 /* Setup gadget structure */ 3001 /* Setup gadget structure */
2553 udc_controller->gadget.ops = &fsl_gadget_ops; 3002 udc_controller->gadget.ops = &fsl_gadget_ops;
2554 udc_controller->gadget.max_speed = USB_SPEED_HIGH; 3003 udc_controller->gadget.is_dualspeed = 1;
2555 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep; 3004 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2556 INIT_LIST_HEAD(&udc_controller->gadget.ep_list); 3005 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2557 udc_controller->gadget.speed = USB_SPEED_UNKNOWN; 3006 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
@@ -2561,14 +3010,10 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
2561 dev_set_name(&udc_controller->gadget.dev, "gadget"); 3010 dev_set_name(&udc_controller->gadget.dev, "gadget");
2562 udc_controller->gadget.dev.release = fsl_udc_release; 3011 udc_controller->gadget.dev.release = fsl_udc_release;
2563 udc_controller->gadget.dev.parent = &pdev->dev; 3012 udc_controller->gadget.dev.parent = &pdev->dev;
2564 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2565 ret = device_register(&udc_controller->gadget.dev); 3013 ret = device_register(&udc_controller->gadget.dev);
2566 if (ret < 0) 3014 if (ret < 0)
2567 goto err_free_irq; 3015 goto err_free_irq;
2568 3016
2569 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2570 udc_controller->gadget.is_otg = 1;
2571
2572 /* setup QH and epctrl for ep0 */ 3017 /* setup QH and epctrl for ep0 */
2573 ep0_setup(udc_controller); 3018 ep0_setup(udc_controller);
2574 3019
@@ -2577,7 +3022,7 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
2577 /* for ep0: the desc defined here; 3022 /* for ep0: the desc defined here;
2578 * for other eps, gadget layer called ep_enable with defined desc 3023 * for other eps, gadget layer called ep_enable with defined desc
2579 */ 3024 */
2580 udc_controller->eps[0].ep.desc = &fsl_ep0_desc; 3025 udc_controller->eps[0].desc = &fsl_ep0_desc;
2581 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD; 3026 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2582 3027
2583 /* setup the udc->eps[] for non-control endpoints and link 3028 /* setup the udc->eps[] for non-control endpoints and link
@@ -2605,6 +3050,38 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
2605 goto err_del_udc; 3050 goto err_del_udc;
2606 3051
2607 create_proc_file(); 3052 create_proc_file();
3053
3054 /* create a delayed work for detecting the USB charger */
3055 INIT_DELAYED_WORK(&udc_controller->work, fsl_udc_charger_detect_work);
3056 INIT_WORK(&udc_controller->charger_work, fsl_udc_set_current_limit_work);
3057
3058 /* Get the regulator for drawing the vbus current in udc driver */
3059 udc_controller->vbus_regulator = regulator_get(NULL, "usb_bat_chg");
3060 if (IS_ERR(udc_controller->vbus_regulator)) {
3061 dev_info(&pdev->dev,
3062 "usb_bat_chg regulator not registered:"
3063 " USB charging will not be enabled\n");
3064 udc_controller->vbus_regulator = NULL;
3065 }
3066
3067#ifdef CONFIG_USB_OTG_UTILS
3068 udc_controller->transceiver = otg_get_transceiver();
3069 if (udc_controller->transceiver) {
3070 dr_controller_stop(udc_controller);
3071 dr_controller_reset(udc_controller);
3072 fsl_udc_clk_suspend(false);
3073 udc_controller->vbus_active = 0;
3074 udc_controller->usb_state = USB_STATE_DEFAULT;
3075 otg_set_peripheral(udc_controller->transceiver, &udc_controller->gadget);
3076 }
3077#else
3078#ifdef CONFIG_ARCH_TEGRA
3079 /* Power down the phy if cable is not connected */
3080 if(!vbus_enabled())
3081 fsl_udc_clk_suspend(false);
3082#endif
3083#endif
3084
2608 return 0; 3085 return 0;
2609 3086
2610err_del_udc: 3087err_del_udc:
@@ -2620,8 +3097,7 @@ err_iounmap:
2620err_iounmap_noclk: 3097err_iounmap_noclk:
2621 iounmap(dr_regs); 3098 iounmap(dr_regs);
2622err_release_mem_region: 3099err_release_mem_region:
2623 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) 3100 release_mem_region(res->start, resource_size(res));
2624 release_mem_region(res->start, resource_size(res));
2625err_kfree: 3101err_kfree:
2626 kfree(udc_controller); 3102 kfree(udc_controller);
2627 udc_controller = NULL; 3103 udc_controller = NULL;
@@ -2644,6 +3120,13 @@ static int __exit fsl_udc_remove(struct platform_device *pdev)
2644 usb_del_gadget_udc(&udc_controller->gadget); 3120 usb_del_gadget_udc(&udc_controller->gadget);
2645 udc_controller->done = &done; 3121 udc_controller->done = &done;
2646 3122
3123 cancel_delayed_work(&udc_controller->work);
3124 if (udc_controller->vbus_regulator)
3125 regulator_put(udc_controller->vbus_regulator);
3126
3127 if (udc_controller->transceiver)
3128 otg_set_peripheral(udc_controller->transceiver, NULL);
3129
2647 fsl_udc_clk_release(); 3130 fsl_udc_clk_release();
2648 3131
2649 /* DR has been stopped in usb_gadget_unregister_driver() */ 3132 /* DR has been stopped in usb_gadget_unregister_driver() */
@@ -2657,8 +3140,7 @@ static int __exit fsl_udc_remove(struct platform_device *pdev)
2657 dma_pool_destroy(udc_controller->td_pool); 3140 dma_pool_destroy(udc_controller->td_pool);
2658 free_irq(udc_controller->irq, udc_controller); 3141 free_irq(udc_controller->irq, udc_controller);
2659 iounmap(dr_regs); 3142 iounmap(dr_regs);
2660 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) 3143 release_mem_region(res->start, resource_size(res));
2661 release_mem_region(res->start, resource_size(res));
2662 3144
2663 device_unregister(&udc_controller->gadget.dev); 3145 device_unregister(&udc_controller->gadget.dev);
2664 /* free udc --wait for the release() finished */ 3146 /* free udc --wait for the release() finished */
@@ -2680,8 +3162,27 @@ static int __exit fsl_udc_remove(struct platform_device *pdev)
2680 -----------------------------------------------------------------*/ 3162 -----------------------------------------------------------------*/
2681static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state) 3163static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2682{ 3164{
2683 dr_controller_stop(udc_controller); 3165 if (udc_controller->transceiver) {
2684 return 0; 3166 if (udc_controller->transceiver->state != OTG_STATE_B_PERIPHERAL) {
3167 /* we are not in device mode, return */
3168 return 0;
3169 }
3170 }
3171 if (udc_controller->vbus_active) {
3172 spin_lock(&udc_controller->lock);
3173 /* Reset all internal Queues and inform client driver */
3174 reset_queues(udc_controller);
3175 udc_controller->vbus_active = 0;
3176 udc_controller->usb_state = USB_STATE_DEFAULT;
3177 spin_unlock(&udc_controller->lock);
3178 }
3179 /* stop the controller and turn off the clocks */
3180 dr_controller_stop(udc_controller);
3181 if (udc_controller->transceiver) {
3182 udc_controller->transceiver->state = OTG_STATE_UNDEFINED;
3183 }
3184 fsl_udc_clk_suspend(true);
3185 return 0;
2685} 3186}
2686 3187
2687/*----------------------------------------------------------------- 3188/*-----------------------------------------------------------------
@@ -2690,6 +3191,30 @@ static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2690 *-----------------------------------------------------------------*/ 3191 *-----------------------------------------------------------------*/
2691static int fsl_udc_resume(struct platform_device *pdev) 3192static int fsl_udc_resume(struct platform_device *pdev)
2692{ 3193{
3194 if (udc_controller->transceiver) {
3195 fsl_udc_clk_resume(true);
3196 if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_ID_PIN_STATUS)) {
3197 /* If ID status is low means host is connected, return */
3198 fsl_udc_clk_suspend(false);
3199 return 0;
3200 }
3201 /* check for VBUS */
3202 if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS)) {
3203 /* if there is no VBUS then power down the clocks and return */
3204 fsl_udc_clk_suspend(false);
3205 return 0;
3206 } else {
3207 fsl_udc_clk_suspend(false);
3208 if (udc_controller->transceiver->state == OTG_STATE_A_HOST)
3209 return 0;
3210 /* Detected VBUS set the transceiver state to device mode */
3211 udc_controller->transceiver->state = OTG_STATE_B_PERIPHERAL;
3212 }
3213 }
3214 fsl_udc_clk_resume(true);
3215#if defined(CONFIG_ARCH_TEGRA)
3216 fsl_udc_restart(udc_controller);
3217#else
2693 /* Enable DR irq reg and set controller Run */ 3218 /* Enable DR irq reg and set controller Run */
2694 if (udc_controller->stopped) { 3219 if (udc_controller->stopped) {
2695 dr_controller_setup(udc_controller); 3220 dr_controller_setup(udc_controller);
@@ -2698,65 +3223,14 @@ static int fsl_udc_resume(struct platform_device *pdev)
2698 udc_controller->usb_state = USB_STATE_ATTACHED; 3223 udc_controller->usb_state = USB_STATE_ATTACHED;
2699 udc_controller->ep0_state = WAIT_FOR_SETUP; 3224 udc_controller->ep0_state = WAIT_FOR_SETUP;
2700 udc_controller->ep0_dir = 0; 3225 udc_controller->ep0_dir = 0;
2701 return 0; 3226#endif
2702} 3227 /* Power down the phy if cable is not connected */
2703 3228 if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS))
2704static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state) 3229 fsl_udc_clk_suspend(false);
2705{
2706 struct fsl_udc *udc = udc_controller;
2707 u32 mode, usbcmd;
2708
2709 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2710
2711 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2712
2713 /*
2714 * If the controller is already stopped, then this must be a
2715 * PM suspend. Remember this fact, so that we will leave the
2716 * controller stopped at PM resume time.
2717 */
2718 if (udc->stopped) {
2719 pr_debug("gadget already stopped, leaving early\n");
2720 udc->already_stopped = 1;
2721 return 0;
2722 }
2723
2724 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2725 pr_debug("gadget not in device mode, leaving early\n");
2726 return 0;
2727 }
2728
2729 /* stop the controller */
2730 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2731 fsl_writel(usbcmd, &dr_regs->usbcmd);
2732
2733 udc->stopped = 1;
2734
2735 pr_info("USB Gadget suspended\n");
2736 3230
2737 return 0; 3231 return 0;
2738} 3232}
2739 3233
2740static int fsl_udc_otg_resume(struct device *dev)
2741{
2742 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2743 udc_controller->stopped, udc_controller->already_stopped);
2744
2745 /*
2746 * If the controller was stopped at suspend time, then
2747 * don't resume it now.
2748 */
2749 if (udc_controller->already_stopped) {
2750 udc_controller->already_stopped = 0;
2751 pr_debug("gadget was already stopped, leaving early\n");
2752 return 0;
2753 }
2754
2755 pr_info("USB Gadget resume\n");
2756
2757 return fsl_udc_resume(NULL);
2758}
2759
2760/*------------------------------------------------------------------------- 3234/*-------------------------------------------------------------------------
2761 Register entry point for the peripheral controller driver 3235 Register entry point for the peripheral controller driver
2762--------------------------------------------------------------------------*/ 3236--------------------------------------------------------------------------*/
@@ -2769,9 +3243,6 @@ static struct platform_driver udc_driver = {
2769 .driver = { 3243 .driver = {
2770 .name = (char *)driver_name, 3244 .name = (char *)driver_name,
2771 .owner = THIS_MODULE, 3245 .owner = THIS_MODULE,
2772 /* udc suspend/resume called from OTG driver */
2773 .suspend = fsl_udc_otg_suspend,
2774 .resume = fsl_udc_otg_resume,
2775 }, 3246 },
2776}; 3247};
2777 3248
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 03:24:48 -0400