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authorArend van Spriel <arend@broadcom.com>2011-10-07 10:24:40 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-10-12 11:21:18 -0400
commitfc2d6e573be68ac7b5a0730981fe9444ea2e2eaf (patch)
treee60b944a62ebafb3d717a410541481510b8bab6c /drivers/staging
parent54ced00639aa90c92e0ce399cc84ca6fc6a2eebb (diff)
staging: brcm80211: remove brcm80211 driver from the staging tree
With the mainline patch being applied to the wireless-next repository by John Linville this driver is no longer needed under the staging directory. This patch ends its life under the staging tree. Cc: John W. Linville <linville@tuxdriver.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging')
-rw-r--r--drivers/staging/Kconfig2
-rw-r--r--drivers/staging/Makefile2
-rw-r--r--drivers/staging/brcm80211/Kconfig35
-rw-r--r--drivers/staging/brcm80211/Makefile23
-rw-r--r--drivers/staging/brcm80211/README1
-rw-r--r--drivers/staging/brcm80211/TODO9
-rw-r--r--drivers/staging/brcm80211/brcmfmac/Makefile33
-rw-r--r--drivers/staging/brcm80211/brcmfmac/bcmchip.h32
-rw-r--r--drivers/staging/brcm80211/brcmfmac/bcmsdh.c371
-rw-r--r--drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c625
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd.h773
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_bus.h57
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_cdc.c498
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_common.c872
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_dbg.h58
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_linux.c1354
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_proto.h60
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_sdio.c4581
-rw-r--r--drivers/staging/brcm80211/brcmfmac/sdio_host.h252
-rw-r--r--drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c3730
-rw-r--r--drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h375
-rw-r--r--drivers/staging/brcm80211/brcmsmac/Makefile51
-rw-r--r--drivers/staging/brcm80211/brcmsmac/aiutils.c2079
-rw-r--r--drivers/staging/brcm80211/brcmsmac/aiutils.h378
-rw-r--r--drivers/staging/brcm80211/brcmsmac/ampdu.c1241
-rw-r--r--drivers/staging/brcm80211/brcmsmac/ampdu.h30
-rw-r--r--drivers/staging/brcm80211/brcmsmac/antsel.c308
-rw-r--r--drivers/staging/brcm80211/brcmsmac/antsel.h29
-rw-r--r--drivers/staging/brcm80211/brcmsmac/brcms_trace_events.c23
-rw-r--r--drivers/staging/brcm80211/brcmsmac/brcms_trace_events.h92
-rw-r--r--drivers/staging/brcm80211/brcmsmac/channel.c1565
-rw-r--r--drivers/staging/brcm80211/brcmsmac/channel.h53
-rw-r--r--drivers/staging/brcm80211/brcmsmac/d11.h1898
-rw-r--r--drivers/staging/brcm80211/brcmsmac/dma.c1425
-rw-r--r--drivers/staging/brcm80211/brcmsmac/dma.h120
-rw-r--r--drivers/staging/brcm80211/brcmsmac/mac80211_if.c1701
-rw-r--r--drivers/staging/brcm80211/brcmsmac/mac80211_if.h107
-rw-r--r--drivers/staging/brcm80211/brcmsmac/main.c8841
-rw-r--r--drivers/staging/brcm80211/brcmsmac/main.h819
-rw-r--r--drivers/staging/brcm80211/brcmsmac/nicpci.c835
-rw-r--r--drivers/staging/brcm80211/brcmsmac/nicpci.h82
-rw-r--r--drivers/staging/brcm80211/brcmsmac/otp.c426
-rw-r--r--drivers/staging/brcm80211/brcmsmac/otp.h36
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c2988
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h301
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_int.h1169
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c5154
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.h121
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_n.c28876
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.c308
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.h42
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_radio.h1533
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h167
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.c3250
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.h54
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.c10630
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.h50
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy_shim.c226
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy_shim.h185
-rw-r--r--drivers/staging/brcm80211/brcmsmac/pmu.c458
-rw-r--r--drivers/staging/brcm80211/brcmsmac/pmu.h38
-rw-r--r--drivers/staging/brcm80211/brcmsmac/pub.h655
-rw-r--r--drivers/staging/brcm80211/brcmsmac/rate.c514
-rw-r--r--drivers/staging/brcm80211/brcmsmac/rate.h250
-rw-r--r--drivers/staging/brcm80211/brcmsmac/scb.h82
-rw-r--r--drivers/staging/brcm80211/brcmsmac/srom.c1298
-rw-r--r--drivers/staging/brcm80211/brcmsmac/srom.h34
-rw-r--r--drivers/staging/brcm80211/brcmsmac/stf.c438
-rw-r--r--drivers/staging/brcm80211/brcmsmac/stf.h42
-rw-r--r--drivers/staging/brcm80211/brcmsmac/types.h352
-rw-r--r--drivers/staging/brcm80211/brcmsmac/ucode_loader.c109
-rw-r--r--drivers/staging/brcm80211/brcmsmac/ucode_loader.h58
-rw-r--r--drivers/staging/brcm80211/brcmutil/Makefile29
-rw-r--r--drivers/staging/brcm80211/brcmutil/utils.c600
-rw-r--r--drivers/staging/brcm80211/brcmutil/wifi.c136
-rw-r--r--drivers/staging/brcm80211/include/brcm_hw_ids.h59
-rw-r--r--drivers/staging/brcm80211/include/brcmu_utils.h223
-rw-r--r--drivers/staging/brcm80211/include/brcmu_wifi.h275
-rw-r--r--drivers/staging/brcm80211/include/chipcommon.h284
-rw-r--r--drivers/staging/brcm80211/include/defs.h104
-rw-r--r--drivers/staging/brcm80211/include/soc.h90
81 files changed, 0 insertions, 97064 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index eac0a7fd8ef..ece5033b135 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -44,8 +44,6 @@ source "drivers/staging/wlan-ng/Kconfig"
44 44
45source "drivers/staging/echo/Kconfig" 45source "drivers/staging/echo/Kconfig"
46 46
47source "drivers/staging/brcm80211/Kconfig"
48
49source "drivers/staging/comedi/Kconfig" 47source "drivers/staging/comedi/Kconfig"
50 48
51source "drivers/staging/olpc_dcon/Kconfig" 49source "drivers/staging/olpc_dcon/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 20be1129424..bd8267411a6 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -14,8 +14,6 @@ obj-$(CONFIG_USBIP_CORE) += usbip/
14obj-$(CONFIG_W35UND) += winbond/ 14obj-$(CONFIG_W35UND) += winbond/
15obj-$(CONFIG_PRISM2_USB) += wlan-ng/ 15obj-$(CONFIG_PRISM2_USB) += wlan-ng/
16obj-$(CONFIG_ECHO) += echo/ 16obj-$(CONFIG_ECHO) += echo/
17obj-$(CONFIG_BRCMSMAC) += brcm80211/
18obj-$(CONFIG_BRCMFMAC) += brcm80211/
19obj-$(CONFIG_COMEDI) += comedi/ 17obj-$(CONFIG_COMEDI) += comedi/
20obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/ 18obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/
21obj-$(CONFIG_ASUS_OLED) += asus_oled/ 19obj-$(CONFIG_ASUS_OLED) += asus_oled/
diff --git a/drivers/staging/brcm80211/Kconfig b/drivers/staging/brcm80211/Kconfig
deleted file mode 100644
index f51e0f17d70..00000000000
--- a/drivers/staging/brcm80211/Kconfig
+++ /dev/null
@@ -1,35 +0,0 @@
1config BRCMUTIL
2 tristate
3
4config BRCMSMAC
5 tristate "Broadcom IEEE802.11n PCIe SoftMAC WLAN driver"
6 depends on PCI
7 depends on WLAN && MAC80211
8 depends on BCMA=n
9 select BRCMUTIL
10 select FW_LOADER
11 select CRC_CCITT
12 select CRC8
13 select CORDIC
14 ---help---
15 This module adds support for PCIe wireless adapters based on Broadcom
16 IEEE802.11n SoftMAC chipsets. If you choose to build a module, it'll
17 be called brcmsmac.ko.
18
19config BRCMFMAC
20 tristate "Broadcom IEEE802.11n embedded FullMAC WLAN driver"
21 depends on MMC
22 depends on WLAN && CFG80211
23 select BRCMUTIL
24 select FW_LOADER
25 ---help---
26 This module adds support for embedded wireless adapters based on
27 Broadcom IEEE802.11n FullMAC chipsets. This driver uses the kernel's
28 wireless extensions subsystem. If you choose to build a module,
29 it'll be called brcmfmac.ko.
30
31config BRCMDBG
32 bool "Broadcom driver debug functions"
33 depends on BRCMSMAC || BRCMFMAC
34 ---help---
35 Selecting this enables additional code for debug purposes.
diff --git a/drivers/staging/brcm80211/Makefile b/drivers/staging/brcm80211/Makefile
deleted file mode 100644
index f41c047eca8..00000000000
--- a/drivers/staging/brcm80211/Makefile
+++ /dev/null
@@ -1,23 +0,0 @@
1#
2# Makefile fragment for Broadcom 802.11n Networking Device Driver
3#
4# Copyright (c) 2010 Broadcom Corporation
5#
6# Permission to use, copy, modify, and/or distribute this software for any
7# purpose with or without fee is hereby granted, provided that the above
8# copyright notice and this permission notice appear in all copies.
9#
10# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17
18# common flags
19subdir-ccflags-$(CONFIG_BRCMDBG) += -DBCMDBG
20
21obj-$(CONFIG_BRCMUTIL) += brcmutil/
22obj-$(CONFIG_BRCMFMAC) += brcmfmac/
23obj-$(CONFIG_BRCMSMAC) += brcmsmac/
diff --git a/drivers/staging/brcm80211/README b/drivers/staging/brcm80211/README
deleted file mode 100644
index bb86b1b3e58..00000000000
--- a/drivers/staging/brcm80211/README
+++ /dev/null
@@ -1 +0,0 @@
1refer to: http://linuxwireless.org/en/users/Drivers/brcm80211
diff --git a/drivers/staging/brcm80211/TODO b/drivers/staging/brcm80211/TODO
deleted file mode 100644
index 7f68762b1c3..00000000000
--- a/drivers/staging/brcm80211/TODO
+++ /dev/null
@@ -1,9 +0,0 @@
1To Do List for Broadcom Mac80211 driver before getting in mainline
2
3Bugs
4====
5- none known at this moment
6
7brcm80211 info page
8=====================
9http://linuxwireless.org/en/users/Drivers/brcm80211
diff --git a/drivers/staging/brcm80211/brcmfmac/Makefile b/drivers/staging/brcm80211/brcmfmac/Makefile
deleted file mode 100644
index a1b7637dce3..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/Makefile
+++ /dev/null
@@ -1,33 +0,0 @@
1#
2# Makefile fragment for Broadcom 802.11n Networking Device Driver
3#
4# Copyright (c) 2010 Broadcom Corporation
5#
6# Permission to use, copy, modify, and/or distribute this software for any
7# purpose with or without fee is hereby granted, provided that the above
8# copyright notice and this permission notice appear in all copies.
9#
10# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17
18ccflags-y += \
19 -Idrivers/staging/brcm80211/brcmfmac \
20 -Idrivers/staging/brcm80211/include
21
22DHDOFILES = \
23 wl_cfg80211.o \
24 dhd_cdc.o \
25 dhd_common.o \
26 dhd_sdio.o \
27 dhd_linux.o \
28 bcmsdh.o \
29 bcmsdh_sdmmc.o
30
31obj-$(CONFIG_BRCMFMAC) += brcmfmac.o
32brcmfmac-objs += $(DHDOFILES)
33ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmchip.h b/drivers/staging/brcm80211/brcmfmac/bcmchip.h
deleted file mode 100644
index d7d3afd5a10..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/bcmchip.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _bcmchip_h_
18#define _bcmchip_h_
19
20/* bcm4329 */
21/* SDIO device core, ID 0x829 */
22#define BCM4329_CORE_BUS_BASE 0x18011000
23/* internal memory core, ID 0x80e */
24#define BCM4329_CORE_SOCRAM_BASE 0x18003000
25/* ARM Cortex M3 core, ID 0x82a */
26#define BCM4329_CORE_ARM_BASE 0x18002000
27#define BCM4329_RAMSIZE 0x48000
28/* firmware name */
29#define BCM4329_FW_NAME "brcm/bcm4329-fullmac-4.bin"
30#define BCM4329_NV_NAME "brcm/bcm4329-fullmac-4.txt"
31
32#endif /* _bcmchip_h_ */
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh.c
deleted file mode 100644
index bff9dcd6fad..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/bcmsdh.c
+++ /dev/null
@@ -1,371 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16/* ****************** SDIO CARD Interface Functions **************************/
17
18#include <linux/types.h>
19#include <linux/netdevice.h>
20#include <linux/pci.h>
21#include <linux/pci_ids.h>
22#include <linux/sched.h>
23#include <linux/completion.h>
24#include <linux/mmc/sdio.h>
25#include <linux/mmc/sdio_func.h>
26#include <linux/mmc/card.h>
27
28#include <defs.h>
29#include <brcm_hw_ids.h>
30#include <brcmu_utils.h>
31#include <brcmu_wifi.h>
32#include <soc.h>
33#include "dhd.h"
34#include "dhd_bus.h"
35#include "dhd_dbg.h"
36#include "sdio_host.h"
37
38#define SDIOH_API_ACCESS_RETRY_LIMIT 2
39
40static void brcmf_sdioh_irqhandler(struct sdio_func *func)
41{
42 struct brcmf_sdio_dev *sdiodev = dev_get_drvdata(&func->card->dev);
43
44 brcmf_dbg(TRACE, "***IRQHandler\n");
45
46 sdio_release_host(func);
47
48 brcmf_sdbrcm_isr(sdiodev->bus);
49
50 sdio_claim_host(func);
51}
52
53int brcmf_sdcard_intr_reg(struct brcmf_sdio_dev *sdiodev)
54{
55 brcmf_dbg(TRACE, "Entering\n");
56
57 sdio_claim_host(sdiodev->func[1]);
58 sdio_claim_irq(sdiodev->func[1], brcmf_sdioh_irqhandler);
59 sdio_release_host(sdiodev->func[1]);
60
61 return 0;
62}
63
64int brcmf_sdcard_intr_dereg(struct brcmf_sdio_dev *sdiodev)
65{
66 brcmf_dbg(TRACE, "Entering\n");
67
68 sdio_claim_host(sdiodev->func[1]);
69 sdio_release_irq(sdiodev->func[1]);
70 sdio_release_host(sdiodev->func[1]);
71
72 return 0;
73}
74
75u8 brcmf_sdcard_cfg_read(struct brcmf_sdio_dev *sdiodev, uint fnc_num, u32 addr,
76 int *err)
77{
78 int status;
79 s32 retry = 0;
80 u8 data = 0;
81
82 do {
83 if (retry) /* wait for 1 ms till bus get settled down */
84 udelay(1000);
85 status = brcmf_sdioh_request_byte(sdiodev, SDIOH_READ, fnc_num,
86 addr, (u8 *) &data);
87 } while (status != 0
88 && (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
89 if (err)
90 *err = status;
91
92 brcmf_dbg(INFO, "fun = %d, addr = 0x%x, u8data = 0x%x\n",
93 fnc_num, addr, data);
94
95 return data;
96}
97
98void
99brcmf_sdcard_cfg_write(struct brcmf_sdio_dev *sdiodev, uint fnc_num, u32 addr,
100 u8 data, int *err)
101{
102 int status;
103 s32 retry = 0;
104
105 do {
106 if (retry) /* wait for 1 ms till bus get settled down */
107 udelay(1000);
108 status = brcmf_sdioh_request_byte(sdiodev, SDIOH_WRITE, fnc_num,
109 addr, (u8 *) &data);
110 } while (status != 0
111 && (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
112 if (err)
113 *err = status;
114
115 brcmf_dbg(INFO, "fun = %d, addr = 0x%x, u8data = 0x%x\n",
116 fnc_num, addr, data);
117}
118
119int
120brcmf_sdcard_set_sbaddr_window(struct brcmf_sdio_dev *sdiodev, u32 address)
121{
122 int err = 0;
123 brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
124 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
125 if (!err)
126 brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
127 SBSDIO_FUNC1_SBADDRMID,
128 (address >> 16) & SBSDIO_SBADDRMID_MASK,
129 &err);
130 if (!err)
131 brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
132 SBSDIO_FUNC1_SBADDRHIGH,
133 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
134 &err);
135
136 return err;
137}
138
139u32 brcmf_sdcard_reg_read(struct brcmf_sdio_dev *sdiodev, u32 addr, uint size)
140{
141 int status;
142 u32 word = 0;
143 uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
144
145 brcmf_dbg(INFO, "fun = 1, addr = 0x%x\n", addr);
146
147 if (bar0 != sdiodev->sbwad) {
148 if (brcmf_sdcard_set_sbaddr_window(sdiodev, bar0))
149 return 0xFFFFFFFF;
150
151 sdiodev->sbwad = bar0;
152 }
153
154 addr &= SBSDIO_SB_OFT_ADDR_MASK;
155 if (size == 4)
156 addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
157
158 status = brcmf_sdioh_request_word(sdiodev, SDIOH_READ, SDIO_FUNC_1,
159 addr, &word, size);
160
161 sdiodev->regfail = (status != 0);
162
163 brcmf_dbg(INFO, "u32data = 0x%x\n", word);
164
165 /* if ok, return appropriately masked word */
166 if (status == 0) {
167 switch (size) {
168 case sizeof(u8):
169 return word & 0xff;
170 case sizeof(u16):
171 return word & 0xffff;
172 case sizeof(u32):
173 return word;
174 default:
175 sdiodev->regfail = true;
176
177 }
178 }
179
180 /* otherwise, bad sdio access or invalid size */
181 brcmf_dbg(ERROR, "error reading addr 0x%04x size %d\n", addr, size);
182 return 0xFFFFFFFF;
183}
184
185u32 brcmf_sdcard_reg_write(struct brcmf_sdio_dev *sdiodev, u32 addr, uint size,
186 u32 data)
187{
188 int status;
189 uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
190 int err = 0;
191
192 brcmf_dbg(INFO, "fun = 1, addr = 0x%x, uint%ddata = 0x%x\n",
193 addr, size * 8, data);
194
195 if (bar0 != sdiodev->sbwad) {
196 err = brcmf_sdcard_set_sbaddr_window(sdiodev, bar0);
197 if (err)
198 return err;
199
200 sdiodev->sbwad = bar0;
201 }
202
203 addr &= SBSDIO_SB_OFT_ADDR_MASK;
204 if (size == 4)
205 addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
206 status =
207 brcmf_sdioh_request_word(sdiodev, SDIOH_WRITE, SDIO_FUNC_1,
208 addr, &data, size);
209 sdiodev->regfail = (status != 0);
210
211 if (status == 0)
212 return 0;
213
214 brcmf_dbg(ERROR, "error writing 0x%08x to addr 0x%04x size %d\n",
215 data, addr, size);
216 return 0xFFFFFFFF;
217}
218
219bool brcmf_sdcard_regfail(struct brcmf_sdio_dev *sdiodev)
220{
221 return sdiodev->regfail;
222}
223
224int
225brcmf_sdcard_recv_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
226 uint flags,
227 u8 *buf, uint nbytes, struct sk_buff *pkt)
228{
229 int status;
230 uint incr_fix;
231 uint width;
232 uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
233 int err = 0;
234
235 brcmf_dbg(INFO, "fun = %d, addr = 0x%x, size = %d\n", fn, addr, nbytes);
236
237 /* Async not implemented yet */
238 if (flags & SDIO_REQ_ASYNC)
239 return -ENOTSUPP;
240
241 if (bar0 != sdiodev->sbwad) {
242 err = brcmf_sdcard_set_sbaddr_window(sdiodev, bar0);
243 if (err)
244 return err;
245
246 sdiodev->sbwad = bar0;
247 }
248
249 addr &= SBSDIO_SB_OFT_ADDR_MASK;
250
251 incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
252 width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
253 if (width == 4)
254 addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
255
256 status = brcmf_sdioh_request_buffer(sdiodev, incr_fix, SDIOH_READ,
257 fn, addr, width, nbytes, buf, pkt);
258
259 return status;
260}
261
262int
263brcmf_sdcard_send_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
264 uint flags, u8 *buf, uint nbytes, struct sk_buff *pkt)
265{
266 uint incr_fix;
267 uint width;
268 uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
269 int err = 0;
270
271 brcmf_dbg(INFO, "fun = %d, addr = 0x%x, size = %d\n", fn, addr, nbytes);
272
273 /* Async not implemented yet */
274 if (flags & SDIO_REQ_ASYNC)
275 return -ENOTSUPP;
276
277 if (bar0 != sdiodev->sbwad) {
278 err = brcmf_sdcard_set_sbaddr_window(sdiodev, bar0);
279 if (err)
280 return err;
281
282 sdiodev->sbwad = bar0;
283 }
284
285 addr &= SBSDIO_SB_OFT_ADDR_MASK;
286
287 incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
288 width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
289 if (width == 4)
290 addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
291
292 return brcmf_sdioh_request_buffer(sdiodev, incr_fix, SDIOH_WRITE, fn,
293 addr, width, nbytes, buf, pkt);
294}
295
296int brcmf_sdcard_rwdata(struct brcmf_sdio_dev *sdiodev, uint rw, u32 addr,
297 u8 *buf, uint nbytes)
298{
299 addr &= SBSDIO_SB_OFT_ADDR_MASK;
300 addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
301
302 return brcmf_sdioh_request_buffer(sdiodev, SDIOH_DATA_INC,
303 (rw ? SDIOH_WRITE : SDIOH_READ), SDIO_FUNC_1,
304 addr, 4, nbytes, buf, NULL);
305}
306
307int brcmf_sdcard_abort(struct brcmf_sdio_dev *sdiodev, uint fn)
308{
309 char t_func = (char)fn;
310 brcmf_dbg(TRACE, "Enter\n");
311
312 /* issue abort cmd52 command through F0 */
313 brcmf_sdioh_request_byte(sdiodev, SDIOH_WRITE, SDIO_FUNC_0,
314 SDIO_CCCR_ABORT, &t_func);
315
316 brcmf_dbg(TRACE, "Exit\n");
317 return 0;
318}
319
320int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
321{
322 u32 regs = 0;
323 int ret = 0;
324
325 ret = brcmf_sdioh_attach(sdiodev);
326 if (ret)
327 goto out;
328
329 regs = SI_ENUM_BASE;
330
331 /* Report the BAR, to fix if needed */
332 sdiodev->sbwad = SI_ENUM_BASE;
333
334 /* try to attach to the target device */
335 sdiodev->bus = brcmf_sdbrcm_probe(0, 0, 0, 0, regs, sdiodev);
336 if (!sdiodev->bus) {
337 brcmf_dbg(ERROR, "device attach failed\n");
338 ret = -ENODEV;
339 goto out;
340 }
341
342out:
343 if (ret)
344 brcmf_sdio_remove(sdiodev);
345
346 return ret;
347}
348EXPORT_SYMBOL(brcmf_sdio_probe);
349
350int brcmf_sdio_remove(struct brcmf_sdio_dev *sdiodev)
351{
352 if (sdiodev->bus) {
353 brcmf_sdbrcm_disconnect(sdiodev->bus);
354 sdiodev->bus = NULL;
355 }
356
357 brcmf_sdioh_detach(sdiodev);
358
359 sdiodev->sbwad = 0;
360
361 return 0;
362}
363EXPORT_SYMBOL(brcmf_sdio_remove);
364
365void brcmf_sdio_wdtmr_enable(struct brcmf_sdio_dev *sdiodev, bool enable)
366{
367 if (enable)
368 brcmf_sdbrcm_wd_timer(sdiodev->bus, BRCMF_WD_POLL_MS);
369 else
370 brcmf_sdbrcm_wd_timer(sdiodev->bus, 0);
371}
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
deleted file mode 100644
index e919de210f7..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
+++ /dev/null
@@ -1,625 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#include <linux/types.h>
17#include <linux/netdevice.h>
18#include <linux/mmc/sdio.h>
19#include <linux/mmc/core.h>
20#include <linux/mmc/sdio_func.h>
21#include <linux/mmc/sdio_ids.h>
22#include <linux/mmc/card.h>
23#include <linux/suspend.h>
24#include <linux/errno.h>
25#include <linux/sched.h> /* request_irq() */
26#include <net/cfg80211.h>
27
28#include <defs.h>
29#include <brcm_hw_ids.h>
30#include <brcmu_utils.h>
31#include <brcmu_wifi.h>
32#include "sdio_host.h"
33#include "dhd.h"
34#include "dhd_dbg.h"
35#include "wl_cfg80211.h"
36
37#define SDIO_VENDOR_ID_BROADCOM 0x02d0
38
39#define DMA_ALIGN_MASK 0x03
40
41#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
42
43#define SDIO_FUNC1_BLOCKSIZE 64
44#define SDIO_FUNC2_BLOCKSIZE 512
45
46/* devices we support, null terminated */
47static const struct sdio_device_id brcmf_sdmmc_ids[] = {
48 {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329)},
49 { /* end: all zeroes */ },
50};
51MODULE_DEVICE_TABLE(sdio, brcmf_sdmmc_ids);
52
53static bool
54brcmf_pm_resume_error(struct brcmf_sdio_dev *sdiodev)
55{
56 bool is_err = false;
57#ifdef CONFIG_PM_SLEEP
58 is_err = atomic_read(&sdiodev->suspend);
59#endif
60 return is_err;
61}
62
63static void
64brcmf_pm_resume_wait(struct brcmf_sdio_dev *sdiodev, wait_queue_head_t *wq)
65{
66#ifdef CONFIG_PM_SLEEP
67 int retry = 0;
68 while (atomic_read(&sdiodev->suspend) && retry++ != 30)
69 wait_event_timeout(*wq, false, HZ/100);
70#endif
71}
72
73static inline int brcmf_sdioh_f0_write_byte(struct brcmf_sdio_dev *sdiodev,
74 uint regaddr, u8 *byte)
75{
76 struct sdio_func *sdfunc = sdiodev->func[0];
77 int err_ret;
78
79 /*
80 * Can only directly write to some F0 registers.
81 * Handle F2 enable/disable and Abort command
82 * as a special case.
83 */
84 if (regaddr == SDIO_CCCR_IOEx) {
85 sdfunc = sdiodev->func[2];
86 if (sdfunc) {
87 sdio_claim_host(sdfunc);
88 if (*byte & SDIO_FUNC_ENABLE_2) {
89 /* Enable Function 2 */
90 err_ret = sdio_enable_func(sdfunc);
91 if (err_ret)
92 brcmf_dbg(ERROR,
93 "enable F2 failed:%d\n",
94 err_ret);
95 } else {
96 /* Disable Function 2 */
97 err_ret = sdio_disable_func(sdfunc);
98 if (err_ret)
99 brcmf_dbg(ERROR,
100 "Disable F2 failed:%d\n",
101 err_ret);
102 }
103 sdio_release_host(sdfunc);
104 }
105 } else if (regaddr == SDIO_CCCR_ABORT) {
106 sdio_claim_host(sdfunc);
107 sdio_writeb(sdfunc, *byte, regaddr, &err_ret);
108 sdio_release_host(sdfunc);
109 } else if (regaddr < 0xF0) {
110 brcmf_dbg(ERROR, "F0 Wr:0x%02x: write disallowed\n", regaddr);
111 err_ret = -EPERM;
112 } else {
113 sdio_claim_host(sdfunc);
114 sdio_f0_writeb(sdfunc, *byte, regaddr, &err_ret);
115 sdio_release_host(sdfunc);
116 }
117
118 return err_ret;
119}
120
121int brcmf_sdioh_request_byte(struct brcmf_sdio_dev *sdiodev, uint rw, uint func,
122 uint regaddr, u8 *byte)
123{
124 int err_ret;
125
126 brcmf_dbg(INFO, "rw=%d, func=%d, addr=0x%05x\n", rw, func, regaddr);
127
128 brcmf_pm_resume_wait(sdiodev, &sdiodev->request_byte_wait);
129 if (brcmf_pm_resume_error(sdiodev))
130 return -EIO;
131
132 if (rw && func == 0) {
133 /* handle F0 separately */
134 err_ret = brcmf_sdioh_f0_write_byte(sdiodev, regaddr, byte);
135 } else {
136 sdio_claim_host(sdiodev->func[func]);
137 if (rw) /* CMD52 Write */
138 sdio_writeb(sdiodev->func[func], *byte, regaddr,
139 &err_ret);
140 else if (func == 0) {
141 *byte = sdio_f0_readb(sdiodev->func[func], regaddr,
142 &err_ret);
143 } else {
144 *byte = sdio_readb(sdiodev->func[func], regaddr,
145 &err_ret);
146 }
147 sdio_release_host(sdiodev->func[func]);
148 }
149
150 if (err_ret)
151 brcmf_dbg(ERROR, "Failed to %s byte F%d:@0x%05x=%02x, Err: %d\n",
152 rw ? "write" : "read", func, regaddr, *byte, err_ret);
153
154 return err_ret;
155}
156
157int brcmf_sdioh_request_word(struct brcmf_sdio_dev *sdiodev,
158 uint rw, uint func, uint addr, u32 *word,
159 uint nbytes)
160{
161 int err_ret = -EIO;
162
163 if (func == 0) {
164 brcmf_dbg(ERROR, "Only CMD52 allowed to F0\n");
165 return -EINVAL;
166 }
167
168 brcmf_dbg(INFO, "rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
169 rw, func, addr, nbytes);
170
171 brcmf_pm_resume_wait(sdiodev, &sdiodev->request_word_wait);
172 if (brcmf_pm_resume_error(sdiodev))
173 return -EIO;
174 /* Claim host controller */
175 sdio_claim_host(sdiodev->func[func]);
176
177 if (rw) { /* CMD52 Write */
178 if (nbytes == 4)
179 sdio_writel(sdiodev->func[func], *word, addr,
180 &err_ret);
181 else if (nbytes == 2)
182 sdio_writew(sdiodev->func[func], (*word & 0xFFFF),
183 addr, &err_ret);
184 else
185 brcmf_dbg(ERROR, "Invalid nbytes: %d\n", nbytes);
186 } else { /* CMD52 Read */
187 if (nbytes == 4)
188 *word = sdio_readl(sdiodev->func[func], addr, &err_ret);
189 else if (nbytes == 2)
190 *word = sdio_readw(sdiodev->func[func], addr,
191 &err_ret) & 0xFFFF;
192 else
193 brcmf_dbg(ERROR, "Invalid nbytes: %d\n", nbytes);
194 }
195
196 /* Release host controller */
197 sdio_release_host(sdiodev->func[func]);
198
199 if (err_ret)
200 brcmf_dbg(ERROR, "Failed to %s word, Err: 0x%08x\n",
201 rw ? "write" : "read", err_ret);
202
203 return err_ret;
204}
205
206static int
207brcmf_sdioh_request_packet(struct brcmf_sdio_dev *sdiodev, uint fix_inc,
208 uint write, uint func, uint addr,
209 struct sk_buff *pkt)
210{
211 bool fifo = (fix_inc == SDIOH_DATA_FIX);
212 u32 SGCount = 0;
213 int err_ret = 0;
214
215 struct sk_buff *pnext;
216
217 brcmf_dbg(TRACE, "Enter\n");
218
219 brcmf_pm_resume_wait(sdiodev, &sdiodev->request_packet_wait);
220 if (brcmf_pm_resume_error(sdiodev))
221 return -EIO;
222
223 /* Claim host controller */
224 sdio_claim_host(sdiodev->func[func]);
225 for (pnext = pkt; pnext; pnext = pnext->next) {
226 uint pkt_len = pnext->len;
227 pkt_len += 3;
228 pkt_len &= 0xFFFFFFFC;
229
230 if ((write) && (!fifo)) {
231 err_ret = sdio_memcpy_toio(sdiodev->func[func], addr,
232 ((u8 *) (pnext->data)),
233 pkt_len);
234 } else if (write) {
235 err_ret = sdio_memcpy_toio(sdiodev->func[func], addr,
236 ((u8 *) (pnext->data)),
237 pkt_len);
238 } else if (fifo) {
239 err_ret = sdio_readsb(sdiodev->func[func],
240 ((u8 *) (pnext->data)),
241 addr, pkt_len);
242 } else {
243 err_ret = sdio_memcpy_fromio(sdiodev->func[func],
244 ((u8 *) (pnext->data)),
245 addr, pkt_len);
246 }
247
248 if (err_ret) {
249 brcmf_dbg(ERROR, "%s FAILED %p[%d], addr=0x%05x, pkt_len=%d, ERR=0x%08x\n",
250 write ? "TX" : "RX", pnext, SGCount, addr,
251 pkt_len, err_ret);
252 } else {
253 brcmf_dbg(TRACE, "%s xfr'd %p[%d], addr=0x%05x, len=%d\n",
254 write ? "TX" : "RX", pnext, SGCount, addr,
255 pkt_len);
256 }
257
258 if (!fifo)
259 addr += pkt_len;
260 SGCount++;
261
262 }
263
264 /* Release host controller */
265 sdio_release_host(sdiodev->func[func]);
266
267 brcmf_dbg(TRACE, "Exit\n");
268 return err_ret;
269}
270
271/*
272 * This function takes a buffer or packet, and fixes everything up
273 * so that in the end, a DMA-able packet is created.
274 *
275 * A buffer does not have an associated packet pointer,
276 * and may or may not be aligned.
277 * A packet may consist of a single packet, or a packet chain.
278 * If it is a packet chain, then all the packets in the chain
279 * must be properly aligned.
280 *
281 * If the packet data is not aligned, then there may only be
282 * one packet, and in this case, it is copied to a new
283 * aligned packet.
284 *
285 */
286int brcmf_sdioh_request_buffer(struct brcmf_sdio_dev *sdiodev,
287 uint fix_inc, uint write, uint func, uint addr,
288 uint reg_width, uint buflen_u, u8 *buffer,
289 struct sk_buff *pkt)
290{
291 int Status;
292 struct sk_buff *mypkt = NULL;
293
294 brcmf_dbg(TRACE, "Enter\n");
295
296 brcmf_pm_resume_wait(sdiodev, &sdiodev->request_buffer_wait);
297 if (brcmf_pm_resume_error(sdiodev))
298 return -EIO;
299 /* Case 1: we don't have a packet. */
300 if (pkt == NULL) {
301 brcmf_dbg(DATA, "Creating new %s Packet, len=%d\n",
302 write ? "TX" : "RX", buflen_u);
303 mypkt = brcmu_pkt_buf_get_skb(buflen_u);
304 if (!mypkt) {
305 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: len %d\n",
306 buflen_u);
307 return -EIO;
308 }
309
310 /* For a write, copy the buffer data into the packet. */
311 if (write)
312 memcpy(mypkt->data, buffer, buflen_u);
313
314 Status = brcmf_sdioh_request_packet(sdiodev, fix_inc, write,
315 func, addr, mypkt);
316
317 /* For a read, copy the packet data back to the buffer. */
318 if (!write)
319 memcpy(buffer, mypkt->data, buflen_u);
320
321 brcmu_pkt_buf_free_skb(mypkt);
322 } else if (((ulong) (pkt->data) & DMA_ALIGN_MASK) != 0) {
323 /*
324 * Case 2: We have a packet, but it is unaligned.
325 * In this case, we cannot have a chain (pkt->next == NULL)
326 */
327 brcmf_dbg(DATA, "Creating aligned %s Packet, len=%d\n",
328 write ? "TX" : "RX", pkt->len);
329 mypkt = brcmu_pkt_buf_get_skb(pkt->len);
330 if (!mypkt) {
331 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: len %d\n",
332 pkt->len);
333 return -EIO;
334 }
335
336 /* For a write, copy the buffer data into the packet. */
337 if (write)
338 memcpy(mypkt->data, pkt->data, pkt->len);
339
340 Status = brcmf_sdioh_request_packet(sdiodev, fix_inc, write,
341 func, addr, mypkt);
342
343 /* For a read, copy the packet data back to the buffer. */
344 if (!write)
345 memcpy(pkt->data, mypkt->data, mypkt->len);
346
347 brcmu_pkt_buf_free_skb(mypkt);
348 } else { /* case 3: We have a packet and
349 it is aligned. */
350 brcmf_dbg(DATA, "Aligned %s Packet, direct DMA\n",
351 write ? "Tx" : "Rx");
352 Status = brcmf_sdioh_request_packet(sdiodev, fix_inc, write,
353 func, addr, pkt);
354 }
355
356 return Status;
357}
358
359/* Read client card reg */
360static int
361brcmf_sdioh_card_regread(struct brcmf_sdio_dev *sdiodev, int func, u32 regaddr,
362 int regsize, u32 *data)
363{
364
365 if ((func == 0) || (regsize == 1)) {
366 u8 temp = 0;
367
368 brcmf_sdioh_request_byte(sdiodev, SDIOH_READ, func, regaddr,
369 &temp);
370 *data = temp;
371 *data &= 0xff;
372 brcmf_dbg(DATA, "byte read data=0x%02x\n", *data);
373 } else {
374 brcmf_sdioh_request_word(sdiodev, SDIOH_READ, func, regaddr,
375 data, regsize);
376 if (regsize == 2)
377 *data &= 0xffff;
378
379 brcmf_dbg(DATA, "word read data=0x%08x\n", *data);
380 }
381
382 return SUCCESS;
383}
384
385static int brcmf_sdioh_get_cisaddr(struct brcmf_sdio_dev *sdiodev, u32 regaddr)
386{
387 /* read 24 bits and return valid 17 bit addr */
388 int i;
389 u32 scratch, regdata;
390 __le32 scratch_le;
391 u8 *ptr = (u8 *)&scratch_le;
392
393 for (i = 0; i < 3; i++) {
394 if ((brcmf_sdioh_card_regread(sdiodev, 0, regaddr, 1,
395 &regdata)) != SUCCESS)
396 brcmf_dbg(ERROR, "Can't read!\n");
397
398 *ptr++ = (u8) regdata;
399 regaddr++;
400 }
401
402 /* Only the lower 17-bits are valid */
403 scratch = le32_to_cpu(scratch_le);
404 scratch &= 0x0001FFFF;
405 return scratch;
406}
407
408static int brcmf_sdioh_enablefuncs(struct brcmf_sdio_dev *sdiodev)
409{
410 int err_ret;
411 u32 fbraddr;
412 u8 func;
413
414 brcmf_dbg(TRACE, "\n");
415
416 /* Get the Card's common CIS address */
417 sdiodev->func_cis_ptr[0] = brcmf_sdioh_get_cisaddr(sdiodev,
418 SDIO_CCCR_CIS);
419 brcmf_dbg(INFO, "Card's Common CIS Ptr = 0x%x\n",
420 sdiodev->func_cis_ptr[0]);
421
422 /* Get the Card's function CIS (for each function) */
423 for (fbraddr = SDIO_FBR_BASE(1), func = 1;
424 func <= sdiodev->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
425 sdiodev->func_cis_ptr[func] =
426 brcmf_sdioh_get_cisaddr(sdiodev, SDIO_FBR_CIS + fbraddr);
427 brcmf_dbg(INFO, "Function %d CIS Ptr = 0x%x\n",
428 func, sdiodev->func_cis_ptr[func]);
429 }
430
431 /* Enable Function 1 */
432 sdio_claim_host(sdiodev->func[1]);
433 err_ret = sdio_enable_func(sdiodev->func[1]);
434 sdio_release_host(sdiodev->func[1]);
435 if (err_ret)
436 brcmf_dbg(ERROR, "Failed to enable F1 Err: 0x%08x\n", err_ret);
437
438 return false;
439}
440
441/*
442 * Public entry points & extern's
443 */
444int brcmf_sdioh_attach(struct brcmf_sdio_dev *sdiodev)
445{
446 int err_ret = 0;
447
448 brcmf_dbg(TRACE, "\n");
449
450 sdiodev->num_funcs = 2;
451
452 sdio_claim_host(sdiodev->func[1]);
453 err_ret = sdio_set_block_size(sdiodev->func[1], SDIO_FUNC1_BLOCKSIZE);
454 sdio_release_host(sdiodev->func[1]);
455 if (err_ret) {
456 brcmf_dbg(ERROR, "Failed to set F1 blocksize\n");
457 goto out;
458 }
459
460 sdio_claim_host(sdiodev->func[2]);
461 err_ret = sdio_set_block_size(sdiodev->func[2], SDIO_FUNC2_BLOCKSIZE);
462 sdio_release_host(sdiodev->func[2]);
463 if (err_ret) {
464 brcmf_dbg(ERROR, "Failed to set F2 blocksize\n");
465 goto out;
466 }
467
468 brcmf_sdioh_enablefuncs(sdiodev);
469
470out:
471 brcmf_dbg(TRACE, "Done\n");
472 return err_ret;
473}
474
475void brcmf_sdioh_detach(struct brcmf_sdio_dev *sdiodev)
476{
477 brcmf_dbg(TRACE, "\n");
478
479 /* Disable Function 2 */
480 sdio_claim_host(sdiodev->func[2]);
481 sdio_disable_func(sdiodev->func[2]);
482 sdio_release_host(sdiodev->func[2]);
483
484 /* Disable Function 1 */
485 sdio_claim_host(sdiodev->func[1]);
486 sdio_disable_func(sdiodev->func[1]);
487 sdio_release_host(sdiodev->func[1]);
488
489}
490
491static int brcmf_ops_sdio_probe(struct sdio_func *func,
492 const struct sdio_device_id *id)
493{
494 int ret = 0;
495 struct brcmf_sdio_dev *sdiodev;
496 brcmf_dbg(TRACE, "Enter\n");
497 brcmf_dbg(TRACE, "func->class=%x\n", func->class);
498 brcmf_dbg(TRACE, "sdio_vendor: 0x%04x\n", func->vendor);
499 brcmf_dbg(TRACE, "sdio_device: 0x%04x\n", func->device);
500 brcmf_dbg(TRACE, "Function#: 0x%04x\n", func->num);
501
502 if (func->num == 1) {
503 if (dev_get_drvdata(&func->card->dev)) {
504 brcmf_dbg(ERROR, "card private drvdata occupied\n");
505 return -ENXIO;
506 }
507 sdiodev = kzalloc(sizeof(struct brcmf_sdio_dev), GFP_KERNEL);
508 if (!sdiodev)
509 return -ENOMEM;
510 sdiodev->func[0] = func->card->sdio_func[0];
511 sdiodev->func[1] = func;
512 dev_set_drvdata(&func->card->dev, sdiodev);
513
514 atomic_set(&sdiodev->suspend, false);
515 init_waitqueue_head(&sdiodev->request_byte_wait);
516 init_waitqueue_head(&sdiodev->request_word_wait);
517 init_waitqueue_head(&sdiodev->request_packet_wait);
518 init_waitqueue_head(&sdiodev->request_buffer_wait);
519 }
520
521 if (func->num == 2) {
522 sdiodev = dev_get_drvdata(&func->card->dev);
523 if ((!sdiodev) || (sdiodev->func[1]->card != func->card))
524 return -ENODEV;
525 sdiodev->func[2] = func;
526
527 brcmf_dbg(TRACE, "F2 found, calling brcmf_sdio_probe...\n");
528 ret = brcmf_sdio_probe(sdiodev);
529 }
530
531 return ret;
532}
533
534static void brcmf_ops_sdio_remove(struct sdio_func *func)
535{
536 struct brcmf_sdio_dev *sdiodev;
537 brcmf_dbg(TRACE, "Enter\n");
538 brcmf_dbg(INFO, "func->class=%x\n", func->class);
539 brcmf_dbg(INFO, "sdio_vendor: 0x%04x\n", func->vendor);
540 brcmf_dbg(INFO, "sdio_device: 0x%04x\n", func->device);
541 brcmf_dbg(INFO, "Function#: 0x%04x\n", func->num);
542
543 if (func->num == 2) {
544 sdiodev = dev_get_drvdata(&func->card->dev);
545 brcmf_dbg(TRACE, "F2 found, calling brcmf_sdio_remove...\n");
546 brcmf_sdio_remove(sdiodev);
547 dev_set_drvdata(&func->card->dev, NULL);
548 kfree(sdiodev);
549 }
550}
551
552#ifdef CONFIG_PM_SLEEP
553static int brcmf_sdio_suspend(struct device *dev)
554{
555 mmc_pm_flag_t sdio_flags;
556 struct brcmf_sdio_dev *sdiodev;
557 struct sdio_func *func = dev_to_sdio_func(dev);
558 int ret = 0;
559
560 brcmf_dbg(TRACE, "\n");
561
562 sdiodev = dev_get_drvdata(&func->card->dev);
563
564 atomic_set(&sdiodev->suspend, true);
565
566 sdio_flags = sdio_get_host_pm_caps(sdiodev->func[1]);
567 if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
568 brcmf_dbg(ERROR, "Host can't keep power while suspended\n");
569 return -EINVAL;
570 }
571
572 ret = sdio_set_host_pm_flags(sdiodev->func[1], MMC_PM_KEEP_POWER);
573 if (ret) {
574 brcmf_dbg(ERROR, "Failed to set pm_flags\n");
575 return ret;
576 }
577
578 brcmf_sdio_wdtmr_enable(sdiodev, false);
579
580 return ret;
581}
582
583static int brcmf_sdio_resume(struct device *dev)
584{
585 struct brcmf_sdio_dev *sdiodev;
586 struct sdio_func *func = dev_to_sdio_func(dev);
587
588 sdiodev = dev_get_drvdata(&func->card->dev);
589 brcmf_sdio_wdtmr_enable(sdiodev, true);
590 atomic_set(&sdiodev->suspend, false);
591 return 0;
592}
593
594static const struct dev_pm_ops brcmf_sdio_pm_ops = {
595 .suspend = brcmf_sdio_suspend,
596 .resume = brcmf_sdio_resume,
597};
598#endif /* CONFIG_PM_SLEEP */
599
600static struct sdio_driver brcmf_sdmmc_driver = {
601 .probe = brcmf_ops_sdio_probe,
602 .remove = brcmf_ops_sdio_remove,
603 .name = "brcmfmac",
604 .id_table = brcmf_sdmmc_ids,
605#ifdef CONFIG_PM_SLEEP
606 .drv = {
607 .pm = &brcmf_sdio_pm_ops,
608 },
609#endif /* CONFIG_PM_SLEEP */
610};
611
612/* bus register interface */
613int brcmf_bus_register(void)
614{
615 brcmf_dbg(TRACE, "Enter\n");
616
617 return sdio_register_driver(&brcmf_sdmmc_driver);
618}
619
620void brcmf_bus_unregister(void)
621{
622 brcmf_dbg(TRACE, "Enter\n");
623
624 sdio_unregister_driver(&brcmf_sdmmc_driver);
625}
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd.h b/drivers/staging/brcm80211/brcmfmac/dhd.h
deleted file mode 100644
index 3ec74778b2e..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/dhd.h
+++ /dev/null
@@ -1,773 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/****************
18 * Common types *
19 */
20
21#ifndef _BRCMF_H_
22#define _BRCMF_H_
23
24#define BRCMF_VERSION_STR "4.218.248.5"
25
26/*******************************************************************************
27 * IO codes that are interpreted by dongle firmware
28 ******************************************************************************/
29#define BRCMF_C_UP 2
30#define BRCMF_C_SET_PROMISC 10
31#define BRCMF_C_GET_RATE 12
32#define BRCMF_C_GET_INFRA 19
33#define BRCMF_C_SET_INFRA 20
34#define BRCMF_C_GET_AUTH 21
35#define BRCMF_C_SET_AUTH 22
36#define BRCMF_C_GET_BSSID 23
37#define BRCMF_C_GET_SSID 25
38#define BRCMF_C_SET_SSID 26
39#define BRCMF_C_GET_CHANNEL 29
40#define BRCMF_C_GET_SRL 31
41#define BRCMF_C_GET_LRL 33
42#define BRCMF_C_GET_RADIO 37
43#define BRCMF_C_SET_RADIO 38
44#define BRCMF_C_GET_PHYTYPE 39
45#define BRCMF_C_SET_KEY 45
46#define BRCMF_C_SET_PASSIVE_SCAN 49
47#define BRCMF_C_SCAN 50
48#define BRCMF_C_SCAN_RESULTS 51
49#define BRCMF_C_DISASSOC 52
50#define BRCMF_C_REASSOC 53
51#define BRCMF_C_SET_ROAM_TRIGGER 55
52#define BRCMF_C_SET_ROAM_DELTA 57
53#define BRCMF_C_GET_DTIMPRD 77
54#define BRCMF_C_SET_COUNTRY 84
55#define BRCMF_C_GET_PM 85
56#define BRCMF_C_SET_PM 86
57#define BRCMF_C_GET_AP 117
58#define BRCMF_C_SET_AP 118
59#define BRCMF_C_GET_RSSI 127
60#define BRCMF_C_GET_WSEC 133
61#define BRCMF_C_SET_WSEC 134
62#define BRCMF_C_GET_PHY_NOISE 135
63#define BRCMF_C_GET_BSS_INFO 136
64#define BRCMF_C_SET_SCAN_CHANNEL_TIME 185
65#define BRCMF_C_SET_SCAN_UNASSOC_TIME 187
66#define BRCMF_C_SCB_DEAUTHENTICATE_FOR_REASON 201
67#define BRCMF_C_GET_VALID_CHANNELS 217
68#define BRCMF_C_GET_KEY_PRIMARY 235
69#define BRCMF_C_SET_KEY_PRIMARY 236
70#define BRCMF_C_SET_SCAN_PASSIVE_TIME 258
71#define BRCMF_C_GET_VAR 262
72#define BRCMF_C_SET_VAR 263
73
74/* phy types (returned by WLC_GET_PHYTPE) */
75#define WLC_PHY_TYPE_A 0
76#define WLC_PHY_TYPE_B 1
77#define WLC_PHY_TYPE_G 2
78#define WLC_PHY_TYPE_N 4
79#define WLC_PHY_TYPE_LP 5
80#define WLC_PHY_TYPE_SSN 6
81#define WLC_PHY_TYPE_HT 7
82#define WLC_PHY_TYPE_LCN 8
83#define WLC_PHY_TYPE_NULL 0xf
84
85#define BRCMF_EVENTING_MASK_LEN 16
86
87#define TOE_TX_CSUM_OL 0x00000001
88#define TOE_RX_CSUM_OL 0x00000002
89
90#define BRCMF_BSS_INFO_VERSION 108 /* current ver of brcmf_bss_info struct */
91
92/* size of brcmf_scan_params not including variable length array */
93#define BRCMF_SCAN_PARAMS_FIXED_SIZE 64
94
95/* masks for channel and ssid count */
96#define BRCMF_SCAN_PARAMS_COUNT_MASK 0x0000ffff
97#define BRCMF_SCAN_PARAMS_NSSID_SHIFT 16
98
99#define BRCMF_SCAN_ACTION_START 1
100#define BRCMF_SCAN_ACTION_CONTINUE 2
101#define WL_SCAN_ACTION_ABORT 3
102
103#define BRCMF_ISCAN_REQ_VERSION 1
104
105/* brcmf_iscan_results status values */
106#define BRCMF_SCAN_RESULTS_SUCCESS 0
107#define BRCMF_SCAN_RESULTS_PARTIAL 1
108#define BRCMF_SCAN_RESULTS_PENDING 2
109#define BRCMF_SCAN_RESULTS_ABORTED 3
110#define BRCMF_SCAN_RESULTS_NO_MEM 4
111
112/* Indicates this key is using soft encrypt */
113#define WL_SOFT_KEY (1 << 0)
114/* primary (ie tx) key */
115#define BRCMF_PRIMARY_KEY (1 << 1)
116/* Reserved for backward compat */
117#define WL_KF_RES_4 (1 << 4)
118/* Reserved for backward compat */
119#define WL_KF_RES_5 (1 << 5)
120/* Indicates a group key for a IBSS PEER */
121#define WL_IBSS_PEER_GROUP_KEY (1 << 6)
122
123/* For supporting multiple interfaces */
124#define BRCMF_MAX_IFS 16
125#define BRCMF_DEL_IF -0xe
126#define BRCMF_BAD_IF -0xf
127
128#define DOT11_BSSTYPE_ANY 2
129#define DOT11_MAX_DEFAULT_KEYS 4
130
131#define BRCMF_EVENT_MSG_LINK 0x01
132#define BRCMF_EVENT_MSG_FLUSHTXQ 0x02
133#define BRCMF_EVENT_MSG_GROUP 0x04
134
135struct brcmf_event_msg {
136 __be16 version;
137 __be16 flags;
138 __be32 event_type;
139 __be32 status;
140 __be32 reason;
141 __be32 auth_type;
142 __be32 datalen;
143 u8 addr[ETH_ALEN];
144 char ifname[IFNAMSIZ];
145} __packed;
146
147struct brcm_ethhdr {
148 u16 subtype;
149 u16 length;
150 u8 version;
151 u8 oui[3];
152 u16 usr_subtype;
153} __packed;
154
155struct brcmf_event {
156 struct ethhdr eth;
157 struct brcm_ethhdr hdr;
158 struct brcmf_event_msg msg;
159} __packed;
160
161struct dngl_stats {
162 unsigned long rx_packets; /* total packets received */
163 unsigned long tx_packets; /* total packets transmitted */
164 unsigned long rx_bytes; /* total bytes received */
165 unsigned long tx_bytes; /* total bytes transmitted */
166 unsigned long rx_errors; /* bad packets received */
167 unsigned long tx_errors; /* packet transmit problems */
168 unsigned long rx_dropped; /* packets dropped by dongle */
169 unsigned long tx_dropped; /* packets dropped by dongle */
170 unsigned long multicast; /* multicast packets received */
171};
172
173/* event codes sent by the dongle to this driver */
174#define BRCMF_E_SET_SSID 0
175#define BRCMF_E_JOIN 1
176#define BRCMF_E_START 2
177#define BRCMF_E_AUTH 3
178#define BRCMF_E_AUTH_IND 4
179#define BRCMF_E_DEAUTH 5
180#define BRCMF_E_DEAUTH_IND 6
181#define BRCMF_E_ASSOC 7
182#define BRCMF_E_ASSOC_IND 8
183#define BRCMF_E_REASSOC 9
184#define BRCMF_E_REASSOC_IND 10
185#define BRCMF_E_DISASSOC 11
186#define BRCMF_E_DISASSOC_IND 12
187#define BRCMF_E_QUIET_START 13
188#define BRCMF_E_QUIET_END 14
189#define BRCMF_E_BEACON_RX 15
190#define BRCMF_E_LINK 16
191#define BRCMF_E_MIC_ERROR 17
192#define BRCMF_E_NDIS_LINK 18
193#define BRCMF_E_ROAM 19
194#define BRCMF_E_TXFAIL 20
195#define BRCMF_E_PMKID_CACHE 21
196#define BRCMF_E_RETROGRADE_TSF 22
197#define BRCMF_E_PRUNE 23
198#define BRCMF_E_AUTOAUTH 24
199#define BRCMF_E_EAPOL_MSG 25
200#define BRCMF_E_SCAN_COMPLETE 26
201#define BRCMF_E_ADDTS_IND 27
202#define BRCMF_E_DELTS_IND 28
203#define BRCMF_E_BCNSENT_IND 29
204#define BRCMF_E_BCNRX_MSG 30
205#define BRCMF_E_BCNLOST_MSG 31
206#define BRCMF_E_ROAM_PREP 32
207#define BRCMF_E_PFN_NET_FOUND 33
208#define BRCMF_E_PFN_NET_LOST 34
209#define BRCMF_E_RESET_COMPLETE 35
210#define BRCMF_E_JOIN_START 36
211#define BRCMF_E_ROAM_START 37
212#define BRCMF_E_ASSOC_START 38
213#define BRCMF_E_IBSS_ASSOC 39
214#define BRCMF_E_RADIO 40
215#define BRCMF_E_PSM_WATCHDOG 41
216#define BRCMF_E_PROBREQ_MSG 44
217#define BRCMF_E_SCAN_CONFIRM_IND 45
218#define BRCMF_E_PSK_SUP 46
219#define BRCMF_E_COUNTRY_CODE_CHANGED 47
220#define BRCMF_E_EXCEEDED_MEDIUM_TIME 48
221#define BRCMF_E_ICV_ERROR 49
222#define BRCMF_E_UNICAST_DECODE_ERROR 50
223#define BRCMF_E_MULTICAST_DECODE_ERROR 51
224#define BRCMF_E_TRACE 52
225#define BRCMF_E_IF 54
226#define BRCMF_E_RSSI 56
227#define BRCMF_E_PFN_SCAN_COMPLETE 57
228#define BRCMF_E_EXTLOG_MSG 58
229#define BRCMF_E_ACTION_FRAME 59
230#define BRCMF_E_ACTION_FRAME_COMPLETE 60
231#define BRCMF_E_PRE_ASSOC_IND 61
232#define BRCMF_E_PRE_REASSOC_IND 62
233#define BRCMF_E_CHANNEL_ADOPTED 63
234#define BRCMF_E_AP_STARTED 64
235#define BRCMF_E_DFS_AP_STOP 65
236#define BRCMF_E_DFS_AP_RESUME 66
237#define BRCMF_E_RESERVED1 67
238#define BRCMF_E_RESERVED2 68
239#define BRCMF_E_ESCAN_RESULT 69
240#define BRCMF_E_ACTION_FRAME_OFF_CHAN_COMPLETE 70
241#define BRCMF_E_DCS_REQUEST 73
242
243#define BRCMF_E_FIFO_CREDIT_MAP 74
244
245#define BRCMF_E_LAST 75
246
247#define BRCMF_E_STATUS_SUCCESS 0
248#define BRCMF_E_STATUS_FAIL 1
249#define BRCMF_E_STATUS_TIMEOUT 2
250#define BRCMF_E_STATUS_NO_NETWORKS 3
251#define BRCMF_E_STATUS_ABORT 4
252#define BRCMF_E_STATUS_NO_ACK 5
253#define BRCMF_E_STATUS_UNSOLICITED 6
254#define BRCMF_E_STATUS_ATTEMPT 7
255#define BRCMF_E_STATUS_PARTIAL 8
256#define BRCMF_E_STATUS_NEWSCAN 9
257#define BRCMF_E_STATUS_NEWASSOC 10
258#define BRCMF_E_STATUS_11HQUIET 11
259#define BRCMF_E_STATUS_SUPPRESS 12
260#define BRCMF_E_STATUS_NOCHANS 13
261#define BRCMF_E_STATUS_CS_ABORT 15
262#define BRCMF_E_STATUS_ERROR 16
263
264#define BRCMF_E_REASON_INITIAL_ASSOC 0
265#define BRCMF_E_REASON_LOW_RSSI 1
266#define BRCMF_E_REASON_DEAUTH 2
267#define BRCMF_E_REASON_DISASSOC 3
268#define BRCMF_E_REASON_BCNS_LOST 4
269#define BRCMF_E_REASON_MINTXRATE 9
270#define BRCMF_E_REASON_TXFAIL 10
271
272#define BRCMF_E_REASON_FAST_ROAM_FAILED 5
273#define BRCMF_E_REASON_DIRECTED_ROAM 6
274#define BRCMF_E_REASON_TSPEC_REJECTED 7
275#define BRCMF_E_REASON_BETTER_AP 8
276
277#define BRCMF_E_PRUNE_ENCR_MISMATCH 1
278#define BRCMF_E_PRUNE_BCAST_BSSID 2
279#define BRCMF_E_PRUNE_MAC_DENY 3
280#define BRCMF_E_PRUNE_MAC_NA 4
281#define BRCMF_E_PRUNE_REG_PASSV 5
282#define BRCMF_E_PRUNE_SPCT_MGMT 6
283#define BRCMF_E_PRUNE_RADAR 7
284#define BRCMF_E_RSN_MISMATCH 8
285#define BRCMF_E_PRUNE_NO_COMMON_RATES 9
286#define BRCMF_E_PRUNE_BASIC_RATES 10
287#define BRCMF_E_PRUNE_CIPHER_NA 12
288#define BRCMF_E_PRUNE_KNOWN_STA 13
289#define BRCMF_E_PRUNE_WDS_PEER 15
290#define BRCMF_E_PRUNE_QBSS_LOAD 16
291#define BRCMF_E_PRUNE_HOME_AP 17
292
293#define BRCMF_E_SUP_OTHER 0
294#define BRCMF_E_SUP_DECRYPT_KEY_DATA 1
295#define BRCMF_E_SUP_BAD_UCAST_WEP128 2
296#define BRCMF_E_SUP_BAD_UCAST_WEP40 3
297#define BRCMF_E_SUP_UNSUP_KEY_LEN 4
298#define BRCMF_E_SUP_PW_KEY_CIPHER 5
299#define BRCMF_E_SUP_MSG3_TOO_MANY_IE 6
300#define BRCMF_E_SUP_MSG3_IE_MISMATCH 7
301#define BRCMF_E_SUP_NO_INSTALL_FLAG 8
302#define BRCMF_E_SUP_MSG3_NO_GTK 9
303#define BRCMF_E_SUP_GRP_KEY_CIPHER 10
304#define BRCMF_E_SUP_GRP_MSG1_NO_GTK 11
305#define BRCMF_E_SUP_GTK_DECRYPT_FAIL 12
306#define BRCMF_E_SUP_SEND_FAIL 13
307#define BRCMF_E_SUP_DEAUTH 14
308
309#define BRCMF_E_IF_ADD 1
310#define BRCMF_E_IF_DEL 2
311#define BRCMF_E_IF_CHANGE 3
312
313#define BRCMF_E_IF_ROLE_STA 0
314#define BRCMF_E_IF_ROLE_AP 1
315#define BRCMF_E_IF_ROLE_WDS 2
316
317#define BRCMF_E_LINK_BCN_LOSS 1
318#define BRCMF_E_LINK_DISASSOC 2
319#define BRCMF_E_LINK_ASSOC_REC 3
320#define BRCMF_E_LINK_BSSCFG_DIS 4
321
322/* The level of bus communication with the dongle */
323enum brcmf_bus_state {
324 BRCMF_BUS_DOWN, /* Not ready for frame transfers */
325 BRCMF_BUS_LOAD, /* Download access only (CPU reset) */
326 BRCMF_BUS_DATA /* Ready for frame transfers */
327};
328
329/* Pattern matching filter. Specifies an offset within received packets to
330 * start matching, the pattern to match, the size of the pattern, and a bitmask
331 * that indicates which bits within the pattern should be matched.
332 */
333struct brcmf_pkt_filter_pattern {
334 /*
335 * Offset within received packet to start pattern matching.
336 * Offset '0' is the first byte of the ethernet header.
337 */
338 u32 offset;
339 /* Size of the pattern. Bitmask must be the same size.*/
340 u32 size_bytes;
341 /*
342 * Variable length mask and pattern data. mask starts at offset 0.
343 * Pattern immediately follows mask.
344 */
345 u8 mask_and_pattern[1];
346};
347
348/* IOVAR "pkt_filter_add" parameter. Used to install packet filters. */
349struct brcmf_pkt_filter {
350 u32 id; /* Unique filter id, specified by app. */
351 u32 type; /* Filter type (WL_PKT_FILTER_TYPE_xxx). */
352 u32 negate_match; /* Negate the result of filter matches */
353 union { /* Filter definitions */
354 struct brcmf_pkt_filter_pattern pattern; /* Filter pattern */
355 } u;
356};
357
358/* IOVAR "pkt_filter_enable" parameter. */
359struct brcmf_pkt_filter_enable {
360 u32 id; /* Unique filter id */
361 u32 enable; /* Enable/disable bool */
362};
363
364/* BSS info structure
365 * Applications MUST CHECK ie_offset field and length field to access IEs and
366 * next bss_info structure in a vector (in struct brcmf_scan_results)
367 */
368struct brcmf_bss_info {
369 __le32 version; /* version field */
370 __le32 length; /* byte length of data in this record,
371 * starting at version and including IEs
372 */
373 u8 BSSID[ETH_ALEN];
374 __le16 beacon_period; /* units are Kusec */
375 __le16 capability; /* Capability information */
376 u8 SSID_len;
377 u8 SSID[32];
378 struct {
379 __le32 count; /* # rates in this set */
380 u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
381 } rateset; /* supported rates */
382 __le16 chanspec; /* chanspec for bss */
383 __le16 atim_window; /* units are Kusec */
384 u8 dtim_period; /* DTIM period */
385 __le16 RSSI; /* receive signal strength (in dBm) */
386 s8 phy_noise; /* noise (in dBm) */
387
388 u8 n_cap; /* BSS is 802.11N Capable */
389 /* 802.11N BSS Capabilities (based on HT_CAP_*): */
390 __le32 nbss_cap;
391 u8 ctl_ch; /* 802.11N BSS control channel number */
392 __le32 reserved32[1]; /* Reserved for expansion of BSS properties */
393 u8 flags; /* flags */
394 u8 reserved[3]; /* Reserved for expansion of BSS properties */
395 u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */
396
397 __le16 ie_offset; /* offset at which IEs start, from beginning */
398 __le32 ie_length; /* byte length of Information Elements */
399 __le16 SNR; /* average SNR of during frame reception */
400 /* Add new fields here */
401 /* variable length Information Elements */
402};
403
404struct brcm_rateset_le {
405 /* # rates in this set */
406 __le32 count;
407 /* rates in 500kbps units w/hi bit set if basic */
408 u8 rates[WL_NUMRATES];
409};
410
411struct brcmf_ssid {
412 u32 SSID_len;
413 unsigned char SSID[32];
414};
415
416struct brcmf_ssid_le {
417 __le32 SSID_len;
418 unsigned char SSID[32];
419};
420
421struct brcmf_scan_params_le {
422 struct brcmf_ssid_le ssid_le; /* default: {0, ""} */
423 u8 bssid[ETH_ALEN]; /* default: bcast */
424 s8 bss_type; /* default: any,
425 * DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT
426 */
427 u8 scan_type; /* flags, 0 use default */
428 __le32 nprobes; /* -1 use default, number of probes per channel */
429 __le32 active_time; /* -1 use default, dwell time per channel for
430 * active scanning
431 */
432 __le32 passive_time; /* -1 use default, dwell time per channel
433 * for passive scanning
434 */
435 __le32 home_time; /* -1 use default, dwell time for the
436 * home channel between channel scans
437 */
438 __le32 channel_num; /* count of channels and ssids that follow
439 *
440 * low half is count of channels in
441 * channel_list, 0 means default (use all
442 * available channels)
443 *
444 * high half is entries in struct brcmf_ssid
445 * array that follows channel_list, aligned for
446 * s32 (4 bytes) meaning an odd channel count
447 * implies a 2-byte pad between end of
448 * channel_list and first ssid
449 *
450 * if ssid count is zero, single ssid in the
451 * fixed parameter portion is assumed, otherwise
452 * ssid in the fixed portion is ignored
453 */
454 __le16 channel_list[1]; /* list of chanspecs */
455};
456
457/* incremental scan struct */
458struct brcmf_iscan_params_le {
459 __le32 version;
460 __le16 action;
461 __le16 scan_duration;
462 struct brcmf_scan_params_le params_le;
463};
464
465struct brcmf_scan_results {
466 u32 buflen;
467 u32 version;
468 u32 count;
469 struct brcmf_bss_info bss_info[1];
470};
471
472struct brcmf_scan_results_le {
473 __le32 buflen;
474 __le32 version;
475 __le32 count;
476 struct brcmf_bss_info bss_info[1];
477};
478
479/* used for association with a specific BSSID and chanspec list */
480struct brcmf_assoc_params_le {
481 /* 00:00:00:00:00:00: broadcast scan */
482 u8 bssid[ETH_ALEN];
483 /* 0: all available channels, otherwise count of chanspecs in
484 * chanspec_list */
485 __le32 chanspec_num;
486 /* list of chanspecs */
487 __le16 chanspec_list[1];
488};
489
490/* used for join with or without a specific bssid and channel list */
491struct brcmf_join_params {
492 struct brcmf_ssid_le ssid_le;
493 struct brcmf_assoc_params_le params_le;
494};
495
496/* size of brcmf_scan_results not including variable length array */
497#define BRCMF_SCAN_RESULTS_FIXED_SIZE \
498 (sizeof(struct brcmf_scan_results) - sizeof(struct brcmf_bss_info))
499
500/* incremental scan results struct */
501struct brcmf_iscan_results {
502 union {
503 u32 status;
504 __le32 status_le;
505 };
506 union {
507 struct brcmf_scan_results results;
508 struct brcmf_scan_results_le results_le;
509 };
510};
511
512/* size of brcmf_iscan_results not including variable length array */
513#define BRCMF_ISCAN_RESULTS_FIXED_SIZE \
514 (BRCMF_SCAN_RESULTS_FIXED_SIZE + \
515 offsetof(struct brcmf_iscan_results, results))
516
517struct brcmf_wsec_key {
518 u32 index; /* key index */
519 u32 len; /* key length */
520 u8 data[WLAN_MAX_KEY_LEN]; /* key data */
521 u32 pad_1[18];
522 u32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
523 u32 flags; /* misc flags */
524 u32 pad_2[3];
525 u32 iv_initialized; /* has IV been initialized already? */
526 u32 pad_3;
527 /* Rx IV */
528 struct {
529 u32 hi; /* upper 32 bits of IV */
530 u16 lo; /* lower 16 bits of IV */
531 } rxiv;
532 u32 pad_4[2];
533 u8 ea[ETH_ALEN]; /* per station */
534};
535
536/*
537 * dongle requires same struct as above but with fields in little endian order
538 */
539struct brcmf_wsec_key_le {
540 __le32 index; /* key index */
541 __le32 len; /* key length */
542 u8 data[WLAN_MAX_KEY_LEN]; /* key data */
543 __le32 pad_1[18];
544 __le32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
545 __le32 flags; /* misc flags */
546 __le32 pad_2[3];
547 __le32 iv_initialized; /* has IV been initialized already? */
548 __le32 pad_3;
549 /* Rx IV */
550 struct {
551 __le32 hi; /* upper 32 bits of IV */
552 __le16 lo; /* lower 16 bits of IV */
553 } rxiv;
554 __le32 pad_4[2];
555 u8 ea[ETH_ALEN]; /* per station */
556};
557
558/* Used to get specific STA parameters */
559struct brcmf_scb_val_le {
560 __le32 val;
561 u8 ea[ETH_ALEN];
562};
563
564/* channel encoding */
565struct brcmf_channel_info_le {
566 __le32 hw_channel;
567 __le32 target_channel;
568 __le32 scan_channel;
569};
570
571/* Bus independent dongle command */
572struct brcmf_dcmd {
573 uint cmd; /* common dongle cmd definition */
574 void *buf; /* pointer to user buffer */
575 uint len; /* length of user buffer */
576 u8 set; /* get or set request (optional) */
577 uint used; /* bytes read or written (optional) */
578 uint needed; /* bytes needed (optional) */
579};
580
581/* Forward decls for struct brcmf_pub (see below) */
582struct brcmf_bus; /* device bus info */
583struct brcmf_proto; /* device communication protocol info */
584struct brcmf_info; /* device driver info */
585struct brcmf_cfg80211_dev; /* cfg80211 device info */
586
587/* Common structure for module and instance linkage */
588struct brcmf_pub {
589 /* Linkage ponters */
590 struct brcmf_bus *bus;
591 struct brcmf_proto *prot;
592 struct brcmf_info *info;
593 struct brcmf_cfg80211_dev *config;
594
595 /* Internal brcmf items */
596 bool up; /* Driver up/down (to OS) */
597 bool txoff; /* Transmit flow-controlled */
598 enum brcmf_bus_state busstate;
599 uint hdrlen; /* Total BRCMF header length (proto + bus) */
600 uint maxctl; /* Max size rxctl request from proto to bus */
601 uint rxsz; /* Rx buffer size bus module should use */
602 u8 wme_dp; /* wme discard priority */
603
604 /* Dongle media info */
605 bool iswl; /* Dongle-resident driver is wl */
606 unsigned long drv_version; /* Version of dongle-resident driver */
607 u8 mac[ETH_ALEN]; /* MAC address obtained from dongle */
608 struct dngl_stats dstats; /* Stats for dongle-based data */
609
610 /* Additional stats for the bus level */
611
612 /* Data packets sent to dongle */
613 unsigned long tx_packets;
614 /* Multicast data packets sent to dongle */
615 unsigned long tx_multicast;
616 /* Errors in sending data to dongle */
617 unsigned long tx_errors;
618 /* Control packets sent to dongle */
619 unsigned long tx_ctlpkts;
620 /* Errors sending control frames to dongle */
621 unsigned long tx_ctlerrs;
622 /* Packets sent up the network interface */
623 unsigned long rx_packets;
624 /* Multicast packets sent up the network interface */
625 unsigned long rx_multicast;
626 /* Errors processing rx data packets */
627 unsigned long rx_errors;
628 /* Control frames processed from dongle */
629 unsigned long rx_ctlpkts;
630
631 /* Errors in processing rx control frames */
632 unsigned long rx_ctlerrs;
633 /* Packets dropped locally (no memory) */
634 unsigned long rx_dropped;
635 /* Packets flushed due to unscheduled sendup thread */
636 unsigned long rx_flushed;
637 /* Number of times dpc scheduled by watchdog timer */
638 unsigned long wd_dpc_sched;
639
640 /* Number of packets where header read-ahead was used. */
641 unsigned long rx_readahead_cnt;
642 /* Number of tx packets we had to realloc for headroom */
643 unsigned long tx_realloc;
644 /* Number of flow control pkts recvd */
645 unsigned long fc_packets;
646
647 /* Last error return */
648 int bcmerror;
649 uint tickcnt;
650
651 /* Last error from dongle */
652 int dongle_error;
653
654 /* Suspend disable flag flag */
655 int suspend_disable_flag; /* "1" to disable all extra powersaving
656 during suspend */
657 int in_suspend; /* flag set to 1 when early suspend called */
658 int dtim_skip; /* dtim skip , default 0 means wake each dtim */
659
660 /* Pkt filter defination */
661 char *pktfilter[100];
662 int pktfilter_count;
663
664 u8 country_code[BRCM_CNTRY_BUF_SZ];
665 char eventmask[BRCMF_EVENTING_MASK_LEN];
666
667};
668
669struct brcmf_if_event {
670 u8 ifidx;
671 u8 action;
672 u8 flags;
673 u8 bssidx;
674};
675
676struct bcmevent_name {
677 uint event;
678 const char *name;
679};
680
681extern const struct bcmevent_name bcmevent_names[];
682
683/* Indication from bus module regarding presence/insertion of dongle.
684 * Return struct brcmf_pub pointer, used as handle to OS module in later calls.
685 * Returned structure should have bus and prot pointers filled in.
686 * bus_hdrlen specifies required headroom for bus module header.
687 */
688extern struct brcmf_pub *brcmf_attach(struct brcmf_bus *bus,
689 uint bus_hdrlen);
690extern int brcmf_net_attach(struct brcmf_pub *drvr, int idx);
691extern int brcmf_netdev_wait_pend8021x(struct net_device *ndev);
692
693extern s32 brcmf_exec_dcmd(struct net_device *dev, u32 cmd, void *arg, u32 len);
694
695/* Indication from bus module regarding removal/absence of dongle */
696extern void brcmf_detach(struct brcmf_pub *drvr);
697
698/* Indication from bus module to change flow-control state */
699extern void brcmf_txflowcontrol(struct brcmf_pub *drvr, int ifidx, bool on);
700
701extern bool brcmf_c_prec_enq(struct brcmf_pub *drvr, struct pktq *q,
702 struct sk_buff *pkt, int prec);
703
704/* Receive frame for delivery to OS. Callee disposes of rxp. */
705extern void brcmf_rx_frame(struct brcmf_pub *drvr, int ifidx,
706 struct sk_buff *rxp, int numpkt);
707
708/* Return pointer to interface name */
709extern char *brcmf_ifname(struct brcmf_pub *drvr, int idx);
710
711/* Notify tx completion */
712extern void brcmf_txcomplete(struct brcmf_pub *drvr, struct sk_buff *txp,
713 bool success);
714
715/* Query dongle */
716extern int brcmf_proto_cdc_query_dcmd(struct brcmf_pub *drvr, int ifidx,
717 uint cmd, void *buf, uint len);
718
719/* OS independent layer functions */
720extern int brcmf_os_proto_block(struct brcmf_pub *drvr);
721extern int brcmf_os_proto_unblock(struct brcmf_pub *drvr);
722#ifdef BCMDBG
723extern int brcmf_write_to_file(struct brcmf_pub *drvr, u8 *buf, int size);
724#endif /* BCMDBG */
725
726extern int brcmf_ifname2idx(struct brcmf_info *drvr_priv, char *name);
727extern int brcmf_c_host_event(struct brcmf_info *drvr_priv, int *idx,
728 void *pktdata, struct brcmf_event_msg *,
729 void **data_ptr);
730
731extern void brcmf_c_init(void);
732
733extern int brcmf_add_if(struct brcmf_info *drvr_priv, int ifidx,
734 struct net_device *ndev, char *name, u8 *mac_addr,
735 u32 flags, u8 bssidx);
736extern void brcmf_del_if(struct brcmf_info *drvr_priv, int ifidx);
737
738/* Send packet to dongle via data channel */
739extern int brcmf_sendpkt(struct brcmf_pub *drvr, int ifidx,\
740 struct sk_buff *pkt);
741
742extern int brcmf_bus_start(struct brcmf_pub *drvr);
743
744extern void brcmf_c_pktfilter_offload_set(struct brcmf_pub *drvr, char *arg);
745extern void brcmf_c_pktfilter_offload_enable(struct brcmf_pub *drvr, char *arg,
746 int enable, int master_mode);
747
748#define BRCMF_DCMD_SMLEN 256 /* "small" cmd buffer required */
749#define BRCMF_DCMD_MEDLEN 1536 /* "med" cmd buffer required */
750#define BRCMF_DCMD_MAXLEN 8192 /* max length cmd buffer required */
751
752/* message levels */
753#define BRCMF_ERROR_VAL 0x0001
754#define BRCMF_TRACE_VAL 0x0002
755#define BRCMF_INFO_VAL 0x0004
756#define BRCMF_DATA_VAL 0x0008
757#define BRCMF_CTL_VAL 0x0010
758#define BRCMF_TIMER_VAL 0x0020
759#define BRCMF_HDRS_VAL 0x0040
760#define BRCMF_BYTES_VAL 0x0080
761#define BRCMF_INTR_VAL 0x0100
762#define BRCMF_GLOM_VAL 0x0400
763#define BRCMF_EVENT_VAL 0x0800
764#define BRCMF_BTA_VAL 0x1000
765#define BRCMF_ISCAN_VAL 0x2000
766
767/* Enter idle immediately (no timeout) */
768#define BRCMF_IDLE_IMMEDIATE (-1)
769#define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
770 when idle */
771#define BRCMF_IDLE_INTERVAL 1
772
773#endif /* _BRCMF_H_ */
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_bus.h b/drivers/staging/brcm80211/brcmfmac/dhd_bus.h
deleted file mode 100644
index a249407c9a1..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/dhd_bus.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCMF_BUS_H_
18#define _BRCMF_BUS_H_
19
20/* Packet alignment for most efficient SDIO (can change based on platform) */
21#define BRCMF_SDALIGN (1 << 6)
22
23/* watchdog polling interval in ms */
24#define BRCMF_WD_POLL_MS 10
25
26/*
27 * Exported from brcmf bus module (brcmf_usb, brcmf_sdio)
28 */
29
30/* Indicate (dis)interest in finding dongles. */
31extern int brcmf_bus_register(void);
32extern void brcmf_bus_unregister(void);
33
34/* obtain linux device object providing bus function */
35extern struct device *brcmf_bus_get_device(struct brcmf_bus *bus);
36
37/* Stop bus module: clear pending frames, disable data flow */
38extern void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus);
39
40/* Initialize bus module: prepare for communication w/dongle */
41extern int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr);
42
43/* Send a data frame to the dongle. Callee disposes of txp. */
44extern int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *txp);
45
46/* Send/receive a control message to/from the dongle.
47 * Expects caller to enforce a single outstanding transaction.
48 */
49extern int
50brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen);
51
52extern int
53brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen);
54
55extern void brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick);
56
57#endif /* _BRCMF_BUS_H_ */
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c b/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
deleted file mode 100644
index e34c5c3d1d5..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
+++ /dev/null
@@ -1,498 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*******************************************************************************
18 * Communicates with the dongle by using dcmd codes.
19 * For certain dcmd codes, the dongle interprets string data from the host.
20 ******************************************************************************/
21
22#include <linux/types.h>
23#include <linux/netdevice.h>
24#include <linux/sched.h>
25#include <defs.h>
26
27#include <brcmu_utils.h>
28#include <brcmu_wifi.h>
29
30#include "dhd.h"
31#include "dhd_proto.h"
32#include "dhd_bus.h"
33#include "dhd_dbg.h"
34
35struct brcmf_proto_cdc_dcmd {
36 __le32 cmd; /* dongle command value */
37 __le32 len; /* lower 16: output buflen;
38 * upper 16: input buflen (excludes header) */
39 __le32 flags; /* flag defns given below */
40 __le32 status; /* status code returned from the device */
41};
42
43/* Max valid buffer size that can be sent to the dongle */
44#define CDC_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN)
45
46/* CDC flag definitions */
47#define CDC_DCMD_ERROR 0x01 /* 1=cmd failed */
48#define CDC_DCMD_SET 0x02 /* 0=get, 1=set cmd */
49#define CDC_DCMD_IF_MASK 0xF000 /* I/F index */
50#define CDC_DCMD_IF_SHIFT 12
51#define CDC_DCMD_ID_MASK 0xFFFF0000 /* id an cmd pairing */
52#define CDC_DCMD_ID_SHIFT 16 /* ID Mask shift bits */
53#define CDC_DCMD_ID(flags) \
54 (((flags) & CDC_DCMD_ID_MASK) >> CDC_DCMD_ID_SHIFT)
55
56/*
57 * BDC header - Broadcom specific extension of CDC.
58 * Used on data packets to convey priority across USB.
59 */
60#define BDC_HEADER_LEN 4
61#define BDC_PROTO_VER 1 /* Protocol version */
62#define BDC_FLAG_VER_MASK 0xf0 /* Protocol version mask */
63#define BDC_FLAG_VER_SHIFT 4 /* Protocol version shift */
64#define BDC_FLAG_SUM_GOOD 0x04 /* Good RX checksums */
65#define BDC_FLAG_SUM_NEEDED 0x08 /* Dongle needs to do TX checksums */
66#define BDC_PRIORITY_MASK 0x7
67#define BDC_FLAG2_IF_MASK 0x0f /* packet rx interface in APSTA */
68#define BDC_FLAG2_IF_SHIFT 0
69
70#define BDC_GET_IF_IDX(hdr) \
71 ((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT))
72#define BDC_SET_IF_IDX(hdr, idx) \
73 ((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | \
74 ((idx) << BDC_FLAG2_IF_SHIFT)))
75
76struct brcmf_proto_bdc_header {
77 u8 flags;
78 u8 priority; /* 802.1d Priority, 4:7 flow control info for usb */
79 u8 flags2;
80 u8 rssi;
81};
82
83
84#define RETRIES 2 /* # of retries to retrieve matching dcmd response */
85#define BUS_HEADER_LEN (16+BRCMF_SDALIGN) /* Must be atleast SDPCM_RESERVE
86 * (amount of header tha might be added)
87 * plus any space that might be needed
88 * for alignment padding.
89 */
90#define ROUND_UP_MARGIN 2048 /* Biggest SDIO block size possible for
91 * round off at the end of buffer
92 */
93
94struct brcmf_proto {
95 u16 reqid;
96 u8 pending;
97 u32 lastcmd;
98 u8 bus_header[BUS_HEADER_LEN];
99 struct brcmf_proto_cdc_dcmd msg;
100 unsigned char buf[BRCMF_DCMD_MAXLEN + ROUND_UP_MARGIN];
101};
102
103static int brcmf_proto_cdc_msg(struct brcmf_pub *drvr)
104{
105 struct brcmf_proto *prot = drvr->prot;
106 int len = le32_to_cpu(prot->msg.len) +
107 sizeof(struct brcmf_proto_cdc_dcmd);
108
109 brcmf_dbg(TRACE, "Enter\n");
110
111 /* NOTE : cdc->msg.len holds the desired length of the buffer to be
112 * returned. Only up to CDC_MAX_MSG_SIZE of this buffer area
113 * is actually sent to the dongle
114 */
115 if (len > CDC_MAX_MSG_SIZE)
116 len = CDC_MAX_MSG_SIZE;
117
118 /* Send request */
119 return brcmf_sdbrcm_bus_txctl(drvr->bus, (unsigned char *)&prot->msg,
120 len);
121}
122
123static int brcmf_proto_cdc_cmplt(struct brcmf_pub *drvr, u32 id, u32 len)
124{
125 int ret;
126 struct brcmf_proto *prot = drvr->prot;
127
128 brcmf_dbg(TRACE, "Enter\n");
129
130 do {
131 ret = brcmf_sdbrcm_bus_rxctl(drvr->bus,
132 (unsigned char *)&prot->msg,
133 len + sizeof(struct brcmf_proto_cdc_dcmd));
134 if (ret < 0)
135 break;
136 } while (CDC_DCMD_ID(le32_to_cpu(prot->msg.flags)) != id);
137
138 return ret;
139}
140
141int
142brcmf_proto_cdc_query_dcmd(struct brcmf_pub *drvr, int ifidx, uint cmd,
143 void *buf, uint len)
144{
145 struct brcmf_proto *prot = drvr->prot;
146 struct brcmf_proto_cdc_dcmd *msg = &prot->msg;
147 void *info;
148 int ret = 0, retries = 0;
149 u32 id, flags;
150
151 brcmf_dbg(TRACE, "Enter\n");
152 brcmf_dbg(CTL, "cmd %d len %d\n", cmd, len);
153
154 /* Respond "bcmerror" and "bcmerrorstr" with local cache */
155 if (cmd == BRCMF_C_GET_VAR && buf) {
156 if (!strcmp((char *)buf, "bcmerrorstr")) {
157 strncpy((char *)buf, "bcm_error",
158 BCME_STRLEN);
159 goto done;
160 } else if (!strcmp((char *)buf, "bcmerror")) {
161 *(int *)buf = drvr->dongle_error;
162 goto done;
163 }
164 }
165
166 memset(msg, 0, sizeof(struct brcmf_proto_cdc_dcmd));
167
168 msg->cmd = cpu_to_le32(cmd);
169 msg->len = cpu_to_le32(len);
170 flags = (++prot->reqid << CDC_DCMD_ID_SHIFT);
171 flags = (flags & ~CDC_DCMD_IF_MASK) |
172 (ifidx << CDC_DCMD_IF_SHIFT);
173 msg->flags = cpu_to_le32(flags);
174
175 if (buf)
176 memcpy(prot->buf, buf, len);
177
178 ret = brcmf_proto_cdc_msg(drvr);
179 if (ret < 0) {
180 brcmf_dbg(ERROR, "brcmf_proto_cdc_msg failed w/status %d\n",
181 ret);
182 goto done;
183 }
184
185retry:
186 /* wait for interrupt and get first fragment */
187 ret = brcmf_proto_cdc_cmplt(drvr, prot->reqid, len);
188 if (ret < 0)
189 goto done;
190
191 flags = le32_to_cpu(msg->flags);
192 id = (flags & CDC_DCMD_ID_MASK) >> CDC_DCMD_ID_SHIFT;
193
194 if ((id < prot->reqid) && (++retries < RETRIES))
195 goto retry;
196 if (id != prot->reqid) {
197 brcmf_dbg(ERROR, "%s: unexpected request id %d (expected %d)\n",
198 brcmf_ifname(drvr, ifidx), id, prot->reqid);
199 ret = -EINVAL;
200 goto done;
201 }
202
203 /* Check info buffer */
204 info = (void *)&msg[1];
205
206 /* Copy info buffer */
207 if (buf) {
208 if (ret < (int)len)
209 len = ret;
210 memcpy(buf, info, len);
211 }
212
213 /* Check the ERROR flag */
214 if (flags & CDC_DCMD_ERROR) {
215 ret = le32_to_cpu(msg->status);
216 /* Cache error from dongle */
217 drvr->dongle_error = ret;
218 }
219
220done:
221 return ret;
222}
223
224int brcmf_proto_cdc_set_dcmd(struct brcmf_pub *drvr, int ifidx, uint cmd,
225 void *buf, uint len)
226{
227 struct brcmf_proto *prot = drvr->prot;
228 struct brcmf_proto_cdc_dcmd *msg = &prot->msg;
229 int ret = 0;
230 u32 flags, id;
231
232 brcmf_dbg(TRACE, "Enter\n");
233 brcmf_dbg(CTL, "cmd %d len %d\n", cmd, len);
234
235 memset(msg, 0, sizeof(struct brcmf_proto_cdc_dcmd));
236
237 msg->cmd = cpu_to_le32(cmd);
238 msg->len = cpu_to_le32(len);
239 flags = (++prot->reqid << CDC_DCMD_ID_SHIFT) | CDC_DCMD_SET;
240 flags = (flags & ~CDC_DCMD_IF_MASK) |
241 (ifidx << CDC_DCMD_IF_SHIFT);
242 msg->flags = cpu_to_le32(flags);
243
244 if (buf)
245 memcpy(prot->buf, buf, len);
246
247 ret = brcmf_proto_cdc_msg(drvr);
248 if (ret < 0)
249 goto done;
250
251 ret = brcmf_proto_cdc_cmplt(drvr, prot->reqid, len);
252 if (ret < 0)
253 goto done;
254
255 flags = le32_to_cpu(msg->flags);
256 id = (flags & CDC_DCMD_ID_MASK) >> CDC_DCMD_ID_SHIFT;
257
258 if (id != prot->reqid) {
259 brcmf_dbg(ERROR, "%s: unexpected request id %d (expected %d)\n",
260 brcmf_ifname(drvr, ifidx), id, prot->reqid);
261 ret = -EINVAL;
262 goto done;
263 }
264
265 /* Check the ERROR flag */
266 if (flags & CDC_DCMD_ERROR) {
267 ret = le32_to_cpu(msg->status);
268 /* Cache error from dongle */
269 drvr->dongle_error = ret;
270 }
271
272done:
273 return ret;
274}
275
276int
277brcmf_proto_dcmd(struct brcmf_pub *drvr, int ifidx, struct brcmf_dcmd *dcmd,
278 int len)
279{
280 struct brcmf_proto *prot = drvr->prot;
281 int ret = -1;
282
283 if (drvr->busstate == BRCMF_BUS_DOWN) {
284 brcmf_dbg(ERROR, "bus is down. we have nothing to do.\n");
285 return ret;
286 }
287 brcmf_os_proto_block(drvr);
288
289 brcmf_dbg(TRACE, "Enter\n");
290
291 if (len > BRCMF_DCMD_MAXLEN)
292 goto done;
293
294 if (prot->pending == true) {
295 brcmf_dbg(TRACE, "CDC packet is pending!!!! cmd=0x%x (%lu) lastcmd=0x%x (%lu)\n",
296 dcmd->cmd, (unsigned long)dcmd->cmd, prot->lastcmd,
297 (unsigned long)prot->lastcmd);
298 if (dcmd->cmd == BRCMF_C_SET_VAR ||
299 dcmd->cmd == BRCMF_C_GET_VAR)
300 brcmf_dbg(TRACE, "iovar cmd=%s\n", (char *)dcmd->buf);
301
302 goto done;
303 }
304
305 prot->pending = true;
306 prot->lastcmd = dcmd->cmd;
307 if (dcmd->set)
308 ret = brcmf_proto_cdc_set_dcmd(drvr, ifidx, dcmd->cmd,
309 dcmd->buf, len);
310 else {
311 ret = brcmf_proto_cdc_query_dcmd(drvr, ifidx, dcmd->cmd,
312 dcmd->buf, len);
313 if (ret > 0)
314 dcmd->used = ret -
315 sizeof(struct brcmf_proto_cdc_dcmd);
316 }
317
318 if (ret >= 0)
319 ret = 0;
320 else {
321 struct brcmf_proto_cdc_dcmd *msg = &prot->msg;
322 /* len == needed when set/query fails from dongle */
323 dcmd->needed = le32_to_cpu(msg->len);
324 }
325
326 /* Intercept the wme_dp dongle cmd here */
327 if (!ret && dcmd->cmd == BRCMF_C_SET_VAR &&
328 !strcmp(dcmd->buf, "wme_dp")) {
329 int slen;
330 __le32 val = 0;
331
332 slen = strlen("wme_dp") + 1;
333 if (len >= (int)(slen + sizeof(int)))
334 memcpy(&val, (char *)dcmd->buf + slen, sizeof(int));
335 drvr->wme_dp = (u8) le32_to_cpu(val);
336 }
337
338 prot->pending = false;
339
340done:
341 brcmf_os_proto_unblock(drvr);
342
343 return ret;
344}
345
346static bool pkt_sum_needed(struct sk_buff *skb)
347{
348 return skb->ip_summed == CHECKSUM_PARTIAL;
349}
350
351static void pkt_set_sum_good(struct sk_buff *skb, bool x)
352{
353 skb->ip_summed = (x ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
354}
355
356void brcmf_proto_hdrpush(struct brcmf_pub *drvr, int ifidx,
357 struct sk_buff *pktbuf)
358{
359 struct brcmf_proto_bdc_header *h;
360
361 brcmf_dbg(TRACE, "Enter\n");
362
363 /* Push BDC header used to convey priority for buses that don't */
364
365 skb_push(pktbuf, BDC_HEADER_LEN);
366
367 h = (struct brcmf_proto_bdc_header *)(pktbuf->data);
368
369 h->flags = (BDC_PROTO_VER << BDC_FLAG_VER_SHIFT);
370 if (pkt_sum_needed(pktbuf))
371 h->flags |= BDC_FLAG_SUM_NEEDED;
372
373 h->priority = (pktbuf->priority & BDC_PRIORITY_MASK);
374 h->flags2 = 0;
375 h->rssi = 0;
376 BDC_SET_IF_IDX(h, ifidx);
377}
378
379int brcmf_proto_hdrpull(struct brcmf_pub *drvr, int *ifidx,
380 struct sk_buff *pktbuf)
381{
382 struct brcmf_proto_bdc_header *h;
383
384 brcmf_dbg(TRACE, "Enter\n");
385
386 /* Pop BDC header used to convey priority for buses that don't */
387
388 if (pktbuf->len < BDC_HEADER_LEN) {
389 brcmf_dbg(ERROR, "rx data too short (%d < %d)\n",
390 pktbuf->len, BDC_HEADER_LEN);
391 return -EBADE;
392 }
393
394 h = (struct brcmf_proto_bdc_header *)(pktbuf->data);
395
396 *ifidx = BDC_GET_IF_IDX(h);
397 if (*ifidx >= BRCMF_MAX_IFS) {
398 brcmf_dbg(ERROR, "rx data ifnum out of range (%d)\n", *ifidx);
399 return -EBADE;
400 }
401
402 if (((h->flags & BDC_FLAG_VER_MASK) >> BDC_FLAG_VER_SHIFT) !=
403 BDC_PROTO_VER) {
404 brcmf_dbg(ERROR, "%s: non-BDC packet received, flags 0x%x\n",
405 brcmf_ifname(drvr, *ifidx), h->flags);
406 return -EBADE;
407 }
408
409 if (h->flags & BDC_FLAG_SUM_GOOD) {
410 brcmf_dbg(INFO, "%s: BDC packet received with good rx-csum, flags 0x%x\n",
411 brcmf_ifname(drvr, *ifidx), h->flags);
412 pkt_set_sum_good(pktbuf, true);
413 }
414
415 pktbuf->priority = h->priority & BDC_PRIORITY_MASK;
416
417 skb_pull(pktbuf, BDC_HEADER_LEN);
418
419 return 0;
420}
421
422int brcmf_proto_attach(struct brcmf_pub *drvr)
423{
424 struct brcmf_proto *cdc;
425
426 cdc = kzalloc(sizeof(struct brcmf_proto), GFP_ATOMIC);
427 if (!cdc)
428 goto fail;
429
430 /* ensure that the msg buf directly follows the cdc msg struct */
431 if ((unsigned long)(&cdc->msg + 1) != (unsigned long)cdc->buf) {
432 brcmf_dbg(ERROR, "struct brcmf_proto is not correctly defined\n");
433 goto fail;
434 }
435
436 drvr->prot = cdc;
437 drvr->hdrlen += BDC_HEADER_LEN;
438 drvr->maxctl = BRCMF_DCMD_MAXLEN +
439 sizeof(struct brcmf_proto_cdc_dcmd) + ROUND_UP_MARGIN;
440 return 0;
441
442fail:
443 kfree(cdc);
444 return -ENOMEM;
445}
446
447/* ~NOTE~ What if another thread is waiting on the semaphore? Holding it? */
448void brcmf_proto_detach(struct brcmf_pub *drvr)
449{
450 kfree(drvr->prot);
451 drvr->prot = NULL;
452}
453
454void brcmf_proto_dstats(struct brcmf_pub *drvr)
455{
456 /* No stats from dongle added yet, copy bus stats */
457 drvr->dstats.tx_packets = drvr->tx_packets;
458 drvr->dstats.tx_errors = drvr->tx_errors;
459 drvr->dstats.rx_packets = drvr->rx_packets;
460 drvr->dstats.rx_errors = drvr->rx_errors;
461 drvr->dstats.rx_dropped = drvr->rx_dropped;
462 drvr->dstats.multicast = drvr->rx_multicast;
463 return;
464}
465
466int brcmf_proto_init(struct brcmf_pub *drvr)
467{
468 int ret = 0;
469 char buf[128];
470
471 brcmf_dbg(TRACE, "Enter\n");
472
473 brcmf_os_proto_block(drvr);
474
475 /* Get the device MAC address */
476 strcpy(buf, "cur_etheraddr");
477 ret = brcmf_proto_cdc_query_dcmd(drvr, 0, BRCMF_C_GET_VAR,
478 buf, sizeof(buf));
479 if (ret < 0) {
480 brcmf_os_proto_unblock(drvr);
481 return ret;
482 }
483 memcpy(drvr->mac, buf, ETH_ALEN);
484
485 brcmf_os_proto_unblock(drvr);
486
487 ret = brcmf_c_preinit_dcmds(drvr);
488
489 /* Always assumes wl for now */
490 drvr->iswl = true;
491
492 return ret;
493}
494
495void brcmf_proto_stop(struct brcmf_pub *drvr)
496{
497 /* Nothing to do for CDC */
498}
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_common.c b/drivers/staging/brcm80211/brcmfmac/dhd_common.c
deleted file mode 100644
index 4075fd74dd9..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/dhd_common.c
+++ /dev/null
@@ -1,872 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#include <linux/kernel.h>
17#include <linux/string.h>
18#include <linux/sched.h>
19#include <linux/netdevice.h>
20#include <asm/unaligned.h>
21#include <defs.h>
22#include <brcmu_wifi.h>
23#include <brcmu_utils.h>
24#include "dhd.h"
25#include "dhd_bus.h"
26#include "dhd_proto.h"
27#include "dhd_dbg.h"
28
29#define BRCM_OUI "\x00\x10\x18"
30#define DOT11_OUI_LEN 3
31#define BCMILCP_BCM_SUBTYPE_EVENT 1
32#define PKTFILTER_BUF_SIZE 2048
33#define BRCMF_ARPOL_MODE 0xb /* agent|snoop|peer_autoreply */
34
35int brcmf_msg_level;
36
37#define MSGTRACE_VERSION 1
38
39#define BRCMF_PKT_FILTER_FIXED_LEN offsetof(struct brcmf_pkt_filter, u)
40#define BRCMF_PKT_FILTER_PATTERN_FIXED_LEN \
41 offsetof(struct brcmf_pkt_filter_pattern, mask_and_pattern)
42
43#ifdef BCMDBG
44static const char brcmf_version[] =
45 "Dongle Host Driver, version " BRCMF_VERSION_STR "\nCompiled on "
46 __DATE__ " at " __TIME__;
47#else
48static const char brcmf_version[] =
49 "Dongle Host Driver, version " BRCMF_VERSION_STR;
50#endif
51
52/* Message trace header */
53struct msgtrace_hdr {
54 u8 version;
55 u8 spare;
56 __be16 len; /* Len of the trace */
57 __be32 seqnum; /* Sequence number of message. Useful
58 * if the messsage has been lost
59 * because of DMA error or a bus reset
60 * (ex: SDIO Func2)
61 */
62 __be32 discarded_bytes; /* Number of discarded bytes because of
63 trace overflow */
64 __be32 discarded_printf; /* Number of discarded printf
65 because of trace overflow */
66} __packed;
67
68void brcmf_c_init(void)
69{
70 /* Init global variables at run-time, not as part of the declaration.
71 * This is required to support init/de-init of the driver.
72 * Initialization
73 * of globals as part of the declaration results in non-deterministic
74 * behaviour since the value of the globals may be different on the
75 * first time that the driver is initialized vs subsequent
76 * initializations.
77 */
78 brcmf_msg_level = BRCMF_ERROR_VAL;
79}
80
81bool brcmf_c_prec_enq(struct brcmf_pub *drvr, struct pktq *q,
82 struct sk_buff *pkt, int prec)
83{
84 struct sk_buff *p;
85 int eprec = -1; /* precedence to evict from */
86 bool discard_oldest;
87
88 /* Fast case, precedence queue is not full and we are also not
89 * exceeding total queue length
90 */
91 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
92 brcmu_pktq_penq(q, prec, pkt);
93 return true;
94 }
95
96 /* Determine precedence from which to evict packet, if any */
97 if (pktq_pfull(q, prec))
98 eprec = prec;
99 else if (pktq_full(q)) {
100 p = brcmu_pktq_peek_tail(q, &eprec);
101 if (eprec > prec)
102 return false;
103 }
104
105 /* Evict if needed */
106 if (eprec >= 0) {
107 /* Detect queueing to unconfigured precedence */
108 discard_oldest = ac_bitmap_tst(drvr->wme_dp, eprec);
109 if (eprec == prec && !discard_oldest)
110 return false; /* refuse newer (incoming) packet */
111 /* Evict packet according to discard policy */
112 p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
113 brcmu_pktq_pdeq_tail(q, eprec);
114 if (p == NULL)
115 brcmf_dbg(ERROR, "brcmu_pktq_penq() failed, oldest %d\n",
116 discard_oldest);
117
118 brcmu_pkt_buf_free_skb(p);
119 }
120
121 /* Enqueue */
122 p = brcmu_pktq_penq(q, prec, pkt);
123 if (p == NULL)
124 brcmf_dbg(ERROR, "brcmu_pktq_penq() failed\n");
125
126 return p != NULL;
127}
128
129#ifdef BCMDBG
130static void
131brcmf_c_show_host_event(struct brcmf_event_msg *event, void *event_data)
132{
133 uint i, status, reason;
134 bool group = false, flush_txq = false, link = false;
135 char *auth_str, *event_name;
136 unsigned char *buf;
137 char err_msg[256], eabuf[ETHER_ADDR_STR_LEN];
138 static struct {
139 uint event;
140 char *event_name;
141 } event_names[] = {
142 {
143 BRCMF_E_SET_SSID, "SET_SSID"}, {
144 BRCMF_E_JOIN, "JOIN"}, {
145 BRCMF_E_START, "START"}, {
146 BRCMF_E_AUTH, "AUTH"}, {
147 BRCMF_E_AUTH_IND, "AUTH_IND"}, {
148 BRCMF_E_DEAUTH, "DEAUTH"}, {
149 BRCMF_E_DEAUTH_IND, "DEAUTH_IND"}, {
150 BRCMF_E_ASSOC, "ASSOC"}, {
151 BRCMF_E_ASSOC_IND, "ASSOC_IND"}, {
152 BRCMF_E_REASSOC, "REASSOC"}, {
153 BRCMF_E_REASSOC_IND, "REASSOC_IND"}, {
154 BRCMF_E_DISASSOC, "DISASSOC"}, {
155 BRCMF_E_DISASSOC_IND, "DISASSOC_IND"}, {
156 BRCMF_E_QUIET_START, "START_QUIET"}, {
157 BRCMF_E_QUIET_END, "END_QUIET"}, {
158 BRCMF_E_BEACON_RX, "BEACON_RX"}, {
159 BRCMF_E_LINK, "LINK"}, {
160 BRCMF_E_MIC_ERROR, "MIC_ERROR"}, {
161 BRCMF_E_NDIS_LINK, "NDIS_LINK"}, {
162 BRCMF_E_ROAM, "ROAM"}, {
163 BRCMF_E_TXFAIL, "TXFAIL"}, {
164 BRCMF_E_PMKID_CACHE, "PMKID_CACHE"}, {
165 BRCMF_E_RETROGRADE_TSF, "RETROGRADE_TSF"}, {
166 BRCMF_E_PRUNE, "PRUNE"}, {
167 BRCMF_E_AUTOAUTH, "AUTOAUTH"}, {
168 BRCMF_E_EAPOL_MSG, "EAPOL_MSG"}, {
169 BRCMF_E_SCAN_COMPLETE, "SCAN_COMPLETE"}, {
170 BRCMF_E_ADDTS_IND, "ADDTS_IND"}, {
171 BRCMF_E_DELTS_IND, "DELTS_IND"}, {
172 BRCMF_E_BCNSENT_IND, "BCNSENT_IND"}, {
173 BRCMF_E_BCNRX_MSG, "BCNRX_MSG"}, {
174 BRCMF_E_BCNLOST_MSG, "BCNLOST_MSG"}, {
175 BRCMF_E_ROAM_PREP, "ROAM_PREP"}, {
176 BRCMF_E_PFN_NET_FOUND, "PNO_NET_FOUND"}, {
177 BRCMF_E_PFN_NET_LOST, "PNO_NET_LOST"}, {
178 BRCMF_E_RESET_COMPLETE, "RESET_COMPLETE"}, {
179 BRCMF_E_JOIN_START, "JOIN_START"}, {
180 BRCMF_E_ROAM_START, "ROAM_START"}, {
181 BRCMF_E_ASSOC_START, "ASSOC_START"}, {
182 BRCMF_E_IBSS_ASSOC, "IBSS_ASSOC"}, {
183 BRCMF_E_RADIO, "RADIO"}, {
184 BRCMF_E_PSM_WATCHDOG, "PSM_WATCHDOG"}, {
185 BRCMF_E_PROBREQ_MSG, "PROBREQ_MSG"}, {
186 BRCMF_E_SCAN_CONFIRM_IND, "SCAN_CONFIRM_IND"}, {
187 BRCMF_E_PSK_SUP, "PSK_SUP"}, {
188 BRCMF_E_COUNTRY_CODE_CHANGED, "COUNTRY_CODE_CHANGED"}, {
189 BRCMF_E_EXCEEDED_MEDIUM_TIME, "EXCEEDED_MEDIUM_TIME"}, {
190 BRCMF_E_ICV_ERROR, "ICV_ERROR"}, {
191 BRCMF_E_UNICAST_DECODE_ERROR, "UNICAST_DECODE_ERROR"}, {
192 BRCMF_E_MULTICAST_DECODE_ERROR, "MULTICAST_DECODE_ERROR"}, {
193 BRCMF_E_TRACE, "TRACE"}, {
194 BRCMF_E_ACTION_FRAME, "ACTION FRAME"}, {
195 BRCMF_E_ACTION_FRAME_COMPLETE, "ACTION FRAME TX COMPLETE"}, {
196 BRCMF_E_IF, "IF"}, {
197 BRCMF_E_RSSI, "RSSI"}, {
198 BRCMF_E_PFN_SCAN_COMPLETE, "SCAN_COMPLETE"}
199 };
200 uint event_type, flags, auth_type, datalen;
201 static u32 seqnum_prev;
202 struct msgtrace_hdr hdr;
203 u32 nblost;
204 char *s, *p;
205
206 event_type = be32_to_cpu(event->event_type);
207 flags = be16_to_cpu(event->flags);
208 status = be32_to_cpu(event->status);
209 reason = be32_to_cpu(event->reason);
210 auth_type = be32_to_cpu(event->auth_type);
211 datalen = be32_to_cpu(event->datalen);
212 /* debug dump of event messages */
213 sprintf(eabuf, "%pM", event->addr);
214
215 event_name = "UNKNOWN";
216 for (i = 0; i < ARRAY_SIZE(event_names); i++) {
217 if (event_names[i].event == event_type)
218 event_name = event_names[i].event_name;
219 }
220
221 brcmf_dbg(EVENT, "EVENT: %s, event ID = %d\n", event_name, event_type);
222 brcmf_dbg(EVENT, "flags 0x%04x, status %d, reason %d, auth_type %d MAC %s\n",
223 flags, status, reason, auth_type, eabuf);
224
225 if (flags & BRCMF_EVENT_MSG_LINK)
226 link = true;
227 if (flags & BRCMF_EVENT_MSG_GROUP)
228 group = true;
229 if (flags & BRCMF_EVENT_MSG_FLUSHTXQ)
230 flush_txq = true;
231
232 switch (event_type) {
233 case BRCMF_E_START:
234 case BRCMF_E_DEAUTH:
235 case BRCMF_E_DISASSOC:
236 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s\n", event_name, eabuf);
237 break;
238
239 case BRCMF_E_ASSOC_IND:
240 case BRCMF_E_REASSOC_IND:
241 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s\n", event_name, eabuf);
242 break;
243
244 case BRCMF_E_ASSOC:
245 case BRCMF_E_REASSOC:
246 if (status == BRCMF_E_STATUS_SUCCESS)
247 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, SUCCESS\n",
248 event_name, eabuf);
249 else if (status == BRCMF_E_STATUS_TIMEOUT)
250 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, TIMEOUT\n",
251 event_name, eabuf);
252 else if (status == BRCMF_E_STATUS_FAIL)
253 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, FAILURE, reason %d\n",
254 event_name, eabuf, (int)reason);
255 else
256 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, unexpected status %d\n",
257 event_name, eabuf, (int)status);
258 break;
259
260 case BRCMF_E_DEAUTH_IND:
261 case BRCMF_E_DISASSOC_IND:
262 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, reason %d\n",
263 event_name, eabuf, (int)reason);
264 break;
265
266 case BRCMF_E_AUTH:
267 case BRCMF_E_AUTH_IND:
268 if (auth_type == WLAN_AUTH_OPEN)
269 auth_str = "Open System";
270 else if (auth_type == WLAN_AUTH_SHARED_KEY)
271 auth_str = "Shared Key";
272 else {
273 sprintf(err_msg, "AUTH unknown: %d", (int)auth_type);
274 auth_str = err_msg;
275 }
276 if (event_type == BRCMF_E_AUTH_IND)
277 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, %s\n",
278 event_name, eabuf, auth_str);
279 else if (status == BRCMF_E_STATUS_SUCCESS)
280 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, %s, SUCCESS\n",
281 event_name, eabuf, auth_str);
282 else if (status == BRCMF_E_STATUS_TIMEOUT)
283 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, %s, TIMEOUT\n",
284 event_name, eabuf, auth_str);
285 else if (status == BRCMF_E_STATUS_FAIL) {
286 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, %s, FAILURE, reason %d\n",
287 event_name, eabuf, auth_str, (int)reason);
288 }
289
290 break;
291
292 case BRCMF_E_JOIN:
293 case BRCMF_E_ROAM:
294 case BRCMF_E_SET_SSID:
295 if (status == BRCMF_E_STATUS_SUCCESS)
296 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s\n",
297 event_name, eabuf);
298 else if (status == BRCMF_E_STATUS_FAIL)
299 brcmf_dbg(EVENT, "MACEVENT: %s, failed\n", event_name);
300 else if (status == BRCMF_E_STATUS_NO_NETWORKS)
301 brcmf_dbg(EVENT, "MACEVENT: %s, no networks found\n",
302 event_name);
303 else
304 brcmf_dbg(EVENT, "MACEVENT: %s, unexpected status %d\n",
305 event_name, (int)status);
306 break;
307
308 case BRCMF_E_BEACON_RX:
309 if (status == BRCMF_E_STATUS_SUCCESS)
310 brcmf_dbg(EVENT, "MACEVENT: %s, SUCCESS\n", event_name);
311 else if (status == BRCMF_E_STATUS_FAIL)
312 brcmf_dbg(EVENT, "MACEVENT: %s, FAIL\n", event_name);
313 else
314 brcmf_dbg(EVENT, "MACEVENT: %s, status %d\n",
315 event_name, status);
316 break;
317
318 case BRCMF_E_LINK:
319 brcmf_dbg(EVENT, "MACEVENT: %s %s\n",
320 event_name, link ? "UP" : "DOWN");
321 break;
322
323 case BRCMF_E_MIC_ERROR:
324 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s, Group %d, Flush %d\n",
325 event_name, eabuf, group, flush_txq);
326 break;
327
328 case BRCMF_E_ICV_ERROR:
329 case BRCMF_E_UNICAST_DECODE_ERROR:
330 case BRCMF_E_MULTICAST_DECODE_ERROR:
331 brcmf_dbg(EVENT, "MACEVENT: %s, MAC %s\n", event_name, eabuf);
332 break;
333
334 case BRCMF_E_TXFAIL:
335 brcmf_dbg(EVENT, "MACEVENT: %s, RA %s\n", event_name, eabuf);
336 break;
337
338 case BRCMF_E_SCAN_COMPLETE:
339 case BRCMF_E_PMKID_CACHE:
340 brcmf_dbg(EVENT, "MACEVENT: %s\n", event_name);
341 break;
342
343 case BRCMF_E_PFN_NET_FOUND:
344 case BRCMF_E_PFN_NET_LOST:
345 case BRCMF_E_PFN_SCAN_COMPLETE:
346 brcmf_dbg(EVENT, "PNOEVENT: %s\n", event_name);
347 break;
348
349 case BRCMF_E_PSK_SUP:
350 case BRCMF_E_PRUNE:
351 brcmf_dbg(EVENT, "MACEVENT: %s, status %d, reason %d\n",
352 event_name, (int)status, (int)reason);
353 break;
354
355 case BRCMF_E_TRACE:
356 buf = (unsigned char *) event_data;
357 memcpy(&hdr, buf, sizeof(struct msgtrace_hdr));
358
359 if (hdr.version != MSGTRACE_VERSION) {
360 brcmf_dbg(ERROR,
361 "MACEVENT: %s [unsupported version --> brcmf"
362 " version:%d dongle version:%d]\n",
363 event_name, MSGTRACE_VERSION, hdr.version);
364 /* Reset datalen to avoid display below */
365 datalen = 0;
366 break;
367 }
368
369 /* There are 2 bytes available at the end of data */
370 *(buf + sizeof(struct msgtrace_hdr)
371 + be16_to_cpu(hdr.len)) = '\0';
372
373 if (be32_to_cpu(hdr.discarded_bytes)
374 || be32_to_cpu(hdr.discarded_printf))
375 brcmf_dbg(ERROR,
376 "WLC_E_TRACE: [Discarded traces in dongle -->"
377 " discarded_bytes %d discarded_printf %d]\n",
378 be32_to_cpu(hdr.discarded_bytes),
379 be32_to_cpu(hdr.discarded_printf));
380
381 nblost = be32_to_cpu(hdr.seqnum) - seqnum_prev - 1;
382 if (nblost > 0)
383 brcmf_dbg(ERROR, "WLC_E_TRACE: [Event lost --> seqnum "
384 " %d nblost %d\n", be32_to_cpu(hdr.seqnum),
385 nblost);
386 seqnum_prev = be32_to_cpu(hdr.seqnum);
387
388 /* Display the trace buffer. Advance from \n to \n to
389 * avoid display big
390 * printf (issue with Linux printk )
391 */
392 p = (char *)&buf[sizeof(struct msgtrace_hdr)];
393 while ((s = strstr(p, "\n")) != NULL) {
394 *s = '\0';
395 printk(KERN_DEBUG"%s\n", p);
396 p = s + 1;
397 }
398 printk(KERN_DEBUG "%s\n", p);
399
400 /* Reset datalen to avoid display below */
401 datalen = 0;
402 break;
403
404 case BRCMF_E_RSSI:
405 brcmf_dbg(EVENT, "MACEVENT: %s %d\n",
406 event_name, be32_to_cpu(*((__be32 *)event_data)));
407 break;
408
409 default:
410 brcmf_dbg(EVENT,
411 "MACEVENT: %s %d, MAC %s, status %d, reason %d, "
412 "auth %d\n", event_name, event_type, eabuf,
413 (int)status, (int)reason, (int)auth_type);
414 break;
415 }
416
417 /* show any appended data */
418 if (datalen) {
419 buf = (unsigned char *) event_data;
420 brcmf_dbg(EVENT, " data (%d) : ", datalen);
421 for (i = 0; i < datalen; i++)
422 brcmf_dbg(EVENT, " 0x%02x ", *buf++);
423 brcmf_dbg(EVENT, "\n");
424 }
425}
426#endif /* BCMDBG */
427
428int
429brcmf_c_host_event(struct brcmf_info *drvr_priv, int *ifidx, void *pktdata,
430 struct brcmf_event_msg *event, void **data_ptr)
431{
432 /* check whether packet is a BRCM event pkt */
433 struct brcmf_event *pvt_data = (struct brcmf_event *) pktdata;
434 struct brcmf_if_event *ifevent;
435 char *event_data;
436 u32 type, status;
437 u16 flags;
438 int evlen;
439
440 if (memcmp(BRCM_OUI, &pvt_data->hdr.oui[0], DOT11_OUI_LEN)) {
441 brcmf_dbg(ERROR, "mismatched OUI, bailing\n");
442 return -EBADE;
443 }
444
445 /* BRCM event pkt may be unaligned - use xxx_ua to load user_subtype. */
446 if (get_unaligned_be16(&pvt_data->hdr.usr_subtype) !=
447 BCMILCP_BCM_SUBTYPE_EVENT) {
448 brcmf_dbg(ERROR, "mismatched subtype, bailing\n");
449 return -EBADE;
450 }
451
452 *data_ptr = &pvt_data[1];
453 event_data = *data_ptr;
454
455 /* memcpy since BRCM event pkt may be unaligned. */
456 memcpy(event, &pvt_data->msg, sizeof(struct brcmf_event_msg));
457
458 type = get_unaligned_be32(&event->event_type);
459 flags = get_unaligned_be16(&event->flags);
460 status = get_unaligned_be32(&event->status);
461 evlen = get_unaligned_be32(&event->datalen) +
462 sizeof(struct brcmf_event);
463
464 switch (type) {
465 case BRCMF_E_IF:
466 ifevent = (struct brcmf_if_event *) event_data;
467 brcmf_dbg(TRACE, "if event\n");
468
469 if (ifevent->ifidx > 0 && ifevent->ifidx < BRCMF_MAX_IFS) {
470 if (ifevent->action == BRCMF_E_IF_ADD)
471 brcmf_add_if(drvr_priv, ifevent->ifidx, NULL,
472 event->ifname,
473 pvt_data->eth.h_dest,
474 ifevent->flags, ifevent->bssidx);
475 else
476 brcmf_del_if(drvr_priv, ifevent->ifidx);
477 } else {
478 brcmf_dbg(ERROR, "Invalid ifidx %d for %s\n",
479 ifevent->ifidx, event->ifname);
480 }
481
482 /* send up the if event: btamp user needs it */
483 *ifidx = brcmf_ifname2idx(drvr_priv, event->ifname);
484 break;
485
486 /* These are what external supplicant/authenticator wants */
487 case BRCMF_E_LINK:
488 case BRCMF_E_ASSOC_IND:
489 case BRCMF_E_REASSOC_IND:
490 case BRCMF_E_DISASSOC_IND:
491 case BRCMF_E_MIC_ERROR:
492 default:
493 /* Fall through: this should get _everything_ */
494
495 *ifidx = brcmf_ifname2idx(drvr_priv, event->ifname);
496 brcmf_dbg(TRACE, "MAC event %d, flags %x, status %x\n",
497 type, flags, status);
498
499 /* put it back to BRCMF_E_NDIS_LINK */
500 if (type == BRCMF_E_NDIS_LINK) {
501 u32 temp1;
502 __be32 temp2;
503
504 temp1 = get_unaligned_be32(&event->event_type);
505 brcmf_dbg(TRACE, "Converted to WLC_E_LINK type %d\n",
506 temp1);
507
508 temp2 = cpu_to_be32(BRCMF_E_NDIS_LINK);
509 memcpy((void *)(&pvt_data->msg.event_type), &temp2,
510 sizeof(pvt_data->msg.event_type));
511 }
512 break;
513 }
514
515#ifdef BCMDBG
516 brcmf_c_show_host_event(event, event_data);
517#endif /* BCMDBG */
518
519 return 0;
520}
521
522/* Convert user's input in hex pattern to byte-size mask */
523static int brcmf_c_pattern_atoh(char *src, char *dst)
524{
525 int i;
526 if (strncmp(src, "0x", 2) != 0 && strncmp(src, "0X", 2) != 0) {
527 brcmf_dbg(ERROR, "Mask invalid format. Needs to start with 0x\n");
528 return -EINVAL;
529 }
530 src = src + 2; /* Skip past 0x */
531 if (strlen(src) % 2 != 0) {
532 brcmf_dbg(ERROR, "Mask invalid format. Length must be even.\n");
533 return -EINVAL;
534 }
535 for (i = 0; *src != '\0'; i++) {
536 unsigned long res;
537 char num[3];
538 strncpy(num, src, 2);
539 num[2] = '\0';
540 if (kstrtoul(num, 16, &res))
541 return -EINVAL;
542 dst[i] = (u8)res;
543 src += 2;
544 }
545 return i;
546}
547
548void
549brcmf_c_pktfilter_offload_enable(struct brcmf_pub *drvr, char *arg, int enable,
550 int master_mode)
551{
552 unsigned long res;
553 char *argv[8];
554 int i = 0;
555 const char *str;
556 int buf_len;
557 int str_len;
558 char *arg_save = NULL, *arg_org = NULL;
559 int rc;
560 char buf[128];
561 struct brcmf_pkt_filter_enable enable_parm;
562 struct brcmf_pkt_filter_enable *pkt_filterp;
563
564 arg_save = kmalloc(strlen(arg) + 1, GFP_ATOMIC);
565 if (!arg_save)
566 goto fail;
567
568 arg_org = arg_save;
569 memcpy(arg_save, arg, strlen(arg) + 1);
570
571 argv[i] = strsep(&arg_save, " ");
572
573 i = 0;
574 if (NULL == argv[i]) {
575 brcmf_dbg(ERROR, "No args provided\n");
576 goto fail;
577 }
578
579 str = "pkt_filter_enable";
580 str_len = strlen(str);
581 strncpy(buf, str, str_len);
582 buf[str_len] = '\0';
583 buf_len = str_len + 1;
584
585 pkt_filterp = (struct brcmf_pkt_filter_enable *) (buf + str_len + 1);
586
587 /* Parse packet filter id. */
588 enable_parm.id = 0;
589 if (!kstrtoul(argv[i], 0, &res))
590 enable_parm.id = (u32)res;
591
592 /* Parse enable/disable value. */
593 enable_parm.enable = enable;
594
595 buf_len += sizeof(enable_parm);
596 memcpy((char *)pkt_filterp, &enable_parm, sizeof(enable_parm));
597
598 /* Enable/disable the specified filter. */
599 rc = brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, buf, buf_len);
600 rc = rc >= 0 ? 0 : rc;
601 if (rc)
602 brcmf_dbg(TRACE, "failed to add pktfilter %s, retcode = %d\n",
603 arg, rc);
604 else
605 brcmf_dbg(TRACE, "successfully added pktfilter %s\n", arg);
606
607 /* Contorl the master mode */
608 brcmu_mkiovar("pkt_filter_mode", (char *)&master_mode, 4, buf,
609 sizeof(buf));
610 rc = brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, buf,
611 sizeof(buf));
612 rc = rc >= 0 ? 0 : rc;
613 if (rc)
614 brcmf_dbg(TRACE, "failed to add pktfilter %s, retcode = %d\n",
615 arg, rc);
616
617fail:
618 kfree(arg_org);
619}
620
621void brcmf_c_pktfilter_offload_set(struct brcmf_pub *drvr, char *arg)
622{
623 const char *str;
624 struct brcmf_pkt_filter pkt_filter;
625 struct brcmf_pkt_filter *pkt_filterp;
626 unsigned long res;
627 int buf_len;
628 int str_len;
629 int rc;
630 u32 mask_size;
631 u32 pattern_size;
632 char *argv[8], *buf = NULL;
633 int i = 0;
634 char *arg_save = NULL, *arg_org = NULL;
635
636 arg_save = kstrdup(arg, GFP_ATOMIC);
637 if (!arg_save)
638 goto fail;
639
640 arg_org = arg_save;
641
642 buf = kmalloc(PKTFILTER_BUF_SIZE, GFP_ATOMIC);
643 if (!buf)
644 goto fail;
645
646 argv[i] = strsep(&arg_save, " ");
647 while (argv[i++])
648 argv[i] = strsep(&arg_save, " ");
649
650 i = 0;
651 if (NULL == argv[i]) {
652 brcmf_dbg(ERROR, "No args provided\n");
653 goto fail;
654 }
655
656 str = "pkt_filter_add";
657 strcpy(buf, str);
658 str_len = strlen(str);
659 buf_len = str_len + 1;
660
661 pkt_filterp = (struct brcmf_pkt_filter *) (buf + str_len + 1);
662
663 /* Parse packet filter id. */
664 pkt_filter.id = 0;
665 if (!kstrtoul(argv[i], 0, &res))
666 pkt_filter.id = (u32)res;
667
668 if (NULL == argv[++i]) {
669 brcmf_dbg(ERROR, "Polarity not provided\n");
670 goto fail;
671 }
672
673 /* Parse filter polarity. */
674 pkt_filter.negate_match = 0;
675 if (!kstrtoul(argv[i], 0, &res))
676 pkt_filter.negate_match = (u32)res;
677
678 if (NULL == argv[++i]) {
679 brcmf_dbg(ERROR, "Filter type not provided\n");
680 goto fail;
681 }
682
683 /* Parse filter type. */
684 pkt_filter.type = 0;
685 if (!kstrtoul(argv[i], 0, &res))
686 pkt_filter.type = (u32)res;
687
688 if (NULL == argv[++i]) {
689 brcmf_dbg(ERROR, "Offset not provided\n");
690 goto fail;
691 }
692
693 /* Parse pattern filter offset. */
694 pkt_filter.u.pattern.offset = 0;
695 if (!kstrtoul(argv[i], 0, &res))
696 pkt_filter.u.pattern.offset = (u32)res;
697
698 if (NULL == argv[++i]) {
699 brcmf_dbg(ERROR, "Bitmask not provided\n");
700 goto fail;
701 }
702
703 /* Parse pattern filter mask. */
704 mask_size =
705 brcmf_c_pattern_atoh
706 (argv[i], (char *)pkt_filterp->u.pattern.mask_and_pattern);
707
708 if (NULL == argv[++i]) {
709 brcmf_dbg(ERROR, "Pattern not provided\n");
710 goto fail;
711 }
712
713 /* Parse pattern filter pattern. */
714 pattern_size =
715 brcmf_c_pattern_atoh(argv[i],
716 (char *)&pkt_filterp->u.pattern.
717 mask_and_pattern[mask_size]);
718
719 if (mask_size != pattern_size) {
720 brcmf_dbg(ERROR, "Mask and pattern not the same size\n");
721 goto fail;
722 }
723
724 pkt_filter.u.pattern.size_bytes = mask_size;
725 buf_len += BRCMF_PKT_FILTER_FIXED_LEN;
726 buf_len += (BRCMF_PKT_FILTER_PATTERN_FIXED_LEN + 2 * mask_size);
727
728 /* Keep-alive attributes are set in local
729 * variable (keep_alive_pkt), and
730 ** then memcpy'ed into buffer (keep_alive_pktp) since there is no
731 ** guarantee that the buffer is properly aligned.
732 */
733 memcpy((char *)pkt_filterp,
734 &pkt_filter,
735 BRCMF_PKT_FILTER_FIXED_LEN + BRCMF_PKT_FILTER_PATTERN_FIXED_LEN);
736
737 rc = brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, buf, buf_len);
738 rc = rc >= 0 ? 0 : rc;
739
740 if (rc)
741 brcmf_dbg(TRACE, "failed to add pktfilter %s, retcode = %d\n",
742 arg, rc);
743 else
744 brcmf_dbg(TRACE, "successfully added pktfilter %s\n", arg);
745
746fail:
747 kfree(arg_org);
748
749 kfree(buf);
750}
751
752static void brcmf_c_arp_offload_set(struct brcmf_pub *drvr, int arp_mode)
753{
754 char iovbuf[32];
755 int retcode;
756
757 brcmu_mkiovar("arp_ol", (char *)&arp_mode, 4, iovbuf, sizeof(iovbuf));
758 retcode = brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR,
759 iovbuf, sizeof(iovbuf));
760 retcode = retcode >= 0 ? 0 : retcode;
761 if (retcode)
762 brcmf_dbg(TRACE, "failed to set ARP offload mode to 0x%x, retcode = %d\n",
763 arp_mode, retcode);
764 else
765 brcmf_dbg(TRACE, "successfully set ARP offload mode to 0x%x\n",
766 arp_mode);
767}
768
769static void brcmf_c_arp_offload_enable(struct brcmf_pub *drvr, int arp_enable)
770{
771 char iovbuf[32];
772 int retcode;
773
774 brcmu_mkiovar("arpoe", (char *)&arp_enable, 4, iovbuf, sizeof(iovbuf));
775 retcode = brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR,
776 iovbuf, sizeof(iovbuf));
777 retcode = retcode >= 0 ? 0 : retcode;
778 if (retcode)
779 brcmf_dbg(TRACE, "failed to enable ARP offload to %d, retcode = %d\n",
780 arp_enable, retcode);
781 else
782 brcmf_dbg(TRACE, "successfully enabled ARP offload to %d\n",
783 arp_enable);
784}
785
786int brcmf_c_preinit_dcmds(struct brcmf_pub *drvr)
787{
788 char iovbuf[BRCMF_EVENTING_MASK_LEN + 12]; /* Room for
789 "event_msgs" + '\0' + bitvec */
790 uint up = 0;
791 char buf[128], *ptr;
792 u32 dongle_align = BRCMF_SDALIGN;
793 u32 glom = 0;
794 u32 roaming = 1;
795 uint bcn_timeout = 3;
796 int scan_assoc_time = 40;
797 int scan_unassoc_time = 40;
798 int i;
799
800 brcmf_os_proto_block(drvr);
801
802 /* Set Country code */
803 if (drvr->country_code[0] != 0) {
804 if (brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_COUNTRY,
805 drvr->country_code,
806 sizeof(drvr->country_code)) < 0)
807 brcmf_dbg(ERROR, "country code setting failed\n");
808 }
809
810 /* query for 'ver' to get version info from firmware */
811 memset(buf, 0, sizeof(buf));
812 ptr = buf;
813 brcmu_mkiovar("ver", NULL, 0, buf, sizeof(buf));
814 brcmf_proto_cdc_query_dcmd(drvr, 0, BRCMF_C_GET_VAR, buf, sizeof(buf));
815 strsep(&ptr, "\n");
816 /* Print fw version info */
817 brcmf_dbg(ERROR, "Firmware version = %s\n", buf);
818
819 /* Match Host and Dongle rx alignment */
820 brcmu_mkiovar("bus:txglomalign", (char *)&dongle_align, 4, iovbuf,
821 sizeof(iovbuf));
822 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, iovbuf,
823 sizeof(iovbuf));
824
825 /* disable glom option per default */
826 brcmu_mkiovar("bus:txglom", (char *)&glom, 4, iovbuf, sizeof(iovbuf));
827 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, iovbuf,
828 sizeof(iovbuf));
829
830 /* Setup timeout if Beacons are lost and roam is off to report
831 link down */
832 brcmu_mkiovar("bcn_timeout", (char *)&bcn_timeout, 4, iovbuf,
833 sizeof(iovbuf));
834 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, iovbuf,
835 sizeof(iovbuf));
836
837 /* Enable/Disable build-in roaming to allowed ext supplicant to take
838 of romaing */
839 brcmu_mkiovar("roam_off", (char *)&roaming, 4,
840 iovbuf, sizeof(iovbuf));
841 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, iovbuf,
842 sizeof(iovbuf));
843
844 /* Force STA UP */
845 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_UP, (char *)&up, sizeof(up));
846
847 /* Setup event_msgs */
848 brcmu_mkiovar("event_msgs", drvr->eventmask, BRCMF_EVENTING_MASK_LEN,
849 iovbuf, sizeof(iovbuf));
850 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_VAR, iovbuf,
851 sizeof(iovbuf));
852
853 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_SCAN_CHANNEL_TIME,
854 (char *)&scan_assoc_time, sizeof(scan_assoc_time));
855 brcmf_proto_cdc_set_dcmd(drvr, 0, BRCMF_C_SET_SCAN_UNASSOC_TIME,
856 (char *)&scan_unassoc_time, sizeof(scan_unassoc_time));
857
858 /* Set and enable ARP offload feature */
859 brcmf_c_arp_offload_set(drvr, BRCMF_ARPOL_MODE);
860 brcmf_c_arp_offload_enable(drvr, true);
861
862 /* Set up pkt filter */
863 for (i = 0; i < drvr->pktfilter_count; i++) {
864 brcmf_c_pktfilter_offload_set(drvr, drvr->pktfilter[i]);
865 brcmf_c_pktfilter_offload_enable(drvr, drvr->pktfilter[i],
866 0, true);
867 }
868
869 brcmf_os_proto_unblock(drvr);
870
871 return 0;
872}
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_dbg.h b/drivers/staging/brcm80211/brcmfmac/dhd_dbg.h
deleted file mode 100644
index 7467922f053..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/dhd_dbg.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCMF_DBG_H_
18#define _BRCMF_DBG_H_
19
20#if defined(BCMDBG)
21
22#define brcmf_dbg(level, fmt, ...) \
23do { \
24 if (BRCMF_ERROR_VAL == BRCMF_##level##_VAL) { \
25 if (brcmf_msg_level & BRCMF_##level##_VAL) { \
26 if (net_ratelimit()) \
27 printk(KERN_DEBUG "%s: " fmt, \
28 __func__, ##__VA_ARGS__); \
29 } \
30 } else { \
31 if (brcmf_msg_level & BRCMF_##level##_VAL) { \
32 printk(KERN_DEBUG "%s: " fmt, \
33 __func__, ##__VA_ARGS__); \
34 } \
35 } \
36} while (0)
37
38#define BRCMF_DATA_ON() (brcmf_msg_level & BRCMF_DATA_VAL)
39#define BRCMF_CTL_ON() (brcmf_msg_level & BRCMF_CTL_VAL)
40#define BRCMF_HDRS_ON() (brcmf_msg_level & BRCMF_HDRS_VAL)
41#define BRCMF_BYTES_ON() (brcmf_msg_level & BRCMF_BYTES_VAL)
42#define BRCMF_GLOM_ON() (brcmf_msg_level & BRCMF_GLOM_VAL)
43
44#else /* (defined BCMDBG) || (defined BCMDBG) */
45
46#define brcmf_dbg(level, fmt, ...) no_printk(fmt, ##__VA_ARGS__)
47
48#define BRCMF_DATA_ON() 0
49#define BRCMF_CTL_ON() 0
50#define BRCMF_HDRS_ON() 0
51#define BRCMF_BYTES_ON() 0
52#define BRCMF_GLOM_ON() 0
53
54#endif /* defined(BCMDBG) */
55
56extern int brcmf_msg_level;
57
58#endif /* _BRCMF_DBG_H_ */
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_linux.c b/drivers/staging/brcm80211/brcmfmac/dhd_linux.c
deleted file mode 100644
index 99ba5e3e45f..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/dhd_linux.c
+++ /dev/null
@@ -1,1354 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/kthread.h>
20#include <linux/slab.h>
21#include <linux/skbuff.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/mmc/sdio_func.h>
25#include <linux/random.h>
26#include <linux/spinlock.h>
27#include <linux/ethtool.h>
28#include <linux/fcntl.h>
29#include <linux/fs.h>
30#include <linux/uaccess.h>
31#include <linux/hardirq.h>
32#include <linux/mutex.h>
33#include <linux/wait.h>
34#include <net/cfg80211.h>
35#include <net/rtnetlink.h>
36#include <defs.h>
37#include <brcmu_utils.h>
38#include <brcmu_wifi.h>
39
40#include "dhd.h"
41#include "dhd_bus.h"
42#include "dhd_proto.h"
43#include "dhd_dbg.h"
44#include "wl_cfg80211.h"
45#include "bcmchip.h"
46
47MODULE_AUTHOR("Broadcom Corporation");
48MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN fullmac driver.");
49MODULE_SUPPORTED_DEVICE("Broadcom 802.11n WLAN fullmac cards");
50MODULE_LICENSE("Dual BSD/GPL");
51
52
53/* Interface control information */
54struct brcmf_if {
55 struct brcmf_info *info; /* back pointer to brcmf_info */
56 /* OS/stack specifics */
57 struct net_device *ndev;
58 struct net_device_stats stats;
59 int idx; /* iface idx in dongle */
60 int state; /* interface state */
61 u8 mac_addr[ETH_ALEN]; /* assigned MAC address */
62};
63
64/* Local private structure (extension of pub) */
65struct brcmf_info {
66 struct brcmf_pub pub;
67
68 /* OS/stack specifics */
69 struct brcmf_if *iflist[BRCMF_MAX_IFS];
70
71 struct mutex proto_block;
72
73 struct work_struct setmacaddr_work;
74 struct work_struct multicast_work;
75 u8 macvalue[ETH_ALEN];
76 atomic_t pend_8021x_cnt;
77};
78
79/* Error bits */
80module_param(brcmf_msg_level, int, 0);
81
82
83static int brcmf_net2idx(struct brcmf_info *drvr_priv, struct net_device *ndev)
84{
85 int i = 0;
86
87 while (i < BRCMF_MAX_IFS) {
88 if (drvr_priv->iflist[i] && drvr_priv->iflist[i]->ndev == ndev)
89 return i;
90 i++;
91 }
92
93 return BRCMF_BAD_IF;
94}
95
96int brcmf_ifname2idx(struct brcmf_info *drvr_priv, char *name)
97{
98 int i = BRCMF_MAX_IFS;
99 struct brcmf_if *ifp;
100
101 if (name == NULL || *name == '\0')
102 return 0;
103
104 while (--i > 0) {
105 ifp = drvr_priv->iflist[i];
106 if (ifp && !strncmp(ifp->ndev->name, name, IFNAMSIZ))
107 break;
108 }
109
110 brcmf_dbg(TRACE, "return idx %d for \"%s\"\n", i, name);
111
112 return i; /* default - the primary interface */
113}
114
115char *brcmf_ifname(struct brcmf_pub *drvr, int ifidx)
116{
117 struct brcmf_info *drvr_priv = drvr->info;
118
119 if (ifidx < 0 || ifidx >= BRCMF_MAX_IFS) {
120 brcmf_dbg(ERROR, "ifidx %d out of range\n", ifidx);
121 return "<if_bad>";
122 }
123
124 if (drvr_priv->iflist[ifidx] == NULL) {
125 brcmf_dbg(ERROR, "null i/f %d\n", ifidx);
126 return "<if_null>";
127 }
128
129 if (drvr_priv->iflist[ifidx]->ndev)
130 return drvr_priv->iflist[ifidx]->ndev->name;
131
132 return "<if_none>";
133}
134
135static void _brcmf_set_multicast_list(struct work_struct *work)
136{
137 struct net_device *ndev;
138 struct netdev_hw_addr *ha;
139 u32 allmulti, cnt;
140 __le32 cnt_le;
141 __le32 allmulti_le;
142
143 struct brcmf_dcmd dcmd;
144 char *buf, *bufp;
145 uint buflen;
146 int ret;
147
148 struct brcmf_info *drvr_priv = container_of(work, struct brcmf_info,
149 multicast_work);
150
151 ndev = drvr_priv->iflist[0]->ndev;
152 cnt = netdev_mc_count(ndev);
153
154 /* Determine initial value of allmulti flag */
155 allmulti = (ndev->flags & IFF_ALLMULTI) ? true : false;
156
157 /* Send down the multicast list first. */
158
159 buflen = sizeof("mcast_list") + sizeof(cnt) + (cnt * ETH_ALEN);
160 bufp = buf = kmalloc(buflen, GFP_ATOMIC);
161 if (!bufp)
162 return;
163
164 strcpy(bufp, "mcast_list");
165 bufp += strlen("mcast_list") + 1;
166
167 cnt_le = cpu_to_le32(cnt);
168 memcpy(bufp, &cnt_le, sizeof(cnt));
169 bufp += sizeof(cnt_le);
170
171 netdev_for_each_mc_addr(ha, ndev) {
172 if (!cnt)
173 break;
174 memcpy(bufp, ha->addr, ETH_ALEN);
175 bufp += ETH_ALEN;
176 cnt--;
177 }
178
179 memset(&dcmd, 0, sizeof(dcmd));
180 dcmd.cmd = BRCMF_C_SET_VAR;
181 dcmd.buf = buf;
182 dcmd.len = buflen;
183 dcmd.set = true;
184
185 ret = brcmf_proto_dcmd(&drvr_priv->pub, 0, &dcmd, dcmd.len);
186 if (ret < 0) {
187 brcmf_dbg(ERROR, "%s: set mcast_list failed, cnt %d\n",
188 brcmf_ifname(&drvr_priv->pub, 0), cnt);
189 allmulti = cnt ? true : allmulti;
190 }
191
192 kfree(buf);
193
194 /* Now send the allmulti setting. This is based on the setting in the
195 * net_device flags, but might be modified above to be turned on if we
196 * were trying to set some addresses and dongle rejected it...
197 */
198
199 buflen = sizeof("allmulti") + sizeof(allmulti);
200 buf = kmalloc(buflen, GFP_ATOMIC);
201 if (!buf)
202 return;
203
204 allmulti_le = cpu_to_le32(allmulti);
205
206 if (!brcmu_mkiovar
207 ("allmulti", (void *)&allmulti_le,
208 sizeof(allmulti_le), buf, buflen)) {
209 brcmf_dbg(ERROR, "%s: mkiovar failed for allmulti, datalen %d buflen %u\n",
210 brcmf_ifname(&drvr_priv->pub, 0),
211 (int)sizeof(allmulti), buflen);
212 kfree(buf);
213 return;
214 }
215
216 memset(&dcmd, 0, sizeof(dcmd));
217 dcmd.cmd = BRCMF_C_SET_VAR;
218 dcmd.buf = buf;
219 dcmd.len = buflen;
220 dcmd.set = true;
221
222 ret = brcmf_proto_dcmd(&drvr_priv->pub, 0, &dcmd, dcmd.len);
223 if (ret < 0) {
224 brcmf_dbg(ERROR, "%s: set allmulti %d failed\n",
225 brcmf_ifname(&drvr_priv->pub, 0),
226 le32_to_cpu(allmulti_le));
227 }
228
229 kfree(buf);
230
231 /* Finally, pick up the PROMISC flag as well, like the NIC
232 driver does */
233
234 allmulti = (ndev->flags & IFF_PROMISC) ? true : false;
235 allmulti_le = cpu_to_le32(allmulti);
236
237 memset(&dcmd, 0, sizeof(dcmd));
238 dcmd.cmd = BRCMF_C_SET_PROMISC;
239 dcmd.buf = &allmulti_le;
240 dcmd.len = sizeof(allmulti_le);
241 dcmd.set = true;
242
243 ret = brcmf_proto_dcmd(&drvr_priv->pub, 0, &dcmd, dcmd.len);
244 if (ret < 0) {
245 brcmf_dbg(ERROR, "%s: set promisc %d failed\n",
246 brcmf_ifname(&drvr_priv->pub, 0),
247 le32_to_cpu(allmulti_le));
248 }
249}
250
251static void
252_brcmf_set_mac_address(struct work_struct *work)
253{
254 char buf[32];
255 struct brcmf_dcmd dcmd;
256 int ret;
257
258 struct brcmf_info *drvr_priv = container_of(work, struct brcmf_info,
259 setmacaddr_work);
260
261 brcmf_dbg(TRACE, "enter\n");
262 if (!brcmu_mkiovar("cur_etheraddr", (char *)drvr_priv->macvalue,
263 ETH_ALEN, buf, 32)) {
264 brcmf_dbg(ERROR, "%s: mkiovar failed for cur_etheraddr\n",
265 brcmf_ifname(&drvr_priv->pub, 0));
266 return;
267 }
268 memset(&dcmd, 0, sizeof(dcmd));
269 dcmd.cmd = BRCMF_C_SET_VAR;
270 dcmd.buf = buf;
271 dcmd.len = 32;
272 dcmd.set = true;
273
274 ret = brcmf_proto_dcmd(&drvr_priv->pub, 0, &dcmd, dcmd.len);
275 if (ret < 0)
276 brcmf_dbg(ERROR, "%s: set cur_etheraddr failed\n",
277 brcmf_ifname(&drvr_priv->pub, 0));
278 else
279 memcpy(drvr_priv->iflist[0]->ndev->dev_addr,
280 drvr_priv->macvalue, ETH_ALEN);
281
282 return;
283}
284
285static int brcmf_netdev_set_mac_address(struct net_device *ndev, void *addr)
286{
287 struct brcmf_info *drvr_priv = *(struct brcmf_info **)
288 netdev_priv(ndev);
289 struct sockaddr *sa = (struct sockaddr *)addr;
290 int ifidx;
291
292 ifidx = brcmf_net2idx(drvr_priv, ndev);
293 if (ifidx == BRCMF_BAD_IF)
294 return -1;
295
296 memcpy(&drvr_priv->macvalue, sa->sa_data, ETH_ALEN);
297 schedule_work(&drvr_priv->setmacaddr_work);
298 return 0;
299}
300
301static void brcmf_netdev_set_multicast_list(struct net_device *ndev)
302{
303 struct brcmf_info *drvr_priv = *(struct brcmf_info **)
304 netdev_priv(ndev);
305 int ifidx;
306
307 ifidx = brcmf_net2idx(drvr_priv, ndev);
308 if (ifidx == BRCMF_BAD_IF)
309 return;
310
311 schedule_work(&drvr_priv->multicast_work);
312}
313
314int brcmf_sendpkt(struct brcmf_pub *drvr, int ifidx, struct sk_buff *pktbuf)
315{
316 struct brcmf_info *drvr_priv = drvr->info;
317
318 /* Reject if down */
319 if (!drvr->up || (drvr->busstate == BRCMF_BUS_DOWN))
320 return -ENODEV;
321
322 /* Update multicast statistic */
323 if (pktbuf->len >= ETH_ALEN) {
324 u8 *pktdata = (u8 *) (pktbuf->data);
325 struct ethhdr *eh = (struct ethhdr *)pktdata;
326
327 if (is_multicast_ether_addr(eh->h_dest))
328 drvr->tx_multicast++;
329 if (ntohs(eh->h_proto) == ETH_P_PAE)
330 atomic_inc(&drvr_priv->pend_8021x_cnt);
331 }
332
333 /* If the protocol uses a data header, apply it */
334 brcmf_proto_hdrpush(drvr, ifidx, pktbuf);
335
336 /* Use bus module to send data frame */
337 return brcmf_sdbrcm_bus_txdata(drvr->bus, pktbuf);
338}
339
340static int brcmf_netdev_start_xmit(struct sk_buff *skb, struct net_device *ndev)
341{
342 int ret;
343 struct brcmf_info *drvr_priv = *(struct brcmf_info **)
344 netdev_priv(ndev);
345 int ifidx;
346
347 brcmf_dbg(TRACE, "Enter\n");
348
349 /* Reject if down */
350 if (!drvr_priv->pub.up || (drvr_priv->pub.busstate == BRCMF_BUS_DOWN)) {
351 brcmf_dbg(ERROR, "xmit rejected pub.up=%d busstate=%d\n",
352 drvr_priv->pub.up, drvr_priv->pub.busstate);
353 netif_stop_queue(ndev);
354 return -ENODEV;
355 }
356
357 ifidx = brcmf_net2idx(drvr_priv, ndev);
358 if (ifidx == BRCMF_BAD_IF) {
359 brcmf_dbg(ERROR, "bad ifidx %d\n", ifidx);
360 netif_stop_queue(ndev);
361 return -ENODEV;
362 }
363
364 /* Make sure there's enough room for any header */
365 if (skb_headroom(skb) < drvr_priv->pub.hdrlen) {
366 struct sk_buff *skb2;
367
368 brcmf_dbg(INFO, "%s: insufficient headroom\n",
369 brcmf_ifname(&drvr_priv->pub, ifidx));
370 drvr_priv->pub.tx_realloc++;
371 skb2 = skb_realloc_headroom(skb, drvr_priv->pub.hdrlen);
372 dev_kfree_skb(skb);
373 skb = skb2;
374 if (skb == NULL) {
375 brcmf_dbg(ERROR, "%s: skb_realloc_headroom failed\n",
376 brcmf_ifname(&drvr_priv->pub, ifidx));
377 ret = -ENOMEM;
378 goto done;
379 }
380 }
381
382 ret = brcmf_sendpkt(&drvr_priv->pub, ifidx, skb);
383
384done:
385 if (ret)
386 drvr_priv->pub.dstats.tx_dropped++;
387 else
388 drvr_priv->pub.tx_packets++;
389
390 /* Return ok: we always eat the packet */
391 return 0;
392}
393
394void brcmf_txflowcontrol(struct brcmf_pub *drvr, int ifidx, bool state)
395{
396 struct net_device *ndev;
397 struct brcmf_info *drvr_priv = drvr->info;
398
399 brcmf_dbg(TRACE, "Enter\n");
400
401 drvr->txoff = state;
402 ndev = drvr_priv->iflist[ifidx]->ndev;
403 if (state == ON)
404 netif_stop_queue(ndev);
405 else
406 netif_wake_queue(ndev);
407}
408
409static int brcmf_host_event(struct brcmf_info *drvr_priv, int *ifidx,
410 void *pktdata, struct brcmf_event_msg *event,
411 void **data)
412{
413 int bcmerror = 0;
414
415 bcmerror = brcmf_c_host_event(drvr_priv, ifidx, pktdata, event, data);
416 if (bcmerror != 0)
417 return bcmerror;
418
419 if (drvr_priv->iflist[*ifidx]->ndev)
420 brcmf_cfg80211_event(drvr_priv->iflist[*ifidx]->ndev,
421 event, *data);
422
423 return bcmerror;
424}
425
426void brcmf_rx_frame(struct brcmf_pub *drvr, int ifidx, struct sk_buff *skb,
427 int numpkt)
428{
429 struct brcmf_info *drvr_priv = drvr->info;
430 unsigned char *eth;
431 uint len;
432 void *data;
433 struct sk_buff *pnext, *save_pktbuf;
434 int i;
435 struct brcmf_if *ifp;
436 struct brcmf_event_msg event;
437
438 brcmf_dbg(TRACE, "Enter\n");
439
440 save_pktbuf = skb;
441
442 for (i = 0; skb && i < numpkt; i++, skb = pnext) {
443
444 pnext = skb->next;
445 skb->next = NULL;
446
447 /* Get the protocol, maintain skb around eth_type_trans()
448 * The main reason for this hack is for the limitation of
449 * Linux 2.4 where 'eth_type_trans' uses the
450 * 'net->hard_header_len'
451 * to perform skb_pull inside vs ETH_HLEN. Since to avoid
452 * coping of the packet coming from the network stack to add
453 * BDC, Hardware header etc, during network interface
454 * registration
455 * we set the 'net->hard_header_len' to ETH_HLEN + extra space
456 * required
457 * for BDC, Hardware header etc. and not just the ETH_HLEN
458 */
459 eth = skb->data;
460 len = skb->len;
461
462 ifp = drvr_priv->iflist[ifidx];
463 if (ifp == NULL)
464 ifp = drvr_priv->iflist[0];
465
466 skb->dev = ifp->ndev;
467 skb->protocol = eth_type_trans(skb, skb->dev);
468
469 if (skb->pkt_type == PACKET_MULTICAST)
470 drvr_priv->pub.rx_multicast++;
471
472 skb->data = eth;
473 skb->len = len;
474
475 /* Strip header, count, deliver upward */
476 skb_pull(skb, ETH_HLEN);
477
478 /* Process special event packets and then discard them */
479 if (ntohs(skb->protocol) == ETH_P_LINK_CTL)
480 brcmf_host_event(drvr_priv, &ifidx,
481 skb_mac_header(skb),
482 &event, &data);
483
484 if (drvr_priv->iflist[ifidx] &&
485 !drvr_priv->iflist[ifidx]->state)
486 ifp = drvr_priv->iflist[ifidx];
487
488 if (ifp->ndev)
489 ifp->ndev->last_rx = jiffies;
490
491 drvr->dstats.rx_bytes += skb->len;
492 drvr->rx_packets++; /* Local count */
493
494 if (in_interrupt())
495 netif_rx(skb);
496 else
497 /* If the receive is not processed inside an ISR,
498 * the softirqd must be woken explicitly to service
499 * the NET_RX_SOFTIRQ. In 2.6 kernels, this is handled
500 * by netif_rx_ni(), but in earlier kernels, we need
501 * to do it manually.
502 */
503 netif_rx_ni(skb);
504 }
505}
506
507void brcmf_txcomplete(struct brcmf_pub *drvr, struct sk_buff *txp, bool success)
508{
509 uint ifidx;
510 struct brcmf_info *drvr_priv = drvr->info;
511 struct ethhdr *eh;
512 u16 type;
513
514 brcmf_proto_hdrpull(drvr, &ifidx, txp);
515
516 eh = (struct ethhdr *)(txp->data);
517 type = ntohs(eh->h_proto);
518
519 if (type == ETH_P_PAE)
520 atomic_dec(&drvr_priv->pend_8021x_cnt);
521
522}
523
524static struct net_device_stats *brcmf_netdev_get_stats(struct net_device *ndev)
525{
526 struct brcmf_info *drvr_priv = *(struct brcmf_info **)
527 netdev_priv(ndev);
528 struct brcmf_if *ifp;
529 int ifidx;
530
531 brcmf_dbg(TRACE, "Enter\n");
532
533 ifidx = brcmf_net2idx(drvr_priv, ndev);
534 if (ifidx == BRCMF_BAD_IF)
535 return NULL;
536
537 ifp = drvr_priv->iflist[ifidx];
538
539 if (drvr_priv->pub.up)
540 /* Use the protocol to get dongle stats */
541 brcmf_proto_dstats(&drvr_priv->pub);
542
543 /* Copy dongle stats to net device stats */
544 ifp->stats.rx_packets = drvr_priv->pub.dstats.rx_packets;
545 ifp->stats.tx_packets = drvr_priv->pub.dstats.tx_packets;
546 ifp->stats.rx_bytes = drvr_priv->pub.dstats.rx_bytes;
547 ifp->stats.tx_bytes = drvr_priv->pub.dstats.tx_bytes;
548 ifp->stats.rx_errors = drvr_priv->pub.dstats.rx_errors;
549 ifp->stats.tx_errors = drvr_priv->pub.dstats.tx_errors;
550 ifp->stats.rx_dropped = drvr_priv->pub.dstats.rx_dropped;
551 ifp->stats.tx_dropped = drvr_priv->pub.dstats.tx_dropped;
552 ifp->stats.multicast = drvr_priv->pub.dstats.multicast;
553
554 return &ifp->stats;
555}
556
557/* Retrieve current toe component enables, which are kept
558 as a bitmap in toe_ol iovar */
559static int brcmf_toe_get(struct brcmf_info *drvr_priv, int ifidx, u32 *toe_ol)
560{
561 struct brcmf_dcmd dcmd;
562 char buf[32];
563 int ret;
564
565 memset(&dcmd, 0, sizeof(dcmd));
566
567 dcmd.cmd = BRCMF_C_GET_VAR;
568 dcmd.buf = buf;
569 dcmd.len = (uint) sizeof(buf);
570 dcmd.set = false;
571
572 strcpy(buf, "toe_ol");
573 ret = brcmf_proto_dcmd(&drvr_priv->pub, ifidx, &dcmd, dcmd.len);
574 if (ret < 0) {
575 /* Check for older dongle image that doesn't support toe_ol */
576 if (ret == -EIO) {
577 brcmf_dbg(ERROR, "%s: toe not supported by device\n",
578 brcmf_ifname(&drvr_priv->pub, ifidx));
579 return -EOPNOTSUPP;
580 }
581
582 brcmf_dbg(INFO, "%s: could not get toe_ol: ret=%d\n",
583 brcmf_ifname(&drvr_priv->pub, ifidx), ret);
584 return ret;
585 }
586
587 memcpy(toe_ol, buf, sizeof(u32));
588 return 0;
589}
590
591/* Set current toe component enables in toe_ol iovar,
592 and set toe global enable iovar */
593static int brcmf_toe_set(struct brcmf_info *drvr_priv, int ifidx, u32 toe_ol)
594{
595 struct brcmf_dcmd dcmd;
596 char buf[32];
597 int toe, ret;
598
599 memset(&dcmd, 0, sizeof(dcmd));
600
601 dcmd.cmd = BRCMF_C_SET_VAR;
602 dcmd.buf = buf;
603 dcmd.len = (uint) sizeof(buf);
604 dcmd.set = true;
605
606 /* Set toe_ol as requested */
607
608 strcpy(buf, "toe_ol");
609 memcpy(&buf[sizeof("toe_ol")], &toe_ol, sizeof(u32));
610
611 ret = brcmf_proto_dcmd(&drvr_priv->pub, ifidx, &dcmd, dcmd.len);
612 if (ret < 0) {
613 brcmf_dbg(ERROR, "%s: could not set toe_ol: ret=%d\n",
614 brcmf_ifname(&drvr_priv->pub, ifidx), ret);
615 return ret;
616 }
617
618 /* Enable toe globally only if any components are enabled. */
619
620 toe = (toe_ol != 0);
621
622 strcpy(buf, "toe");
623 memcpy(&buf[sizeof("toe")], &toe, sizeof(u32));
624
625 ret = brcmf_proto_dcmd(&drvr_priv->pub, ifidx, &dcmd, dcmd.len);
626 if (ret < 0) {
627 brcmf_dbg(ERROR, "%s: could not set toe: ret=%d\n",
628 brcmf_ifname(&drvr_priv->pub, ifidx), ret);
629 return ret;
630 }
631
632 return 0;
633}
634
635static void brcmf_ethtool_get_drvinfo(struct net_device *ndev,
636 struct ethtool_drvinfo *info)
637{
638 struct brcmf_info *drvr_priv = *(struct brcmf_info **)
639 netdev_priv(ndev);
640
641 sprintf(info->driver, KBUILD_MODNAME);
642 sprintf(info->version, "%lu", drvr_priv->pub.drv_version);
643 sprintf(info->fw_version, "%s", BCM4329_FW_NAME);
644 sprintf(info->bus_info, "%s",
645 dev_name(brcmf_bus_get_device(drvr_priv->pub.bus)));
646}
647
648static struct ethtool_ops brcmf_ethtool_ops = {
649 .get_drvinfo = brcmf_ethtool_get_drvinfo
650};
651
652static int brcmf_ethtool(struct brcmf_info *drvr_priv, void __user *uaddr)
653{
654 struct ethtool_drvinfo info;
655 char drvname[sizeof(info.driver)];
656 u32 cmd;
657 struct ethtool_value edata;
658 u32 toe_cmpnt, csum_dir;
659 int ret;
660
661 brcmf_dbg(TRACE, "Enter\n");
662
663 /* all ethtool calls start with a cmd word */
664 if (copy_from_user(&cmd, uaddr, sizeof(u32)))
665 return -EFAULT;
666
667 switch (cmd) {
668 case ETHTOOL_GDRVINFO:
669 /* Copy out any request driver name */
670 if (copy_from_user(&info, uaddr, sizeof(info)))
671 return -EFAULT;
672 strncpy(drvname, info.driver, sizeof(info.driver));
673 drvname[sizeof(info.driver) - 1] = '\0';
674
675 /* clear struct for return */
676 memset(&info, 0, sizeof(info));
677 info.cmd = cmd;
678
679 /* if requested, identify ourselves */
680 if (strcmp(drvname, "?dhd") == 0) {
681 sprintf(info.driver, "dhd");
682 strcpy(info.version, BRCMF_VERSION_STR);
683 }
684
685 /* otherwise, require dongle to be up */
686 else if (!drvr_priv->pub.up) {
687 brcmf_dbg(ERROR, "dongle is not up\n");
688 return -ENODEV;
689 }
690
691 /* finally, report dongle driver type */
692 else if (drvr_priv->pub.iswl)
693 sprintf(info.driver, "wl");
694 else
695 sprintf(info.driver, "xx");
696
697 sprintf(info.version, "%lu", drvr_priv->pub.drv_version);
698 if (copy_to_user(uaddr, &info, sizeof(info)))
699 return -EFAULT;
700 brcmf_dbg(CTL, "given %*s, returning %s\n",
701 (int)sizeof(drvname), drvname, info.driver);
702 break;
703
704 /* Get toe offload components from dongle */
705 case ETHTOOL_GRXCSUM:
706 case ETHTOOL_GTXCSUM:
707 ret = brcmf_toe_get(drvr_priv, 0, &toe_cmpnt);
708 if (ret < 0)
709 return ret;
710
711 csum_dir =
712 (cmd == ETHTOOL_GTXCSUM) ? TOE_TX_CSUM_OL : TOE_RX_CSUM_OL;
713
714 edata.cmd = cmd;
715 edata.data = (toe_cmpnt & csum_dir) ? 1 : 0;
716
717 if (copy_to_user(uaddr, &edata, sizeof(edata)))
718 return -EFAULT;
719 break;
720
721 /* Set toe offload components in dongle */
722 case ETHTOOL_SRXCSUM:
723 case ETHTOOL_STXCSUM:
724 if (copy_from_user(&edata, uaddr, sizeof(edata)))
725 return -EFAULT;
726
727 /* Read the current settings, update and write back */
728 ret = brcmf_toe_get(drvr_priv, 0, &toe_cmpnt);
729 if (ret < 0)
730 return ret;
731
732 csum_dir =
733 (cmd == ETHTOOL_STXCSUM) ? TOE_TX_CSUM_OL : TOE_RX_CSUM_OL;
734
735 if (edata.data != 0)
736 toe_cmpnt |= csum_dir;
737 else
738 toe_cmpnt &= ~csum_dir;
739
740 ret = brcmf_toe_set(drvr_priv, 0, toe_cmpnt);
741 if (ret < 0)
742 return ret;
743
744 /* If setting TX checksum mode, tell Linux the new mode */
745 if (cmd == ETHTOOL_STXCSUM) {
746 if (edata.data)
747 drvr_priv->iflist[0]->ndev->features |=
748 NETIF_F_IP_CSUM;
749 else
750 drvr_priv->iflist[0]->ndev->features &=
751 ~NETIF_F_IP_CSUM;
752 }
753
754 break;
755
756 default:
757 return -EOPNOTSUPP;
758 }
759
760 return 0;
761}
762
763static int brcmf_netdev_ioctl_entry(struct net_device *ndev, struct ifreq *ifr,
764 int cmd)
765{
766 struct brcmf_info *drvr_priv = *(struct brcmf_info **)
767 netdev_priv(ndev);
768 int ifidx;
769
770 ifidx = brcmf_net2idx(drvr_priv, ndev);
771 brcmf_dbg(TRACE, "ifidx %d, cmd 0x%04x\n", ifidx, cmd);
772
773 if (ifidx == BRCMF_BAD_IF)
774 return -1;
775
776 if (cmd == SIOCETHTOOL)
777 return brcmf_ethtool(drvr_priv, ifr->ifr_data);
778
779 return -EOPNOTSUPP;
780}
781
782/* called only from within this driver. Sends a command to the dongle. */
783s32 brcmf_exec_dcmd(struct net_device *ndev, u32 cmd, void *arg, u32 len)
784{
785 struct brcmf_dcmd dcmd;
786 s32 err = 0;
787 int buflen = 0;
788 bool is_set_key_cmd;
789 struct brcmf_info *drvr_priv = *(struct brcmf_info **)
790 netdev_priv(ndev);
791 int ifidx;
792
793 memset(&dcmd, 0, sizeof(dcmd));
794 dcmd.cmd = cmd;
795 dcmd.buf = arg;
796 dcmd.len = len;
797
798 ifidx = brcmf_net2idx(drvr_priv, ndev);
799
800 if (dcmd.buf != NULL)
801 buflen = min_t(uint, dcmd.len, BRCMF_DCMD_MAXLEN);
802
803 /* send to dongle (must be up, and wl) */
804 if ((drvr_priv->pub.busstate != BRCMF_BUS_DATA)) {
805 brcmf_dbg(ERROR, "DONGLE_DOWN\n");
806 err = -EIO;
807 goto done;
808 }
809
810 if (!drvr_priv->pub.iswl) {
811 err = -EIO;
812 goto done;
813 }
814
815 /*
816 * Intercept BRCMF_C_SET_KEY CMD - serialize M4 send and
817 * set key CMD to prevent M4 encryption.
818 */
819 is_set_key_cmd = ((dcmd.cmd == BRCMF_C_SET_KEY) ||
820 ((dcmd.cmd == BRCMF_C_SET_VAR) &&
821 !(strncmp("wsec_key", dcmd.buf, 9))) ||
822 ((dcmd.cmd == BRCMF_C_SET_VAR) &&
823 !(strncmp("bsscfg:wsec_key", dcmd.buf, 15))));
824 if (is_set_key_cmd)
825 brcmf_netdev_wait_pend8021x(ndev);
826
827 err = brcmf_proto_dcmd(&drvr_priv->pub, ifidx, &dcmd, buflen);
828
829done:
830 if (err > 0)
831 err = 0;
832
833 return err;
834}
835
836static int brcmf_netdev_stop(struct net_device *ndev)
837{
838 struct brcmf_pub *drvr = *(struct brcmf_pub **) netdev_priv(ndev);
839
840 brcmf_dbg(TRACE, "Enter\n");
841 brcmf_cfg80211_down(drvr->config);
842 if (drvr->up == 0)
843 return 0;
844
845 /* Set state and stop OS transmissions */
846 drvr->up = 0;
847 netif_stop_queue(ndev);
848
849 return 0;
850}
851
852static int brcmf_netdev_open(struct net_device *ndev)
853{
854 struct brcmf_info *drvr_priv = *(struct brcmf_info **)
855 netdev_priv(ndev);
856 u32 toe_ol;
857 int ifidx = brcmf_net2idx(drvr_priv, ndev);
858 s32 ret = 0;
859
860 brcmf_dbg(TRACE, "ifidx %d\n", ifidx);
861
862 if (ifidx == 0) { /* do it only for primary eth0 */
863
864 /* try to bring up bus */
865 ret = brcmf_bus_start(&drvr_priv->pub);
866 if (ret != 0) {
867 brcmf_dbg(ERROR, "failed with code %d\n", ret);
868 return -1;
869 }
870 atomic_set(&drvr_priv->pend_8021x_cnt, 0);
871
872 memcpy(ndev->dev_addr, drvr_priv->pub.mac, ETH_ALEN);
873
874 /* Get current TOE mode from dongle */
875 if (brcmf_toe_get(drvr_priv, ifidx, &toe_ol) >= 0
876 && (toe_ol & TOE_TX_CSUM_OL) != 0)
877 drvr_priv->iflist[ifidx]->ndev->features |=
878 NETIF_F_IP_CSUM;
879 else
880 drvr_priv->iflist[ifidx]->ndev->features &=
881 ~NETIF_F_IP_CSUM;
882 }
883 /* Allow transmit calls */
884 netif_start_queue(ndev);
885 drvr_priv->pub.up = 1;
886 if (brcmf_cfg80211_up(drvr_priv->pub.config)) {
887 brcmf_dbg(ERROR, "failed to bring up cfg80211\n");
888 return -1;
889 }
890
891 return ret;
892}
893
894int
895brcmf_add_if(struct brcmf_info *drvr_priv, int ifidx, struct net_device *ndev,
896 char *name, u8 *mac_addr, u32 flags, u8 bssidx)
897{
898 struct brcmf_if *ifp;
899 int ret = 0, err = 0;
900
901 brcmf_dbg(TRACE, "idx %d, handle->%p\n", ifidx, ndev);
902
903 ifp = drvr_priv->iflist[ifidx];
904 if (!ifp) {
905 ifp = kmalloc(sizeof(struct brcmf_if), GFP_ATOMIC);
906 if (!ifp)
907 return -ENOMEM;
908 }
909
910 memset(ifp, 0, sizeof(struct brcmf_if));
911 ifp->info = drvr_priv;
912 drvr_priv->iflist[ifidx] = ifp;
913 if (mac_addr != NULL)
914 memcpy(&ifp->mac_addr, mac_addr, ETH_ALEN);
915
916 if (ndev == NULL) {
917 ifp->state = BRCMF_E_IF_ADD;
918 ifp->idx = ifidx;
919 /*
920 * Delete the existing interface before overwriting it
921 * in case we missed the BRCMF_E_IF_DEL event.
922 */
923 if (ifp->ndev != NULL) {
924 brcmf_dbg(ERROR, "ERROR: netdev:%s already exists, try free & unregister\n",
925 ifp->ndev->name);
926 netif_stop_queue(ifp->ndev);
927 unregister_netdev(ifp->ndev);
928 free_netdev(ifp->ndev);
929 }
930
931 /* Allocate netdev, including space for private structure */
932 ifp->ndev = alloc_netdev(sizeof(drvr_priv), "wlan%d",
933 ether_setup);
934 if (!ifp->ndev) {
935 brcmf_dbg(ERROR, "OOM - alloc_netdev\n");
936 ret = -ENOMEM;
937 }
938
939 if (ret == 0) {
940 memcpy(netdev_priv(ifp->ndev), &drvr_priv,
941 sizeof(drvr_priv));
942 err = brcmf_net_attach(&drvr_priv->pub, ifp->idx);
943 if (err != 0) {
944 brcmf_dbg(ERROR, "brcmf_net_attach failed, err %d\n",
945 err);
946 ret = -EOPNOTSUPP;
947 } else {
948 brcmf_dbg(TRACE, " ==== pid:%x, net_device for if:%s created ===\n",
949 current->pid, ifp->ndev->name);
950 ifp->state = 0;
951 }
952 }
953
954 if (ret < 0) {
955 if (ifp->ndev)
956 free_netdev(ifp->ndev);
957
958 drvr_priv->iflist[ifp->idx] = NULL;
959 kfree(ifp);
960 }
961 } else
962 ifp->ndev = ndev;
963
964 return 0;
965}
966
967void brcmf_del_if(struct brcmf_info *drvr_priv, int ifidx)
968{
969 struct brcmf_if *ifp;
970
971 brcmf_dbg(TRACE, "idx %d\n", ifidx);
972
973 ifp = drvr_priv->iflist[ifidx];
974 if (!ifp) {
975 brcmf_dbg(ERROR, "Null interface\n");
976 return;
977 }
978
979 ifp->state = BRCMF_E_IF_DEL;
980 ifp->idx = ifidx;
981 if (ifp->ndev != NULL) {
982 netif_stop_queue(ifp->ndev);
983 unregister_netdev(ifp->ndev);
984 free_netdev(ifp->ndev);
985 drvr_priv->iflist[ifidx] = NULL;
986 kfree(ifp);
987 }
988}
989
990struct brcmf_pub *brcmf_attach(struct brcmf_bus *bus, uint bus_hdrlen)
991{
992 struct brcmf_info *drvr_priv = NULL;
993 struct net_device *ndev;
994
995 brcmf_dbg(TRACE, "Enter\n");
996
997 /* Allocate netdev, including space for private structure */
998 ndev = alloc_netdev(sizeof(drvr_priv), "wlan%d", ether_setup);
999 if (!ndev) {
1000 brcmf_dbg(ERROR, "OOM - alloc_netdev\n");
1001 goto fail;
1002 }
1003
1004 /* Allocate primary brcmf_info */
1005 drvr_priv = kzalloc(sizeof(struct brcmf_info), GFP_ATOMIC);
1006 if (!drvr_priv)
1007 goto fail;
1008
1009 /*
1010 * Save the brcmf_info into the priv
1011 */
1012 memcpy(netdev_priv(ndev), &drvr_priv, sizeof(drvr_priv));
1013
1014 if (brcmf_add_if(drvr_priv, 0, ndev, ndev->name, NULL, 0, 0) ==
1015 BRCMF_BAD_IF)
1016 goto fail;
1017
1018 ndev->netdev_ops = NULL;
1019 mutex_init(&drvr_priv->proto_block);
1020
1021 /* Link to info module */
1022 drvr_priv->pub.info = drvr_priv;
1023
1024 /* Link to bus module */
1025 drvr_priv->pub.bus = bus;
1026 drvr_priv->pub.hdrlen = bus_hdrlen;
1027
1028 /* Attach and link in the protocol */
1029 if (brcmf_proto_attach(&drvr_priv->pub) != 0) {
1030 brcmf_dbg(ERROR, "brcmf_prot_attach failed\n");
1031 goto fail;
1032 }
1033
1034 /* Attach and link in the cfg80211 */
1035 drvr_priv->pub.config =
1036 brcmf_cfg80211_attach(ndev,
1037 brcmf_bus_get_device(bus),
1038 &drvr_priv->pub);
1039 if (drvr_priv->pub.config == NULL) {
1040 brcmf_dbg(ERROR, "wl_cfg80211_attach failed\n");
1041 goto fail;
1042 }
1043
1044 INIT_WORK(&drvr_priv->setmacaddr_work, _brcmf_set_mac_address);
1045 INIT_WORK(&drvr_priv->multicast_work, _brcmf_set_multicast_list);
1046
1047 /*
1048 * Save the brcmf_info into the priv
1049 */
1050 memcpy(netdev_priv(ndev), &drvr_priv, sizeof(drvr_priv));
1051
1052 return &drvr_priv->pub;
1053
1054fail:
1055 if (ndev)
1056 free_netdev(ndev);
1057 if (drvr_priv)
1058 brcmf_detach(&drvr_priv->pub);
1059
1060 return NULL;
1061}
1062
1063int brcmf_bus_start(struct brcmf_pub *drvr)
1064{
1065 int ret = -1;
1066 struct brcmf_info *drvr_priv = drvr->info;
1067 /* Room for "event_msgs" + '\0' + bitvec */
1068 char iovbuf[BRCMF_EVENTING_MASK_LEN + 12];
1069
1070 brcmf_dbg(TRACE, "\n");
1071
1072 /* Bring up the bus */
1073 ret = brcmf_sdbrcm_bus_init(&drvr_priv->pub);
1074 if (ret != 0) {
1075 brcmf_dbg(ERROR, "brcmf_sdbrcm_bus_init failed %d\n", ret);
1076 return ret;
1077 }
1078
1079 /* If bus is not ready, can't come up */
1080 if (drvr_priv->pub.busstate != BRCMF_BUS_DATA) {
1081 brcmf_dbg(ERROR, "failed bus is not ready\n");
1082 return -ENODEV;
1083 }
1084
1085 brcmu_mkiovar("event_msgs", drvr->eventmask, BRCMF_EVENTING_MASK_LEN,
1086 iovbuf, sizeof(iovbuf));
1087 brcmf_proto_cdc_query_dcmd(drvr, 0, BRCMF_C_GET_VAR, iovbuf,
1088 sizeof(iovbuf));
1089 memcpy(drvr->eventmask, iovbuf, BRCMF_EVENTING_MASK_LEN);
1090
1091 setbit(drvr->eventmask, BRCMF_E_SET_SSID);
1092 setbit(drvr->eventmask, BRCMF_E_PRUNE);
1093 setbit(drvr->eventmask, BRCMF_E_AUTH);
1094 setbit(drvr->eventmask, BRCMF_E_REASSOC);
1095 setbit(drvr->eventmask, BRCMF_E_REASSOC_IND);
1096 setbit(drvr->eventmask, BRCMF_E_DEAUTH_IND);
1097 setbit(drvr->eventmask, BRCMF_E_DISASSOC_IND);
1098 setbit(drvr->eventmask, BRCMF_E_DISASSOC);
1099 setbit(drvr->eventmask, BRCMF_E_JOIN);
1100 setbit(drvr->eventmask, BRCMF_E_ASSOC_IND);
1101 setbit(drvr->eventmask, BRCMF_E_PSK_SUP);
1102 setbit(drvr->eventmask, BRCMF_E_LINK);
1103 setbit(drvr->eventmask, BRCMF_E_NDIS_LINK);
1104 setbit(drvr->eventmask, BRCMF_E_MIC_ERROR);
1105 setbit(drvr->eventmask, BRCMF_E_PMKID_CACHE);
1106 setbit(drvr->eventmask, BRCMF_E_TXFAIL);
1107 setbit(drvr->eventmask, BRCMF_E_JOIN_START);
1108 setbit(drvr->eventmask, BRCMF_E_SCAN_COMPLETE);
1109
1110/* enable dongle roaming event */
1111
1112 drvr->pktfilter_count = 1;
1113 /* Setup filter to allow only unicast */
1114 drvr->pktfilter[0] = "100 0 0 0 0x01 0x00";
1115
1116 /* Bus is ready, do any protocol initialization */
1117 ret = brcmf_proto_init(&drvr_priv->pub);
1118 if (ret < 0)
1119 return ret;
1120
1121 return 0;
1122}
1123
1124static struct net_device_ops brcmf_netdev_ops_pri = {
1125 .ndo_open = brcmf_netdev_open,
1126 .ndo_stop = brcmf_netdev_stop,
1127 .ndo_get_stats = brcmf_netdev_get_stats,
1128 .ndo_do_ioctl = brcmf_netdev_ioctl_entry,
1129 .ndo_start_xmit = brcmf_netdev_start_xmit,
1130 .ndo_set_mac_address = brcmf_netdev_set_mac_address,
1131 .ndo_set_multicast_list = brcmf_netdev_set_multicast_list
1132};
1133
1134int brcmf_net_attach(struct brcmf_pub *drvr, int ifidx)
1135{
1136 struct brcmf_info *drvr_priv = drvr->info;
1137 struct net_device *ndev;
1138 u8 temp_addr[ETH_ALEN] = {
1139 0x00, 0x90, 0x4c, 0x11, 0x22, 0x33};
1140
1141 brcmf_dbg(TRACE, "ifidx %d\n", ifidx);
1142
1143 ndev = drvr_priv->iflist[ifidx]->ndev;
1144 ndev->netdev_ops = &brcmf_netdev_ops_pri;
1145
1146 /*
1147 * We have to use the primary MAC for virtual interfaces
1148 */
1149 if (ifidx != 0) {
1150 /* for virtual interfaces use the primary MAC */
1151 memcpy(temp_addr, drvr_priv->pub.mac, ETH_ALEN);
1152
1153 }
1154
1155 if (ifidx == 1) {
1156 brcmf_dbg(TRACE, "ACCESS POINT MAC:\n");
1157 /* ACCESSPOINT INTERFACE CASE */
1158 temp_addr[0] |= 0X02; /* set bit 2 ,
1159 - Locally Administered address */
1160
1161 }
1162 ndev->hard_header_len = ETH_HLEN + drvr_priv->pub.hdrlen;
1163 ndev->ethtool_ops = &brcmf_ethtool_ops;
1164
1165 drvr_priv->pub.rxsz = ndev->mtu + ndev->hard_header_len +
1166 drvr_priv->pub.hdrlen;
1167
1168 memcpy(ndev->dev_addr, temp_addr, ETH_ALEN);
1169
1170 if (register_netdev(ndev) != 0) {
1171 brcmf_dbg(ERROR, "couldn't register the net device\n");
1172 goto fail;
1173 }
1174
1175 brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
1176
1177 return 0;
1178
1179fail:
1180 ndev->netdev_ops = NULL;
1181 return -EBADE;
1182}
1183
1184static void brcmf_bus_detach(struct brcmf_pub *drvr)
1185{
1186 struct brcmf_info *drvr_priv;
1187
1188 brcmf_dbg(TRACE, "Enter\n");
1189
1190 if (drvr) {
1191 drvr_priv = drvr->info;
1192 if (drvr_priv) {
1193 /* Stop the protocol module */
1194 brcmf_proto_stop(&drvr_priv->pub);
1195
1196 /* Stop the bus module */
1197 brcmf_sdbrcm_bus_stop(drvr_priv->pub.bus);
1198 }
1199 }
1200}
1201
1202void brcmf_detach(struct brcmf_pub *drvr)
1203{
1204 struct brcmf_info *drvr_priv;
1205
1206 brcmf_dbg(TRACE, "Enter\n");
1207
1208 if (drvr) {
1209 drvr_priv = drvr->info;
1210 if (drvr_priv) {
1211 struct brcmf_if *ifp;
1212 int i;
1213
1214 for (i = 1; i < BRCMF_MAX_IFS; i++)
1215 if (drvr_priv->iflist[i])
1216 brcmf_del_if(drvr_priv, i);
1217
1218 ifp = drvr_priv->iflist[0];
1219 if (ifp->ndev->netdev_ops == &brcmf_netdev_ops_pri) {
1220 rtnl_lock();
1221 brcmf_netdev_stop(ifp->ndev);
1222 rtnl_unlock();
1223 unregister_netdev(ifp->ndev);
1224 }
1225
1226 cancel_work_sync(&drvr_priv->setmacaddr_work);
1227 cancel_work_sync(&drvr_priv->multicast_work);
1228
1229 brcmf_bus_detach(drvr);
1230
1231 if (drvr->prot)
1232 brcmf_proto_detach(drvr);
1233
1234 brcmf_cfg80211_detach(drvr->config);
1235
1236 free_netdev(ifp->ndev);
1237 kfree(ifp);
1238 kfree(drvr_priv);
1239 }
1240 }
1241}
1242
1243static void __exit brcmf_module_cleanup(void)
1244{
1245 brcmf_dbg(TRACE, "Enter\n");
1246
1247 brcmf_bus_unregister();
1248}
1249
1250static int __init brcmf_module_init(void)
1251{
1252 int error;
1253
1254 brcmf_dbg(TRACE, "Enter\n");
1255
1256 error = brcmf_bus_register();
1257
1258 if (error) {
1259 brcmf_dbg(ERROR, "brcmf_bus_register failed\n");
1260 goto failed;
1261 }
1262 return 0;
1263
1264failed:
1265 return -EINVAL;
1266}
1267
1268module_init(brcmf_module_init);
1269module_exit(brcmf_module_cleanup);
1270
1271int brcmf_os_proto_block(struct brcmf_pub *drvr)
1272{
1273 struct brcmf_info *drvr_priv = drvr->info;
1274
1275 if (drvr_priv) {
1276 mutex_lock(&drvr_priv->proto_block);
1277 return 1;
1278 }
1279 return 0;
1280}
1281
1282int brcmf_os_proto_unblock(struct brcmf_pub *drvr)
1283{
1284 struct brcmf_info *drvr_priv = drvr->info;
1285
1286 if (drvr_priv) {
1287 mutex_unlock(&drvr_priv->proto_block);
1288 return 1;
1289 }
1290
1291 return 0;
1292}
1293
1294static int brcmf_get_pend_8021x_cnt(struct brcmf_info *drvr_priv)
1295{
1296 return atomic_read(&drvr_priv->pend_8021x_cnt);
1297}
1298
1299#define MAX_WAIT_FOR_8021X_TX 10
1300
1301int brcmf_netdev_wait_pend8021x(struct net_device *ndev)
1302{
1303 struct brcmf_info *drvr_priv = *(struct brcmf_info **)netdev_priv(ndev);
1304 int timeout = 10 * HZ / 1000;
1305 int ntimes = MAX_WAIT_FOR_8021X_TX;
1306 int pend = brcmf_get_pend_8021x_cnt(drvr_priv);
1307
1308 while (ntimes && pend) {
1309 if (pend) {
1310 set_current_state(TASK_INTERRUPTIBLE);
1311 schedule_timeout(timeout);
1312 set_current_state(TASK_RUNNING);
1313 ntimes--;
1314 }
1315 pend = brcmf_get_pend_8021x_cnt(drvr_priv);
1316 }
1317 return pend;
1318}
1319
1320#ifdef BCMDBG
1321int brcmf_write_to_file(struct brcmf_pub *drvr, u8 *buf, int size)
1322{
1323 int ret = 0;
1324 struct file *fp;
1325 mm_segment_t old_fs;
1326 loff_t pos = 0;
1327
1328 /* change to KERNEL_DS address limit */
1329 old_fs = get_fs();
1330 set_fs(KERNEL_DS);
1331
1332 /* open file to write */
1333 fp = filp_open("/tmp/mem_dump", O_WRONLY | O_CREAT, 0640);
1334 if (!fp) {
1335 brcmf_dbg(ERROR, "open file error\n");
1336 ret = -1;
1337 goto exit;
1338 }
1339
1340 /* Write buf to file */
1341 fp->f_op->write(fp, buf, size, &pos);
1342
1343exit:
1344 /* free buf before return */
1345 kfree(buf);
1346 /* close file before return */
1347 if (fp)
1348 filp_close(fp, current->files);
1349 /* restore previous address limit */
1350 set_fs(old_fs);
1351
1352 return ret;
1353}
1354#endif /* BCMDBG */
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_proto.h b/drivers/staging/brcm80211/brcmfmac/dhd_proto.h
deleted file mode 100644
index 4ee1ea846f6..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/dhd_proto.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCMF_PROTO_H_
18#define _BRCMF_PROTO_H_
19
20/*
21 * Exported from the brcmf protocol module (brcmf_cdc)
22 */
23
24/* Linkage, sets prot link and updates hdrlen in pub */
25extern int brcmf_proto_attach(struct brcmf_pub *drvr);
26
27/* Unlink, frees allocated protocol memory (including brcmf_proto) */
28extern void brcmf_proto_detach(struct brcmf_pub *drvr);
29
30/* Initialize protocol: sync w/dongle state.
31 * Sets dongle media info (iswl, drv_version, mac address).
32 */
33extern int brcmf_proto_init(struct brcmf_pub *drvr);
34
35/* Stop protocol: sync w/dongle state. */
36extern void brcmf_proto_stop(struct brcmf_pub *drvr);
37
38/* Add any protocol-specific data header.
39 * Caller must reserve prot_hdrlen prepend space.
40 */
41extern void brcmf_proto_hdrpush(struct brcmf_pub *, int ifidx,
42 struct sk_buff *txp);
43
44/* Remove any protocol-specific data header. */
45extern int brcmf_proto_hdrpull(struct brcmf_pub *, int *ifidx,
46 struct sk_buff *rxp);
47
48/* Use protocol to issue command to dongle */
49extern int brcmf_proto_dcmd(struct brcmf_pub *drvr, int ifidx,
50 struct brcmf_dcmd *dcmd, int len);
51
52/* Update local copy of dongle statistics */
53extern void brcmf_proto_dstats(struct brcmf_pub *drvr);
54
55extern int brcmf_c_preinit_dcmds(struct brcmf_pub *drvr);
56
57extern int brcmf_proto_cdc_set_dcmd(struct brcmf_pub *drvr, int ifidx,
58 uint cmd, void *buf, uint len);
59
60#endif /* _BRCMF_PROTO_H_ */
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c b/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
deleted file mode 100644
index 6885755f4ec..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
+++ /dev/null
@@ -1,4581 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/kthread.h>
20#include <linux/printk.h>
21#include <linux/pci_ids.h>
22#include <linux/netdevice.h>
23#include <linux/interrupt.h>
24#include <linux/sched.h>
25#include <linux/mmc/sdio.h>
26#include <linux/mmc/sdio_func.h>
27#include <linux/mmc/card.h>
28#include <linux/semaphore.h>
29#include <linux/firmware.h>
30#include <asm/unaligned.h>
31#include <defs.h>
32#include <brcmu_wifi.h>
33#include <brcmu_utils.h>
34#include <brcm_hw_ids.h>
35#include <soc.h>
36#include "sdio_host.h"
37
38#define DCMD_RESP_TIMEOUT 2000 /* In milli second */
39
40#ifdef BCMDBG
41
42#define BRCMF_TRAP_INFO_SIZE 80
43
44#define CBUF_LEN (128)
45
46struct rte_log_le {
47 __le32 buf; /* Can't be pointer on (64-bit) hosts */
48 __le32 buf_size;
49 __le32 idx;
50 char *_buf_compat; /* Redundant pointer for backward compat. */
51};
52
53struct rte_console {
54 /* Virtual UART
55 * When there is no UART (e.g. Quickturn),
56 * the host should write a complete
57 * input line directly into cbuf and then write
58 * the length into vcons_in.
59 * This may also be used when there is a real UART
60 * (at risk of conflicting with
61 * the real UART). vcons_out is currently unused.
62 */
63 uint vcons_in;
64 uint vcons_out;
65
66 /* Output (logging) buffer
67 * Console output is written to a ring buffer log_buf at index log_idx.
68 * The host may read the output when it sees log_idx advance.
69 * Output will be lost if the output wraps around faster than the host
70 * polls.
71 */
72 struct rte_log_le log_le;
73
74 /* Console input line buffer
75 * Characters are read one at a time into cbuf
76 * until <CR> is received, then
77 * the buffer is processed as a command line.
78 * Also used for virtual UART.
79 */
80 uint cbuf_idx;
81 char cbuf[CBUF_LEN];
82};
83
84#endif /* BCMDBG */
85#include <chipcommon.h>
86
87#include "dhd.h"
88#include "dhd_bus.h"
89#include "dhd_proto.h"
90#include "dhd_dbg.h"
91#include <bcmchip.h>
92
93#define TXQLEN 2048 /* bulk tx queue length */
94#define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
95#define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
96#define PRIOMASK 7
97
98#define TXRETRIES 2 /* # of retries for tx frames */
99
100#define BRCMF_RXBOUND 50 /* Default for max rx frames in
101 one scheduling */
102
103#define BRCMF_TXBOUND 20 /* Default for max tx frames in
104 one scheduling */
105
106#define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
107
108#define MEMBLOCK 2048 /* Block size used for downloading
109 of dongle image */
110#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
111 biggest possible glom */
112
113#define BRCMF_FIRSTREAD (1 << 6)
114
115
116/* SBSDIO_DEVICE_CTL */
117
118/* 1: device will assert busy signal when receiving CMD53 */
119#define SBSDIO_DEVCTL_SETBUSY 0x01
120/* 1: assertion of sdio interrupt is synchronous to the sdio clock */
121#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
122/* 1: mask all interrupts to host except the chipActive (rev 8) */
123#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
124/* 1: isolate internal sdio signals, put external pads in tri-state; requires
125 * sdio bus power cycle to clear (rev 9) */
126#define SBSDIO_DEVCTL_PADS_ISO 0x08
127/* Force SD->SB reset mapping (rev 11) */
128#define SBSDIO_DEVCTL_SB_RST_CTL 0x30
129/* Determined by CoreControl bit */
130#define SBSDIO_DEVCTL_RST_CORECTL 0x00
131/* Force backplane reset */
132#define SBSDIO_DEVCTL_RST_BPRESET 0x10
133/* Force no backplane reset */
134#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
135
136/* SBSDIO_FUNC1_CHIPCLKCSR */
137
138/* Force ALP request to backplane */
139#define SBSDIO_FORCE_ALP 0x01
140/* Force HT request to backplane */
141#define SBSDIO_FORCE_HT 0x02
142/* Force ILP request to backplane */
143#define SBSDIO_FORCE_ILP 0x04
144/* Make ALP ready (power up xtal) */
145#define SBSDIO_ALP_AVAIL_REQ 0x08
146/* Make HT ready (power up PLL) */
147#define SBSDIO_HT_AVAIL_REQ 0x10
148/* Squelch clock requests from HW */
149#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
150/* Status: ALP is ready */
151#define SBSDIO_ALP_AVAIL 0x40
152/* Status: HT is ready */
153#define SBSDIO_HT_AVAIL 0x80
154
155#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
156#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
157#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
158#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
159
160#define SBSDIO_CLKAV(regval, alponly) \
161 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
162
163/* direct(mapped) cis space */
164
165/* MAPPED common CIS address */
166#define SBSDIO_CIS_BASE_COMMON 0x1000
167/* maximum bytes in one CIS */
168#define SBSDIO_CIS_SIZE_LIMIT 0x200
169/* cis offset addr is < 17 bits */
170#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
171
172/* manfid tuple length, include tuple, link bytes */
173#define SBSDIO_CIS_MANFID_TUPLE_LEN 6
174
175/* intstatus */
176#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
177#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
178#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
179#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
180#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
181#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
182#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
183#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
184#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
185#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
186#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
187#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
188#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
189#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
190#define I_PC (1 << 10) /* descriptor error */
191#define I_PD (1 << 11) /* data error */
192#define I_DE (1 << 12) /* Descriptor protocol Error */
193#define I_RU (1 << 13) /* Receive descriptor Underflow */
194#define I_RO (1 << 14) /* Receive fifo Overflow */
195#define I_XU (1 << 15) /* Transmit fifo Underflow */
196#define I_RI (1 << 16) /* Receive Interrupt */
197#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
198#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
199#define I_XI (1 << 24) /* Transmit Interrupt */
200#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
201#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
202#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
203#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
204#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
205#define I_SRESET (1 << 30) /* CCCR RES interrupt */
206#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
207#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
208#define I_DMA (I_RI | I_XI | I_ERRORS)
209
210/* corecontrol */
211#define CC_CISRDY (1 << 0) /* CIS Ready */
212#define CC_BPRESEN (1 << 1) /* CCCR RES signal */
213#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
214#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
215#define CC_XMTDATAAVAIL_MODE (1 << 4)
216#define CC_XMTDATAAVAIL_CTRL (1 << 5)
217
218/* SDA_FRAMECTRL */
219#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
220#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
221#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
222#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
223
224/* HW frame tag */
225#define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
226
227/* Total length of frame header for dongle protocol */
228#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
229#define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
230
231/*
232 * Software allocation of To SB Mailbox resources
233 */
234
235/* tosbmailbox bits corresponding to intstatus bits */
236#define SMB_NAK (1 << 0) /* Frame NAK */
237#define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
238#define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
239#define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
240
241/* tosbmailboxdata */
242#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
243
244/*
245 * Software allocation of To Host Mailbox resources
246 */
247
248/* intstatus bits */
249#define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
250#define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
251#define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
252#define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
253
254/* tohostmailboxdata */
255#define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
256#define HMB_DATA_DEVREADY 2 /* talk to host after enable */
257#define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
258#define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
259
260#define HMB_DATA_FCDATA_MASK 0xff000000
261#define HMB_DATA_FCDATA_SHIFT 24
262
263#define HMB_DATA_VERSION_MASK 0x00ff0000
264#define HMB_DATA_VERSION_SHIFT 16
265
266/*
267 * Software-defined protocol header
268 */
269
270/* Current protocol version */
271#define SDPCM_PROT_VERSION 4
272
273/* SW frame header */
274#define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
275
276#define SDPCM_CHANNEL_MASK 0x00000f00
277#define SDPCM_CHANNEL_SHIFT 8
278#define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
279
280#define SDPCM_NEXTLEN_OFFSET 2
281
282/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
283#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
284#define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
285#define SDPCM_DOFFSET_MASK 0xff000000
286#define SDPCM_DOFFSET_SHIFT 24
287#define SDPCM_FCMASK_OFFSET 4 /* Flow control */
288#define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
289#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
290#define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
291
292#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
293
294/* logical channel numbers */
295#define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
296#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
297#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
298#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
299#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
300
301#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
302
303#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
304
305/*
306 * Shared structure between dongle and the host.
307 * The structure contains pointers to trap or assert information.
308 */
309#define SDPCM_SHARED_VERSION 0x0002
310#define SDPCM_SHARED_VERSION_MASK 0x00FF
311#define SDPCM_SHARED_ASSERT_BUILT 0x0100
312#define SDPCM_SHARED_ASSERT 0x0200
313#define SDPCM_SHARED_TRAP 0x0400
314
315/* Space for header read, limit for data packets */
316#define MAX_HDR_READ (1 << 6)
317#define MAX_RX_DATASZ 2048
318
319/* Maximum milliseconds to wait for F2 to come up */
320#define BRCMF_WAIT_F2RDY 3000
321
322/* Bump up limit on waiting for HT to account for first startup;
323 * if the image is doing a CRC calculation before programming the PMU
324 * for HT availability, it could take a couple hundred ms more, so
325 * max out at a 1 second (1000000us).
326 */
327#undef PMU_MAX_TRANSITION_DLY
328#define PMU_MAX_TRANSITION_DLY 1000000
329
330/* Value for ChipClockCSR during initial setup */
331#define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
332 SBSDIO_ALP_AVAIL_REQ)
333
334/* Flags for SDH calls */
335#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
336
337/* sbimstate */
338#define SBIM_IBE 0x20000 /* inbanderror */
339#define SBIM_TO 0x40000 /* timeout */
340#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
341#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
342
343/* sbtmstatelow */
344
345/* reset */
346#define SBTML_RESET 0x0001
347/* reject field */
348#define SBTML_REJ_MASK 0x0006
349/* reject */
350#define SBTML_REJ 0x0002
351/* temporary reject, for error recovery */
352#define SBTML_TMPREJ 0x0004
353
354/* Shift to locate the SI control flags in sbtml */
355#define SBTML_SICF_SHIFT 16
356
357/* sbtmstatehigh */
358#define SBTMH_SERR 0x0001 /* serror */
359#define SBTMH_INT 0x0002 /* interrupt */
360#define SBTMH_BUSY 0x0004 /* busy */
361#define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
362
363/* Shift to locate the SI status flags in sbtmh */
364#define SBTMH_SISF_SHIFT 16
365
366/* sbidlow */
367#define SBIDL_INIT 0x80 /* initiator */
368
369/* sbidhigh */
370#define SBIDH_RC_MASK 0x000f /* revision code */
371#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
372#define SBIDH_RCE_SHIFT 8
373#define SBCOREREV(sbidh) \
374 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
375 ((sbidh) & SBIDH_RC_MASK))
376#define SBIDH_CC_MASK 0x8ff0 /* core code */
377#define SBIDH_CC_SHIFT 4
378#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
379#define SBIDH_VC_SHIFT 16
380
381/*
382 * Conversion of 802.1D priority to precedence level
383 */
384static uint prio2prec(u32 prio)
385{
386 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
387 (prio^2) : prio;
388}
389
390/*
391 * Core reg address translation.
392 * Both macro's returns a 32 bits byte address on the backplane bus.
393 */
394#define CORE_CC_REG(base, field) \
395 (base + offsetof(struct chipcregs, field))
396#define CORE_BUS_REG(base, field) \
397 (base + offsetof(struct sdpcmd_regs, field))
398#define CORE_SB(base, field) \
399 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
400
401/* core registers */
402struct sdpcmd_regs {
403 u32 corecontrol; /* 0x00, rev8 */
404 u32 corestatus; /* rev8 */
405 u32 PAD[1];
406 u32 biststatus; /* rev8 */
407
408 /* PCMCIA access */
409 u16 pcmciamesportaladdr; /* 0x010, rev8 */
410 u16 PAD[1];
411 u16 pcmciamesportalmask; /* rev8 */
412 u16 PAD[1];
413 u16 pcmciawrframebc; /* rev8 */
414 u16 PAD[1];
415 u16 pcmciaunderflowtimer; /* rev8 */
416 u16 PAD[1];
417
418 /* interrupt */
419 u32 intstatus; /* 0x020, rev8 */
420 u32 hostintmask; /* rev8 */
421 u32 intmask; /* rev8 */
422 u32 sbintstatus; /* rev8 */
423 u32 sbintmask; /* rev8 */
424 u32 funcintmask; /* rev4 */
425 u32 PAD[2];
426 u32 tosbmailbox; /* 0x040, rev8 */
427 u32 tohostmailbox; /* rev8 */
428 u32 tosbmailboxdata; /* rev8 */
429 u32 tohostmailboxdata; /* rev8 */
430
431 /* synchronized access to registers in SDIO clock domain */
432 u32 sdioaccess; /* 0x050, rev8 */
433 u32 PAD[3];
434
435 /* PCMCIA frame control */
436 u8 pcmciaframectrl; /* 0x060, rev8 */
437 u8 PAD[3];
438 u8 pcmciawatermark; /* rev8 */
439 u8 PAD[155];
440
441 /* interrupt batching control */
442 u32 intrcvlazy; /* 0x100, rev8 */
443 u32 PAD[3];
444
445 /* counters */
446 u32 cmd52rd; /* 0x110, rev8 */
447 u32 cmd52wr; /* rev8 */
448 u32 cmd53rd; /* rev8 */
449 u32 cmd53wr; /* rev8 */
450 u32 abort; /* rev8 */
451 u32 datacrcerror; /* rev8 */
452 u32 rdoutofsync; /* rev8 */
453 u32 wroutofsync; /* rev8 */
454 u32 writebusy; /* rev8 */
455 u32 readwait; /* rev8 */
456 u32 readterm; /* rev8 */
457 u32 writeterm; /* rev8 */
458 u32 PAD[40];
459 u32 clockctlstatus; /* rev8 */
460 u32 PAD[7];
461
462 u32 PAD[128]; /* DMA engines */
463
464 /* SDIO/PCMCIA CIS region */
465 char cis[512]; /* 0x400-0x5ff, rev6 */
466
467 /* PCMCIA function control registers */
468 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
469 u16 PAD[55];
470
471 /* PCMCIA backplane access */
472 u16 backplanecsr; /* 0x76E, rev6 */
473 u16 backplaneaddr0; /* rev6 */
474 u16 backplaneaddr1; /* rev6 */
475 u16 backplaneaddr2; /* rev6 */
476 u16 backplaneaddr3; /* rev6 */
477 u16 backplanedata0; /* rev6 */
478 u16 backplanedata1; /* rev6 */
479 u16 backplanedata2; /* rev6 */
480 u16 backplanedata3; /* rev6 */
481 u16 PAD[31];
482
483 /* sprom "size" & "blank" info */
484 u16 spromstatus; /* 0x7BE, rev2 */
485 u32 PAD[464];
486
487 u16 PAD[0x80];
488};
489
490#ifdef BCMDBG
491/* Device console log buffer state */
492struct brcmf_console {
493 uint count; /* Poll interval msec counter */
494 uint log_addr; /* Log struct address (fixed) */
495 struct rte_log_le log_le; /* Log struct (host copy) */
496 uint bufsize; /* Size of log buffer */
497 u8 *buf; /* Log buffer (host copy) */
498 uint last; /* Last buffer read index */
499};
500#endif /* BCMDBG */
501
502struct sdpcm_shared {
503 u32 flags;
504 u32 trap_addr;
505 u32 assert_exp_addr;
506 u32 assert_file_addr;
507 u32 assert_line;
508 u32 console_addr; /* Address of struct rte_console */
509 u32 msgtrace_addr;
510 u8 tag[32];
511};
512
513struct sdpcm_shared_le {
514 __le32 flags;
515 __le32 trap_addr;
516 __le32 assert_exp_addr;
517 __le32 assert_file_addr;
518 __le32 assert_line;
519 __le32 console_addr; /* Address of struct rte_console */
520 __le32 msgtrace_addr;
521 u8 tag[32];
522};
523
524
525/* misc chip info needed by some of the routines */
526struct chip_info {
527 u32 chip;
528 u32 chiprev;
529 u32 cccorebase;
530 u32 ccrev;
531 u32 cccaps;
532 u32 buscorebase; /* 32 bits backplane bus address */
533 u32 buscorerev;
534 u32 buscoretype;
535 u32 ramcorebase;
536 u32 armcorebase;
537 u32 pmurev;
538 u32 ramsize;
539};
540
541/* Private data for SDIO bus interaction */
542struct brcmf_bus {
543 struct brcmf_pub *drvr;
544
545 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
546 struct chip_info *ci; /* Chip info struct */
547 char *vars; /* Variables (from CIS and/or other) */
548 uint varsz; /* Size of variables buffer */
549
550 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
551
552 u32 hostintmask; /* Copy of Host Interrupt Mask */
553 u32 intstatus; /* Intstatus bits (events) pending */
554 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
555 bool fcstate; /* State of dongle flow-control */
556
557 uint blocksize; /* Block size of SDIO transfers */
558 uint roundup; /* Max roundup limit */
559
560 struct pktq txq; /* Queue length used for flow-control */
561 u8 flowcontrol; /* per prio flow control bitmask */
562 u8 tx_seq; /* Transmit sequence number (next) */
563 u8 tx_max; /* Maximum transmit sequence allowed */
564
565 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
566 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
567 u16 nextlen; /* Next Read Len from last header */
568 u8 rx_seq; /* Receive sequence number (expected) */
569 bool rxskip; /* Skip receive (awaiting NAK ACK) */
570
571 uint rxbound; /* Rx frames to read before resched */
572 uint txbound; /* Tx frames to send before resched */
573 uint txminmax;
574
575 struct sk_buff *glomd; /* Packet containing glomming descriptor */
576 struct sk_buff *glom; /* Packet chain for glommed superframe */
577 uint glomerr; /* Glom packet read errors */
578
579 u8 *rxbuf; /* Buffer for receiving control packets */
580 uint rxblen; /* Allocated length of rxbuf */
581 u8 *rxctl; /* Aligned pointer into rxbuf */
582 u8 *databuf; /* Buffer for receiving big glom packet */
583 u8 *dataptr; /* Aligned pointer into databuf */
584 uint rxlen; /* Length of valid data in buffer */
585
586 u8 sdpcm_ver; /* Bus protocol reported by dongle */
587
588 bool intr; /* Use interrupts */
589 bool poll; /* Use polling */
590 bool ipend; /* Device interrupt is pending */
591 uint intrcount; /* Count of device interrupt callbacks */
592 uint lastintrs; /* Count as of last watchdog timer */
593 uint spurious; /* Count of spurious interrupts */
594 uint pollrate; /* Ticks between device polls */
595 uint polltick; /* Tick counter */
596 uint pollcnt; /* Count of active polls */
597
598#ifdef BCMDBG
599 uint console_interval;
600 struct brcmf_console console; /* Console output polling support */
601 uint console_addr; /* Console address from shared struct */
602#endif /* BCMDBG */
603
604 uint regfails; /* Count of R_REG failures */
605
606 uint clkstate; /* State of sd and backplane clock(s) */
607 bool activity; /* Activity flag for clock down */
608 s32 idletime; /* Control for activity timeout */
609 s32 idlecount; /* Activity timeout counter */
610 s32 idleclock; /* How to set bus driver when idle */
611 s32 sd_rxchain;
612 bool use_rxchain; /* If brcmf should use PKT chains */
613 bool sleeping; /* Is SDIO bus sleeping? */
614 bool rxflow_mode; /* Rx flow control mode */
615 bool rxflow; /* Is rx flow control on */
616 bool alp_only; /* Don't use HT clock (ALP only) */
617/* Field to decide if rx of control frames happen in rxbuf or lb-pool */
618 bool usebufpool;
619
620 /* Some additional counters */
621 uint tx_sderrs; /* Count of tx attempts with sd errors */
622 uint fcqueued; /* Tx packets that got queued */
623 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
624 uint rx_toolong; /* Receive frames too long to receive */
625 uint rxc_errors; /* SDIO errors when reading control frames */
626 uint rx_hdrfail; /* SDIO errors on header reads */
627 uint rx_badhdr; /* Bad received headers (roosync?) */
628 uint rx_badseq; /* Mismatched rx sequence number */
629 uint fc_rcvd; /* Number of flow-control events received */
630 uint fc_xoff; /* Number which turned on flow-control */
631 uint fc_xon; /* Number which turned off flow-control */
632 uint rxglomfail; /* Failed deglom attempts */
633 uint rxglomframes; /* Number of glom frames (superframes) */
634 uint rxglompkts; /* Number of packets from glom frames */
635 uint f2rxhdrs; /* Number of header reads */
636 uint f2rxdata; /* Number of frame data reads */
637 uint f2txdata; /* Number of f2 frame writes */
638 uint f1regdata; /* Number of f1 register accesses */
639
640 u8 *ctrl_frame_buf;
641 u32 ctrl_frame_len;
642 bool ctrl_frame_stat;
643
644 spinlock_t txqlock;
645 wait_queue_head_t ctrl_wait;
646 wait_queue_head_t dcmd_resp_wait;
647
648 struct timer_list timer;
649 struct completion watchdog_wait;
650 struct task_struct *watchdog_tsk;
651 bool wd_timer_valid;
652 uint save_ms;
653
654 struct task_struct *dpc_tsk;
655 struct completion dpc_wait;
656
657 struct semaphore sdsem;
658
659 const char *fw_name;
660 const struct firmware *firmware;
661 const char *nv_name;
662 u32 fw_ptr;
663};
664
665struct sbconfig {
666 u32 PAD[2];
667 u32 sbipsflag; /* initiator port ocp slave flag */
668 u32 PAD[3];
669 u32 sbtpsflag; /* target port ocp slave flag */
670 u32 PAD[11];
671 u32 sbtmerrloga; /* (sonics >= 2.3) */
672 u32 PAD;
673 u32 sbtmerrlog; /* (sonics >= 2.3) */
674 u32 PAD[3];
675 u32 sbadmatch3; /* address match3 */
676 u32 PAD;
677 u32 sbadmatch2; /* address match2 */
678 u32 PAD;
679 u32 sbadmatch1; /* address match1 */
680 u32 PAD[7];
681 u32 sbimstate; /* initiator agent state */
682 u32 sbintvec; /* interrupt mask */
683 u32 sbtmstatelow; /* target state */
684 u32 sbtmstatehigh; /* target state */
685 u32 sbbwa0; /* bandwidth allocation table0 */
686 u32 PAD;
687 u32 sbimconfiglow; /* initiator configuration */
688 u32 sbimconfighigh; /* initiator configuration */
689 u32 sbadmatch0; /* address match0 */
690 u32 PAD;
691 u32 sbtmconfiglow; /* target configuration */
692 u32 sbtmconfighigh; /* target configuration */
693 u32 sbbconfig; /* broadcast configuration */
694 u32 PAD;
695 u32 sbbstate; /* broadcast state */
696 u32 PAD[3];
697 u32 sbactcnfg; /* activate configuration */
698 u32 PAD[3];
699 u32 sbflagst; /* current sbflags */
700 u32 PAD[3];
701 u32 sbidlow; /* identification */
702 u32 sbidhigh; /* identification */
703};
704
705/* clkstate */
706#define CLK_NONE 0
707#define CLK_SDONLY 1
708#define CLK_PENDING 2 /* Not used yet */
709#define CLK_AVAIL 3
710
711#ifdef BCMDBG
712static int qcount[NUMPRIO];
713static int tx_packets[NUMPRIO];
714#endif /* BCMDBG */
715
716#define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
717
718#define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
719
720/* Retry count for register access failures */
721static const uint retry_limit = 2;
722
723/* Limit on rounding up frames */
724static const uint max_roundup = 512;
725
726#define ALIGNMENT 4
727
728static void pkt_align(struct sk_buff *p, int len, int align)
729{
730 uint datalign;
731 datalign = (unsigned long)(p->data);
732 datalign = roundup(datalign, (align)) - datalign;
733 if (datalign)
734 skb_pull(p, datalign);
735 __skb_trim(p, len);
736}
737
738/* To check if there's window offered */
739static bool data_ok(struct brcmf_bus *bus)
740{
741 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
742 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
743}
744
745/*
746 * Reads a register in the SDIO hardware block. This block occupies a series of
747 * adresses on the 32 bit backplane bus.
748 */
749static void
750r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
751{
752 *retryvar = 0;
753 do {
754 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
755 bus->ci->buscorebase + reg_offset, sizeof(u32));
756 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
757 (++(*retryvar) <= retry_limit));
758 if (*retryvar) {
759 bus->regfails += (*retryvar-1);
760 if (*retryvar > retry_limit) {
761 brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
762 *regvar = 0;
763 }
764 }
765}
766
767static void
768w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
769{
770 *retryvar = 0;
771 do {
772 brcmf_sdcard_reg_write(bus->sdiodev,
773 bus->ci->buscorebase + reg_offset,
774 sizeof(u32), regval);
775 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
776 (++(*retryvar) <= retry_limit));
777 if (*retryvar) {
778 bus->regfails += (*retryvar-1);
779 if (*retryvar > retry_limit)
780 brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
781 reg_offset);
782 }
783}
784
785#define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
786
787#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
788
789/* Packet free applicable unconditionally for sdio and sdspi.
790 * Conditional if bufpool was present for gspi bus.
791 */
792static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
793{
794 if (bus->usebufpool)
795 brcmu_pkt_buf_free_skb(pkt);
796}
797
798/* Turn backplane clock on or off */
799static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
800{
801 int err;
802 u8 clkctl, clkreq, devctl;
803 unsigned long timeout;
804
805 brcmf_dbg(TRACE, "Enter\n");
806
807 clkctl = 0;
808
809 if (on) {
810 /* Request HT Avail */
811 clkreq =
812 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
813
814 if ((bus->ci->chip == BCM4329_CHIP_ID)
815 && (bus->ci->chiprev == 0))
816 clkreq |= SBSDIO_FORCE_ALP;
817
818 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
819 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
820 if (err) {
821 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
822 return -EBADE;
823 }
824
825 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
826 && (bus->ci->buscorerev == 9))) {
827 u32 dummy, retries;
828 r_sdreg32(bus, &dummy,
829 offsetof(struct sdpcmd_regs, clockctlstatus),
830 &retries);
831 }
832
833 /* Check current status */
834 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
835 SBSDIO_FUNC1_CHIPCLKCSR, &err);
836 if (err) {
837 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
838 return -EBADE;
839 }
840
841 /* Go to pending and await interrupt if appropriate */
842 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
843 /* Allow only clock-available interrupt */
844 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
845 SDIO_FUNC_1,
846 SBSDIO_DEVICE_CTL, &err);
847 if (err) {
848 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
849 err);
850 return -EBADE;
851 }
852
853 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
854 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
855 SBSDIO_DEVICE_CTL, devctl, &err);
856 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
857 bus->clkstate = CLK_PENDING;
858
859 return 0;
860 } else if (bus->clkstate == CLK_PENDING) {
861 /* Cancel CA-only interrupt filter */
862 devctl =
863 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
864 SBSDIO_DEVICE_CTL, &err);
865 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
866 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
867 SBSDIO_DEVICE_CTL, devctl, &err);
868 }
869
870 /* Otherwise, wait here (polling) for HT Avail */
871 timeout = jiffies +
872 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
873 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
874 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
875 SDIO_FUNC_1,
876 SBSDIO_FUNC1_CHIPCLKCSR,
877 &err);
878 if (time_after(jiffies, timeout))
879 break;
880 else
881 usleep_range(5000, 10000);
882 }
883 if (err) {
884 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
885 return -EBADE;
886 }
887 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
888 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
889 PMU_MAX_TRANSITION_DLY, clkctl);
890 return -EBADE;
891 }
892
893 /* Mark clock available */
894 bus->clkstate = CLK_AVAIL;
895 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
896
897#if defined(BCMDBG)
898 if (bus->alp_only != true) {
899 if (SBSDIO_ALPONLY(clkctl))
900 brcmf_dbg(ERROR, "HT Clock should be on\n");
901 }
902#endif /* defined (BCMDBG) */
903
904 bus->activity = true;
905 } else {
906 clkreq = 0;
907
908 if (bus->clkstate == CLK_PENDING) {
909 /* Cancel CA-only interrupt filter */
910 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
911 SDIO_FUNC_1,
912 SBSDIO_DEVICE_CTL, &err);
913 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
914 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
915 SBSDIO_DEVICE_CTL, devctl, &err);
916 }
917
918 bus->clkstate = CLK_SDONLY;
919 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
920 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
921 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
922 if (err) {
923 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
924 err);
925 return -EBADE;
926 }
927 }
928 return 0;
929}
930
931/* Change idle/active SD state */
932static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
933{
934 brcmf_dbg(TRACE, "Enter\n");
935
936 if (on)
937 bus->clkstate = CLK_SDONLY;
938 else
939 bus->clkstate = CLK_NONE;
940
941 return 0;
942}
943
944/* Transition SD and backplane clock readiness */
945static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
946{
947#ifdef BCMDBG
948 uint oldstate = bus->clkstate;
949#endif /* BCMDBG */
950
951 brcmf_dbg(TRACE, "Enter\n");
952
953 /* Early exit if we're already there */
954 if (bus->clkstate == target) {
955 if (target == CLK_AVAIL) {
956 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
957 bus->activity = true;
958 }
959 return 0;
960 }
961
962 switch (target) {
963 case CLK_AVAIL:
964 /* Make sure SD clock is available */
965 if (bus->clkstate == CLK_NONE)
966 brcmf_sdbrcm_sdclk(bus, true);
967 /* Now request HT Avail on the backplane */
968 brcmf_sdbrcm_htclk(bus, true, pendok);
969 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
970 bus->activity = true;
971 break;
972
973 case CLK_SDONLY:
974 /* Remove HT request, or bring up SD clock */
975 if (bus->clkstate == CLK_NONE)
976 brcmf_sdbrcm_sdclk(bus, true);
977 else if (bus->clkstate == CLK_AVAIL)
978 brcmf_sdbrcm_htclk(bus, false, false);
979 else
980 brcmf_dbg(ERROR, "request for %d -> %d\n",
981 bus->clkstate, target);
982 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
983 break;
984
985 case CLK_NONE:
986 /* Make sure to remove HT request */
987 if (bus->clkstate == CLK_AVAIL)
988 brcmf_sdbrcm_htclk(bus, false, false);
989 /* Now remove the SD clock */
990 brcmf_sdbrcm_sdclk(bus, false);
991 brcmf_sdbrcm_wd_timer(bus, 0);
992 break;
993 }
994#ifdef BCMDBG
995 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
996#endif /* BCMDBG */
997
998 return 0;
999}
1000
1001static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1002{
1003 uint retries = 0;
1004
1005 brcmf_dbg(INFO, "request %s (currently %s)\n",
1006 sleep ? "SLEEP" : "WAKE",
1007 bus->sleeping ? "SLEEP" : "WAKE");
1008
1009 /* Done if we're already in the requested state */
1010 if (sleep == bus->sleeping)
1011 return 0;
1012
1013 /* Going to sleep: set the alarm and turn off the lights... */
1014 if (sleep) {
1015 /* Don't sleep if something is pending */
1016 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1017 return -EBUSY;
1018
1019 /* Make sure the controller has the bus up */
1020 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1021
1022 /* Tell device to start using OOB wakeup */
1023 w_sdreg32(bus, SMB_USE_OOB,
1024 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1025 if (retries > retry_limit)
1026 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
1027
1028 /* Turn off our contribution to the HT clock request */
1029 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1030
1031 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1032 SBSDIO_FUNC1_CHIPCLKCSR,
1033 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1034
1035 /* Isolate the bus */
1036 if (bus->ci->chip != BCM4329_CHIP_ID) {
1037 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1038 SBSDIO_DEVICE_CTL,
1039 SBSDIO_DEVCTL_PADS_ISO, NULL);
1040 }
1041
1042 /* Change state */
1043 bus->sleeping = true;
1044
1045 } else {
1046 /* Waking up: bus power up is ok, set local state */
1047
1048 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1049 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1050
1051 /* Force pad isolation off if possible
1052 (in case power never toggled) */
1053 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1054 && (bus->ci->buscorerev >= 10))
1055 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1056 SBSDIO_DEVICE_CTL, 0, NULL);
1057
1058 /* Make sure the controller has the bus up */
1059 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1060
1061 /* Send misc interrupt to indicate OOB not needed */
1062 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1063 &retries);
1064 if (retries <= retry_limit)
1065 w_sdreg32(bus, SMB_DEV_INT,
1066 offsetof(struct sdpcmd_regs, tosbmailbox),
1067 &retries);
1068
1069 if (retries > retry_limit)
1070 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
1071
1072 /* Make sure we have SD bus access */
1073 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1074
1075 /* Change state */
1076 bus->sleeping = false;
1077 }
1078
1079 return 0;
1080}
1081
1082static void bus_wake(struct brcmf_bus *bus)
1083{
1084 if (bus->sleeping)
1085 brcmf_sdbrcm_bussleep(bus, false);
1086}
1087
1088static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
1089{
1090 u32 intstatus = 0;
1091 u32 hmb_data;
1092 u8 fcbits;
1093 uint retries = 0;
1094
1095 brcmf_dbg(TRACE, "Enter\n");
1096
1097 /* Read mailbox data and ack that we did so */
1098 r_sdreg32(bus, &hmb_data,
1099 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
1100
1101 if (retries <= retry_limit)
1102 w_sdreg32(bus, SMB_INT_ACK,
1103 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1104 bus->f1regdata += 2;
1105
1106 /* Dongle recomposed rx frames, accept them again */
1107 if (hmb_data & HMB_DATA_NAKHANDLED) {
1108 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
1109 bus->rx_seq);
1110 if (!bus->rxskip)
1111 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
1112
1113 bus->rxskip = false;
1114 intstatus |= I_HMB_FRAME_IND;
1115 }
1116
1117 /*
1118 * DEVREADY does not occur with gSPI.
1119 */
1120 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1121 bus->sdpcm_ver =
1122 (hmb_data & HMB_DATA_VERSION_MASK) >>
1123 HMB_DATA_VERSION_SHIFT;
1124 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1125 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
1126 "expecting %d\n",
1127 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1128 else
1129 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
1130 bus->sdpcm_ver);
1131 }
1132
1133 /*
1134 * Flow Control has been moved into the RX headers and this out of band
1135 * method isn't used any more.
1136 * remaining backward compatible with older dongles.
1137 */
1138 if (hmb_data & HMB_DATA_FC) {
1139 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1140 HMB_DATA_FCDATA_SHIFT;
1141
1142 if (fcbits & ~bus->flowcontrol)
1143 bus->fc_xoff++;
1144
1145 if (bus->flowcontrol & ~fcbits)
1146 bus->fc_xon++;
1147
1148 bus->fc_rcvd++;
1149 bus->flowcontrol = fcbits;
1150 }
1151
1152 /* Shouldn't be any others */
1153 if (hmb_data & ~(HMB_DATA_DEVREADY |
1154 HMB_DATA_NAKHANDLED |
1155 HMB_DATA_FC |
1156 HMB_DATA_FWREADY |
1157 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1158 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
1159 hmb_data);
1160
1161 return intstatus;
1162}
1163
1164static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
1165{
1166 uint retries = 0;
1167 u16 lastrbc;
1168 u8 hi, lo;
1169 int err;
1170
1171 brcmf_dbg(ERROR, "%sterminate frame%s\n",
1172 abort ? "abort command, " : "",
1173 rtx ? ", send NAK" : "");
1174
1175 if (abort)
1176 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1177
1178 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1179 SBSDIO_FUNC1_FRAMECTRL,
1180 SFC_RF_TERM, &err);
1181 bus->f1regdata++;
1182
1183 /* Wait until the packet has been flushed (device/FIFO stable) */
1184 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1185 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1186 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
1187 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1188 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
1189 bus->f1regdata += 2;
1190
1191 if ((hi == 0) && (lo == 0))
1192 break;
1193
1194 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1195 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
1196 lastrbc, (hi << 8) + lo);
1197 }
1198 lastrbc = (hi << 8) + lo;
1199 }
1200
1201 if (!retries)
1202 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
1203 else
1204 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
1205
1206 if (rtx) {
1207 bus->rxrtx++;
1208 w_sdreg32(bus, SMB_NAK,
1209 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1210
1211 bus->f1regdata++;
1212 if (retries <= retry_limit)
1213 bus->rxskip = true;
1214 }
1215
1216 /* Clear partial in any case */
1217 bus->nextlen = 0;
1218
1219 /* If we can't reach the device, signal failure */
1220 if (err || brcmf_sdcard_regfail(bus->sdiodev))
1221 bus->drvr->busstate = BRCMF_BUS_DOWN;
1222}
1223
1224static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1225{
1226 u16 dlen, totlen;
1227 u8 *dptr, num = 0;
1228
1229 u16 sublen, check;
1230 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
1231
1232 int errcode;
1233 u8 chan, seq, doff, sfdoff;
1234 u8 txmax;
1235
1236 int ifidx = 0;
1237 bool usechain = bus->use_rxchain;
1238
1239 /* If packets, issue read(s) and send up packet chain */
1240 /* Return sequence numbers consumed? */
1241
1242 brcmf_dbg(TRACE, "start: glomd %p glom %p\n", bus->glomd, bus->glom);
1243
1244 /* If there's a descriptor, generate the packet chain */
1245 if (bus->glomd) {
1246 pfirst = plast = pnext = NULL;
1247 dlen = (u16) (bus->glomd->len);
1248 dptr = bus->glomd->data;
1249 if (!dlen || (dlen & 1)) {
1250 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1251 dlen);
1252 dlen = 0;
1253 }
1254
1255 for (totlen = num = 0; dlen; num++) {
1256 /* Get (and move past) next length */
1257 sublen = get_unaligned_le16(dptr);
1258 dlen -= sizeof(u16);
1259 dptr += sizeof(u16);
1260 if ((sublen < SDPCM_HDRLEN) ||
1261 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1262 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1263 num, sublen);
1264 pnext = NULL;
1265 break;
1266 }
1267 if (sublen % BRCMF_SDALIGN) {
1268 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1269 sublen, BRCMF_SDALIGN);
1270 usechain = false;
1271 }
1272 totlen += sublen;
1273
1274 /* For last frame, adjust read len so total
1275 is a block multiple */
1276 if (!dlen) {
1277 sublen +=
1278 (roundup(totlen, bus->blocksize) - totlen);
1279 totlen = roundup(totlen, bus->blocksize);
1280 }
1281
1282 /* Allocate/chain packet for next subframe */
1283 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1284 if (pnext == NULL) {
1285 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1286 num, sublen);
1287 break;
1288 }
1289 if (!pfirst) {
1290 pfirst = plast = pnext;
1291 } else {
1292 plast->next = pnext;
1293 plast = pnext;
1294 }
1295
1296 /* Adhere to start alignment requirements */
1297 pkt_align(pnext, sublen, BRCMF_SDALIGN);
1298 }
1299
1300 /* If all allocations succeeded, save packet chain
1301 in bus structure */
1302 if (pnext) {
1303 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1304 totlen, num);
1305 if (BRCMF_GLOM_ON() && bus->nextlen &&
1306 totlen != bus->nextlen) {
1307 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1308 bus->nextlen, totlen, rxseq);
1309 }
1310 bus->glom = pfirst;
1311 pfirst = pnext = NULL;
1312 } else {
1313 if (pfirst)
1314 brcmu_pkt_buf_free_skb(pfirst);
1315 bus->glom = NULL;
1316 num = 0;
1317 }
1318
1319 /* Done with descriptor packet */
1320 brcmu_pkt_buf_free_skb(bus->glomd);
1321 bus->glomd = NULL;
1322 bus->nextlen = 0;
1323 }
1324
1325 /* Ok -- either we just generated a packet chain,
1326 or had one from before */
1327 if (bus->glom) {
1328 if (BRCMF_GLOM_ON()) {
1329 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1330 for (pnext = bus->glom; pnext; pnext = pnext->next) {
1331 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1332 pnext, (u8 *) (pnext->data),
1333 pnext->len, pnext->len);
1334 }
1335 }
1336
1337 pfirst = bus->glom;
1338 dlen = (u16) brcmu_pkttotlen(pfirst);
1339
1340 /* Do an SDIO read for the superframe. Configurable iovar to
1341 * read directly into the chained packet, or allocate a large
1342 * packet and and copy into the chain.
1343 */
1344 if (usechain) {
1345 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1346 bus->sdiodev->sbwad,
1347 SDIO_FUNC_2,
1348 F2SYNC, (u8 *) pfirst->data, dlen,
1349 pfirst);
1350 } else if (bus->dataptr) {
1351 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1352 bus->sdiodev->sbwad,
1353 SDIO_FUNC_2,
1354 F2SYNC, bus->dataptr, dlen,
1355 NULL);
1356 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
1357 bus->dataptr);
1358 if (sublen != dlen) {
1359 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1360 dlen, sublen);
1361 errcode = -1;
1362 }
1363 pnext = NULL;
1364 } else {
1365 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1366 dlen);
1367 errcode = -1;
1368 }
1369 bus->f2rxdata++;
1370
1371 /* On failure, kill the superframe, allow a couple retries */
1372 if (errcode < 0) {
1373 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1374 dlen, errcode);
1375 bus->drvr->rx_errors++;
1376
1377 if (bus->glomerr++ < 3) {
1378 brcmf_sdbrcm_rxfail(bus, true, true);
1379 } else {
1380 bus->glomerr = 0;
1381 brcmf_sdbrcm_rxfail(bus, true, false);
1382 brcmu_pkt_buf_free_skb(bus->glom);
1383 bus->rxglomfail++;
1384 bus->glom = NULL;
1385 }
1386 return 0;
1387 }
1388#ifdef BCMDBG
1389 if (BRCMF_GLOM_ON()) {
1390 printk(KERN_DEBUG "SUPERFRAME:\n");
1391 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1392 pfirst->data, min_t(int, pfirst->len, 48));
1393 }
1394#endif
1395
1396 /* Validate the superframe header */
1397 dptr = (u8 *) (pfirst->data);
1398 sublen = get_unaligned_le16(dptr);
1399 check = get_unaligned_le16(dptr + sizeof(u16));
1400
1401 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1402 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1403 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1404 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1405 brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
1406 bus->nextlen, seq);
1407 bus->nextlen = 0;
1408 }
1409 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1410 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1411
1412 errcode = 0;
1413 if ((u16)~(sublen ^ check)) {
1414 brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1415 sublen, check);
1416 errcode = -1;
1417 } else if (roundup(sublen, bus->blocksize) != dlen) {
1418 brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1419 sublen, roundup(sublen, bus->blocksize),
1420 dlen);
1421 errcode = -1;
1422 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
1423 SDPCM_GLOM_CHANNEL) {
1424 brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
1425 SDPCM_PACKET_CHANNEL(
1426 &dptr[SDPCM_FRAMETAG_LEN]));
1427 errcode = -1;
1428 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
1429 brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
1430 errcode = -1;
1431 } else if ((doff < SDPCM_HDRLEN) ||
1432 (doff > (pfirst->len - SDPCM_HDRLEN))) {
1433 brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1434 doff, sublen, pfirst->len, SDPCM_HDRLEN);
1435 errcode = -1;
1436 }
1437
1438 /* Check sequence number of superframe SW header */
1439 if (rxseq != seq) {
1440 brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
1441 seq, rxseq);
1442 bus->rx_badseq++;
1443 rxseq = seq;
1444 }
1445
1446 /* Check window for sanity */
1447 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1448 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1449 txmax, bus->tx_seq);
1450 txmax = bus->tx_seq + 2;
1451 }
1452 bus->tx_max = txmax;
1453
1454 /* Remove superframe header, remember offset */
1455 skb_pull(pfirst, doff);
1456 sfdoff = doff;
1457
1458 /* Validate all the subframe headers */
1459 for (num = 0, pnext = pfirst; pnext && !errcode;
1460 num++, pnext = pnext->next) {
1461 dptr = (u8 *) (pnext->data);
1462 dlen = (u16) (pnext->len);
1463 sublen = get_unaligned_le16(dptr);
1464 check = get_unaligned_le16(dptr + sizeof(u16));
1465 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1466 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1467#ifdef BCMDBG
1468 if (BRCMF_GLOM_ON()) {
1469 printk(KERN_DEBUG "subframe:\n");
1470 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1471 dptr, 32);
1472 }
1473#endif
1474
1475 if ((u16)~(sublen ^ check)) {
1476 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1477 num, sublen, check);
1478 errcode = -1;
1479 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
1480 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1481 num, sublen, dlen);
1482 errcode = -1;
1483 } else if ((chan != SDPCM_DATA_CHANNEL) &&
1484 (chan != SDPCM_EVENT_CHANNEL)) {
1485 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
1486 num, chan);
1487 errcode = -1;
1488 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
1489 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1490 num, doff, sublen, SDPCM_HDRLEN);
1491 errcode = -1;
1492 }
1493 }
1494
1495 if (errcode) {
1496 /* Terminate frame on error, request
1497 a couple retries */
1498 if (bus->glomerr++ < 3) {
1499 /* Restore superframe header space */
1500 skb_push(pfirst, sfdoff);
1501 brcmf_sdbrcm_rxfail(bus, true, true);
1502 } else {
1503 bus->glomerr = 0;
1504 brcmf_sdbrcm_rxfail(bus, true, false);
1505 brcmu_pkt_buf_free_skb(bus->glom);
1506 bus->rxglomfail++;
1507 bus->glom = NULL;
1508 }
1509 bus->nextlen = 0;
1510 return 0;
1511 }
1512
1513 /* Basic SD framing looks ok - process each packet (header) */
1514 save_pfirst = pfirst;
1515 bus->glom = NULL;
1516 plast = NULL;
1517
1518 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
1519 pnext = pfirst->next;
1520 pfirst->next = NULL;
1521
1522 dptr = (u8 *) (pfirst->data);
1523 sublen = get_unaligned_le16(dptr);
1524 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1525 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1526 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1527
1528 brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1529 num, pfirst, pfirst->data,
1530 pfirst->len, sublen, chan, seq);
1531
1532 /* precondition: chan == SDPCM_DATA_CHANNEL ||
1533 chan == SDPCM_EVENT_CHANNEL */
1534
1535 if (rxseq != seq) {
1536 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
1537 seq, rxseq);
1538 bus->rx_badseq++;
1539 rxseq = seq;
1540 }
1541#ifdef BCMDBG
1542 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1543 printk(KERN_DEBUG "Rx Subframe Data:\n");
1544 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1545 dptr, dlen);
1546 }
1547#endif
1548
1549 __skb_trim(pfirst, sublen);
1550 skb_pull(pfirst, doff);
1551
1552 if (pfirst->len == 0) {
1553 brcmu_pkt_buf_free_skb(pfirst);
1554 if (plast)
1555 plast->next = pnext;
1556 else
1557 save_pfirst = pnext;
1558
1559 continue;
1560 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
1561 pfirst) != 0) {
1562 brcmf_dbg(ERROR, "rx protocol error\n");
1563 bus->drvr->rx_errors++;
1564 brcmu_pkt_buf_free_skb(pfirst);
1565 if (plast)
1566 plast->next = pnext;
1567 else
1568 save_pfirst = pnext;
1569
1570 continue;
1571 }
1572
1573 /* this packet will go up, link back into
1574 chain and count it */
1575 pfirst->next = pnext;
1576 plast = pfirst;
1577 num++;
1578
1579#ifdef BCMDBG
1580 if (BRCMF_GLOM_ON()) {
1581 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1582 num, pfirst, pfirst->data,
1583 pfirst->len, pfirst->next,
1584 pfirst->prev);
1585 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1586 pfirst->data,
1587 min_t(int, pfirst->len, 32));
1588 }
1589#endif /* BCMDBG */
1590 }
1591 if (num) {
1592 up(&bus->sdsem);
1593 brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
1594 down(&bus->sdsem);
1595 }
1596
1597 bus->rxglomframes++;
1598 bus->rxglompkts += num;
1599 }
1600 return num;
1601}
1602
1603static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
1604 bool *pending)
1605{
1606 DECLARE_WAITQUEUE(wait, current);
1607 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1608
1609 /* Wait until control frame is available */
1610 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1611 set_current_state(TASK_INTERRUPTIBLE);
1612
1613 while (!(*condition) && (!signal_pending(current) && timeout))
1614 timeout = schedule_timeout(timeout);
1615
1616 if (signal_pending(current))
1617 *pending = true;
1618
1619 set_current_state(TASK_RUNNING);
1620 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1621
1622 return timeout;
1623}
1624
1625static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
1626{
1627 if (waitqueue_active(&bus->dcmd_resp_wait))
1628 wake_up_interruptible(&bus->dcmd_resp_wait);
1629
1630 return 0;
1631}
1632static void
1633brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
1634{
1635 uint rdlen, pad;
1636
1637 int sdret;
1638
1639 brcmf_dbg(TRACE, "Enter\n");
1640
1641 /* Set rxctl for frame (w/optional alignment) */
1642 bus->rxctl = bus->rxbuf;
1643 bus->rxctl += BRCMF_FIRSTREAD;
1644 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1645 if (pad)
1646 bus->rxctl += (BRCMF_SDALIGN - pad);
1647 bus->rxctl -= BRCMF_FIRSTREAD;
1648
1649 /* Copy the already-read portion over */
1650 memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1651 if (len <= BRCMF_FIRSTREAD)
1652 goto gotpkt;
1653
1654 /* Raise rdlen to next SDIO block to avoid tail command */
1655 rdlen = len - BRCMF_FIRSTREAD;
1656 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1657 pad = bus->blocksize - (rdlen % bus->blocksize);
1658 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1659 ((len + pad) < bus->drvr->maxctl))
1660 rdlen += pad;
1661 } else if (rdlen % BRCMF_SDALIGN) {
1662 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1663 }
1664
1665 /* Satisfy length-alignment requirements */
1666 if (rdlen & (ALIGNMENT - 1))
1667 rdlen = roundup(rdlen, ALIGNMENT);
1668
1669 /* Drop if the read is too big or it exceeds our maximum */
1670 if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
1671 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1672 rdlen, bus->drvr->maxctl);
1673 bus->drvr->rx_errors++;
1674 brcmf_sdbrcm_rxfail(bus, false, false);
1675 goto done;
1676 }
1677
1678 if ((len - doff) > bus->drvr->maxctl) {
1679 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1680 len, len - doff, bus->drvr->maxctl);
1681 bus->drvr->rx_errors++;
1682 bus->rx_toolong++;
1683 brcmf_sdbrcm_rxfail(bus, false, false);
1684 goto done;
1685 }
1686
1687 /* Read remainder of frame body into the rxctl buffer */
1688 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1689 bus->sdiodev->sbwad,
1690 SDIO_FUNC_2,
1691 F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen,
1692 NULL);
1693 bus->f2rxdata++;
1694
1695 /* Control frame failures need retransmission */
1696 if (sdret < 0) {
1697 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1698 rdlen, sdret);
1699 bus->rxc_errors++;
1700 brcmf_sdbrcm_rxfail(bus, true, true);
1701 goto done;
1702 }
1703
1704gotpkt:
1705
1706#ifdef BCMDBG
1707 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1708 printk(KERN_DEBUG "RxCtrl:\n");
1709 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
1710 }
1711#endif
1712
1713 /* Point to valid data and indicate its length */
1714 bus->rxctl += doff;
1715 bus->rxlen = len - doff;
1716
1717done:
1718 /* Awake any waiters */
1719 brcmf_sdbrcm_dcmd_resp_wake(bus);
1720}
1721
1722/* Pad read to blocksize for efficiency */
1723static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
1724{
1725 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1726 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1727 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1728 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1729 *rdlen += *pad;
1730 } else if (*rdlen % BRCMF_SDALIGN) {
1731 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1732 }
1733}
1734
1735static void
1736brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
1737 struct sk_buff **pkt, u8 **rxbuf)
1738{
1739 int sdret; /* Return code from calls */
1740
1741 *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
1742 if (*pkt == NULL)
1743 return;
1744
1745 pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
1746 *rxbuf = (u8 *) ((*pkt)->data);
1747 /* Read the entire frame */
1748 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1749 SDIO_FUNC_2, F2SYNC,
1750 *rxbuf, rdlen, *pkt);
1751 bus->f2rxdata++;
1752
1753 if (sdret < 0) {
1754 brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
1755 rdlen, sdret);
1756 brcmu_pkt_buf_free_skb(*pkt);
1757 bus->drvr->rx_errors++;
1758 /* Force retry w/normal header read.
1759 * Don't attempt NAK for
1760 * gSPI
1761 */
1762 brcmf_sdbrcm_rxfail(bus, true, true);
1763 *pkt = NULL;
1764 }
1765}
1766
1767/* Checks the header */
1768static int
1769brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
1770 u8 rxseq, u16 nextlen, u16 *len)
1771{
1772 u16 check;
1773 bool len_consistent; /* Result of comparing readahead len and
1774 len from hw-hdr */
1775
1776 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
1777
1778 /* Extract hardware header fields */
1779 *len = get_unaligned_le16(bus->rxhdr);
1780 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1781
1782 /* All zeros means readahead info was bad */
1783 if (!(*len | check)) {
1784 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
1785 goto fail;
1786 }
1787
1788 /* Validate check bytes */
1789 if ((u16)~(*len ^ check)) {
1790 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1791 nextlen, *len, check);
1792 bus->rx_badhdr++;
1793 brcmf_sdbrcm_rxfail(bus, false, false);
1794 goto fail;
1795 }
1796
1797 /* Validate frame length */
1798 if (*len < SDPCM_HDRLEN) {
1799 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
1800 *len);
1801 goto fail;
1802 }
1803
1804 /* Check for consistency with readahead info */
1805 len_consistent = (nextlen != (roundup(*len, 16) >> 4));
1806 if (len_consistent) {
1807 /* Mismatch, force retry w/normal
1808 header (may be >4K) */
1809 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1810 nextlen, *len, roundup(*len, 16),
1811 rxseq);
1812 brcmf_sdbrcm_rxfail(bus, true, true);
1813 goto fail;
1814 }
1815
1816 return 0;
1817
1818fail:
1819 brcmf_sdbrcm_pktfree2(bus, pkt);
1820 return -EINVAL;
1821}
1822
1823/* Return true if there may be more frames to read */
1824static uint
1825brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
1826{
1827 u16 len, check; /* Extracted hardware header fields */
1828 u8 chan, seq, doff; /* Extracted software header fields */
1829 u8 fcbits; /* Extracted fcbits from software header */
1830
1831 struct sk_buff *pkt; /* Packet for event or data frames */
1832 u16 pad; /* Number of pad bytes to read */
1833 u16 rdlen; /* Total number of bytes to read */
1834 u8 rxseq; /* Next sequence number to expect */
1835 uint rxleft = 0; /* Remaining number of frames allowed */
1836 int sdret; /* Return code from calls */
1837 u8 txmax; /* Maximum tx sequence offered */
1838 u8 *rxbuf;
1839 int ifidx = 0;
1840 uint rxcount = 0; /* Total frames read */
1841
1842 brcmf_dbg(TRACE, "Enter\n");
1843
1844 /* Not finished unless we encounter no more frames indication */
1845 *finished = false;
1846
1847 for (rxseq = bus->rx_seq, rxleft = maxframes;
1848 !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
1849 rxseq++, rxleft--) {
1850
1851 /* Handle glomming separately */
1852 if (bus->glom || bus->glomd) {
1853 u8 cnt;
1854 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1855 bus->glomd, bus->glom);
1856 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1857 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1858 rxseq += cnt - 1;
1859 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1860 continue;
1861 }
1862
1863 /* Try doing single read if we can */
1864 if (bus->nextlen) {
1865 u16 nextlen = bus->nextlen;
1866 bus->nextlen = 0;
1867
1868 rdlen = len = nextlen << 4;
1869 brcmf_pad(bus, &pad, &rdlen);
1870
1871 /*
1872 * After the frame is received we have to
1873 * distinguish whether it is data
1874 * or non-data frame.
1875 */
1876 brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
1877 if (pkt == NULL) {
1878 /* Give up on data, request rtx of events */
1879 brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1880 len, rdlen, rxseq);
1881 continue;
1882 }
1883
1884 if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
1885 &len) < 0)
1886 continue;
1887
1888 /* Extract software header fields */
1889 chan = SDPCM_PACKET_CHANNEL(
1890 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1891 seq = SDPCM_PACKET_SEQUENCE(
1892 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1893 doff = SDPCM_DOFFSET_VALUE(
1894 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1895 txmax = SDPCM_WINDOW_VALUE(
1896 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1897
1898 bus->nextlen =
1899 bus->rxhdr[SDPCM_FRAMETAG_LEN +
1900 SDPCM_NEXTLEN_OFFSET];
1901 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1902 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1903 bus->nextlen, seq);
1904 bus->nextlen = 0;
1905 }
1906
1907 bus->drvr->rx_readahead_cnt++;
1908
1909 /* Handle Flow Control */
1910 fcbits = SDPCM_FCMASK_VALUE(
1911 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1912
1913 if (bus->flowcontrol != fcbits) {
1914 if (~bus->flowcontrol & fcbits)
1915 bus->fc_xoff++;
1916
1917 if (bus->flowcontrol & ~fcbits)
1918 bus->fc_xon++;
1919
1920 bus->fc_rcvd++;
1921 bus->flowcontrol = fcbits;
1922 }
1923
1924 /* Check and update sequence number */
1925 if (rxseq != seq) {
1926 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
1927 seq, rxseq);
1928 bus->rx_badseq++;
1929 rxseq = seq;
1930 }
1931
1932 /* Check window for sanity */
1933 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1934 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
1935 txmax, bus->tx_seq);
1936 txmax = bus->tx_seq + 2;
1937 }
1938 bus->tx_max = txmax;
1939
1940#ifdef BCMDBG
1941 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1942 printk(KERN_DEBUG "Rx Data:\n");
1943 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1944 rxbuf, len);
1945 } else if (BRCMF_HDRS_ON()) {
1946 printk(KERN_DEBUG "RxHdr:\n");
1947 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1948 bus->rxhdr, SDPCM_HDRLEN);
1949 }
1950#endif
1951
1952 if (chan == SDPCM_CONTROL_CHANNEL) {
1953 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
1954 seq);
1955 /* Force retry w/normal header read */
1956 bus->nextlen = 0;
1957 brcmf_sdbrcm_rxfail(bus, false, true);
1958 brcmf_sdbrcm_pktfree2(bus, pkt);
1959 continue;
1960 }
1961
1962 /* Validate data offset */
1963 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1964 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
1965 doff, len, SDPCM_HDRLEN);
1966 brcmf_sdbrcm_rxfail(bus, false, false);
1967 brcmf_sdbrcm_pktfree2(bus, pkt);
1968 continue;
1969 }
1970
1971 /* All done with this one -- now deliver the packet */
1972 goto deliver;
1973 }
1974
1975 /* Read frame header (hardware and software) */
1976 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1977 SDIO_FUNC_2, F2SYNC, bus->rxhdr,
1978 BRCMF_FIRSTREAD, NULL);
1979 bus->f2rxhdrs++;
1980
1981 if (sdret < 0) {
1982 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
1983 bus->rx_hdrfail++;
1984 brcmf_sdbrcm_rxfail(bus, true, true);
1985 continue;
1986 }
1987#ifdef BCMDBG
1988 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
1989 printk(KERN_DEBUG "RxHdr:\n");
1990 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1991 bus->rxhdr, SDPCM_HDRLEN);
1992 }
1993#endif
1994
1995 /* Extract hardware header fields */
1996 len = get_unaligned_le16(bus->rxhdr);
1997 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1998
1999 /* All zeros means no more frames */
2000 if (!(len | check)) {
2001 *finished = true;
2002 break;
2003 }
2004
2005 /* Validate check bytes */
2006 if ((u16) ~(len ^ check)) {
2007 brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
2008 len, check);
2009 bus->rx_badhdr++;
2010 brcmf_sdbrcm_rxfail(bus, false, false);
2011 continue;
2012 }
2013
2014 /* Validate frame length */
2015 if (len < SDPCM_HDRLEN) {
2016 brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
2017 continue;
2018 }
2019
2020 /* Extract software header fields */
2021 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2022 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2023 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2024 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2025
2026 /* Validate data offset */
2027 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
2028 brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
2029 doff, len, SDPCM_HDRLEN, seq);
2030 bus->rx_badhdr++;
2031 brcmf_sdbrcm_rxfail(bus, false, false);
2032 continue;
2033 }
2034
2035 /* Save the readahead length if there is one */
2036 bus->nextlen =
2037 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
2038 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
2039 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
2040 bus->nextlen, seq);
2041 bus->nextlen = 0;
2042 }
2043
2044 /* Handle Flow Control */
2045 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2046
2047 if (bus->flowcontrol != fcbits) {
2048 if (~bus->flowcontrol & fcbits)
2049 bus->fc_xoff++;
2050
2051 if (bus->flowcontrol & ~fcbits)
2052 bus->fc_xon++;
2053
2054 bus->fc_rcvd++;
2055 bus->flowcontrol = fcbits;
2056 }
2057
2058 /* Check and update sequence number */
2059 if (rxseq != seq) {
2060 brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
2061 bus->rx_badseq++;
2062 rxseq = seq;
2063 }
2064
2065 /* Check window for sanity */
2066 if ((u8) (txmax - bus->tx_seq) > 0x40) {
2067 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
2068 txmax, bus->tx_seq);
2069 txmax = bus->tx_seq + 2;
2070 }
2071 bus->tx_max = txmax;
2072
2073 /* Call a separate function for control frames */
2074 if (chan == SDPCM_CONTROL_CHANNEL) {
2075 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
2076 continue;
2077 }
2078
2079 /* precondition: chan is either SDPCM_DATA_CHANNEL,
2080 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
2081 SDPCM_GLOM_CHANNEL */
2082
2083 /* Length to read */
2084 rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
2085
2086 /* May pad read to blocksize for efficiency */
2087 if (bus->roundup && bus->blocksize &&
2088 (rdlen > bus->blocksize)) {
2089 pad = bus->blocksize - (rdlen % bus->blocksize);
2090 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
2091 ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
2092 rdlen += pad;
2093 } else if (rdlen % BRCMF_SDALIGN) {
2094 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
2095 }
2096
2097 /* Satisfy length-alignment requirements */
2098 if (rdlen & (ALIGNMENT - 1))
2099 rdlen = roundup(rdlen, ALIGNMENT);
2100
2101 if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
2102 /* Too long -- skip this frame */
2103 brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
2104 len, rdlen);
2105 bus->drvr->rx_errors++;
2106 bus->rx_toolong++;
2107 brcmf_sdbrcm_rxfail(bus, false, false);
2108 continue;
2109 }
2110
2111 pkt = brcmu_pkt_buf_get_skb(rdlen +
2112 BRCMF_FIRSTREAD + BRCMF_SDALIGN);
2113 if (!pkt) {
2114 /* Give up on data, request rtx of events */
2115 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
2116 rdlen, chan);
2117 bus->drvr->rx_dropped++;
2118 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
2119 continue;
2120 }
2121
2122 /* Leave room for what we already read, and align remainder */
2123 skb_pull(pkt, BRCMF_FIRSTREAD);
2124 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
2125
2126 /* Read the remaining frame data */
2127 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
2128 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
2129 rdlen, pkt);
2130 bus->f2rxdata++;
2131
2132 if (sdret < 0) {
2133 brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
2134 ((chan == SDPCM_EVENT_CHANNEL) ? "event"
2135 : ((chan == SDPCM_DATA_CHANNEL) ? "data"
2136 : "test")), sdret);
2137 brcmu_pkt_buf_free_skb(pkt);
2138 bus->drvr->rx_errors++;
2139 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
2140 continue;
2141 }
2142
2143 /* Copy the already-read portion */
2144 skb_push(pkt, BRCMF_FIRSTREAD);
2145 memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
2146
2147#ifdef BCMDBG
2148 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2149 printk(KERN_DEBUG "Rx Data:\n");
2150 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2151 pkt->data, len);
2152 }
2153#endif
2154
2155deliver:
2156 /* Save superframe descriptor and allocate packet frame */
2157 if (chan == SDPCM_GLOM_CHANNEL) {
2158 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
2159 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2160 len);
2161#ifdef BCMDBG
2162 if (BRCMF_GLOM_ON()) {
2163 printk(KERN_DEBUG "Glom Data:\n");
2164 print_hex_dump_bytes("",
2165 DUMP_PREFIX_OFFSET,
2166 pkt->data, len);
2167 }
2168#endif
2169 __skb_trim(pkt, len);
2170 skb_pull(pkt, SDPCM_HDRLEN);
2171 bus->glomd = pkt;
2172 } else {
2173 brcmf_dbg(ERROR, "%s: glom superframe w/o "
2174 "descriptor!\n", __func__);
2175 brcmf_sdbrcm_rxfail(bus, false, false);
2176 }
2177 continue;
2178 }
2179
2180 /* Fill in packet len and prio, deliver upward */
2181 __skb_trim(pkt, len);
2182 skb_pull(pkt, doff);
2183
2184 if (pkt->len == 0) {
2185 brcmu_pkt_buf_free_skb(pkt);
2186 continue;
2187 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
2188 brcmf_dbg(ERROR, "rx protocol error\n");
2189 brcmu_pkt_buf_free_skb(pkt);
2190 bus->drvr->rx_errors++;
2191 continue;
2192 }
2193
2194 /* Unlock during rx call */
2195 up(&bus->sdsem);
2196 brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
2197 down(&bus->sdsem);
2198 }
2199 rxcount = maxframes - rxleft;
2200#ifdef BCMDBG
2201 /* Message if we hit the limit */
2202 if (!rxleft)
2203 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
2204 maxframes);
2205 else
2206#endif /* BCMDBG */
2207 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2208 /* Back off rxseq if awaiting rtx, update rx_seq */
2209 if (bus->rxskip)
2210 rxseq--;
2211 bus->rx_seq = rxseq;
2212
2213 return rxcount;
2214}
2215
2216static int
2217brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
2218 u8 *buf, uint nbytes, struct sk_buff *pkt)
2219{
2220 return brcmf_sdcard_send_buf
2221 (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
2222}
2223
2224static void
2225brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
2226{
2227 up(&bus->sdsem);
2228 wait_event_interruptible_timeout(bus->ctrl_wait,
2229 (*lockvar == false), HZ * 2);
2230 down(&bus->sdsem);
2231 return;
2232}
2233
2234static void
2235brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
2236{
2237 if (waitqueue_active(&bus->ctrl_wait))
2238 wake_up_interruptible(&bus->ctrl_wait);
2239 return;
2240}
2241
2242/* Writes a HW/SW header into the packet and sends it. */
2243/* Assumes: (a) header space already there, (b) caller holds lock */
2244static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
2245 uint chan, bool free_pkt)
2246{
2247 int ret;
2248 u8 *frame;
2249 u16 len, pad = 0;
2250 u32 swheader;
2251 struct sk_buff *new;
2252 int i;
2253
2254 brcmf_dbg(TRACE, "Enter\n");
2255
2256 frame = (u8 *) (pkt->data);
2257
2258 /* Add alignment padding, allocate new packet if needed */
2259 pad = ((unsigned long)frame % BRCMF_SDALIGN);
2260 if (pad) {
2261 if (skb_headroom(pkt) < pad) {
2262 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
2263 skb_headroom(pkt), pad);
2264 bus->drvr->tx_realloc++;
2265 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
2266 if (!new) {
2267 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
2268 pkt->len + BRCMF_SDALIGN);
2269 ret = -ENOMEM;
2270 goto done;
2271 }
2272
2273 pkt_align(new, pkt->len, BRCMF_SDALIGN);
2274 memcpy(new->data, pkt->data, pkt->len);
2275 if (free_pkt)
2276 brcmu_pkt_buf_free_skb(pkt);
2277 /* free the pkt if canned one is not used */
2278 free_pkt = true;
2279 pkt = new;
2280 frame = (u8 *) (pkt->data);
2281 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
2282 pad = 0;
2283 } else {
2284 skb_push(pkt, pad);
2285 frame = (u8 *) (pkt->data);
2286 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2287 memset(frame, 0, pad + SDPCM_HDRLEN);
2288 }
2289 }
2290 /* precondition: pad < BRCMF_SDALIGN */
2291
2292 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2293 len = (u16) (pkt->len);
2294 *(__le16 *) frame = cpu_to_le16(len);
2295 *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
2296
2297 /* Software tag: channel, sequence number, data offset */
2298 swheader =
2299 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
2300 (((pad +
2301 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2302
2303 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2304 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2305
2306#ifdef BCMDBG
2307 tx_packets[pkt->priority]++;
2308 if (BRCMF_BYTES_ON() &&
2309 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
2310 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
2311 printk(KERN_DEBUG "Tx Frame:\n");
2312 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
2313 } else if (BRCMF_HDRS_ON()) {
2314 printk(KERN_DEBUG "TxHdr:\n");
2315 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2316 frame, min_t(u16, len, 16));
2317 }
2318#endif
2319
2320 /* Raise len to next SDIO block to eliminate tail command */
2321 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2322 u16 pad = bus->blocksize - (len % bus->blocksize);
2323 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2324 len += pad;
2325 } else if (len % BRCMF_SDALIGN) {
2326 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2327 }
2328
2329 /* Some controllers have trouble with odd bytes -- round to even */
2330 if (len & (ALIGNMENT - 1))
2331 len = roundup(len, ALIGNMENT);
2332
2333 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2334 SDIO_FUNC_2, F2SYNC, frame,
2335 len, pkt);
2336 bus->f2txdata++;
2337
2338 if (ret < 0) {
2339 /* On failure, abort the command and terminate the frame */
2340 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2341 ret);
2342 bus->tx_sderrs++;
2343
2344 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2345 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2346 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2347 NULL);
2348 bus->f1regdata++;
2349
2350 for (i = 0; i < 3; i++) {
2351 u8 hi, lo;
2352 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2353 SDIO_FUNC_1,
2354 SBSDIO_FUNC1_WFRAMEBCHI,
2355 NULL);
2356 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2357 SDIO_FUNC_1,
2358 SBSDIO_FUNC1_WFRAMEBCLO,
2359 NULL);
2360 bus->f1regdata += 2;
2361 if ((hi == 0) && (lo == 0))
2362 break;
2363 }
2364
2365 }
2366 if (ret == 0)
2367 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2368
2369done:
2370 /* restore pkt buffer pointer before calling tx complete routine */
2371 skb_pull(pkt, SDPCM_HDRLEN + pad);
2372 up(&bus->sdsem);
2373 brcmf_txcomplete(bus->drvr, pkt, ret != 0);
2374 down(&bus->sdsem);
2375
2376 if (free_pkt)
2377 brcmu_pkt_buf_free_skb(pkt);
2378
2379 return ret;
2380}
2381
2382static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
2383{
2384 struct sk_buff *pkt;
2385 u32 intstatus = 0;
2386 uint retries = 0;
2387 int ret = 0, prec_out;
2388 uint cnt = 0;
2389 uint datalen;
2390 u8 tx_prec_map;
2391
2392 struct brcmf_pub *drvr = bus->drvr;
2393
2394 brcmf_dbg(TRACE, "Enter\n");
2395
2396 tx_prec_map = ~bus->flowcontrol;
2397
2398 /* Send frames until the limit or some other event */
2399 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
2400 spin_lock_bh(&bus->txqlock);
2401 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2402 if (pkt == NULL) {
2403 spin_unlock_bh(&bus->txqlock);
2404 break;
2405 }
2406 spin_unlock_bh(&bus->txqlock);
2407 datalen = pkt->len - SDPCM_HDRLEN;
2408
2409 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
2410 if (ret)
2411 bus->drvr->tx_errors++;
2412 else
2413 bus->drvr->dstats.tx_bytes += datalen;
2414
2415 /* In poll mode, need to check for other events */
2416 if (!bus->intr && cnt) {
2417 /* Check device status, signal pending interrupt */
2418 r_sdreg32(bus, &intstatus,
2419 offsetof(struct sdpcmd_regs, intstatus),
2420 &retries);
2421 bus->f2txdata++;
2422 if (brcmf_sdcard_regfail(bus->sdiodev))
2423 break;
2424 if (intstatus & bus->hostintmask)
2425 bus->ipend = true;
2426 }
2427 }
2428
2429 /* Deflow-control stack if needed */
2430 if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
2431 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
2432 brcmf_txflowcontrol(drvr, 0, OFF);
2433
2434 return cnt;
2435}
2436
2437static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
2438{
2439 u32 intstatus, newstatus = 0;
2440 uint retries = 0;
2441 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2442 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2443 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2444 bool rxdone = true; /* Flag for no more read data */
2445 bool resched = false; /* Flag indicating resched wanted */
2446
2447 brcmf_dbg(TRACE, "Enter\n");
2448
2449 /* Start with leftover status bits */
2450 intstatus = bus->intstatus;
2451
2452 down(&bus->sdsem);
2453
2454 /* If waiting for HTAVAIL, check status */
2455 if (bus->clkstate == CLK_PENDING) {
2456 int err;
2457 u8 clkctl, devctl = 0;
2458
2459#ifdef BCMDBG
2460 /* Check for inconsistent device control */
2461 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2462 SBSDIO_DEVICE_CTL, &err);
2463 if (err) {
2464 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
2465 bus->drvr->busstate = BRCMF_BUS_DOWN;
2466 }
2467#endif /* BCMDBG */
2468
2469 /* Read CSR, if clock on switch to AVAIL, else ignore */
2470 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2471 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2472 if (err) {
2473 brcmf_dbg(ERROR, "error reading CSR: %d\n",
2474 err);
2475 bus->drvr->busstate = BRCMF_BUS_DOWN;
2476 }
2477
2478 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2479 devctl, clkctl);
2480
2481 if (SBSDIO_HTAV(clkctl)) {
2482 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
2483 SDIO_FUNC_1,
2484 SBSDIO_DEVICE_CTL, &err);
2485 if (err) {
2486 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2487 err);
2488 bus->drvr->busstate = BRCMF_BUS_DOWN;
2489 }
2490 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2491 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2492 SBSDIO_DEVICE_CTL, devctl, &err);
2493 if (err) {
2494 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2495 err);
2496 bus->drvr->busstate = BRCMF_BUS_DOWN;
2497 }
2498 bus->clkstate = CLK_AVAIL;
2499 } else {
2500 goto clkwait;
2501 }
2502 }
2503
2504 bus_wake(bus);
2505
2506 /* Make sure backplane clock is on */
2507 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2508 if (bus->clkstate == CLK_PENDING)
2509 goto clkwait;
2510
2511 /* Pending interrupt indicates new device status */
2512 if (bus->ipend) {
2513 bus->ipend = false;
2514 r_sdreg32(bus, &newstatus,
2515 offsetof(struct sdpcmd_regs, intstatus), &retries);
2516 bus->f1regdata++;
2517 if (brcmf_sdcard_regfail(bus->sdiodev))
2518 newstatus = 0;
2519 newstatus &= bus->hostintmask;
2520 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
2521 if (newstatus) {
2522 w_sdreg32(bus, newstatus,
2523 offsetof(struct sdpcmd_regs, intstatus),
2524 &retries);
2525 bus->f1regdata++;
2526 }
2527 }
2528
2529 /* Merge new bits with previous */
2530 intstatus |= newstatus;
2531 bus->intstatus = 0;
2532
2533 /* Handle flow-control change: read new state in case our ack
2534 * crossed another change interrupt. If change still set, assume
2535 * FC ON for safety, let next loop through do the debounce.
2536 */
2537 if (intstatus & I_HMB_FC_CHANGE) {
2538 intstatus &= ~I_HMB_FC_CHANGE;
2539 w_sdreg32(bus, I_HMB_FC_CHANGE,
2540 offsetof(struct sdpcmd_regs, intstatus), &retries);
2541
2542 r_sdreg32(bus, &newstatus,
2543 offsetof(struct sdpcmd_regs, intstatus), &retries);
2544 bus->f1regdata += 2;
2545 bus->fcstate =
2546 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
2547 intstatus |= (newstatus & bus->hostintmask);
2548 }
2549
2550 /* Handle host mailbox indication */
2551 if (intstatus & I_HMB_HOST_INT) {
2552 intstatus &= ~I_HMB_HOST_INT;
2553 intstatus |= brcmf_sdbrcm_hostmail(bus);
2554 }
2555
2556 /* Generally don't ask for these, can get CRC errors... */
2557 if (intstatus & I_WR_OOSYNC) {
2558 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2559 intstatus &= ~I_WR_OOSYNC;
2560 }
2561
2562 if (intstatus & I_RD_OOSYNC) {
2563 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2564 intstatus &= ~I_RD_OOSYNC;
2565 }
2566
2567 if (intstatus & I_SBINT) {
2568 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2569 intstatus &= ~I_SBINT;
2570 }
2571
2572 /* Would be active due to wake-wlan in gSPI */
2573 if (intstatus & I_CHIPACTIVE) {
2574 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2575 intstatus &= ~I_CHIPACTIVE;
2576 }
2577
2578 /* Ignore frame indications if rxskip is set */
2579 if (bus->rxskip)
2580 intstatus &= ~I_HMB_FRAME_IND;
2581
2582 /* On frame indication, read available frames */
2583 if (PKT_AVAILABLE()) {
2584 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
2585 if (rxdone || bus->rxskip)
2586 intstatus &= ~I_HMB_FRAME_IND;
2587 rxlimit -= min(framecnt, rxlimit);
2588 }
2589
2590 /* Keep still-pending events for next scheduling */
2591 bus->intstatus = intstatus;
2592
2593clkwait:
2594 if (data_ok(bus) && bus->ctrl_frame_stat &&
2595 (bus->clkstate == CLK_AVAIL)) {
2596 int ret, i;
2597
2598 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2599 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
2600 (u32) bus->ctrl_frame_len, NULL);
2601
2602 if (ret < 0) {
2603 /* On failure, abort the command and
2604 terminate the frame */
2605 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2606 ret);
2607 bus->tx_sderrs++;
2608
2609 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2610
2611 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2612 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2613 NULL);
2614 bus->f1regdata++;
2615
2616 for (i = 0; i < 3; i++) {
2617 u8 hi, lo;
2618 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2619 SDIO_FUNC_1,
2620 SBSDIO_FUNC1_WFRAMEBCHI,
2621 NULL);
2622 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2623 SDIO_FUNC_1,
2624 SBSDIO_FUNC1_WFRAMEBCLO,
2625 NULL);
2626 bus->f1regdata += 2;
2627 if ((hi == 0) && (lo == 0))
2628 break;
2629 }
2630
2631 }
2632 if (ret == 0)
2633 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2634
2635 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
2636 bus->ctrl_frame_stat = false;
2637 brcmf_sdbrcm_wait_event_wakeup(bus);
2638 }
2639 /* Send queued frames (limit 1 if rx may still be pending) */
2640 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
2641 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2642 && data_ok(bus)) {
2643 framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
2644 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2645 txlimit -= framecnt;
2646 }
2647
2648 /* Resched if events or tx frames are pending,
2649 else await next interrupt */
2650 /* On failed register access, all bets are off:
2651 no resched or interrupts */
2652 if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
2653 brcmf_sdcard_regfail(bus->sdiodev)) {
2654 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
2655 brcmf_sdcard_regfail(bus->sdiodev));
2656 bus->drvr->busstate = BRCMF_BUS_DOWN;
2657 bus->intstatus = 0;
2658 } else if (bus->clkstate == CLK_PENDING) {
2659 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2660 resched = true;
2661 } else if (bus->intstatus || bus->ipend ||
2662 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
2663 && data_ok(bus)) || PKT_AVAILABLE()) {
2664 resched = true;
2665 }
2666
2667 bus->dpc_sched = resched;
2668
2669 /* If we're done for now, turn off clock request. */
2670 if ((bus->clkstate != CLK_PENDING)
2671 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2672 bus->activity = false;
2673 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2674 }
2675
2676 up(&bus->sdsem);
2677
2678 return resched;
2679}
2680
2681static int brcmf_sdbrcm_dpc_thread(void *data)
2682{
2683 struct brcmf_bus *bus = (struct brcmf_bus *) data;
2684
2685 allow_signal(SIGTERM);
2686 /* Run until signal received */
2687 while (1) {
2688 if (kthread_should_stop())
2689 break;
2690 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
2691 /* Call bus dpc unless it indicated down
2692 (then clean stop) */
2693 if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
2694 if (brcmf_sdbrcm_dpc(bus))
2695 complete(&bus->dpc_wait);
2696 } else {
2697 /* after stopping the bus, exit thread */
2698 brcmf_sdbrcm_bus_stop(bus);
2699 bus->dpc_tsk = NULL;
2700 break;
2701 }
2702 } else
2703 break;
2704 }
2705 return 0;
2706}
2707
2708int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
2709{
2710 int ret = -EBADE;
2711 uint datalen, prec;
2712
2713 brcmf_dbg(TRACE, "Enter\n");
2714
2715 datalen = pkt->len;
2716
2717 /* Add space for the header */
2718 skb_push(pkt, SDPCM_HDRLEN);
2719 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2720
2721 prec = prio2prec((pkt->priority & PRIOMASK));
2722
2723 /* Check for existing queue, current flow-control,
2724 pending event, or pending clock */
2725 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2726 bus->fcqueued++;
2727
2728 /* Priority based enq */
2729 spin_lock_bh(&bus->txqlock);
2730 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
2731 skb_pull(pkt, SDPCM_HDRLEN);
2732 brcmf_txcomplete(bus->drvr, pkt, false);
2733 brcmu_pkt_buf_free_skb(pkt);
2734 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2735 ret = -ENOSR;
2736 } else {
2737 ret = 0;
2738 }
2739 spin_unlock_bh(&bus->txqlock);
2740
2741 if (pktq_len(&bus->txq) >= TXHI)
2742 brcmf_txflowcontrol(bus->drvr, 0, ON);
2743
2744#ifdef BCMDBG
2745 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2746 qcount[prec] = pktq_plen(&bus->txq, prec);
2747#endif
2748 /* Schedule DPC if needed to send queued packet(s) */
2749 if (!bus->dpc_sched) {
2750 bus->dpc_sched = true;
2751 if (bus->dpc_tsk)
2752 complete(&bus->dpc_wait);
2753 }
2754
2755 return ret;
2756}
2757
2758static int
2759brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
2760 uint size)
2761{
2762 int bcmerror = 0;
2763 u32 sdaddr;
2764 uint dsize;
2765
2766 /* Determine initial transfer parameters */
2767 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2768 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2769 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2770 else
2771 dsize = size;
2772
2773 /* Set the backplane window to include the start address */
2774 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2775 if (bcmerror) {
2776 brcmf_dbg(ERROR, "window change failed\n");
2777 goto xfer_done;
2778 }
2779
2780 /* Do the transfer(s) */
2781 while (size) {
2782 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2783 write ? "write" : "read", dsize,
2784 sdaddr, address & SBSDIO_SBWINDOW_MASK);
2785 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2786 sdaddr, data, dsize);
2787 if (bcmerror) {
2788 brcmf_dbg(ERROR, "membytes transfer failed\n");
2789 break;
2790 }
2791
2792 /* Adjust for next transfer (if any) */
2793 size -= dsize;
2794 if (size) {
2795 data += dsize;
2796 address += dsize;
2797 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2798 address);
2799 if (bcmerror) {
2800 brcmf_dbg(ERROR, "window change failed\n");
2801 break;
2802 }
2803 sdaddr = 0;
2804 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2805 }
2806 }
2807
2808xfer_done:
2809 /* Return the window to backplane enumeration space for core access */
2810 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2811 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2812 bus->sdiodev->sbwad);
2813
2814 return bcmerror;
2815}
2816
2817#ifdef BCMDBG
2818#define CONSOLE_LINE_MAX 192
2819
2820static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2821{
2822 struct brcmf_console *c = &bus->console;
2823 u8 line[CONSOLE_LINE_MAX], ch;
2824 u32 n, idx, addr;
2825 int rv;
2826
2827 /* Don't do anything until FWREADY updates console address */
2828 if (bus->console_addr == 0)
2829 return 0;
2830
2831 /* Read console log struct */
2832 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2833 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2834 sizeof(c->log_le));
2835 if (rv < 0)
2836 return rv;
2837
2838 /* Allocate console buffer (one time only) */
2839 if (c->buf == NULL) {
2840 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2841 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2842 if (c->buf == NULL)
2843 return -ENOMEM;
2844 }
2845
2846 idx = le32_to_cpu(c->log_le.idx);
2847
2848 /* Protect against corrupt value */
2849 if (idx > c->bufsize)
2850 return -EBADE;
2851
2852 /* Skip reading the console buffer if the index pointer
2853 has not moved */
2854 if (idx == c->last)
2855 return 0;
2856
2857 /* Read the console buffer */
2858 addr = le32_to_cpu(c->log_le.buf);
2859 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2860 if (rv < 0)
2861 return rv;
2862
2863 while (c->last != idx) {
2864 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2865 if (c->last == idx) {
2866 /* This would output a partial line.
2867 * Instead, back up
2868 * the buffer pointer and output this
2869 * line next time around.
2870 */
2871 if (c->last >= n)
2872 c->last -= n;
2873 else
2874 c->last = c->bufsize - n;
2875 goto break2;
2876 }
2877 ch = c->buf[c->last];
2878 c->last = (c->last + 1) % c->bufsize;
2879 if (ch == '\n')
2880 break;
2881 line[n] = ch;
2882 }
2883
2884 if (n > 0) {
2885 if (line[n - 1] == '\r')
2886 n--;
2887 line[n] = 0;
2888 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2889 }
2890 }
2891break2:
2892
2893 return 0;
2894}
2895#endif /* BCMDBG */
2896
2897static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
2898{
2899 int i;
2900 int ret;
2901
2902 bus->ctrl_frame_stat = false;
2903 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2904 SDIO_FUNC_2, F2SYNC, frame, len, NULL);
2905
2906 if (ret < 0) {
2907 /* On failure, abort the command and terminate the frame */
2908 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2909 ret);
2910 bus->tx_sderrs++;
2911
2912 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2913
2914 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2915 SBSDIO_FUNC1_FRAMECTRL,
2916 SFC_WF_TERM, NULL);
2917 bus->f1regdata++;
2918
2919 for (i = 0; i < 3; i++) {
2920 u8 hi, lo;
2921 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2922 SBSDIO_FUNC1_WFRAMEBCHI,
2923 NULL);
2924 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2925 SBSDIO_FUNC1_WFRAMEBCLO,
2926 NULL);
2927 bus->f1regdata += 2;
2928 if (hi == 0 && lo == 0)
2929 break;
2930 }
2931 return ret;
2932 }
2933
2934 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2935
2936 return ret;
2937}
2938
2939int
2940brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
2941{
2942 u8 *frame;
2943 u16 len;
2944 u32 swheader;
2945 uint retries = 0;
2946 u8 doff = 0;
2947 int ret = -1;
2948
2949 brcmf_dbg(TRACE, "Enter\n");
2950
2951 /* Back the pointer to make a room for bus header */
2952 frame = msg - SDPCM_HDRLEN;
2953 len = (msglen += SDPCM_HDRLEN);
2954
2955 /* Add alignment padding (optional for ctl frames) */
2956 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2957 if (doff) {
2958 frame -= doff;
2959 len += doff;
2960 msglen += doff;
2961 memset(frame, 0, doff + SDPCM_HDRLEN);
2962 }
2963 /* precondition: doff < BRCMF_SDALIGN */
2964 doff += SDPCM_HDRLEN;
2965
2966 /* Round send length to next SDIO block */
2967 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2968 u16 pad = bus->blocksize - (len % bus->blocksize);
2969 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2970 len += pad;
2971 } else if (len % BRCMF_SDALIGN) {
2972 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2973 }
2974
2975 /* Satisfy length-alignment requirements */
2976 if (len & (ALIGNMENT - 1))
2977 len = roundup(len, ALIGNMENT);
2978
2979 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2980
2981 /* Need to lock here to protect txseq and SDIO tx calls */
2982 down(&bus->sdsem);
2983
2984 bus_wake(bus);
2985
2986 /* Make sure backplane clock is on */
2987 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2988
2989 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2990 *(__le16 *) frame = cpu_to_le16((u16) msglen);
2991 *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
2992
2993 /* Software tag: channel, sequence number, data offset */
2994 swheader =
2995 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
2996 SDPCM_CHANNEL_MASK)
2997 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
2998 SDPCM_DOFFSET_MASK);
2999 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
3000 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
3001
3002 if (!data_ok(bus)) {
3003 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
3004 bus->tx_max, bus->tx_seq);
3005 bus->ctrl_frame_stat = true;
3006 /* Send from dpc */
3007 bus->ctrl_frame_buf = frame;
3008 bus->ctrl_frame_len = len;
3009
3010 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
3011
3012 if (bus->ctrl_frame_stat == false) {
3013 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
3014 ret = 0;
3015 } else {
3016 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
3017 ret = -1;
3018 }
3019 }
3020
3021 if (ret == -1) {
3022#ifdef BCMDBG
3023 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
3024 printk(KERN_DEBUG "Tx Frame:\n");
3025 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3026 frame, len);
3027 } else if (BRCMF_HDRS_ON()) {
3028 printk(KERN_DEBUG "TxHdr:\n");
3029 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3030 frame, min_t(u16, len, 16));
3031 }
3032#endif
3033
3034 do {
3035 ret = brcmf_tx_frame(bus, frame, len);
3036 } while (ret < 0 && retries++ < TXRETRIES);
3037 }
3038
3039 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
3040 bus->activity = false;
3041 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
3042 }
3043
3044 up(&bus->sdsem);
3045
3046 if (ret)
3047 bus->drvr->tx_ctlerrs++;
3048 else
3049 bus->drvr->tx_ctlpkts++;
3050
3051 return ret ? -EIO : 0;
3052}
3053
3054int
3055brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
3056{
3057 int timeleft;
3058 uint rxlen = 0;
3059 bool pending;
3060
3061 brcmf_dbg(TRACE, "Enter\n");
3062
3063 /* Wait until control frame is available */
3064 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3065
3066 down(&bus->sdsem);
3067 rxlen = bus->rxlen;
3068 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3069 bus->rxlen = 0;
3070 up(&bus->sdsem);
3071
3072 if (rxlen) {
3073 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3074 rxlen, msglen);
3075 } else if (timeleft == 0) {
3076 brcmf_dbg(ERROR, "resumed on timeout\n");
3077 } else if (pending == true) {
3078 brcmf_dbg(CTL, "cancelled\n");
3079 return -ERESTARTSYS;
3080 } else {
3081 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3082 }
3083
3084 if (rxlen)
3085 bus->drvr->rx_ctlpkts++;
3086 else
3087 bus->drvr->rx_ctlerrs++;
3088
3089 return rxlen ? (int)rxlen : -ETIMEDOUT;
3090}
3091
3092static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
3093{
3094 int bcmerror = 0;
3095
3096 brcmf_dbg(TRACE, "Enter\n");
3097
3098 /* Basic sanity checks */
3099 if (bus->drvr->up) {
3100 bcmerror = -EISCONN;
3101 goto err;
3102 }
3103 if (!len) {
3104 bcmerror = -EOVERFLOW;
3105 goto err;
3106 }
3107
3108 /* Free the old ones and replace with passed variables */
3109 kfree(bus->vars);
3110
3111 bus->vars = kmalloc(len, GFP_ATOMIC);
3112 bus->varsz = bus->vars ? len : 0;
3113 if (bus->vars == NULL) {
3114 bcmerror = -ENOMEM;
3115 goto err;
3116 }
3117
3118 /* Copy the passed variables, which should include the
3119 terminating double-null */
3120 memcpy(bus->vars, arg, bus->varsz);
3121err:
3122 return bcmerror;
3123}
3124
3125static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
3126{
3127 int bcmerror = 0;
3128 u32 varsize;
3129 u32 varaddr;
3130 u8 *vbuffer;
3131 u32 varsizew;
3132 __le32 varsizew_le;
3133#ifdef BCMDBG
3134 char *nvram_ularray;
3135#endif /* BCMDBG */
3136
3137 /* Even if there are no vars are to be written, we still
3138 need to set the ramsize. */
3139 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
3140 varaddr = (bus->ramsize - 4) - varsize;
3141
3142 if (bus->vars) {
3143 vbuffer = kzalloc(varsize, GFP_ATOMIC);
3144 if (!vbuffer)
3145 return -ENOMEM;
3146
3147 memcpy(vbuffer, bus->vars, bus->varsz);
3148
3149 /* Write the vars list */
3150 bcmerror =
3151 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
3152#ifdef BCMDBG
3153 /* Verify NVRAM bytes */
3154 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
3155 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
3156 if (!nvram_ularray)
3157 return -ENOMEM;
3158
3159 /* Upload image to verify downloaded contents. */
3160 memset(nvram_ularray, 0xaa, varsize);
3161
3162 /* Read the vars list to temp buffer for comparison */
3163 bcmerror =
3164 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
3165 varsize);
3166 if (bcmerror) {
3167 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3168 bcmerror, varsize, varaddr);
3169 }
3170 /* Compare the org NVRAM with the one read from RAM */
3171 if (memcmp(vbuffer, nvram_ularray, varsize))
3172 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3173 else
3174 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3175
3176 kfree(nvram_ularray);
3177#endif /* BCMDBG */
3178
3179 kfree(vbuffer);
3180 }
3181
3182 /* adjust to the user specified RAM */
3183 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3184 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3185 varaddr, varsize);
3186 varsize = ((bus->ramsize - 4) - varaddr);
3187
3188 /*
3189 * Determine the length token:
3190 * Varsize, converted to words, in lower 16-bits, checksum
3191 * in upper 16-bits.
3192 */
3193 if (bcmerror) {
3194 varsizew = 0;
3195 varsizew_le = cpu_to_le32(0);
3196 } else {
3197 varsizew = varsize / 4;
3198 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3199 varsizew_le = cpu_to_le32(varsizew);
3200 }
3201
3202 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3203 varsize, varsizew);
3204
3205 /* Write the length token to the last word */
3206 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3207 (u8 *)&varsizew_le, 4);
3208
3209 return bcmerror;
3210}
3211
3212static void
3213brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3214{
3215 u32 regdata;
3216
3217 regdata = brcmf_sdcard_reg_read(sdiodev,
3218 CORE_SB(corebase, sbtmstatelow), 4);
3219 if (regdata & SBTML_RESET)
3220 return;
3221
3222 regdata = brcmf_sdcard_reg_read(sdiodev,
3223 CORE_SB(corebase, sbtmstatelow), 4);
3224 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
3225 /*
3226 * set target reject and spin until busy is clear
3227 * (preserve core-specific bits)
3228 */
3229 regdata = brcmf_sdcard_reg_read(sdiodev,
3230 CORE_SB(corebase, sbtmstatelow), 4);
3231 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
3232 4, regdata | SBTML_REJ);
3233
3234 regdata = brcmf_sdcard_reg_read(sdiodev,
3235 CORE_SB(corebase, sbtmstatelow), 4);
3236 udelay(1);
3237 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3238 CORE_SB(corebase, sbtmstatehigh), 4) &
3239 SBTMH_BUSY), 100000);
3240
3241 regdata = brcmf_sdcard_reg_read(sdiodev,
3242 CORE_SB(corebase, sbtmstatehigh), 4);
3243 if (regdata & SBTMH_BUSY)
3244 brcmf_dbg(ERROR, "ARM core still busy\n");
3245
3246 regdata = brcmf_sdcard_reg_read(sdiodev,
3247 CORE_SB(corebase, sbidlow), 4);
3248 if (regdata & SBIDL_INIT) {
3249 regdata = brcmf_sdcard_reg_read(sdiodev,
3250 CORE_SB(corebase, sbimstate), 4) |
3251 SBIM_RJ;
3252 brcmf_sdcard_reg_write(sdiodev,
3253 CORE_SB(corebase, sbimstate), 4,
3254 regdata);
3255 regdata = brcmf_sdcard_reg_read(sdiodev,
3256 CORE_SB(corebase, sbimstate), 4);
3257 udelay(1);
3258 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3259 CORE_SB(corebase, sbimstate), 4) &
3260 SBIM_BY), 100000);
3261 }
3262
3263 /* set reset and reject while enabling the clocks */
3264 brcmf_sdcard_reg_write(sdiodev,
3265 CORE_SB(corebase, sbtmstatelow), 4,
3266 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3267 SBTML_REJ | SBTML_RESET));
3268 regdata = brcmf_sdcard_reg_read(sdiodev,
3269 CORE_SB(corebase, sbtmstatelow), 4);
3270 udelay(10);
3271
3272 /* clear the initiator reject bit */
3273 regdata = brcmf_sdcard_reg_read(sdiodev,
3274 CORE_SB(corebase, sbidlow), 4);
3275 if (regdata & SBIDL_INIT) {
3276 regdata = brcmf_sdcard_reg_read(sdiodev,
3277 CORE_SB(corebase, sbimstate), 4) &
3278 ~SBIM_RJ;
3279 brcmf_sdcard_reg_write(sdiodev,
3280 CORE_SB(corebase, sbimstate), 4,
3281 regdata);
3282 }
3283 }
3284
3285 /* leave reset and reject asserted */
3286 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3287 (SBTML_REJ | SBTML_RESET));
3288 udelay(1);
3289}
3290
3291static void
3292brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3293{
3294 u32 regdata;
3295
3296 /*
3297 * Must do the disable sequence first to work for
3298 * arbitrary current core state.
3299 */
3300 brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
3301
3302 /*
3303 * Now do the initialization sequence.
3304 * set reset while enabling the clock and
3305 * forcing them on throughout the core
3306 */
3307 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3308 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3309 SBTML_RESET);
3310 udelay(1);
3311
3312 regdata = brcmf_sdcard_reg_read(sdiodev,
3313 CORE_SB(corebase, sbtmstatehigh), 4);
3314 if (regdata & SBTMH_SERR)
3315 brcmf_sdcard_reg_write(sdiodev,
3316 CORE_SB(corebase, sbtmstatehigh), 4, 0);
3317
3318 regdata = brcmf_sdcard_reg_read(sdiodev,
3319 CORE_SB(corebase, sbimstate), 4);
3320 if (regdata & (SBIM_IBE | SBIM_TO))
3321 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
3322 regdata & ~(SBIM_IBE | SBIM_TO));
3323
3324 /* clear reset and allow it to propagate throughout the core */
3325 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3326 (SICF_FGC << SBTML_SICF_SHIFT) |
3327 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3328 udelay(1);
3329
3330 /* leave clock enabled */
3331 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3332 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3333 udelay(1);
3334}
3335
3336static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3337{
3338 uint retries;
3339 u32 regdata;
3340 int bcmerror = 0;
3341
3342 /* To enter download state, disable ARM and reset SOCRAM.
3343 * To exit download state, simply reset ARM (default is RAM boot).
3344 */
3345 if (enter) {
3346 bus->alp_only = true;
3347
3348 brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
3349 bus->ci->armcorebase);
3350
3351 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
3352
3353 /* Clear the top bit of memory */
3354 if (bus->ramsize) {
3355 u32 zeros = 0;
3356 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3357 (u8 *)&zeros, 4);
3358 }
3359 } else {
3360 regdata = brcmf_sdcard_reg_read(bus->sdiodev,
3361 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
3362 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
3363 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3364 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
3365 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3366 bcmerror = -EBADE;
3367 goto fail;
3368 }
3369
3370 bcmerror = brcmf_sdbrcm_write_vars(bus);
3371 if (bcmerror) {
3372 brcmf_dbg(ERROR, "no vars written to RAM\n");
3373 bcmerror = 0;
3374 }
3375
3376 w_sdreg32(bus, 0xFFFFFFFF,
3377 offsetof(struct sdpcmd_regs, intstatus), &retries);
3378
3379 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
3380
3381 /* Allow HT Clock now that the ARM is running. */
3382 bus->alp_only = false;
3383
3384 bus->drvr->busstate = BRCMF_BUS_LOAD;
3385 }
3386fail:
3387 return bcmerror;
3388}
3389
3390static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
3391{
3392 if (bus->firmware->size < bus->fw_ptr + len)
3393 len = bus->firmware->size - bus->fw_ptr;
3394
3395 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3396 bus->fw_ptr += len;
3397 return len;
3398}
3399
3400MODULE_FIRMWARE(BCM4329_FW_NAME);
3401MODULE_FIRMWARE(BCM4329_NV_NAME);
3402
3403static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
3404{
3405 int offset = 0;
3406 uint len;
3407 u8 *memblock = NULL, *memptr;
3408 int ret;
3409
3410 brcmf_dbg(INFO, "Enter\n");
3411
3412 bus->fw_name = BCM4329_FW_NAME;
3413 ret = request_firmware(&bus->firmware, bus->fw_name,
3414 &bus->sdiodev->func[2]->dev);
3415 if (ret) {
3416 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3417 return ret;
3418 }
3419 bus->fw_ptr = 0;
3420
3421 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3422 if (memblock == NULL) {
3423 ret = -ENOMEM;
3424 goto err;
3425 }
3426 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3427 memptr += (BRCMF_SDALIGN -
3428 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3429
3430 /* Download image */
3431 while ((len =
3432 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3433 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3434 if (ret) {
3435 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3436 ret, MEMBLOCK, offset);
3437 goto err;
3438 }
3439
3440 offset += MEMBLOCK;
3441 }
3442
3443err:
3444 kfree(memblock);
3445
3446 release_firmware(bus->firmware);
3447 bus->fw_ptr = 0;
3448
3449 return ret;
3450}
3451
3452/*
3453 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3454 * and ending in a NUL.
3455 * Removes carriage returns, empty lines, comment lines, and converts
3456 * newlines to NULs.
3457 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3458 * by two NULs.
3459*/
3460
3461static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3462{
3463 char *dp;
3464 bool findNewline;
3465 int column;
3466 uint buf_len, n;
3467
3468 dp = varbuf;
3469
3470 findNewline = false;
3471 column = 0;
3472
3473 for (n = 0; n < len; n++) {
3474 if (varbuf[n] == 0)
3475 break;
3476 if (varbuf[n] == '\r')
3477 continue;
3478 if (findNewline && varbuf[n] != '\n')
3479 continue;
3480 findNewline = false;
3481 if (varbuf[n] == '#') {
3482 findNewline = true;
3483 continue;
3484 }
3485 if (varbuf[n] == '\n') {
3486 if (column == 0)
3487 continue;
3488 *dp++ = 0;
3489 column = 0;
3490 continue;
3491 }
3492 *dp++ = varbuf[n];
3493 column++;
3494 }
3495 buf_len = dp - varbuf;
3496
3497 while (dp < varbuf + n)
3498 *dp++ = 0;
3499
3500 return buf_len;
3501}
3502
3503static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
3504{
3505 uint len;
3506 char *memblock = NULL;
3507 char *bufp;
3508 int ret;
3509
3510 bus->nv_name = BCM4329_NV_NAME;
3511 ret = request_firmware(&bus->firmware, bus->nv_name,
3512 &bus->sdiodev->func[2]->dev);
3513 if (ret) {
3514 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3515 return ret;
3516 }
3517 bus->fw_ptr = 0;
3518
3519 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
3520 if (memblock == NULL) {
3521 ret = -ENOMEM;
3522 goto err;
3523 }
3524
3525 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3526
3527 if (len > 0 && len < MEMBLOCK) {
3528 bufp = (char *)memblock;
3529 bufp[len] = 0;
3530 len = brcmf_process_nvram_vars(bufp, len);
3531 bufp += len;
3532 *bufp++ = 0;
3533 if (len)
3534 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3535 if (ret)
3536 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3537 } else {
3538 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3539 ret = -EIO;
3540 }
3541
3542err:
3543 kfree(memblock);
3544
3545 release_firmware(bus->firmware);
3546 bus->fw_ptr = 0;
3547
3548 return ret;
3549}
3550
3551static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3552{
3553 int bcmerror = -1;
3554
3555 /* Keep arm in reset */
3556 if (brcmf_sdbrcm_download_state(bus, true)) {
3557 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3558 goto err;
3559 }
3560
3561 /* External image takes precedence if specified */
3562 if (brcmf_sdbrcm_download_code_file(bus)) {
3563 brcmf_dbg(ERROR, "dongle image file download failed\n");
3564 goto err;
3565 }
3566
3567 /* External nvram takes precedence if specified */
3568 if (brcmf_sdbrcm_download_nvram(bus))
3569 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3570
3571 /* Take arm out of reset */
3572 if (brcmf_sdbrcm_download_state(bus, false)) {
3573 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3574 goto err;
3575 }
3576
3577 bcmerror = 0;
3578
3579err:
3580 return bcmerror;
3581}
3582
3583static bool
3584brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3585{
3586 bool ret;
3587
3588 /* Download the firmware */
3589 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3590
3591 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3592
3593 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3594
3595 return ret;
3596}
3597
3598void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
3599{
3600 u32 local_hostintmask;
3601 u8 saveclk;
3602 uint retries;
3603 int err;
3604
3605 brcmf_dbg(TRACE, "Enter\n");
3606
3607 if (bus->watchdog_tsk) {
3608 send_sig(SIGTERM, bus->watchdog_tsk, 1);
3609 kthread_stop(bus->watchdog_tsk);
3610 bus->watchdog_tsk = NULL;
3611 }
3612
3613 if (bus->dpc_tsk && bus->dpc_tsk != current) {
3614 send_sig(SIGTERM, bus->dpc_tsk, 1);
3615 kthread_stop(bus->dpc_tsk);
3616 bus->dpc_tsk = NULL;
3617 }
3618
3619 down(&bus->sdsem);
3620
3621 bus_wake(bus);
3622
3623 /* Enable clock for device interrupts */
3624 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3625
3626 /* Disable and clear interrupts at the chip level also */
3627 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3628 local_hostintmask = bus->hostintmask;
3629 bus->hostintmask = 0;
3630
3631 /* Change our idea of bus state */
3632 bus->drvr->busstate = BRCMF_BUS_DOWN;
3633
3634 /* Force clocks on backplane to be sure F2 interrupt propagates */
3635 saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3636 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3637 if (!err) {
3638 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3639 SBSDIO_FUNC1_CHIPCLKCSR,
3640 (saveclk | SBSDIO_FORCE_HT), &err);
3641 }
3642 if (err)
3643 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3644
3645 /* Turn off the bus (F2), free any pending packets */
3646 brcmf_dbg(INTR, "disable SDIO interrupts\n");
3647 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3648 SDIO_FUNC_ENABLE_1, NULL);
3649
3650 /* Clear any pending interrupts now that F2 is disabled */
3651 w_sdreg32(bus, local_hostintmask,
3652 offsetof(struct sdpcmd_regs, intstatus), &retries);
3653
3654 /* Turn off the backplane clock (only) */
3655 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3656
3657 /* Clear the data packet queues */
3658 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3659
3660 /* Clear any held glomming stuff */
3661 if (bus->glomd)
3662 brcmu_pkt_buf_free_skb(bus->glomd);
3663
3664 if (bus->glom)
3665 brcmu_pkt_buf_free_skb(bus->glom);
3666
3667 bus->glom = bus->glomd = NULL;
3668
3669 /* Clear rx control and wake any waiters */
3670 bus->rxlen = 0;
3671 brcmf_sdbrcm_dcmd_resp_wake(bus);
3672
3673 /* Reset some F2 state stuff */
3674 bus->rxskip = false;
3675 bus->tx_seq = bus->rx_seq = 0;
3676
3677 up(&bus->sdsem);
3678}
3679
3680int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
3681{
3682 struct brcmf_bus *bus = drvr->bus;
3683 unsigned long timeout;
3684 uint retries = 0;
3685 u8 ready, enable;
3686 int err, ret = 0;
3687 u8 saveclk;
3688
3689 brcmf_dbg(TRACE, "Enter\n");
3690
3691 /* try to download image and nvram to the dongle */
3692 if (drvr->busstate == BRCMF_BUS_DOWN) {
3693 if (!(brcmf_sdbrcm_download_firmware(bus)))
3694 return -1;
3695 }
3696
3697 if (!bus->drvr)
3698 return 0;
3699
3700 /* Start the watchdog timer */
3701 bus->drvr->tickcnt = 0;
3702 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3703
3704 down(&bus->sdsem);
3705
3706 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3707 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3708 if (bus->clkstate != CLK_AVAIL)
3709 goto exit;
3710
3711 /* Force clocks on backplane to be sure F2 interrupt propagates */
3712 saveclk =
3713 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3714 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3715 if (!err) {
3716 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3717 SBSDIO_FUNC1_CHIPCLKCSR,
3718 (saveclk | SBSDIO_FORCE_HT), &err);
3719 }
3720 if (err) {
3721 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3722 goto exit;
3723 }
3724
3725 /* Enable function 2 (frame transfers) */
3726 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3727 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3728 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3729
3730 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3731 enable, NULL);
3732
3733 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3734 ready = 0;
3735 while (enable != ready) {
3736 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3737 SDIO_CCCR_IORx, NULL);
3738 if (time_after(jiffies, timeout))
3739 break;
3740 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3741 /* prevent busy waiting if it takes too long */
3742 msleep_interruptible(20);
3743 }
3744
3745 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3746
3747 /* If F2 successfully enabled, set core and enable interrupts */
3748 if (ready == enable) {
3749 /* Set up the interrupt mask and enable interrupts */
3750 bus->hostintmask = HOSTINTMASK;
3751 w_sdreg32(bus, bus->hostintmask,
3752 offsetof(struct sdpcmd_regs, hostintmask), &retries);
3753
3754 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3755 SBSDIO_WATERMARK, 8, &err);
3756
3757 /* Set bus state according to enable result */
3758 drvr->busstate = BRCMF_BUS_DATA;
3759 }
3760
3761 else {
3762 /* Disable F2 again */
3763 enable = SDIO_FUNC_ENABLE_1;
3764 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3765 SDIO_CCCR_IOEx, enable, NULL);
3766 }
3767
3768 /* Restore previous clock setting */
3769 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3770 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3771
3772 /* If we didn't come up, turn off backplane clock */
3773 if (drvr->busstate != BRCMF_BUS_DATA)
3774 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3775
3776exit:
3777 up(&bus->sdsem);
3778
3779 return ret;
3780}
3781
3782void brcmf_sdbrcm_isr(void *arg)
3783{
3784 struct brcmf_bus *bus = (struct brcmf_bus *) arg;
3785
3786 brcmf_dbg(TRACE, "Enter\n");
3787
3788 if (!bus) {
3789 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3790 return;
3791 }
3792
3793 if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
3794 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3795 return;
3796 }
3797 /* Count the interrupt call */
3798 bus->intrcount++;
3799 bus->ipend = true;
3800
3801 /* Shouldn't get this interrupt if we're sleeping? */
3802 if (bus->sleeping) {
3803 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3804 return;
3805 }
3806
3807 /* Disable additional interrupts (is this needed now)? */
3808 if (!bus->intr)
3809 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3810
3811 bus->dpc_sched = true;
3812 if (bus->dpc_tsk)
3813 complete(&bus->dpc_wait);
3814}
3815
3816static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
3817{
3818 struct brcmf_bus *bus;
3819
3820 brcmf_dbg(TIMER, "Enter\n");
3821
3822 bus = drvr->bus;
3823
3824 /* Ignore the timer if simulating bus down */
3825 if (bus->sleeping)
3826 return false;
3827
3828 down(&bus->sdsem);
3829
3830 /* Poll period: check device if appropriate. */
3831 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3832 u32 intstatus = 0;
3833
3834 /* Reset poll tick */
3835 bus->polltick = 0;
3836
3837 /* Check device if no interrupts */
3838 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3839
3840 if (!bus->dpc_sched) {
3841 u8 devpend;
3842 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3843 SDIO_FUNC_0, SDIO_CCCR_INTx,
3844 NULL);
3845 intstatus =
3846 devpend & (INTR_STATUS_FUNC1 |
3847 INTR_STATUS_FUNC2);
3848 }
3849
3850 /* If there is something, make like the ISR and
3851 schedule the DPC */
3852 if (intstatus) {
3853 bus->pollcnt++;
3854 bus->ipend = true;
3855
3856 bus->dpc_sched = true;
3857 if (bus->dpc_tsk)
3858 complete(&bus->dpc_wait);
3859 }
3860 }
3861
3862 /* Update interrupt tracking */
3863 bus->lastintrs = bus->intrcount;
3864 }
3865#ifdef BCMDBG
3866 /* Poll for console output periodically */
3867 if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
3868 bus->console.count += BRCMF_WD_POLL_MS;
3869 if (bus->console.count >= bus->console_interval) {
3870 bus->console.count -= bus->console_interval;
3871 /* Make sure backplane clock is on */
3872 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3873 if (brcmf_sdbrcm_readconsole(bus) < 0)
3874 /* stop on error */
3875 bus->console_interval = 0;
3876 }
3877 }
3878#endif /* BCMDBG */
3879
3880 /* On idle timeout clear activity flag and/or turn off clock */
3881 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3882 if (++bus->idlecount >= bus->idletime) {
3883 bus->idlecount = 0;
3884 if (bus->activity) {
3885 bus->activity = false;
3886 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3887 } else {
3888 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3889 }
3890 }
3891 }
3892
3893 up(&bus->sdsem);
3894
3895 return bus->ipend;
3896}
3897
3898static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3899{
3900 if (chipid == BCM4329_CHIP_ID)
3901 return true;
3902 return false;
3903}
3904
3905static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
3906{
3907 brcmf_dbg(TRACE, "Enter\n");
3908
3909 kfree(bus->rxbuf);
3910 bus->rxctl = bus->rxbuf = NULL;
3911 bus->rxlen = 0;
3912
3913 kfree(bus->databuf);
3914 bus->databuf = NULL;
3915}
3916
3917static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
3918{
3919 brcmf_dbg(TRACE, "Enter\n");
3920
3921 if (bus->drvr->maxctl) {
3922 bus->rxblen =
3923 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
3924 ALIGNMENT) + BRCMF_SDALIGN;
3925 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3926 if (!(bus->rxbuf))
3927 goto fail;
3928 }
3929
3930 /* Allocate buffer to receive glomed packet */
3931 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3932 if (!(bus->databuf)) {
3933 /* release rxbuf which was already located as above */
3934 if (!bus->rxblen)
3935 kfree(bus->rxbuf);
3936 goto fail;
3937 }
3938
3939 /* Align the buffer */
3940 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3941 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3942 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
3943 else
3944 bus->dataptr = bus->databuf;
3945
3946 return true;
3947
3948fail:
3949 return false;
3950}
3951
3952/* SDIO Pad drive strength to select value mappings */
3953struct sdiod_drive_str {
3954 u8 strength; /* Pad Drive Strength in mA */
3955 u8 sel; /* Chip-specific select value */
3956};
3957
3958/* SDIO Drive Strength to sel value table for PMU Rev 1 */
3959static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
3960 {
3961 4, 0x2}, {
3962 2, 0x3}, {
3963 1, 0x0}, {
3964 0, 0x0}
3965 };
3966
3967/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
3968static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
3969 {
3970 12, 0x7}, {
3971 10, 0x6}, {
3972 8, 0x5}, {
3973 6, 0x4}, {
3974 4, 0x2}, {
3975 2, 0x1}, {
3976 0, 0x0}
3977 };
3978
3979/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
3980static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
3981 {
3982 32, 0x7}, {
3983 26, 0x6}, {
3984 22, 0x5}, {
3985 16, 0x4}, {
3986 12, 0x3}, {
3987 8, 0x2}, {
3988 4, 0x1}, {
3989 0, 0x0}
3990 };
3991
3992#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
3993
3994static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
3995 u32 drivestrength) {
3996 struct sdiod_drive_str *str_tab = NULL;
3997 u32 str_mask = 0;
3998 u32 str_shift = 0;
3999 char chn[8];
4000
4001 if (!(bus->ci->cccaps & CC_CAP_PMU))
4002 return;
4003
4004 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
4005 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
4006 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
4007 str_mask = 0x30000000;
4008 str_shift = 28;
4009 break;
4010 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
4011 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
4012 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
4013 str_mask = 0x00003800;
4014 str_shift = 11;
4015 break;
4016 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
4017 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
4018 str_mask = 0x00003800;
4019 str_shift = 11;
4020 break;
4021 default:
4022 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
4023 brcmu_chipname(bus->ci->chip, chn, 8),
4024 bus->ci->chiprev, bus->ci->pmurev);
4025 break;
4026 }
4027
4028 if (str_tab != NULL) {
4029 u32 drivestrength_sel = 0;
4030 u32 cc_data_temp;
4031 int i;
4032
4033 for (i = 0; str_tab[i].strength != 0; i++) {
4034 if (drivestrength >= str_tab[i].strength) {
4035 drivestrength_sel = str_tab[i].sel;
4036 break;
4037 }
4038 }
4039
4040 brcmf_sdcard_reg_write(bus->sdiodev,
4041 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4042 4, 1);
4043 cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
4044 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
4045 cc_data_temp &= ~str_mask;
4046 drivestrength_sel <<= str_shift;
4047 cc_data_temp |= drivestrength_sel;
4048 brcmf_sdcard_reg_write(bus->sdiodev,
4049 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4050 4, cc_data_temp);
4051
4052 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
4053 drivestrength, cc_data_temp);
4054 }
4055}
4056
4057static int
4058brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
4059 struct chip_info *ci, u32 regs)
4060{
4061 u32 regdata;
4062
4063 /*
4064 * Get CC core rev
4065 * Chipid is assume to be at offset 0 from regs arg
4066 * For different chiptypes or old sdio hosts w/o chipcommon,
4067 * other ways of recognition should be added here.
4068 */
4069 ci->cccorebase = regs;
4070 regdata = brcmf_sdcard_reg_read(sdiodev,
4071 CORE_CC_REG(ci->cccorebase, chipid), 4);
4072 ci->chip = regdata & CID_ID_MASK;
4073 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
4074
4075 brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
4076
4077 /* Address of cores for new chips should be added here */
4078 switch (ci->chip) {
4079 case BCM4329_CHIP_ID:
4080 ci->buscorebase = BCM4329_CORE_BUS_BASE;
4081 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
4082 ci->armcorebase = BCM4329_CORE_ARM_BASE;
4083 ci->ramsize = BCM4329_RAMSIZE;
4084 break;
4085 default:
4086 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
4087 return -ENODEV;
4088 }
4089
4090 regdata = brcmf_sdcard_reg_read(sdiodev,
4091 CORE_SB(ci->cccorebase, sbidhigh), 4);
4092 ci->ccrev = SBCOREREV(regdata);
4093
4094 regdata = brcmf_sdcard_reg_read(sdiodev,
4095 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
4096 ci->pmurev = regdata & PCAP_REV_MASK;
4097
4098 regdata = brcmf_sdcard_reg_read(sdiodev,
4099 CORE_SB(ci->buscorebase, sbidhigh), 4);
4100 ci->buscorerev = SBCOREREV(regdata);
4101 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4102
4103 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
4104 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
4105
4106 /* get chipcommon capabilites */
4107 ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
4108 CORE_CC_REG(ci->cccorebase, capabilities), 4);
4109
4110 return 0;
4111}
4112
4113static int
4114brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
4115{
4116 struct chip_info *ci;
4117 int err;
4118 u8 clkval, clkset;
4119
4120 brcmf_dbg(TRACE, "Enter\n");
4121
4122 /* alloc chip_info_t */
4123 ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
4124 if (NULL == ci)
4125 return -ENOMEM;
4126
4127 /* bus/core/clk setup for register access */
4128 /* Try forcing SDIO core to do ALPAvail request only */
4129 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
4130 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4131 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
4132 if (err) {
4133 brcmf_dbg(ERROR, "error writing for HT off\n");
4134 goto fail;
4135 }
4136
4137 /* If register supported, wait for ALPAvail and then force ALP */
4138 /* This may take up to 15 milliseconds */
4139 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4140 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
4141 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
4142 SPINWAIT(((clkval =
4143 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4144 SBSDIO_FUNC1_CHIPCLKCSR,
4145 NULL)),
4146 !SBSDIO_ALPAV(clkval)),
4147 PMU_MAX_TRANSITION_DLY);
4148 if (!SBSDIO_ALPAV(clkval)) {
4149 brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
4150 clkval);
4151 err = -EBUSY;
4152 goto fail;
4153 }
4154 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
4155 SBSDIO_FORCE_ALP;
4156 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4157 SBSDIO_FUNC1_CHIPCLKCSR,
4158 clkset, &err);
4159 udelay(65);
4160 } else {
4161 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
4162 clkset, clkval);
4163 err = -EACCES;
4164 goto fail;
4165 }
4166
4167 /* Also, disable the extra SDIO pull-ups */
4168 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4169 SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
4170
4171 err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
4172 if (err)
4173 goto fail;
4174
4175 /*
4176 * Make sure any on-chip ARM is off (in case strapping is wrong),
4177 * or downloaded code was already running.
4178 */
4179 brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
4180
4181 brcmf_sdcard_reg_write(bus->sdiodev,
4182 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
4183 brcmf_sdcard_reg_write(bus->sdiodev,
4184 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
4185
4186 /* Disable F2 to clear any intermediate frame state on the dongle */
4187 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4188 SDIO_FUNC_ENABLE_1, NULL);
4189
4190 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
4191 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4192 0, NULL);
4193
4194 /* Done with backplane-dependent accesses, can drop clock... */
4195 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4196 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4197
4198 bus->ci = ci;
4199 return 0;
4200fail:
4201 bus->ci = NULL;
4202 kfree(ci);
4203 return err;
4204}
4205
4206static bool
4207brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4208{
4209 u8 clkctl = 0;
4210 int err = 0;
4211 int reg_addr;
4212 u32 reg_val;
4213
4214 bus->alp_only = true;
4215
4216 /* Return the window to backplane enumeration space for core access */
4217 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
4218 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
4219
4220#ifdef BCMDBG
4221 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
4222 brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
4223
4224#endif /* BCMDBG */
4225
4226 /*
4227 * Force PLL off until brcmf_sdbrcm_chip_attach()
4228 * programs PLL control regs
4229 */
4230
4231 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4232 SBSDIO_FUNC1_CHIPCLKCSR,
4233 BRCMF_INIT_CLKCTL1, &err);
4234 if (!err)
4235 clkctl =
4236 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4237 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4238
4239 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
4240 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
4241 err, BRCMF_INIT_CLKCTL1, clkctl);
4242 goto fail;
4243 }
4244
4245 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
4246 brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
4247 goto fail;
4248 }
4249
4250 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
4251 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
4252 goto fail;
4253 }
4254
4255 brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH);
4256
4257 /* Get info on the ARM and SOCRAM cores... */
4258 brcmf_sdcard_reg_read(bus->sdiodev,
4259 CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4260 bus->ramsize = bus->ci->ramsize;
4261 if (!(bus->ramsize)) {
4262 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
4263 goto fail;
4264 }
4265
4266 /* Set core control so an SDIO reset does a backplane reset */
4267 reg_addr = bus->ci->buscorebase +
4268 offsetof(struct sdpcmd_regs, corecontrol);
4269 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4270 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
4271 reg_val | CC_BPRESEN);
4272
4273 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4274
4275 /* Locate an appropriately-aligned portion of hdrbuf */
4276 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4277 BRCMF_SDALIGN);
4278
4279 /* Set the poll and/or interrupt flags */
4280 bus->intr = true;
4281 bus->poll = false;
4282 if (bus->poll)
4283 bus->pollrate = 1;
4284
4285 return true;
4286
4287fail:
4288 return false;
4289}
4290
4291static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
4292{
4293 brcmf_dbg(TRACE, "Enter\n");
4294
4295 /* Disable F2 to clear any intermediate frame state on the dongle */
4296 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4297 SDIO_FUNC_ENABLE_1, NULL);
4298
4299 bus->drvr->busstate = BRCMF_BUS_DOWN;
4300 bus->sleeping = false;
4301 bus->rxflow = false;
4302
4303 /* Done with backplane-dependent accesses, can drop clock... */
4304 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4305 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4306
4307 /* ...and initialize clock/power states */
4308 bus->clkstate = CLK_SDONLY;
4309 bus->idletime = BRCMF_IDLE_INTERVAL;
4310 bus->idleclock = BRCMF_IDLE_ACTIVE;
4311
4312 /* Query the F2 block size, set roundup accordingly */
4313 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4314 bus->roundup = min(max_roundup, bus->blocksize);
4315
4316 /* bus module does not support packet chaining */
4317 bus->use_rxchain = false;
4318 bus->sd_rxchain = false;
4319
4320 return true;
4321}
4322
4323static int
4324brcmf_sdbrcm_watchdog_thread(void *data)
4325{
4326 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4327
4328 allow_signal(SIGTERM);
4329 /* Run until signal received */
4330 while (1) {
4331 if (kthread_should_stop())
4332 break;
4333 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
4334 brcmf_sdbrcm_bus_watchdog(bus->drvr);
4335 /* Count the tick for reference */
4336 bus->drvr->tickcnt++;
4337 } else
4338 break;
4339 }
4340 return 0;
4341}
4342
4343static void
4344brcmf_sdbrcm_watchdog(unsigned long data)
4345{
4346 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4347
4348 if (bus->watchdog_tsk) {
4349 complete(&bus->watchdog_wait);
4350 /* Reschedule the watchdog */
4351 if (bus->wd_timer_valid)
4352 mod_timer(&bus->timer,
4353 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4354 }
4355}
4356
4357static void
4358brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
4359{
4360 brcmf_dbg(TRACE, "Enter\n");
4361
4362 kfree(bus->ci);
4363 bus->ci = NULL;
4364}
4365
4366static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4367{
4368 brcmf_dbg(TRACE, "Enter\n");
4369
4370 if (bus->ci) {
4371 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4372 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4373 brcmf_sdbrcm_chip_detach(bus);
4374 if (bus->vars && bus->varsz)
4375 kfree(bus->vars);
4376 bus->vars = NULL;
4377 }
4378
4379 brcmf_dbg(TRACE, "Disconnected\n");
4380}
4381
4382/* Detach and free everything */
4383static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
4384{
4385 brcmf_dbg(TRACE, "Enter\n");
4386
4387 if (bus) {
4388 /* De-register interrupt handler */
4389 brcmf_sdcard_intr_dereg(bus->sdiodev);
4390
4391 if (bus->drvr) {
4392 brcmf_detach(bus->drvr);
4393 brcmf_sdbrcm_release_dongle(bus);
4394 bus->drvr = NULL;
4395 }
4396
4397 brcmf_sdbrcm_release_malloc(bus);
4398
4399 kfree(bus);
4400 }
4401
4402 brcmf_dbg(TRACE, "Disconnected\n");
4403}
4404
4405void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4406 u32 regsva, struct brcmf_sdio_dev *sdiodev)
4407{
4408 int ret;
4409 struct brcmf_bus *bus;
4410
4411 /* Init global variables at run-time, not as part of the declaration.
4412 * This is required to support init/de-init of the driver.
4413 * Initialization
4414 * of globals as part of the declaration results in non-deterministic
4415 * behavior since the value of the globals may be different on the
4416 * first time that the driver is initialized vs subsequent
4417 * initializations.
4418 */
4419 brcmf_c_init();
4420
4421 brcmf_dbg(TRACE, "Enter\n");
4422
4423 /* We make an assumption about address window mappings:
4424 * regsva == SI_ENUM_BASE*/
4425
4426 /* Allocate private bus interface state */
4427 bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
4428 if (!bus)
4429 goto fail;
4430
4431 bus->sdiodev = sdiodev;
4432 sdiodev->bus = bus;
4433 bus->txbound = BRCMF_TXBOUND;
4434 bus->rxbound = BRCMF_RXBOUND;
4435 bus->txminmax = BRCMF_TXMINMAX;
4436 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
4437 bus->usebufpool = false; /* Use bufpool if allocated,
4438 else use locally malloced rxbuf */
4439
4440 /* attempt to attach to the dongle */
4441 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
4442 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
4443 goto fail;
4444 }
4445
4446 spin_lock_init(&bus->txqlock);
4447 init_waitqueue_head(&bus->ctrl_wait);
4448 init_waitqueue_head(&bus->dcmd_resp_wait);
4449
4450 /* Set up the watchdog timer */
4451 init_timer(&bus->timer);
4452 bus->timer.data = (unsigned long)bus;
4453 bus->timer.function = brcmf_sdbrcm_watchdog;
4454
4455 /* Initialize thread based operation and lock */
4456 sema_init(&bus->sdsem, 1);
4457
4458 /* Initialize watchdog thread */
4459 init_completion(&bus->watchdog_wait);
4460 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
4461 bus, "brcmf_watchdog");
4462 if (IS_ERR(bus->watchdog_tsk)) {
4463 printk(KERN_WARNING
4464 "brcmf_watchdog thread failed to start\n");
4465 bus->watchdog_tsk = NULL;
4466 }
4467 /* Initialize DPC thread */
4468 init_completion(&bus->dpc_wait);
4469 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
4470 bus, "brcmf_dpc");
4471 if (IS_ERR(bus->dpc_tsk)) {
4472 printk(KERN_WARNING
4473 "brcmf_dpc thread failed to start\n");
4474 bus->dpc_tsk = NULL;
4475 }
4476
4477 /* Attach to the brcmf/OS/network interface */
4478 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
4479 if (!bus->drvr) {
4480 brcmf_dbg(ERROR, "brcmf_attach failed\n");
4481 goto fail;
4482 }
4483
4484 /* Allocate buffers */
4485 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4486 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
4487 goto fail;
4488 }
4489
4490 if (!(brcmf_sdbrcm_probe_init(bus))) {
4491 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
4492 goto fail;
4493 }
4494
4495 /* Register interrupt callback, but mask it (not operational yet). */
4496 brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
4497 ret = brcmf_sdcard_intr_reg(bus->sdiodev);
4498 if (ret != 0) {
4499 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
4500 goto fail;
4501 }
4502 brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
4503
4504 brcmf_dbg(INFO, "completed!!\n");
4505
4506 /* if firmware path present try to download and bring up bus */
4507 ret = brcmf_bus_start(bus->drvr);
4508 if (ret != 0) {
4509 if (ret == -ENOLINK) {
4510 brcmf_dbg(ERROR, "dongle is not responding\n");
4511 goto fail;
4512 }
4513 }
4514 /* Ok, have the per-port tell the stack we're open for business */
4515 if (brcmf_net_attach(bus->drvr, 0) != 0) {
4516 brcmf_dbg(ERROR, "Net attach failed!!\n");
4517 goto fail;
4518 }
4519
4520 return bus;
4521
4522fail:
4523 brcmf_sdbrcm_release(bus);
4524 return NULL;
4525}
4526
4527void brcmf_sdbrcm_disconnect(void *ptr)
4528{
4529 struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
4530
4531 brcmf_dbg(TRACE, "Enter\n");
4532
4533 if (bus)
4534 brcmf_sdbrcm_release(bus);
4535
4536 brcmf_dbg(TRACE, "Disconnected\n");
4537}
4538
4539struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
4540{
4541 return &bus->sdiodev->func[2]->dev;
4542}
4543
4544void
4545brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4546{
4547 /* don't start the wd until fw is loaded */
4548 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4549 return;
4550
4551 /* Totally stop the timer */
4552 if (!wdtick && bus->wd_timer_valid == true) {
4553 del_timer_sync(&bus->timer);
4554 bus->wd_timer_valid = false;
4555 bus->save_ms = wdtick;
4556 return;
4557 }
4558
4559 if (wdtick) {
4560 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4561 if (bus->wd_timer_valid == true)
4562 /* Stop timer and restart at new value */
4563 del_timer_sync(&bus->timer);
4564
4565 /* Create timer again when watchdog period is
4566 dynamically changed or in the first instance
4567 */
4568 bus->timer.expires =
4569 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4570 add_timer(&bus->timer);
4571
4572 } else {
4573 /* Re arm the timer, at last watchdog period */
4574 mod_timer(&bus->timer,
4575 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4576 }
4577
4578 bus->wd_timer_valid = true;
4579 bus->save_ms = wdtick;
4580 }
4581}
diff --git a/drivers/staging/brcm80211/brcmfmac/sdio_host.h b/drivers/staging/brcm80211/brcmfmac/sdio_host.h
deleted file mode 100644
index 726fa898111..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/sdio_host.h
+++ /dev/null
@@ -1,252 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_SDH_H_
18#define _BRCM_SDH_H_
19
20#include <linux/skbuff.h>
21
22#define SDIO_FUNC_0 0
23#define SDIO_FUNC_1 1
24#define SDIO_FUNC_2 2
25
26#define SDIOD_FBR_SIZE 0x100
27
28/* io_en */
29#define SDIO_FUNC_ENABLE_1 0x02
30#define SDIO_FUNC_ENABLE_2 0x04
31
32/* io_rdys */
33#define SDIO_FUNC_READY_1 0x02
34#define SDIO_FUNC_READY_2 0x04
35
36/* intr_status */
37#define INTR_STATUS_FUNC1 0x2
38#define INTR_STATUS_FUNC2 0x4
39
40/* Maximum number of I/O funcs */
41#define SDIOD_MAX_IOFUNCS 7
42
43/* as of sdiod rev 0, supports 3 functions */
44#define SBSDIO_NUM_FUNCTION 3
45
46/* function 1 miscellaneous registers */
47
48/* sprom command and status */
49#define SBSDIO_SPROM_CS 0x10000
50/* sprom info register */
51#define SBSDIO_SPROM_INFO 0x10001
52/* sprom indirect access data byte 0 */
53#define SBSDIO_SPROM_DATA_LOW 0x10002
54/* sprom indirect access data byte 1 */
55#define SBSDIO_SPROM_DATA_HIGH 0x10003
56/* sprom indirect access addr byte 0 */
57#define SBSDIO_SPROM_ADDR_LOW 0x10004
58/* sprom indirect access addr byte 0 */
59#define SBSDIO_SPROM_ADDR_HIGH 0x10005
60/* xtal_pu (gpio) output */
61#define SBSDIO_CHIP_CTRL_DATA 0x10006
62/* xtal_pu (gpio) enable */
63#define SBSDIO_CHIP_CTRL_EN 0x10007
64/* rev < 7, watermark for sdio device */
65#define SBSDIO_WATERMARK 0x10008
66/* control busy signal generation */
67#define SBSDIO_DEVICE_CTL 0x10009
68
69/* SB Address Window Low (b15) */
70#define SBSDIO_FUNC1_SBADDRLOW 0x1000A
71/* SB Address Window Mid (b23:b16) */
72#define SBSDIO_FUNC1_SBADDRMID 0x1000B
73/* SB Address Window High (b31:b24) */
74#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
75/* Frame Control (frame term/abort) */
76#define SBSDIO_FUNC1_FRAMECTRL 0x1000D
77/* ChipClockCSR (ALP/HT ctl/status) */
78#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
79/* SdioPullUp (on cmd, d0-d2) */
80#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
81/* Write Frame Byte Count Low */
82#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
83/* Write Frame Byte Count High */
84#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
85/* Read Frame Byte Count Low */
86#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
87/* Read Frame Byte Count High */
88#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
89
90#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
91#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
92
93/* function 1 OCP space */
94
95/* sb offset addr is <= 15 bits, 32k */
96#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
97#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
98/* with b15, maps to 32-bit SB access */
99#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
100
101/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
102
103#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
104#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
105#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
106/* Address bits from SBADDR regs */
107#define SBSDIO_SBWINDOW_MASK 0xffff8000
108
109#define SDIOH_READ 0 /* Read request */
110#define SDIOH_WRITE 1 /* Write request */
111
112#define SDIOH_DATA_FIX 0 /* Fixed addressing */
113#define SDIOH_DATA_INC 1 /* Incremental addressing */
114
115/* internal return code */
116#define SUCCESS 0
117#define ERROR 1
118
119struct brcmf_sdreg {
120 int func;
121 int offset;
122 int value;
123};
124
125struct brcmf_sdio_dev {
126 struct sdio_func *func[SDIO_MAX_FUNCS];
127 u8 num_funcs; /* Supported funcs on client */
128 u32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
129 u32 sbwad; /* Save backplane window address */
130 bool regfail; /* status of last reg_r/w call */
131 void *bus;
132 atomic_t suspend; /* suspend flag */
133 wait_queue_head_t request_byte_wait;
134 wait_queue_head_t request_word_wait;
135 wait_queue_head_t request_packet_wait;
136 wait_queue_head_t request_buffer_wait;
137
138};
139
140/* Register/deregister device interrupt handler. */
141extern int
142brcmf_sdcard_intr_reg(struct brcmf_sdio_dev *sdiodev);
143
144extern int brcmf_sdcard_intr_dereg(struct brcmf_sdio_dev *sdiodev);
145
146/* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface).
147 * fn: function number
148 * addr: unmodified SDIO-space address
149 * data: data byte to write
150 * err: pointer to error code (or NULL)
151 */
152extern u8 brcmf_sdcard_cfg_read(struct brcmf_sdio_dev *sdiodev, uint func,
153 u32 addr, int *err);
154extern void brcmf_sdcard_cfg_write(struct brcmf_sdio_dev *sdiodev, uint func,
155 u32 addr, u8 data, int *err);
156
157/* Synchronous access to device (client) core registers via CMD53 to F1.
158 * addr: backplane address (i.e. >= regsva from attach)
159 * size: register width in bytes (2 or 4)
160 * data: data for register write
161 */
162extern u32
163brcmf_sdcard_reg_read(struct brcmf_sdio_dev *sdiodev, u32 addr, uint size);
164
165extern u32
166brcmf_sdcard_reg_write(struct brcmf_sdio_dev *sdiodev, u32 addr, uint size,
167 u32 data);
168
169/* Indicate if last reg read/write failed */
170extern bool brcmf_sdcard_regfail(struct brcmf_sdio_dev *sdiodev);
171
172/* Buffer transfer to/from device (client) core via cmd53.
173 * fn: function number
174 * addr: backplane address (i.e. >= regsva from attach)
175 * flags: backplane width, address increment, sync/async
176 * buf: pointer to memory data buffer
177 * nbytes: number of bytes to transfer to/from buf
178 * pkt: pointer to packet associated with buf (if any)
179 * complete: callback function for command completion (async only)
180 * handle: handle for completion callback (first arg in callback)
181 * Returns 0 or error code.
182 * NOTE: Async operation is not currently supported.
183 */
184extern int
185brcmf_sdcard_send_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
186 uint flags, u8 *buf, uint nbytes, struct sk_buff *pkt);
187extern int
188brcmf_sdcard_recv_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
189 uint flags, u8 *buf, uint nbytes, struct sk_buff *pkt);
190
191/* Flags bits */
192
193/* Four-byte target (backplane) width (vs. two-byte) */
194#define SDIO_REQ_4BYTE 0x1
195/* Fixed address (FIFO) (vs. incrementing address) */
196#define SDIO_REQ_FIXED 0x2
197/* Async request (vs. sync request) */
198#define SDIO_REQ_ASYNC 0x4
199
200/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
201 * rw: read or write (0/1)
202 * addr: direct SDIO address
203 * buf: pointer to memory data buffer
204 * nbytes: number of bytes to transfer to/from buf
205 * Returns 0 or error code.
206 */
207extern int brcmf_sdcard_rwdata(struct brcmf_sdio_dev *sdiodev, uint rw,
208 u32 addr, u8 *buf, uint nbytes);
209
210/* Issue an abort to the specified function */
211extern int brcmf_sdcard_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
212
213/* platform specific/high level functions */
214extern int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
215extern int brcmf_sdio_remove(struct brcmf_sdio_dev *sdiodev);
216
217extern int brcmf_sdcard_set_sbaddr_window(struct brcmf_sdio_dev *sdiodev,
218 u32 address);
219
220/* attach, return handler on success, NULL if failed.
221 * The handler shall be provided by all subsequent calls. No local cache
222 * cfghdl points to the starting address of pci device mapped memory
223 */
224extern int brcmf_sdioh_attach(struct brcmf_sdio_dev *sdiodev);
225extern void brcmf_sdioh_detach(struct brcmf_sdio_dev *sdiodev);
226
227/* read or write one byte using cmd52 */
228extern int brcmf_sdioh_request_byte(struct brcmf_sdio_dev *sdiodev, uint rw,
229 uint fnc, uint addr, u8 *byte);
230
231/* read or write 2/4 bytes using cmd53 */
232extern int
233brcmf_sdioh_request_word(struct brcmf_sdio_dev *sdiodev,
234 uint rw, uint fnc, uint addr,
235 u32 *word, uint nbyte);
236
237/* read or write any buffer using cmd53 */
238extern int
239brcmf_sdioh_request_buffer(struct brcmf_sdio_dev *sdiodev,
240 uint fix_inc, uint rw, uint fnc_num,
241 u32 addr, uint regwidth,
242 u32 buflen, u8 *buffer, struct sk_buff *pkt);
243
244/* Watchdog timer interface for pm ops */
245extern void brcmf_sdio_wdtmr_enable(struct brcmf_sdio_dev *sdiodev,
246 bool enable);
247
248extern void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
249 u32 regsva, struct brcmf_sdio_dev *sdiodev);
250extern void brcmf_sdbrcm_disconnect(void *ptr);
251extern void brcmf_sdbrcm_isr(void *arg);
252#endif /* _BRCM_SDH_H_ */
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
deleted file mode 100644
index fc643c1eb59..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
+++ /dev/null
@@ -1,3730 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/* Toplevel file. Relies on dhd_linux.c to send commands to the dongle. */
18
19#include <linux/kernel.h>
20#include <linux/if_arp.h>
21#include <linux/sched.h>
22#include <linux/kthread.h>
23#include <linux/netdevice.h>
24#include <linux/bitops.h>
25#include <linux/etherdevice.h>
26#include <linux/ieee80211.h>
27#include <linux/uaccess.h>
28#include <net/cfg80211.h>
29
30#include <brcmu_utils.h>
31#include <defs.h>
32#include <brcmu_wifi.h>
33#include "dhd.h"
34#include "wl_cfg80211.h"
35
36#define BRCMF_ASSOC_PARAMS_FIXED_SIZE \
37 (sizeof(struct brcmf_assoc_params_le) - sizeof(u16))
38
39static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
40
41static u32 brcmf_dbg_level = WL_DBG_ERR;
42
43static void brcmf_set_drvdata(struct brcmf_cfg80211_dev *dev, void *data)
44{
45 dev->driver_data = data;
46}
47
48static void *brcmf_get_drvdata(struct brcmf_cfg80211_dev *dev)
49{
50 void *data = NULL;
51
52 if (dev)
53 data = dev->driver_data;
54 return data;
55}
56
57static
58struct brcmf_cfg80211_priv *brcmf_priv_get(struct brcmf_cfg80211_dev *cfg_dev)
59{
60 struct brcmf_cfg80211_iface *ci = brcmf_get_drvdata(cfg_dev);
61 return ci->cfg_priv;
62}
63
64static bool check_sys_up(struct wiphy *wiphy)
65{
66 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
67 if (!test_bit(WL_STATUS_READY, &cfg_priv->status)) {
68 WL_INFO("device is not ready : status (%d)\n",
69 (int)cfg_priv->status);
70 return false;
71 }
72 return true;
73}
74
75#define CHAN2G(_channel, _freq, _flags) { \
76 .band = IEEE80211_BAND_2GHZ, \
77 .center_freq = (_freq), \
78 .hw_value = (_channel), \
79 .flags = (_flags), \
80 .max_antenna_gain = 0, \
81 .max_power = 30, \
82}
83
84#define CHAN5G(_channel, _flags) { \
85 .band = IEEE80211_BAND_5GHZ, \
86 .center_freq = 5000 + (5 * (_channel)), \
87 .hw_value = (_channel), \
88 .flags = (_flags), \
89 .max_antenna_gain = 0, \
90 .max_power = 30, \
91}
92
93#define RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
94#define RATETAB_ENT(_rateid, _flags) \
95 { \
96 .bitrate = RATE_TO_BASE100KBPS(_rateid), \
97 .hw_value = (_rateid), \
98 .flags = (_flags), \
99 }
100
101static struct ieee80211_rate __wl_rates[] = {
102 RATETAB_ENT(BRCM_RATE_1M, 0),
103 RATETAB_ENT(BRCM_RATE_2M, IEEE80211_RATE_SHORT_PREAMBLE),
104 RATETAB_ENT(BRCM_RATE_5M5, IEEE80211_RATE_SHORT_PREAMBLE),
105 RATETAB_ENT(BRCM_RATE_11M, IEEE80211_RATE_SHORT_PREAMBLE),
106 RATETAB_ENT(BRCM_RATE_6M, 0),
107 RATETAB_ENT(BRCM_RATE_9M, 0),
108 RATETAB_ENT(BRCM_RATE_12M, 0),
109 RATETAB_ENT(BRCM_RATE_18M, 0),
110 RATETAB_ENT(BRCM_RATE_24M, 0),
111 RATETAB_ENT(BRCM_RATE_36M, 0),
112 RATETAB_ENT(BRCM_RATE_48M, 0),
113 RATETAB_ENT(BRCM_RATE_54M, 0),
114};
115
116#define wl_a_rates (__wl_rates + 4)
117#define wl_a_rates_size 8
118#define wl_g_rates (__wl_rates + 0)
119#define wl_g_rates_size 12
120
121static struct ieee80211_channel __wl_2ghz_channels[] = {
122 CHAN2G(1, 2412, 0),
123 CHAN2G(2, 2417, 0),
124 CHAN2G(3, 2422, 0),
125 CHAN2G(4, 2427, 0),
126 CHAN2G(5, 2432, 0),
127 CHAN2G(6, 2437, 0),
128 CHAN2G(7, 2442, 0),
129 CHAN2G(8, 2447, 0),
130 CHAN2G(9, 2452, 0),
131 CHAN2G(10, 2457, 0),
132 CHAN2G(11, 2462, 0),
133 CHAN2G(12, 2467, 0),
134 CHAN2G(13, 2472, 0),
135 CHAN2G(14, 2484, 0),
136};
137
138static struct ieee80211_channel __wl_5ghz_a_channels[] = {
139 CHAN5G(34, 0), CHAN5G(36, 0),
140 CHAN5G(38, 0), CHAN5G(40, 0),
141 CHAN5G(42, 0), CHAN5G(44, 0),
142 CHAN5G(46, 0), CHAN5G(48, 0),
143 CHAN5G(52, 0), CHAN5G(56, 0),
144 CHAN5G(60, 0), CHAN5G(64, 0),
145 CHAN5G(100, 0), CHAN5G(104, 0),
146 CHAN5G(108, 0), CHAN5G(112, 0),
147 CHAN5G(116, 0), CHAN5G(120, 0),
148 CHAN5G(124, 0), CHAN5G(128, 0),
149 CHAN5G(132, 0), CHAN5G(136, 0),
150 CHAN5G(140, 0), CHAN5G(149, 0),
151 CHAN5G(153, 0), CHAN5G(157, 0),
152 CHAN5G(161, 0), CHAN5G(165, 0),
153 CHAN5G(184, 0), CHAN5G(188, 0),
154 CHAN5G(192, 0), CHAN5G(196, 0),
155 CHAN5G(200, 0), CHAN5G(204, 0),
156 CHAN5G(208, 0), CHAN5G(212, 0),
157 CHAN5G(216, 0),
158};
159
160static struct ieee80211_channel __wl_5ghz_n_channels[] = {
161 CHAN5G(32, 0), CHAN5G(34, 0),
162 CHAN5G(36, 0), CHAN5G(38, 0),
163 CHAN5G(40, 0), CHAN5G(42, 0),
164 CHAN5G(44, 0), CHAN5G(46, 0),
165 CHAN5G(48, 0), CHAN5G(50, 0),
166 CHAN5G(52, 0), CHAN5G(54, 0),
167 CHAN5G(56, 0), CHAN5G(58, 0),
168 CHAN5G(60, 0), CHAN5G(62, 0),
169 CHAN5G(64, 0), CHAN5G(66, 0),
170 CHAN5G(68, 0), CHAN5G(70, 0),
171 CHAN5G(72, 0), CHAN5G(74, 0),
172 CHAN5G(76, 0), CHAN5G(78, 0),
173 CHAN5G(80, 0), CHAN5G(82, 0),
174 CHAN5G(84, 0), CHAN5G(86, 0),
175 CHAN5G(88, 0), CHAN5G(90, 0),
176 CHAN5G(92, 0), CHAN5G(94, 0),
177 CHAN5G(96, 0), CHAN5G(98, 0),
178 CHAN5G(100, 0), CHAN5G(102, 0),
179 CHAN5G(104, 0), CHAN5G(106, 0),
180 CHAN5G(108, 0), CHAN5G(110, 0),
181 CHAN5G(112, 0), CHAN5G(114, 0),
182 CHAN5G(116, 0), CHAN5G(118, 0),
183 CHAN5G(120, 0), CHAN5G(122, 0),
184 CHAN5G(124, 0), CHAN5G(126, 0),
185 CHAN5G(128, 0), CHAN5G(130, 0),
186 CHAN5G(132, 0), CHAN5G(134, 0),
187 CHAN5G(136, 0), CHAN5G(138, 0),
188 CHAN5G(140, 0), CHAN5G(142, 0),
189 CHAN5G(144, 0), CHAN5G(145, 0),
190 CHAN5G(146, 0), CHAN5G(147, 0),
191 CHAN5G(148, 0), CHAN5G(149, 0),
192 CHAN5G(150, 0), CHAN5G(151, 0),
193 CHAN5G(152, 0), CHAN5G(153, 0),
194 CHAN5G(154, 0), CHAN5G(155, 0),
195 CHAN5G(156, 0), CHAN5G(157, 0),
196 CHAN5G(158, 0), CHAN5G(159, 0),
197 CHAN5G(160, 0), CHAN5G(161, 0),
198 CHAN5G(162, 0), CHAN5G(163, 0),
199 CHAN5G(164, 0), CHAN5G(165, 0),
200 CHAN5G(166, 0), CHAN5G(168, 0),
201 CHAN5G(170, 0), CHAN5G(172, 0),
202 CHAN5G(174, 0), CHAN5G(176, 0),
203 CHAN5G(178, 0), CHAN5G(180, 0),
204 CHAN5G(182, 0), CHAN5G(184, 0),
205 CHAN5G(186, 0), CHAN5G(188, 0),
206 CHAN5G(190, 0), CHAN5G(192, 0),
207 CHAN5G(194, 0), CHAN5G(196, 0),
208 CHAN5G(198, 0), CHAN5G(200, 0),
209 CHAN5G(202, 0), CHAN5G(204, 0),
210 CHAN5G(206, 0), CHAN5G(208, 0),
211 CHAN5G(210, 0), CHAN5G(212, 0),
212 CHAN5G(214, 0), CHAN5G(216, 0),
213 CHAN5G(218, 0), CHAN5G(220, 0),
214 CHAN5G(222, 0), CHAN5G(224, 0),
215 CHAN5G(226, 0), CHAN5G(228, 0),
216};
217
218static struct ieee80211_supported_band __wl_band_2ghz = {
219 .band = IEEE80211_BAND_2GHZ,
220 .channels = __wl_2ghz_channels,
221 .n_channels = ARRAY_SIZE(__wl_2ghz_channels),
222 .bitrates = wl_g_rates,
223 .n_bitrates = wl_g_rates_size,
224};
225
226static struct ieee80211_supported_band __wl_band_5ghz_a = {
227 .band = IEEE80211_BAND_5GHZ,
228 .channels = __wl_5ghz_a_channels,
229 .n_channels = ARRAY_SIZE(__wl_5ghz_a_channels),
230 .bitrates = wl_a_rates,
231 .n_bitrates = wl_a_rates_size,
232};
233
234static struct ieee80211_supported_band __wl_band_5ghz_n = {
235 .band = IEEE80211_BAND_5GHZ,
236 .channels = __wl_5ghz_n_channels,
237 .n_channels = ARRAY_SIZE(__wl_5ghz_n_channels),
238 .bitrates = wl_a_rates,
239 .n_bitrates = wl_a_rates_size,
240};
241
242static const u32 __wl_cipher_suites[] = {
243 WLAN_CIPHER_SUITE_WEP40,
244 WLAN_CIPHER_SUITE_WEP104,
245 WLAN_CIPHER_SUITE_TKIP,
246 WLAN_CIPHER_SUITE_CCMP,
247 WLAN_CIPHER_SUITE_AES_CMAC,
248};
249
250/* function for reading/writing a single u32 from/to the dongle */
251static int
252brcmf_exec_dcmd_u32(struct net_device *ndev, u32 cmd, u32 *par)
253{
254 int err;
255 __le32 par_le = cpu_to_le32(*par);
256
257 err = brcmf_exec_dcmd(ndev, cmd, &par_le, sizeof(__le32));
258 *par = le32_to_cpu(par_le);
259
260 return err;
261}
262
263static void convert_key_from_CPU(struct brcmf_wsec_key *key,
264 struct brcmf_wsec_key_le *key_le)
265{
266 key_le->index = cpu_to_le32(key->index);
267 key_le->len = cpu_to_le32(key->len);
268 key_le->algo = cpu_to_le32(key->algo);
269 key_le->flags = cpu_to_le32(key->flags);
270 key_le->rxiv.hi = cpu_to_le32(key->rxiv.hi);
271 key_le->rxiv.lo = cpu_to_le16(key->rxiv.lo);
272 key_le->iv_initialized = cpu_to_le32(key->iv_initialized);
273 memcpy(key_le->data, key->data, sizeof(key->data));
274 memcpy(key_le->ea, key->ea, sizeof(key->ea));
275}
276
277static int send_key_to_dongle(struct net_device *ndev,
278 struct brcmf_wsec_key *key)
279{
280 int err;
281 struct brcmf_wsec_key_le key_le;
282
283 convert_key_from_CPU(key, &key_le);
284 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_KEY, &key_le, sizeof(key_le));
285 if (err)
286 WL_ERR("WLC_SET_KEY error (%d)\n", err);
287 return err;
288}
289
290static s32
291brcmf_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev,
292 enum nl80211_iftype type, u32 *flags,
293 struct vif_params *params)
294{
295 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
296 struct wireless_dev *wdev;
297 s32 infra = 0;
298 s32 err = 0;
299
300 WL_TRACE("Enter\n");
301 if (!check_sys_up(wiphy))
302 return -EIO;
303
304 switch (type) {
305 case NL80211_IFTYPE_MONITOR:
306 case NL80211_IFTYPE_WDS:
307 WL_ERR("type (%d) : currently we do not support this type\n",
308 type);
309 return -EOPNOTSUPP;
310 case NL80211_IFTYPE_ADHOC:
311 cfg_priv->conf->mode = WL_MODE_IBSS;
312 infra = 0;
313 break;
314 case NL80211_IFTYPE_STATION:
315 cfg_priv->conf->mode = WL_MODE_BSS;
316 infra = 1;
317 break;
318 default:
319 err = -EINVAL;
320 goto done;
321 }
322
323 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_SET_INFRA, &infra);
324 if (err) {
325 WL_ERR("WLC_SET_INFRA error (%d)\n", err);
326 err = -EAGAIN;
327 } else {
328 wdev = ndev->ieee80211_ptr;
329 wdev->iftype = type;
330 }
331
332 WL_INFO("IF Type = %s\n",
333 (cfg_priv->conf->mode == WL_MODE_IBSS) ? "Adhoc" : "Infra");
334
335done:
336 WL_TRACE("Exit\n");
337
338 return err;
339}
340
341static s32 brcmf_dev_intvar_set(struct net_device *ndev, s8 *name, s32 val)
342{
343 s8 buf[BRCMF_DCMD_SMLEN];
344 u32 len;
345 s32 err = 0;
346 __le32 val_le;
347
348 val_le = cpu_to_le32(val);
349 len = brcmu_mkiovar(name, (char *)(&val_le), sizeof(val_le), buf,
350 sizeof(buf));
351 BUG_ON(!len);
352
353 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_VAR, buf, len);
354 if (err)
355 WL_ERR("error (%d)\n", err);
356
357 return err;
358}
359
360static s32
361brcmf_dev_intvar_get(struct net_device *ndev, s8 *name, s32 *retval)
362{
363 union {
364 s8 buf[BRCMF_DCMD_SMLEN];
365 __le32 val;
366 } var;
367 u32 len;
368 u32 data_null;
369 s32 err = 0;
370
371 len =
372 brcmu_mkiovar(name, (char *)(&data_null), 0, (char *)(&var),
373 sizeof(var.buf));
374 BUG_ON(!len);
375 err = brcmf_exec_dcmd(ndev, BRCMF_C_GET_VAR, &var, len);
376 if (err)
377 WL_ERR("error (%d)\n", err);
378
379 *retval = le32_to_cpu(var.val);
380
381 return err;
382}
383
384static void brcmf_set_mpc(struct net_device *ndev, int mpc)
385{
386 s32 err = 0;
387 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
388
389 if (test_bit(WL_STATUS_READY, &cfg_priv->status)) {
390 err = brcmf_dev_intvar_set(ndev, "mpc", mpc);
391 if (err) {
392 WL_ERR("fail to set mpc\n");
393 return;
394 }
395 WL_INFO("MPC : %d\n", mpc);
396 }
397}
398
399static void wl_iscan_prep(struct brcmf_scan_params_le *params_le,
400 struct brcmf_ssid *ssid)
401{
402 memcpy(params_le->bssid, ether_bcast, ETH_ALEN);
403 params_le->bss_type = DOT11_BSSTYPE_ANY;
404 params_le->scan_type = 0;
405 params_le->channel_num = 0;
406 params_le->nprobes = cpu_to_le32(-1);
407 params_le->active_time = cpu_to_le32(-1);
408 params_le->passive_time = cpu_to_le32(-1);
409 params_le->home_time = cpu_to_le32(-1);
410 if (ssid && ssid->SSID_len)
411 memcpy(&params_le->ssid_le, ssid, sizeof(struct brcmf_ssid));
412}
413
414static s32
415brcmf_dev_iovar_setbuf(struct net_device *ndev, s8 * iovar, void *param,
416 s32 paramlen, void *bufptr, s32 buflen)
417{
418 s32 iolen;
419
420 iolen = brcmu_mkiovar(iovar, param, paramlen, bufptr, buflen);
421 BUG_ON(!iolen);
422
423 return brcmf_exec_dcmd(ndev, BRCMF_C_SET_VAR, bufptr, iolen);
424}
425
426static s32
427brcmf_dev_iovar_getbuf(struct net_device *ndev, s8 * iovar, void *param,
428 s32 paramlen, void *bufptr, s32 buflen)
429{
430 s32 iolen;
431
432 iolen = brcmu_mkiovar(iovar, param, paramlen, bufptr, buflen);
433 BUG_ON(!iolen);
434
435 return brcmf_exec_dcmd(ndev, BRCMF_C_GET_VAR, bufptr, buflen);
436}
437
438static s32
439brcmf_run_iscan(struct brcmf_cfg80211_iscan_ctrl *iscan,
440 struct brcmf_ssid *ssid, u16 action)
441{
442 s32 params_size = BRCMF_SCAN_PARAMS_FIXED_SIZE +
443 offsetof(struct brcmf_iscan_params_le, params_le);
444 struct brcmf_iscan_params_le *params;
445 s32 err = 0;
446
447 if (ssid && ssid->SSID_len)
448 params_size += sizeof(struct brcmf_ssid);
449 params = kzalloc(params_size, GFP_KERNEL);
450 if (!params)
451 return -ENOMEM;
452 BUG_ON(params_size >= BRCMF_DCMD_SMLEN);
453
454 wl_iscan_prep(&params->params_le, ssid);
455
456 params->version = cpu_to_le32(BRCMF_ISCAN_REQ_VERSION);
457 params->action = cpu_to_le16(action);
458 params->scan_duration = cpu_to_le16(0);
459
460 err = brcmf_dev_iovar_setbuf(iscan->ndev, "iscan", params, params_size,
461 iscan->dcmd_buf, BRCMF_DCMD_SMLEN);
462 if (err) {
463 if (err == -EBUSY)
464 WL_INFO("system busy : iscan canceled\n");
465 else
466 WL_ERR("error (%d)\n", err);
467 }
468
469 kfree(params);
470 return err;
471}
472
473static s32 brcmf_do_iscan(struct brcmf_cfg80211_priv *cfg_priv)
474{
475 struct brcmf_cfg80211_iscan_ctrl *iscan = cfg_to_iscan(cfg_priv);
476 struct net_device *ndev = cfg_to_ndev(cfg_priv);
477 struct brcmf_ssid ssid;
478 s32 passive_scan;
479 s32 err = 0;
480
481 /* Broadcast scan by default */
482 memset(&ssid, 0, sizeof(ssid));
483
484 iscan->state = WL_ISCAN_STATE_SCANING;
485
486 passive_scan = cfg_priv->active_scan ? 0 : 1;
487 err = brcmf_exec_dcmd(cfg_to_ndev(cfg_priv), BRCMF_C_SET_PASSIVE_SCAN,
488 &passive_scan, sizeof(passive_scan));
489 if (err) {
490 WL_ERR("error (%d)\n", err);
491 return err;
492 }
493 brcmf_set_mpc(ndev, 0);
494 cfg_priv->iscan_kickstart = true;
495 err = brcmf_run_iscan(iscan, &ssid, BRCMF_SCAN_ACTION_START);
496 if (err) {
497 brcmf_set_mpc(ndev, 1);
498 cfg_priv->iscan_kickstart = false;
499 return err;
500 }
501 mod_timer(&iscan->timer, jiffies + iscan->timer_ms * HZ / 1000);
502 iscan->timer_on = 1;
503 return err;
504}
505
506static s32
507__brcmf_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
508 struct cfg80211_scan_request *request,
509 struct cfg80211_ssid *this_ssid)
510{
511 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
512 struct cfg80211_ssid *ssids;
513 struct brcmf_cfg80211_scan_req *sr = cfg_priv->scan_req_int;
514 s32 passive_scan;
515 bool iscan_req;
516 bool spec_scan;
517 s32 err = 0;
518 u32 SSID_len;
519
520 if (test_bit(WL_STATUS_SCANNING, &cfg_priv->status)) {
521 WL_ERR("Scanning already : status (%lu)\n", cfg_priv->status);
522 return -EAGAIN;
523 }
524 if (test_bit(WL_STATUS_SCAN_ABORTING, &cfg_priv->status)) {
525 WL_ERR("Scanning being aborted : status (%lu)\n",
526 cfg_priv->status);
527 return -EAGAIN;
528 }
529 if (test_bit(WL_STATUS_CONNECTING, &cfg_priv->status)) {
530 WL_ERR("Connecting : status (%lu)\n",
531 cfg_priv->status);
532 return -EAGAIN;
533 }
534
535 iscan_req = false;
536 spec_scan = false;
537 if (request) {
538 /* scan bss */
539 ssids = request->ssids;
540 if (cfg_priv->iscan_on && (!ssids || !ssids->ssid_len))
541 iscan_req = true;
542 } else {
543 /* scan in ibss */
544 /* we don't do iscan in ibss */
545 ssids = this_ssid;
546 }
547
548 cfg_priv->scan_request = request;
549 set_bit(WL_STATUS_SCANNING, &cfg_priv->status);
550 if (iscan_req) {
551 err = brcmf_do_iscan(cfg_priv);
552 if (!err)
553 return err;
554 else
555 goto scan_out;
556 } else {
557 WL_SCAN("ssid \"%s\", ssid_len (%d)\n",
558 ssids->ssid, ssids->ssid_len);
559 memset(&sr->ssid_le, 0, sizeof(sr->ssid_le));
560 SSID_len = min_t(u8, sizeof(sr->ssid_le.SSID), ssids->ssid_len);
561 sr->ssid_le.SSID_len = cpu_to_le32(0);
562 if (SSID_len) {
563 memcpy(sr->ssid_le.SSID, ssids->ssid, SSID_len);
564 sr->ssid_le.SSID_len = cpu_to_le32(SSID_len);
565 spec_scan = true;
566 } else {
567 WL_SCAN("Broadcast scan\n");
568 }
569
570 passive_scan = cfg_priv->active_scan ? 0 : 1;
571 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_PASSIVE_SCAN,
572 &passive_scan, sizeof(passive_scan));
573 if (err) {
574 WL_ERR("WLC_SET_PASSIVE_SCAN error (%d)\n", err);
575 goto scan_out;
576 }
577 brcmf_set_mpc(ndev, 0);
578 err = brcmf_exec_dcmd(ndev, BRCMF_C_SCAN, &sr->ssid_le,
579 sizeof(sr->ssid_le));
580 if (err) {
581 if (err == -EBUSY)
582 WL_INFO("system busy : scan for \"%s\" "
583 "canceled\n", sr->ssid_le.SSID);
584 else
585 WL_ERR("WLC_SCAN error (%d)\n", err);
586
587 brcmf_set_mpc(ndev, 1);
588 goto scan_out;
589 }
590 }
591
592 return 0;
593
594scan_out:
595 clear_bit(WL_STATUS_SCANNING, &cfg_priv->status);
596 cfg_priv->scan_request = NULL;
597 return err;
598}
599
600static s32
601brcmf_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
602 struct cfg80211_scan_request *request)
603{
604 s32 err = 0;
605
606 WL_TRACE("Enter\n");
607
608 if (!check_sys_up(wiphy))
609 return -EIO;
610
611 err = __brcmf_cfg80211_scan(wiphy, ndev, request, NULL);
612 if (err)
613 WL_ERR("scan error (%d)\n", err);
614
615 WL_TRACE("Exit\n");
616 return err;
617}
618
619static s32 brcmf_set_rts(struct net_device *ndev, u32 rts_threshold)
620{
621 s32 err = 0;
622
623 err = brcmf_dev_intvar_set(ndev, "rtsthresh", rts_threshold);
624 if (err)
625 WL_ERR("Error (%d)\n", err);
626
627 return err;
628}
629
630static s32 brcmf_set_frag(struct net_device *ndev, u32 frag_threshold)
631{
632 s32 err = 0;
633
634 err = brcmf_dev_intvar_set(ndev, "fragthresh", frag_threshold);
635 if (err)
636 WL_ERR("Error (%d)\n", err);
637
638 return err;
639}
640
641static s32 brcmf_set_retry(struct net_device *ndev, u32 retry, bool l)
642{
643 s32 err = 0;
644 u32 cmd = (l ? BRCM_SET_LRL : BRCM_SET_SRL);
645
646 err = brcmf_exec_dcmd_u32(ndev, cmd, &retry);
647 if (err) {
648 WL_ERR("cmd (%d) , error (%d)\n", cmd, err);
649 return err;
650 }
651 return err;
652}
653
654static s32 brcmf_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed)
655{
656 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
657 struct net_device *ndev = cfg_to_ndev(cfg_priv);
658 s32 err = 0;
659
660 WL_TRACE("Enter\n");
661 if (!check_sys_up(wiphy))
662 return -EIO;
663
664 if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
665 (cfg_priv->conf->rts_threshold != wiphy->rts_threshold)) {
666 cfg_priv->conf->rts_threshold = wiphy->rts_threshold;
667 err = brcmf_set_rts(ndev, cfg_priv->conf->rts_threshold);
668 if (!err)
669 goto done;
670 }
671 if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
672 (cfg_priv->conf->frag_threshold != wiphy->frag_threshold)) {
673 cfg_priv->conf->frag_threshold = wiphy->frag_threshold;
674 err = brcmf_set_frag(ndev, cfg_priv->conf->frag_threshold);
675 if (!err)
676 goto done;
677 }
678 if (changed & WIPHY_PARAM_RETRY_LONG
679 && (cfg_priv->conf->retry_long != wiphy->retry_long)) {
680 cfg_priv->conf->retry_long = wiphy->retry_long;
681 err = brcmf_set_retry(ndev, cfg_priv->conf->retry_long, true);
682 if (!err)
683 goto done;
684 }
685 if (changed & WIPHY_PARAM_RETRY_SHORT
686 && (cfg_priv->conf->retry_short != wiphy->retry_short)) {
687 cfg_priv->conf->retry_short = wiphy->retry_short;
688 err = brcmf_set_retry(ndev, cfg_priv->conf->retry_short, false);
689 if (!err)
690 goto done;
691 }
692
693done:
694 WL_TRACE("Exit\n");
695 return err;
696}
697
698static void *brcmf_read_prof(struct brcmf_cfg80211_priv *cfg_priv, s32 item)
699{
700 switch (item) {
701 case WL_PROF_SEC:
702 return &cfg_priv->profile->sec;
703 case WL_PROF_BSSID:
704 return &cfg_priv->profile->bssid;
705 case WL_PROF_SSID:
706 return &cfg_priv->profile->ssid;
707 }
708 WL_ERR("invalid item (%d)\n", item);
709 return NULL;
710}
711
712static s32
713brcmf_update_prof(struct brcmf_cfg80211_priv *cfg_priv,
714 const struct brcmf_event_msg *e, void *data, s32 item)
715{
716 s32 err = 0;
717 struct brcmf_ssid *ssid;
718
719 switch (item) {
720 case WL_PROF_SSID:
721 ssid = (struct brcmf_ssid *) data;
722 memset(cfg_priv->profile->ssid.SSID, 0,
723 sizeof(cfg_priv->profile->ssid.SSID));
724 memcpy(cfg_priv->profile->ssid.SSID,
725 ssid->SSID, ssid->SSID_len);
726 cfg_priv->profile->ssid.SSID_len = ssid->SSID_len;
727 break;
728 case WL_PROF_BSSID:
729 if (data)
730 memcpy(cfg_priv->profile->bssid, data, ETH_ALEN);
731 else
732 memset(cfg_priv->profile->bssid, 0, ETH_ALEN);
733 break;
734 case WL_PROF_SEC:
735 memcpy(&cfg_priv->profile->sec, data,
736 sizeof(cfg_priv->profile->sec));
737 break;
738 case WL_PROF_BEACONINT:
739 cfg_priv->profile->beacon_interval = *(u16 *)data;
740 break;
741 case WL_PROF_DTIMPERIOD:
742 cfg_priv->profile->dtim_period = *(u8 *)data;
743 break;
744 default:
745 WL_ERR("unsupported item (%d)\n", item);
746 err = -EOPNOTSUPP;
747 break;
748 }
749
750 return err;
751}
752
753static void brcmf_init_prof(struct brcmf_cfg80211_profile *prof)
754{
755 memset(prof, 0, sizeof(*prof));
756}
757
758static void brcmf_ch_to_chanspec(int ch, struct brcmf_join_params *join_params,
759 size_t *join_params_size)
760{
761 u16 chanspec = 0;
762
763 if (ch != 0) {
764 if (ch <= CH_MAX_2G_CHANNEL)
765 chanspec |= WL_CHANSPEC_BAND_2G;
766 else
767 chanspec |= WL_CHANSPEC_BAND_5G;
768
769 chanspec |= WL_CHANSPEC_BW_20;
770 chanspec |= WL_CHANSPEC_CTL_SB_NONE;
771
772 *join_params_size += BRCMF_ASSOC_PARAMS_FIXED_SIZE +
773 sizeof(u16);
774
775 chanspec |= (ch & WL_CHANSPEC_CHAN_MASK);
776 join_params->params_le.chanspec_list[0] = cpu_to_le16(chanspec);
777 join_params->params_le.chanspec_num = cpu_to_le32(1);
778
779 WL_CONN("join_params->params.chanspec_list[0]= %#X,"
780 "channel %d, chanspec %#X\n",
781 chanspec, ch, chanspec);
782 }
783}
784
785static void brcmf_link_down(struct brcmf_cfg80211_priv *cfg_priv)
786{
787 struct net_device *ndev = NULL;
788 s32 err = 0;
789
790 WL_TRACE("Enter\n");
791
792 if (cfg_priv->link_up) {
793 ndev = cfg_to_ndev(cfg_priv);
794 WL_INFO("Call WLC_DISASSOC to stop excess roaming\n ");
795 err = brcmf_exec_dcmd(ndev, BRCMF_C_DISASSOC, NULL, 0);
796 if (err)
797 WL_ERR("WLC_DISASSOC failed (%d)\n", err);
798 cfg_priv->link_up = false;
799 }
800 WL_TRACE("Exit\n");
801}
802
803static s32
804brcmf_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *ndev,
805 struct cfg80211_ibss_params *params)
806{
807 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
808 struct brcmf_join_params join_params;
809 size_t join_params_size = 0;
810 s32 err = 0;
811 s32 wsec = 0;
812 s32 bcnprd;
813 struct brcmf_ssid ssid;
814
815 WL_TRACE("Enter\n");
816 if (!check_sys_up(wiphy))
817 return -EIO;
818
819 if (params->ssid)
820 WL_CONN("SSID: %s\n", params->ssid);
821 else {
822 WL_CONN("SSID: NULL, Not supported\n");
823 return -EOPNOTSUPP;
824 }
825
826 set_bit(WL_STATUS_CONNECTING, &cfg_priv->status);
827
828 if (params->bssid)
829 WL_CONN("BSSID: %02X %02X %02X %02X %02X %02X\n",
830 params->bssid[0], params->bssid[1], params->bssid[2],
831 params->bssid[3], params->bssid[4], params->bssid[5]);
832 else
833 WL_CONN("No BSSID specified\n");
834
835 if (params->channel)
836 WL_CONN("channel: %d\n", params->channel->center_freq);
837 else
838 WL_CONN("no channel specified\n");
839
840 if (params->channel_fixed)
841 WL_CONN("fixed channel required\n");
842 else
843 WL_CONN("no fixed channel required\n");
844
845 if (params->ie && params->ie_len)
846 WL_CONN("ie len: %d\n", params->ie_len);
847 else
848 WL_CONN("no ie specified\n");
849
850 if (params->beacon_interval)
851 WL_CONN("beacon interval: %d\n", params->beacon_interval);
852 else
853 WL_CONN("no beacon interval specified\n");
854
855 if (params->basic_rates)
856 WL_CONN("basic rates: %08X\n", params->basic_rates);
857 else
858 WL_CONN("no basic rates specified\n");
859
860 if (params->privacy)
861 WL_CONN("privacy required\n");
862 else
863 WL_CONN("no privacy required\n");
864
865 /* Configure Privacy for starter */
866 if (params->privacy)
867 wsec |= WEP_ENABLED;
868
869 err = brcmf_dev_intvar_set(ndev, "wsec", wsec);
870 if (err) {
871 WL_ERR("wsec failed (%d)\n", err);
872 goto done;
873 }
874
875 /* Configure Beacon Interval for starter */
876 if (params->beacon_interval)
877 bcnprd = params->beacon_interval;
878 else
879 bcnprd = 100;
880
881 err = brcmf_exec_dcmd_u32(ndev, BRCM_SET_BCNPRD, &bcnprd);
882 if (err) {
883 WL_ERR("WLC_SET_BCNPRD failed (%d)\n", err);
884 goto done;
885 }
886
887 /* Configure required join parameter */
888 memset(&join_params, 0, sizeof(struct brcmf_join_params));
889
890 /* SSID */
891 ssid.SSID_len = min_t(u32, params->ssid_len, 32);
892 memcpy(ssid.SSID, params->ssid, ssid.SSID_len);
893 memcpy(join_params.ssid_le.SSID, params->ssid, ssid.SSID_len);
894 join_params.ssid_le.SSID_len = cpu_to_le32(ssid.SSID_len);
895 join_params_size = sizeof(join_params.ssid_le);
896 brcmf_update_prof(cfg_priv, NULL, &ssid, WL_PROF_SSID);
897
898 /* BSSID */
899 if (params->bssid) {
900 memcpy(join_params.params_le.bssid, params->bssid, ETH_ALEN);
901 join_params_size = sizeof(join_params.ssid_le) +
902 BRCMF_ASSOC_PARAMS_FIXED_SIZE;
903 } else {
904 memcpy(join_params.params_le.bssid, ether_bcast, ETH_ALEN);
905 }
906
907 brcmf_update_prof(cfg_priv, NULL,
908 &join_params.params_le.bssid, WL_PROF_BSSID);
909
910 /* Channel */
911 if (params->channel) {
912 u32 target_channel;
913
914 cfg_priv->channel =
915 ieee80211_frequency_to_channel(
916 params->channel->center_freq);
917 if (params->channel_fixed) {
918 /* adding chanspec */
919 brcmf_ch_to_chanspec(cfg_priv->channel,
920 &join_params, &join_params_size);
921 }
922
923 /* set channel for starter */
924 target_channel = cfg_priv->channel;
925 err = brcmf_exec_dcmd_u32(ndev, BRCM_SET_CHANNEL,
926 &target_channel);
927 if (err) {
928 WL_ERR("WLC_SET_CHANNEL failed (%d)\n", err);
929 goto done;
930 }
931 } else
932 cfg_priv->channel = 0;
933
934 cfg_priv->ibss_starter = false;
935
936
937 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_SSID,
938 &join_params, join_params_size);
939 if (err) {
940 WL_ERR("WLC_SET_SSID failed (%d)\n", err);
941 goto done;
942 }
943
944done:
945 if (err)
946 clear_bit(WL_STATUS_CONNECTING, &cfg_priv->status);
947 WL_TRACE("Exit\n");
948 return err;
949}
950
951static s32
952brcmf_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *ndev)
953{
954 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
955 s32 err = 0;
956
957 WL_TRACE("Enter\n");
958 if (!check_sys_up(wiphy))
959 return -EIO;
960
961 brcmf_link_down(cfg_priv);
962
963 WL_TRACE("Exit\n");
964
965 return err;
966}
967
968static s32 brcmf_set_wpa_version(struct net_device *ndev,
969 struct cfg80211_connect_params *sme)
970{
971 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
972 struct brcmf_cfg80211_security *sec;
973 s32 val = 0;
974 s32 err = 0;
975
976 if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_1)
977 val = WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED;
978 else if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_2)
979 val = WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED;
980 else
981 val = WPA_AUTH_DISABLED;
982 WL_CONN("setting wpa_auth to 0x%0x\n", val);
983 err = brcmf_dev_intvar_set(ndev, "wpa_auth", val);
984 if (err) {
985 WL_ERR("set wpa_auth failed (%d)\n", err);
986 return err;
987 }
988 sec = brcmf_read_prof(cfg_priv, WL_PROF_SEC);
989 sec->wpa_versions = sme->crypto.wpa_versions;
990 return err;
991}
992
993static s32 brcmf_set_auth_type(struct net_device *ndev,
994 struct cfg80211_connect_params *sme)
995{
996 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
997 struct brcmf_cfg80211_security *sec;
998 s32 val = 0;
999 s32 err = 0;
1000
1001 switch (sme->auth_type) {
1002 case NL80211_AUTHTYPE_OPEN_SYSTEM:
1003 val = 0;
1004 WL_CONN("open system\n");
1005 break;
1006 case NL80211_AUTHTYPE_SHARED_KEY:
1007 val = 1;
1008 WL_CONN("shared key\n");
1009 break;
1010 case NL80211_AUTHTYPE_AUTOMATIC:
1011 val = 2;
1012 WL_CONN("automatic\n");
1013 break;
1014 case NL80211_AUTHTYPE_NETWORK_EAP:
1015 WL_CONN("network eap\n");
1016 default:
1017 val = 2;
1018 WL_ERR("invalid auth type (%d)\n", sme->auth_type);
1019 break;
1020 }
1021
1022 err = brcmf_dev_intvar_set(ndev, "auth", val);
1023 if (err) {
1024 WL_ERR("set auth failed (%d)\n", err);
1025 return err;
1026 }
1027 sec = brcmf_read_prof(cfg_priv, WL_PROF_SEC);
1028 sec->auth_type = sme->auth_type;
1029 return err;
1030}
1031
1032static s32
1033brcmf_set_set_cipher(struct net_device *ndev,
1034 struct cfg80211_connect_params *sme)
1035{
1036 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
1037 struct brcmf_cfg80211_security *sec;
1038 s32 pval = 0;
1039 s32 gval = 0;
1040 s32 err = 0;
1041
1042 if (sme->crypto.n_ciphers_pairwise) {
1043 switch (sme->crypto.ciphers_pairwise[0]) {
1044 case WLAN_CIPHER_SUITE_WEP40:
1045 case WLAN_CIPHER_SUITE_WEP104:
1046 pval = WEP_ENABLED;
1047 break;
1048 case WLAN_CIPHER_SUITE_TKIP:
1049 pval = TKIP_ENABLED;
1050 break;
1051 case WLAN_CIPHER_SUITE_CCMP:
1052 pval = AES_ENABLED;
1053 break;
1054 case WLAN_CIPHER_SUITE_AES_CMAC:
1055 pval = AES_ENABLED;
1056 break;
1057 default:
1058 WL_ERR("invalid cipher pairwise (%d)\n",
1059 sme->crypto.ciphers_pairwise[0]);
1060 return -EINVAL;
1061 }
1062 }
1063 if (sme->crypto.cipher_group) {
1064 switch (sme->crypto.cipher_group) {
1065 case WLAN_CIPHER_SUITE_WEP40:
1066 case WLAN_CIPHER_SUITE_WEP104:
1067 gval = WEP_ENABLED;
1068 break;
1069 case WLAN_CIPHER_SUITE_TKIP:
1070 gval = TKIP_ENABLED;
1071 break;
1072 case WLAN_CIPHER_SUITE_CCMP:
1073 gval = AES_ENABLED;
1074 break;
1075 case WLAN_CIPHER_SUITE_AES_CMAC:
1076 gval = AES_ENABLED;
1077 break;
1078 default:
1079 WL_ERR("invalid cipher group (%d)\n",
1080 sme->crypto.cipher_group);
1081 return -EINVAL;
1082 }
1083 }
1084
1085 WL_CONN("pval (%d) gval (%d)\n", pval, gval);
1086 err = brcmf_dev_intvar_set(ndev, "wsec", pval | gval);
1087 if (err) {
1088 WL_ERR("error (%d)\n", err);
1089 return err;
1090 }
1091
1092 sec = brcmf_read_prof(cfg_priv, WL_PROF_SEC);
1093 sec->cipher_pairwise = sme->crypto.ciphers_pairwise[0];
1094 sec->cipher_group = sme->crypto.cipher_group;
1095
1096 return err;
1097}
1098
1099static s32
1100brcmf_set_key_mgmt(struct net_device *ndev, struct cfg80211_connect_params *sme)
1101{
1102 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
1103 struct brcmf_cfg80211_security *sec;
1104 s32 val = 0;
1105 s32 err = 0;
1106
1107 if (sme->crypto.n_akm_suites) {
1108 err = brcmf_dev_intvar_get(ndev, "wpa_auth", &val);
1109 if (err) {
1110 WL_ERR("could not get wpa_auth (%d)\n", err);
1111 return err;
1112 }
1113 if (val & (WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED)) {
1114 switch (sme->crypto.akm_suites[0]) {
1115 case WLAN_AKM_SUITE_8021X:
1116 val = WPA_AUTH_UNSPECIFIED;
1117 break;
1118 case WLAN_AKM_SUITE_PSK:
1119 val = WPA_AUTH_PSK;
1120 break;
1121 default:
1122 WL_ERR("invalid cipher group (%d)\n",
1123 sme->crypto.cipher_group);
1124 return -EINVAL;
1125 }
1126 } else if (val & (WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED)) {
1127 switch (sme->crypto.akm_suites[0]) {
1128 case WLAN_AKM_SUITE_8021X:
1129 val = WPA2_AUTH_UNSPECIFIED;
1130 break;
1131 case WLAN_AKM_SUITE_PSK:
1132 val = WPA2_AUTH_PSK;
1133 break;
1134 default:
1135 WL_ERR("invalid cipher group (%d)\n",
1136 sme->crypto.cipher_group);
1137 return -EINVAL;
1138 }
1139 }
1140
1141 WL_CONN("setting wpa_auth to %d\n", val);
1142 err = brcmf_dev_intvar_set(ndev, "wpa_auth", val);
1143 if (err) {
1144 WL_ERR("could not set wpa_auth (%d)\n", err);
1145 return err;
1146 }
1147 }
1148 sec = brcmf_read_prof(cfg_priv, WL_PROF_SEC);
1149 sec->wpa_auth = sme->crypto.akm_suites[0];
1150
1151 return err;
1152}
1153
1154static s32
1155brcmf_set_set_sharedkey(struct net_device *ndev,
1156 struct cfg80211_connect_params *sme)
1157{
1158 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
1159 struct brcmf_cfg80211_security *sec;
1160 struct brcmf_wsec_key key;
1161 s32 val;
1162 s32 err = 0;
1163
1164 WL_CONN("key len (%d)\n", sme->key_len);
1165 if (sme->key_len) {
1166 sec = brcmf_read_prof(cfg_priv, WL_PROF_SEC);
1167 WL_CONN("wpa_versions 0x%x cipher_pairwise 0x%x\n",
1168 sec->wpa_versions, sec->cipher_pairwise);
1169 if (!
1170 (sec->wpa_versions & (NL80211_WPA_VERSION_1 |
1171 NL80211_WPA_VERSION_2))
1172&& (sec->cipher_pairwise & (WLAN_CIPHER_SUITE_WEP40 |
1173 WLAN_CIPHER_SUITE_WEP104))) {
1174 memset(&key, 0, sizeof(key));
1175 key.len = (u32) sme->key_len;
1176 key.index = (u32) sme->key_idx;
1177 if (key.len > sizeof(key.data)) {
1178 WL_ERR("Too long key length (%u)\n", key.len);
1179 return -EINVAL;
1180 }
1181 memcpy(key.data, sme->key, key.len);
1182 key.flags = BRCMF_PRIMARY_KEY;
1183 switch (sec->cipher_pairwise) {
1184 case WLAN_CIPHER_SUITE_WEP40:
1185 key.algo = CRYPTO_ALGO_WEP1;
1186 break;
1187 case WLAN_CIPHER_SUITE_WEP104:
1188 key.algo = CRYPTO_ALGO_WEP128;
1189 break;
1190 default:
1191 WL_ERR("Invalid algorithm (%d)\n",
1192 sme->crypto.ciphers_pairwise[0]);
1193 return -EINVAL;
1194 }
1195 /* Set the new key/index */
1196 WL_CONN("key length (%d) key index (%d) algo (%d)\n",
1197 key.len, key.index, key.algo);
1198 WL_CONN("key \"%s\"\n", key.data);
1199 err = send_key_to_dongle(ndev, &key);
1200 if (err)
1201 return err;
1202
1203 if (sec->auth_type == NL80211_AUTHTYPE_OPEN_SYSTEM) {
1204 WL_CONN("set auth_type to shared key\n");
1205 val = 1; /* shared key */
1206 err = brcmf_dev_intvar_set(ndev, "auth", val);
1207 if (err) {
1208 WL_ERR("set auth failed (%d)\n", err);
1209 return err;
1210 }
1211 }
1212 }
1213 }
1214 return err;
1215}
1216
1217static s32
1218brcmf_cfg80211_connect(struct wiphy *wiphy, struct net_device *ndev,
1219 struct cfg80211_connect_params *sme)
1220{
1221 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
1222 struct ieee80211_channel *chan = sme->channel;
1223 struct brcmf_join_params join_params;
1224 size_t join_params_size;
1225 struct brcmf_ssid ssid;
1226
1227 s32 err = 0;
1228
1229 WL_TRACE("Enter\n");
1230 if (!check_sys_up(wiphy))
1231 return -EIO;
1232
1233 if (!sme->ssid) {
1234 WL_ERR("Invalid ssid\n");
1235 return -EOPNOTSUPP;
1236 }
1237
1238 set_bit(WL_STATUS_CONNECTING, &cfg_priv->status);
1239
1240 if (chan) {
1241 cfg_priv->channel =
1242 ieee80211_frequency_to_channel(chan->center_freq);
1243 WL_CONN("channel (%d), center_req (%d)\n",
1244 cfg_priv->channel, chan->center_freq);
1245 } else
1246 cfg_priv->channel = 0;
1247
1248 WL_INFO("ie (%p), ie_len (%zd)\n", sme->ie, sme->ie_len);
1249
1250 err = brcmf_set_wpa_version(ndev, sme);
1251 if (err) {
1252 WL_ERR("wl_set_wpa_version failed (%d)\n", err);
1253 goto done;
1254 }
1255
1256 err = brcmf_set_auth_type(ndev, sme);
1257 if (err) {
1258 WL_ERR("wl_set_auth_type failed (%d)\n", err);
1259 goto done;
1260 }
1261
1262 err = brcmf_set_set_cipher(ndev, sme);
1263 if (err) {
1264 WL_ERR("wl_set_set_cipher failed (%d)\n", err);
1265 goto done;
1266 }
1267
1268 err = brcmf_set_key_mgmt(ndev, sme);
1269 if (err) {
1270 WL_ERR("wl_set_key_mgmt failed (%d)\n", err);
1271 goto done;
1272 }
1273
1274 err = brcmf_set_set_sharedkey(ndev, sme);
1275 if (err) {
1276 WL_ERR("wl_set_set_sharedkey failed (%d)\n", err);
1277 goto done;
1278 }
1279
1280 memset(&join_params, 0, sizeof(join_params));
1281 join_params_size = sizeof(join_params.ssid_le);
1282
1283 ssid.SSID_len = min_t(u32, sizeof(ssid.SSID), sme->ssid_len);
1284 memcpy(&join_params.ssid_le.SSID, sme->ssid, ssid.SSID_len);
1285 memcpy(&ssid.SSID, sme->ssid, ssid.SSID_len);
1286 join_params.ssid_le.SSID_len = cpu_to_le32(ssid.SSID_len);
1287 brcmf_update_prof(cfg_priv, NULL, &ssid, WL_PROF_SSID);
1288
1289 memcpy(join_params.params_le.bssid, ether_bcast, ETH_ALEN);
1290
1291 if (ssid.SSID_len < IEEE80211_MAX_SSID_LEN)
1292 WL_CONN("ssid \"%s\", len (%d)\n",
1293 ssid.SSID, ssid.SSID_len);
1294
1295 brcmf_ch_to_chanspec(cfg_priv->channel,
1296 &join_params, &join_params_size);
1297 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_SSID,
1298 &join_params, join_params_size);
1299 if (err)
1300 WL_ERR("WLC_SET_SSID failed (%d)\n", err);
1301
1302done:
1303 if (err)
1304 clear_bit(WL_STATUS_CONNECTING, &cfg_priv->status);
1305 WL_TRACE("Exit\n");
1306 return err;
1307}
1308
1309static s32
1310brcmf_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *ndev,
1311 u16 reason_code)
1312{
1313 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
1314 struct brcmf_scb_val_le scbval;
1315 s32 err = 0;
1316
1317 WL_TRACE("Enter. Reason code = %d\n", reason_code);
1318 if (!check_sys_up(wiphy))
1319 return -EIO;
1320
1321 clear_bit(WL_STATUS_CONNECTED, &cfg_priv->status);
1322
1323 memcpy(&scbval.ea, brcmf_read_prof(cfg_priv, WL_PROF_BSSID), ETH_ALEN);
1324 scbval.val = cpu_to_le32(reason_code);
1325 err = brcmf_exec_dcmd(ndev, BRCMF_C_DISASSOC, &scbval,
1326 sizeof(struct brcmf_scb_val_le));
1327 if (err)
1328 WL_ERR("error (%d)\n", err);
1329
1330 cfg_priv->link_up = false;
1331
1332 WL_TRACE("Exit\n");
1333 return err;
1334}
1335
1336static s32
1337brcmf_cfg80211_set_tx_power(struct wiphy *wiphy,
1338 enum nl80211_tx_power_setting type, s32 dbm)
1339{
1340
1341 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
1342 struct net_device *ndev = cfg_to_ndev(cfg_priv);
1343 u16 txpwrmw;
1344 s32 err = 0;
1345 s32 disable = 0;
1346
1347 WL_TRACE("Enter\n");
1348 if (!check_sys_up(wiphy))
1349 return -EIO;
1350
1351 switch (type) {
1352 case NL80211_TX_POWER_AUTOMATIC:
1353 break;
1354 case NL80211_TX_POWER_LIMITED:
1355 if (dbm < 0) {
1356 WL_ERR("TX_POWER_LIMITED - dbm is negative\n");
1357 err = -EINVAL;
1358 goto done;
1359 }
1360 break;
1361 case NL80211_TX_POWER_FIXED:
1362 if (dbm < 0) {
1363 WL_ERR("TX_POWER_FIXED - dbm is negative\n");
1364 err = -EINVAL;
1365 goto done;
1366 }
1367 break;
1368 }
1369 /* Make sure radio is off or on as far as software is concerned */
1370 disable = WL_RADIO_SW_DISABLE << 16;
1371 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_SET_RADIO, &disable);
1372 if (err)
1373 WL_ERR("WLC_SET_RADIO error (%d)\n", err);
1374
1375 if (dbm > 0xffff)
1376 txpwrmw = 0xffff;
1377 else
1378 txpwrmw = (u16) dbm;
1379 err = brcmf_dev_intvar_set(ndev, "qtxpower",
1380 (s32) (brcmu_mw_to_qdbm(txpwrmw)));
1381 if (err)
1382 WL_ERR("qtxpower error (%d)\n", err);
1383 cfg_priv->conf->tx_power = dbm;
1384
1385done:
1386 WL_TRACE("Exit\n");
1387 return err;
1388}
1389
1390static s32 brcmf_cfg80211_get_tx_power(struct wiphy *wiphy, s32 *dbm)
1391{
1392 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
1393 struct net_device *ndev = cfg_to_ndev(cfg_priv);
1394 s32 txpwrdbm;
1395 u8 result;
1396 s32 err = 0;
1397
1398 WL_TRACE("Enter\n");
1399 if (!check_sys_up(wiphy))
1400 return -EIO;
1401
1402 err = brcmf_dev_intvar_get(ndev, "qtxpower", &txpwrdbm);
1403 if (err) {
1404 WL_ERR("error (%d)\n", err);
1405 goto done;
1406 }
1407
1408 result = (u8) (txpwrdbm & ~WL_TXPWR_OVERRIDE);
1409 *dbm = (s32) brcmu_qdbm_to_mw(result);
1410
1411done:
1412 WL_TRACE("Exit\n");
1413 return err;
1414}
1415
1416static s32
1417brcmf_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *ndev,
1418 u8 key_idx, bool unicast, bool multicast)
1419{
1420 u32 index;
1421 u32 wsec;
1422 s32 err = 0;
1423
1424 WL_TRACE("Enter\n");
1425 WL_CONN("key index (%d)\n", key_idx);
1426 if (!check_sys_up(wiphy))
1427 return -EIO;
1428
1429 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_GET_WSEC, &wsec);
1430 if (err) {
1431 WL_ERR("WLC_GET_WSEC error (%d)\n", err);
1432 goto done;
1433 }
1434
1435 if (wsec & WEP_ENABLED) {
1436 /* Just select a new current key */
1437 index = key_idx;
1438 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_SET_KEY_PRIMARY,
1439 &index);
1440 if (err)
1441 WL_ERR("error (%d)\n", err);
1442 }
1443done:
1444 WL_TRACE("Exit\n");
1445 return err;
1446}
1447
1448static s32
1449brcmf_add_keyext(struct wiphy *wiphy, struct net_device *ndev,
1450 u8 key_idx, const u8 *mac_addr, struct key_params *params)
1451{
1452 struct brcmf_wsec_key key;
1453 struct brcmf_wsec_key_le key_le;
1454 s32 err = 0;
1455
1456 memset(&key, 0, sizeof(key));
1457 key.index = (u32) key_idx;
1458 /* Instead of bcast for ea address for default wep keys,
1459 driver needs it to be Null */
1460 if (!is_multicast_ether_addr(mac_addr))
1461 memcpy((char *)&key.ea, (void *)mac_addr, ETH_ALEN);
1462 key.len = (u32) params->key_len;
1463 /* check for key index change */
1464 if (key.len == 0) {
1465 /* key delete */
1466 err = send_key_to_dongle(ndev, &key);
1467 if (err)
1468 return err;
1469 } else {
1470 if (key.len > sizeof(key.data)) {
1471 WL_ERR("Invalid key length (%d)\n", key.len);
1472 return -EINVAL;
1473 }
1474
1475 WL_CONN("Setting the key index %d\n", key.index);
1476 memcpy(key.data, params->key, key.len);
1477
1478 if (params->cipher == WLAN_CIPHER_SUITE_TKIP) {
1479 u8 keybuf[8];
1480 memcpy(keybuf, &key.data[24], sizeof(keybuf));
1481 memcpy(&key.data[24], &key.data[16], sizeof(keybuf));
1482 memcpy(&key.data[16], keybuf, sizeof(keybuf));
1483 }
1484
1485 /* if IW_ENCODE_EXT_RX_SEQ_VALID set */
1486 if (params->seq && params->seq_len == 6) {
1487 /* rx iv */
1488 u8 *ivptr;
1489 ivptr = (u8 *) params->seq;
1490 key.rxiv.hi = (ivptr[5] << 24) | (ivptr[4] << 16) |
1491 (ivptr[3] << 8) | ivptr[2];
1492 key.rxiv.lo = (ivptr[1] << 8) | ivptr[0];
1493 key.iv_initialized = true;
1494 }
1495
1496 switch (params->cipher) {
1497 case WLAN_CIPHER_SUITE_WEP40:
1498 key.algo = CRYPTO_ALGO_WEP1;
1499 WL_CONN("WLAN_CIPHER_SUITE_WEP40\n");
1500 break;
1501 case WLAN_CIPHER_SUITE_WEP104:
1502 key.algo = CRYPTO_ALGO_WEP128;
1503 WL_CONN("WLAN_CIPHER_SUITE_WEP104\n");
1504 break;
1505 case WLAN_CIPHER_SUITE_TKIP:
1506 key.algo = CRYPTO_ALGO_TKIP;
1507 WL_CONN("WLAN_CIPHER_SUITE_TKIP\n");
1508 break;
1509 case WLAN_CIPHER_SUITE_AES_CMAC:
1510 key.algo = CRYPTO_ALGO_AES_CCM;
1511 WL_CONN("WLAN_CIPHER_SUITE_AES_CMAC\n");
1512 break;
1513 case WLAN_CIPHER_SUITE_CCMP:
1514 key.algo = CRYPTO_ALGO_AES_CCM;
1515 WL_CONN("WLAN_CIPHER_SUITE_CCMP\n");
1516 break;
1517 default:
1518 WL_ERR("Invalid cipher (0x%x)\n", params->cipher);
1519 return -EINVAL;
1520 }
1521 convert_key_from_CPU(&key, &key_le);
1522
1523 brcmf_netdev_wait_pend8021x(ndev);
1524 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_KEY, &key_le,
1525 sizeof(key_le));
1526 if (err) {
1527 WL_ERR("WLC_SET_KEY error (%d)\n", err);
1528 return err;
1529 }
1530 }
1531 return err;
1532}
1533
1534static s32
1535brcmf_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
1536 u8 key_idx, bool pairwise, const u8 *mac_addr,
1537 struct key_params *params)
1538{
1539 struct brcmf_wsec_key key;
1540 s32 val;
1541 s32 wsec;
1542 s32 err = 0;
1543 u8 keybuf[8];
1544
1545 WL_TRACE("Enter\n");
1546 WL_CONN("key index (%d)\n", key_idx);
1547 if (!check_sys_up(wiphy))
1548 return -EIO;
1549
1550 if (mac_addr) {
1551 WL_TRACE("Exit");
1552 return brcmf_add_keyext(wiphy, ndev, key_idx, mac_addr, params);
1553 }
1554 memset(&key, 0, sizeof(key));
1555
1556 key.len = (u32) params->key_len;
1557 key.index = (u32) key_idx;
1558
1559 if (key.len > sizeof(key.data)) {
1560 WL_ERR("Too long key length (%u)\n", key.len);
1561 err = -EINVAL;
1562 goto done;
1563 }
1564 memcpy(key.data, params->key, key.len);
1565
1566 key.flags = BRCMF_PRIMARY_KEY;
1567 switch (params->cipher) {
1568 case WLAN_CIPHER_SUITE_WEP40:
1569 key.algo = CRYPTO_ALGO_WEP1;
1570 WL_CONN("WLAN_CIPHER_SUITE_WEP40\n");
1571 break;
1572 case WLAN_CIPHER_SUITE_WEP104:
1573 key.algo = CRYPTO_ALGO_WEP128;
1574 WL_CONN("WLAN_CIPHER_SUITE_WEP104\n");
1575 break;
1576 case WLAN_CIPHER_SUITE_TKIP:
1577 memcpy(keybuf, &key.data[24], sizeof(keybuf));
1578 memcpy(&key.data[24], &key.data[16], sizeof(keybuf));
1579 memcpy(&key.data[16], keybuf, sizeof(keybuf));
1580 key.algo = CRYPTO_ALGO_TKIP;
1581 WL_CONN("WLAN_CIPHER_SUITE_TKIP\n");
1582 break;
1583 case WLAN_CIPHER_SUITE_AES_CMAC:
1584 key.algo = CRYPTO_ALGO_AES_CCM;
1585 WL_CONN("WLAN_CIPHER_SUITE_AES_CMAC\n");
1586 break;
1587 case WLAN_CIPHER_SUITE_CCMP:
1588 key.algo = CRYPTO_ALGO_AES_CCM;
1589 WL_CONN("WLAN_CIPHER_SUITE_CCMP\n");
1590 break;
1591 default:
1592 WL_ERR("Invalid cipher (0x%x)\n", params->cipher);
1593 err = -EINVAL;
1594 goto done;
1595 }
1596
1597 err = send_key_to_dongle(ndev, &key); /* Set the new key/index */
1598 if (err)
1599 goto done;
1600
1601 val = WEP_ENABLED;
1602 err = brcmf_dev_intvar_get(ndev, "wsec", &wsec);
1603 if (err) {
1604 WL_ERR("get wsec error (%d)\n", err);
1605 goto done;
1606 }
1607 wsec &= ~(WEP_ENABLED);
1608 wsec |= val;
1609 err = brcmf_dev_intvar_set(ndev, "wsec", wsec);
1610 if (err) {
1611 WL_ERR("set wsec error (%d)\n", err);
1612 goto done;
1613 }
1614
1615 val = 1; /* assume shared key. otherwise 0 */
1616 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_SET_AUTH, &val);
1617 if (err)
1618 WL_ERR("WLC_SET_AUTH error (%d)\n", err);
1619done:
1620 WL_TRACE("Exit\n");
1621 return err;
1622}
1623
1624static s32
1625brcmf_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev,
1626 u8 key_idx, bool pairwise, const u8 *mac_addr)
1627{
1628 struct brcmf_wsec_key key;
1629 s32 err = 0;
1630 s32 val;
1631 s32 wsec;
1632
1633 WL_TRACE("Enter\n");
1634 if (!check_sys_up(wiphy))
1635 return -EIO;
1636
1637 memset(&key, 0, sizeof(key));
1638
1639 key.index = (u32) key_idx;
1640 key.flags = BRCMF_PRIMARY_KEY;
1641 key.algo = CRYPTO_ALGO_OFF;
1642
1643 WL_CONN("key index (%d)\n", key_idx);
1644
1645 /* Set the new key/index */
1646 err = send_key_to_dongle(ndev, &key);
1647 if (err) {
1648 if (err == -EINVAL) {
1649 if (key.index >= DOT11_MAX_DEFAULT_KEYS)
1650 /* we ignore this key index in this case */
1651 WL_ERR("invalid key index (%d)\n", key_idx);
1652 }
1653 /* Ignore this error, may happen during DISASSOC */
1654 err = -EAGAIN;
1655 goto done;
1656 }
1657
1658 val = 0;
1659 err = brcmf_dev_intvar_get(ndev, "wsec", &wsec);
1660 if (err) {
1661 WL_ERR("get wsec error (%d)\n", err);
1662 /* Ignore this error, may happen during DISASSOC */
1663 err = -EAGAIN;
1664 goto done;
1665 }
1666 wsec &= ~(WEP_ENABLED);
1667 wsec |= val;
1668 err = brcmf_dev_intvar_set(ndev, "wsec", wsec);
1669 if (err) {
1670 WL_ERR("set wsec error (%d)\n", err);
1671 /* Ignore this error, may happen during DISASSOC */
1672 err = -EAGAIN;
1673 goto done;
1674 }
1675
1676 val = 0; /* assume open key. otherwise 1 */
1677 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_SET_AUTH, &val);
1678 if (err) {
1679 WL_ERR("WLC_SET_AUTH error (%d)\n", err);
1680 /* Ignore this error, may happen during DISASSOC */
1681 err = -EAGAIN;
1682 }
1683done:
1684 WL_TRACE("Exit\n");
1685 return err;
1686}
1687
1688static s32
1689brcmf_cfg80211_get_key(struct wiphy *wiphy, struct net_device *ndev,
1690 u8 key_idx, bool pairwise, const u8 *mac_addr, void *cookie,
1691 void (*callback) (void *cookie, struct key_params * params))
1692{
1693 struct key_params params;
1694 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
1695 struct brcmf_cfg80211_security *sec;
1696 s32 wsec;
1697 s32 err = 0;
1698
1699 WL_TRACE("Enter\n");
1700 WL_CONN("key index (%d)\n", key_idx);
1701 if (!check_sys_up(wiphy))
1702 return -EIO;
1703
1704 memset(&params, 0, sizeof(params));
1705
1706 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_GET_WSEC, &wsec);
1707 if (err) {
1708 WL_ERR("WLC_GET_WSEC error (%d)\n", err);
1709 /* Ignore this error, may happen during DISASSOC */
1710 err = -EAGAIN;
1711 goto done;
1712 }
1713 switch (wsec) {
1714 case WEP_ENABLED:
1715 sec = brcmf_read_prof(cfg_priv, WL_PROF_SEC);
1716 if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP40) {
1717 params.cipher = WLAN_CIPHER_SUITE_WEP40;
1718 WL_CONN("WLAN_CIPHER_SUITE_WEP40\n");
1719 } else if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP104) {
1720 params.cipher = WLAN_CIPHER_SUITE_WEP104;
1721 WL_CONN("WLAN_CIPHER_SUITE_WEP104\n");
1722 }
1723 break;
1724 case TKIP_ENABLED:
1725 params.cipher = WLAN_CIPHER_SUITE_TKIP;
1726 WL_CONN("WLAN_CIPHER_SUITE_TKIP\n");
1727 break;
1728 case AES_ENABLED:
1729 params.cipher = WLAN_CIPHER_SUITE_AES_CMAC;
1730 WL_CONN("WLAN_CIPHER_SUITE_AES_CMAC\n");
1731 break;
1732 default:
1733 WL_ERR("Invalid algo (0x%x)\n", wsec);
1734 err = -EINVAL;
1735 goto done;
1736 }
1737 callback(cookie, &params);
1738
1739done:
1740 WL_TRACE("Exit\n");
1741 return err;
1742}
1743
1744static s32
1745brcmf_cfg80211_config_default_mgmt_key(struct wiphy *wiphy,
1746 struct net_device *ndev, u8 key_idx)
1747{
1748 WL_INFO("Not supported\n");
1749
1750 return -EOPNOTSUPP;
1751}
1752
1753static s32
1754brcmf_cfg80211_get_station(struct wiphy *wiphy, struct net_device *ndev,
1755 u8 *mac, struct station_info *sinfo)
1756{
1757 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
1758 struct brcmf_scb_val_le scb_val;
1759 int rssi;
1760 s32 rate;
1761 s32 err = 0;
1762 u8 *bssid = brcmf_read_prof(cfg_priv, WL_PROF_BSSID);
1763
1764 WL_TRACE("Enter\n");
1765 if (!check_sys_up(wiphy))
1766 return -EIO;
1767
1768 if (memcmp(mac, bssid, ETH_ALEN)) {
1769 WL_ERR("Wrong Mac address cfg_mac-%X:%X:%X:%X:%X:%X"
1770 "wl_bssid-%X:%X:%X:%X:%X:%X\n",
1771 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
1772 bssid[0], bssid[1], bssid[2], bssid[3],
1773 bssid[4], bssid[5]);
1774 err = -ENOENT;
1775 goto done;
1776 }
1777
1778 /* Report the current tx rate */
1779 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_GET_RATE, &rate);
1780 if (err) {
1781 WL_ERR("Could not get rate (%d)\n", err);
1782 } else {
1783 sinfo->filled |= STATION_INFO_TX_BITRATE;
1784 sinfo->txrate.legacy = rate * 5;
1785 WL_CONN("Rate %d Mbps\n", rate / 2);
1786 }
1787
1788 if (test_bit(WL_STATUS_CONNECTED, &cfg_priv->status)) {
1789 scb_val.val = cpu_to_le32(0);
1790 err = brcmf_exec_dcmd(ndev, BRCMF_C_GET_RSSI, &scb_val,
1791 sizeof(struct brcmf_scb_val_le));
1792 if (err)
1793 WL_ERR("Could not get rssi (%d)\n", err);
1794
1795 rssi = le32_to_cpu(scb_val.val);
1796 sinfo->filled |= STATION_INFO_SIGNAL;
1797 sinfo->signal = rssi;
1798 WL_CONN("RSSI %d dBm\n", rssi);
1799 }
1800
1801done:
1802 WL_TRACE("Exit\n");
1803 return err;
1804}
1805
1806static s32
1807brcmf_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *ndev,
1808 bool enabled, s32 timeout)
1809{
1810 s32 pm;
1811 s32 err = 0;
1812 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
1813
1814 WL_TRACE("Enter\n");
1815
1816 /*
1817 * Powersave enable/disable request is coming from the
1818 * cfg80211 even before the interface is up. In that
1819 * scenario, driver will be storing the power save
1820 * preference in cfg_priv struct to apply this to
1821 * FW later while initializing the dongle
1822 */
1823 cfg_priv->pwr_save = enabled;
1824 if (!test_bit(WL_STATUS_READY, &cfg_priv->status)) {
1825
1826 WL_INFO("Device is not ready,"
1827 "storing the value in cfg_priv struct\n");
1828 goto done;
1829 }
1830
1831 pm = enabled ? PM_FAST : PM_OFF;
1832 WL_INFO("power save %s\n", (pm ? "enabled" : "disabled"));
1833
1834 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_SET_PM, &pm);
1835 if (err) {
1836 if (err == -ENODEV)
1837 WL_ERR("net_device is not ready yet\n");
1838 else
1839 WL_ERR("error (%d)\n", err);
1840 }
1841done:
1842 WL_TRACE("Exit\n");
1843 return err;
1844}
1845
1846static s32
1847brcmf_cfg80211_set_bitrate_mask(struct wiphy *wiphy, struct net_device *ndev,
1848 const u8 *addr,
1849 const struct cfg80211_bitrate_mask *mask)
1850{
1851 struct brcm_rateset_le rateset_le;
1852 s32 rate;
1853 s32 val;
1854 s32 err_bg;
1855 s32 err_a;
1856 u32 legacy;
1857 s32 err = 0;
1858
1859 WL_TRACE("Enter\n");
1860 if (!check_sys_up(wiphy))
1861 return -EIO;
1862
1863 /* addr param is always NULL. ignore it */
1864 /* Get current rateset */
1865 err = brcmf_exec_dcmd(ndev, BRCM_GET_CURR_RATESET, &rateset_le,
1866 sizeof(rateset_le));
1867 if (err) {
1868 WL_ERR("could not get current rateset (%d)\n", err);
1869 goto done;
1870 }
1871
1872 legacy = ffs(mask->control[IEEE80211_BAND_2GHZ].legacy & 0xFFFF);
1873 if (!legacy)
1874 legacy = ffs(mask->control[IEEE80211_BAND_5GHZ].legacy &
1875 0xFFFF);
1876
1877 val = wl_g_rates[legacy - 1].bitrate * 100000;
1878
1879 if (val < le32_to_cpu(rateset_le.count))
1880 /* Select rate by rateset index */
1881 rate = rateset_le.rates[val] & 0x7f;
1882 else
1883 /* Specified rate in bps */
1884 rate = val / 500000;
1885
1886 WL_CONN("rate %d mbps\n", rate / 2);
1887
1888 /*
1889 *
1890 * Set rate override,
1891 * Since the is a/b/g-blind, both a/bg_rate are enforced.
1892 */
1893 err_bg = brcmf_dev_intvar_set(ndev, "bg_rate", rate);
1894 err_a = brcmf_dev_intvar_set(ndev, "a_rate", rate);
1895 if (err_bg && err_a) {
1896 WL_ERR("could not set fixed rate (%d) (%d)\n", err_bg, err_a);
1897 err = err_bg | err_a;
1898 }
1899
1900done:
1901 WL_TRACE("Exit\n");
1902 return err;
1903}
1904
1905static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_priv *cfg_priv,
1906 struct brcmf_bss_info *bi)
1907{
1908 struct wiphy *wiphy = cfg_to_wiphy(cfg_priv);
1909 struct ieee80211_channel *notify_channel;
1910 struct cfg80211_bss *bss;
1911 struct ieee80211_supported_band *band;
1912 s32 err = 0;
1913 u16 channel;
1914 u32 freq;
1915 u64 notify_timestamp;
1916 u16 notify_capability;
1917 u16 notify_interval;
1918 u8 *notify_ie;
1919 size_t notify_ielen;
1920 s32 notify_signal;
1921
1922 if (le32_to_cpu(bi->length) > WL_BSS_INFO_MAX) {
1923 WL_ERR("Bss info is larger than buffer. Discarding\n");
1924 return 0;
1925 }
1926
1927 channel = bi->ctl_ch ? bi->ctl_ch :
1928 CHSPEC_CHANNEL(le16_to_cpu(bi->chanspec));
1929
1930 if (channel <= CH_MAX_2G_CHANNEL)
1931 band = wiphy->bands[IEEE80211_BAND_2GHZ];
1932 else
1933 band = wiphy->bands[IEEE80211_BAND_5GHZ];
1934
1935 freq = ieee80211_channel_to_frequency(channel, band->band);
1936 notify_channel = ieee80211_get_channel(wiphy, freq);
1937
1938 notify_timestamp = jiffies_to_msecs(jiffies)*1000; /* uSec */
1939 notify_capability = le16_to_cpu(bi->capability);
1940 notify_interval = le16_to_cpu(bi->beacon_period);
1941 notify_ie = (u8 *)bi + le16_to_cpu(bi->ie_offset);
1942 notify_ielen = le32_to_cpu(bi->ie_length);
1943 notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100;
1944
1945 WL_CONN("bssid: %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
1946 bi->BSSID[0], bi->BSSID[1], bi->BSSID[2],
1947 bi->BSSID[3], bi->BSSID[4], bi->BSSID[5]);
1948 WL_CONN("Channel: %d(%d)\n", channel, freq);
1949 WL_CONN("Capability: %X\n", notify_capability);
1950 WL_CONN("Beacon interval: %d\n", notify_interval);
1951 WL_CONN("Signal: %d\n", notify_signal);
1952 WL_CONN("notify_timestamp: %#018llx\n", notify_timestamp);
1953
1954 bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)bi->BSSID,
1955 notify_timestamp, notify_capability, notify_interval, notify_ie,
1956 notify_ielen, notify_signal, GFP_KERNEL);
1957
1958 if (!bss) {
1959 WL_ERR("cfg80211_inform_bss_frame error\n");
1960 return -EINVAL;
1961 }
1962
1963 return err;
1964}
1965
1966static s32 brcmf_inform_bss(struct brcmf_cfg80211_priv *cfg_priv)
1967{
1968 struct brcmf_scan_results *bss_list;
1969 struct brcmf_bss_info *bi = NULL; /* must be initialized */
1970 s32 err = 0;
1971 int i;
1972
1973 bss_list = cfg_priv->bss_list;
1974 if (bss_list->version != BRCMF_BSS_INFO_VERSION) {
1975 WL_ERR("Version %d != WL_BSS_INFO_VERSION\n",
1976 bss_list->version);
1977 return -EOPNOTSUPP;
1978 }
1979 WL_SCAN("scanned AP count (%d)\n", bss_list->count);
1980 for (i = 0; i < bss_list->count && i < WL_AP_MAX; i++) {
1981 bi = next_bss(bss_list, bi);
1982 err = brcmf_inform_single_bss(cfg_priv, bi);
1983 if (err)
1984 break;
1985 }
1986 return err;
1987}
1988
1989static s32 wl_inform_ibss(struct brcmf_cfg80211_priv *cfg_priv,
1990 struct net_device *ndev, const u8 *bssid)
1991{
1992 struct wiphy *wiphy = cfg_to_wiphy(cfg_priv);
1993 struct ieee80211_channel *notify_channel;
1994 struct brcmf_bss_info *bi = NULL;
1995 struct ieee80211_supported_band *band;
1996 u8 *buf = NULL;
1997 s32 err = 0;
1998 u16 channel;
1999 u32 freq;
2000 u64 notify_timestamp;
2001 u16 notify_capability;
2002 u16 notify_interval;
2003 u8 *notify_ie;
2004 size_t notify_ielen;
2005 s32 notify_signal;
2006
2007 WL_TRACE("Enter\n");
2008
2009 buf = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
2010 if (buf == NULL) {
2011 err = -ENOMEM;
2012 goto CleanUp;
2013 }
2014
2015 *(__le32 *)buf = cpu_to_le32(WL_BSS_INFO_MAX);
2016
2017 err = brcmf_exec_dcmd(ndev, BRCMF_C_GET_BSS_INFO, buf, WL_BSS_INFO_MAX);
2018 if (err) {
2019 WL_ERR("WLC_GET_BSS_INFO failed: %d\n", err);
2020 goto CleanUp;
2021 }
2022
2023 bi = (struct brcmf_bss_info *)(buf + 4);
2024
2025 channel = bi->ctl_ch ? bi->ctl_ch :
2026 CHSPEC_CHANNEL(le16_to_cpu(bi->chanspec));
2027
2028 if (channel <= CH_MAX_2G_CHANNEL)
2029 band = wiphy->bands[IEEE80211_BAND_2GHZ];
2030 else
2031 band = wiphy->bands[IEEE80211_BAND_5GHZ];
2032
2033 freq = ieee80211_channel_to_frequency(channel, band->band);
2034 notify_channel = ieee80211_get_channel(wiphy, freq);
2035
2036 notify_timestamp = jiffies_to_msecs(jiffies)*1000; /* uSec */
2037 notify_capability = le16_to_cpu(bi->capability);
2038 notify_interval = le16_to_cpu(bi->beacon_period);
2039 notify_ie = (u8 *)bi + le16_to_cpu(bi->ie_offset);
2040 notify_ielen = le32_to_cpu(bi->ie_length);
2041 notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100;
2042
2043 WL_CONN("channel: %d(%d)\n", channel, freq);
2044 WL_CONN("capability: %X\n", notify_capability);
2045 WL_CONN("beacon interval: %d\n", notify_interval);
2046 WL_CONN("signal: %d\n", notify_signal);
2047 WL_CONN("notify_timestamp: %#018llx\n", notify_timestamp);
2048
2049 cfg80211_inform_bss(wiphy, notify_channel, bssid,
2050 notify_timestamp, notify_capability, notify_interval,
2051 notify_ie, notify_ielen, notify_signal, GFP_KERNEL);
2052
2053CleanUp:
2054
2055 kfree(buf);
2056
2057 WL_TRACE("Exit\n");
2058
2059 return err;
2060}
2061
2062static bool brcmf_is_ibssmode(struct brcmf_cfg80211_priv *cfg_priv)
2063{
2064 return cfg_priv->conf->mode == WL_MODE_IBSS;
2065}
2066
2067static s32 brcmf_update_bss_info(struct brcmf_cfg80211_priv *cfg_priv)
2068{
2069 struct brcmf_bss_info *bi;
2070 struct brcmf_ssid *ssid;
2071 struct brcmu_tlv *tim;
2072 u16 beacon_interval;
2073 u8 dtim_period;
2074 size_t ie_len;
2075 u8 *ie;
2076 s32 err = 0;
2077
2078 WL_TRACE("Enter\n");
2079 if (brcmf_is_ibssmode(cfg_priv))
2080 return err;
2081
2082 ssid = (struct brcmf_ssid *)brcmf_read_prof(cfg_priv, WL_PROF_SSID);
2083
2084 *(__le32 *)cfg_priv->extra_buf = cpu_to_le32(WL_EXTRA_BUF_MAX);
2085 err = brcmf_exec_dcmd(cfg_to_ndev(cfg_priv), BRCMF_C_GET_BSS_INFO,
2086 cfg_priv->extra_buf, WL_EXTRA_BUF_MAX);
2087 if (err) {
2088 WL_ERR("Could not get bss info %d\n", err);
2089 goto update_bss_info_out;
2090 }
2091
2092 bi = (struct brcmf_bss_info *)(cfg_priv->extra_buf + 4);
2093 err = brcmf_inform_single_bss(cfg_priv, bi);
2094 if (err)
2095 goto update_bss_info_out;
2096
2097 ie = ((u8 *)bi) + le16_to_cpu(bi->ie_offset);
2098 ie_len = le32_to_cpu(bi->ie_length);
2099 beacon_interval = le16_to_cpu(bi->beacon_period);
2100
2101 tim = brcmu_parse_tlvs(ie, ie_len, WLAN_EID_TIM);
2102 if (tim)
2103 dtim_period = tim->data[1];
2104 else {
2105 /*
2106 * active scan was done so we could not get dtim
2107 * information out of probe response.
2108 * so we speficially query dtim information to dongle.
2109 */
2110 u32 var;
2111 err = brcmf_dev_intvar_get(cfg_to_ndev(cfg_priv),
2112 "dtim_assoc", &var);
2113 if (err) {
2114 WL_ERR("wl dtim_assoc failed (%d)\n", err);
2115 goto update_bss_info_out;
2116 }
2117 dtim_period = (u8)var;
2118 }
2119
2120 brcmf_update_prof(cfg_priv, NULL, &beacon_interval, WL_PROF_BEACONINT);
2121 brcmf_update_prof(cfg_priv, NULL, &dtim_period, WL_PROF_DTIMPERIOD);
2122
2123update_bss_info_out:
2124 WL_TRACE("Exit");
2125 return err;
2126}
2127
2128static void brcmf_term_iscan(struct brcmf_cfg80211_priv *cfg_priv)
2129{
2130 struct brcmf_cfg80211_iscan_ctrl *iscan = cfg_to_iscan(cfg_priv);
2131 struct brcmf_ssid ssid;
2132
2133 if (cfg_priv->iscan_on) {
2134 iscan->state = WL_ISCAN_STATE_IDLE;
2135
2136 if (iscan->timer_on) {
2137 del_timer_sync(&iscan->timer);
2138 iscan->timer_on = 0;
2139 }
2140
2141 cancel_work_sync(&iscan->work);
2142
2143 /* Abort iscan running in FW */
2144 memset(&ssid, 0, sizeof(ssid));
2145 brcmf_run_iscan(iscan, &ssid, WL_SCAN_ACTION_ABORT);
2146 }
2147}
2148
2149static void brcmf_notify_iscan_complete(struct brcmf_cfg80211_iscan_ctrl *iscan,
2150 bool aborted)
2151{
2152 struct brcmf_cfg80211_priv *cfg_priv = iscan_to_cfg(iscan);
2153 struct net_device *ndev = cfg_to_ndev(cfg_priv);
2154
2155 if (!test_and_clear_bit(WL_STATUS_SCANNING, &cfg_priv->status)) {
2156 WL_ERR("Scan complete while device not scanning\n");
2157 return;
2158 }
2159 if (cfg_priv->scan_request) {
2160 WL_SCAN("ISCAN Completed scan: %s\n",
2161 aborted ? "Aborted" : "Done");
2162 cfg80211_scan_done(cfg_priv->scan_request, aborted);
2163 brcmf_set_mpc(ndev, 1);
2164 cfg_priv->scan_request = NULL;
2165 }
2166 cfg_priv->iscan_kickstart = false;
2167}
2168
2169static s32 brcmf_wakeup_iscan(struct brcmf_cfg80211_iscan_ctrl *iscan)
2170{
2171 if (iscan->state != WL_ISCAN_STATE_IDLE) {
2172 WL_SCAN("wake up iscan\n");
2173 schedule_work(&iscan->work);
2174 return 0;
2175 }
2176
2177 return -EIO;
2178}
2179
2180static s32
2181brcmf_get_iscan_results(struct brcmf_cfg80211_iscan_ctrl *iscan, u32 *status,
2182 struct brcmf_scan_results **bss_list)
2183{
2184 struct brcmf_iscan_results list;
2185 struct brcmf_scan_results *results;
2186 struct brcmf_scan_results_le *results_le;
2187 struct brcmf_iscan_results *list_buf;
2188 s32 err = 0;
2189
2190 memset(iscan->scan_buf, 0, WL_ISCAN_BUF_MAX);
2191 list_buf = (struct brcmf_iscan_results *)iscan->scan_buf;
2192 results = &list_buf->results;
2193 results_le = &list_buf->results_le;
2194 results->buflen = BRCMF_ISCAN_RESULTS_FIXED_SIZE;
2195 results->version = 0;
2196 results->count = 0;
2197
2198 memset(&list, 0, sizeof(list));
2199 list.results_le.buflen = cpu_to_le32(WL_ISCAN_BUF_MAX);
2200 err = brcmf_dev_iovar_getbuf(iscan->ndev, "iscanresults", &list,
2201 BRCMF_ISCAN_RESULTS_FIXED_SIZE,
2202 iscan->scan_buf, WL_ISCAN_BUF_MAX);
2203 if (err) {
2204 WL_ERR("error (%d)\n", err);
2205 return err;
2206 }
2207 results->buflen = le32_to_cpu(results_le->buflen);
2208 results->version = le32_to_cpu(results_le->version);
2209 results->count = le32_to_cpu(results_le->count);
2210 WL_SCAN("results->count = %d\n", results_le->count);
2211 WL_SCAN("results->buflen = %d\n", results_le->buflen);
2212 *status = le32_to_cpu(list_buf->status_le);
2213 WL_SCAN("status = %d\n", *status);
2214 *bss_list = results;
2215
2216 return err;
2217}
2218
2219static s32 brcmf_iscan_done(struct brcmf_cfg80211_priv *cfg_priv)
2220{
2221 struct brcmf_cfg80211_iscan_ctrl *iscan = cfg_priv->iscan;
2222 s32 err = 0;
2223
2224 iscan->state = WL_ISCAN_STATE_IDLE;
2225 brcmf_inform_bss(cfg_priv);
2226 brcmf_notify_iscan_complete(iscan, false);
2227
2228 return err;
2229}
2230
2231static s32 brcmf_iscan_pending(struct brcmf_cfg80211_priv *cfg_priv)
2232{
2233 struct brcmf_cfg80211_iscan_ctrl *iscan = cfg_priv->iscan;
2234 s32 err = 0;
2235
2236 /* Reschedule the timer */
2237 mod_timer(&iscan->timer, jiffies + iscan->timer_ms * HZ / 1000);
2238 iscan->timer_on = 1;
2239
2240 return err;
2241}
2242
2243static s32 brcmf_iscan_inprogress(struct brcmf_cfg80211_priv *cfg_priv)
2244{
2245 struct brcmf_cfg80211_iscan_ctrl *iscan = cfg_priv->iscan;
2246 s32 err = 0;
2247
2248 brcmf_inform_bss(cfg_priv);
2249 brcmf_run_iscan(iscan, NULL, BRCMF_SCAN_ACTION_CONTINUE);
2250 /* Reschedule the timer */
2251 mod_timer(&iscan->timer, jiffies + iscan->timer_ms * HZ / 1000);
2252 iscan->timer_on = 1;
2253
2254 return err;
2255}
2256
2257static s32 brcmf_iscan_aborted(struct brcmf_cfg80211_priv *cfg_priv)
2258{
2259 struct brcmf_cfg80211_iscan_ctrl *iscan = cfg_priv->iscan;
2260 s32 err = 0;
2261
2262 iscan->state = WL_ISCAN_STATE_IDLE;
2263 brcmf_notify_iscan_complete(iscan, true);
2264
2265 return err;
2266}
2267
2268static void brcmf_cfg80211_iscan_handler(struct work_struct *work)
2269{
2270 struct brcmf_cfg80211_iscan_ctrl *iscan =
2271 container_of(work, struct brcmf_cfg80211_iscan_ctrl,
2272 work);
2273 struct brcmf_cfg80211_priv *cfg_priv = iscan_to_cfg(iscan);
2274 struct brcmf_cfg80211_iscan_eloop *el = &iscan->el;
2275 u32 status = BRCMF_SCAN_RESULTS_PARTIAL;
2276
2277 if (iscan->timer_on) {
2278 del_timer_sync(&iscan->timer);
2279 iscan->timer_on = 0;
2280 }
2281
2282 if (brcmf_get_iscan_results(iscan, &status, &cfg_priv->bss_list)) {
2283 status = BRCMF_SCAN_RESULTS_ABORTED;
2284 WL_ERR("Abort iscan\n");
2285 }
2286
2287 el->handler[status](cfg_priv);
2288}
2289
2290static void brcmf_iscan_timer(unsigned long data)
2291{
2292 struct brcmf_cfg80211_iscan_ctrl *iscan =
2293 (struct brcmf_cfg80211_iscan_ctrl *)data;
2294
2295 if (iscan) {
2296 iscan->timer_on = 0;
2297 WL_SCAN("timer expired\n");
2298 brcmf_wakeup_iscan(iscan);
2299 }
2300}
2301
2302static s32 brcmf_invoke_iscan(struct brcmf_cfg80211_priv *cfg_priv)
2303{
2304 struct brcmf_cfg80211_iscan_ctrl *iscan = cfg_to_iscan(cfg_priv);
2305
2306 if (cfg_priv->iscan_on) {
2307 iscan->state = WL_ISCAN_STATE_IDLE;
2308 INIT_WORK(&iscan->work, brcmf_cfg80211_iscan_handler);
2309 }
2310
2311 return 0;
2312}
2313
2314static void brcmf_init_iscan_eloop(struct brcmf_cfg80211_iscan_eloop *el)
2315{
2316 memset(el, 0, sizeof(*el));
2317 el->handler[BRCMF_SCAN_RESULTS_SUCCESS] = brcmf_iscan_done;
2318 el->handler[BRCMF_SCAN_RESULTS_PARTIAL] = brcmf_iscan_inprogress;
2319 el->handler[BRCMF_SCAN_RESULTS_PENDING] = brcmf_iscan_pending;
2320 el->handler[BRCMF_SCAN_RESULTS_ABORTED] = brcmf_iscan_aborted;
2321 el->handler[BRCMF_SCAN_RESULTS_NO_MEM] = brcmf_iscan_aborted;
2322}
2323
2324static s32 brcmf_init_iscan(struct brcmf_cfg80211_priv *cfg_priv)
2325{
2326 struct brcmf_cfg80211_iscan_ctrl *iscan = cfg_to_iscan(cfg_priv);
2327 int err = 0;
2328
2329 if (cfg_priv->iscan_on) {
2330 iscan->ndev = cfg_to_ndev(cfg_priv);
2331 brcmf_init_iscan_eloop(&iscan->el);
2332 iscan->timer_ms = WL_ISCAN_TIMER_INTERVAL_MS;
2333 init_timer(&iscan->timer);
2334 iscan->timer.data = (unsigned long) iscan;
2335 iscan->timer.function = brcmf_iscan_timer;
2336 err = brcmf_invoke_iscan(cfg_priv);
2337 if (!err)
2338 iscan->data = cfg_priv;
2339 }
2340
2341 return err;
2342}
2343
2344static void brcmf_delay(u32 ms)
2345{
2346 if (ms < 1000 / HZ) {
2347 cond_resched();
2348 mdelay(ms);
2349 } else {
2350 msleep(ms);
2351 }
2352}
2353
2354static s32 brcmf_cfg80211_resume(struct wiphy *wiphy)
2355{
2356 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
2357
2358 /*
2359 * Check for WL_STATUS_READY before any function call which
2360 * could result is bus access. Don't block the resume for
2361 * any driver error conditions
2362 */
2363 WL_TRACE("Enter\n");
2364
2365 if (test_bit(WL_STATUS_READY, &cfg_priv->status))
2366 brcmf_invoke_iscan(wiphy_to_cfg(wiphy));
2367
2368 WL_TRACE("Exit\n");
2369 return 0;
2370}
2371
2372static s32 brcmf_cfg80211_suspend(struct wiphy *wiphy,
2373 struct cfg80211_wowlan *wow)
2374{
2375 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
2376 struct net_device *ndev = cfg_to_ndev(cfg_priv);
2377
2378 WL_TRACE("Enter\n");
2379
2380 /*
2381 * Check for WL_STATUS_READY before any function call which
2382 * could result is bus access. Don't block the suspend for
2383 * any driver error conditions
2384 */
2385
2386 /*
2387 * While going to suspend if associated with AP disassociate
2388 * from AP to save power while system is in suspended state
2389 */
2390 if ((test_bit(WL_STATUS_CONNECTED, &cfg_priv->status) ||
2391 test_bit(WL_STATUS_CONNECTING, &cfg_priv->status)) &&
2392 test_bit(WL_STATUS_READY, &cfg_priv->status)) {
2393 WL_INFO("Disassociating from AP"
2394 " while entering suspend state\n");
2395 brcmf_link_down(cfg_priv);
2396
2397 /*
2398 * Make sure WPA_Supplicant receives all the event
2399 * generated due to DISASSOC call to the fw to keep
2400 * the state fw and WPA_Supplicant state consistent
2401 */
2402 brcmf_delay(500);
2403 }
2404
2405 set_bit(WL_STATUS_SCAN_ABORTING, &cfg_priv->status);
2406 if (test_bit(WL_STATUS_READY, &cfg_priv->status))
2407 brcmf_term_iscan(cfg_priv);
2408
2409 if (cfg_priv->scan_request) {
2410 /* Indidate scan abort to cfg80211 layer */
2411 WL_INFO("Terminating scan in progress\n");
2412 cfg80211_scan_done(cfg_priv->scan_request, true);
2413 cfg_priv->scan_request = NULL;
2414 }
2415 clear_bit(WL_STATUS_SCANNING, &cfg_priv->status);
2416 clear_bit(WL_STATUS_SCAN_ABORTING, &cfg_priv->status);
2417
2418 /* Turn off watchdog timer */
2419 if (test_bit(WL_STATUS_READY, &cfg_priv->status)) {
2420 WL_INFO("Enable MPC\n");
2421 brcmf_set_mpc(ndev, 1);
2422 }
2423
2424 WL_TRACE("Exit\n");
2425
2426 return 0;
2427}
2428
2429static __used s32
2430brcmf_dev_bufvar_set(struct net_device *ndev, s8 *name, s8 *buf, s32 len)
2431{
2432 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
2433 u32 buflen;
2434
2435 buflen = brcmu_mkiovar(name, buf, len, cfg_priv->dcmd_buf,
2436 WL_DCMD_LEN_MAX);
2437 BUG_ON(!buflen);
2438
2439 return brcmf_exec_dcmd(ndev, BRCMF_C_SET_VAR, cfg_priv->dcmd_buf,
2440 buflen);
2441}
2442
2443static s32
2444brcmf_dev_bufvar_get(struct net_device *ndev, s8 *name, s8 *buf,
2445 s32 buf_len)
2446{
2447 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
2448 u32 len;
2449 s32 err = 0;
2450
2451 len = brcmu_mkiovar(name, NULL, 0, cfg_priv->dcmd_buf,
2452 WL_DCMD_LEN_MAX);
2453 BUG_ON(!len);
2454 err = brcmf_exec_dcmd(ndev, BRCMF_C_GET_VAR, cfg_priv->dcmd_buf,
2455 WL_DCMD_LEN_MAX);
2456 if (err) {
2457 WL_ERR("error (%d)\n", err);
2458 return err;
2459 }
2460 memcpy(buf, cfg_priv->dcmd_buf, buf_len);
2461
2462 return err;
2463}
2464
2465static __used s32
2466brcmf_update_pmklist(struct net_device *ndev,
2467 struct brcmf_cfg80211_pmk_list *pmk_list, s32 err)
2468{
2469 int i, j;
2470
2471 WL_CONN("No of elements %d\n", pmk_list->pmkids.npmkid);
2472 for (i = 0; i < pmk_list->pmkids.npmkid; i++) {
2473 WL_CONN("PMKID[%d]: %pM =\n", i,
2474 &pmk_list->pmkids.pmkid[i].BSSID);
2475 for (j = 0; j < WLAN_PMKID_LEN; j++)
2476 WL_CONN("%02x\n", pmk_list->pmkids.pmkid[i].PMKID[j]);
2477 }
2478
2479 if (!err)
2480 brcmf_dev_bufvar_set(ndev, "pmkid_info", (char *)pmk_list,
2481 sizeof(*pmk_list));
2482
2483 return err;
2484}
2485
2486static s32
2487brcmf_cfg80211_set_pmksa(struct wiphy *wiphy, struct net_device *ndev,
2488 struct cfg80211_pmksa *pmksa)
2489{
2490 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
2491 struct pmkid_list *pmkids = &cfg_priv->pmk_list->pmkids;
2492 s32 err = 0;
2493 int i;
2494
2495 WL_TRACE("Enter\n");
2496 if (!check_sys_up(wiphy))
2497 return -EIO;
2498
2499 for (i = 0; i < pmkids->npmkid; i++)
2500 if (!memcmp(pmksa->bssid, pmkids->pmkid[i].BSSID, ETH_ALEN))
2501 break;
2502 if (i < WL_NUM_PMKIDS_MAX) {
2503 memcpy(pmkids->pmkid[i].BSSID, pmksa->bssid, ETH_ALEN);
2504 memcpy(pmkids->pmkid[i].PMKID, pmksa->pmkid, WLAN_PMKID_LEN);
2505 if (i == pmkids->npmkid)
2506 pmkids->npmkid++;
2507 } else
2508 err = -EINVAL;
2509
2510 WL_CONN("set_pmksa,IW_PMKSA_ADD - PMKID: %pM =\n",
2511 pmkids->pmkid[pmkids->npmkid].BSSID);
2512 for (i = 0; i < WLAN_PMKID_LEN; i++)
2513 WL_CONN("%02x\n", pmkids->pmkid[pmkids->npmkid].PMKID[i]);
2514
2515 err = brcmf_update_pmklist(ndev, cfg_priv->pmk_list, err);
2516
2517 WL_TRACE("Exit\n");
2518 return err;
2519}
2520
2521static s32
2522brcmf_cfg80211_del_pmksa(struct wiphy *wiphy, struct net_device *ndev,
2523 struct cfg80211_pmksa *pmksa)
2524{
2525 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
2526 struct pmkid_list pmkid;
2527 s32 err = 0;
2528 int i;
2529
2530 WL_TRACE("Enter\n");
2531 if (!check_sys_up(wiphy))
2532 return -EIO;
2533
2534 memcpy(&pmkid.pmkid[0].BSSID, pmksa->bssid, ETH_ALEN);
2535 memcpy(&pmkid.pmkid[0].PMKID, pmksa->pmkid, WLAN_PMKID_LEN);
2536
2537 WL_CONN("del_pmksa,IW_PMKSA_REMOVE - PMKID: %pM =\n",
2538 &pmkid.pmkid[0].BSSID);
2539 for (i = 0; i < WLAN_PMKID_LEN; i++)
2540 WL_CONN("%02x\n", pmkid.pmkid[0].PMKID[i]);
2541
2542 for (i = 0; i < cfg_priv->pmk_list->pmkids.npmkid; i++)
2543 if (!memcmp
2544 (pmksa->bssid, &cfg_priv->pmk_list->pmkids.pmkid[i].BSSID,
2545 ETH_ALEN))
2546 break;
2547
2548 if ((cfg_priv->pmk_list->pmkids.npmkid > 0)
2549 && (i < cfg_priv->pmk_list->pmkids.npmkid)) {
2550 memset(&cfg_priv->pmk_list->pmkids.pmkid[i], 0,
2551 sizeof(struct pmkid));
2552 for (; i < (cfg_priv->pmk_list->pmkids.npmkid - 1); i++) {
2553 memcpy(&cfg_priv->pmk_list->pmkids.pmkid[i].BSSID,
2554 &cfg_priv->pmk_list->pmkids.pmkid[i + 1].BSSID,
2555 ETH_ALEN);
2556 memcpy(&cfg_priv->pmk_list->pmkids.pmkid[i].PMKID,
2557 &cfg_priv->pmk_list->pmkids.pmkid[i + 1].PMKID,
2558 WLAN_PMKID_LEN);
2559 }
2560 cfg_priv->pmk_list->pmkids.npmkid--;
2561 } else
2562 err = -EINVAL;
2563
2564 err = brcmf_update_pmklist(ndev, cfg_priv->pmk_list, err);
2565
2566 WL_TRACE("Exit\n");
2567 return err;
2568
2569}
2570
2571static s32
2572brcmf_cfg80211_flush_pmksa(struct wiphy *wiphy, struct net_device *ndev)
2573{
2574 struct brcmf_cfg80211_priv *cfg_priv = wiphy_to_cfg(wiphy);
2575 s32 err = 0;
2576
2577 WL_TRACE("Enter\n");
2578 if (!check_sys_up(wiphy))
2579 return -EIO;
2580
2581 memset(cfg_priv->pmk_list, 0, sizeof(*cfg_priv->pmk_list));
2582 err = brcmf_update_pmklist(ndev, cfg_priv->pmk_list, err);
2583
2584 WL_TRACE("Exit\n");
2585 return err;
2586
2587}
2588
2589static struct cfg80211_ops wl_cfg80211_ops = {
2590 .change_virtual_intf = brcmf_cfg80211_change_iface,
2591 .scan = brcmf_cfg80211_scan,
2592 .set_wiphy_params = brcmf_cfg80211_set_wiphy_params,
2593 .join_ibss = brcmf_cfg80211_join_ibss,
2594 .leave_ibss = brcmf_cfg80211_leave_ibss,
2595 .get_station = brcmf_cfg80211_get_station,
2596 .set_tx_power = brcmf_cfg80211_set_tx_power,
2597 .get_tx_power = brcmf_cfg80211_get_tx_power,
2598 .add_key = brcmf_cfg80211_add_key,
2599 .del_key = brcmf_cfg80211_del_key,
2600 .get_key = brcmf_cfg80211_get_key,
2601 .set_default_key = brcmf_cfg80211_config_default_key,
2602 .set_default_mgmt_key = brcmf_cfg80211_config_default_mgmt_key,
2603 .set_power_mgmt = brcmf_cfg80211_set_power_mgmt,
2604 .set_bitrate_mask = brcmf_cfg80211_set_bitrate_mask,
2605 .connect = brcmf_cfg80211_connect,
2606 .disconnect = brcmf_cfg80211_disconnect,
2607 .suspend = brcmf_cfg80211_suspend,
2608 .resume = brcmf_cfg80211_resume,
2609 .set_pmksa = brcmf_cfg80211_set_pmksa,
2610 .del_pmksa = brcmf_cfg80211_del_pmksa,
2611 .flush_pmksa = brcmf_cfg80211_flush_pmksa
2612};
2613
2614static s32 brcmf_mode_to_nl80211_iftype(s32 mode)
2615{
2616 s32 err = 0;
2617
2618 switch (mode) {
2619 case WL_MODE_BSS:
2620 return NL80211_IFTYPE_STATION;
2621 case WL_MODE_IBSS:
2622 return NL80211_IFTYPE_ADHOC;
2623 default:
2624 return NL80211_IFTYPE_UNSPECIFIED;
2625 }
2626
2627 return err;
2628}
2629
2630static struct wireless_dev *brcmf_alloc_wdev(s32 sizeof_iface,
2631 struct device *ndev)
2632{
2633 struct wireless_dev *wdev;
2634 s32 err = 0;
2635
2636 wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
2637 if (!wdev)
2638 return ERR_PTR(-ENOMEM);
2639
2640 wdev->wiphy =
2641 wiphy_new(&wl_cfg80211_ops,
2642 sizeof(struct brcmf_cfg80211_priv) + sizeof_iface);
2643 if (!wdev->wiphy) {
2644 WL_ERR("Couldn not allocate wiphy device\n");
2645 err = -ENOMEM;
2646 goto wiphy_new_out;
2647 }
2648 set_wiphy_dev(wdev->wiphy, ndev);
2649 wdev->wiphy->max_scan_ssids = WL_NUM_SCAN_MAX;
2650 wdev->wiphy->max_num_pmkids = WL_NUM_PMKIDS_MAX;
2651 wdev->wiphy->interface_modes =
2652 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
2653 wdev->wiphy->bands[IEEE80211_BAND_2GHZ] = &__wl_band_2ghz;
2654 wdev->wiphy->bands[IEEE80211_BAND_5GHZ] = &__wl_band_5ghz_a; /* Set
2655 * it as 11a by default.
2656 * This will be updated with
2657 * 11n phy tables in
2658 * "ifconfig up"
2659 * if phy has 11n capability
2660 */
2661 wdev->wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
2662 wdev->wiphy->cipher_suites = __wl_cipher_suites;
2663 wdev->wiphy->n_cipher_suites = ARRAY_SIZE(__wl_cipher_suites);
2664 wdev->wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT; /* enable power
2665 * save mode
2666 * by default
2667 */
2668 err = wiphy_register(wdev->wiphy);
2669 if (err < 0) {
2670 WL_ERR("Couldn not register wiphy device (%d)\n", err);
2671 goto wiphy_register_out;
2672 }
2673 return wdev;
2674
2675wiphy_register_out:
2676 wiphy_free(wdev->wiphy);
2677
2678wiphy_new_out:
2679 kfree(wdev);
2680
2681 return ERR_PTR(err);
2682}
2683
2684static void brcmf_free_wdev(struct brcmf_cfg80211_priv *cfg_priv)
2685{
2686 struct wireless_dev *wdev = cfg_priv->wdev;
2687
2688 if (!wdev) {
2689 WL_ERR("wdev is invalid\n");
2690 return;
2691 }
2692 wiphy_unregister(wdev->wiphy);
2693 wiphy_free(wdev->wiphy);
2694 kfree(wdev);
2695 cfg_priv->wdev = NULL;
2696}
2697
2698static bool brcmf_is_linkup(struct brcmf_cfg80211_priv *cfg_priv,
2699 const struct brcmf_event_msg *e)
2700{
2701 u32 event = be32_to_cpu(e->event_type);
2702 u32 status = be32_to_cpu(e->status);
2703
2704 if (event == BRCMF_E_SET_SSID && status == BRCMF_E_STATUS_SUCCESS) {
2705 WL_CONN("Processing set ssid\n");
2706 cfg_priv->link_up = true;
2707 return true;
2708 }
2709
2710 return false;
2711}
2712
2713static bool brcmf_is_linkdown(struct brcmf_cfg80211_priv *cfg_priv,
2714 const struct brcmf_event_msg *e)
2715{
2716 u32 event = be32_to_cpu(e->event_type);
2717 u16 flags = be16_to_cpu(e->flags);
2718
2719 if (event == BRCMF_E_LINK && (!(flags & BRCMF_EVENT_MSG_LINK))) {
2720 WL_CONN("Processing link down\n");
2721 return true;
2722 }
2723 return false;
2724}
2725
2726static bool brcmf_is_nonetwork(struct brcmf_cfg80211_priv *cfg_priv,
2727 const struct brcmf_event_msg *e)
2728{
2729 u32 event = be32_to_cpu(e->event_type);
2730 u32 status = be32_to_cpu(e->status);
2731
2732 if (event == BRCMF_E_LINK && status == BRCMF_E_STATUS_NO_NETWORKS) {
2733 WL_CONN("Processing Link %s & no network found\n",
2734 be16_to_cpu(e->flags) & BRCMF_EVENT_MSG_LINK ?
2735 "up" : "down");
2736 return true;
2737 }
2738
2739 if (event == BRCMF_E_SET_SSID && status != BRCMF_E_STATUS_SUCCESS) {
2740 WL_CONN("Processing connecting & no network found\n");
2741 return true;
2742 }
2743
2744 return false;
2745}
2746
2747static void brcmf_clear_assoc_ies(struct brcmf_cfg80211_priv *cfg_priv)
2748{
2749 struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg_priv);
2750
2751 kfree(conn_info->req_ie);
2752 conn_info->req_ie = NULL;
2753 conn_info->req_ie_len = 0;
2754 kfree(conn_info->resp_ie);
2755 conn_info->resp_ie = NULL;
2756 conn_info->resp_ie_len = 0;
2757}
2758
2759static s32 brcmf_get_assoc_ies(struct brcmf_cfg80211_priv *cfg_priv)
2760{
2761 struct net_device *ndev = cfg_to_ndev(cfg_priv);
2762 struct brcmf_cfg80211_assoc_ielen *assoc_info;
2763 struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg_priv);
2764 u32 req_len;
2765 u32 resp_len;
2766 s32 err = 0;
2767
2768 brcmf_clear_assoc_ies(cfg_priv);
2769
2770 err = brcmf_dev_bufvar_get(ndev, "assoc_info", cfg_priv->extra_buf,
2771 WL_ASSOC_INFO_MAX);
2772 if (err) {
2773 WL_ERR("could not get assoc info (%d)\n", err);
2774 return err;
2775 }
2776 assoc_info = (struct brcmf_cfg80211_assoc_ielen *)cfg_priv->extra_buf;
2777 req_len = assoc_info->req_len;
2778 resp_len = assoc_info->resp_len;
2779 if (req_len) {
2780 err = brcmf_dev_bufvar_get(ndev, "assoc_req_ies",
2781 cfg_priv->extra_buf,
2782 WL_ASSOC_INFO_MAX);
2783 if (err) {
2784 WL_ERR("could not get assoc req (%d)\n", err);
2785 return err;
2786 }
2787 conn_info->req_ie_len = req_len;
2788 conn_info->req_ie =
2789 kmemdup(cfg_priv->extra_buf, conn_info->req_ie_len,
2790 GFP_KERNEL);
2791 } else {
2792 conn_info->req_ie_len = 0;
2793 conn_info->req_ie = NULL;
2794 }
2795 if (resp_len) {
2796 err = brcmf_dev_bufvar_get(ndev, "assoc_resp_ies",
2797 cfg_priv->extra_buf,
2798 WL_ASSOC_INFO_MAX);
2799 if (err) {
2800 WL_ERR("could not get assoc resp (%d)\n", err);
2801 return err;
2802 }
2803 conn_info->resp_ie_len = resp_len;
2804 conn_info->resp_ie =
2805 kmemdup(cfg_priv->extra_buf, conn_info->resp_ie_len,
2806 GFP_KERNEL);
2807 } else {
2808 conn_info->resp_ie_len = 0;
2809 conn_info->resp_ie = NULL;
2810 }
2811 WL_CONN("req len (%d) resp len (%d)\n",
2812 conn_info->req_ie_len, conn_info->resp_ie_len);
2813
2814 return err;
2815}
2816
2817static s32
2818brcmf_bss_roaming_done(struct brcmf_cfg80211_priv *cfg_priv,
2819 struct net_device *ndev,
2820 const struct brcmf_event_msg *e)
2821{
2822 struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg_priv);
2823 struct wiphy *wiphy = cfg_to_wiphy(cfg_priv);
2824 struct brcmf_channel_info_le channel_le;
2825 struct ieee80211_channel *notify_channel;
2826 struct ieee80211_supported_band *band;
2827 u32 freq;
2828 s32 err = 0;
2829 u32 target_channel;
2830
2831 WL_TRACE("Enter\n");
2832
2833 brcmf_get_assoc_ies(cfg_priv);
2834 brcmf_update_prof(cfg_priv, NULL, &e->addr, WL_PROF_BSSID);
2835 brcmf_update_bss_info(cfg_priv);
2836
2837 brcmf_exec_dcmd(ndev, BRCMF_C_GET_CHANNEL, &channel_le,
2838 sizeof(channel_le));
2839
2840 target_channel = le32_to_cpu(channel_le.target_channel);
2841 WL_CONN("Roamed to channel %d\n", target_channel);
2842
2843 if (target_channel <= CH_MAX_2G_CHANNEL)
2844 band = wiphy->bands[IEEE80211_BAND_2GHZ];
2845 else
2846 band = wiphy->bands[IEEE80211_BAND_5GHZ];
2847
2848 freq = ieee80211_channel_to_frequency(target_channel, band->band);
2849 notify_channel = ieee80211_get_channel(wiphy, freq);
2850
2851 cfg80211_roamed(ndev, notify_channel,
2852 (u8 *)brcmf_read_prof(cfg_priv, WL_PROF_BSSID),
2853 conn_info->req_ie, conn_info->req_ie_len,
2854 conn_info->resp_ie, conn_info->resp_ie_len, GFP_KERNEL);
2855 WL_CONN("Report roaming result\n");
2856
2857 set_bit(WL_STATUS_CONNECTED, &cfg_priv->status);
2858 WL_TRACE("Exit\n");
2859 return err;
2860}
2861
2862static s32
2863brcmf_bss_connect_done(struct brcmf_cfg80211_priv *cfg_priv,
2864 struct net_device *ndev, const struct brcmf_event_msg *e,
2865 bool completed)
2866{
2867 struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg_priv);
2868 s32 err = 0;
2869
2870 WL_TRACE("Enter\n");
2871
2872 if (test_and_clear_bit(WL_STATUS_CONNECTING, &cfg_priv->status)) {
2873 if (completed) {
2874 brcmf_get_assoc_ies(cfg_priv);
2875 brcmf_update_prof(cfg_priv, NULL, &e->addr,
2876 WL_PROF_BSSID);
2877 brcmf_update_bss_info(cfg_priv);
2878 }
2879 cfg80211_connect_result(ndev,
2880 (u8 *)brcmf_read_prof(cfg_priv,
2881 WL_PROF_BSSID),
2882 conn_info->req_ie,
2883 conn_info->req_ie_len,
2884 conn_info->resp_ie,
2885 conn_info->resp_ie_len,
2886 completed ? WLAN_STATUS_SUCCESS :
2887 WLAN_STATUS_AUTH_TIMEOUT,
2888 GFP_KERNEL);
2889 if (completed)
2890 set_bit(WL_STATUS_CONNECTED, &cfg_priv->status);
2891 WL_CONN("Report connect result - connection %s\n",
2892 completed ? "succeeded" : "failed");
2893 }
2894 WL_TRACE("Exit\n");
2895 return err;
2896}
2897
2898static s32
2899brcmf_notify_connect_status(struct brcmf_cfg80211_priv *cfg_priv,
2900 struct net_device *ndev,
2901 const struct brcmf_event_msg *e, void *data)
2902{
2903 s32 err = 0;
2904
2905 if (brcmf_is_linkup(cfg_priv, e)) {
2906 WL_CONN("Linkup\n");
2907 if (brcmf_is_ibssmode(cfg_priv)) {
2908 brcmf_update_prof(cfg_priv, NULL, (void *)e->addr,
2909 WL_PROF_BSSID);
2910 wl_inform_ibss(cfg_priv, ndev, e->addr);
2911 cfg80211_ibss_joined(ndev, e->addr, GFP_KERNEL);
2912 clear_bit(WL_STATUS_CONNECTING, &cfg_priv->status);
2913 set_bit(WL_STATUS_CONNECTED, &cfg_priv->status);
2914 } else
2915 brcmf_bss_connect_done(cfg_priv, ndev, e, true);
2916 } else if (brcmf_is_linkdown(cfg_priv, e)) {
2917 WL_CONN("Linkdown\n");
2918 if (brcmf_is_ibssmode(cfg_priv)) {
2919 clear_bit(WL_STATUS_CONNECTING, &cfg_priv->status);
2920 if (test_and_clear_bit(WL_STATUS_CONNECTED,
2921 &cfg_priv->status))
2922 brcmf_link_down(cfg_priv);
2923 } else {
2924 brcmf_bss_connect_done(cfg_priv, ndev, e, false);
2925 if (test_and_clear_bit(WL_STATUS_CONNECTED,
2926 &cfg_priv->status)) {
2927 cfg80211_disconnected(ndev, 0, NULL, 0,
2928 GFP_KERNEL);
2929 brcmf_link_down(cfg_priv);
2930 }
2931 }
2932 brcmf_init_prof(cfg_priv->profile);
2933 } else if (brcmf_is_nonetwork(cfg_priv, e)) {
2934 if (brcmf_is_ibssmode(cfg_priv))
2935 clear_bit(WL_STATUS_CONNECTING, &cfg_priv->status);
2936 else
2937 brcmf_bss_connect_done(cfg_priv, ndev, e, false);
2938 }
2939
2940 return err;
2941}
2942
2943static s32
2944brcmf_notify_roaming_status(struct brcmf_cfg80211_priv *cfg_priv,
2945 struct net_device *ndev,
2946 const struct brcmf_event_msg *e, void *data)
2947{
2948 s32 err = 0;
2949 u32 event = be32_to_cpu(e->event_type);
2950 u32 status = be32_to_cpu(e->status);
2951
2952 if (event == BRCMF_E_ROAM && status == BRCMF_E_STATUS_SUCCESS) {
2953 if (test_bit(WL_STATUS_CONNECTED, &cfg_priv->status))
2954 brcmf_bss_roaming_done(cfg_priv, ndev, e);
2955 else
2956 brcmf_bss_connect_done(cfg_priv, ndev, e, true);
2957 }
2958
2959 return err;
2960}
2961
2962static s32
2963brcmf_notify_mic_status(struct brcmf_cfg80211_priv *cfg_priv,
2964 struct net_device *ndev,
2965 const struct brcmf_event_msg *e, void *data)
2966{
2967 u16 flags = be16_to_cpu(e->flags);
2968 enum nl80211_key_type key_type;
2969
2970 if (flags & BRCMF_EVENT_MSG_GROUP)
2971 key_type = NL80211_KEYTYPE_GROUP;
2972 else
2973 key_type = NL80211_KEYTYPE_PAIRWISE;
2974
2975 cfg80211_michael_mic_failure(ndev, (u8 *)&e->addr, key_type, -1,
2976 NULL, GFP_KERNEL);
2977
2978 return 0;
2979}
2980
2981static s32
2982brcmf_notify_scan_status(struct brcmf_cfg80211_priv *cfg_priv,
2983 struct net_device *ndev,
2984 const struct brcmf_event_msg *e, void *data)
2985{
2986 struct brcmf_channel_info_le channel_inform_le;
2987 struct brcmf_scan_results_le *bss_list_le;
2988 u32 len = WL_SCAN_BUF_MAX;
2989 s32 err = 0;
2990 bool scan_abort = false;
2991 u32 scan_channel;
2992
2993 WL_TRACE("Enter\n");
2994
2995 if (cfg_priv->iscan_on && cfg_priv->iscan_kickstart) {
2996 WL_TRACE("Exit\n");
2997 return brcmf_wakeup_iscan(cfg_to_iscan(cfg_priv));
2998 }
2999
3000 if (!test_and_clear_bit(WL_STATUS_SCANNING, &cfg_priv->status)) {
3001 WL_ERR("Scan complete while device not scanning\n");
3002 scan_abort = true;
3003 err = -EINVAL;
3004 goto scan_done_out;
3005 }
3006
3007 err = brcmf_exec_dcmd(ndev, BRCMF_C_GET_CHANNEL, &channel_inform_le,
3008 sizeof(channel_inform_le));
3009 if (err) {
3010 WL_ERR("scan busy (%d)\n", err);
3011 scan_abort = true;
3012 goto scan_done_out;
3013 }
3014 scan_channel = le32_to_cpu(channel_inform_le.scan_channel);
3015 if (scan_channel)
3016 WL_CONN("channel_inform.scan_channel (%d)\n", scan_channel);
3017 cfg_priv->bss_list = cfg_priv->scan_results;
3018 bss_list_le = (struct brcmf_scan_results_le *) cfg_priv->bss_list;
3019
3020 memset(cfg_priv->scan_results, 0, len);
3021 bss_list_le->buflen = cpu_to_le32(len);
3022 err = brcmf_exec_dcmd(ndev, BRCMF_C_SCAN_RESULTS,
3023 cfg_priv->scan_results, len);
3024 if (err) {
3025 WL_ERR("%s Scan_results error (%d)\n", ndev->name, err);
3026 err = -EINVAL;
3027 scan_abort = true;
3028 goto scan_done_out;
3029 }
3030 cfg_priv->scan_results->buflen = le32_to_cpu(bss_list_le->buflen);
3031 cfg_priv->scan_results->version = le32_to_cpu(bss_list_le->version);
3032 cfg_priv->scan_results->count = le32_to_cpu(bss_list_le->count);
3033
3034 err = brcmf_inform_bss(cfg_priv);
3035 if (err) {
3036 scan_abort = true;
3037 goto scan_done_out;
3038 }
3039
3040scan_done_out:
3041 if (cfg_priv->scan_request) {
3042 WL_SCAN("calling cfg80211_scan_done\n");
3043 cfg80211_scan_done(cfg_priv->scan_request, scan_abort);
3044 brcmf_set_mpc(ndev, 1);
3045 cfg_priv->scan_request = NULL;
3046 }
3047
3048 WL_TRACE("Exit\n");
3049
3050 return err;
3051}
3052
3053static void brcmf_init_conf(struct brcmf_cfg80211_conf *conf)
3054{
3055 conf->mode = (u32)-1;
3056 conf->frag_threshold = (u32)-1;
3057 conf->rts_threshold = (u32)-1;
3058 conf->retry_short = (u32)-1;
3059 conf->retry_long = (u32)-1;
3060 conf->tx_power = -1;
3061}
3062
3063static void brcmf_init_eloop_handler(struct brcmf_cfg80211_event_loop *el)
3064{
3065 memset(el, 0, sizeof(*el));
3066 el->handler[BRCMF_E_SCAN_COMPLETE] = brcmf_notify_scan_status;
3067 el->handler[BRCMF_E_LINK] = brcmf_notify_connect_status;
3068 el->handler[BRCMF_E_ROAM] = brcmf_notify_roaming_status;
3069 el->handler[BRCMF_E_MIC_ERROR] = brcmf_notify_mic_status;
3070 el->handler[BRCMF_E_SET_SSID] = brcmf_notify_connect_status;
3071}
3072
3073static void brcmf_deinit_priv_mem(struct brcmf_cfg80211_priv *cfg_priv)
3074{
3075 kfree(cfg_priv->scan_results);
3076 cfg_priv->scan_results = NULL;
3077 kfree(cfg_priv->bss_info);
3078 cfg_priv->bss_info = NULL;
3079 kfree(cfg_priv->conf);
3080 cfg_priv->conf = NULL;
3081 kfree(cfg_priv->profile);
3082 cfg_priv->profile = NULL;
3083 kfree(cfg_priv->scan_req_int);
3084 cfg_priv->scan_req_int = NULL;
3085 kfree(cfg_priv->dcmd_buf);
3086 cfg_priv->dcmd_buf = NULL;
3087 kfree(cfg_priv->extra_buf);
3088 cfg_priv->extra_buf = NULL;
3089 kfree(cfg_priv->iscan);
3090 cfg_priv->iscan = NULL;
3091 kfree(cfg_priv->pmk_list);
3092 cfg_priv->pmk_list = NULL;
3093}
3094
3095static s32 brcmf_init_priv_mem(struct brcmf_cfg80211_priv *cfg_priv)
3096{
3097 cfg_priv->scan_results = kzalloc(WL_SCAN_BUF_MAX, GFP_KERNEL);
3098 if (!cfg_priv->scan_results)
3099 goto init_priv_mem_out;
3100 cfg_priv->conf = kzalloc(sizeof(*cfg_priv->conf), GFP_KERNEL);
3101 if (!cfg_priv->conf)
3102 goto init_priv_mem_out;
3103 cfg_priv->profile = kzalloc(sizeof(*cfg_priv->profile), GFP_KERNEL);
3104 if (!cfg_priv->profile)
3105 goto init_priv_mem_out;
3106 cfg_priv->bss_info = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
3107 if (!cfg_priv->bss_info)
3108 goto init_priv_mem_out;
3109 cfg_priv->scan_req_int = kzalloc(sizeof(*cfg_priv->scan_req_int),
3110 GFP_KERNEL);
3111 if (!cfg_priv->scan_req_int)
3112 goto init_priv_mem_out;
3113 cfg_priv->dcmd_buf = kzalloc(WL_DCMD_LEN_MAX, GFP_KERNEL);
3114 if (!cfg_priv->dcmd_buf)
3115 goto init_priv_mem_out;
3116 cfg_priv->extra_buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
3117 if (!cfg_priv->extra_buf)
3118 goto init_priv_mem_out;
3119 cfg_priv->iscan = kzalloc(sizeof(*cfg_priv->iscan), GFP_KERNEL);
3120 if (!cfg_priv->iscan)
3121 goto init_priv_mem_out;
3122 cfg_priv->pmk_list = kzalloc(sizeof(*cfg_priv->pmk_list), GFP_KERNEL);
3123 if (!cfg_priv->pmk_list)
3124 goto init_priv_mem_out;
3125
3126 return 0;
3127
3128init_priv_mem_out:
3129 brcmf_deinit_priv_mem(cfg_priv);
3130
3131 return -ENOMEM;
3132}
3133
3134/*
3135* retrieve first queued event from head
3136*/
3137
3138static struct brcmf_cfg80211_event_q *brcmf_deq_event(
3139 struct brcmf_cfg80211_priv *cfg_priv)
3140{
3141 struct brcmf_cfg80211_event_q *e = NULL;
3142
3143 spin_lock_irq(&cfg_priv->evt_q_lock);
3144 if (!list_empty(&cfg_priv->evt_q_list)) {
3145 e = list_first_entry(&cfg_priv->evt_q_list,
3146 struct brcmf_cfg80211_event_q, evt_q_list);
3147 list_del(&e->evt_q_list);
3148 }
3149 spin_unlock_irq(&cfg_priv->evt_q_lock);
3150
3151 return e;
3152}
3153
3154/*
3155** push event to tail of the queue
3156*/
3157
3158static s32
3159brcmf_enq_event(struct brcmf_cfg80211_priv *cfg_priv, u32 event,
3160 const struct brcmf_event_msg *msg)
3161{
3162 struct brcmf_cfg80211_event_q *e;
3163 s32 err = 0;
3164
3165 e = kzalloc(sizeof(struct brcmf_cfg80211_event_q), GFP_KERNEL);
3166 if (!e)
3167 return -ENOMEM;
3168
3169 e->etype = event;
3170 memcpy(&e->emsg, msg, sizeof(struct brcmf_event_msg));
3171
3172 spin_lock_irq(&cfg_priv->evt_q_lock);
3173 list_add_tail(&e->evt_q_list, &cfg_priv->evt_q_list);
3174 spin_unlock_irq(&cfg_priv->evt_q_lock);
3175
3176 return err;
3177}
3178
3179static void brcmf_put_event(struct brcmf_cfg80211_event_q *e)
3180{
3181 kfree(e);
3182}
3183
3184static void brcmf_cfg80211_event_handler(struct work_struct *work)
3185{
3186 struct brcmf_cfg80211_priv *cfg_priv =
3187 container_of(work, struct brcmf_cfg80211_priv,
3188 event_work);
3189 struct brcmf_cfg80211_event_q *e;
3190
3191 e = brcmf_deq_event(cfg_priv);
3192 if (unlikely(!e)) {
3193 WL_ERR("event queue empty...\n");
3194 return;
3195 }
3196
3197 do {
3198 WL_INFO("event type (%d)\n", e->etype);
3199 if (cfg_priv->el.handler[e->etype])
3200 cfg_priv->el.handler[e->etype](cfg_priv,
3201 cfg_to_ndev(cfg_priv),
3202 &e->emsg, e->edata);
3203 else
3204 WL_INFO("Unknown Event (%d): ignoring\n", e->etype);
3205 brcmf_put_event(e);
3206 } while ((e = brcmf_deq_event(cfg_priv)));
3207
3208}
3209
3210static void brcmf_init_eq(struct brcmf_cfg80211_priv *cfg_priv)
3211{
3212 spin_lock_init(&cfg_priv->evt_q_lock);
3213 INIT_LIST_HEAD(&cfg_priv->evt_q_list);
3214}
3215
3216static void brcmf_flush_eq(struct brcmf_cfg80211_priv *cfg_priv)
3217{
3218 struct brcmf_cfg80211_event_q *e;
3219
3220 spin_lock_irq(&cfg_priv->evt_q_lock);
3221 while (!list_empty(&cfg_priv->evt_q_list)) {
3222 e = list_first_entry(&cfg_priv->evt_q_list,
3223 struct brcmf_cfg80211_event_q, evt_q_list);
3224 list_del(&e->evt_q_list);
3225 kfree(e);
3226 }
3227 spin_unlock_irq(&cfg_priv->evt_q_lock);
3228}
3229
3230static s32 wl_init_priv(struct brcmf_cfg80211_priv *cfg_priv)
3231{
3232 s32 err = 0;
3233
3234 cfg_priv->scan_request = NULL;
3235 cfg_priv->pwr_save = true;
3236 cfg_priv->iscan_on = true; /* iscan on & off switch.
3237 we enable iscan per default */
3238 cfg_priv->roam_on = true; /* roam on & off switch.
3239 we enable roam per default */
3240
3241 cfg_priv->iscan_kickstart = false;
3242 cfg_priv->active_scan = true; /* we do active scan for
3243 specific scan per default */
3244 cfg_priv->dongle_up = false; /* dongle is not up yet */
3245 brcmf_init_eq(cfg_priv);
3246 err = brcmf_init_priv_mem(cfg_priv);
3247 if (err)
3248 return err;
3249 INIT_WORK(&cfg_priv->event_work, brcmf_cfg80211_event_handler);
3250 brcmf_init_eloop_handler(&cfg_priv->el);
3251 mutex_init(&cfg_priv->usr_sync);
3252 err = brcmf_init_iscan(cfg_priv);
3253 if (err)
3254 return err;
3255 brcmf_init_conf(cfg_priv->conf);
3256 brcmf_init_prof(cfg_priv->profile);
3257 brcmf_link_down(cfg_priv);
3258
3259 return err;
3260}
3261
3262static void wl_deinit_priv(struct brcmf_cfg80211_priv *cfg_priv)
3263{
3264 cancel_work_sync(&cfg_priv->event_work);
3265 cfg_priv->dongle_up = false; /* dongle down */
3266 brcmf_flush_eq(cfg_priv);
3267 brcmf_link_down(cfg_priv);
3268 brcmf_term_iscan(cfg_priv);
3269 brcmf_deinit_priv_mem(cfg_priv);
3270}
3271
3272struct brcmf_cfg80211_dev *brcmf_cfg80211_attach(struct net_device *ndev,
3273 struct device *busdev,
3274 void *data)
3275{
3276 struct wireless_dev *wdev;
3277 struct brcmf_cfg80211_priv *cfg_priv;
3278 struct brcmf_cfg80211_iface *ci;
3279 struct brcmf_cfg80211_dev *cfg_dev;
3280 s32 err = 0;
3281
3282 if (!ndev) {
3283 WL_ERR("ndev is invalid\n");
3284 return NULL;
3285 }
3286 cfg_dev = kzalloc(sizeof(struct brcmf_cfg80211_dev), GFP_KERNEL);
3287 if (!cfg_dev)
3288 return NULL;
3289
3290 wdev = brcmf_alloc_wdev(sizeof(struct brcmf_cfg80211_iface), busdev);
3291 if (IS_ERR(wdev)) {
3292 kfree(cfg_dev);
3293 return NULL;
3294 }
3295
3296 wdev->iftype = brcmf_mode_to_nl80211_iftype(WL_MODE_BSS);
3297 cfg_priv = wdev_to_cfg(wdev);
3298 cfg_priv->wdev = wdev;
3299 cfg_priv->pub = data;
3300 ci = (struct brcmf_cfg80211_iface *)&cfg_priv->ci;
3301 ci->cfg_priv = cfg_priv;
3302 ndev->ieee80211_ptr = wdev;
3303 SET_NETDEV_DEV(ndev, wiphy_dev(wdev->wiphy));
3304 wdev->netdev = ndev;
3305 err = wl_init_priv(cfg_priv);
3306 if (err) {
3307 WL_ERR("Failed to init iwm_priv (%d)\n", err);
3308 goto cfg80211_attach_out;
3309 }
3310 brcmf_set_drvdata(cfg_dev, ci);
3311
3312 return cfg_dev;
3313
3314cfg80211_attach_out:
3315 brcmf_free_wdev(cfg_priv);
3316 kfree(cfg_dev);
3317 return NULL;
3318}
3319
3320void brcmf_cfg80211_detach(struct brcmf_cfg80211_dev *cfg_dev)
3321{
3322 struct brcmf_cfg80211_priv *cfg_priv;
3323
3324 cfg_priv = brcmf_priv_get(cfg_dev);
3325
3326 wl_deinit_priv(cfg_priv);
3327 brcmf_free_wdev(cfg_priv);
3328 brcmf_set_drvdata(cfg_dev, NULL);
3329 kfree(cfg_dev);
3330}
3331
3332void
3333brcmf_cfg80211_event(struct net_device *ndev,
3334 const struct brcmf_event_msg *e, void *data)
3335{
3336 u32 event_type = be32_to_cpu(e->event_type);
3337 struct brcmf_cfg80211_priv *cfg_priv = ndev_to_cfg(ndev);
3338
3339 if (!brcmf_enq_event(cfg_priv, event_type, e))
3340 schedule_work(&cfg_priv->event_work);
3341}
3342
3343static s32 brcmf_dongle_mode(struct net_device *ndev, s32 iftype)
3344{
3345 s32 infra = 0;
3346 s32 err = 0;
3347
3348 switch (iftype) {
3349 case NL80211_IFTYPE_MONITOR:
3350 case NL80211_IFTYPE_WDS:
3351 WL_ERR("type (%d) : currently we do not support this mode\n",
3352 iftype);
3353 err = -EINVAL;
3354 return err;
3355 case NL80211_IFTYPE_ADHOC:
3356 infra = 0;
3357 break;
3358 case NL80211_IFTYPE_STATION:
3359 infra = 1;
3360 break;
3361 default:
3362 err = -EINVAL;
3363 WL_ERR("invalid type (%d)\n", iftype);
3364 return err;
3365 }
3366 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_SET_INFRA, &infra);
3367 if (err) {
3368 WL_ERR("WLC_SET_INFRA error (%d)\n", err);
3369 return err;
3370 }
3371
3372 return 0;
3373}
3374
3375static s32 brcmf_dongle_eventmsg(struct net_device *ndev)
3376{
3377 /* Room for "event_msgs" + '\0' + bitvec */
3378 s8 iovbuf[BRCMF_EVENTING_MASK_LEN + 12];
3379 s8 eventmask[BRCMF_EVENTING_MASK_LEN];
3380 s32 err = 0;
3381
3382 WL_TRACE("Enter\n");
3383
3384 /* Setup event_msgs */
3385 brcmu_mkiovar("event_msgs", eventmask, BRCMF_EVENTING_MASK_LEN, iovbuf,
3386 sizeof(iovbuf));
3387 err = brcmf_exec_dcmd(ndev, BRCMF_C_GET_VAR, iovbuf, sizeof(iovbuf));
3388 if (err) {
3389 WL_ERR("Get event_msgs error (%d)\n", err);
3390 goto dongle_eventmsg_out;
3391 }
3392 memcpy(eventmask, iovbuf, BRCMF_EVENTING_MASK_LEN);
3393
3394 setbit(eventmask, BRCMF_E_SET_SSID);
3395 setbit(eventmask, BRCMF_E_ROAM);
3396 setbit(eventmask, BRCMF_E_PRUNE);
3397 setbit(eventmask, BRCMF_E_AUTH);
3398 setbit(eventmask, BRCMF_E_REASSOC);
3399 setbit(eventmask, BRCMF_E_REASSOC_IND);
3400 setbit(eventmask, BRCMF_E_DEAUTH_IND);
3401 setbit(eventmask, BRCMF_E_DISASSOC_IND);
3402 setbit(eventmask, BRCMF_E_DISASSOC);
3403 setbit(eventmask, BRCMF_E_JOIN);
3404 setbit(eventmask, BRCMF_E_ASSOC_IND);
3405 setbit(eventmask, BRCMF_E_PSK_SUP);
3406 setbit(eventmask, BRCMF_E_LINK);
3407 setbit(eventmask, BRCMF_E_NDIS_LINK);
3408 setbit(eventmask, BRCMF_E_MIC_ERROR);
3409 setbit(eventmask, BRCMF_E_PMKID_CACHE);
3410 setbit(eventmask, BRCMF_E_TXFAIL);
3411 setbit(eventmask, BRCMF_E_JOIN_START);
3412 setbit(eventmask, BRCMF_E_SCAN_COMPLETE);
3413
3414 brcmu_mkiovar("event_msgs", eventmask, BRCMF_EVENTING_MASK_LEN, iovbuf,
3415 sizeof(iovbuf));
3416 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_VAR, iovbuf, sizeof(iovbuf));
3417 if (err) {
3418 WL_ERR("Set event_msgs error (%d)\n", err);
3419 goto dongle_eventmsg_out;
3420 }
3421
3422dongle_eventmsg_out:
3423 WL_TRACE("Exit\n");
3424 return err;
3425}
3426
3427static s32
3428brcmf_dongle_roam(struct net_device *ndev, u32 roamvar, u32 bcn_timeout)
3429{
3430 s8 iovbuf[32];
3431 s32 roamtrigger[2];
3432 s32 roam_delta[2];
3433 s32 err = 0;
3434
3435 /*
3436 * Setup timeout if Beacons are lost and roam is
3437 * off to report link down
3438 */
3439 if (roamvar) {
3440 brcmu_mkiovar("bcn_timeout", (char *)&bcn_timeout,
3441 sizeof(bcn_timeout), iovbuf, sizeof(iovbuf));
3442 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_VAR,
3443 iovbuf, sizeof(iovbuf));
3444 if (err) {
3445 WL_ERR("bcn_timeout error (%d)\n", err);
3446 goto dongle_rom_out;
3447 }
3448 }
3449
3450 /*
3451 * Enable/Disable built-in roaming to allow supplicant
3452 * to take care of roaming
3453 */
3454 WL_INFO("Internal Roaming = %s\n", roamvar ? "Off" : "On");
3455 brcmu_mkiovar("roam_off", (char *)&roamvar,
3456 sizeof(roamvar), iovbuf, sizeof(iovbuf));
3457 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_VAR, iovbuf, sizeof(iovbuf));
3458 if (err) {
3459 WL_ERR("roam_off error (%d)\n", err);
3460 goto dongle_rom_out;
3461 }
3462
3463 roamtrigger[0] = WL_ROAM_TRIGGER_LEVEL;
3464 roamtrigger[1] = BRCM_BAND_ALL;
3465 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_ROAM_TRIGGER,
3466 (void *)roamtrigger, sizeof(roamtrigger));
3467 if (err) {
3468 WL_ERR("WLC_SET_ROAM_TRIGGER error (%d)\n", err);
3469 goto dongle_rom_out;
3470 }
3471
3472 roam_delta[0] = WL_ROAM_DELTA;
3473 roam_delta[1] = BRCM_BAND_ALL;
3474 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_ROAM_DELTA,
3475 (void *)roam_delta, sizeof(roam_delta));
3476 if (err) {
3477 WL_ERR("WLC_SET_ROAM_DELTA error (%d)\n", err);
3478 goto dongle_rom_out;
3479 }
3480
3481dongle_rom_out:
3482 return err;
3483}
3484
3485static s32
3486brcmf_dongle_scantime(struct net_device *ndev, s32 scan_assoc_time,
3487 s32 scan_unassoc_time, s32 scan_passive_time)
3488{
3489 s32 err = 0;
3490
3491 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_SCAN_CHANNEL_TIME,
3492 &scan_assoc_time, sizeof(scan_assoc_time));
3493 if (err) {
3494 if (err == -EOPNOTSUPP)
3495 WL_INFO("Scan assoc time is not supported\n");
3496 else
3497 WL_ERR("Scan assoc time error (%d)\n", err);
3498 goto dongle_scantime_out;
3499 }
3500 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_SCAN_UNASSOC_TIME,
3501 &scan_unassoc_time, sizeof(scan_unassoc_time));
3502 if (err) {
3503 if (err == -EOPNOTSUPP)
3504 WL_INFO("Scan unassoc time is not supported\n");
3505 else
3506 WL_ERR("Scan unassoc time error (%d)\n", err);
3507 goto dongle_scantime_out;
3508 }
3509
3510 err = brcmf_exec_dcmd(ndev, BRCMF_C_SET_SCAN_PASSIVE_TIME,
3511 &scan_passive_time, sizeof(scan_passive_time));
3512 if (err) {
3513 if (err == -EOPNOTSUPP)
3514 WL_INFO("Scan passive time is not supported\n");
3515 else
3516 WL_ERR("Scan passive time error (%d)\n", err);
3517 goto dongle_scantime_out;
3518 }
3519
3520dongle_scantime_out:
3521 return err;
3522}
3523
3524static s32 wl_update_wiphybands(struct brcmf_cfg80211_priv *cfg_priv)
3525{
3526 struct wiphy *wiphy;
3527 s32 phy_list;
3528 s8 phy;
3529 s32 err = 0;
3530
3531 err = brcmf_exec_dcmd(cfg_to_ndev(cfg_priv), BRCM_GET_PHYLIST,
3532 &phy_list, sizeof(phy_list));
3533 if (err) {
3534 WL_ERR("error (%d)\n", err);
3535 return err;
3536 }
3537
3538 phy = ((char *)&phy_list)[1];
3539 WL_INFO("%c phy\n", phy);
3540 if (phy == 'n' || phy == 'a') {
3541 wiphy = cfg_to_wiphy(cfg_priv);
3542 wiphy->bands[IEEE80211_BAND_5GHZ] = &__wl_band_5ghz_n;
3543 }
3544
3545 return err;
3546}
3547
3548static s32 brcmf_dongle_probecap(struct brcmf_cfg80211_priv *cfg_priv)
3549{
3550 return wl_update_wiphybands(cfg_priv);
3551}
3552
3553static s32 brcmf_config_dongle(struct brcmf_cfg80211_priv *cfg_priv)
3554{
3555 struct net_device *ndev;
3556 struct wireless_dev *wdev;
3557 s32 power_mode;
3558 s32 err = 0;
3559
3560 if (cfg_priv->dongle_up)
3561 return err;
3562
3563 ndev = cfg_to_ndev(cfg_priv);
3564 wdev = ndev->ieee80211_ptr;
3565
3566 brcmf_dongle_scantime(ndev, WL_SCAN_CHANNEL_TIME,
3567 WL_SCAN_UNASSOC_TIME, WL_SCAN_PASSIVE_TIME);
3568
3569 err = brcmf_dongle_eventmsg(ndev);
3570 if (err)
3571 goto default_conf_out;
3572
3573 power_mode = cfg_priv->pwr_save ? PM_FAST : PM_OFF;
3574 err = brcmf_exec_dcmd_u32(ndev, BRCMF_C_SET_PM, &power_mode);
3575 if (err)
3576 goto default_conf_out;
3577 WL_INFO("power save set to %s\n",
3578 (power_mode ? "enabled" : "disabled"));
3579
3580 err = brcmf_dongle_roam(ndev, (cfg_priv->roam_on ? 0 : 1),
3581 WL_BEACON_TIMEOUT);
3582 if (err)
3583 goto default_conf_out;
3584 err = brcmf_dongle_mode(ndev, wdev->iftype);
3585 if (err && err != -EINPROGRESS)
3586 goto default_conf_out;
3587 err = brcmf_dongle_probecap(cfg_priv);
3588 if (err)
3589 goto default_conf_out;
3590
3591 /* -EINPROGRESS: Call commit handler */
3592
3593default_conf_out:
3594
3595 cfg_priv->dongle_up = true;
3596
3597 return err;
3598
3599}
3600
3601static int brcmf_debugfs_add_netdev_params(struct brcmf_cfg80211_priv *cfg_priv)
3602{
3603 char buf[10+IFNAMSIZ];
3604 struct dentry *fd;
3605 s32 err = 0;
3606
3607 sprintf(buf, "netdev:%s", cfg_to_ndev(cfg_priv)->name);
3608 cfg_priv->debugfsdir = debugfs_create_dir(buf,
3609 cfg_to_wiphy(cfg_priv)->debugfsdir);
3610
3611 fd = debugfs_create_u16("beacon_int", S_IRUGO, cfg_priv->debugfsdir,
3612 (u16 *)&cfg_priv->profile->beacon_interval);
3613 if (!fd) {
3614 err = -ENOMEM;
3615 goto err_out;
3616 }
3617
3618 fd = debugfs_create_u8("dtim_period", S_IRUGO, cfg_priv->debugfsdir,
3619 (u8 *)&cfg_priv->profile->dtim_period);
3620 if (!fd) {
3621 err = -ENOMEM;
3622 goto err_out;
3623 }
3624
3625err_out:
3626 return err;
3627}
3628
3629static void brcmf_debugfs_remove_netdev(struct brcmf_cfg80211_priv *cfg_priv)
3630{
3631 debugfs_remove_recursive(cfg_priv->debugfsdir);
3632 cfg_priv->debugfsdir = NULL;
3633}
3634
3635static s32 __brcmf_cfg80211_up(struct brcmf_cfg80211_priv *cfg_priv)
3636{
3637 s32 err = 0;
3638
3639 set_bit(WL_STATUS_READY, &cfg_priv->status);
3640
3641 brcmf_debugfs_add_netdev_params(cfg_priv);
3642
3643 err = brcmf_config_dongle(cfg_priv);
3644 if (err)
3645 return err;
3646
3647 brcmf_invoke_iscan(cfg_priv);
3648
3649 return err;
3650}
3651
3652static s32 __brcmf_cfg80211_down(struct brcmf_cfg80211_priv *cfg_priv)
3653{
3654 /*
3655 * While going down, if associated with AP disassociate
3656 * from AP to save power
3657 */
3658 if ((test_bit(WL_STATUS_CONNECTED, &cfg_priv->status) ||
3659 test_bit(WL_STATUS_CONNECTING, &cfg_priv->status)) &&
3660 test_bit(WL_STATUS_READY, &cfg_priv->status)) {
3661 WL_INFO("Disassociating from AP");
3662 brcmf_link_down(cfg_priv);
3663
3664 /* Make sure WPA_Supplicant receives all the event
3665 generated due to DISASSOC call to the fw to keep
3666 the state fw and WPA_Supplicant state consistent
3667 */
3668 brcmf_delay(500);
3669 }
3670
3671 set_bit(WL_STATUS_SCAN_ABORTING, &cfg_priv->status);
3672 brcmf_term_iscan(cfg_priv);
3673 if (cfg_priv->scan_request) {
3674 cfg80211_scan_done(cfg_priv->scan_request, true);
3675 /* May need to perform this to cover rmmod */
3676 /* wl_set_mpc(cfg_to_ndev(wl), 1); */
3677 cfg_priv->scan_request = NULL;
3678 }
3679 clear_bit(WL_STATUS_READY, &cfg_priv->status);
3680 clear_bit(WL_STATUS_SCANNING, &cfg_priv->status);
3681 clear_bit(WL_STATUS_SCAN_ABORTING, &cfg_priv->status);
3682
3683 brcmf_debugfs_remove_netdev(cfg_priv);
3684
3685 return 0;
3686}
3687
3688s32 brcmf_cfg80211_up(struct brcmf_cfg80211_dev *cfg_dev)
3689{
3690 struct brcmf_cfg80211_priv *cfg_priv;
3691 s32 err = 0;
3692
3693 cfg_priv = brcmf_priv_get(cfg_dev);
3694 mutex_lock(&cfg_priv->usr_sync);
3695 err = __brcmf_cfg80211_up(cfg_priv);
3696 mutex_unlock(&cfg_priv->usr_sync);
3697
3698 return err;
3699}
3700
3701s32 brcmf_cfg80211_down(struct brcmf_cfg80211_dev *cfg_dev)
3702{
3703 struct brcmf_cfg80211_priv *cfg_priv;
3704 s32 err = 0;
3705
3706 cfg_priv = brcmf_priv_get(cfg_dev);
3707 mutex_lock(&cfg_priv->usr_sync);
3708 err = __brcmf_cfg80211_down(cfg_priv);
3709 mutex_unlock(&cfg_priv->usr_sync);
3710
3711 return err;
3712}
3713
3714static __used s32 brcmf_add_ie(struct brcmf_cfg80211_priv *cfg_priv,
3715 u8 t, u8 l, u8 *v)
3716{
3717 struct brcmf_cfg80211_ie *ie = &cfg_priv->ie;
3718 s32 err = 0;
3719
3720 if (ie->offset + l + 2 > WL_TLV_INFO_MAX) {
3721 WL_ERR("ei crosses buffer boundary\n");
3722 return -ENOSPC;
3723 }
3724 ie->buf[ie->offset] = t;
3725 ie->buf[ie->offset + 1] = l;
3726 memcpy(&ie->buf[ie->offset + 2], v, l);
3727 ie->offset += l + 2;
3728
3729 return err;
3730}
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
deleted file mode 100644
index e69f4f6bf94..00000000000
--- a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
+++ /dev/null
@@ -1,375 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _wl_cfg80211_h_
18#define _wl_cfg80211_h_
19
20struct brcmf_cfg80211_conf;
21struct brcmf_cfg80211_iface;
22struct brcmf_cfg80211_priv;
23struct brcmf_cfg80211_security;
24struct brcmf_cfg80211_ibss;
25
26#define WL_DBG_NONE 0
27#define WL_DBG_CONN (1 << 5)
28#define WL_DBG_SCAN (1 << 4)
29#define WL_DBG_TRACE (1 << 3)
30#define WL_DBG_INFO (1 << 1)
31#define WL_DBG_ERR (1 << 0)
32#define WL_DBG_MASK ((WL_DBG_INFO | WL_DBG_ERR | WL_DBG_TRACE) | \
33 (WL_DBG_SCAN) | (WL_DBG_CONN))
34
35#define WL_ERR(fmt, args...) \
36do { \
37 if (brcmf_dbg_level & WL_DBG_ERR) { \
38 if (net_ratelimit()) { \
39 printk(KERN_ERR "ERROR @%s : " fmt, \
40 __func__, ##args); \
41 } \
42 } \
43} while (0)
44
45#if (defined BCMDBG)
46#define WL_INFO(fmt, args...) \
47do { \
48 if (brcmf_dbg_level & WL_DBG_INFO) { \
49 if (net_ratelimit()) { \
50 printk(KERN_ERR "INFO @%s : " fmt, \
51 __func__, ##args); \
52 } \
53 } \
54} while (0)
55
56#define WL_TRACE(fmt, args...) \
57do { \
58 if (brcmf_dbg_level & WL_DBG_TRACE) { \
59 if (net_ratelimit()) { \
60 printk(KERN_ERR "TRACE @%s : " fmt, \
61 __func__, ##args); \
62 } \
63 } \
64} while (0)
65
66#define WL_SCAN(fmt, args...) \
67do { \
68 if (brcmf_dbg_level & WL_DBG_SCAN) { \
69 if (net_ratelimit()) { \
70 printk(KERN_ERR "SCAN @%s : " fmt, \
71 __func__, ##args); \
72 } \
73 } \
74} while (0)
75
76#define WL_CONN(fmt, args...) \
77do { \
78 if (brcmf_dbg_level & WL_DBG_CONN) { \
79 if (net_ratelimit()) { \
80 printk(KERN_ERR "CONN @%s : " fmt, \
81 __func__, ##args); \
82 } \
83 } \
84} while (0)
85
86#else /* (defined BCMDBG) */
87#define WL_INFO(fmt, args...)
88#define WL_TRACE(fmt, args...)
89#define WL_SCAN(fmt, args...)
90#define WL_CONN(fmt, args...)
91#endif /* (defined BCMDBG) */
92
93#define WL_NUM_SCAN_MAX 1
94#define WL_NUM_PMKIDS_MAX MAXPMKID /* will be used
95 * for 2.6.33 kernel
96 * or later
97 */
98#define WL_SCAN_BUF_MAX (1024 * 8)
99#define WL_TLV_INFO_MAX 1024
100#define WL_BSS_INFO_MAX 2048
101#define WL_ASSOC_INFO_MAX 512 /*
102 * needs to grab assoc info from dongle to
103 * report it to cfg80211 through "connect"
104 * event
105 */
106#define WL_DCMD_LEN_MAX 1024
107#define WL_EXTRA_BUF_MAX 2048
108#define WL_ISCAN_BUF_MAX 2048 /*
109 * the buf length can be BRCMF_DCMD_MAXLEN
110 * to reduce iteration
111 */
112#define WL_ISCAN_TIMER_INTERVAL_MS 3000
113#define WL_SCAN_ERSULTS_LAST (BRCMF_SCAN_RESULTS_NO_MEM+1)
114#define WL_AP_MAX 256 /* virtually unlimitted as long
115 * as kernel memory allows
116 */
117
118#define WL_ROAM_TRIGGER_LEVEL -75
119#define WL_ROAM_DELTA 20
120#define WL_BEACON_TIMEOUT 3
121
122#define WL_SCAN_CHANNEL_TIME 40
123#define WL_SCAN_UNASSOC_TIME 40
124#define WL_SCAN_PASSIVE_TIME 120
125
126/* dongle status */
127enum wl_status {
128 WL_STATUS_READY,
129 WL_STATUS_SCANNING,
130 WL_STATUS_SCAN_ABORTING,
131 WL_STATUS_CONNECTING,
132 WL_STATUS_CONNECTED
133};
134
135/* wi-fi mode */
136enum wl_mode {
137 WL_MODE_BSS,
138 WL_MODE_IBSS,
139 WL_MODE_AP
140};
141
142/* dongle profile list */
143enum wl_prof_list {
144 WL_PROF_MODE,
145 WL_PROF_SSID,
146 WL_PROF_SEC,
147 WL_PROF_IBSS,
148 WL_PROF_BAND,
149 WL_PROF_BSSID,
150 WL_PROF_ACT,
151 WL_PROF_BEACONINT,
152 WL_PROF_DTIMPERIOD
153};
154
155/* dongle iscan state */
156enum wl_iscan_state {
157 WL_ISCAN_STATE_IDLE,
158 WL_ISCAN_STATE_SCANING
159};
160
161/* dongle configuration */
162struct brcmf_cfg80211_conf {
163 u32 mode; /* adhoc , infrastructure or ap */
164 u32 frag_threshold;
165 u32 rts_threshold;
166 u32 retry_short;
167 u32 retry_long;
168 s32 tx_power;
169 struct ieee80211_channel channel;
170};
171
172/* cfg80211 main event loop */
173struct brcmf_cfg80211_event_loop {
174 s32(*handler[BRCMF_E_LAST]) (struct brcmf_cfg80211_priv *cfg_priv,
175 struct net_device *ndev,
176 const struct brcmf_event_msg *e,
177 void *data);
178};
179
180/* representing interface of cfg80211 plane */
181struct brcmf_cfg80211_iface {
182 struct brcmf_cfg80211_priv *cfg_priv;
183};
184
185struct brcmf_cfg80211_dev {
186 void *driver_data; /* to store cfg80211 object information */
187};
188
189/* basic structure of scan request */
190struct brcmf_cfg80211_scan_req {
191 struct brcmf_ssid_le ssid_le;
192};
193
194/* basic structure of information element */
195struct brcmf_cfg80211_ie {
196 u16 offset;
197 u8 buf[WL_TLV_INFO_MAX];
198};
199
200/* event queue for cfg80211 main event */
201struct brcmf_cfg80211_event_q {
202 struct list_head evt_q_list;
203 u32 etype;
204 struct brcmf_event_msg emsg;
205 s8 edata[1];
206};
207
208/* security information with currently associated ap */
209struct brcmf_cfg80211_security {
210 u32 wpa_versions;
211 u32 auth_type;
212 u32 cipher_pairwise;
213 u32 cipher_group;
214 u32 wpa_auth;
215};
216
217/* ibss information for currently joined ibss network */
218struct brcmf_cfg80211_ibss {
219 u8 beacon_interval; /* in millisecond */
220 u8 atim; /* in millisecond */
221 s8 join_only;
222 u8 band;
223 u8 channel;
224};
225
226/* dongle profile */
227struct brcmf_cfg80211_profile {
228 u32 mode;
229 struct brcmf_ssid ssid;
230 u8 bssid[ETH_ALEN];
231 u16 beacon_interval;
232 u8 dtim_period;
233 struct brcmf_cfg80211_security sec;
234 struct brcmf_cfg80211_ibss ibss;
235 s32 band;
236};
237
238/* dongle iscan event loop */
239struct brcmf_cfg80211_iscan_eloop {
240 s32 (*handler[WL_SCAN_ERSULTS_LAST])
241 (struct brcmf_cfg80211_priv *cfg_priv);
242};
243
244/* dongle iscan controller */
245struct brcmf_cfg80211_iscan_ctrl {
246 struct net_device *ndev;
247 struct timer_list timer;
248 u32 timer_ms;
249 u32 timer_on;
250 s32 state;
251 struct work_struct work;
252 struct brcmf_cfg80211_iscan_eloop el;
253 void *data;
254 s8 dcmd_buf[BRCMF_DCMD_SMLEN];
255 s8 scan_buf[WL_ISCAN_BUF_MAX];
256};
257
258/* association inform */
259struct brcmf_cfg80211_connect_info {
260 u8 *req_ie;
261 s32 req_ie_len;
262 u8 *resp_ie;
263 s32 resp_ie_len;
264};
265
266/* assoc ie length */
267struct brcmf_cfg80211_assoc_ielen {
268 u32 req_len;
269 u32 resp_len;
270};
271
272/* wpa2 pmk list */
273struct brcmf_cfg80211_pmk_list {
274 struct pmkid_list pmkids;
275 struct pmkid foo[MAXPMKID - 1];
276};
277
278/* dongle private data of cfg80211 interface */
279struct brcmf_cfg80211_priv {
280 struct wireless_dev *wdev; /* representing wl cfg80211 device */
281 struct brcmf_cfg80211_conf *conf; /* dongle configuration */
282 struct cfg80211_scan_request *scan_request; /* scan request
283 object */
284 struct brcmf_cfg80211_event_loop el; /* main event loop */
285 struct list_head evt_q_list; /* used for event queue */
286 spinlock_t evt_q_lock; /* for event queue synchronization */
287 struct mutex usr_sync; /* maily for dongle up/down synchronization */
288 struct brcmf_scan_results *bss_list; /* bss_list holding scanned
289 ap information */
290 struct brcmf_scan_results *scan_results;
291 struct brcmf_cfg80211_scan_req *scan_req_int; /* scan request object
292 for internal purpose */
293 struct wl_cfg80211_bss_info *bss_info; /* bss information for
294 cfg80211 layer */
295 struct brcmf_cfg80211_ie ie; /* information element object for
296 internal purpose */
297 struct brcmf_cfg80211_profile *profile; /* holding dongle profile */
298 struct brcmf_cfg80211_iscan_ctrl *iscan; /* iscan controller */
299 struct brcmf_cfg80211_connect_info conn_info; /* association info */
300 struct brcmf_cfg80211_pmk_list *pmk_list; /* wpa2 pmk list */
301 struct work_struct event_work; /* event handler work struct */
302 unsigned long status; /* current dongle status */
303 void *pub;
304 u32 channel; /* current channel */
305 bool iscan_on; /* iscan on/off switch */
306 bool iscan_kickstart; /* indicate iscan already started */
307 bool active_scan; /* current scan mode */
308 bool ibss_starter; /* indicates this sta is ibss starter */
309 bool link_up; /* link/connection up flag */
310 bool pwr_save; /* indicate whether dongle to support
311 power save mode */
312 bool dongle_up; /* indicate whether dongle up or not */
313 bool roam_on; /* on/off switch for dongle self-roaming */
314 bool scan_tried; /* indicates if first scan attempted */
315 u8 *dcmd_buf; /* dcmd buffer */
316 u8 *extra_buf; /* maily to grab assoc information */
317 struct dentry *debugfsdir;
318 u8 ci[0] __aligned(NETDEV_ALIGN);
319};
320
321static inline struct wiphy *cfg_to_wiphy(struct brcmf_cfg80211_priv *w)
322{
323 return w->wdev->wiphy;
324}
325
326static inline struct brcmf_cfg80211_priv *wiphy_to_cfg(struct wiphy *w)
327{
328 return (struct brcmf_cfg80211_priv *)(wiphy_priv(w));
329}
330
331static inline struct brcmf_cfg80211_priv *wdev_to_cfg(struct wireless_dev *wd)
332{
333 return (struct brcmf_cfg80211_priv *)(wdev_priv(wd));
334}
335
336static inline struct net_device *cfg_to_ndev(struct brcmf_cfg80211_priv *cfg)
337{
338 return cfg->wdev->netdev;
339}
340
341static inline struct brcmf_cfg80211_priv *ndev_to_cfg(struct net_device *ndev)
342{
343 return wdev_to_cfg(ndev->ieee80211_ptr);
344}
345
346#define iscan_to_cfg(i) ((struct brcmf_cfg80211_priv *)(i->data))
347#define cfg_to_iscan(w) (w->iscan)
348
349static inline struct
350brcmf_cfg80211_connect_info *cfg_to_conn(struct brcmf_cfg80211_priv *cfg)
351{
352 return &cfg->conn_info;
353}
354
355static inline struct brcmf_bss_info *next_bss(struct brcmf_scan_results *list,
356 struct brcmf_bss_info *bss)
357{
358 return bss = bss ?
359 (struct brcmf_bss_info *)((unsigned long)bss +
360 le32_to_cpu(bss->length)) :
361 list->bss_info;
362}
363
364extern struct brcmf_cfg80211_dev *brcmf_cfg80211_attach(struct net_device *ndev,
365 struct device *busdev,
366 void *data);
367extern void brcmf_cfg80211_detach(struct brcmf_cfg80211_dev *cfg);
368
369/* event handler from dongle */
370extern void brcmf_cfg80211_event(struct net_device *ndev,
371 const struct brcmf_event_msg *e, void *data);
372extern s32 brcmf_cfg80211_up(struct brcmf_cfg80211_dev *cfg_dev);
373extern s32 brcmf_cfg80211_down(struct brcmf_cfg80211_dev *cfg_dev);
374
375#endif /* _wl_cfg80211_h_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/Makefile b/drivers/staging/brcm80211/brcmsmac/Makefile
deleted file mode 100644
index a8a152b7e01..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
1#
2# Makefile fragment for Broadcom 802.11n Networking Device Driver
3#
4# Copyright (c) 2010 Broadcom Corporation
5#
6# Permission to use, copy, modify, and/or distribute this software for any
7# purpose with or without fee is hereby granted, provided that the above
8# copyright notice and this permission notice appear in all copies.
9#
10# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17
18ccflags-y := \
19 -D__CHECK_ENDIAN__ \
20 -Idrivers/staging/brcm80211/brcmsmac \
21 -Idrivers/staging/brcm80211/brcmsmac/phy \
22 -Idrivers/staging/brcm80211/include
23
24BRCMSMAC_OFILES := \
25 mac80211_if.o \
26 ucode_loader.o \
27 ampdu.o \
28 antsel.o \
29 channel.o \
30 main.o \
31 phy_shim.o \
32 pmu.o \
33 rate.o \
34 stf.o \
35 aiutils.o \
36 phy/phy_cmn.o \
37 phy/phy_lcn.o \
38 phy/phy_n.o \
39 phy/phytbl_lcn.o \
40 phy/phytbl_n.o \
41 phy/phy_qmath.o \
42 otp.o \
43 srom.o \
44 dma.o \
45 nicpci.o \
46 brcms_trace_events.o
47
48MODULEPFX := brcmsmac
49
50obj-$(CONFIG_BRCMSMAC) += $(MODULEPFX).o
51$(MODULEPFX)-objs = $(BRCMSMAC_OFILES)
diff --git a/drivers/staging/brcm80211/brcmsmac/aiutils.c b/drivers/staging/brcm80211/brcmsmac/aiutils.c
deleted file mode 100644
index 025fa0eb6f4..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/aiutils.c
+++ /dev/null
@@ -1,2079 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * File contents: support functions for PCI/PCIe
17 */
18
19#include <linux/delay.h>
20#include <linux/pci.h>
21
22#include <defs.h>
23#include <chipcommon.h>
24#include <brcmu_utils.h>
25#include <brcm_hw_ids.h>
26#include <soc.h>
27#include "types.h"
28#include "pub.h"
29#include "pmu.h"
30#include "srom.h"
31#include "nicpci.h"
32#include "aiutils.h"
33
34/* slow_clk_ctl */
35 /* slow clock source mask */
36#define SCC_SS_MASK 0x00000007
37 /* source of slow clock is LPO */
38#define SCC_SS_LPO 0x00000000
39 /* source of slow clock is crystal */
40#define SCC_SS_XTAL 0x00000001
41 /* source of slow clock is PCI */
42#define SCC_SS_PCI 0x00000002
43 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
44#define SCC_LF 0x00000200
45 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
46#define SCC_LP 0x00000400
47 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
48#define SCC_FS 0x00000800
49 /* IgnorePllOffReq, 1/0:
50 * power logic ignores/honors PLL clock disable requests from core
51 */
52#define SCC_IP 0x00001000
53 /* XtalControlEn, 1/0:
54 * power logic does/doesn't disable crystal when appropriate
55 */
56#define SCC_XC 0x00002000
57 /* XtalPU (RO), 1/0: crystal running/disabled */
58#define SCC_XP 0x00004000
59 /* ClockDivider (SlowClk = 1/(4+divisor)) */
60#define SCC_CD_MASK 0xffff0000
61#define SCC_CD_SHIFT 16
62
63/* system_clk_ctl */
64 /* ILPen: Enable Idle Low Power */
65#define SYCC_IE 0x00000001
66 /* ALPen: Enable Active Low Power */
67#define SYCC_AE 0x00000002
68 /* ForcePLLOn */
69#define SYCC_FP 0x00000004
70 /* Force ALP (or HT if ALPen is not set */
71#define SYCC_AR 0x00000008
72 /* Force HT */
73#define SYCC_HR 0x00000010
74 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
75#define SYCC_CD_MASK 0xffff0000
76#define SYCC_CD_SHIFT 16
77
78#define CST4329_SPROM_OTP_SEL_MASK 0x00000003
79 /* OTP is powered up, use def. CIS, no SPROM */
80#define CST4329_DEFCIS_SEL 0
81 /* OTP is powered up, SPROM is present */
82#define CST4329_SPROM_SEL 1
83 /* OTP is powered up, no SPROM */
84#define CST4329_OTP_SEL 2
85 /* OTP is powered down, SPROM is present */
86#define CST4329_OTP_PWRDN 3
87
88#define CST4329_SPI_SDIO_MODE_MASK 0x00000004
89#define CST4329_SPI_SDIO_MODE_SHIFT 2
90
91/* 43224 chip-specific ChipControl register bits */
92#define CCTRL43224_GPIO_TOGGLE 0x8000
93 /* 12 mA drive strength */
94#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0
95 /* 12 mA drive strength for later 43224s */
96#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0
97
98/* 43236 Chip specific ChipStatus register bits */
99#define CST43236_SFLASH_MASK 0x00000040
100#define CST43236_OTP_MASK 0x00000080
101#define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
102#define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
103#define CST43236_BOOT_MASK 0x00001800
104#define CST43236_BOOT_SHIFT 11
105#define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
106#define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */
107#define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */
108#define CST43236_BOOT_FROM_INVALID 3
109
110/* 4331 chip-specific ChipControl register bits */
111 /* 0 disable */
112#define CCTRL4331_BT_COEXIST (1<<0)
113 /* 0 SECI is disabled (JTAG functional) */
114#define CCTRL4331_SECI (1<<1)
115 /* 0 disable */
116#define CCTRL4331_EXT_LNA (1<<2)
117 /* sprom/gpio13-15 mux */
118#define CCTRL4331_SPROM_GPIO13_15 (1<<3)
119 /* 0 ext pa disable, 1 ext pa enabled */
120#define CCTRL4331_EXTPA_EN (1<<4)
121 /* set drive out GPIO_CLK on sprom_cs pin */
122#define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5)
123 /* use sprom_cs pin as PCIE mdio interface */
124#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6)
125 /* aband extpa will be at gpio2/5 and sprom_dout */
126#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7)
127 /* override core control on pipe_AuxClkEnable */
128#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8)
129 /* override core control on pipe_AuxPowerDown */
130#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9)
131 /* pcie_auxclkenable */
132#define CCTRL4331_PCIE_AUXCLKEN (1<<10)
133 /* pcie_pipe_pllpowerdown */
134#define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11)
135 /* enable bt_shd0 at gpio4 */
136#define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16)
137 /* enable bt_shd1 at gpio5 */
138#define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17)
139
140/* 4331 Chip specific ChipStatus register bits */
141 /* crystal frequency 20/40Mhz */
142#define CST4331_XTAL_FREQ 0x00000001
143#define CST4331_SPROM_PRESENT 0x00000002
144#define CST4331_OTP_PRESENT 0x00000004
145#define CST4331_LDO_RF 0x00000008
146#define CST4331_LDO_PAR 0x00000010
147
148/* 4319 chip-specific ChipStatus register bits */
149#define CST4319_SPI_CPULESSUSB 0x00000001
150#define CST4319_SPI_CLK_POL 0x00000002
151#define CST4319_SPI_CLK_PH 0x00000008
152 /* gpio [7:6], SDIO CIS selection */
153#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0
154#define CST4319_SPROM_OTP_SEL_SHIFT 6
155 /* use default CIS, OTP is powered up */
156#define CST4319_DEFCIS_SEL 0x00000000
157 /* use SPROM, OTP is powered up */
158#define CST4319_SPROM_SEL 0x00000040
159 /* use OTP, OTP is powered up */
160#define CST4319_OTP_SEL 0x00000080
161 /* use SPROM, OTP is powered down */
162#define CST4319_OTP_PWRDN 0x000000c0
163 /* gpio [8], sdio/usb mode */
164#define CST4319_SDIO_USB_MODE 0x00000100
165#define CST4319_REMAP_SEL_MASK 0x00000600
166#define CST4319_ILPDIV_EN 0x00000800
167#define CST4319_XTAL_PD_POL 0x00001000
168#define CST4319_LPO_SEL 0x00002000
169#define CST4319_RES_INIT_MODE 0x0000c000
170 /* PALDO is configured with external PNP */
171#define CST4319_PALDO_EXTPNP 0x00010000
172#define CST4319_CBUCK_MODE_MASK 0x00060000
173#define CST4319_CBUCK_MODE_BURST 0x00020000
174#define CST4319_CBUCK_MODE_LPBURST 0x00060000
175#define CST4319_RCAL_VALID 0x01000000
176#define CST4319_RCAL_VALUE_MASK 0x3e000000
177#define CST4319_RCAL_VALUE_SHIFT 25
178
179/* 4336 chip-specific ChipStatus register bits */
180#define CST4336_SPI_MODE_MASK 0x00000001
181#define CST4336_SPROM_PRESENT 0x00000002
182#define CST4336_OTP_PRESENT 0x00000004
183#define CST4336_ARMREMAP_0 0x00000008
184#define CST4336_ILPDIV_EN_MASK 0x00000010
185#define CST4336_ILPDIV_EN_SHIFT 4
186#define CST4336_XTAL_PD_POL_MASK 0x00000020
187#define CST4336_XTAL_PD_POL_SHIFT 5
188#define CST4336_LPO_SEL_MASK 0x00000040
189#define CST4336_LPO_SEL_SHIFT 6
190#define CST4336_RES_INIT_MODE_MASK 0x00000180
191#define CST4336_RES_INIT_MODE_SHIFT 7
192#define CST4336_CBUCK_MODE_MASK 0x00000600
193#define CST4336_CBUCK_MODE_SHIFT 9
194
195/* 4313 chip-specific ChipStatus register bits */
196#define CST4313_SPROM_PRESENT 1
197#define CST4313_OTP_PRESENT 2
198#define CST4313_SPROM_OTP_SEL_MASK 0x00000002
199#define CST4313_SPROM_OTP_SEL_SHIFT 0
200
201/* 4313 Chip specific ChipControl register bits */
202 /* 12 mA drive strengh for later 4313 */
203#define CCTRL_4313_12MA_LED_DRIVE 0x00000007
204
205/* Manufacturer Ids */
206#define MFGID_ARM 0x43b
207#define MFGID_BRCM 0x4bf
208#define MFGID_MIPS 0x4a7
209
210/* Enumeration ROM registers */
211#define ER_EROMENTRY 0x000
212#define ER_REMAPCONTROL 0xe00
213#define ER_REMAPSELECT 0xe04
214#define ER_MASTERSELECT 0xe10
215#define ER_ITCR 0xf00
216#define ER_ITIP 0xf04
217
218/* Erom entries */
219#define ER_TAG 0xe
220#define ER_TAG1 0x6
221#define ER_VALID 1
222#define ER_CI 0
223#define ER_MP 2
224#define ER_ADD 4
225#define ER_END 0xe
226#define ER_BAD 0xffffffff
227
228/* EROM CompIdentA */
229#define CIA_MFG_MASK 0xfff00000
230#define CIA_MFG_SHIFT 20
231#define CIA_CID_MASK 0x000fff00
232#define CIA_CID_SHIFT 8
233#define CIA_CCL_MASK 0x000000f0
234#define CIA_CCL_SHIFT 4
235
236/* EROM CompIdentB */
237#define CIB_REV_MASK 0xff000000
238#define CIB_REV_SHIFT 24
239#define CIB_NSW_MASK 0x00f80000
240#define CIB_NSW_SHIFT 19
241#define CIB_NMW_MASK 0x0007c000
242#define CIB_NMW_SHIFT 14
243#define CIB_NSP_MASK 0x00003e00
244#define CIB_NSP_SHIFT 9
245#define CIB_NMP_MASK 0x000001f0
246#define CIB_NMP_SHIFT 4
247
248/* EROM AddrDesc */
249#define AD_ADDR_MASK 0xfffff000
250#define AD_SP_MASK 0x00000f00
251#define AD_SP_SHIFT 8
252#define AD_ST_MASK 0x000000c0
253#define AD_ST_SHIFT 6
254#define AD_ST_SLAVE 0x00000000
255#define AD_ST_BRIDGE 0x00000040
256#define AD_ST_SWRAP 0x00000080
257#define AD_ST_MWRAP 0x000000c0
258#define AD_SZ_MASK 0x00000030
259#define AD_SZ_SHIFT 4
260#define AD_SZ_4K 0x00000000
261#define AD_SZ_8K 0x00000010
262#define AD_SZ_16K 0x00000020
263#define AD_SZ_SZD 0x00000030
264#define AD_AG32 0x00000008
265#define AD_ADDR_ALIGN 0x00000fff
266#define AD_SZ_BASE 0x00001000 /* 4KB */
267
268/* EROM SizeDesc */
269#define SD_SZ_MASK 0xfffff000
270#define SD_SG32 0x00000008
271#define SD_SZ_ALIGN 0x00000fff
272
273/* PCI config space bit 4 for 4306c0 slow clock source */
274#define PCI_CFG_GPIO_SCS 0x10
275/* PCI config space GPIO 14 for Xtal power-up */
276#define PCI_CFG_GPIO_XTAL 0x40
277/* PCI config space GPIO 15 for PLL power-down */
278#define PCI_CFG_GPIO_PLL 0x80
279
280/* power control defines */
281#define PLL_DELAY 150 /* us pll on delay */
282#define FREF_DELAY 200 /* us fref change delay */
283#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
284
285/* resetctrl */
286#define AIRC_RESET 1
287
288#define NOREV -1 /* Invalid rev */
289
290/* GPIO Based LED powersave defines */
291#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
292#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
293
294/* When Srom support present, fields in sromcontrol */
295#define SRC_START 0x80000000
296#define SRC_BUSY 0x80000000
297#define SRC_OPCODE 0x60000000
298#define SRC_OP_READ 0x00000000
299#define SRC_OP_WRITE 0x20000000
300#define SRC_OP_WRDIS 0x40000000
301#define SRC_OP_WREN 0x60000000
302#define SRC_OTPSEL 0x00000010
303#define SRC_LOCK 0x00000008
304#define SRC_SIZE_MASK 0x00000006
305#define SRC_SIZE_1K 0x00000000
306#define SRC_SIZE_4K 0x00000002
307#define SRC_SIZE_16K 0x00000004
308#define SRC_SIZE_SHIFT 1
309#define SRC_PRESENT 0x00000001
310
311/* External PA enable mask */
312#define GPIO_CTRL_EPA_EN_MASK 0x40
313
314#define DEFAULT_GPIOTIMERVAL \
315 ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
316
317#define BADIDX (SI_MAXCORES + 1)
318
319/* Newer chips can access PCI/PCIE and CC core without requiring to change
320 * PCI BAR0 WIN
321 */
322#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
323 (((si)->pub.buscoretype == PCI_CORE_ID) && \
324 (si)->pub.buscorerev >= 13))
325
326#define CCREGS_FAST(si) (((char __iomem *)((si)->curmap) + \
327 PCI_16KB0_CCREGS_OFFSET))
328
329#define IS_SIM(chippkg) \
330 ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
331
332/*
333 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
334 * before after core switching to avoid invalid register accesss inside ISR.
335 */
336#define INTR_OFF(si, intr_val) \
337 if ((si)->intrsoff_fn && \
338 (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
339 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg)
340
341#define INTR_RESTORE(si, intr_val) \
342 if ((si)->intrsrestore_fn && \
343 (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
344 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val)
345
346#define PCI(si) ((si)->pub.buscoretype == PCI_CORE_ID)
347#define PCIE(si) ((si)->pub.buscoretype == PCIE_CORE_ID)
348
349#define PCI_FORCEHT(si) (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
350
351#ifdef BCMDBG
352#define SI_MSG(args) printk args
353#else
354#define SI_MSG(args)
355#endif /* BCMDBG */
356
357#define GOODCOREADDR(x, b) \
358 (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
359 IS_ALIGNED((x), SI_CORE_SIZE))
360
361#define PCIEREGS(si) ((__iomem char *)((si)->curmap) + \
362 PCI_16KB0_PCIREGS_OFFSET)
363
364struct aidmp {
365 u32 oobselina30; /* 0x000 */
366 u32 oobselina74; /* 0x004 */
367 u32 PAD[6];
368 u32 oobselinb30; /* 0x020 */
369 u32 oobselinb74; /* 0x024 */
370 u32 PAD[6];
371 u32 oobselinc30; /* 0x040 */
372 u32 oobselinc74; /* 0x044 */
373 u32 PAD[6];
374 u32 oobselind30; /* 0x060 */
375 u32 oobselind74; /* 0x064 */
376 u32 PAD[38];
377 u32 oobselouta30; /* 0x100 */
378 u32 oobselouta74; /* 0x104 */
379 u32 PAD[6];
380 u32 oobseloutb30; /* 0x120 */
381 u32 oobseloutb74; /* 0x124 */
382 u32 PAD[6];
383 u32 oobseloutc30; /* 0x140 */
384 u32 oobseloutc74; /* 0x144 */
385 u32 PAD[6];
386 u32 oobseloutd30; /* 0x160 */
387 u32 oobseloutd74; /* 0x164 */
388 u32 PAD[38];
389 u32 oobsynca; /* 0x200 */
390 u32 oobseloutaen; /* 0x204 */
391 u32 PAD[6];
392 u32 oobsyncb; /* 0x220 */
393 u32 oobseloutben; /* 0x224 */
394 u32 PAD[6];
395 u32 oobsyncc; /* 0x240 */
396 u32 oobseloutcen; /* 0x244 */
397 u32 PAD[6];
398 u32 oobsyncd; /* 0x260 */
399 u32 oobseloutden; /* 0x264 */
400 u32 PAD[38];
401 u32 oobaextwidth; /* 0x300 */
402 u32 oobainwidth; /* 0x304 */
403 u32 oobaoutwidth; /* 0x308 */
404 u32 PAD[5];
405 u32 oobbextwidth; /* 0x320 */
406 u32 oobbinwidth; /* 0x324 */
407 u32 oobboutwidth; /* 0x328 */
408 u32 PAD[5];
409 u32 oobcextwidth; /* 0x340 */
410 u32 oobcinwidth; /* 0x344 */
411 u32 oobcoutwidth; /* 0x348 */
412 u32 PAD[5];
413 u32 oobdextwidth; /* 0x360 */
414 u32 oobdinwidth; /* 0x364 */
415 u32 oobdoutwidth; /* 0x368 */
416 u32 PAD[37];
417 u32 ioctrlset; /* 0x400 */
418 u32 ioctrlclear; /* 0x404 */
419 u32 ioctrl; /* 0x408 */
420 u32 PAD[61];
421 u32 iostatus; /* 0x500 */
422 u32 PAD[127];
423 u32 ioctrlwidth; /* 0x700 */
424 u32 iostatuswidth; /* 0x704 */
425 u32 PAD[62];
426 u32 resetctrl; /* 0x800 */
427 u32 resetstatus; /* 0x804 */
428 u32 resetreadid; /* 0x808 */
429 u32 resetwriteid; /* 0x80c */
430 u32 PAD[60];
431 u32 errlogctrl; /* 0x900 */
432 u32 errlogdone; /* 0x904 */
433 u32 errlogstatus; /* 0x908 */
434 u32 errlogaddrlo; /* 0x90c */
435 u32 errlogaddrhi; /* 0x910 */
436 u32 errlogid; /* 0x914 */
437 u32 errloguser; /* 0x918 */
438 u32 errlogflags; /* 0x91c */
439 u32 PAD[56];
440 u32 intstatus; /* 0xa00 */
441 u32 PAD[127];
442 u32 config; /* 0xe00 */
443 u32 PAD[63];
444 u32 itcr; /* 0xf00 */
445 u32 PAD[3];
446 u32 itipooba; /* 0xf10 */
447 u32 itipoobb; /* 0xf14 */
448 u32 itipoobc; /* 0xf18 */
449 u32 itipoobd; /* 0xf1c */
450 u32 PAD[4];
451 u32 itipoobaout; /* 0xf30 */
452 u32 itipoobbout; /* 0xf34 */
453 u32 itipoobcout; /* 0xf38 */
454 u32 itipoobdout; /* 0xf3c */
455 u32 PAD[4];
456 u32 itopooba; /* 0xf50 */
457 u32 itopoobb; /* 0xf54 */
458 u32 itopoobc; /* 0xf58 */
459 u32 itopoobd; /* 0xf5c */
460 u32 PAD[4];
461 u32 itopoobain; /* 0xf70 */
462 u32 itopoobbin; /* 0xf74 */
463 u32 itopoobcin; /* 0xf78 */
464 u32 itopoobdin; /* 0xf7c */
465 u32 PAD[4];
466 u32 itopreset; /* 0xf90 */
467 u32 PAD[15];
468 u32 peripherialid4; /* 0xfd0 */
469 u32 peripherialid5; /* 0xfd4 */
470 u32 peripherialid6; /* 0xfd8 */
471 u32 peripherialid7; /* 0xfdc */
472 u32 peripherialid0; /* 0xfe0 */
473 u32 peripherialid1; /* 0xfe4 */
474 u32 peripherialid2; /* 0xfe8 */
475 u32 peripherialid3; /* 0xfec */
476 u32 componentid0; /* 0xff0 */
477 u32 componentid1; /* 0xff4 */
478 u32 componentid2; /* 0xff8 */
479 u32 componentid3; /* 0xffc */
480};
481
482/* EROM parsing */
483
484static u32
485get_erom_ent(struct si_pub *sih, u32 __iomem **eromptr, u32 mask, u32 match)
486{
487 u32 ent;
488 uint inv = 0, nom = 0;
489
490 while (true) {
491 ent = R_REG(*eromptr);
492 (*eromptr)++;
493
494 if (mask == 0)
495 break;
496
497 if ((ent & ER_VALID) == 0) {
498 inv++;
499 continue;
500 }
501
502 if (ent == (ER_END | ER_VALID))
503 break;
504
505 if ((ent & mask) == match)
506 break;
507
508 nom++;
509 }
510
511 return ent;
512}
513
514static u32
515get_asd(struct si_pub *sih, u32 __iomem **eromptr, uint sp, uint ad, uint st,
516 u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
517{
518 u32 asd, sz, szd;
519
520 asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
521 if (((asd & ER_TAG1) != ER_ADD) ||
522 (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
523 ((asd & AD_ST_MASK) != st)) {
524 /* This is not what we want, "push" it back */
525 (*eromptr)--;
526 return 0;
527 }
528 *addrl = asd & AD_ADDR_MASK;
529 if (asd & AD_AG32)
530 *addrh = get_erom_ent(sih, eromptr, 0, 0);
531 else
532 *addrh = 0;
533 *sizeh = 0;
534 sz = asd & AD_SZ_MASK;
535 if (sz == AD_SZ_SZD) {
536 szd = get_erom_ent(sih, eromptr, 0, 0);
537 *sizel = szd & SD_SZ_MASK;
538 if (szd & SD_SG32)
539 *sizeh = get_erom_ent(sih, eromptr, 0, 0);
540 } else
541 *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
542
543 return asd;
544}
545
546static void ai_hwfixup(struct si_info *sii)
547{
548}
549
550/* parse the enumeration rom to identify all cores */
551static void ai_scan(struct si_pub *sih, struct chipcregs __iomem *cc)
552{
553 struct si_info *sii = (struct si_info *)sih;
554
555 u32 erombase;
556 u32 __iomem *eromptr, *eromlim;
557 void __iomem *regs = cc;
558
559 erombase = R_REG(&cc->eromptr);
560
561 /* Set wrappers address */
562 sii->curwrap = (void *)((unsigned long)cc + SI_CORE_SIZE);
563
564 /* Now point the window at the erom */
565 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, erombase);
566 eromptr = regs;
567 eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
568
569 while (eromptr < eromlim) {
570 u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
571 u32 mpd, asd, addrl, addrh, sizel, sizeh;
572 u32 __iomem *base;
573 uint i, j, idx;
574 bool br;
575
576 br = false;
577
578 /* Grok a component */
579 cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
580 if (cia == (ER_END | ER_VALID)) {
581 /* Found END of erom */
582 ai_hwfixup(sii);
583 return;
584 }
585 base = eromptr - 1;
586 cib = get_erom_ent(sih, &eromptr, 0, 0);
587
588 if ((cib & ER_TAG) != ER_CI) {
589 /* CIA not followed by CIB */
590 goto error;
591 }
592
593 cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
594 mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
595 crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
596 nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
597 nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
598 nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
599 nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
600
601 if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
602 continue;
603 if ((nmw + nsw == 0)) {
604 /* A component which is not a core */
605 if (cid == OOB_ROUTER_CORE_ID) {
606 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
607 &addrl, &addrh, &sizel, &sizeh);
608 if (asd != 0)
609 sii->oob_router = addrl;
610 }
611 continue;
612 }
613
614 idx = sii->numcores;
615/* sii->eromptr[idx] = base; */
616 sii->cia[idx] = cia;
617 sii->cib[idx] = cib;
618 sii->coreid[idx] = cid;
619
620 for (i = 0; i < nmp; i++) {
621 mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
622 if ((mpd & ER_TAG) != ER_MP) {
623 /* Not enough MP entries for component */
624 goto error;
625 }
626 }
627
628 /* First Slave Address Descriptor should be port 0:
629 * the main register space for the core
630 */
631 asd =
632 get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
633 &sizel, &sizeh);
634 if (asd == 0) {
635 /* Try again to see if it is a bridge */
636 asd =
637 get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
638 &addrh, &sizel, &sizeh);
639 if (asd != 0)
640 br = true;
641 else if ((addrh != 0) || (sizeh != 0)
642 || (sizel != SI_CORE_SIZE)) {
643 /* First Slave ASD for core malformed */
644 goto error;
645 }
646 }
647 sii->coresba[idx] = addrl;
648 sii->coresba_size[idx] = sizel;
649 /* Get any more ASDs in port 0 */
650 j = 1;
651 do {
652 asd =
653 get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
654 &addrh, &sizel, &sizeh);
655 if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
656 sii->coresba2[idx] = addrl;
657 sii->coresba2_size[idx] = sizel;
658 }
659 j++;
660 } while (asd != 0);
661
662 /* Go through the ASDs for other slave ports */
663 for (i = 1; i < nsp; i++) {
664 j = 0;
665 do {
666 asd =
667 get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
668 &addrl, &addrh, &sizel, &sizeh);
669 } while (asd != 0);
670 if (j == 0) {
671 /* SP has no address descriptors */
672 goto error;
673 }
674 }
675
676 /* Now get master wrappers */
677 for (i = 0; i < nmw; i++) {
678 asd =
679 get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
680 &addrh, &sizel, &sizeh);
681 if (asd == 0) {
682 /* Missing descriptor for MW */
683 goto error;
684 }
685 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
686 /* Master wrapper %d is not 4KB */
687 goto error;
688 }
689 if (i == 0)
690 sii->wrapba[idx] = addrl;
691 }
692
693 /* And finally slave wrappers */
694 for (i = 0; i < nsw; i++) {
695 uint fwp = (nsp == 1) ? 0 : 1;
696 asd =
697 get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
698 &addrl, &addrh, &sizel, &sizeh);
699 if (asd == 0) {
700 /* Missing descriptor for SW */
701 goto error;
702 }
703 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
704 /* Slave wrapper is not 4KB */
705 goto error;
706 }
707 if ((nmw == 0) && (i == 0))
708 sii->wrapba[idx] = addrl;
709 }
710
711 /* Don't record bridges */
712 if (br)
713 continue;
714
715 /* Done with core */
716 sii->numcores++;
717 }
718
719 error:
720 /* Reached end of erom without finding END */
721 sii->numcores = 0;
722 return;
723}
724
725/*
726 * This function changes the logical "focus" to the indicated core.
727 * Return the current core's virtual address. Since each core starts with the
728 * same set of registers (BIST, clock control, etc), the returned address
729 * contains the first register of this 'common' register block (not to be
730 * confused with 'common core').
731 */
732void __iomem *ai_setcoreidx(struct si_pub *sih, uint coreidx)
733{
734 struct si_info *sii = (struct si_info *)sih;
735 u32 addr = sii->coresba[coreidx];
736 u32 wrap = sii->wrapba[coreidx];
737
738 if (coreidx >= sii->numcores)
739 return NULL;
740
741 /* point bar0 window */
742 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, addr);
743 /* point bar0 2nd 4KB window */
744 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN2, wrap);
745 sii->curidx = coreidx;
746
747 return sii->curmap;
748}
749
750/* Return the number of address spaces in current core */
751int ai_numaddrspaces(struct si_pub *sih)
752{
753 return 2;
754}
755
756/* Return the address of the nth address space in the current core */
757u32 ai_addrspace(struct si_pub *sih, uint asidx)
758{
759 struct si_info *sii;
760 uint cidx;
761
762 sii = (struct si_info *)sih;
763 cidx = sii->curidx;
764
765 if (asidx == 0)
766 return sii->coresba[cidx];
767 else if (asidx == 1)
768 return sii->coresba2[cidx];
769 else {
770 /* Need to parse the erom again to find addr space */
771 return 0;
772 }
773}
774
775/* Return the size of the nth address space in the current core */
776u32 ai_addrspacesize(struct si_pub *sih, uint asidx)
777{
778 struct si_info *sii;
779 uint cidx;
780
781 sii = (struct si_info *)sih;
782 cidx = sii->curidx;
783
784 if (asidx == 0)
785 return sii->coresba_size[cidx];
786 else if (asidx == 1)
787 return sii->coresba2_size[cidx];
788 else {
789 /* Need to parse the erom again to find addr */
790 return 0;
791 }
792}
793
794uint ai_flag(struct si_pub *sih)
795{
796 struct si_info *sii;
797 struct aidmp *ai;
798
799 sii = (struct si_info *)sih;
800 ai = sii->curwrap;
801
802 return R_REG(&ai->oobselouta30) & 0x1f;
803}
804
805void ai_setint(struct si_pub *sih, int siflag)
806{
807}
808
809uint ai_corevendor(struct si_pub *sih)
810{
811 struct si_info *sii;
812 u32 cia;
813
814 sii = (struct si_info *)sih;
815 cia = sii->cia[sii->curidx];
816 return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
817}
818
819uint ai_corerev(struct si_pub *sih)
820{
821 struct si_info *sii;
822 u32 cib;
823
824 sii = (struct si_info *)sih;
825 cib = sii->cib[sii->curidx];
826 return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
827}
828
829bool ai_iscoreup(struct si_pub *sih)
830{
831 struct si_info *sii;
832 struct aidmp *ai;
833
834 sii = (struct si_info *)sih;
835 ai = sii->curwrap;
836
837 return (((R_REG(&ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
838 SICF_CLOCK_EN)
839 && ((R_REG(&ai->resetctrl) & AIRC_RESET) == 0));
840}
841
842void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val)
843{
844 struct si_info *sii;
845 struct aidmp *ai;
846 u32 w;
847
848 sii = (struct si_info *)sih;
849
850 ai = sii->curwrap;
851
852 if (mask || val) {
853 w = ((R_REG(&ai->ioctrl) & ~mask) | val);
854 W_REG(&ai->ioctrl, w);
855 }
856}
857
858u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val)
859{
860 struct si_info *sii;
861 struct aidmp *ai;
862 u32 w;
863
864 sii = (struct si_info *)sih;
865 ai = sii->curwrap;
866
867 if (mask || val) {
868 w = ((R_REG(&ai->ioctrl) & ~mask) | val);
869 W_REG(&ai->ioctrl, w);
870 }
871
872 return R_REG(&ai->ioctrl);
873}
874
875/* return true if PCIE capability exists in the pci config space */
876static bool ai_ispcie(struct si_info *sii)
877{
878 u8 cap_ptr;
879
880 cap_ptr =
881 pcicore_find_pci_capability(sii->pbus, PCI_CAP_ID_EXP, NULL,
882 NULL);
883 if (!cap_ptr)
884 return false;
885
886 return true;
887}
888
889static bool ai_buscore_prep(struct si_info *sii)
890{
891 /* kludge to enable the clock on the 4306 which lacks a slowclock */
892 if (!ai_ispcie(sii))
893 ai_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
894 return true;
895}
896
897u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val)
898{
899 struct si_info *sii;
900 struct aidmp *ai;
901 u32 w;
902
903 sii = (struct si_info *)sih;
904 ai = sii->curwrap;
905
906 if (mask || val) {
907 w = ((R_REG(&ai->iostatus) & ~mask) | val);
908 W_REG(&ai->iostatus, w);
909 }
910
911 return R_REG(&ai->iostatus);
912}
913
914static bool
915ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
916{
917 bool pci, pcie;
918 uint i;
919 uint pciidx, pcieidx, pcirev, pcierev;
920 struct chipcregs __iomem *cc;
921
922 cc = ai_setcoreidx(&sii->pub, SI_CC_IDX);
923
924 /* get chipcommon rev */
925 sii->pub.ccrev = (int)ai_corerev(&sii->pub);
926
927 /* get chipcommon chipstatus */
928 if (sii->pub.ccrev >= 11)
929 sii->pub.chipst = R_REG(&cc->chipstatus);
930
931 /* get chipcommon capabilites */
932 sii->pub.cccaps = R_REG(&cc->capabilities);
933 /* get chipcommon extended capabilities */
934
935 if (sii->pub.ccrev >= 35)
936 sii->pub.cccaps_ext = R_REG(&cc->capabilities_ext);
937
938 /* get pmu rev and caps */
939 if (sii->pub.cccaps & CC_CAP_PMU) {
940 sii->pub.pmucaps = R_REG(&cc->pmucapabilities);
941 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
942 }
943
944 /* figure out bus/orignal core idx */
945 sii->pub.buscoretype = NODEV_CORE_ID;
946 sii->pub.buscorerev = NOREV;
947 sii->pub.buscoreidx = BADIDX;
948
949 pci = pcie = false;
950 pcirev = pcierev = NOREV;
951 pciidx = pcieidx = BADIDX;
952
953 for (i = 0; i < sii->numcores; i++) {
954 uint cid, crev;
955
956 ai_setcoreidx(&sii->pub, i);
957 cid = ai_coreid(&sii->pub);
958 crev = ai_corerev(&sii->pub);
959
960 if (cid == PCI_CORE_ID) {
961 pciidx = i;
962 pcirev = crev;
963 pci = true;
964 } else if (cid == PCIE_CORE_ID) {
965 pcieidx = i;
966 pcierev = crev;
967 pcie = true;
968 }
969
970 /* find the core idx before entering this func. */
971 if ((savewin && (savewin == sii->coresba[i])) ||
972 (cc == sii->regs[i]))
973 *origidx = i;
974 }
975
976 if (pci && pcie) {
977 if (ai_ispcie(sii))
978 pci = false;
979 else
980 pcie = false;
981 }
982 if (pci) {
983 sii->pub.buscoretype = PCI_CORE_ID;
984 sii->pub.buscorerev = pcirev;
985 sii->pub.buscoreidx = pciidx;
986 } else if (pcie) {
987 sii->pub.buscoretype = PCIE_CORE_ID;
988 sii->pub.buscorerev = pcierev;
989 sii->pub.buscoreidx = pcieidx;
990 }
991
992 /* fixup necessary chip/core configurations */
993 if (SI_FAST(sii)) {
994 if (!sii->pch) {
995 sii->pch = pcicore_init(&sii->pub, sii->pbus,
996 (__iomem void *)PCIEREGS(sii));
997 if (sii->pch == NULL)
998 return false;
999 }
1000 }
1001 if (ai_pci_fixcfg(&sii->pub)) {
1002 /* si_doattach: si_pci_fixcfg failed */
1003 return false;
1004 }
1005
1006 /* return to the original core */
1007 ai_setcoreidx(&sii->pub, *origidx);
1008
1009 return true;
1010}
1011
1012/*
1013 * get boardtype and boardrev
1014 */
1015static __used void ai_nvram_process(struct si_info *sii)
1016{
1017 uint w = 0;
1018
1019 /* do a pci config read to get subsystem id and subvendor id */
1020 pci_read_config_dword(sii->pbus, PCI_SUBSYSTEM_VENDOR_ID, &w);
1021
1022 sii->pub.boardvendor = w & 0xffff;
1023 sii->pub.boardtype = (w >> 16) & 0xffff;
1024 sii->pub.boardflags = getintvar(&sii->pub, BRCMS_SROM_BOARDFLAGS);
1025}
1026
1027static struct si_info *ai_doattach(struct si_info *sii,
1028 void __iomem *regs, struct pci_dev *pbus)
1029{
1030 struct si_pub *sih = &sii->pub;
1031 u32 w, savewin;
1032 struct chipcregs __iomem *cc;
1033 uint socitype;
1034 uint origidx;
1035
1036 memset((unsigned char *) sii, 0, sizeof(struct si_info));
1037
1038 savewin = 0;
1039
1040 sih->buscoreidx = BADIDX;
1041
1042 sii->curmap = regs;
1043 sii->pbus = pbus;
1044
1045 /* find Chipcommon address */
1046 pci_read_config_dword(sii->pbus, PCI_BAR0_WIN, &savewin);
1047 if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
1048 savewin = SI_ENUM_BASE;
1049
1050 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN,
1051 SI_ENUM_BASE);
1052 cc = (struct chipcregs __iomem *) regs;
1053
1054 /* bus/core/clk setup for register access */
1055 if (!ai_buscore_prep(sii))
1056 return NULL;
1057
1058 /*
1059 * ChipID recognition.
1060 * We assume we can read chipid at offset 0 from the regs arg.
1061 * If we add other chiptypes (or if we need to support old sdio
1062 * hosts w/o chipcommon), some way of recognizing them needs to
1063 * be added here.
1064 */
1065 w = R_REG(&cc->chipid);
1066 socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
1067 /* Might as wll fill in chip id rev & pkg */
1068 sih->chip = w & CID_ID_MASK;
1069 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
1070 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
1071
1072 sih->issim = false;
1073
1074 /* scan for cores */
1075 if (socitype == SOCI_AI) {
1076 SI_MSG(("Found chip type AI (0x%08x)\n", w));
1077 /* pass chipc address instead of original core base */
1078 ai_scan(&sii->pub, cc);
1079 } else {
1080 /* Found chip of unknown type */
1081 return NULL;
1082 }
1083 /* no cores found, bail out */
1084 if (sii->numcores == 0)
1085 return NULL;
1086
1087 /* bus/core/clk setup */
1088 origidx = SI_CC_IDX;
1089 if (!ai_buscore_setup(sii, savewin, &origidx))
1090 goto exit;
1091
1092 /* Init nvram from sprom/otp if they exist */
1093 if (srom_var_init(&sii->pub, cc))
1094 goto exit;
1095
1096 ai_nvram_process(sii);
1097
1098 /* === NVRAM, clock is ready === */
1099 cc = (struct chipcregs __iomem *) ai_setcore(sih, CC_CORE_ID, 0);
1100 W_REG(&cc->gpiopullup, 0);
1101 W_REG(&cc->gpiopulldown, 0);
1102 ai_setcoreidx(sih, origidx);
1103
1104 /* PMU specific initializations */
1105 if (sih->cccaps & CC_CAP_PMU) {
1106 u32 xtalfreq;
1107 si_pmu_init(sih);
1108 si_pmu_chip_init(sih);
1109
1110 xtalfreq = si_pmu_measure_alpclk(sih);
1111 si_pmu_pll_init(sih, xtalfreq);
1112 si_pmu_res_init(sih);
1113 si_pmu_swreg_init(sih);
1114 }
1115
1116 /* setup the GPIO based LED powersave register */
1117 w = getintvar(sih, BRCMS_SROM_LEDDC);
1118 if (w == 0)
1119 w = DEFAULT_GPIOTIMERVAL;
1120 ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, gpiotimerval),
1121 ~0, w);
1122
1123 if (PCIE(sii))
1124 pcicore_attach(sii->pch, SI_DOATTACH);
1125
1126 if (sih->chip == BCM43224_CHIP_ID) {
1127 /*
1128 * enable 12 mA drive strenth for 43224 and
1129 * set chipControl register bit 15
1130 */
1131 if (sih->chiprev == 0) {
1132 SI_MSG(("Applying 43224A0 WARs\n"));
1133 ai_corereg(sih, SI_CC_IDX,
1134 offsetof(struct chipcregs, chipcontrol),
1135 CCTRL43224_GPIO_TOGGLE,
1136 CCTRL43224_GPIO_TOGGLE);
1137 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
1138 CCTRL_43224A0_12MA_LED_DRIVE);
1139 }
1140 if (sih->chiprev >= 1) {
1141 SI_MSG(("Applying 43224B0+ WARs\n"));
1142 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
1143 CCTRL_43224B0_12MA_LED_DRIVE);
1144 }
1145 }
1146
1147 if (sih->chip == BCM4313_CHIP_ID) {
1148 /*
1149 * enable 12 mA drive strenth for 4313 and
1150 * set chipControl register bit 1
1151 */
1152 SI_MSG(("Applying 4313 WARs\n"));
1153 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
1154 CCTRL_4313_12MA_LED_DRIVE);
1155 }
1156
1157 return sii;
1158
1159 exit:
1160 if (sii->pch)
1161 pcicore_deinit(sii->pch);
1162 sii->pch = NULL;
1163
1164 return NULL;
1165}
1166
1167/*
1168 * Allocate a si handle.
1169 * devid - pci device id (used to determine chip#)
1170 * osh - opaque OS handle
1171 * regs - virtual address of initial core registers
1172 */
1173struct si_pub *
1174ai_attach(void __iomem *regs, struct pci_dev *sdh)
1175{
1176 struct si_info *sii;
1177
1178 /* alloc struct si_info */
1179 sii = kmalloc(sizeof(struct si_info), GFP_ATOMIC);
1180 if (sii == NULL)
1181 return NULL;
1182
1183 if (ai_doattach(sii, regs, sdh) == NULL) {
1184 kfree(sii);
1185 return NULL;
1186 }
1187
1188 return (struct si_pub *) sii;
1189}
1190
1191/* may be called with core in reset */
1192void ai_detach(struct si_pub *sih)
1193{
1194 struct si_info *sii;
1195
1196 struct si_pub *si_local = NULL;
1197 memcpy(&si_local, &sih, sizeof(struct si_pub **));
1198
1199 sii = (struct si_info *)sih;
1200
1201 if (sii == NULL)
1202 return;
1203
1204 if (sii->pch)
1205 pcicore_deinit(sii->pch);
1206 sii->pch = NULL;
1207
1208 srom_free_vars(sih);
1209 kfree(sii);
1210}
1211
1212/* register driver interrupt disabling and restoring callback functions */
1213void
1214ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
1215 void *intrsrestore_fn,
1216 void *intrsenabled_fn, void *intr_arg)
1217{
1218 struct si_info *sii;
1219
1220 sii = (struct si_info *)sih;
1221 sii->intr_arg = intr_arg;
1222 sii->intrsoff_fn = (u32 (*)(void *)) intrsoff_fn;
1223 sii->intrsrestore_fn = (void (*) (void *, u32)) intrsrestore_fn;
1224 sii->intrsenabled_fn = (bool (*)(void *)) intrsenabled_fn;
1225 /* save current core id. when this function called, the current core
1226 * must be the core which provides driver functions(il, et, wl, etc.)
1227 */
1228 sii->dev_coreid = sii->coreid[sii->curidx];
1229}
1230
1231void ai_deregister_intr_callback(struct si_pub *sih)
1232{
1233 struct si_info *sii;
1234
1235 sii = (struct si_info *)sih;
1236 sii->intrsoff_fn = NULL;
1237}
1238
1239uint ai_coreid(struct si_pub *sih)
1240{
1241 struct si_info *sii;
1242
1243 sii = (struct si_info *)sih;
1244 return sii->coreid[sii->curidx];
1245}
1246
1247uint ai_coreidx(struct si_pub *sih)
1248{
1249 struct si_info *sii;
1250
1251 sii = (struct si_info *)sih;
1252 return sii->curidx;
1253}
1254
1255bool ai_backplane64(struct si_pub *sih)
1256{
1257 return (sih->cccaps & CC_CAP_BKPLN64) != 0;
1258}
1259
1260/* return index of coreid or BADIDX if not found */
1261uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit)
1262{
1263 struct si_info *sii;
1264 uint found;
1265 uint i;
1266
1267 sii = (struct si_info *)sih;
1268
1269 found = 0;
1270
1271 for (i = 0; i < sii->numcores; i++)
1272 if (sii->coreid[i] == coreid) {
1273 if (found == coreunit)
1274 return i;
1275 found++;
1276 }
1277
1278 return BADIDX;
1279}
1280
1281/*
1282 * This function changes logical "focus" to the indicated core;
1283 * must be called with interrupts off.
1284 * Moreover, callers should keep interrupts off during switching
1285 * out of and back to d11 core.
1286 */
1287void __iomem *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit)
1288{
1289 uint idx;
1290
1291 idx = ai_findcoreidx(sih, coreid, coreunit);
1292 if (idx >= SI_MAXCORES)
1293 return NULL;
1294
1295 return ai_setcoreidx(sih, idx);
1296}
1297
1298/* Turn off interrupt as required by ai_setcore, before switch core */
1299void __iomem *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
1300 uint *intr_val)
1301{
1302 void __iomem *cc;
1303 struct si_info *sii;
1304
1305 sii = (struct si_info *)sih;
1306
1307 if (SI_FAST(sii)) {
1308 /* Overloading the origidx variable to remember the coreid,
1309 * this works because the core ids cannot be confused with
1310 * core indices.
1311 */
1312 *origidx = coreid;
1313 if (coreid == CC_CORE_ID)
1314 return CCREGS_FAST(sii);
1315 else if (coreid == sih->buscoretype)
1316 return PCIEREGS(sii);
1317 }
1318 INTR_OFF(sii, *intr_val);
1319 *origidx = sii->curidx;
1320 cc = ai_setcore(sih, coreid, 0);
1321 return cc;
1322}
1323
1324/* restore coreidx and restore interrupt */
1325void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val)
1326{
1327 struct si_info *sii;
1328
1329 sii = (struct si_info *)sih;
1330 if (SI_FAST(sii)
1331 && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
1332 return;
1333
1334 ai_setcoreidx(sih, coreid);
1335 INTR_RESTORE(sii, intr_val);
1336}
1337
1338void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val)
1339{
1340 struct si_info *sii = (struct si_info *)sih;
1341 u32 *w = (u32 *) sii->curwrap;
1342 W_REG(w + (offset / 4), val);
1343 return;
1344}
1345
1346/*
1347 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set
1348 * operation, switch back to the original core, and return the new value.
1349 *
1350 * When using the silicon backplane, no fiddling with interrupts or core
1351 * switches is needed.
1352 *
1353 * Also, when using pci/pcie, we can optimize away the core switching for pci
1354 * registers and (on newer pci cores) chipcommon registers.
1355 */
1356uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
1357 uint val)
1358{
1359 uint origidx = 0;
1360 u32 __iomem *r = NULL;
1361 uint w;
1362 uint intr_val = 0;
1363 bool fast = false;
1364 struct si_info *sii;
1365
1366 sii = (struct si_info *)sih;
1367
1368 if (coreidx >= SI_MAXCORES)
1369 return 0;
1370
1371 /*
1372 * If pci/pcie, we can get at pci/pcie regs
1373 * and on newer cores to chipc
1374 */
1375 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
1376 /* Chipc registers are mapped at 12KB */
1377 fast = true;
1378 r = (u32 __iomem *)((__iomem char *)sii->curmap +
1379 PCI_16KB0_CCREGS_OFFSET + regoff);
1380 } else if (sii->pub.buscoreidx == coreidx) {
1381 /*
1382 * pci registers are at either in the last 2KB of
1383 * an 8KB window or, in pcie and pci rev 13 at 8KB
1384 */
1385 fast = true;
1386 if (SI_FAST(sii))
1387 r = (u32 __iomem *)((__iomem char *)sii->curmap +
1388 PCI_16KB0_PCIREGS_OFFSET + regoff);
1389 else
1390 r = (u32 __iomem *)((__iomem char *)sii->curmap +
1391 ((regoff >= SBCONFIGOFF) ?
1392 PCI_BAR0_PCISBR_OFFSET :
1393 PCI_BAR0_PCIREGS_OFFSET) + regoff);
1394 }
1395
1396 if (!fast) {
1397 INTR_OFF(sii, intr_val);
1398
1399 /* save current core index */
1400 origidx = ai_coreidx(&sii->pub);
1401
1402 /* switch core */
1403 r = (u32 __iomem *) ((unsigned char __iomem *)
1404 ai_setcoreidx(&sii->pub, coreidx) + regoff);
1405 }
1406
1407 /* mask and set */
1408 if (mask || val) {
1409 w = (R_REG(r) & ~mask) | val;
1410 W_REG(r, w);
1411 }
1412
1413 /* readback */
1414 w = R_REG(r);
1415
1416 if (!fast) {
1417 /* restore core index */
1418 if (origidx != coreidx)
1419 ai_setcoreidx(&sii->pub, origidx);
1420
1421 INTR_RESTORE(sii, intr_val);
1422 }
1423
1424 return w;
1425}
1426
1427void ai_core_disable(struct si_pub *sih, u32 bits)
1428{
1429 struct si_info *sii;
1430 u32 dummy;
1431 struct aidmp *ai;
1432
1433 sii = (struct si_info *)sih;
1434
1435 ai = sii->curwrap;
1436
1437 /* if core is already in reset, just return */
1438 if (R_REG(&ai->resetctrl) & AIRC_RESET)
1439 return;
1440
1441 W_REG(&ai->ioctrl, bits);
1442 dummy = R_REG(&ai->ioctrl);
1443 udelay(10);
1444
1445 W_REG(&ai->resetctrl, AIRC_RESET);
1446 udelay(1);
1447}
1448
1449/* reset and re-enable a core
1450 * inputs:
1451 * bits - core specific bits that are set during and after reset sequence
1452 * resetbits - core specific bits that are set only during reset sequence
1453 */
1454void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits)
1455{
1456 struct si_info *sii;
1457 struct aidmp *ai;
1458 u32 dummy;
1459
1460 sii = (struct si_info *)sih;
1461 ai = sii->curwrap;
1462
1463 /*
1464 * Must do the disable sequence first to work
1465 * for arbitrary current core state.
1466 */
1467 ai_core_disable(sih, (bits | resetbits));
1468
1469 /*
1470 * Now do the initialization sequence.
1471 */
1472 W_REG(&ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
1473 dummy = R_REG(&ai->ioctrl);
1474 W_REG(&ai->resetctrl, 0);
1475 udelay(1);
1476
1477 W_REG(&ai->ioctrl, (bits | SICF_CLOCK_EN));
1478 dummy = R_REG(&ai->ioctrl);
1479 udelay(1);
1480}
1481
1482/* return the slow clock source - LPO, XTAL, or PCI */
1483static uint ai_slowclk_src(struct si_info *sii)
1484{
1485 struct chipcregs __iomem *cc;
1486 u32 val;
1487
1488 if (sii->pub.ccrev < 6) {
1489 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT,
1490 &val);
1491 if (val & PCI_CFG_GPIO_SCS)
1492 return SCC_SS_PCI;
1493 return SCC_SS_XTAL;
1494 } else if (sii->pub.ccrev < 10) {
1495 cc = (struct chipcregs __iomem *)
1496 ai_setcoreidx(&sii->pub, sii->curidx);
1497 return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
1498 } else /* Insta-clock */
1499 return SCC_SS_XTAL;
1500}
1501
1502/*
1503* return the ILP (slowclock) min or max frequency
1504* precondition: we've established the chip has dynamic clk control
1505*/
1506static uint ai_slowclk_freq(struct si_info *sii, bool max_freq,
1507 struct chipcregs __iomem *cc)
1508{
1509 u32 slowclk;
1510 uint div;
1511
1512 slowclk = ai_slowclk_src(sii);
1513 if (sii->pub.ccrev < 6) {
1514 if (slowclk == SCC_SS_PCI)
1515 return max_freq ? (PCIMAXFREQ / 64)
1516 : (PCIMINFREQ / 64);
1517 else
1518 return max_freq ? (XTALMAXFREQ / 32)
1519 : (XTALMINFREQ / 32);
1520 } else if (sii->pub.ccrev < 10) {
1521 div = 4 *
1522 (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>
1523 SCC_CD_SHIFT) + 1);
1524 if (slowclk == SCC_SS_LPO)
1525 return max_freq ? LPOMAXFREQ : LPOMINFREQ;
1526 else if (slowclk == SCC_SS_XTAL)
1527 return max_freq ? (XTALMAXFREQ / div)
1528 : (XTALMINFREQ / div);
1529 else if (slowclk == SCC_SS_PCI)
1530 return max_freq ? (PCIMAXFREQ / div)
1531 : (PCIMINFREQ / div);
1532 } else {
1533 /* Chipc rev 10 is InstaClock */
1534 div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
1535 div = 4 * (div + 1);
1536 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
1537 }
1538 return 0;
1539}
1540
1541static void
1542ai_clkctl_setdelay(struct si_info *sii, struct chipcregs __iomem *cc)
1543{
1544 uint slowmaxfreq, pll_delay, slowclk;
1545 uint pll_on_delay, fref_sel_delay;
1546
1547 pll_delay = PLL_DELAY;
1548
1549 /*
1550 * If the slow clock is not sourced by the xtal then
1551 * add the xtal_on_delay since the xtal will also be
1552 * powered down by dynamic clk control logic.
1553 */
1554
1555 slowclk = ai_slowclk_src(sii);
1556 if (slowclk != SCC_SS_XTAL)
1557 pll_delay += XTAL_ON_DELAY;
1558
1559 /* Starting with 4318 it is ILP that is used for the delays */
1560 slowmaxfreq =
1561 ai_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc);
1562
1563 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
1564 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
1565
1566 W_REG(&cc->pll_on_delay, pll_on_delay);
1567 W_REG(&cc->fref_sel_delay, fref_sel_delay);
1568}
1569
1570/* initialize power control delay registers */
1571void ai_clkctl_init(struct si_pub *sih)
1572{
1573 struct si_info *sii;
1574 uint origidx = 0;
1575 struct chipcregs __iomem *cc;
1576 bool fast;
1577
1578 if (!(sih->cccaps & CC_CAP_PWR_CTL))
1579 return;
1580
1581 sii = (struct si_info *)sih;
1582 fast = SI_FAST(sii);
1583 if (!fast) {
1584 origidx = sii->curidx;
1585 cc = (struct chipcregs __iomem *)
1586 ai_setcore(sih, CC_CORE_ID, 0);
1587 if (cc == NULL)
1588 return;
1589 } else {
1590 cc = (struct chipcregs __iomem *) CCREGS_FAST(sii);
1591 if (cc == NULL)
1592 return;
1593 }
1594
1595 /* set all Instaclk chip ILP to 1 MHz */
1596 if (sih->ccrev >= 10)
1597 SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,
1598 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
1599
1600 ai_clkctl_setdelay(sii, cc);
1601
1602 if (!fast)
1603 ai_setcoreidx(sih, origidx);
1604}
1605
1606/*
1607 * return the value suitable for writing to the
1608 * dot11 core FAST_PWRUP_DELAY register
1609 */
1610u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
1611{
1612 struct si_info *sii;
1613 uint origidx = 0;
1614 struct chipcregs __iomem *cc;
1615 uint slowminfreq;
1616 u16 fpdelay;
1617 uint intr_val = 0;
1618 bool fast;
1619
1620 sii = (struct si_info *)sih;
1621 if (sih->cccaps & CC_CAP_PMU) {
1622 INTR_OFF(sii, intr_val);
1623 fpdelay = si_pmu_fast_pwrup_delay(sih);
1624 INTR_RESTORE(sii, intr_val);
1625 return fpdelay;
1626 }
1627
1628 if (!(sih->cccaps & CC_CAP_PWR_CTL))
1629 return 0;
1630
1631 fast = SI_FAST(sii);
1632 fpdelay = 0;
1633 if (!fast) {
1634 origidx = sii->curidx;
1635 INTR_OFF(sii, intr_val);
1636 cc = (struct chipcregs __iomem *)
1637 ai_setcore(sih, CC_CORE_ID, 0);
1638 if (cc == NULL)
1639 goto done;
1640 } else {
1641 cc = (struct chipcregs __iomem *) CCREGS_FAST(sii);
1642 if (cc == NULL)
1643 goto done;
1644 }
1645
1646 slowminfreq = ai_slowclk_freq(sii, false, cc);
1647 fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
1648 (slowminfreq - 1)) / slowminfreq;
1649
1650 done:
1651 if (!fast) {
1652 ai_setcoreidx(sih, origidx);
1653 INTR_RESTORE(sii, intr_val);
1654 }
1655 return fpdelay;
1656}
1657
1658/* turn primary xtal and/or pll off/on */
1659int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
1660{
1661 struct si_info *sii;
1662 u32 in, out, outen;
1663
1664 sii = (struct si_info *)sih;
1665
1666 /* pcie core doesn't have any mapping to control the xtal pu */
1667 if (PCIE(sii))
1668 return -1;
1669
1670 pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in);
1671 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, &out);
1672 pci_read_config_dword(sii->pbus, PCI_GPIO_OUTEN, &outen);
1673
1674 /*
1675 * Avoid glitching the clock if GPRS is already using it.
1676 * We can't actually read the state of the PLLPD so we infer it
1677 * by the value of XTAL_PU which *is* readable via gpioin.
1678 */
1679 if (on && (in & PCI_CFG_GPIO_XTAL))
1680 return 0;
1681
1682 if (what & XTAL)
1683 outen |= PCI_CFG_GPIO_XTAL;
1684 if (what & PLL)
1685 outen |= PCI_CFG_GPIO_PLL;
1686
1687 if (on) {
1688 /* turn primary xtal on */
1689 if (what & XTAL) {
1690 out |= PCI_CFG_GPIO_XTAL;
1691 if (what & PLL)
1692 out |= PCI_CFG_GPIO_PLL;
1693 pci_write_config_dword(sii->pbus,
1694 PCI_GPIO_OUT, out);
1695 pci_write_config_dword(sii->pbus,
1696 PCI_GPIO_OUTEN, outen);
1697 udelay(XTAL_ON_DELAY);
1698 }
1699
1700 /* turn pll on */
1701 if (what & PLL) {
1702 out &= ~PCI_CFG_GPIO_PLL;
1703 pci_write_config_dword(sii->pbus,
1704 PCI_GPIO_OUT, out);
1705 mdelay(2);
1706 }
1707 } else {
1708 if (what & XTAL)
1709 out &= ~PCI_CFG_GPIO_XTAL;
1710 if (what & PLL)
1711 out |= PCI_CFG_GPIO_PLL;
1712 pci_write_config_dword(sii->pbus,
1713 PCI_GPIO_OUT, out);
1714 pci_write_config_dword(sii->pbus,
1715 PCI_GPIO_OUTEN, outen);
1716 }
1717
1718 return 0;
1719}
1720
1721/* clk control mechanism through chipcommon, no policy checking */
1722static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
1723{
1724 uint origidx = 0;
1725 struct chipcregs __iomem *cc;
1726 u32 scc;
1727 uint intr_val = 0;
1728 bool fast = SI_FAST(sii);
1729
1730 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1731 if (sii->pub.ccrev < 6)
1732 return false;
1733
1734 if (!fast) {
1735 INTR_OFF(sii, intr_val);
1736 origidx = sii->curidx;
1737 cc = (struct chipcregs __iomem *)
1738 ai_setcore(&sii->pub, CC_CORE_ID, 0);
1739 } else {
1740 cc = (struct chipcregs __iomem *) CCREGS_FAST(sii);
1741 if (cc == NULL)
1742 goto done;
1743 }
1744
1745 if (!(sii->pub.cccaps & CC_CAP_PWR_CTL) && (sii->pub.ccrev < 20))
1746 goto done;
1747
1748 switch (mode) {
1749 case CLK_FAST: /* FORCEHT, fast (pll) clock */
1750 if (sii->pub.ccrev < 10) {
1751 /*
1752 * don't forget to force xtal back
1753 * on before we clear SCC_DYN_XTAL..
1754 */
1755 ai_clkctl_xtal(&sii->pub, XTAL, ON);
1756 SET_REG(&cc->slow_clk_ctl,
1757 (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
1758 } else if (sii->pub.ccrev < 20) {
1759 OR_REG(&cc->system_clk_ctl, SYCC_HR);
1760 } else {
1761 OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
1762 }
1763
1764 /* wait for the PLL */
1765 if (sii->pub.cccaps & CC_CAP_PMU) {
1766 u32 htavail = CCS_HTAVAIL;
1767 SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
1768 == 0), PMU_MAX_TRANSITION_DLY);
1769 } else {
1770 udelay(PLL_DELAY);
1771 }
1772 break;
1773
1774 case CLK_DYNAMIC: /* enable dynamic clock control */
1775 if (sii->pub.ccrev < 10) {
1776 scc = R_REG(&cc->slow_clk_ctl);
1777 scc &= ~(SCC_FS | SCC_IP | SCC_XC);
1778 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
1779 scc |= SCC_XC;
1780 W_REG(&cc->slow_clk_ctl, scc);
1781
1782 /*
1783 * for dynamic control, we have to
1784 * release our xtal_pu "force on"
1785 */
1786 if (scc & SCC_XC)
1787 ai_clkctl_xtal(&sii->pub, XTAL, OFF);
1788 } else if (sii->pub.ccrev < 20) {
1789 /* Instaclock */
1790 AND_REG(&cc->system_clk_ctl, ~SYCC_HR);
1791 } else {
1792 AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT);
1793 }
1794 break;
1795
1796 default:
1797 break;
1798 }
1799
1800 done:
1801 if (!fast) {
1802 ai_setcoreidx(&sii->pub, origidx);
1803 INTR_RESTORE(sii, intr_val);
1804 }
1805 return mode == CLK_FAST;
1806}
1807
1808/*
1809 * clock control policy function throught chipcommon
1810 *
1811 * set dynamic clk control mode (forceslow, forcefast, dynamic)
1812 * returns true if we are forcing fast clock
1813 * this is a wrapper over the next internal function
1814 * to allow flexible policy settings for outside caller
1815 */
1816bool ai_clkctl_cc(struct si_pub *sih, uint mode)
1817{
1818 struct si_info *sii;
1819
1820 sii = (struct si_info *)sih;
1821
1822 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1823 if (sih->ccrev < 6)
1824 return false;
1825
1826 if (PCI_FORCEHT(sii))
1827 return mode == CLK_FAST;
1828
1829 return _ai_clkctl_cc(sii, mode);
1830}
1831
1832/* Build device path */
1833int ai_devpath(struct si_pub *sih, char *path, int size)
1834{
1835 int slen;
1836
1837 if (!path || size <= 0)
1838 return -1;
1839
1840 slen = snprintf(path, (size_t) size, "pci/%u/%u/",
1841 ((struct si_info *)sih)->pbus->bus->number,
1842 PCI_SLOT(((struct pci_dev *)
1843 (((struct si_info *)(sih))->pbus))->devfn));
1844
1845 if (slen < 0 || slen >= size) {
1846 path[0] = '\0';
1847 return -1;
1848 }
1849
1850 return 0;
1851}
1852
1853void ai_pci_up(struct si_pub *sih)
1854{
1855 struct si_info *sii;
1856
1857 sii = (struct si_info *)sih;
1858
1859 if (PCI_FORCEHT(sii))
1860 _ai_clkctl_cc(sii, CLK_FAST);
1861
1862 if (PCIE(sii))
1863 pcicore_up(sii->pch, SI_PCIUP);
1864
1865}
1866
1867/* Unconfigure and/or apply various WARs when system is going to sleep mode */
1868void ai_pci_sleep(struct si_pub *sih)
1869{
1870 struct si_info *sii;
1871
1872 sii = (struct si_info *)sih;
1873
1874 pcicore_sleep(sii->pch);
1875}
1876
1877/* Unconfigure and/or apply various WARs when going down */
1878void ai_pci_down(struct si_pub *sih)
1879{
1880 struct si_info *sii;
1881
1882 sii = (struct si_info *)sih;
1883
1884 /* release FORCEHT since chip is going to "down" state */
1885 if (PCI_FORCEHT(sii))
1886 _ai_clkctl_cc(sii, CLK_DYNAMIC);
1887
1888 pcicore_down(sii->pch, SI_PCIDOWN);
1889}
1890
1891/*
1892 * Configure the pci core for pci client (NIC) action
1893 * coremask is the bitvec of cores by index to be enabled.
1894 */
1895void ai_pci_setup(struct si_pub *sih, uint coremask)
1896{
1897 struct si_info *sii;
1898 struct sbpciregs __iomem *regs = NULL;
1899 u32 siflag = 0, w;
1900 uint idx = 0;
1901
1902 sii = (struct si_info *)sih;
1903
1904 if (PCI(sii)) {
1905 /* get current core index */
1906 idx = sii->curidx;
1907
1908 /* we interrupt on this backplane flag number */
1909 siflag = ai_flag(sih);
1910
1911 /* switch over to pci core */
1912 regs = ai_setcoreidx(sih, sii->pub.buscoreidx);
1913 }
1914
1915 /*
1916 * Enable sb->pci interrupts. Assume
1917 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
1918 */
1919 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
1920 /* pci config write to set this core bit in PCIIntMask */
1921 pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w);
1922 w |= (coremask << PCI_SBIM_SHIFT);
1923 pci_write_config_dword(sii->pbus, PCI_INT_MASK, w);
1924 } else {
1925 /* set sbintvec bit for our flag number */
1926 ai_setint(sih, siflag);
1927 }
1928
1929 if (PCI(sii)) {
1930 pcicore_pci_setup(sii->pch, regs);
1931
1932 /* switch back to previous core */
1933 ai_setcoreidx(sih, idx);
1934 }
1935}
1936
1937/*
1938 * Fixup SROMless PCI device's configuration.
1939 * The current core may be changed upon return.
1940 */
1941int ai_pci_fixcfg(struct si_pub *sih)
1942{
1943 uint origidx;
1944 void __iomem *regs = NULL;
1945 struct si_info *sii = (struct si_info *)sih;
1946
1947 /* Fixup PI in SROM shadow area to enable the correct PCI core access */
1948 /* save the current index */
1949 origidx = ai_coreidx(&sii->pub);
1950
1951 /* check 'pi' is correct and fix it if not */
1952 regs = ai_setcore(&sii->pub, sii->pub.buscoretype, 0);
1953 if (sii->pub.buscoretype == PCIE_CORE_ID)
1954 pcicore_fixcfg_pcie(sii->pch,
1955 (struct sbpcieregs __iomem *)regs);
1956 else if (sii->pub.buscoretype == PCI_CORE_ID)
1957 pcicore_fixcfg_pci(sii->pch, (struct sbpciregs __iomem *)regs);
1958
1959 /* restore the original index */
1960 ai_setcoreidx(&sii->pub, origidx);
1961
1962 pcicore_hwup(sii->pch);
1963 return 0;
1964}
1965
1966/* mask&set gpiocontrol bits */
1967u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
1968{
1969 uint regoff;
1970
1971 regoff = offsetof(struct chipcregs, gpiocontrol);
1972 return ai_corereg(sih, SI_CC_IDX, regoff, mask, val);
1973}
1974
1975void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
1976{
1977 struct si_info *sii;
1978 struct chipcregs __iomem *cc;
1979 uint origidx;
1980 u32 val;
1981
1982 sii = (struct si_info *)sih;
1983 origidx = ai_coreidx(sih);
1984
1985 cc = (struct chipcregs __iomem *) ai_setcore(sih, CC_CORE_ID, 0);
1986
1987 val = R_REG(&cc->chipcontrol);
1988
1989 if (on) {
1990 if (sih->chippkg == 9 || sih->chippkg == 0xb)
1991 /* Ext PA Controls for 4331 12x9 Package */
1992 W_REG(&cc->chipcontrol, val |
1993 CCTRL4331_EXTPA_EN |
1994 CCTRL4331_EXTPA_ON_GPIO2_5);
1995 else
1996 /* Ext PA Controls for 4331 12x12 Package */
1997 W_REG(&cc->chipcontrol,
1998 val | CCTRL4331_EXTPA_EN);
1999 } else {
2000 val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
2001 W_REG(&cc->chipcontrol, val);
2002 }
2003
2004 ai_setcoreidx(sih, origidx);
2005}
2006
2007/* Enable BT-COEX & Ex-PA for 4313 */
2008void ai_epa_4313war(struct si_pub *sih)
2009{
2010 struct si_info *sii;
2011 struct chipcregs __iomem *cc;
2012 uint origidx;
2013
2014 sii = (struct si_info *)sih;
2015 origidx = ai_coreidx(sih);
2016
2017 cc = ai_setcore(sih, CC_CORE_ID, 0);
2018
2019 /* EPA Fix */
2020 W_REG(&cc->gpiocontrol,
2021 R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
2022
2023 ai_setcoreidx(sih, origidx);
2024}
2025
2026/* check if the device is removed */
2027bool ai_deviceremoved(struct si_pub *sih)
2028{
2029 u32 w;
2030 struct si_info *sii;
2031
2032 sii = (struct si_info *)sih;
2033
2034 pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);
2035 if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
2036 return true;
2037
2038 return false;
2039}
2040
2041bool ai_is_sprom_available(struct si_pub *sih)
2042{
2043 if (sih->ccrev >= 31) {
2044 struct si_info *sii;
2045 uint origidx;
2046 struct chipcregs __iomem *cc;
2047 u32 sromctrl;
2048
2049 if ((sih->cccaps & CC_CAP_SROM) == 0)
2050 return false;
2051
2052 sii = (struct si_info *)sih;
2053 origidx = sii->curidx;
2054 cc = ai_setcoreidx(sih, SI_CC_IDX);
2055 sromctrl = R_REG(&cc->sromcontrol);
2056 ai_setcoreidx(sih, origidx);
2057 return sromctrl & SRC_PRESENT;
2058 }
2059
2060 switch (sih->chip) {
2061 case BCM4313_CHIP_ID:
2062 return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
2063 default:
2064 return true;
2065 }
2066}
2067
2068bool ai_is_otp_disabled(struct si_pub *sih)
2069{
2070 switch (sih->chip) {
2071 case BCM4313_CHIP_ID:
2072 return (sih->chipst & CST4313_OTP_PRESENT) == 0;
2073 /* These chips always have their OTP on */
2074 case BCM43224_CHIP_ID:
2075 case BCM43225_CHIP_ID:
2076 default:
2077 return false;
2078 }
2079}
diff --git a/drivers/staging/brcm80211/brcmsmac/aiutils.h b/drivers/staging/brcm80211/brcmsmac/aiutils.h
deleted file mode 100644
index 106a7424a7c..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/aiutils.h
+++ /dev/null
@@ -1,378 +0,0 @@
1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_AIUTILS_H_
18#define _BRCM_AIUTILS_H_
19
20#include "types.h"
21
22/*
23 * SOC Interconnect Address Map.
24 * All regions may not exist on all chips.
25 */
26/* each core gets 4Kbytes for registers */
27#define SI_CORE_SIZE 0x1000
28/*
29 * Max cores (this is arbitrary, for software
30 * convenience and could be changed if we
31 * make any larger chips
32 */
33#define SI_MAXCORES 16
34
35/* Client Mode sb2pcitranslation2 size in bytes */
36#define SI_PCI_DMA_SZ 0x40000000
37
38/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
39#define SI_PCIE_DMA_H32 0x80000000
40
41/* core codes */
42#define NODEV_CORE_ID 0x700 /* Invalid coreid */
43#define CC_CORE_ID 0x800 /* chipcommon core */
44#define ILINE20_CORE_ID 0x801 /* iline20 core */
45#define SRAM_CORE_ID 0x802 /* sram core */
46#define SDRAM_CORE_ID 0x803 /* sdram core */
47#define PCI_CORE_ID 0x804 /* pci core */
48#define MIPS_CORE_ID 0x805 /* mips core */
49#define ENET_CORE_ID 0x806 /* enet mac core */
50#define CODEC_CORE_ID 0x807 /* v90 codec core */
51#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
52#define ADSL_CORE_ID 0x809 /* ADSL core */
53#define ILINE100_CORE_ID 0x80a /* iline100 core */
54#define IPSEC_CORE_ID 0x80b /* ipsec core */
55#define UTOPIA_CORE_ID 0x80c /* utopia core */
56#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
57#define SOCRAM_CORE_ID 0x80e /* internal memory core */
58#define MEMC_CORE_ID 0x80f /* memc sdram core */
59#define OFDM_CORE_ID 0x810 /* OFDM phy core */
60#define EXTIF_CORE_ID 0x811 /* external interface core */
61#define D11_CORE_ID 0x812 /* 802.11 MAC core */
62#define APHY_CORE_ID 0x813 /* 802.11a phy core */
63#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
64#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
65#define MIPS33_CORE_ID 0x816 /* mips3302 core */
66#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
67#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
68#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
69#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
70#define SDIOH_CORE_ID 0x81b /* sdio host core */
71#define ROBO_CORE_ID 0x81c /* roboswitch core */
72#define ATA100_CORE_ID 0x81d /* parallel ATA core */
73#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
74#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
75#define PCIE_CORE_ID 0x820 /* pci express core */
76#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
77#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
78#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
79#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
80#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
81#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
82#define PMU_CORE_ID 0x827 /* PMU core */
83#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
84#define SDIOD_CORE_ID 0x829 /* SDIO device core */
85#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
86#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
87#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
88#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
89#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
90#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
91#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
92#define SC_CORE_ID 0x831 /* shared common core */
93#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
94#define SPIH_CORE_ID 0x833 /* SPI host core */
95#define I2S_CORE_ID 0x834 /* I2S core */
96#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
97#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
98#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
99#define DEF_AI_COMP 0xfff /* Default component, in ai chips it
100 * maps all unused address ranges
101 */
102
103/* chipcommon being the first core: */
104#define SI_CC_IDX 0
105
106/* SOC Interconnect types (aka chip types) */
107#define SOCI_AI 1
108
109/* Common core control flags */
110#define SICF_BIST_EN 0x8000
111#define SICF_PME_EN 0x4000
112#define SICF_CORE_BITS 0x3ffc
113#define SICF_FGC 0x0002
114#define SICF_CLOCK_EN 0x0001
115
116/* Common core status flags */
117#define SISF_BIST_DONE 0x8000
118#define SISF_BIST_ERROR 0x4000
119#define SISF_GATED_CLK 0x2000
120#define SISF_DMA64 0x1000
121#define SISF_CORE_BITS 0x0fff
122
123/* A register that is common to all cores to
124 * communicate w/PMU regarding clock control.
125 */
126#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
127
128/* clk_ctl_st register */
129#define CCS_FORCEALP 0x00000001 /* force ALP request */
130#define CCS_FORCEHT 0x00000002 /* force HT request */
131#define CCS_FORCEILP 0x00000004 /* force ILP request */
132#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
133#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
134#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
135#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
136#define CCS_ERSRC_REQ_SHIFT 8
137#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
138#define CCS_HTAVAIL 0x00020000 /* HT is available */
139#define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
140#define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
141#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
142#define CCS_ERSRC_STS_SHIFT 24
143
144/* HT avail in chipc and pcmcia on 4328a0 */
145#define CCS0_HTAVAIL 0x00010000
146/* ALP avail in chipc and pcmcia on 4328a0 */
147#define CCS0_ALPAVAIL 0x00020000
148
149/* Not really related to SOC Interconnect, but a couple of software
150 * conventions for the use the flash space:
151 */
152
153/* Minumum amount of flash we support */
154#define FLASH_MIN 0x00020000 /* Minimum flash size */
155
156#define CC_SROM_OTP 0x800 /* SROM/OTP address space */
157
158/* gpiotimerval */
159#define GPIO_ONTIME_SHIFT 16
160
161/* Fields in clkdiv */
162#define CLKD_OTP 0x000f0000
163#define CLKD_OTP_SHIFT 16
164
165/* Package IDs */
166#define BCM4717_PKG_ID 9 /* 4717 package id */
167#define BCM4718_PKG_ID 10 /* 4718 package id */
168#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
169
170/* these are router chips */
171#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
172#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
173#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
174
175/* dynamic clock control defines */
176#define LPOMINFREQ 25000 /* low power oscillator min */
177#define LPOMAXFREQ 43000 /* low power oscillator max */
178#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
179#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
180#define PCIMINFREQ 25000000 /* 25 MHz */
181#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
182
183#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
184#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
185
186/* clkctl xtal what flags */
187#define XTAL 0x1 /* primary crystal oscillator (2050) */
188#define PLL 0x2 /* main chip pll */
189
190/* clkctl clk mode */
191#define CLK_FAST 0 /* force fast (pll) clock */
192#define CLK_DYNAMIC 2 /* enable dynamic clock control */
193
194/* GPIO usage priorities */
195#define GPIO_DRV_PRIORITY 0 /* Driver */
196#define GPIO_APP_PRIORITY 1 /* Application */
197#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
198 * reservation
199 */
200
201/* GPIO pull up/down */
202#define GPIO_PULLUP 0
203#define GPIO_PULLDN 1
204
205/* GPIO event regtype */
206#define GPIO_REGEVT 0 /* GPIO register event */
207#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
208#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
209
210/* device path */
211#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
212
213/* SI routine enumeration: to be used by update function with multiple hooks */
214#define SI_DOATTACH 1
215#define SI_PCIDOWN 2
216#define SI_PCIUP 3
217
218/*
219 * Data structure to export all chip specific common variables
220 * public (read-only) portion of aiutils handle returned by si_attach()
221 */
222struct si_pub {
223 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
224 uint buscorerev; /* buscore rev */
225 uint buscoreidx; /* buscore index */
226 int ccrev; /* chip common core rev */
227 u32 cccaps; /* chip common capabilities */
228 u32 cccaps_ext; /* chip common capabilities extension */
229 int pmurev; /* pmu core rev */
230 u32 pmucaps; /* pmu capabilities */
231 uint boardtype; /* board type */
232 uint boardvendor; /* board vendor */
233 uint boardflags; /* board flags */
234 uint boardflags2; /* board flags2 */
235 uint chip; /* chip number */
236 uint chiprev; /* chip revision */
237 uint chippkg; /* chip package option */
238 u32 chipst; /* chip status */
239 bool issim; /* chip is in simulation or emulation */
240 uint socirev; /* SOC interconnect rev */
241 bool pci_pr32414;
242
243};
244
245struct pci_dev;
246
247struct gpioh_item {
248 void *arg;
249 bool level;
250 void (*handler) (u32 stat, void *arg);
251 u32 event;
252 struct gpioh_item *next;
253};
254
255/* misc si info needed by some of the routines */
256struct si_info {
257 struct si_pub pub; /* back plane public state (must be first) */
258 struct pci_dev *pbus; /* handle to pci bus */
259 uint dev_coreid; /* the core provides driver functions */
260 void *intr_arg; /* interrupt callback function arg */
261 u32 (*intrsoff_fn) (void *intr_arg); /* turns chip interrupts off */
262 /* restore chip interrupts */
263 void (*intrsrestore_fn) (void *intr_arg, u32 arg);
264 /* check if interrupts are enabled */
265 bool (*intrsenabled_fn) (void *intr_arg);
266
267 struct pcicore_info *pch; /* PCI/E core handle */
268
269 struct list_head var_list; /* list of srom variables */
270
271 void __iomem *curmap; /* current regs va */
272 void __iomem *regs[SI_MAXCORES]; /* other regs va */
273
274 uint curidx; /* current core index */
275 uint numcores; /* # discovered cores */
276 uint coreid[SI_MAXCORES]; /* id of each core */
277 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
278 void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
279 u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
280 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
281 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
282
283 void *curwrap; /* current wrapper va */
284 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
285 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
286
287 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
288 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
289 u32 oob_router; /* oob router registers for axi */
290};
291
292/*
293 * Many of the routines below take an 'sih' handle as their first arg.
294 * Allocate this by calling si_attach(). Free it by calling si_detach().
295 * At any one time, the sih is logically focused on one particular si core
296 * (the "current core").
297 * Use si_setcore() or si_setcoreidx() to change the association to another core
298 */
299
300
301/* AMBA Interconnect exported externs */
302extern uint ai_flag(struct si_pub *sih);
303extern void ai_setint(struct si_pub *sih, int siflag);
304extern uint ai_coreidx(struct si_pub *sih);
305extern uint ai_corevendor(struct si_pub *sih);
306extern uint ai_corerev(struct si_pub *sih);
307extern bool ai_iscoreup(struct si_pub *sih);
308extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
309extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
310extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
311extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
312 uint val);
313extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
314extern void ai_core_disable(struct si_pub *sih, u32 bits);
315extern int ai_numaddrspaces(struct si_pub *sih);
316extern u32 ai_addrspace(struct si_pub *sih, uint asidx);
317extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
318extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
319
320/* === exported functions === */
321extern struct si_pub *ai_attach(void __iomem *regs, struct pci_dev *sdh);
322extern void ai_detach(struct si_pub *sih);
323extern uint ai_coreid(struct si_pub *sih);
324extern uint ai_corerev(struct si_pub *sih);
325extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
326 uint val);
327extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
328extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
329extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
330extern bool ai_iscoreup(struct si_pub *sih);
331extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
332extern void __iomem *ai_setcoreidx(struct si_pub *sih, uint coreidx);
333extern void __iomem *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
334extern void __iomem *ai_switch_core(struct si_pub *sih, uint coreid,
335 uint *origidx, uint *intr_val);
336extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
337extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
338extern void ai_core_disable(struct si_pub *sih, u32 bits);
339extern u32 ai_alp_clock(struct si_pub *sih);
340extern u32 ai_ilp_clock(struct si_pub *sih);
341extern void ai_pci_setup(struct si_pub *sih, uint coremask);
342extern void ai_setint(struct si_pub *sih, int siflag);
343extern bool ai_backplane64(struct si_pub *sih);
344extern void ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
345 void *intrsrestore_fn,
346 void *intrsenabled_fn, void *intr_arg);
347extern void ai_deregister_intr_callback(struct si_pub *sih);
348extern void ai_clkctl_init(struct si_pub *sih);
349extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
350extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
351extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
352extern bool ai_deviceremoved(struct si_pub *sih);
353extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
354 u8 priority);
355
356/* OTP status */
357extern bool ai_is_otp_disabled(struct si_pub *sih);
358
359/* SPROM availability */
360extern bool ai_is_sprom_available(struct si_pub *sih);
361
362/*
363 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
364 * The returned path is NULL terminated and has trailing '/'.
365 * Return 0 on success, nonzero otherwise.
366 */
367extern int ai_devpath(struct si_pub *sih, char *path, int size);
368
369extern void ai_pci_sleep(struct si_pub *sih);
370extern void ai_pci_down(struct si_pub *sih);
371extern void ai_pci_up(struct si_pub *sih);
372extern int ai_pci_fixcfg(struct si_pub *sih);
373
374extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
375/* Enable Ex-PA for 4313 */
376extern void ai_epa_4313war(struct si_pub *sih);
377
378#endif /* _BRCM_AIUTILS_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/ampdu.c b/drivers/staging/brcm80211/brcmsmac/ampdu.c
deleted file mode 100644
index 7f27dbdb6b6..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/ampdu.c
+++ /dev/null
@@ -1,1241 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#include <net/mac80211.h>
17
18#include "rate.h"
19#include "scb.h"
20#include "phy/phy_hal.h"
21#include "antsel.h"
22#include "main.h"
23#include "ampdu.h"
24
25/* max number of mpdus in an ampdu */
26#define AMPDU_MAX_MPDU 32
27/* max number of mpdus in an ampdu to a legacy */
28#define AMPDU_NUM_MPDU_LEGACY 16
29/* max Tx ba window size (in pdu) */
30#define AMPDU_TX_BA_MAX_WSIZE 64
31/* default Tx ba window size (in pdu) */
32#define AMPDU_TX_BA_DEF_WSIZE 64
33/* default Rx ba window size (in pdu) */
34#define AMPDU_RX_BA_DEF_WSIZE 64
35/* max Rx ba window size (in pdu) */
36#define AMPDU_RX_BA_MAX_WSIZE 64
37/* max dur of tx ampdu (in msec) */
38#define AMPDU_MAX_DUR 5
39/* default tx retry limit */
40#define AMPDU_DEF_RETRY_LIMIT 5
41/* default tx retry limit at reg rate */
42#define AMPDU_DEF_RR_RETRY_LIMIT 2
43/* default weight of ampdu in txfifo */
44#define AMPDU_DEF_TXPKT_WEIGHT 2
45/* default ffpld reserved bytes */
46#define AMPDU_DEF_FFPLD_RSVD 2048
47/* # of inis to be freed on detach */
48#define AMPDU_INI_FREE 10
49/* max # of mpdus released at a time */
50#define AMPDU_SCB_MAX_RELEASE 20
51
52#define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
53#define FFPLD_TX_MAX_UNFL 200 /* default value of the average number of ampdu
54 * without underflows
55 */
56#define FFPLD_MPDU_SIZE 1800 /* estimate of maximum mpdu size */
57#define FFPLD_MAX_MCS 23 /* we don't deal with mcs 32 */
58#define FFPLD_PLD_INCR 1000 /* increments in bytes */
59#define FFPLD_MAX_AMPDU_CNT 5000 /* maximum number of ampdu we
60 * accumulate between resets.
61 */
62
63#define AMPDU_DELIMITER_LEN 4
64
65/* max allowed number of mpdus in an ampdu (2 streams) */
66#define AMPDU_NUM_MPDU 16
67
68#define TX_SEQ_TO_INDEX(seq) ((seq) % AMPDU_TX_BA_MAX_WSIZE)
69
70/* max possible overhead per mpdu in the ampdu; 3 is for roundup if needed */
71#define AMPDU_MAX_MPDU_OVERHEAD (FCS_LEN + DOT11_ICV_AES_LEN +\
72 AMPDU_DELIMITER_LEN + 3\
73 + DOT11_A4_HDR_LEN + DOT11_QOS_LEN + DOT11_IV_MAX_LEN)
74
75/* modulo add/sub, bound = 2^k */
76#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
77#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
78
79/* structure to hold tx fifo information and pre-loading state
80 * counters specific to tx underflows of ampdus
81 * some counters might be redundant with the ones in wlc or ampdu structures.
82 * This allows to maintain a specific state independently of
83 * how often and/or when the wlc counters are updated.
84 *
85 * ampdu_pld_size: number of bytes to be pre-loaded
86 * mcs2ampdu_table: per-mcs max # of mpdus in an ampdu
87 * prev_txfunfl: num of underflows last read from the HW macstats counter
88 * accum_txfunfl: num of underflows since we modified pld params
89 * accum_txampdu: num of tx ampdu since we modified pld params
90 * prev_txampdu: previous reading of tx ampdu
91 * dmaxferrate: estimated dma avg xfer rate in kbits/sec
92 */
93struct brcms_fifo_info {
94 u16 ampdu_pld_size;
95 u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1];
96 u16 prev_txfunfl;
97 u32 accum_txfunfl;
98 u32 accum_txampdu;
99 u32 prev_txampdu;
100 u32 dmaxferrate;
101};
102
103/* AMPDU module specific state
104 *
105 * wlc: pointer to main wlc structure
106 * scb_handle: scb cubby handle to retrieve data from scb
107 * ini_enable: per-tid initiator enable/disable of ampdu
108 * ba_tx_wsize: Tx ba window size (in pdu)
109 * ba_rx_wsize: Rx ba window size (in pdu)
110 * retry_limit: mpdu transmit retry limit
111 * rr_retry_limit: mpdu transmit retry limit at regular rate
112 * retry_limit_tid: per-tid mpdu transmit retry limit
113 * rr_retry_limit_tid: per-tid mpdu transmit retry limit at regular rate
114 * mpdu_density: min mpdu spacing (0-7) ==> 2^(x-1)/8 usec
115 * max_pdu: max pdus allowed in ampdu
116 * dur: max duration of an ampdu (in msec)
117 * txpkt_weight: weight of ampdu in txfifo; reduces rate lag
118 * rx_factor: maximum rx ampdu factor (0-3) ==> 2^(13+x) bytes
119 * ffpld_rsvd: number of bytes to reserve for preload
120 * max_txlen: max size of ampdu per mcs, bw and sgi
121 * mfbr: enable multiple fallback rate
122 * tx_max_funl: underflows should be kept such that
123 * (tx_max_funfl*underflows) < tx frames
124 * fifo_tb: table of fifo infos
125 */
126struct ampdu_info {
127 struct brcms_c_info *wlc;
128 int scb_handle;
129 u8 ini_enable[AMPDU_MAX_SCB_TID];
130 u8 ba_tx_wsize;
131 u8 ba_rx_wsize;
132 u8 retry_limit;
133 u8 rr_retry_limit;
134 u8 retry_limit_tid[AMPDU_MAX_SCB_TID];
135 u8 rr_retry_limit_tid[AMPDU_MAX_SCB_TID];
136 u8 mpdu_density;
137 s8 max_pdu;
138 u8 dur;
139 u8 txpkt_weight;
140 u8 rx_factor;
141 u32 ffpld_rsvd;
142 u32 max_txlen[MCS_TABLE_SIZE][2][2];
143 bool mfbr;
144 u32 tx_max_funl;
145 struct brcms_fifo_info fifo_tb[NUM_FFPLD_FIFO];
146};
147
148/* used for flushing ampdu packets */
149struct cb_del_ampdu_pars {
150 struct ieee80211_sta *sta;
151 u16 tid;
152};
153
154static void brcms_c_scb_ampdu_update_max_txlen(struct ampdu_info *ampdu, u8 dur)
155{
156 u32 rate, mcs;
157
158 for (mcs = 0; mcs < MCS_TABLE_SIZE; mcs++) {
159 /* rate is in Kbps; dur is in msec ==> len = (rate * dur) / 8 */
160 /* 20MHz, No SGI */
161 rate = mcs_2_rate(mcs, false, false);
162 ampdu->max_txlen[mcs][0][0] = (rate * dur) >> 3;
163 /* 40 MHz, No SGI */
164 rate = mcs_2_rate(mcs, true, false);
165 ampdu->max_txlen[mcs][1][0] = (rate * dur) >> 3;
166 /* 20MHz, SGI */
167 rate = mcs_2_rate(mcs, false, true);
168 ampdu->max_txlen[mcs][0][1] = (rate * dur) >> 3;
169 /* 40 MHz, SGI */
170 rate = mcs_2_rate(mcs, true, true);
171 ampdu->max_txlen[mcs][1][1] = (rate * dur) >> 3;
172 }
173}
174
175static bool brcms_c_ampdu_cap(struct ampdu_info *ampdu)
176{
177 if (BRCMS_PHY_11N_CAP(ampdu->wlc->band))
178 return true;
179 else
180 return false;
181}
182
183static int brcms_c_ampdu_set(struct ampdu_info *ampdu, bool on)
184{
185 struct brcms_c_info *wlc = ampdu->wlc;
186
187 wlc->pub->_ampdu = false;
188
189 if (on) {
190 if (!(wlc->pub->_n_enab & SUPPORT_11N)) {
191 wiphy_err(ampdu->wlc->wiphy, "wl%d: driver not "
192 "nmode enabled\n", wlc->pub->unit);
193 return -ENOTSUPP;
194 }
195 if (!brcms_c_ampdu_cap(ampdu)) {
196 wiphy_err(ampdu->wlc->wiphy, "wl%d: device not "
197 "ampdu capable\n", wlc->pub->unit);
198 return -ENOTSUPP;
199 }
200 wlc->pub->_ampdu = on;
201 }
202
203 return 0;
204}
205
206static void brcms_c_ffpld_init(struct ampdu_info *ampdu)
207{
208 int i, j;
209 struct brcms_fifo_info *fifo;
210
211 for (j = 0; j < NUM_FFPLD_FIFO; j++) {
212 fifo = (ampdu->fifo_tb + j);
213 fifo->ampdu_pld_size = 0;
214 for (i = 0; i <= FFPLD_MAX_MCS; i++)
215 fifo->mcs2ampdu_table[i] = 255;
216 fifo->dmaxferrate = 0;
217 fifo->accum_txampdu = 0;
218 fifo->prev_txfunfl = 0;
219 fifo->accum_txfunfl = 0;
220
221 }
222}
223
224struct ampdu_info *brcms_c_ampdu_attach(struct brcms_c_info *wlc)
225{
226 struct ampdu_info *ampdu;
227 int i;
228
229 ampdu = kzalloc(sizeof(struct ampdu_info), GFP_ATOMIC);
230 if (!ampdu)
231 return NULL;
232
233 ampdu->wlc = wlc;
234
235 for (i = 0; i < AMPDU_MAX_SCB_TID; i++)
236 ampdu->ini_enable[i] = true;
237 /* Disable ampdu for VO by default */
238 ampdu->ini_enable[PRIO_8021D_VO] = false;
239 ampdu->ini_enable[PRIO_8021D_NC] = false;
240
241 /* Disable ampdu for BK by default since not enough fifo space */
242 ampdu->ini_enable[PRIO_8021D_NONE] = false;
243 ampdu->ini_enable[PRIO_8021D_BK] = false;
244
245 ampdu->ba_tx_wsize = AMPDU_TX_BA_DEF_WSIZE;
246 ampdu->ba_rx_wsize = AMPDU_RX_BA_DEF_WSIZE;
247 ampdu->mpdu_density = AMPDU_DEF_MPDU_DENSITY;
248 ampdu->max_pdu = AUTO;
249 ampdu->dur = AMPDU_MAX_DUR;
250 ampdu->txpkt_weight = AMPDU_DEF_TXPKT_WEIGHT;
251
252 ampdu->ffpld_rsvd = AMPDU_DEF_FFPLD_RSVD;
253 /*
254 * bump max ampdu rcv size to 64k for all 11n
255 * devices except 4321A0 and 4321A1
256 */
257 if (BRCMS_ISNPHY(wlc->band) && NREV_LT(wlc->band->phyrev, 2))
258 ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_32K;
259 else
260 ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_64K;
261 ampdu->retry_limit = AMPDU_DEF_RETRY_LIMIT;
262 ampdu->rr_retry_limit = AMPDU_DEF_RR_RETRY_LIMIT;
263
264 for (i = 0; i < AMPDU_MAX_SCB_TID; i++) {
265 ampdu->retry_limit_tid[i] = ampdu->retry_limit;
266 ampdu->rr_retry_limit_tid[i] = ampdu->rr_retry_limit;
267 }
268
269 brcms_c_scb_ampdu_update_max_txlen(ampdu, ampdu->dur);
270 ampdu->mfbr = false;
271 /* try to set ampdu to the default value */
272 brcms_c_ampdu_set(ampdu, wlc->pub->_ampdu);
273
274 ampdu->tx_max_funl = FFPLD_TX_MAX_UNFL;
275 brcms_c_ffpld_init(ampdu);
276
277 return ampdu;
278}
279
280void brcms_c_ampdu_detach(struct ampdu_info *ampdu)
281{
282 kfree(ampdu);
283}
284
285static void brcms_c_scb_ampdu_update_config(struct ampdu_info *ampdu,
286 struct scb *scb)
287{
288 struct scb_ampdu *scb_ampdu = &scb->scb_ampdu;
289 int i;
290
291 scb_ampdu->max_pdu = AMPDU_NUM_MPDU;
292
293 /* go back to legacy size if some preloading is occurring */
294 for (i = 0; i < NUM_FFPLD_FIFO; i++) {
295 if (ampdu->fifo_tb[i].ampdu_pld_size > FFPLD_PLD_INCR)
296 scb_ampdu->max_pdu = AMPDU_NUM_MPDU_LEGACY;
297 }
298
299 /* apply user override */
300 if (ampdu->max_pdu != AUTO)
301 scb_ampdu->max_pdu = (u8) ampdu->max_pdu;
302
303 scb_ampdu->release = min_t(u8, scb_ampdu->max_pdu,
304 AMPDU_SCB_MAX_RELEASE);
305
306 if (scb_ampdu->max_rx_ampdu_bytes)
307 scb_ampdu->release = min_t(u8, scb_ampdu->release,
308 scb_ampdu->max_rx_ampdu_bytes / 1600);
309
310 scb_ampdu->release = min(scb_ampdu->release,
311 ampdu->fifo_tb[TX_AC_BE_FIFO].
312 mcs2ampdu_table[FFPLD_MAX_MCS]);
313}
314
315static void brcms_c_scb_ampdu_update_config_all(struct ampdu_info *ampdu)
316{
317 brcms_c_scb_ampdu_update_config(ampdu, &ampdu->wlc->pri_scb);
318}
319
320static void brcms_c_ffpld_calc_mcs2ampdu_table(struct ampdu_info *ampdu, int f)
321{
322 int i;
323 u32 phy_rate, dma_rate, tmp;
324 u8 max_mpdu;
325 struct brcms_fifo_info *fifo = (ampdu->fifo_tb + f);
326
327 /* recompute the dma rate */
328 /* note : we divide/multiply by 100 to avoid integer overflows */
329 max_mpdu = min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS],
330 AMPDU_NUM_MPDU_LEGACY);
331 phy_rate = mcs_2_rate(FFPLD_MAX_MCS, true, false);
332 dma_rate =
333 (((phy_rate / 100) *
334 (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
335 / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
336 fifo->dmaxferrate = dma_rate;
337
338 /* fill up the mcs2ampdu table; do not recalc the last mcs */
339 dma_rate = dma_rate >> 7;
340 for (i = 0; i < FFPLD_MAX_MCS; i++) {
341 /* shifting to keep it within integer range */
342 phy_rate = mcs_2_rate(i, true, false) >> 7;
343 if (phy_rate > dma_rate) {
344 tmp = ((fifo->ampdu_pld_size * phy_rate) /
345 ((phy_rate - dma_rate) * FFPLD_MPDU_SIZE)) + 1;
346 tmp = min_t(u32, tmp, 255);
347 fifo->mcs2ampdu_table[i] = (u8) tmp;
348 }
349 }
350}
351
352/* evaluate the dma transfer rate using the tx underflows as feedback.
353 * If necessary, increase tx fifo preloading. If not enough,
354 * decrease maximum ampdu size for each mcs till underflows stop
355 * Return 1 if pre-loading not active, -1 if not an underflow event,
356 * 0 if pre-loading module took care of the event.
357 */
358static int brcms_c_ffpld_check_txfunfl(struct brcms_c_info *wlc, int fid)
359{
360 struct ampdu_info *ampdu = wlc->ampdu;
361 u32 phy_rate = mcs_2_rate(FFPLD_MAX_MCS, true, false);
362 u32 txunfl_ratio;
363 u8 max_mpdu;
364 u32 current_ampdu_cnt = 0;
365 u16 max_pld_size;
366 u32 new_txunfl;
367 struct brcms_fifo_info *fifo = (ampdu->fifo_tb + fid);
368 uint xmtfifo_sz;
369 u16 cur_txunfl;
370
371 /* return if we got here for a different reason than underflows */
372 cur_txunfl = brcms_b_read_shm(wlc->hw,
373 M_UCODE_MACSTAT +
374 offsetof(struct macstat, txfunfl[fid]));
375 new_txunfl = (u16) (cur_txunfl - fifo->prev_txfunfl);
376 if (new_txunfl == 0) {
377 BCMMSG(wlc->wiphy, "TX status FRAG set but no tx underflows\n");
378 return -1;
379 }
380 fifo->prev_txfunfl = cur_txunfl;
381
382 if (!ampdu->tx_max_funl)
383 return 1;
384
385 /* check if fifo is big enough */
386 if (brcms_b_xmtfifo_sz_get(wlc->hw, fid, &xmtfifo_sz))
387 return -1;
388
389 if ((TXFIFO_SIZE_UNIT * (u32) xmtfifo_sz) <= ampdu->ffpld_rsvd)
390 return 1;
391
392 max_pld_size = TXFIFO_SIZE_UNIT * xmtfifo_sz - ampdu->ffpld_rsvd;
393 fifo->accum_txfunfl += new_txunfl;
394
395 /* we need to wait for at least 10 underflows */
396 if (fifo->accum_txfunfl < 10)
397 return 0;
398
399 BCMMSG(wlc->wiphy, "ampdu_count %d tx_underflows %d\n",
400 current_ampdu_cnt, fifo->accum_txfunfl);
401
402 /*
403 compute the current ratio of tx unfl per ampdu.
404 When the current ampdu count becomes too
405 big while the ratio remains small, we reset
406 the current count in order to not
407 introduce too big of a latency in detecting a
408 large amount of tx underflows later.
409 */
410
411 txunfl_ratio = current_ampdu_cnt / fifo->accum_txfunfl;
412
413 if (txunfl_ratio > ampdu->tx_max_funl) {
414 if (current_ampdu_cnt >= FFPLD_MAX_AMPDU_CNT)
415 fifo->accum_txfunfl = 0;
416
417 return 0;
418 }
419 max_mpdu = min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS],
420 AMPDU_NUM_MPDU_LEGACY);
421
422 /* In case max value max_pdu is already lower than
423 the fifo depth, there is nothing more we can do.
424 */
425
426 if (fifo->ampdu_pld_size >= max_mpdu * FFPLD_MPDU_SIZE) {
427 fifo->accum_txfunfl = 0;
428 return 0;
429 }
430
431 if (fifo->ampdu_pld_size < max_pld_size) {
432
433 /* increment by TX_FIFO_PLD_INC bytes */
434 fifo->ampdu_pld_size += FFPLD_PLD_INCR;
435 if (fifo->ampdu_pld_size > max_pld_size)
436 fifo->ampdu_pld_size = max_pld_size;
437
438 /* update scb release size */
439 brcms_c_scb_ampdu_update_config_all(ampdu);
440
441 /*
442 * compute a new dma xfer rate for max_mpdu @ max mcs.
443 * This is the minimum dma rate that can achieve no
444 * underflow condition for the current mpdu size.
445 *
446 * note : we divide/multiply by 100 to avoid integer overflows
447 */
448 fifo->dmaxferrate =
449 (((phy_rate / 100) *
450 (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
451 / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
452
453 BCMMSG(wlc->wiphy, "DMA estimated transfer rate %d; "
454 "pre-load size %d\n",
455 fifo->dmaxferrate, fifo->ampdu_pld_size);
456 } else {
457
458 /* decrease ampdu size */
459 if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] > 1) {
460 if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] == 255)
461 fifo->mcs2ampdu_table[FFPLD_MAX_MCS] =
462 AMPDU_NUM_MPDU_LEGACY - 1;
463 else
464 fifo->mcs2ampdu_table[FFPLD_MAX_MCS] -= 1;
465
466 /* recompute the table */
467 brcms_c_ffpld_calc_mcs2ampdu_table(ampdu, fid);
468
469 /* update scb release size */
470 brcms_c_scb_ampdu_update_config_all(ampdu);
471 }
472 }
473 fifo->accum_txfunfl = 0;
474 return 0;
475}
476
477void
478brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid,
479 u8 ba_wsize, /* negotiated ba window size (in pdu) */
480 uint max_rx_ampdu_bytes) /* from ht_cap in beacon */
481{
482 struct scb_ampdu *scb_ampdu;
483 struct scb_ampdu_tid_ini *ini;
484 struct ampdu_info *ampdu = wlc->ampdu;
485 struct scb *scb = &wlc->pri_scb;
486 scb_ampdu = &scb->scb_ampdu;
487
488 if (!ampdu->ini_enable[tid]) {
489 wiphy_err(ampdu->wlc->wiphy, "%s: Rejecting tid %d\n",
490 __func__, tid);
491 return;
492 }
493
494 ini = &scb_ampdu->ini[tid];
495 ini->tid = tid;
496 ini->scb = scb_ampdu->scb;
497 ini->ba_wsize = ba_wsize;
498 scb_ampdu->max_rx_ampdu_bytes = max_rx_ampdu_bytes;
499}
500
501int
502brcms_c_sendampdu(struct ampdu_info *ampdu, struct brcms_txq_info *qi,
503 struct sk_buff **pdu, int prec)
504{
505 struct brcms_c_info *wlc;
506 struct sk_buff *p, *pkt[AMPDU_MAX_MPDU];
507 u8 tid, ndelim;
508 int err = 0;
509 u8 preamble_type = BRCMS_GF_PREAMBLE;
510 u8 fbr_preamble_type = BRCMS_GF_PREAMBLE;
511 u8 rts_preamble_type = BRCMS_LONG_PREAMBLE;
512 u8 rts_fbr_preamble_type = BRCMS_LONG_PREAMBLE;
513
514 bool rr = true, fbr = false;
515 uint i, count = 0, fifo, seg_cnt = 0;
516 u16 plen, len, seq = 0, mcl, mch, index, frameid, dma_len = 0;
517 u32 ampdu_len, max_ampdu_bytes = 0;
518 struct d11txh *txh = NULL;
519 u8 *plcp;
520 struct ieee80211_hdr *h;
521 struct scb *scb;
522 struct scb_ampdu *scb_ampdu;
523 struct scb_ampdu_tid_ini *ini;
524 u8 mcs = 0;
525 bool use_rts = false, use_cts = false;
526 u32 rspec = 0, rspec_fallback = 0;
527 u32 rts_rspec = 0, rts_rspec_fallback = 0;
528 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
529 struct ieee80211_rts *rts;
530 u8 rr_retry_limit;
531 struct brcms_fifo_info *f;
532 bool fbr_iscck;
533 struct ieee80211_tx_info *tx_info;
534 u16 qlen;
535 struct wiphy *wiphy;
536
537 wlc = ampdu->wlc;
538 wiphy = wlc->wiphy;
539 p = *pdu;
540
541 tid = (u8) (p->priority);
542
543 f = ampdu->fifo_tb + prio2fifo[tid];
544
545 scb = &wlc->pri_scb;
546 scb_ampdu = &scb->scb_ampdu;
547 ini = &scb_ampdu->ini[tid];
548
549 /* Let pressure continue to build ... */
550 qlen = pktq_plen(&qi->q, prec);
551 if (ini->tx_in_transit > 0 &&
552 qlen < min(scb_ampdu->max_pdu, ini->ba_wsize))
553 /* Collect multiple MPDU's to be sent in the next AMPDU */
554 return -EBUSY;
555
556 /* at this point we intend to transmit an AMPDU */
557 rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
558 ampdu_len = 0;
559 dma_len = 0;
560 while (p) {
561 struct ieee80211_tx_rate *txrate;
562
563 tx_info = IEEE80211_SKB_CB(p);
564 txrate = tx_info->status.rates;
565
566 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
567 err = brcms_c_prep_pdu(wlc, p, &fifo);
568 } else {
569 wiphy_err(wiphy, "%s: AMPDU flag is off!\n", __func__);
570 *pdu = NULL;
571 err = 0;
572 break;
573 }
574
575 if (err) {
576 if (err == -EBUSY) {
577 wiphy_err(wiphy, "wl%d: sendampdu: "
578 "prep_xdu retry; seq 0x%x\n",
579 wlc->pub->unit, seq);
580 *pdu = p;
581 break;
582 }
583
584 /* error in the packet; reject it */
585 wiphy_err(wiphy, "wl%d: sendampdu: prep_xdu "
586 "rejected; seq 0x%x\n", wlc->pub->unit, seq);
587 *pdu = NULL;
588 break;
589 }
590
591 /* pkt is good to be aggregated */
592 txh = (struct d11txh *) p->data;
593 plcp = (u8 *) (txh + 1);
594 h = (struct ieee80211_hdr *)(plcp + D11_PHY_HDR_LEN);
595 seq = le16_to_cpu(h->seq_ctrl) >> SEQNUM_SHIFT;
596 index = TX_SEQ_TO_INDEX(seq);
597
598 /* check mcl fields and test whether it can be agg'd */
599 mcl = le16_to_cpu(txh->MacTxControlLow);
600 mcl &= ~TXC_AMPDU_MASK;
601 fbr_iscck = !(le16_to_cpu(txh->XtraFrameTypes) & 0x3);
602 txh->PreloadSize = 0; /* always default to 0 */
603
604 /* Handle retry limits */
605 if (txrate[0].count <= rr_retry_limit) {
606 txrate[0].count++;
607 rr = true;
608 fbr = false;
609 } else {
610 fbr = true;
611 rr = false;
612 txrate[1].count++;
613 }
614
615 /* extract the length info */
616 len = fbr_iscck ? BRCMS_GET_CCK_PLCP_LEN(txh->FragPLCPFallback)
617 : BRCMS_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
618
619 /* retrieve null delimiter count */
620 ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
621 seg_cnt += 1;
622
623 BCMMSG(wlc->wiphy, "wl%d: mpdu %d plcp_len %d\n",
624 wlc->pub->unit, count, len);
625
626 /*
627 * aggregateable mpdu. For ucode/hw agg,
628 * test whether need to break or change the epoch
629 */
630 if (count == 0) {
631 mcl |= (TXC_AMPDU_FIRST << TXC_AMPDU_SHIFT);
632 /* refill the bits since might be a retx mpdu */
633 mcl |= TXC_STARTMSDU;
634 rts = (struct ieee80211_rts *)&txh->rts_frame;
635
636 if (ieee80211_is_rts(rts->frame_control)) {
637 mcl |= TXC_SENDRTS;
638 use_rts = true;
639 }
640 if (ieee80211_is_cts(rts->frame_control)) {
641 mcl |= TXC_SENDCTS;
642 use_cts = true;
643 }
644 } else {
645 mcl |= (TXC_AMPDU_MIDDLE << TXC_AMPDU_SHIFT);
646 mcl &= ~(TXC_STARTMSDU | TXC_SENDRTS | TXC_SENDCTS);
647 }
648
649 len = roundup(len, 4);
650 ampdu_len += (len + (ndelim + 1) * AMPDU_DELIMITER_LEN);
651
652 dma_len += (u16) brcmu_pkttotlen(p);
653
654 BCMMSG(wlc->wiphy, "wl%d: ampdu_len %d"
655 " seg_cnt %d null delim %d\n",
656 wlc->pub->unit, ampdu_len, seg_cnt, ndelim);
657
658 txh->MacTxControlLow = cpu_to_le16(mcl);
659
660 /* this packet is added */
661 pkt[count++] = p;
662
663 /* patch the first MPDU */
664 if (count == 1) {
665 u8 plcp0, plcp3, is40, sgi;
666 struct ieee80211_sta *sta;
667
668 sta = tx_info->control.sta;
669
670 if (rr) {
671 plcp0 = plcp[0];
672 plcp3 = plcp[3];
673 } else {
674 plcp0 = txh->FragPLCPFallback[0];
675 plcp3 = txh->FragPLCPFallback[3];
676
677 }
678 is40 = (plcp0 & MIMO_PLCP_40MHZ) ? 1 : 0;
679 sgi = plcp3_issgi(plcp3) ? 1 : 0;
680 mcs = plcp0 & ~MIMO_PLCP_40MHZ;
681 max_ampdu_bytes =
682 min(scb_ampdu->max_rx_ampdu_bytes,
683 ampdu->max_txlen[mcs][is40][sgi]);
684
685 if (is40)
686 mimo_ctlchbw =
687 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
688 wlc->band->pi))
689 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
690
691 /* rebuild the rspec and rspec_fallback */
692 rspec = RSPEC_MIMORATE;
693 rspec |= plcp[0] & ~MIMO_PLCP_40MHZ;
694 if (plcp[0] & MIMO_PLCP_40MHZ)
695 rspec |= (PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT);
696
697 if (fbr_iscck) /* CCK */
698 rspec_fallback = cck_rspec(cck_phy2mac_rate
699 (txh->FragPLCPFallback[0]));
700 else { /* MIMO */
701 rspec_fallback = RSPEC_MIMORATE;
702 rspec_fallback |=
703 txh->FragPLCPFallback[0] & ~MIMO_PLCP_40MHZ;
704 if (txh->FragPLCPFallback[0] & MIMO_PLCP_40MHZ)
705 rspec_fallback |=
706 (PHY_TXC1_BW_40MHZ <<
707 RSPEC_BW_SHIFT);
708 }
709
710 if (use_rts || use_cts) {
711 rts_rspec =
712 brcms_c_rspec_to_rts_rspec(wlc,
713 rspec, false, mimo_ctlchbw);
714 rts_rspec_fallback =
715 brcms_c_rspec_to_rts_rspec(wlc,
716 rspec_fallback, false, mimo_ctlchbw);
717 }
718 }
719
720 /* if (first mpdu for host agg) */
721 /* test whether to add more */
722 if ((mcs_2_rate(mcs, true, false) >= f->dmaxferrate) &&
723 (count == f->mcs2ampdu_table[mcs])) {
724 BCMMSG(wlc->wiphy, "wl%d: PR 37644: stopping"
725 " ampdu at %d for mcs %d\n",
726 wlc->pub->unit, count, mcs);
727 break;
728 }
729
730 if (count == scb_ampdu->max_pdu)
731 break;
732
733 /*
734 * check to see if the next pkt is
735 * a candidate for aggregation
736 */
737 p = pktq_ppeek(&qi->q, prec);
738 /* tx_info must be checked with current p */
739 tx_info = IEEE80211_SKB_CB(p);
740
741 if (p) {
742 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
743 ((u8) (p->priority) == tid)) {
744
745 plen = brcmu_pkttotlen(p) +
746 AMPDU_MAX_MPDU_OVERHEAD;
747 plen = max(scb_ampdu->min_len, plen);
748
749 if ((plen + ampdu_len) > max_ampdu_bytes) {
750 p = NULL;
751 continue;
752 }
753
754 /*
755 * check if there are enough
756 * descriptors available
757 */
758 if (*wlc->core->txavail[fifo] <= seg_cnt + 1) {
759 wiphy_err(wiphy, "%s: No fifo space "
760 "!!\n", __func__);
761 p = NULL;
762 continue;
763 }
764 p = brcmu_pktq_pdeq(&qi->q, prec);
765 } else {
766 p = NULL;
767 }
768 }
769 } /* end while(p) */
770
771 ini->tx_in_transit += count;
772
773 if (count) {
774 /* patch up the last txh */
775 txh = (struct d11txh *) pkt[count - 1]->data;
776 mcl = le16_to_cpu(txh->MacTxControlLow);
777 mcl &= ~TXC_AMPDU_MASK;
778 mcl |= (TXC_AMPDU_LAST << TXC_AMPDU_SHIFT);
779 txh->MacTxControlLow = cpu_to_le16(mcl);
780
781 /* remove the null delimiter after last mpdu */
782 ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
783 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] = 0;
784 ampdu_len -= ndelim * AMPDU_DELIMITER_LEN;
785
786 /* remove the pad len from last mpdu */
787 fbr_iscck = ((le16_to_cpu(txh->XtraFrameTypes) & 0x3) == 0);
788 len = fbr_iscck ? BRCMS_GET_CCK_PLCP_LEN(txh->FragPLCPFallback)
789 : BRCMS_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
790 ampdu_len -= roundup(len, 4) - len;
791
792 /* patch up the first txh & plcp */
793 txh = (struct d11txh *) pkt[0]->data;
794 plcp = (u8 *) (txh + 1);
795
796 BRCMS_SET_MIMO_PLCP_LEN(plcp, ampdu_len);
797 /* mark plcp to indicate ampdu */
798 BRCMS_SET_MIMO_PLCP_AMPDU(plcp);
799
800 /* reset the mixed mode header durations */
801 if (txh->MModeLen) {
802 u16 mmodelen =
803 brcms_c_calc_lsig_len(wlc, rspec, ampdu_len);
804 txh->MModeLen = cpu_to_le16(mmodelen);
805 preamble_type = BRCMS_MM_PREAMBLE;
806 }
807 if (txh->MModeFbrLen) {
808 u16 mmfbrlen =
809 brcms_c_calc_lsig_len(wlc, rspec_fallback,
810 ampdu_len);
811 txh->MModeFbrLen = cpu_to_le16(mmfbrlen);
812 fbr_preamble_type = BRCMS_MM_PREAMBLE;
813 }
814
815 /* set the preload length */
816 if (mcs_2_rate(mcs, true, false) >= f->dmaxferrate) {
817 dma_len = min(dma_len, f->ampdu_pld_size);
818 txh->PreloadSize = cpu_to_le16(dma_len);
819 } else
820 txh->PreloadSize = 0;
821
822 mch = le16_to_cpu(txh->MacTxControlHigh);
823
824 /* update RTS dur fields */
825 if (use_rts || use_cts) {
826 u16 durid;
827 rts = (struct ieee80211_rts *)&txh->rts_frame;
828 if ((mch & TXC_PREAMBLE_RTS_MAIN_SHORT) ==
829 TXC_PREAMBLE_RTS_MAIN_SHORT)
830 rts_preamble_type = BRCMS_SHORT_PREAMBLE;
831
832 if ((mch & TXC_PREAMBLE_RTS_FB_SHORT) ==
833 TXC_PREAMBLE_RTS_FB_SHORT)
834 rts_fbr_preamble_type = BRCMS_SHORT_PREAMBLE;
835
836 durid =
837 brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec,
838 rspec, rts_preamble_type,
839 preamble_type, ampdu_len,
840 true);
841 rts->duration = cpu_to_le16(durid);
842 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
843 rts_rspec_fallback,
844 rspec_fallback,
845 rts_fbr_preamble_type,
846 fbr_preamble_type,
847 ampdu_len, true);
848 txh->RTSDurFallback = cpu_to_le16(durid);
849 /* set TxFesTimeNormal */
850 txh->TxFesTimeNormal = rts->duration;
851 /* set fallback rate version of TxFesTimeNormal */
852 txh->TxFesTimeFallback = txh->RTSDurFallback;
853 }
854
855 /* set flag and plcp for fallback rate */
856 if (fbr) {
857 mch |= TXC_AMPDU_FBR;
858 txh->MacTxControlHigh = cpu_to_le16(mch);
859 BRCMS_SET_MIMO_PLCP_AMPDU(plcp);
860 BRCMS_SET_MIMO_PLCP_AMPDU(txh->FragPLCPFallback);
861 }
862
863 BCMMSG(wlc->wiphy, "wl%d: count %d ampdu_len %d\n",
864 wlc->pub->unit, count, ampdu_len);
865
866 /* inform rate_sel if it this is a rate probe pkt */
867 frameid = le16_to_cpu(txh->TxFrameID);
868 if (frameid & TXFID_RATE_PROBE_MASK)
869 wiphy_err(wiphy, "%s: XXX what to do with "
870 "TXFID_RATE_PROBE_MASK!?\n", __func__);
871
872 for (i = 0; i < count; i++)
873 brcms_c_txfifo(wlc, fifo, pkt[i], i == (count - 1),
874 ampdu->txpkt_weight);
875
876 }
877 /* endif (count) */
878 return err;
879}
880
881static void
882brcms_c_ampdu_rate_status(struct brcms_c_info *wlc,
883 struct ieee80211_tx_info *tx_info,
884 struct tx_status *txs, u8 mcs)
885{
886 struct ieee80211_tx_rate *txrate = tx_info->status.rates;
887 int i;
888
889 /* clear the rest of the rates */
890 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
891 txrate[i].idx = -1;
892 txrate[i].count = 0;
893 }
894}
895
896static void
897brcms_c_ampdu_dotxstatus_complete(struct ampdu_info *ampdu, struct scb *scb,
898 struct sk_buff *p, struct tx_status *txs,
899 u32 s1, u32 s2)
900{
901 struct scb_ampdu *scb_ampdu;
902 struct brcms_c_info *wlc = ampdu->wlc;
903 struct scb_ampdu_tid_ini *ini;
904 u8 bitmap[8], queue, tid;
905 struct d11txh *txh;
906 u8 *plcp;
907 struct ieee80211_hdr *h;
908 u16 seq, start_seq = 0, bindex, index, mcl;
909 u8 mcs = 0;
910 bool ba_recd = false, ack_recd = false;
911 u8 suc_mpdu = 0, tot_mpdu = 0;
912 uint supr_status;
913 bool update_rate = true, retry = true, tx_error = false;
914 u16 mimoantsel = 0;
915 u8 antselid = 0;
916 u8 retry_limit, rr_retry_limit;
917 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p);
918 struct wiphy *wiphy = wlc->wiphy;
919
920#ifdef BCMDBG
921 u8 hole[AMPDU_MAX_MPDU];
922 memset(hole, 0, sizeof(hole));
923#endif
924
925 scb_ampdu = &scb->scb_ampdu;
926 tid = (u8) (p->priority);
927
928 ini = &scb_ampdu->ini[tid];
929 retry_limit = ampdu->retry_limit_tid[tid];
930 rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
931 memset(bitmap, 0, sizeof(bitmap));
932 queue = txs->frameid & TXFID_QUEUE_MASK;
933 supr_status = txs->status & TX_STATUS_SUPR_MASK;
934
935 if (txs->status & TX_STATUS_ACK_RCV) {
936 if (TX_STATUS_SUPR_UF == supr_status)
937 update_rate = false;
938
939 WARN_ON(!(txs->status & TX_STATUS_INTERMEDIATE));
940 start_seq = txs->sequence >> SEQNUM_SHIFT;
941 bitmap[0] = (txs->status & TX_STATUS_BA_BMAP03_MASK) >>
942 TX_STATUS_BA_BMAP03_SHIFT;
943
944 WARN_ON(s1 & TX_STATUS_INTERMEDIATE);
945 WARN_ON(!(s1 & TX_STATUS_AMPDU));
946
947 bitmap[0] |=
948 (s1 & TX_STATUS_BA_BMAP47_MASK) <<
949 TX_STATUS_BA_BMAP47_SHIFT;
950 bitmap[1] = (s1 >> 8) & 0xff;
951 bitmap[2] = (s1 >> 16) & 0xff;
952 bitmap[3] = (s1 >> 24) & 0xff;
953
954 bitmap[4] = s2 & 0xff;
955 bitmap[5] = (s2 >> 8) & 0xff;
956 bitmap[6] = (s2 >> 16) & 0xff;
957 bitmap[7] = (s2 >> 24) & 0xff;
958
959 ba_recd = true;
960 } else {
961 if (supr_status) {
962 update_rate = false;
963 if (supr_status == TX_STATUS_SUPR_BADCH) {
964 wiphy_err(wiphy, "%s: Pkt tx suppressed, "
965 "illegal channel possibly %d\n",
966 __func__, CHSPEC_CHANNEL(
967 wlc->default_bss->chanspec));
968 } else {
969 if (supr_status != TX_STATUS_SUPR_FRAG)
970 wiphy_err(wiphy, "%s:"
971 "supr_status 0x%x\n",
972 __func__, supr_status);
973 }
974 /* no need to retry for badch; will fail again */
975 if (supr_status == TX_STATUS_SUPR_BADCH ||
976 supr_status == TX_STATUS_SUPR_EXPTIME) {
977 retry = false;
978 } else if (supr_status == TX_STATUS_SUPR_EXPTIME) {
979 /* TX underflow:
980 * try tuning pre-loading or ampdu size
981 */
982 } else if (supr_status == TX_STATUS_SUPR_FRAG) {
983 /*
984 * if there were underflows, but pre-loading
985 * is not active, notify rate adaptation.
986 */
987 if (brcms_c_ffpld_check_txfunfl(wlc,
988 prio2fifo[tid]) > 0)
989 tx_error = true;
990 }
991 } else if (txs->phyerr) {
992 update_rate = false;
993 wiphy_err(wiphy, "wl%d: ampdu tx phy "
994 "error (0x%x)\n", wlc->pub->unit,
995 txs->phyerr);
996
997 if (brcm_msg_level & LOG_ERROR_VAL) {
998 brcmu_prpkt("txpkt (AMPDU)", p);
999 brcms_c_print_txdesc((struct d11txh *) p->data);
1000 }
1001 brcms_c_print_txstatus(txs);
1002 }
1003 }
1004
1005 /* loop through all pkts and retry if not acked */
1006 while (p) {
1007 tx_info = IEEE80211_SKB_CB(p);
1008 txh = (struct d11txh *) p->data;
1009 mcl = le16_to_cpu(txh->MacTxControlLow);
1010 plcp = (u8 *) (txh + 1);
1011 h = (struct ieee80211_hdr *)(plcp + D11_PHY_HDR_LEN);
1012 seq = le16_to_cpu(h->seq_ctrl) >> SEQNUM_SHIFT;
1013
1014 if (tot_mpdu == 0) {
1015 mcs = plcp[0] & MIMO_PLCP_MCS_MASK;
1016 mimoantsel = le16_to_cpu(txh->ABI_MimoAntSel);
1017 }
1018
1019 index = TX_SEQ_TO_INDEX(seq);
1020 ack_recd = false;
1021 if (ba_recd) {
1022 bindex = MODSUB_POW2(seq, start_seq, SEQNUM_MAX);
1023 BCMMSG(wlc->wiphy, "tid %d seq %d,"
1024 " start_seq %d, bindex %d set %d, index %d\n",
1025 tid, seq, start_seq, bindex,
1026 isset(bitmap, bindex), index);
1027 /* if acked then clear bit and free packet */
1028 if ((bindex < AMPDU_TX_BA_MAX_WSIZE)
1029 && isset(bitmap, bindex)) {
1030 ini->tx_in_transit--;
1031 ini->txretry[index] = 0;
1032
1033 /*
1034 * ampdu_ack_len:
1035 * number of acked aggregated frames
1036 */
1037 /* ampdu_len: number of aggregated frames */
1038 brcms_c_ampdu_rate_status(wlc, tx_info, txs,
1039 mcs);
1040 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1041 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1042 tx_info->status.ampdu_ack_len =
1043 tx_info->status.ampdu_len = 1;
1044
1045 skb_pull(p, D11_PHY_HDR_LEN);
1046 skb_pull(p, D11_TXH_LEN);
1047
1048 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
1049 p);
1050 ack_recd = true;
1051 suc_mpdu++;
1052 }
1053 }
1054 /* either retransmit or send bar if ack not recd */
1055 if (!ack_recd) {
1056 struct ieee80211_tx_rate *txrate =
1057 tx_info->status.rates;
1058 if (retry && (txrate[0].count < (int)retry_limit)) {
1059 ini->txretry[index]++;
1060 ini->tx_in_transit--;
1061 /*
1062 * Use high prededence for retransmit to
1063 * give some punch
1064 */
1065 /* brcms_c_txq_enq(wlc, scb, p,
1066 * BRCMS_PRIO_TO_PREC(tid)); */
1067 brcms_c_txq_enq(wlc, scb, p,
1068 BRCMS_PRIO_TO_HI_PREC(tid));
1069 } else {
1070 /* Retry timeout */
1071 ini->tx_in_transit--;
1072 ieee80211_tx_info_clear_status(tx_info);
1073 tx_info->status.ampdu_ack_len = 0;
1074 tx_info->status.ampdu_len = 1;
1075 tx_info->flags |=
1076 IEEE80211_TX_STAT_AMPDU_NO_BACK;
1077 skb_pull(p, D11_PHY_HDR_LEN);
1078 skb_pull(p, D11_TXH_LEN);
1079 wiphy_err(wiphy, "%s: BA Timeout, seq %d, in_"
1080 "transit %d\n", "AMPDU status", seq,
1081 ini->tx_in_transit);
1082 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
1083 p);
1084 }
1085 }
1086 tot_mpdu++;
1087
1088 /* break out if last packet of ampdu */
1089 if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
1090 TXC_AMPDU_LAST)
1091 break;
1092
1093 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
1094 }
1095 brcms_c_send_q(wlc);
1096
1097 /* update rate state */
1098 antselid = brcms_c_antsel_antsel2id(wlc->asi, mimoantsel);
1099
1100 brcms_c_txfifo_complete(wlc, queue, ampdu->txpkt_weight);
1101}
1102
1103void
1104brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
1105 struct sk_buff *p, struct tx_status *txs)
1106{
1107 struct scb_ampdu *scb_ampdu;
1108 struct brcms_c_info *wlc = ampdu->wlc;
1109 struct scb_ampdu_tid_ini *ini;
1110 u32 s1 = 0, s2 = 0;
1111 struct ieee80211_tx_info *tx_info;
1112
1113 tx_info = IEEE80211_SKB_CB(p);
1114
1115 /* BMAC_NOTE: For the split driver, second level txstatus comes later
1116 * So if the ACK was received then wait for the second level else just
1117 * call the first one
1118 */
1119 if (txs->status & TX_STATUS_ACK_RCV) {
1120 u8 status_delay = 0;
1121
1122 /* wait till the next 8 bytes of txstatus is available */
1123 while (((s1 = R_REG(&wlc->regs->frmtxstatus)) & TXS_V) == 0) {
1124 udelay(1);
1125 status_delay++;
1126 if (status_delay > 10)
1127 return; /* error condition */
1128 }
1129
1130 s2 = R_REG(&wlc->regs->frmtxstatus2);
1131 }
1132
1133 if (scb) {
1134 scb_ampdu = &scb->scb_ampdu;
1135 ini = &scb_ampdu->ini[p->priority];
1136 brcms_c_ampdu_dotxstatus_complete(ampdu, scb, p, txs, s1, s2);
1137 } else {
1138 /* loop through all pkts and free */
1139 u8 queue = txs->frameid & TXFID_QUEUE_MASK;
1140 struct d11txh *txh;
1141 u16 mcl;
1142 while (p) {
1143 tx_info = IEEE80211_SKB_CB(p);
1144 txh = (struct d11txh *) p->data;
1145 mcl = le16_to_cpu(txh->MacTxControlLow);
1146 brcmu_pkt_buf_free_skb(p);
1147 /* break out if last packet of ampdu */
1148 if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
1149 TXC_AMPDU_LAST)
1150 break;
1151 p = dma_getnexttxp(wlc->hw->di[queue],
1152 DMA_RANGE_TRANSMITTED);
1153 }
1154 brcms_c_txfifo_complete(wlc, queue, ampdu->txpkt_weight);
1155 }
1156}
1157
1158void brcms_c_ampdu_macaddr_upd(struct brcms_c_info *wlc)
1159{
1160 char template[T_RAM_ACCESS_SZ * 2];
1161
1162 /* driver needs to write the ta in the template; ta is at offset 16 */
1163 memset(template, 0, sizeof(template));
1164 memcpy(template, wlc->pub->cur_etheraddr, ETH_ALEN);
1165 brcms_b_write_template_ram(wlc->hw, (T_BA_TPL_BASE + 16),
1166 (T_RAM_ACCESS_SZ * 2),
1167 template);
1168}
1169
1170bool brcms_c_aggregatable(struct brcms_c_info *wlc, u8 tid)
1171{
1172 return wlc->ampdu->ini_enable[tid];
1173}
1174
1175void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu)
1176{
1177 struct brcms_c_info *wlc = ampdu->wlc;
1178
1179 /*
1180 * Extend ucode internal watchdog timer to
1181 * match larger received frames
1182 */
1183 if ((ampdu->rx_factor & IEEE80211_HT_AMPDU_PARM_FACTOR) ==
1184 IEEE80211_HT_MAX_AMPDU_64K) {
1185 brcms_b_write_shm(wlc->hw, M_MIMO_MAXSYM, MIMO_MAXSYM_MAX);
1186 brcms_b_write_shm(wlc->hw, M_WATCHDOG_8TU, WATCHDOG_8TU_MAX);
1187 } else {
1188 brcms_b_write_shm(wlc->hw, M_MIMO_MAXSYM, MIMO_MAXSYM_DEF);
1189 brcms_b_write_shm(wlc->hw, M_WATCHDOG_8TU, WATCHDOG_8TU_DEF);
1190 }
1191}
1192
1193/*
1194 * callback function that helps flushing ampdu packets from a priority queue
1195 */
1196static bool cb_del_ampdu_pkt(struct sk_buff *mpdu, void *arg_a)
1197{
1198 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(mpdu);
1199 struct cb_del_ampdu_pars *ampdu_pars =
1200 (struct cb_del_ampdu_pars *)arg_a;
1201 bool rc;
1202
1203 rc = tx_info->flags & IEEE80211_TX_CTL_AMPDU ? true : false;
1204 rc = rc && (tx_info->control.sta == NULL || ampdu_pars->sta == NULL ||
1205 tx_info->control.sta == ampdu_pars->sta);
1206 rc = rc && ((u8)(mpdu->priority) == ampdu_pars->tid);
1207 return rc;
1208}
1209
1210/*
1211 * callback function that helps invalidating ampdu packets in a DMA queue
1212 */
1213static void dma_cb_fn_ampdu(void *txi, void *arg_a)
1214{
1215 struct ieee80211_sta *sta = arg_a;
1216 struct ieee80211_tx_info *tx_info = (struct ieee80211_tx_info *)txi;
1217
1218 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
1219 (tx_info->control.sta == sta || sta == NULL))
1220 tx_info->control.sta = NULL;
1221}
1222
1223/*
1224 * When a remote party is no longer available for ampdu communication, any
1225 * pending tx ampdu packets in the driver have to be flushed.
1226 */
1227void brcms_c_ampdu_flush(struct brcms_c_info *wlc,
1228 struct ieee80211_sta *sta, u16 tid)
1229{
1230 struct brcms_txq_info *qi = wlc->pkt_queue;
1231 struct pktq *pq = &qi->q;
1232 int prec;
1233 struct cb_del_ampdu_pars ampdu_pars;
1234
1235 ampdu_pars.sta = sta;
1236 ampdu_pars.tid = tid;
1237 for (prec = 0; prec < pq->num_prec; prec++)
1238 brcmu_pktq_pflush(pq, prec, true, cb_del_ampdu_pkt,
1239 (void *)&ampdu_pars);
1240 brcms_c_inval_dma_pkts(wlc->hw, sta, dma_cb_fn_ampdu);
1241}
diff --git a/drivers/staging/brcm80211/brcmsmac/ampdu.h b/drivers/staging/brcm80211/brcmsmac/ampdu.h
deleted file mode 100644
index 421f4ba7c63..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/ampdu.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_AMPDU_H_
18#define _BRCM_AMPDU_H_
19
20extern struct ampdu_info *brcms_c_ampdu_attach(struct brcms_c_info *wlc);
21extern void brcms_c_ampdu_detach(struct ampdu_info *ampdu);
22extern int brcms_c_sendampdu(struct ampdu_info *ampdu,
23 struct brcms_txq_info *qi,
24 struct sk_buff **aggp, int prec);
25extern void brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
26 struct sk_buff *p, struct tx_status *txs);
27extern void brcms_c_ampdu_macaddr_upd(struct brcms_c_info *wlc);
28extern void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu);
29
30#endif /* _BRCM_AMPDU_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/antsel.c b/drivers/staging/brcm80211/brcmsmac/antsel.c
deleted file mode 100644
index edc4016fd9a..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/antsel.c
+++ /dev/null
@@ -1,308 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/slab.h>
18#include <net/mac80211.h>
19
20#include "types.h"
21#include "main.h"
22#include "phy_shim.h"
23#include "antsel.h"
24
25#define ANT_SELCFG_AUTO 0x80 /* bit indicates antenna sel AUTO */
26#define ANT_SELCFG_MASK 0x33 /* antenna configuration mask */
27#define ANT_SELCFG_TX_UNICAST 0 /* unicast tx antenna configuration */
28#define ANT_SELCFG_RX_UNICAST 1 /* unicast rx antenna configuration */
29#define ANT_SELCFG_TX_DEF 2 /* default tx antenna configuration */
30#define ANT_SELCFG_RX_DEF 3 /* default rx antenna configuration */
31
32/* useful macros */
33#define BRCMS_ANTSEL_11N_0(ant) ((((ant) & ANT_SELCFG_MASK) >> 4) & 0xf)
34#define BRCMS_ANTSEL_11N_1(ant) (((ant) & ANT_SELCFG_MASK) & 0xf)
35#define BRCMS_ANTIDX_11N(ant) (((BRCMS_ANTSEL_11N_0(ant)) << 2) +\
36 (BRCMS_ANTSEL_11N_1(ant)))
37#define BRCMS_ANT_ISAUTO_11N(ant) (((ant) & ANT_SELCFG_AUTO) == ANT_SELCFG_AUTO)
38#define BRCMS_ANTSEL_11N(ant) ((ant) & ANT_SELCFG_MASK)
39
40/* antenna switch */
41/* defines for no boardlevel antenna diversity */
42#define ANT_SELCFG_DEF_2x2 0x01 /* default antenna configuration */
43
44/* 2x3 antdiv defines and tables for GPIO communication */
45#define ANT_SELCFG_NUM_2x3 3
46#define ANT_SELCFG_DEF_2x3 0x01 /* default antenna configuration */
47
48/* 2x4 antdiv rev4 defines and tables for GPIO communication */
49#define ANT_SELCFG_NUM_2x4 4
50#define ANT_SELCFG_DEF_2x4 0x02 /* default antenna configuration */
51
52static const u16 mimo_2x4_div_antselpat_tbl[] = {
53 0, 0, 0x9, 0xa, /* ant0: 0 ant1: 2,3 */
54 0, 0, 0x5, 0x6, /* ant0: 1 ant1: 2,3 */
55 0, 0, 0, 0, /* n.a. */
56 0, 0, 0, 0 /* n.a. */
57};
58
59static const u8 mimo_2x4_div_antselid_tbl[16] = {
60 0, 0, 0, 0, 0, 2, 3, 0,
61 0, 0, 1, 0, 0, 0, 0, 0 /* pat to antselid */
62};
63
64static const u16 mimo_2x3_div_antselpat_tbl[] = {
65 16, 0, 1, 16, /* ant0: 0 ant1: 1,2 */
66 16, 16, 16, 16, /* n.a. */
67 16, 2, 16, 16, /* ant0: 2 ant1: 1 */
68 16, 16, 16, 16 /* n.a. */
69};
70
71static const u8 mimo_2x3_div_antselid_tbl[16] = {
72 0, 1, 2, 0, 0, 0, 0, 0,
73 0, 0, 0, 0, 0, 0, 0, 0 /* pat to antselid */
74};
75
76/* boardlevel antenna selection: init antenna selection structure */
77static void
78brcms_c_antsel_init_cfg(struct antsel_info *asi, struct brcms_antselcfg *antsel,
79 bool auto_sel)
80{
81 if (asi->antsel_type == ANTSEL_2x3) {
82 u8 antcfg_def = ANT_SELCFG_DEF_2x3 |
83 ((asi->antsel_avail && auto_sel) ? ANT_SELCFG_AUTO : 0);
84 antsel->ant_config[ANT_SELCFG_TX_DEF] = antcfg_def;
85 antsel->ant_config[ANT_SELCFG_TX_UNICAST] = antcfg_def;
86 antsel->ant_config[ANT_SELCFG_RX_DEF] = antcfg_def;
87 antsel->ant_config[ANT_SELCFG_RX_UNICAST] = antcfg_def;
88 antsel->num_antcfg = ANT_SELCFG_NUM_2x3;
89
90 } else if (asi->antsel_type == ANTSEL_2x4) {
91
92 antsel->ant_config[ANT_SELCFG_TX_DEF] = ANT_SELCFG_DEF_2x4;
93 antsel->ant_config[ANT_SELCFG_TX_UNICAST] = ANT_SELCFG_DEF_2x4;
94 antsel->ant_config[ANT_SELCFG_RX_DEF] = ANT_SELCFG_DEF_2x4;
95 antsel->ant_config[ANT_SELCFG_RX_UNICAST] = ANT_SELCFG_DEF_2x4;
96 antsel->num_antcfg = ANT_SELCFG_NUM_2x4;
97
98 } else { /* no antenna selection available */
99
100 antsel->ant_config[ANT_SELCFG_TX_DEF] = ANT_SELCFG_DEF_2x2;
101 antsel->ant_config[ANT_SELCFG_TX_UNICAST] = ANT_SELCFG_DEF_2x2;
102 antsel->ant_config[ANT_SELCFG_RX_DEF] = ANT_SELCFG_DEF_2x2;
103 antsel->ant_config[ANT_SELCFG_RX_UNICAST] = ANT_SELCFG_DEF_2x2;
104 antsel->num_antcfg = 0;
105 }
106}
107
108struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc)
109{
110 struct antsel_info *asi;
111 struct si_pub *sih = wlc->hw->sih;
112
113 asi = kzalloc(sizeof(struct antsel_info), GFP_ATOMIC);
114 if (!asi)
115 return NULL;
116
117 asi->wlc = wlc;
118 asi->pub = wlc->pub;
119 asi->antsel_type = ANTSEL_NA;
120 asi->antsel_avail = false;
121 asi->antsel_antswitch = (u8) getintvar(sih, BRCMS_SROM_ANTSWITCH);
122
123 if ((asi->pub->sromrev >= 4) && (asi->antsel_antswitch != 0)) {
124 switch (asi->antsel_antswitch) {
125 case ANTSWITCH_TYPE_1:
126 case ANTSWITCH_TYPE_2:
127 case ANTSWITCH_TYPE_3:
128 /* 4321/2 board with 2x3 switch logic */
129 asi->antsel_type = ANTSEL_2x3;
130 /* Antenna selection availability */
131 if (((u16) getintvar(sih, BRCMS_SROM_AA2G) == 7) ||
132 ((u16) getintvar(sih, BRCMS_SROM_AA5G) == 7)) {
133 asi->antsel_avail = true;
134 } else if (
135 (u16) getintvar(sih, BRCMS_SROM_AA2G) == 3 ||
136 (u16) getintvar(sih, BRCMS_SROM_AA5G) == 3) {
137 asi->antsel_avail = false;
138 } else {
139 asi->antsel_avail = false;
140 wiphy_err(wlc->wiphy, "antsel_attach: 2o3 "
141 "board cfg invalid\n");
142 }
143
144 break;
145 default:
146 break;
147 }
148 } else if ((asi->pub->sromrev == 4) &&
149 ((u16) getintvar(sih, BRCMS_SROM_AA2G) == 7) &&
150 ((u16) getintvar(sih, BRCMS_SROM_AA5G) == 0)) {
151 /* hack to match old 4321CB2 cards with 2of3 antenna switch */
152 asi->antsel_type = ANTSEL_2x3;
153 asi->antsel_avail = true;
154 } else if (asi->pub->boardflags2 & BFL2_2X4_DIV) {
155 asi->antsel_type = ANTSEL_2x4;
156 asi->antsel_avail = true;
157 }
158
159 /* Set the antenna selection type for the low driver */
160 brcms_b_antsel_type_set(wlc->hw, asi->antsel_type);
161
162 /* Init (auto/manual) antenna selection */
163 brcms_c_antsel_init_cfg(asi, &asi->antcfg_11n, true);
164 brcms_c_antsel_init_cfg(asi, &asi->antcfg_cur, true);
165
166 return asi;
167}
168
169void brcms_c_antsel_detach(struct antsel_info *asi)
170{
171 kfree(asi);
172}
173
174/*
175 * boardlevel antenna selection:
176 * convert ant_cfg to mimo_antsel (ucode interface)
177 */
178static u16 brcms_c_antsel_antcfg2antsel(struct antsel_info *asi, u8 ant_cfg)
179{
180 u8 idx = BRCMS_ANTIDX_11N(BRCMS_ANTSEL_11N(ant_cfg));
181 u16 mimo_antsel = 0;
182
183 if (asi->antsel_type == ANTSEL_2x4) {
184 /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
185 mimo_antsel = (mimo_2x4_div_antselpat_tbl[idx] & 0xf);
186 return mimo_antsel;
187
188 } else if (asi->antsel_type == ANTSEL_2x3) {
189 /* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
190 mimo_antsel = (mimo_2x3_div_antselpat_tbl[idx] & 0xf);
191 return mimo_antsel;
192 }
193
194 return mimo_antsel;
195}
196
197/* boardlevel antenna selection: ucode interface control */
198static int brcms_c_antsel_cfgupd(struct antsel_info *asi,
199 struct brcms_antselcfg *antsel)
200{
201 struct brcms_c_info *wlc = asi->wlc;
202 u8 ant_cfg;
203 u16 mimo_antsel;
204
205 /* 1) Update TX antconfig for all frames that are not unicast data
206 * (aka default TX)
207 */
208 ant_cfg = antsel->ant_config[ANT_SELCFG_TX_DEF];
209 mimo_antsel = brcms_c_antsel_antcfg2antsel(asi, ant_cfg);
210 brcms_b_write_shm(wlc->hw, M_MIMO_ANTSEL_TXDFLT, mimo_antsel);
211 /*
212 * Update driver stats for currently selected
213 * default tx/rx antenna config
214 */
215 asi->antcfg_cur.ant_config[ANT_SELCFG_TX_DEF] = ant_cfg;
216
217 /* 2) Update RX antconfig for all frames that are not unicast data
218 * (aka default RX)
219 */
220 ant_cfg = antsel->ant_config[ANT_SELCFG_RX_DEF];
221 mimo_antsel = brcms_c_antsel_antcfg2antsel(asi, ant_cfg);
222 brcms_b_write_shm(wlc->hw, M_MIMO_ANTSEL_RXDFLT, mimo_antsel);
223 /*
224 * Update driver stats for currently selected
225 * default tx/rx antenna config
226 */
227 asi->antcfg_cur.ant_config[ANT_SELCFG_RX_DEF] = ant_cfg;
228
229 return 0;
230}
231
232void brcms_c_antsel_init(struct antsel_info *asi)
233{
234 if ((asi->antsel_type == ANTSEL_2x3) ||
235 (asi->antsel_type == ANTSEL_2x4))
236 brcms_c_antsel_cfgupd(asi, &asi->antcfg_11n);
237}
238
239/* boardlevel antenna selection: convert id to ant_cfg */
240static u8 brcms_c_antsel_id2antcfg(struct antsel_info *asi, u8 id)
241{
242 u8 antcfg = ANT_SELCFG_DEF_2x2;
243
244 if (asi->antsel_type == ANTSEL_2x4) {
245 /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
246 antcfg = (((id & 0x2) << 3) | ((id & 0x1) + 2));
247 return antcfg;
248
249 } else if (asi->antsel_type == ANTSEL_2x3) {
250 /* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
251 antcfg = (((id & 0x02) << 4) | ((id & 0x1) + 1));
252 return antcfg;
253 }
254
255 return antcfg;
256}
257
258void
259brcms_c_antsel_antcfg_get(struct antsel_info *asi, bool usedef, bool sel,
260 u8 antselid, u8 fbantselid, u8 *antcfg,
261 u8 *fbantcfg)
262{
263 u8 ant;
264
265 /* if use default, assign it and return */
266 if (usedef) {
267 *antcfg = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_DEF];
268 *fbantcfg = *antcfg;
269 return;
270 }
271
272 if (!sel) {
273 *antcfg = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
274 *fbantcfg = *antcfg;
275
276 } else {
277 ant = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
278 if ((ant & ANT_SELCFG_AUTO) == ANT_SELCFG_AUTO) {
279 *antcfg = brcms_c_antsel_id2antcfg(asi, antselid);
280 *fbantcfg = brcms_c_antsel_id2antcfg(asi, fbantselid);
281 } else {
282 *antcfg =
283 asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
284 *fbantcfg = *antcfg;
285 }
286 }
287 return;
288}
289
290/* boardlevel antenna selection: convert mimo_antsel (ucode interface) to id */
291u8 brcms_c_antsel_antsel2id(struct antsel_info *asi, u16 antsel)
292{
293 u8 antselid = 0;
294
295 if (asi->antsel_type == ANTSEL_2x4) {
296 /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
297 antselid = mimo_2x4_div_antselid_tbl[(antsel & 0xf)];
298 return antselid;
299
300 } else if (asi->antsel_type == ANTSEL_2x3) {
301 /* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
302 antselid = mimo_2x3_div_antselid_tbl[(antsel & 0xf)];
303 return antselid;
304 }
305
306 return antselid;
307}
308
diff --git a/drivers/staging/brcm80211/brcmsmac/antsel.h b/drivers/staging/brcm80211/brcmsmac/antsel.h
deleted file mode 100644
index 97ea3881a8e..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/antsel.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_ANTSEL_H_
18#define _BRCM_ANTSEL_H_
19
20extern struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc);
21extern void brcms_c_antsel_detach(struct antsel_info *asi);
22extern void brcms_c_antsel_init(struct antsel_info *asi);
23extern void brcms_c_antsel_antcfg_get(struct antsel_info *asi, bool usedef,
24 bool sel,
25 u8 id, u8 fbid, u8 *antcfg,
26 u8 *fbantcfg);
27extern u8 brcms_c_antsel_antsel2id(struct antsel_info *asi, u16 antsel);
28
29#endif /* _BRCM_ANTSEL_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/brcms_trace_events.c b/drivers/staging/brcm80211/brcmsmac/brcms_trace_events.c
deleted file mode 100644
index 52fc9eeb5fa..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/brcms_trace_events.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/module.h> /* bug in tracepoint.h, it should include this */
18
19#ifndef __CHECKER__
20#include "mac80211_if.h"
21#define CREATE_TRACE_POINTS
22#include "brcms_trace_events.h"
23#endif
diff --git a/drivers/staging/brcm80211/brcmsmac/brcms_trace_events.h b/drivers/staging/brcm80211/brcmsmac/brcms_trace_events.h
deleted file mode 100644
index 27dd73eef56..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/brcms_trace_events.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#undef TRACE_SYSTEM
18#define TRACE_SYSTEM brcmsmac
19
20#if !defined(__TRACE_BRCMSMAC_H) || defined(TRACE_HEADER_MULTI_READ)
21
22#define __TRACE_BRCMSMAC_H
23
24#include <linux/tracepoint.h>
25#include "mac80211_if.h"
26
27#ifndef CONFIG_BRCMDBG
28#undef TRACE_EVENT
29#define TRACE_EVENT(name, proto, ...) \
30static inline void trace_ ## name(proto) {}
31#endif
32
33/*
34 * We define a tracepoint, its arguments, its printk format and its
35 * 'fast binary record' layout.
36 */
37TRACE_EVENT(brcms_timer,
38 /* TPPROTO is the prototype of the function called by this tracepoint */
39 TP_PROTO(struct brcms_timer *t),
40 /*
41 * TPARGS(firstarg, p) are the parameters names, same as found in the
42 * prototype.
43 */
44 TP_ARGS(t),
45 /*
46 * Fast binary tracing: define the trace record via TP_STRUCT__entry().
47 * You can think about it like a regular C structure local variable
48 * definition.
49 */
50 TP_STRUCT__entry(
51 __field(uint, ms)
52 __field(uint, set)
53 __field(uint, periodic)
54 ),
55 TP_fast_assign(
56 __entry->ms = t->ms;
57 __entry->set = t->set;
58 __entry->periodic = t->periodic;
59 ),
60 TP_printk(
61 "ms=%u set=%u periodic=%u",
62 __entry->ms, __entry->set, __entry->periodic
63 )
64);
65
66TRACE_EVENT(brcms_dpc,
67 TP_PROTO(unsigned long data),
68 TP_ARGS(data),
69 TP_STRUCT__entry(
70 __field(unsigned long, data)
71 ),
72 TP_fast_assign(
73 __entry->data = data;
74 ),
75 TP_printk(
76 "data=%p",
77 (void *)__entry->data
78 )
79);
80
81#endif /* __TRACE_BRCMSMAC_H */
82
83#ifdef CONFIG_BRCMDBG
84
85#undef TRACE_INCLUDE_PATH
86#define TRACE_INCLUDE_PATH .
87#undef TRACE_INCLUDE_FILE
88#define TRACE_INCLUDE_FILE brcms_trace_events
89
90#include <trace/define_trace.h>
91
92#endif /* CONFIG_BRCMDBG */
diff --git a/drivers/staging/brcm80211/brcmsmac/channel.c b/drivers/staging/brcm80211/brcmsmac/channel.c
deleted file mode 100644
index a1b415da6c3..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/channel.c
+++ /dev/null
@@ -1,1565 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/types.h>
18#include <net/mac80211.h>
19
20#include <defs.h>
21#include "pub.h"
22#include "phy/phy_hal.h"
23#include "main.h"
24#include "stf.h"
25#include "channel.h"
26
27/* QDB() macro takes a dB value and converts to a quarter dB value */
28#define QDB(n) ((n) * BRCMS_TXPWR_DB_FACTOR)
29
30#define LOCALE_CHAN_01_11 (1<<0)
31#define LOCALE_CHAN_12_13 (1<<1)
32#define LOCALE_CHAN_14 (1<<2)
33#define LOCALE_SET_5G_LOW_JP1 (1<<3) /* 34-48, step 2 */
34#define LOCALE_SET_5G_LOW_JP2 (1<<4) /* 34-46, step 4 */
35#define LOCALE_SET_5G_LOW1 (1<<5) /* 36-48, step 4 */
36#define LOCALE_SET_5G_LOW2 (1<<6) /* 52 */
37#define LOCALE_SET_5G_LOW3 (1<<7) /* 56-64, step 4 */
38#define LOCALE_SET_5G_MID1 (1<<8) /* 100-116, step 4 */
39#define LOCALE_SET_5G_MID2 (1<<9) /* 120-124, step 4 */
40#define LOCALE_SET_5G_MID3 (1<<10) /* 128 */
41#define LOCALE_SET_5G_HIGH1 (1<<11) /* 132-140, step 4 */
42#define LOCALE_SET_5G_HIGH2 (1<<12) /* 149-161, step 4 */
43#define LOCALE_SET_5G_HIGH3 (1<<13) /* 165 */
44#define LOCALE_CHAN_52_140_ALL (1<<14)
45#define LOCALE_SET_5G_HIGH4 (1<<15) /* 184-216 */
46
47#define LOCALE_CHAN_36_64 (LOCALE_SET_5G_LOW1 | \
48 LOCALE_SET_5G_LOW2 | \
49 LOCALE_SET_5G_LOW3)
50#define LOCALE_CHAN_52_64 (LOCALE_SET_5G_LOW2 | LOCALE_SET_5G_LOW3)
51#define LOCALE_CHAN_100_124 (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2)
52#define LOCALE_CHAN_100_140 (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2 | \
53 LOCALE_SET_5G_MID3 | LOCALE_SET_5G_HIGH1)
54#define LOCALE_CHAN_149_165 (LOCALE_SET_5G_HIGH2 | LOCALE_SET_5G_HIGH3)
55#define LOCALE_CHAN_184_216 LOCALE_SET_5G_HIGH4
56
57#define LOCALE_CHAN_01_14 (LOCALE_CHAN_01_11 | \
58 LOCALE_CHAN_12_13 | \
59 LOCALE_CHAN_14)
60
61#define LOCALE_RADAR_SET_NONE 0
62#define LOCALE_RADAR_SET_1 1
63
64#define LOCALE_RESTRICTED_NONE 0
65#define LOCALE_RESTRICTED_SET_2G_SHORT 1
66#define LOCALE_RESTRICTED_CHAN_165 2
67#define LOCALE_CHAN_ALL_5G 3
68#define LOCALE_RESTRICTED_JAPAN_LEGACY 4
69#define LOCALE_RESTRICTED_11D_2G 5
70#define LOCALE_RESTRICTED_11D_5G 6
71#define LOCALE_RESTRICTED_LOW_HI 7
72#define LOCALE_RESTRICTED_12_13_14 8
73
74#define LOCALE_2G_IDX_i 0
75#define LOCALE_5G_IDX_11 0
76#define LOCALE_MIMO_IDX_bn 0
77#define LOCALE_MIMO_IDX_11n 0
78
79/* max of BAND_5G_PWR_LVLS and 6 for 2.4 GHz */
80#define BRCMS_MAXPWR_TBL_SIZE 6
81/* max of BAND_5G_PWR_LVLS and 14 for 2.4 GHz */
82#define BRCMS_MAXPWR_MIMO_TBL_SIZE 14
83
84/* power level in group of 2.4GHz band channels:
85 * maxpwr[0] - CCK channels [1]
86 * maxpwr[1] - CCK channels [2-10]
87 * maxpwr[2] - CCK channels [11-14]
88 * maxpwr[3] - OFDM channels [1]
89 * maxpwr[4] - OFDM channels [2-10]
90 * maxpwr[5] - OFDM channels [11-14]
91 */
92
93/* maxpwr mapping to 5GHz band channels:
94 * maxpwr[0] - channels [34-48]
95 * maxpwr[1] - channels [52-60]
96 * maxpwr[2] - channels [62-64]
97 * maxpwr[3] - channels [100-140]
98 * maxpwr[4] - channels [149-165]
99 */
100#define BAND_5G_PWR_LVLS 5 /* 5 power levels for 5G */
101
102#define LC(id) LOCALE_MIMO_IDX_ ## id
103
104#define LC_2G(id) LOCALE_2G_IDX_ ## id
105
106#define LC_5G(id) LOCALE_5G_IDX_ ## id
107
108#define LOCALES(band2, band5, mimo2, mimo5) \
109 {LC_2G(band2), LC_5G(band5), LC(mimo2), LC(mimo5)}
110
111/* macro to get 2.4 GHz channel group index for tx power */
112#define CHANNEL_POWER_IDX_2G_CCK(c) (((c) < 2) ? 0 : (((c) < 11) ? 1 : 2))
113#define CHANNEL_POWER_IDX_2G_OFDM(c) (((c) < 2) ? 3 : (((c) < 11) ? 4 : 5))
114
115/* macro to get 5 GHz channel group index for tx power */
116#define CHANNEL_POWER_IDX_5G(c) (((c) < 52) ? 0 : \
117 (((c) < 62) ? 1 : \
118 (((c) < 100) ? 2 : \
119 (((c) < 149) ? 3 : 4))))
120
121#define ISDFS_EU(fl) (((fl) & BRCMS_DFS_EU) == BRCMS_DFS_EU)
122
123struct brcms_cm_band {
124 /* struct locale_info flags */
125 u8 locale_flags;
126 /* List of valid channels in the country */
127 struct brcms_chanvec valid_channels;
128 /* List of restricted use channels */
129 const struct brcms_chanvec *restricted_channels;
130 /* List of radar sensitive channels */
131 const struct brcms_chanvec *radar_channels;
132 u8 PAD[8];
133};
134
135 /* locale per-channel tx power limits for MIMO frames
136 * maxpwr arrays are index by channel for 2.4 GHz limits, and
137 * by sub-band for 5 GHz limits using CHANNEL_POWER_IDX_5G(channel)
138 */
139struct locale_mimo_info {
140 /* tx 20 MHz power limits, qdBm units */
141 s8 maxpwr20[BRCMS_MAXPWR_MIMO_TBL_SIZE];
142 /* tx 40 MHz power limits, qdBm units */
143 s8 maxpwr40[BRCMS_MAXPWR_MIMO_TBL_SIZE];
144 u8 flags;
145};
146
147/* Country names and abbreviations with locale defined from ISO 3166 */
148struct country_info {
149 const u8 locale_2G; /* 2.4G band locale */
150 const u8 locale_5G; /* 5G band locale */
151 const u8 locale_mimo_2G; /* 2.4G mimo info */
152 const u8 locale_mimo_5G; /* 5G mimo info */
153};
154
155struct brcms_cm_info {
156 struct brcms_pub *pub;
157 struct brcms_c_info *wlc;
158 char srom_ccode[BRCM_CNTRY_BUF_SZ]; /* Country Code in SROM */
159 uint srom_regrev; /* Regulatory Rev for the SROM ccode */
160 const struct country_info *country; /* current country def */
161 char ccode[BRCM_CNTRY_BUF_SZ]; /* current internal Country Code */
162 uint regrev; /* current Regulatory Revision */
163 char country_abbrev[BRCM_CNTRY_BUF_SZ]; /* current advertised ccode */
164 /* per-band state (one per phy/radio) */
165 struct brcms_cm_band bandstate[MAXBANDS];
166 /* quiet channels currently for radar sensitivity or 11h support */
167 /* channels on which we cannot transmit */
168 struct brcms_chanvec quiet_channels;
169};
170
171/* locale channel and power info. */
172struct locale_info {
173 u32 valid_channels;
174 /* List of radar sensitive channels */
175 u8 radar_channels;
176 /* List of channels used only if APs are detected */
177 u8 restricted_channels;
178 /* Max tx pwr in qdBm for each sub-band */
179 s8 maxpwr[BRCMS_MAXPWR_TBL_SIZE];
180 /* Country IE advertised max tx pwr in dBm per sub-band */
181 s8 pub_maxpwr[BAND_5G_PWR_LVLS];
182 u8 flags;
183};
184
185/* Regulatory Matrix Spreadsheet (CLM) MIMO v3.7.9 */
186
187/*
188 * Some common channel sets
189 */
190
191/* No channels */
192static const struct brcms_chanvec chanvec_none = {
193 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
196 0x00, 0x00, 0x00, 0x00}
197};
198
199/* All 2.4 GHz HW channels */
200static const struct brcms_chanvec chanvec_all_2G = {
201 {0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
202 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
203 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
204 0x00, 0x00, 0x00, 0x00}
205};
206
207/* All 5 GHz HW channels */
208static const struct brcms_chanvec chanvec_all_5G = {
209 {0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x11, 0x11,
210 0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11,
211 0x11, 0x11, 0x20, 0x22, 0x22, 0x00, 0x00, 0x11,
212 0x11, 0x11, 0x11, 0x01}
213};
214
215/*
216 * Radar channel sets
217 */
218
219/* Channels 52 - 64, 100 - 140 */
220static const struct brcms_chanvec radar_set1 = {
221 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, /* 52 - 60 */
222 0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11, /* 64, 100 - 124 */
223 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 128 - 140 */
224 0x00, 0x00, 0x00, 0x00}
225};
226
227/*
228 * Restricted channel sets
229 */
230
231/* Channels 34, 38, 42, 46 */
232static const struct brcms_chanvec restricted_set_japan_legacy = {
233 {0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
234 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
236 0x00, 0x00, 0x00, 0x00}
237};
238
239/* Channels 12, 13 */
240static const struct brcms_chanvec restricted_set_2g_short = {
241 {0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
243 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
244 0x00, 0x00, 0x00, 0x00}
245};
246
247/* Channel 165 */
248static const struct brcms_chanvec restricted_chan_165 = {
249 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
251 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
252 0x00, 0x00, 0x00, 0x00}
253};
254
255/* Channels 36 - 48 & 149 - 165 */
256static const struct brcms_chanvec restricted_low_hi = {
257 {0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x20, 0x22, 0x22, 0x00, 0x00, 0x00,
260 0x00, 0x00, 0x00, 0x00}
261};
262
263/* Channels 12 - 14 */
264static const struct brcms_chanvec restricted_set_12_13_14 = {
265 {0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
266 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
267 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
268 0x00, 0x00, 0x00, 0x00}
269};
270
271/* global memory to provide working buffer for expanded locale */
272
273static const struct brcms_chanvec *g_table_radar_set[] = {
274 &chanvec_none,
275 &radar_set1
276};
277
278static const struct brcms_chanvec *g_table_restricted_chan[] = {
279 &chanvec_none, /* restricted_set_none */
280 &restricted_set_2g_short,
281 &restricted_chan_165,
282 &chanvec_all_5G,
283 &restricted_set_japan_legacy,
284 &chanvec_all_2G, /* restricted_set_11d_2G */
285 &chanvec_all_5G, /* restricted_set_11d_5G */
286 &restricted_low_hi,
287 &restricted_set_12_13_14
288};
289
290static const struct brcms_chanvec locale_2g_01_11 = {
291 {0xfe, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
292 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
293 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
294 0x00, 0x00, 0x00, 0x00}
295};
296
297static const struct brcms_chanvec locale_2g_12_13 = {
298 {0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
299 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
300 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
301 0x00, 0x00, 0x00, 0x00}
302};
303
304static const struct brcms_chanvec locale_2g_14 = {
305 {0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
306 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
307 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
308 0x00, 0x00, 0x00, 0x00}
309};
310
311static const struct brcms_chanvec locale_5g_LOW_JP1 = {
312 {0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01, 0x00,
313 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
314 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
315 0x00, 0x00, 0x00, 0x00}
316};
317
318static const struct brcms_chanvec locale_5g_LOW_JP2 = {
319 {0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
320 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
322 0x00, 0x00, 0x00, 0x00}
323};
324
325static const struct brcms_chanvec locale_5g_LOW1 = {
326 {0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
329 0x00, 0x00, 0x00, 0x00}
330};
331
332static const struct brcms_chanvec locale_5g_LOW2 = {
333 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
334 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
336 0x00, 0x00, 0x00, 0x00}
337};
338
339static const struct brcms_chanvec locale_5g_LOW3 = {
340 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
341 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
342 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
343 0x00, 0x00, 0x00, 0x00}
344};
345
346static const struct brcms_chanvec locale_5g_MID1 = {
347 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
348 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x00,
349 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
350 0x00, 0x00, 0x00, 0x00}
351};
352
353static const struct brcms_chanvec locale_5g_MID2 = {
354 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
356 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
357 0x00, 0x00, 0x00, 0x00}
358};
359
360static const struct brcms_chanvec locale_5g_MID3 = {
361 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
362 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
363 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
364 0x00, 0x00, 0x00, 0x00}
365};
366
367static const struct brcms_chanvec locale_5g_HIGH1 = {
368 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
369 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
370 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
371 0x00, 0x00, 0x00, 0x00}
372};
373
374static const struct brcms_chanvec locale_5g_HIGH2 = {
375 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
376 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
377 0x00, 0x00, 0x20, 0x22, 0x02, 0x00, 0x00, 0x00,
378 0x00, 0x00, 0x00, 0x00}
379};
380
381static const struct brcms_chanvec locale_5g_HIGH3 = {
382 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
383 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
384 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
385 0x00, 0x00, 0x00, 0x00}
386};
387
388static const struct brcms_chanvec locale_5g_52_140_ALL = {
389 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11,
390 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
391 0x11, 0x11, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
392 0x00, 0x00, 0x00, 0x00}
393};
394
395static const struct brcms_chanvec locale_5g_HIGH4 = {
396 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
397 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
398 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
399 0x11, 0x11, 0x11, 0x11}
400};
401
402static const struct brcms_chanvec *g_table_locale_base[] = {
403 &locale_2g_01_11,
404 &locale_2g_12_13,
405 &locale_2g_14,
406 &locale_5g_LOW_JP1,
407 &locale_5g_LOW_JP2,
408 &locale_5g_LOW1,
409 &locale_5g_LOW2,
410 &locale_5g_LOW3,
411 &locale_5g_MID1,
412 &locale_5g_MID2,
413 &locale_5g_MID3,
414 &locale_5g_HIGH1,
415 &locale_5g_HIGH2,
416 &locale_5g_HIGH3,
417 &locale_5g_52_140_ALL,
418 &locale_5g_HIGH4
419};
420
421static void brcms_c_locale_add_channels(struct brcms_chanvec *target,
422 const struct brcms_chanvec *channels)
423{
424 u8 i;
425 for (i = 0; i < sizeof(struct brcms_chanvec); i++)
426 target->vec[i] |= channels->vec[i];
427}
428
429static void brcms_c_locale_get_channels(const struct locale_info *locale,
430 struct brcms_chanvec *channels)
431{
432 u8 i;
433
434 memset(channels, 0, sizeof(struct brcms_chanvec));
435
436 for (i = 0; i < ARRAY_SIZE(g_table_locale_base); i++) {
437 if (locale->valid_channels & (1 << i))
438 brcms_c_locale_add_channels(channels,
439 g_table_locale_base[i]);
440 }
441}
442
443/*
444 * Locale Definitions - 2.4 GHz
445 */
446static const struct locale_info locale_i = { /* locale i. channel 1 - 13 */
447 LOCALE_CHAN_01_11 | LOCALE_CHAN_12_13,
448 LOCALE_RADAR_SET_NONE,
449 LOCALE_RESTRICTED_SET_2G_SHORT,
450 {QDB(19), QDB(19), QDB(19),
451 QDB(19), QDB(19), QDB(19)},
452 {20, 20, 20, 0},
453 BRCMS_EIRP
454};
455
456/*
457 * Locale Definitions - 5 GHz
458 */
459static const struct locale_info locale_11 = {
460 /* locale 11. channel 36 - 48, 52 - 64, 100 - 140, 149 - 165 */
461 LOCALE_CHAN_36_64 | LOCALE_CHAN_100_140 | LOCALE_CHAN_149_165,
462 LOCALE_RADAR_SET_1,
463 LOCALE_RESTRICTED_NONE,
464 {QDB(21), QDB(21), QDB(21), QDB(21), QDB(21)},
465 {23, 23, 23, 30, 30},
466 BRCMS_EIRP | BRCMS_DFS_EU
467};
468
469static const struct locale_info *g_locale_2g_table[] = {
470 &locale_i
471};
472
473static const struct locale_info *g_locale_5g_table[] = {
474 &locale_11
475};
476
477/*
478 * MIMO Locale Definitions - 2.4 GHz
479 */
480static const struct locale_mimo_info locale_bn = {
481 {QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
482 QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
483 QDB(13), QDB(13), QDB(13)},
484 {0, 0, QDB(13), QDB(13), QDB(13),
485 QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
486 QDB(13), 0, 0},
487 0
488};
489
490static const struct locale_mimo_info *g_mimo_2g_table[] = {
491 &locale_bn
492};
493
494/*
495 * MIMO Locale Definitions - 5 GHz
496 */
497static const struct locale_mimo_info locale_11n = {
498 { /* 12.5 dBm */ 50, 50, 50, QDB(15), QDB(15)},
499 {QDB(14), QDB(15), QDB(15), QDB(15), QDB(15)},
500 0
501};
502
503static const struct locale_mimo_info *g_mimo_5g_table[] = {
504 &locale_11n
505};
506
507static const struct {
508 char abbrev[BRCM_CNTRY_BUF_SZ]; /* country abbreviation */
509 struct country_info country;
510} cntry_locales[] = {
511 {
512 "X2", LOCALES(i, 11, bn, 11n)}, /* Worldwide RoW 2 */
513};
514
515#ifdef SUPPORT_40MHZ
516/* 20MHz channel info for 40MHz pairing support */
517struct chan20_info {
518 u8 sb;
519 u8 adj_sbs;
520};
521
522/* indicates adjacent channels that are allowed for a 40 Mhz channel and
523 * those that permitted by the HT
524 */
525struct chan20_info chan20_info[] = {
526 /* 11b/11g */
527/* 0 */ {1, (CH_UPPER_SB | CH_EWA_VALID)},
528/* 1 */ {2, (CH_UPPER_SB | CH_EWA_VALID)},
529/* 2 */ {3, (CH_UPPER_SB | CH_EWA_VALID)},
530/* 3 */ {4, (CH_UPPER_SB | CH_EWA_VALID)},
531/* 4 */ {5, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
532/* 5 */ {6, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
533/* 6 */ {7, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
534/* 7 */ {8, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
535/* 8 */ {9, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
536/* 9 */ {10, (CH_LOWER_SB | CH_EWA_VALID)},
537/* 10 */ {11, (CH_LOWER_SB | CH_EWA_VALID)},
538/* 11 */ {12, (CH_LOWER_SB)},
539/* 12 */ {13, (CH_LOWER_SB)},
540/* 13 */ {14, (CH_LOWER_SB)},
541
542/* 11a japan high */
543/* 14 */ {34, (CH_UPPER_SB)},
544/* 15 */ {38, (CH_LOWER_SB)},
545/* 16 */ {42, (CH_LOWER_SB)},
546/* 17 */ {46, (CH_LOWER_SB)},
547
548/* 11a usa low */
549/* 18 */ {36, (CH_UPPER_SB | CH_EWA_VALID)},
550/* 19 */ {40, (CH_LOWER_SB | CH_EWA_VALID)},
551/* 20 */ {44, (CH_UPPER_SB | CH_EWA_VALID)},
552/* 21 */ {48, (CH_LOWER_SB | CH_EWA_VALID)},
553/* 22 */ {52, (CH_UPPER_SB | CH_EWA_VALID)},
554/* 23 */ {56, (CH_LOWER_SB | CH_EWA_VALID)},
555/* 24 */ {60, (CH_UPPER_SB | CH_EWA_VALID)},
556/* 25 */ {64, (CH_LOWER_SB | CH_EWA_VALID)},
557
558/* 11a Europe */
559/* 26 */ {100, (CH_UPPER_SB | CH_EWA_VALID)},
560/* 27 */ {104, (CH_LOWER_SB | CH_EWA_VALID)},
561/* 28 */ {108, (CH_UPPER_SB | CH_EWA_VALID)},
562/* 29 */ {112, (CH_LOWER_SB | CH_EWA_VALID)},
563/* 30 */ {116, (CH_UPPER_SB | CH_EWA_VALID)},
564/* 31 */ {120, (CH_LOWER_SB | CH_EWA_VALID)},
565/* 32 */ {124, (CH_UPPER_SB | CH_EWA_VALID)},
566/* 33 */ {128, (CH_LOWER_SB | CH_EWA_VALID)},
567/* 34 */ {132, (CH_UPPER_SB | CH_EWA_VALID)},
568/* 35 */ {136, (CH_LOWER_SB | CH_EWA_VALID)},
569/* 36 */ {140, (CH_LOWER_SB)},
570
571/* 11a usa high, ref5 only */
572/* The 0x80 bit in pdiv means these are REF5, other entries are REF20 */
573/* 37 */ {149, (CH_UPPER_SB | CH_EWA_VALID)},
574/* 38 */ {153, (CH_LOWER_SB | CH_EWA_VALID)},
575/* 39 */ {157, (CH_UPPER_SB | CH_EWA_VALID)},
576/* 40 */ {161, (CH_LOWER_SB | CH_EWA_VALID)},
577/* 41 */ {165, (CH_LOWER_SB)},
578
579/* 11a japan */
580/* 42 */ {184, (CH_UPPER_SB)},
581/* 43 */ {188, (CH_LOWER_SB)},
582/* 44 */ {192, (CH_UPPER_SB)},
583/* 45 */ {196, (CH_LOWER_SB)},
584/* 46 */ {200, (CH_UPPER_SB)},
585/* 47 */ {204, (CH_LOWER_SB)},
586/* 48 */ {208, (CH_UPPER_SB)},
587/* 49 */ {212, (CH_LOWER_SB)},
588/* 50 */ {216, (CH_LOWER_SB)}
589};
590#endif /* SUPPORT_40MHZ */
591
592static const struct locale_info *brcms_c_get_locale_2g(u8 locale_idx)
593{
594 if (locale_idx >= ARRAY_SIZE(g_locale_2g_table))
595 return NULL; /* error condition */
596
597 return g_locale_2g_table[locale_idx];
598}
599
600static const struct locale_info *brcms_c_get_locale_5g(u8 locale_idx)
601{
602 if (locale_idx >= ARRAY_SIZE(g_locale_5g_table))
603 return NULL; /* error condition */
604
605 return g_locale_5g_table[locale_idx];
606}
607
608static const struct locale_mimo_info *brcms_c_get_mimo_2g(u8 locale_idx)
609{
610 if (locale_idx >= ARRAY_SIZE(g_mimo_2g_table))
611 return NULL;
612
613 return g_mimo_2g_table[locale_idx];
614}
615
616static const struct locale_mimo_info *brcms_c_get_mimo_5g(u8 locale_idx)
617{
618 if (locale_idx >= ARRAY_SIZE(g_mimo_5g_table))
619 return NULL;
620
621 return g_mimo_5g_table[locale_idx];
622}
623
624static int
625brcms_c_country_aggregate_map(struct brcms_cm_info *wlc_cm, const char *ccode,
626 char *mapped_ccode, uint *mapped_regrev)
627{
628 return false;
629}
630
631/* Lookup a country info structure from a null terminated country
632 * abbreviation and regrev directly with no translation.
633 */
634static const struct country_info *
635brcms_c_country_lookup_direct(const char *ccode, uint regrev)
636{
637 uint size, i;
638
639 /* Should just return 0 for single locale driver. */
640 /* Keep it this way in case we add more locales. (for now anyway) */
641
642 /*
643 * all other country def arrays are for regrev == 0, so if
644 * regrev is non-zero, fail
645 */
646 if (regrev > 0)
647 return NULL;
648
649 /* find matched table entry from country code */
650 size = ARRAY_SIZE(cntry_locales);
651 for (i = 0; i < size; i++) {
652 if (strcmp(ccode, cntry_locales[i].abbrev) == 0)
653 return &cntry_locales[i].country;
654 }
655 return NULL;
656}
657
658static const struct country_info *
659brcms_c_countrycode_map(struct brcms_cm_info *wlc_cm, const char *ccode,
660 char *mapped_ccode, uint *mapped_regrev)
661{
662 struct brcms_c_info *wlc = wlc_cm->wlc;
663 const struct country_info *country;
664 uint srom_regrev = wlc_cm->srom_regrev;
665 const char *srom_ccode = wlc_cm->srom_ccode;
666 int mapped;
667
668 /* check for currently supported ccode size */
669 if (strlen(ccode) > (BRCM_CNTRY_BUF_SZ - 1)) {
670 wiphy_err(wlc->wiphy, "wl%d: %s: ccode \"%s\" too long for "
671 "match\n", wlc->pub->unit, __func__, ccode);
672 return NULL;
673 }
674
675 /* default mapping is the given ccode and regrev 0 */
676 strncpy(mapped_ccode, ccode, BRCM_CNTRY_BUF_SZ);
677 *mapped_regrev = 0;
678
679 /* If the desired country code matches the srom country code,
680 * then the mapped country is the srom regulatory rev.
681 * Otherwise look for an aggregate mapping.
682 */
683 if (!strcmp(srom_ccode, ccode)) {
684 *mapped_regrev = srom_regrev;
685 mapped = 0;
686 wiphy_err(wlc->wiphy, "srom_code == ccode %s\n", __func__);
687 } else {
688 mapped =
689 brcms_c_country_aggregate_map(wlc_cm, ccode, mapped_ccode,
690 mapped_regrev);
691 }
692
693 /* find the matching built-in country definition */
694 country = brcms_c_country_lookup_direct(mapped_ccode, *mapped_regrev);
695
696 /* if there is not an exact rev match, default to rev zero */
697 if (country == NULL && *mapped_regrev != 0) {
698 *mapped_regrev = 0;
699 country =
700 brcms_c_country_lookup_direct(mapped_ccode, *mapped_regrev);
701 }
702
703 return country;
704}
705
706/* Lookup a country info structure from a null terminated country code
707 * The lookup is case sensitive.
708 */
709static const struct country_info *
710brcms_c_country_lookup(struct brcms_c_info *wlc, const char *ccode)
711{
712 const struct country_info *country;
713 char mapped_ccode[BRCM_CNTRY_BUF_SZ];
714 uint mapped_regrev;
715
716 /*
717 * map the country code to a built-in country code, regrev, and
718 * country_info struct
719 */
720 country = brcms_c_countrycode_map(wlc->cmi, ccode, mapped_ccode,
721 &mapped_regrev);
722
723 return country;
724}
725
726/*
727 * reset the quiet channels vector to the union
728 * of the restricted and radar channel sets
729 */
730static void brcms_c_quiet_channels_reset(struct brcms_cm_info *wlc_cm)
731{
732 struct brcms_c_info *wlc = wlc_cm->wlc;
733 uint i, j;
734 struct brcms_band *band;
735 const struct brcms_chanvec *chanvec;
736
737 memset(&wlc_cm->quiet_channels, 0, sizeof(struct brcms_chanvec));
738
739 band = wlc->band;
740 for (i = 0; i < wlc->pub->_nbands;
741 i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
742
743 /* initialize quiet channels for restricted channels */
744 chanvec = wlc_cm->bandstate[band->bandunit].restricted_channels;
745 for (j = 0; j < sizeof(struct brcms_chanvec); j++)
746 wlc_cm->quiet_channels.vec[j] |= chanvec->vec[j];
747
748 }
749}
750
751/* Is the channel valid for the current locale and current band? */
752static bool brcms_c_valid_channel20(struct brcms_cm_info *wlc_cm, uint val)
753{
754 struct brcms_c_info *wlc = wlc_cm->wlc;
755
756 return ((val < MAXCHANNEL) &&
757 isset(wlc_cm->bandstate[wlc->band->bandunit].valid_channels.vec,
758 val));
759}
760
761/* Is the channel valid for the current locale and specified band? */
762static bool brcms_c_valid_channel20_in_band(struct brcms_cm_info *wlc_cm,
763 uint bandunit, uint val)
764{
765 return ((val < MAXCHANNEL)
766 && isset(wlc_cm->bandstate[bandunit].valid_channels.vec, val));
767}
768
769/* Is the channel valid for the current locale? (but don't consider channels not
770 * available due to bandlocking)
771 */
772static bool brcms_c_valid_channel20_db(struct brcms_cm_info *wlc_cm, uint val)
773{
774 struct brcms_c_info *wlc = wlc_cm->wlc;
775
776 return brcms_c_valid_channel20(wlc->cmi, val) ||
777 (!wlc->bandlocked
778 && brcms_c_valid_channel20_in_band(wlc->cmi,
779 OTHERBANDUNIT(wlc), val));
780}
781
782/* JP, J1 - J10 are Japan ccodes */
783static bool brcms_c_japan_ccode(const char *ccode)
784{
785 return (ccode[0] == 'J' &&
786 (ccode[1] == 'P' || (ccode[1] >= '1' && ccode[1] <= '9')));
787}
788
789/* Returns true if currently set country is Japan or variant */
790static bool brcms_c_japan(struct brcms_c_info *wlc)
791{
792 return brcms_c_japan_ccode(wlc->cmi->country_abbrev);
793}
794
795static void
796brcms_c_channel_min_txpower_limits_with_local_constraint(
797 struct brcms_cm_info *wlc_cm, struct txpwr_limits *txpwr,
798 u8 local_constraint_qdbm)
799{
800 int j;
801
802 /* CCK Rates */
803 for (j = 0; j < WL_TX_POWER_CCK_NUM; j++)
804 txpwr->cck[j] = min(txpwr->cck[j], local_constraint_qdbm);
805
806 /* 20 MHz Legacy OFDM SISO */
807 for (j = 0; j < WL_TX_POWER_OFDM_NUM; j++)
808 txpwr->ofdm[j] = min(txpwr->ofdm[j], local_constraint_qdbm);
809
810 /* 20 MHz Legacy OFDM CDD */
811 for (j = 0; j < BRCMS_NUM_RATES_OFDM; j++)
812 txpwr->ofdm_cdd[j] =
813 min(txpwr->ofdm_cdd[j], local_constraint_qdbm);
814
815 /* 40 MHz Legacy OFDM SISO */
816 for (j = 0; j < BRCMS_NUM_RATES_OFDM; j++)
817 txpwr->ofdm_40_siso[j] =
818 min(txpwr->ofdm_40_siso[j], local_constraint_qdbm);
819
820 /* 40 MHz Legacy OFDM CDD */
821 for (j = 0; j < BRCMS_NUM_RATES_OFDM; j++)
822 txpwr->ofdm_40_cdd[j] =
823 min(txpwr->ofdm_40_cdd[j], local_constraint_qdbm);
824
825 /* 20MHz MCS 0-7 SISO */
826 for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
827 txpwr->mcs_20_siso[j] =
828 min(txpwr->mcs_20_siso[j], local_constraint_qdbm);
829
830 /* 20MHz MCS 0-7 CDD */
831 for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
832 txpwr->mcs_20_cdd[j] =
833 min(txpwr->mcs_20_cdd[j], local_constraint_qdbm);
834
835 /* 20MHz MCS 0-7 STBC */
836 for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
837 txpwr->mcs_20_stbc[j] =
838 min(txpwr->mcs_20_stbc[j], local_constraint_qdbm);
839
840 /* 20MHz MCS 8-15 MIMO */
841 for (j = 0; j < BRCMS_NUM_RATES_MCS_2_STREAM; j++)
842 txpwr->mcs_20_mimo[j] =
843 min(txpwr->mcs_20_mimo[j], local_constraint_qdbm);
844
845 /* 40MHz MCS 0-7 SISO */
846 for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
847 txpwr->mcs_40_siso[j] =
848 min(txpwr->mcs_40_siso[j], local_constraint_qdbm);
849
850 /* 40MHz MCS 0-7 CDD */
851 for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
852 txpwr->mcs_40_cdd[j] =
853 min(txpwr->mcs_40_cdd[j], local_constraint_qdbm);
854
855 /* 40MHz MCS 0-7 STBC */
856 for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
857 txpwr->mcs_40_stbc[j] =
858 min(txpwr->mcs_40_stbc[j], local_constraint_qdbm);
859
860 /* 40MHz MCS 8-15 MIMO */
861 for (j = 0; j < BRCMS_NUM_RATES_MCS_2_STREAM; j++)
862 txpwr->mcs_40_mimo[j] =
863 min(txpwr->mcs_40_mimo[j], local_constraint_qdbm);
864
865 /* 40MHz MCS 32 */
866 txpwr->mcs32 = min(txpwr->mcs32, local_constraint_qdbm);
867
868}
869
870/* Update the radio state (enable/disable) and tx power targets
871 * based on a new set of channel/regulatory information
872 */
873static void brcms_c_channels_commit(struct brcms_cm_info *wlc_cm)
874{
875 struct brcms_c_info *wlc = wlc_cm->wlc;
876 uint chan;
877 struct txpwr_limits txpwr;
878
879 /* search for the existence of any valid channel */
880 for (chan = 0; chan < MAXCHANNEL; chan++) {
881 if (brcms_c_valid_channel20_db(wlc->cmi, chan))
882 break;
883 }
884 if (chan == MAXCHANNEL)
885 chan = INVCHANNEL;
886
887 /*
888 * based on the channel search above, set or
889 * clear WL_RADIO_COUNTRY_DISABLE.
890 */
891 if (chan == INVCHANNEL) {
892 /*
893 * country/locale with no valid channels, set
894 * the radio disable bit
895 */
896 mboolset(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
897 wiphy_err(wlc->wiphy, "wl%d: %s: no valid channel for \"%s\" "
898 "nbands %d bandlocked %d\n", wlc->pub->unit,
899 __func__, wlc_cm->country_abbrev, wlc->pub->_nbands,
900 wlc->bandlocked);
901 } else if (mboolisset(wlc->pub->radio_disabled,
902 WL_RADIO_COUNTRY_DISABLE)) {
903 /*
904 * country/locale with valid channel, clear
905 * the radio disable bit
906 */
907 mboolclr(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
908 }
909
910 /*
911 * Now that the country abbreviation is set, if the radio supports 2G,
912 * then set channel 14 restrictions based on the new locale.
913 */
914 if (wlc->pub->_nbands > 1 || wlc->band->bandtype == BRCM_BAND_2G)
915 wlc_phy_chanspec_ch14_widefilter_set(wlc->band->pi,
916 brcms_c_japan(wlc) ? true :
917 false);
918
919 if (wlc->pub->up && chan != INVCHANNEL) {
920 brcms_c_channel_reg_limits(wlc_cm, wlc->chanspec, &txpwr);
921 brcms_c_channel_min_txpower_limits_with_local_constraint(wlc_cm,
922 &txpwr, BRCMS_TXPWR_MAX);
923 wlc_phy_txpower_limit_set(wlc->band->pi, &txpwr, wlc->chanspec);
924 }
925}
926
927static int
928brcms_c_channels_init(struct brcms_cm_info *wlc_cm,
929 const struct country_info *country)
930{
931 struct brcms_c_info *wlc = wlc_cm->wlc;
932 uint i, j;
933 struct brcms_band *band;
934 const struct locale_info *li;
935 struct brcms_chanvec sup_chan;
936 const struct locale_mimo_info *li_mimo;
937
938 band = wlc->band;
939 for (i = 0; i < wlc->pub->_nbands;
940 i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
941
942 li = (band->bandtype == BRCM_BAND_5G) ?
943 brcms_c_get_locale_5g(country->locale_5G) :
944 brcms_c_get_locale_2g(country->locale_2G);
945 wlc_cm->bandstate[band->bandunit].locale_flags = li->flags;
946 li_mimo = (band->bandtype == BRCM_BAND_5G) ?
947 brcms_c_get_mimo_5g(country->locale_mimo_5G) :
948 brcms_c_get_mimo_2g(country->locale_mimo_2G);
949
950 /* merge the mimo non-mimo locale flags */
951 wlc_cm->bandstate[band->bandunit].locale_flags |=
952 li_mimo->flags;
953
954 wlc_cm->bandstate[band->bandunit].restricted_channels =
955 g_table_restricted_chan[li->restricted_channels];
956 wlc_cm->bandstate[band->bandunit].radar_channels =
957 g_table_radar_set[li->radar_channels];
958
959 /*
960 * set the channel availability, masking out the channels
961 * that may not be supported on this phy.
962 */
963 wlc_phy_chanspec_band_validch(band->pi, band->bandtype,
964 &sup_chan);
965 brcms_c_locale_get_channels(li,
966 &wlc_cm->bandstate[band->bandunit].
967 valid_channels);
968 for (j = 0; j < sizeof(struct brcms_chanvec); j++)
969 wlc_cm->bandstate[band->bandunit].valid_channels.
970 vec[j] &= sup_chan.vec[j];
971 }
972
973 brcms_c_quiet_channels_reset(wlc_cm);
974 brcms_c_channels_commit(wlc_cm);
975
976 return 0;
977}
978
979/*
980 * set the driver's current country and regulatory information
981 * using a country code as the source. Look up built in country
982 * information found with the country code.
983 */
984static void
985brcms_c_set_country_common(struct brcms_cm_info *wlc_cm,
986 const char *country_abbrev,
987 const char *ccode, uint regrev,
988 const struct country_info *country)
989{
990 const struct locale_info *locale;
991 struct brcms_c_info *wlc = wlc_cm->wlc;
992 char prev_country_abbrev[BRCM_CNTRY_BUF_SZ];
993
994 /* save current country state */
995 wlc_cm->country = country;
996
997 memset(&prev_country_abbrev, 0, BRCM_CNTRY_BUF_SZ);
998 strncpy(prev_country_abbrev, wlc_cm->country_abbrev,
999 BRCM_CNTRY_BUF_SZ - 1);
1000
1001 strncpy(wlc_cm->country_abbrev, country_abbrev, BRCM_CNTRY_BUF_SZ - 1);
1002 strncpy(wlc_cm->ccode, ccode, BRCM_CNTRY_BUF_SZ - 1);
1003 wlc_cm->regrev = regrev;
1004
1005 if ((wlc->pub->_n_enab & SUPPORT_11N) !=
1006 wlc->protection->nmode_user)
1007 brcms_c_set_nmode(wlc);
1008
1009 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
1010 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
1011 /* set or restore gmode as required by regulatory */
1012 locale = brcms_c_get_locale_2g(country->locale_2G);
1013 if (locale && (locale->flags & BRCMS_NO_OFDM))
1014 brcms_c_set_gmode(wlc, GMODE_LEGACY_B, false);
1015 else
1016 brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
1017
1018 brcms_c_channels_init(wlc_cm, country);
1019
1020 return;
1021}
1022
1023static int
1024brcms_c_set_countrycode_rev(struct brcms_cm_info *wlc_cm,
1025 const char *country_abbrev,
1026 const char *ccode, int regrev)
1027{
1028 const struct country_info *country;
1029 char mapped_ccode[BRCM_CNTRY_BUF_SZ];
1030 uint mapped_regrev;
1031
1032 /* if regrev is -1, lookup the mapped country code,
1033 * otherwise use the ccode and regrev directly
1034 */
1035 if (regrev == -1) {
1036 /*
1037 * map the country code to a built-in country
1038 * code, regrev, and country_info
1039 */
1040 country =
1041 brcms_c_countrycode_map(wlc_cm, ccode, mapped_ccode,
1042 &mapped_regrev);
1043 } else {
1044 /* find the matching built-in country definition */
1045 country = brcms_c_country_lookup_direct(ccode, regrev);
1046 strncpy(mapped_ccode, ccode, BRCM_CNTRY_BUF_SZ);
1047 mapped_regrev = regrev;
1048 }
1049
1050 if (country == NULL)
1051 return -EINVAL;
1052
1053 /* set the driver state for the country */
1054 brcms_c_set_country_common(wlc_cm, country_abbrev, mapped_ccode,
1055 mapped_regrev, country);
1056
1057 return 0;
1058}
1059
1060/*
1061 * set the driver's current country and regulatory information using
1062 * a country code as the source. Lookup built in country information
1063 * found with the country code.
1064 */
1065static int
1066brcms_c_set_countrycode(struct brcms_cm_info *wlc_cm, const char *ccode)
1067{
1068 char country_abbrev[BRCM_CNTRY_BUF_SZ];
1069 strncpy(country_abbrev, ccode, BRCM_CNTRY_BUF_SZ);
1070 return brcms_c_set_countrycode_rev(wlc_cm, country_abbrev, ccode, -1);
1071}
1072
1073struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc)
1074{
1075 struct brcms_cm_info *wlc_cm;
1076 char country_abbrev[BRCM_CNTRY_BUF_SZ];
1077 const struct country_info *country;
1078 struct brcms_pub *pub = wlc->pub;
1079 char *ccode;
1080
1081 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
1082
1083 wlc_cm = kzalloc(sizeof(struct brcms_cm_info), GFP_ATOMIC);
1084 if (wlc_cm == NULL)
1085 return NULL;
1086 wlc_cm->pub = pub;
1087 wlc_cm->wlc = wlc;
1088 wlc->cmi = wlc_cm;
1089
1090 /* store the country code for passing up as a regulatory hint */
1091 ccode = getvar(wlc->hw->sih, BRCMS_SROM_CCODE);
1092 if (ccode)
1093 strncpy(wlc->pub->srom_ccode, ccode, BRCM_CNTRY_BUF_SZ - 1);
1094
1095 /*
1096 * internal country information which must match
1097 * regulatory constraints in firmware
1098 */
1099 memset(country_abbrev, 0, BRCM_CNTRY_BUF_SZ);
1100 strncpy(country_abbrev, "X2", sizeof(country_abbrev) - 1);
1101 country = brcms_c_country_lookup(wlc, country_abbrev);
1102
1103 /* save default country for exiting 11d regulatory mode */
1104 strncpy(wlc->country_default, country_abbrev, BRCM_CNTRY_BUF_SZ - 1);
1105
1106 /* initialize autocountry_default to driver default */
1107 strncpy(wlc->autocountry_default, "X2", BRCM_CNTRY_BUF_SZ - 1);
1108
1109 brcms_c_set_countrycode(wlc_cm, country_abbrev);
1110
1111 return wlc_cm;
1112}
1113
1114void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm)
1115{
1116 kfree(wlc_cm);
1117}
1118
1119u8
1120brcms_c_channel_locale_flags_in_band(struct brcms_cm_info *wlc_cm,
1121 uint bandunit)
1122{
1123 return wlc_cm->bandstate[bandunit].locale_flags;
1124}
1125
1126static bool
1127brcms_c_quiet_chanspec(struct brcms_cm_info *wlc_cm, u16 chspec)
1128{
1129 return (wlc_cm->wlc->pub->_n_enab & SUPPORT_11N) &&
1130 CHSPEC_IS40(chspec) ?
1131 (isset(wlc_cm->quiet_channels.vec,
1132 lower_20_sb(CHSPEC_CHANNEL(chspec))) ||
1133 isset(wlc_cm->quiet_channels.vec,
1134 upper_20_sb(CHSPEC_CHANNEL(chspec)))) :
1135 isset(wlc_cm->quiet_channels.vec, CHSPEC_CHANNEL(chspec));
1136}
1137
1138void
1139brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm, u16 chanspec,
1140 u8 local_constraint_qdbm)
1141{
1142 struct brcms_c_info *wlc = wlc_cm->wlc;
1143 struct txpwr_limits txpwr;
1144
1145 brcms_c_channel_reg_limits(wlc_cm, chanspec, &txpwr);
1146
1147 brcms_c_channel_min_txpower_limits_with_local_constraint(
1148 wlc_cm, &txpwr, local_constraint_qdbm
1149 );
1150
1151 brcms_b_set_chanspec(wlc->hw, chanspec,
1152 (brcms_c_quiet_chanspec(wlc_cm, chanspec) != 0),
1153 &txpwr);
1154}
1155
1156#ifdef POWER_DBG
1157static void wlc_phy_txpower_limits_dump(struct txpwr_limits *txpwr)
1158{
1159 int i;
1160 char buf[80];
1161 char fraction[4][4] = { " ", ".25", ".5 ", ".75" };
1162
1163 sprintf(buf, "CCK ");
1164 for (i = 0; i < BRCMS_NUM_RATES_CCK; i++)
1165 sprintf(buf[strlen(buf)], " %2d%s",
1166 txpwr->cck[i] / BRCMS_TXPWR_DB_FACTOR,
1167 fraction[txpwr->cck[i] % BRCMS_TXPWR_DB_FACTOR]);
1168 printk(KERN_DEBUG "%s\n", buf);
1169
1170 sprintf(buf, "20 MHz OFDM SISO ");
1171 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1172 sprintf(buf[strlen(buf)], " %2d%s",
1173 txpwr->ofdm[i] / BRCMS_TXPWR_DB_FACTOR,
1174 fraction[txpwr->ofdm[i] % BRCMS_TXPWR_DB_FACTOR]);
1175 printk(KERN_DEBUG "%s\n", buf);
1176
1177 sprintf(buf, "20 MHz OFDM CDD ");
1178 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1179 sprintf(buf[strlen(buf)], " %2d%s",
1180 txpwr->ofdm_cdd[i] / BRCMS_TXPWR_DB_FACTOR,
1181 fraction[txpwr->ofdm_cdd[i] % BRCMS_TXPWR_DB_FACTOR]);
1182 printk(KERN_DEBUG "%s\n", buf);
1183
1184 sprintf(buf, "40 MHz OFDM SISO ");
1185 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1186 sprintf(buf[strlen(buf)], " %2d%s",
1187 txpwr->ofdm_40_siso[i] / BRCMS_TXPWR_DB_FACTOR,
1188 fraction[txpwr->ofdm_40_siso[i] %
1189 BRCMS_TXPWR_DB_FACTOR]);
1190 printk(KERN_DEBUG "%s\n", buf);
1191
1192 sprintf(buf, "40 MHz OFDM CDD ");
1193 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1194 sprintf(buf[strlen(buf)], " %2d%s",
1195 txpwr->ofdm_40_cdd[i] / BRCMS_TXPWR_DB_FACTOR,
1196 fraction[txpwr->ofdm_40_cdd[i] %
1197 BRCMS_TXPWR_DB_FACTOR]);
1198 printk(KERN_DEBUG "%s\n", buf);
1199
1200 sprintf(buf, "20 MHz MCS0-7 SISO ");
1201 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1202 sprintf(buf[strlen(buf)], " %2d%s",
1203 txpwr->mcs_20_siso[i] / BRCMS_TXPWR_DB_FACTOR,
1204 fraction[txpwr->mcs_20_siso[i] %
1205 BRCMS_TXPWR_DB_FACTOR]);
1206 printk(KERN_DEBUG "%s\n", buf);
1207
1208 sprintf(buf, "20 MHz MCS0-7 CDD ");
1209 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1210 sprintf(buf[strlen(buf)], " %2d%s",
1211 txpwr->mcs_20_cdd[i] / BRCMS_TXPWR_DB_FACTOR,
1212 fraction[txpwr->mcs_20_cdd[i] %
1213 BRCMS_TXPWR_DB_FACTOR]);
1214 printk(KERN_DEBUG "%s\n", buf);
1215
1216 sprintf(buf, "20 MHz MCS0-7 STBC ");
1217 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1218 sprintf(buf[strlen(buf)], " %2d%s",
1219 txpwr->mcs_20_stbc[i] / BRCMS_TXPWR_DB_FACTOR,
1220 fraction[txpwr->mcs_20_stbc[i] %
1221 BRCMS_TXPWR_DB_FACTOR]);
1222 printk(KERN_DEBUG "%s\n", buf);
1223
1224 sprintf(buf, "20 MHz MCS8-15 SDM ");
1225 for (i = 0; i < BRCMS_NUM_RATES_MCS_2_STREAM; i++)
1226 sprintf(buf[strlen(buf)], " %2d%s",
1227 txpwr->mcs_20_mimo[i] / BRCMS_TXPWR_DB_FACTOR,
1228 fraction[txpwr->mcs_20_mimo[i] %
1229 BRCMS_TXPWR_DB_FACTOR]);
1230 printk(KERN_DEBUG "%s\n", buf);
1231
1232 sprintf(buf, "40 MHz MCS0-7 SISO ");
1233 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1234 sprintf(buf[strlen(buf)], " %2d%s",
1235 txpwr->mcs_40_siso[i] / BRCMS_TXPWR_DB_FACTOR,
1236 fraction[txpwr->mcs_40_siso[i] %
1237 BRCMS_TXPWR_DB_FACTOR]);
1238 printk(KERN_DEBUG "%s\n", buf);
1239
1240 sprintf(buf, "40 MHz MCS0-7 CDD ");
1241 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1242 sprintf(buf[strlen(buf)], " %2d%s",
1243 txpwr->mcs_40_cdd[i] / BRCMS_TXPWR_DB_FACTOR,
1244 fraction[txpwr->mcs_40_cdd[i] %
1245 BRCMS_TXPWR_DB_FACTOR]);
1246 printk(KERN_DEBUG "%s\n", buf);
1247
1248 sprintf(buf, "40 MHz MCS0-7 STBC ");
1249 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++)
1250 sprintf(buf[strlen(buf)], " %2d%s",
1251 txpwr->mcs_40_stbc[i] / BRCMS_TXPWR_DB_FACTOR,
1252 fraction[txpwr->mcs_40_stbc[i] %
1253 BRCMS_TXPWR_DB_FACTOR]);
1254 printk(KERN_DEBUG "%s\n", buf);
1255
1256 sprintf(buf, "40 MHz MCS8-15 SDM ");
1257 for (i = 0; i < BRCMS_NUM_RATES_MCS_2_STREAM; i++)
1258 sprintf(buf[strlen(buf)], " %2d%s",
1259 txpwr->mcs_40_mimo[i] / BRCMS_TXPWR_DB_FACTOR,
1260 fraction[txpwr->mcs_40_mimo[i] %
1261 BRCMS_TXPWR_DB_FACTOR]);
1262 }
1263 printk(KERN_DEBUG "%s\n", buf);
1264
1265 printk(KERN_DEBUG "MCS32 %2d%s\n",
1266 txpwr->mcs32 / BRCMS_TXPWR_DB_FACTOR,
1267 fraction[txpwr->mcs32 % BRCMS_TXPWR_DB_FACTOR]);
1268}
1269#endif /* POWER_DBG */
1270
1271void
1272brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm, u16 chanspec,
1273 struct txpwr_limits *txpwr)
1274{
1275 struct brcms_c_info *wlc = wlc_cm->wlc;
1276 uint i;
1277 uint chan;
1278 int maxpwr;
1279 int delta;
1280 const struct country_info *country;
1281 struct brcms_band *band;
1282 const struct locale_info *li;
1283 int conducted_max = BRCMS_TXPWR_MAX;
1284 int conducted_ofdm_max = BRCMS_TXPWR_MAX;
1285 const struct locale_mimo_info *li_mimo;
1286 int maxpwr20, maxpwr40;
1287 int maxpwr_idx;
1288 uint j;
1289
1290 memset(txpwr, 0, sizeof(struct txpwr_limits));
1291
1292 if (!brcms_c_valid_chanspec_db(wlc_cm, chanspec)) {
1293 country = brcms_c_country_lookup(wlc, wlc->autocountry_default);
1294 if (country == NULL)
1295 return;
1296 } else {
1297 country = wlc_cm->country;
1298 }
1299
1300 chan = CHSPEC_CHANNEL(chanspec);
1301 band = wlc->bandstate[chspec_bandunit(chanspec)];
1302 li = (band->bandtype == BRCM_BAND_5G) ?
1303 brcms_c_get_locale_5g(country->locale_5G) :
1304 brcms_c_get_locale_2g(country->locale_2G);
1305
1306 li_mimo = (band->bandtype == BRCM_BAND_5G) ?
1307 brcms_c_get_mimo_5g(country->locale_mimo_5G) :
1308 brcms_c_get_mimo_2g(country->locale_mimo_2G);
1309
1310 if (li->flags & BRCMS_EIRP) {
1311 delta = band->antgain;
1312 } else {
1313 delta = 0;
1314 if (band->antgain > QDB(6))
1315 delta = band->antgain - QDB(6); /* Excess over 6 dB */
1316 }
1317
1318 if (li == &locale_i) {
1319 conducted_max = QDB(22);
1320 conducted_ofdm_max = QDB(22);
1321 }
1322
1323 /* CCK txpwr limits for 2.4G band */
1324 if (band->bandtype == BRCM_BAND_2G) {
1325 maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_CCK(chan)];
1326
1327 maxpwr = maxpwr - delta;
1328 maxpwr = max(maxpwr, 0);
1329 maxpwr = min(maxpwr, conducted_max);
1330
1331 for (i = 0; i < BRCMS_NUM_RATES_CCK; i++)
1332 txpwr->cck[i] = (u8) maxpwr;
1333 }
1334
1335 /* OFDM txpwr limits for 2.4G or 5G bands */
1336 if (band->bandtype == BRCM_BAND_2G)
1337 maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_OFDM(chan)];
1338 else
1339 maxpwr = li->maxpwr[CHANNEL_POWER_IDX_5G(chan)];
1340
1341 maxpwr = maxpwr - delta;
1342 maxpwr = max(maxpwr, 0);
1343 maxpwr = min(maxpwr, conducted_ofdm_max);
1344
1345 /* Keep OFDM lmit below CCK limit */
1346 if (band->bandtype == BRCM_BAND_2G)
1347 maxpwr = min_t(int, maxpwr, txpwr->cck[0]);
1348
1349 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
1350 txpwr->ofdm[i] = (u8) maxpwr;
1351
1352 for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++) {
1353 /*
1354 * OFDM 40 MHz SISO has the same power as the corresponding
1355 * MCS0-7 rate unless overriden by the locale specific code.
1356 * We set this value to 0 as a flag (presumably 0 dBm isn't
1357 * a possibility) and then copy the MCS0-7 value to the 40 MHz
1358 * value if it wasn't explicitly set.
1359 */
1360 txpwr->ofdm_40_siso[i] = 0;
1361
1362 txpwr->ofdm_cdd[i] = (u8) maxpwr;
1363
1364 txpwr->ofdm_40_cdd[i] = 0;
1365 }
1366
1367 /* MIMO/HT specific limits */
1368 if (li_mimo->flags & BRCMS_EIRP) {
1369 delta = band->antgain;
1370 } else {
1371 delta = 0;
1372 if (band->antgain > QDB(6))
1373 delta = band->antgain - QDB(6); /* Excess over 6 dB */
1374 }
1375
1376 if (band->bandtype == BRCM_BAND_2G)
1377 maxpwr_idx = (chan - 1);
1378 else
1379 maxpwr_idx = CHANNEL_POWER_IDX_5G(chan);
1380
1381 maxpwr20 = li_mimo->maxpwr20[maxpwr_idx];
1382 maxpwr40 = li_mimo->maxpwr40[maxpwr_idx];
1383
1384 maxpwr20 = maxpwr20 - delta;
1385 maxpwr20 = max(maxpwr20, 0);
1386 maxpwr40 = maxpwr40 - delta;
1387 maxpwr40 = max(maxpwr40, 0);
1388
1389 /* Fill in the MCS 0-7 (SISO) rates */
1390 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
1391
1392 /*
1393 * 20 MHz has the same power as the corresponding OFDM rate
1394 * unless overriden by the locale specific code.
1395 */
1396 txpwr->mcs_20_siso[i] = txpwr->ofdm[i];
1397 txpwr->mcs_40_siso[i] = 0;
1398 }
1399
1400 /* Fill in the MCS 0-7 CDD rates */
1401 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
1402 txpwr->mcs_20_cdd[i] = (u8) maxpwr20;
1403 txpwr->mcs_40_cdd[i] = (u8) maxpwr40;
1404 }
1405
1406 /*
1407 * These locales have SISO expressed in the
1408 * table and override CDD later
1409 */
1410 if (li_mimo == &locale_bn) {
1411 if (li_mimo == &locale_bn) {
1412 maxpwr20 = QDB(16);
1413 maxpwr40 = 0;
1414
1415 if (chan >= 3 && chan <= 11)
1416 maxpwr40 = QDB(16);
1417 }
1418
1419 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
1420 txpwr->mcs_20_siso[i] = (u8) maxpwr20;
1421 txpwr->mcs_40_siso[i] = (u8) maxpwr40;
1422 }
1423 }
1424
1425 /* Fill in the MCS 0-7 STBC rates */
1426 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
1427 txpwr->mcs_20_stbc[i] = 0;
1428 txpwr->mcs_40_stbc[i] = 0;
1429 }
1430
1431 /* Fill in the MCS 8-15 SDM rates */
1432 for (i = 0; i < BRCMS_NUM_RATES_MCS_2_STREAM; i++) {
1433 txpwr->mcs_20_mimo[i] = (u8) maxpwr20;
1434 txpwr->mcs_40_mimo[i] = (u8) maxpwr40;
1435 }
1436
1437 /* Fill in MCS32 */
1438 txpwr->mcs32 = (u8) maxpwr40;
1439
1440 for (i = 0, j = 0; i < BRCMS_NUM_RATES_OFDM; i++, j++) {
1441 if (txpwr->ofdm_40_cdd[i] == 0)
1442 txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j];
1443 if (i == 0) {
1444 i = i + 1;
1445 if (txpwr->ofdm_40_cdd[i] == 0)
1446 txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j];
1447 }
1448 }
1449
1450 /*
1451 * Copy the 40 MHZ MCS 0-7 CDD value to the 40 MHZ MCS 0-7 SISO
1452 * value if it wasn't provided explicitly.
1453 */
1454 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
1455 if (txpwr->mcs_40_siso[i] == 0)
1456 txpwr->mcs_40_siso[i] = txpwr->mcs_40_cdd[i];
1457 }
1458
1459 for (i = 0, j = 0; i < BRCMS_NUM_RATES_OFDM; i++, j++) {
1460 if (txpwr->ofdm_40_siso[i] == 0)
1461 txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j];
1462 if (i == 0) {
1463 i = i + 1;
1464 if (txpwr->ofdm_40_siso[i] == 0)
1465 txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j];
1466 }
1467 }
1468
1469 /*
1470 * Copy the 20 and 40 MHz MCS0-7 CDD values to the corresponding
1471 * STBC values if they weren't provided explicitly.
1472 */
1473 for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
1474 if (txpwr->mcs_20_stbc[i] == 0)
1475 txpwr->mcs_20_stbc[i] = txpwr->mcs_20_cdd[i];
1476
1477 if (txpwr->mcs_40_stbc[i] == 0)
1478 txpwr->mcs_40_stbc[i] = txpwr->mcs_40_cdd[i];
1479 }
1480
1481#ifdef POWER_DBG
1482 wlc_phy_txpower_limits_dump(txpwr);
1483#endif
1484 return;
1485}
1486
1487/*
1488 * Validate the chanspec for this locale, for 40MHZ we need to also
1489 * check that the sidebands are valid 20MZH channels in this locale
1490 * and they are also a legal HT combination
1491 */
1492static bool
1493brcms_c_valid_chanspec_ext(struct brcms_cm_info *wlc_cm, u16 chspec,
1494 bool dualband)
1495{
1496 struct brcms_c_info *wlc = wlc_cm->wlc;
1497 u8 channel = CHSPEC_CHANNEL(chspec);
1498
1499 /* check the chanspec */
1500 if (brcmu_chspec_malformed(chspec)) {
1501 wiphy_err(wlc->wiphy, "wl%d: malformed chanspec 0x%x\n",
1502 wlc->pub->unit, chspec);
1503 return false;
1504 }
1505
1506 if (CHANNEL_BANDUNIT(wlc_cm->wlc, channel) !=
1507 chspec_bandunit(chspec))
1508 return false;
1509
1510 /* Check a 20Mhz channel */
1511 if (CHSPEC_IS20(chspec)) {
1512 if (dualband)
1513 return brcms_c_valid_channel20_db(wlc_cm->wlc->cmi,
1514 channel);
1515 else
1516 return brcms_c_valid_channel20(wlc_cm->wlc->cmi,
1517 channel);
1518 }
1519#ifdef SUPPORT_40MHZ
1520 /*
1521 * We know we are now checking a 40MHZ channel, so we should
1522 * only be here for NPHYS
1523 */
1524 if (BRCMS_ISNPHY(wlc->band) || BRCMS_ISSSLPNPHY(wlc->band)) {
1525 u8 upper_sideband = 0, idx;
1526 u8 num_ch20_entries =
1527 sizeof(chan20_info) / sizeof(struct chan20_info);
1528
1529 if (!VALID_40CHANSPEC_IN_BAND(wlc, chspec_bandunit(chspec)))
1530 return false;
1531
1532 if (dualband) {
1533 if (!brcms_c_valid_channel20_db(wlc->cmi,
1534 lower_20_sb(channel)) ||
1535 !brcms_c_valid_channel20_db(wlc->cmi,
1536 upper_20_sb(channel)))
1537 return false;
1538 } else {
1539 if (!brcms_c_valid_channel20(wlc->cmi,
1540 lower_20_sb(channel)) ||
1541 !brcms_c_valid_channel20(wlc->cmi,
1542 upper_20_sb(channel)))
1543 return false;
1544 }
1545
1546 /* find the lower sideband info in the sideband array */
1547 for (idx = 0; idx < num_ch20_entries; idx++) {
1548 if (chan20_info[idx].sb == lower_20_sb(channel))
1549 upper_sideband = chan20_info[idx].adj_sbs;
1550 }
1551 /* check that the lower sideband allows an upper sideband */
1552 if ((upper_sideband & (CH_UPPER_SB | CH_EWA_VALID)) ==
1553 (CH_UPPER_SB | CH_EWA_VALID))
1554 return true;
1555 return false;
1556 }
1557#endif /* 40 MHZ */
1558
1559 return false;
1560}
1561
1562bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm, u16 chspec)
1563{
1564 return brcms_c_valid_chanspec_ext(wlc_cm, chspec, true);
1565}
diff --git a/drivers/staging/brcm80211/brcmsmac/channel.h b/drivers/staging/brcm80211/brcmsmac/channel.h
deleted file mode 100644
index 808cb4fbfbe..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/channel.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_CHANNEL_H_
18#define _BRCM_CHANNEL_H_
19
20/* conversion for phy txpwr calculations that use .25 dB units */
21#define BRCMS_TXPWR_DB_FACTOR 4
22
23/* bits for locale_info flags */
24#define BRCMS_PEAK_CONDUCTED 0x00 /* Peak for locals */
25#define BRCMS_EIRP 0x01 /* Flag for EIRP */
26#define BRCMS_DFS_TPC 0x02 /* Flag for DFS TPC */
27#define BRCMS_NO_OFDM 0x04 /* Flag for No OFDM */
28#define BRCMS_NO_40MHZ 0x08 /* Flag for No MIMO 40MHz */
29#define BRCMS_NO_MIMO 0x10 /* Flag for No MIMO, 20 or 40 MHz */
30#define BRCMS_RADAR_TYPE_EU 0x20 /* Flag for EU */
31#define BRCMS_DFS_FCC BRCMS_DFS_TPC /* Flag for DFS FCC */
32
33#define BRCMS_DFS_EU (BRCMS_DFS_TPC | BRCMS_RADAR_TYPE_EU) /* Flag for DFS EU */
34
35extern struct brcms_cm_info *
36brcms_c_channel_mgr_attach(struct brcms_c_info *wlc);
37
38extern void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm);
39
40extern u8 brcms_c_channel_locale_flags_in_band(struct brcms_cm_info *wlc_cm,
41 uint bandunit);
42
43extern bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm,
44 u16 chspec);
45
46extern void brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm,
47 u16 chanspec,
48 struct txpwr_limits *txpwr);
49extern void brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm,
50 u16 chanspec,
51 u8 local_constraint_qdbm);
52
53#endif /* _WLC_CHANNEL_H */
diff --git a/drivers/staging/brcm80211/brcmsmac/d11.h b/drivers/staging/brcm80211/brcmsmac/d11.h
deleted file mode 100644
index ed51616abc8..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/d11.h
+++ /dev/null
@@ -1,1898 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_D11_H_
18#define _BRCM_D11_H_
19
20#include <linux/ieee80211.h>
21
22#include <defs.h>
23#include "pub.h"
24#include "dma.h"
25
26/* RX FIFO numbers */
27#define RX_FIFO 0 /* data and ctl frames */
28#define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */
29
30/* TX FIFO numbers using WME Access Category */
31#define TX_AC_BK_FIFO 0 /* Background TX FIFO */
32#define TX_AC_BE_FIFO 1 /* Best-Effort TX FIFO */
33#define TX_AC_VI_FIFO 2 /* Video TX FIFO */
34#define TX_AC_VO_FIFO 3 /* Voice TX FIFO */
35#define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */
36#define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */
37
38/* Addr is byte address used by SW; offset is word offset used by uCode */
39
40/* Per AC TX limit settings */
41#define M_AC_TXLMT_BASE_ADDR (0x180 * 2)
42#define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))
43
44/* Legacy TX FIFO numbers */
45#define TX_DATA_FIFO TX_AC_BE_FIFO
46#define TX_CTL_FIFO TX_AC_VO_FIFO
47
48#define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
49
50struct intctrlregs {
51 u32 intstatus;
52 u32 intmask;
53};
54
55/* PIO structure,
56 * support two PIO format: 2 bytes access and 4 bytes access
57 * basic FIFO register set is per channel(transmit or receive)
58 * a pair of channels is defined for convenience
59 */
60/* 2byte-wide pio register set per channel(xmt or rcv) */
61struct pio2regs {
62 u16 fifocontrol;
63 u16 fifodata;
64 u16 fifofree; /* only valid in xmt channel, not in rcv channel */
65 u16 PAD;
66};
67
68/* a pair of pio channels(tx and rx) */
69struct pio2regp {
70 struct pio2regs tx;
71 struct pio2regs rx;
72};
73
74/* 4byte-wide pio register set per channel(xmt or rcv) */
75struct pio4regs {
76 u32 fifocontrol;
77 u32 fifodata;
78};
79
80/* a pair of pio channels(tx and rx) */
81struct pio4regp {
82 struct pio4regs tx;
83 struct pio4regs rx;
84};
85
86/* read: 32-bit register that can be read as 32-bit or as 2 16-bit
87 * write: only low 16b-it half can be written
88 */
89union pmqreg {
90 u32 pmqhostdata; /* read only! */
91 struct {
92 u16 pmqctrlstatus; /* read/write */
93 u16 PAD;
94 } w;
95};
96
97struct fifo64 {
98 struct dma64regs dmaxmt; /* dma tx */
99 struct pio4regs piotx; /* pio tx */
100 struct dma64regs dmarcv; /* dma rx */
101 struct pio4regs piorx; /* pio rx */
102};
103
104/*
105 * Host Interface Registers
106 */
107struct d11regs {
108 /* Device Control ("semi-standard host registers") */
109 u32 PAD[3]; /* 0x0 - 0x8 */
110 u32 biststatus; /* 0xC */
111 u32 biststatus2; /* 0x10 */
112 u32 PAD; /* 0x14 */
113 u32 gptimer; /* 0x18 */
114 u32 usectimer; /* 0x1c *//* for corerev >= 26 */
115
116 /* Interrupt Control *//* 0x20 */
117 struct intctrlregs intctrlregs[8];
118
119 u32 PAD[40]; /* 0x60 - 0xFC */
120
121 u32 intrcvlazy[4]; /* 0x100 - 0x10C */
122
123 u32 PAD[4]; /* 0x110 - 0x11c */
124
125 u32 maccontrol; /* 0x120 */
126 u32 maccommand; /* 0x124 */
127 u32 macintstatus; /* 0x128 */
128 u32 macintmask; /* 0x12C */
129
130 /* Transmit Template Access */
131 u32 tplatewrptr; /* 0x130 */
132 u32 tplatewrdata; /* 0x134 */
133 u32 PAD[2]; /* 0x138 - 0x13C */
134
135 /* PMQ registers */
136 union pmqreg pmqreg; /* 0x140 */
137 u32 pmqpatl; /* 0x144 */
138 u32 pmqpath; /* 0x148 */
139 u32 PAD; /* 0x14C */
140
141 u32 chnstatus; /* 0x150 */
142 u32 psmdebug; /* 0x154 */
143 u32 phydebug; /* 0x158 */
144 u32 machwcap; /* 0x15C */
145
146 /* Extended Internal Objects */
147 u32 objaddr; /* 0x160 */
148 u32 objdata; /* 0x164 */
149 u32 PAD[2]; /* 0x168 - 0x16c */
150
151 u32 frmtxstatus; /* 0x170 */
152 u32 frmtxstatus2; /* 0x174 */
153 u32 PAD[2]; /* 0x178 - 0x17c */
154
155 /* TSF host access */
156 u32 tsf_timerlow; /* 0x180 */
157 u32 tsf_timerhigh; /* 0x184 */
158 u32 tsf_cfprep; /* 0x188 */
159 u32 tsf_cfpstart; /* 0x18c */
160 u32 tsf_cfpmaxdur32; /* 0x190 */
161 u32 PAD[3]; /* 0x194 - 0x19c */
162
163 u32 maccontrol1; /* 0x1a0 */
164 u32 machwcap1; /* 0x1a4 */
165 u32 PAD[14]; /* 0x1a8 - 0x1dc */
166
167 /* Clock control and hardware workarounds*/
168 u32 clk_ctl_st; /* 0x1e0 */
169 u32 hw_war;
170 u32 d11_phypllctl; /* the phypll request/avail bits are
171 * moved to clk_ctl_st
172 */
173 u32 PAD[5]; /* 0x1ec - 0x1fc */
174
175 /* 0x200-0x37F dma/pio registers */
176 struct fifo64 fifo64regs[6];
177
178 /* FIFO diagnostic port access */
179 struct dma32diag dmafifo; /* 0x380 - 0x38C */
180
181 u32 aggfifocnt; /* 0x390 */
182 u32 aggfifodata; /* 0x394 */
183 u32 PAD[16]; /* 0x398 - 0x3d4 */
184 u16 radioregaddr; /* 0x3d8 */
185 u16 radioregdata; /* 0x3da */
186
187 /*
188 * time delay between the change on rf disable input and
189 * radio shutdown
190 */
191 u32 rfdisabledly; /* 0x3DC */
192
193 /* PHY register access */
194 u16 phyversion; /* 0x3e0 - 0x0 */
195 u16 phybbconfig; /* 0x3e2 - 0x1 */
196 u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
197 u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
198 u16 phyrxstatus0; /* 0x3e8 - 0x4 */
199 u16 phyrxstatus1; /* 0x3ea - 0x5 */
200 u16 phycrsth; /* 0x3ec - 0x6 */
201 u16 phytxerror; /* 0x3ee - 0x7 */
202 u16 phychannel; /* 0x3f0 - 0x8 */
203 u16 PAD[1]; /* 0x3f2 - 0x9 */
204 u16 phytest; /* 0x3f4 - 0xa */
205 u16 phy4waddr; /* 0x3f6 - 0xb */
206 u16 phy4wdatahi; /* 0x3f8 - 0xc */
207 u16 phy4wdatalo; /* 0x3fa - 0xd */
208 u16 phyregaddr; /* 0x3fc - 0xe */
209 u16 phyregdata; /* 0x3fe - 0xf */
210
211 /* IHR *//* 0x400 - 0x7FE */
212
213 /* RXE Block */
214 u16 PAD[3]; /* 0x400 - 0x406 */
215 u16 rcv_fifo_ctl; /* 0x406 */
216 u16 PAD; /* 0x408 - 0x40a */
217 u16 rcv_frm_cnt; /* 0x40a */
218 u16 PAD[4]; /* 0x40a - 0x414 */
219 u16 rssi; /* 0x414 */
220 u16 PAD[5]; /* 0x414 - 0x420 */
221 u16 rcm_ctl; /* 0x420 */
222 u16 rcm_mat_data; /* 0x422 */
223 u16 rcm_mat_mask; /* 0x424 */
224 u16 rcm_mat_dly; /* 0x426 */
225 u16 rcm_cond_mask_l; /* 0x428 */
226 u16 rcm_cond_mask_h; /* 0x42A */
227 u16 rcm_cond_dly; /* 0x42C */
228 u16 PAD[1]; /* 0x42E */
229 u16 ext_ihr_addr; /* 0x430 */
230 u16 ext_ihr_data; /* 0x432 */
231 u16 rxe_phyrs_2; /* 0x434 */
232 u16 rxe_phyrs_3; /* 0x436 */
233 u16 phy_mode; /* 0x438 */
234 u16 rcmta_ctl; /* 0x43a */
235 u16 rcmta_size; /* 0x43c */
236 u16 rcmta_addr0; /* 0x43e */
237 u16 rcmta_addr1; /* 0x440 */
238 u16 rcmta_addr2; /* 0x442 */
239 u16 PAD[30]; /* 0x444 - 0x480 */
240
241 /* PSM Block *//* 0x480 - 0x500 */
242
243 u16 PAD; /* 0x480 */
244 u16 psm_maccontrol_h; /* 0x482 */
245 u16 psm_macintstatus_l; /* 0x484 */
246 u16 psm_macintstatus_h; /* 0x486 */
247 u16 psm_macintmask_l; /* 0x488 */
248 u16 psm_macintmask_h; /* 0x48A */
249 u16 PAD; /* 0x48C */
250 u16 psm_maccommand; /* 0x48E */
251 u16 psm_brc; /* 0x490 */
252 u16 psm_phy_hdr_param; /* 0x492 */
253 u16 psm_postcard; /* 0x494 */
254 u16 psm_pcard_loc_l; /* 0x496 */
255 u16 psm_pcard_loc_h; /* 0x498 */
256 u16 psm_gpio_in; /* 0x49A */
257 u16 psm_gpio_out; /* 0x49C */
258 u16 psm_gpio_oe; /* 0x49E */
259
260 u16 psm_bred_0; /* 0x4A0 */
261 u16 psm_bred_1; /* 0x4A2 */
262 u16 psm_bred_2; /* 0x4A4 */
263 u16 psm_bred_3; /* 0x4A6 */
264 u16 psm_brcl_0; /* 0x4A8 */
265 u16 psm_brcl_1; /* 0x4AA */
266 u16 psm_brcl_2; /* 0x4AC */
267 u16 psm_brcl_3; /* 0x4AE */
268 u16 psm_brpo_0; /* 0x4B0 */
269 u16 psm_brpo_1; /* 0x4B2 */
270 u16 psm_brpo_2; /* 0x4B4 */
271 u16 psm_brpo_3; /* 0x4B6 */
272 u16 psm_brwk_0; /* 0x4B8 */
273 u16 psm_brwk_1; /* 0x4BA */
274 u16 psm_brwk_2; /* 0x4BC */
275 u16 psm_brwk_3; /* 0x4BE */
276
277 u16 psm_base_0; /* 0x4C0 */
278 u16 psm_base_1; /* 0x4C2 */
279 u16 psm_base_2; /* 0x4C4 */
280 u16 psm_base_3; /* 0x4C6 */
281 u16 psm_base_4; /* 0x4C8 */
282 u16 psm_base_5; /* 0x4CA */
283 u16 psm_base_6; /* 0x4CC */
284 u16 psm_pc_reg_0; /* 0x4CE */
285 u16 psm_pc_reg_1; /* 0x4D0 */
286 u16 psm_pc_reg_2; /* 0x4D2 */
287 u16 psm_pc_reg_3; /* 0x4D4 */
288 u16 PAD[0xD]; /* 0x4D6 - 0x4DE */
289 u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */
290 u16 PAD[0x7]; /* 0x4f2 - 0x4fE */
291
292 /* TXE0 Block *//* 0x500 - 0x580 */
293 u16 txe_ctl; /* 0x500 */
294 u16 txe_aux; /* 0x502 */
295 u16 txe_ts_loc; /* 0x504 */
296 u16 txe_time_out; /* 0x506 */
297 u16 txe_wm_0; /* 0x508 */
298 u16 txe_wm_1; /* 0x50A */
299 u16 txe_phyctl; /* 0x50C */
300 u16 txe_status; /* 0x50E */
301 u16 txe_mmplcp0; /* 0x510 */
302 u16 txe_mmplcp1; /* 0x512 */
303 u16 txe_phyctl1; /* 0x514 */
304
305 u16 PAD[0x05]; /* 0x510 - 0x51E */
306
307 /* Transmit control */
308 u16 xmtfifodef; /* 0x520 */
309 u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */
310 u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */
311 u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */
312 u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */
313 u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */
314 u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */
315
316 u16 PAD[0x09]; /* 0x52E - 0x53E */
317
318 u16 xmtfifocmd; /* 0x540 */
319 u16 xmtfifoflush; /* 0x542 */
320 u16 xmtfifothresh; /* 0x544 */
321 u16 xmtfifordy; /* 0x546 */
322 u16 xmtfifoprirdy; /* 0x548 */
323 u16 xmtfiforqpri; /* 0x54A */
324 u16 xmttplatetxptr; /* 0x54C */
325 u16 PAD; /* 0x54E */
326 u16 xmttplateptr; /* 0x550 */
327 u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */
328 u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */
329 u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */
330 u16 PAD[0x04]; /* 0x558 - 0x55E */
331 u16 xmttplatedatalo; /* 0x560 */
332 u16 xmttplatedatahi; /* 0x562 */
333
334 u16 PAD[2]; /* 0x564 - 0x566 */
335
336 u16 xmtsel; /* 0x568 */
337 u16 xmttxcnt; /* 0x56A */
338 u16 xmttxshmaddr; /* 0x56C */
339
340 u16 PAD[0x09]; /* 0x56E - 0x57E */
341
342 /* TXE1 Block */
343 u16 PAD[0x40]; /* 0x580 - 0x5FE */
344
345 /* TSF Block */
346 u16 PAD[0X02]; /* 0x600 - 0x602 */
347 u16 tsf_cfpstrt_l; /* 0x604 */
348 u16 tsf_cfpstrt_h; /* 0x606 */
349 u16 PAD[0X05]; /* 0x608 - 0x610 */
350 u16 tsf_cfppretbtt; /* 0x612 */
351 u16 PAD[0XD]; /* 0x614 - 0x62C */
352 u16 tsf_clk_frac_l; /* 0x62E */
353 u16 tsf_clk_frac_h; /* 0x630 */
354 u16 PAD[0X14]; /* 0x632 - 0x658 */
355 u16 tsf_random; /* 0x65A */
356 u16 PAD[0x05]; /* 0x65C - 0x664 */
357 /* GPTimer 2 registers */
358 u16 tsf_gpt2_stat; /* 0x666 */
359 u16 tsf_gpt2_ctr_l; /* 0x668 */
360 u16 tsf_gpt2_ctr_h; /* 0x66A */
361 u16 tsf_gpt2_val_l; /* 0x66C */
362 u16 tsf_gpt2_val_h; /* 0x66E */
363 u16 tsf_gptall_stat; /* 0x670 */
364 u16 PAD[0x07]; /* 0x672 - 0x67E */
365
366 /* IFS Block */
367 u16 ifs_sifs_rx_tx_tx; /* 0x680 */
368 u16 ifs_sifs_nav_tx; /* 0x682 */
369 u16 ifs_slot; /* 0x684 */
370 u16 PAD; /* 0x686 */
371 u16 ifs_ctl; /* 0x688 */
372 u16 PAD[0x3]; /* 0x68a - 0x68F */
373 u16 ifsstat; /* 0x690 */
374 u16 ifsmedbusyctl; /* 0x692 */
375 u16 iftxdur; /* 0x694 */
376 u16 PAD[0x3]; /* 0x696 - 0x69b */
377 /* EDCF support in dot11macs */
378 u16 ifs_aifsn; /* 0x69c */
379 u16 ifs_ctl1; /* 0x69e */
380
381 /* slow clock registers */
382 u16 scc_ctl; /* 0x6a0 */
383 u16 scc_timer_l; /* 0x6a2 */
384 u16 scc_timer_h; /* 0x6a4 */
385 u16 scc_frac; /* 0x6a6 */
386 u16 scc_fastpwrup_dly; /* 0x6a8 */
387 u16 scc_per; /* 0x6aa */
388 u16 scc_per_frac; /* 0x6ac */
389 u16 scc_cal_timer_l; /* 0x6ae */
390 u16 scc_cal_timer_h; /* 0x6b0 */
391 u16 PAD; /* 0x6b2 */
392
393 u16 PAD[0x26];
394
395 /* NAV Block */
396 u16 nav_ctl; /* 0x700 */
397 u16 navstat; /* 0x702 */
398 u16 PAD[0x3e]; /* 0x702 - 0x77E */
399
400 /* WEP/PMQ Block *//* 0x780 - 0x7FE */
401 u16 PAD[0x20]; /* 0x780 - 0x7BE */
402
403 u16 wepctl; /* 0x7C0 */
404 u16 wepivloc; /* 0x7C2 */
405 u16 wepivkey; /* 0x7C4 */
406 u16 wepwkey; /* 0x7C6 */
407
408 u16 PAD[4]; /* 0x7C8 - 0x7CE */
409 u16 pcmctl; /* 0X7D0 */
410 u16 pcmstat; /* 0X7D2 */
411 u16 PAD[6]; /* 0x7D4 - 0x7DE */
412
413 u16 pmqctl; /* 0x7E0 */
414 u16 pmqstatus; /* 0x7E2 */
415 u16 pmqpat0; /* 0x7E4 */
416 u16 pmqpat1; /* 0x7E6 */
417 u16 pmqpat2; /* 0x7E8 */
418
419 u16 pmqdat; /* 0x7EA */
420 u16 pmqdator; /* 0x7EC */
421 u16 pmqhst; /* 0x7EE */
422 u16 pmqpath0; /* 0x7F0 */
423 u16 pmqpath1; /* 0x7F2 */
424 u16 pmqpath2; /* 0x7F4 */
425 u16 pmqdath; /* 0x7F6 */
426
427 u16 PAD[0x04]; /* 0x7F8 - 0x7FE */
428
429 /* SHM *//* 0x800 - 0xEFE */
430 u16 PAD[0x380]; /* 0x800 - 0xEFE */
431};
432
433#define PIHR_BASE 0x0400 /* byte address of packed IHR region */
434
435/* biststatus */
436#define BT_DONE (1U << 31) /* bist done */
437#define BT_B2S (1 << 30) /* bist2 ram summary bit */
438
439/* intstatus and intmask */
440#define I_PC (1 << 10) /* pci descriptor error */
441#define I_PD (1 << 11) /* pci data error */
442#define I_DE (1 << 12) /* descriptor protocol error */
443#define I_RU (1 << 13) /* receive descriptor underflow */
444#define I_RO (1 << 14) /* receive fifo overflow */
445#define I_XU (1 << 15) /* transmit fifo underflow */
446#define I_RI (1 << 16) /* receive interrupt */
447#define I_XI (1 << 24) /* transmit interrupt */
448
449/* interrupt receive lazy */
450#define IRL_TO_MASK 0x00ffffff /* timeout */
451#define IRL_FC_MASK 0xff000000 /* frame count */
452#define IRL_FC_SHIFT 24 /* frame count */
453
454/*== maccontrol register ==*/
455#define MCTL_GMODE (1U << 31)
456#define MCTL_DISCARD_PMQ (1 << 30)
457#define MCTL_WAKE (1 << 26)
458#define MCTL_HPS (1 << 25)
459#define MCTL_PROMISC (1 << 24)
460#define MCTL_KEEPBADFCS (1 << 23)
461#define MCTL_KEEPCONTROL (1 << 22)
462#define MCTL_PHYLOCK (1 << 21)
463#define MCTL_BCNS_PROMISC (1 << 20)
464#define MCTL_LOCK_RADIO (1 << 19)
465#define MCTL_AP (1 << 18)
466#define MCTL_INFRA (1 << 17)
467#define MCTL_BIGEND (1 << 16)
468#define MCTL_GPOUT_SEL_MASK (3 << 14)
469#define MCTL_GPOUT_SEL_SHIFT 14
470#define MCTL_EN_PSMDBG (1 << 13)
471#define MCTL_IHR_EN (1 << 10)
472#define MCTL_SHM_UPPER (1 << 9)
473#define MCTL_SHM_EN (1 << 8)
474#define MCTL_PSM_JMP_0 (1 << 2)
475#define MCTL_PSM_RUN (1 << 1)
476#define MCTL_EN_MAC (1 << 0)
477
478/*== maccommand register ==*/
479#define MCMD_BCN0VLD (1 << 0)
480#define MCMD_BCN1VLD (1 << 1)
481#define MCMD_DIRFRMQVAL (1 << 2)
482#define MCMD_CCA (1 << 3)
483#define MCMD_BG_NOISE (1 << 4)
484#define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */
485#define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */
486
487/*== macintstatus/macintmask ==*/
488/* gracefully suspended */
489#define MI_MACSSPNDD (1 << 0)
490/* beacon template available */
491#define MI_BCNTPL (1 << 1)
492/* TBTT indication */
493#define MI_TBTT (1 << 2)
494/* beacon successfully tx'd */
495#define MI_BCNSUCCESS (1 << 3)
496/* beacon canceled (IBSS) */
497#define MI_BCNCANCLD (1 << 4)
498/* end of ATIM-window (IBSS) */
499#define MI_ATIMWINEND (1 << 5)
500/* PMQ entries available */
501#define MI_PMQ (1 << 6)
502/* non-specific gen-stat bits that are set by PSM */
503#define MI_NSPECGEN_0 (1 << 7)
504/* non-specific gen-stat bits that are set by PSM */
505#define MI_NSPECGEN_1 (1 << 8)
506/* MAC level Tx error */
507#define MI_MACTXERR (1 << 9)
508/* non-specific gen-stat bits that are set by PSM */
509#define MI_NSPECGEN_3 (1 << 10)
510/* PHY Tx error */
511#define MI_PHYTXERR (1 << 11)
512/* Power Management Event */
513#define MI_PME (1 << 12)
514/* General-purpose timer0 */
515#define MI_GP0 (1 << 13)
516/* General-purpose timer1 */
517#define MI_GP1 (1 << 14)
518/* (ORed) DMA-interrupts */
519#define MI_DMAINT (1 << 15)
520/* MAC has completed a TX FIFO Suspend/Flush */
521#define MI_TXSTOP (1 << 16)
522/* MAC has completed a CCA measurement */
523#define MI_CCA (1 << 17)
524/* MAC has collected background noise samples */
525#define MI_BG_NOISE (1 << 18)
526/* MBSS DTIM TBTT indication */
527#define MI_DTIM_TBTT (1 << 19)
528/* Probe response queue needs attention */
529#define MI_PRQ (1 << 20)
530/* Radio/PHY has been powered back up. */
531#define MI_PWRUP (1 << 21)
532#define MI_RESERVED3 (1 << 22)
533#define MI_RESERVED2 (1 << 23)
534#define MI_RESERVED1 (1 << 25)
535/* MAC detected change on RF Disable input*/
536#define MI_RFDISABLE (1 << 28)
537/* MAC has completed a TX */
538#define MI_TFS (1 << 29)
539/* A phy status change wrt G mode */
540#define MI_PHYCHANGED (1 << 30)
541/* general purpose timeout */
542#define MI_TO (1U << 31)
543
544/* Mac capabilities registers */
545/*== machwcap ==*/
546#define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */
547
548/*== pmqhost data ==*/
549/* data entry of head pmq entry */
550#define PMQH_DATA_MASK 0xffff0000
551/* PM entry for BSS config */
552#define PMQH_BSSCFG 0x00100000
553/* PM Mode OFF: power save off */
554#define PMQH_PMOFF 0x00010000
555/* PM Mode ON: power save on */
556#define PMQH_PMON 0x00020000
557/* Dis-associated or De-authenticated */
558#define PMQH_DASAT 0x00040000
559/* ATIM not acknowledged */
560#define PMQH_ATIMFAIL 0x00080000
561/* delete head entry */
562#define PMQH_DEL_ENTRY 0x00000001
563/* delete head entry to cur read pointer -1 */
564#define PMQH_DEL_MULT 0x00000002
565/* pmq overflow indication */
566#define PMQH_OFLO 0x00000004
567/* entries are present in pmq */
568#define PMQH_NOT_EMPTY 0x00000008
569
570/*== phydebug ==*/
571/* phy is asserting carrier sense */
572#define PDBG_CRS (1 << 0)
573/* phy is taking xmit byte from mac this cycle */
574#define PDBG_TXA (1 << 1)
575/* mac is instructing the phy to transmit a frame */
576#define PDBG_TXF (1 << 2)
577/* phy is signalling a transmit Error to the mac */
578#define PDBG_TXE (1 << 3)
579/* phy detected the end of a valid frame preamble */
580#define PDBG_RXF (1 << 4)
581/* phy detected the end of a valid PLCP header */
582#define PDBG_RXS (1 << 5)
583/* rx start not asserted */
584#define PDBG_RXFRG (1 << 6)
585/* mac is taking receive byte from phy this cycle */
586#define PDBG_RXV (1 << 7)
587/* RF portion of the radio is disabled */
588#define PDBG_RFD (1 << 16)
589
590/*== objaddr register ==*/
591#define OBJADDR_SEL_MASK 0x000F0000
592#define OBJADDR_UCM_SEL 0x00000000
593#define OBJADDR_SHM_SEL 0x00010000
594#define OBJADDR_SCR_SEL 0x00020000
595#define OBJADDR_IHR_SEL 0x00030000
596#define OBJADDR_RCMTA_SEL 0x00040000
597#define OBJADDR_SRCHM_SEL 0x00060000
598#define OBJADDR_WINC 0x01000000
599#define OBJADDR_RINC 0x02000000
600#define OBJADDR_AUTO_INC 0x03000000
601
602#define WEP_PCMADDR 0x07d4
603#define WEP_PCMDATA 0x07d6
604
605/*== frmtxstatus ==*/
606#define TXS_V (1 << 0) /* valid bit */
607#define TXS_STATUS_MASK 0xffff
608#define TXS_FID_MASK 0xffff0000
609#define TXS_FID_SHIFT 16
610
611/*== frmtxstatus2 ==*/
612#define TXS_SEQ_MASK 0xffff
613#define TXS_PTX_MASK 0xff0000
614#define TXS_PTX_SHIFT 16
615#define TXS_MU_MASK 0x01000000
616#define TXS_MU_SHIFT 24
617
618/*== clk_ctl_st ==*/
619#define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */
620#define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */
621#define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */
622#define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */
623
624/* HT Cloclk Ctrl and Clock Avail for 4313 */
625#define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */
626#define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */
627
628/* tsf_cfprep register */
629#define CFPREP_CBI_MASK 0xffffffc0
630#define CFPREP_CBI_SHIFT 6
631#define CFPREP_CFPP 0x00000001
632
633/* tx fifo sizes values are in terms of 256 byte blocks */
634#define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */
635#define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */
636#define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */
637
638#define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */
639#define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */
640#define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */
641#define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */
642
643/*== phy versions (PhyVersion:Revision field) ==*/
644/* analog block version */
645#define PV_AV_MASK 0xf000
646/* analog block version bitfield offset */
647#define PV_AV_SHIFT 12
648/* phy type */
649#define PV_PT_MASK 0x0f00
650/* phy type bitfield offset */
651#define PV_PT_SHIFT 8
652/* phy version */
653#define PV_PV_MASK 0x000f
654#define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
655
656/*== phy types (PhyVersion:PhyType field) ==*/
657#define PHY_TYPE_N 4 /* N-Phy value */
658#define PHY_TYPE_SSN 6 /* SSLPN-Phy value */
659#define PHY_TYPE_LCN 8 /* LCN-Phy value */
660#define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */
661#define PHY_TYPE_NULL 0xf /* Invalid Phy value */
662
663/*== analog types (PhyVersion:AnalogType field) ==*/
664#define ANA_11N_013 5
665
666/* 802.11a PLCP header def */
667struct ofdm_phy_hdr {
668 u8 rlpt[3]; /* rate, length, parity, tail */
669 u16 service;
670 u8 pad;
671} __packed;
672
673#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
674#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
675#define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
676#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
677#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
678
679/* rate encoded per 802.11a-1999 sec 17.3.4.1 */
680#define D11A_PHY_HDR_SRATE(phdr, rate) \
681 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
682/* set reserved field to zero */
683#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
684/* length is number of octets in PSDU */
685#define D11A_PHY_HDR_SLENGTH(phdr, length) \
686 (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \
687 (((length) & 0x0fff) << 5))
688/* set the tail to all zeros */
689#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
690
691#define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */
692#define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */
693
694#define D11A_PHY_TX_DELAY (2) /* 2.1 usec */
695
696#define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */
697#define D11A_PHY_PRE_TIME (16)
698#define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
699
700/* 802.11b PLCP header def */
701struct cck_phy_hdr {
702 u8 signal;
703 u8 service;
704 u16 length;
705 u16 crc;
706} __packed;
707
708#define D11B_PHY_HDR_LEN 6
709
710#define D11B_PHY_TX_DELAY (3) /* 3.4 usec */
711
712#define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3)
713#define D11B_PHY_LPRE_TIME (144)
714#define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
715
716#define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1)
717#define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1)
718#define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
719
720#define D11B_PLCP_SIGNAL_LOCKED (1 << 2)
721#define D11B_PLCP_SIGNAL_LE (1 << 7)
722
723#define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */
724#define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */
725#define MIMO_PLCP_AMPDU 0x08 /* ampdu */
726
727#define BRCMS_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8))
728#define BRCMS_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8))
729#define BRCMS_SET_MIMO_PLCP_LEN(plcp, len) \
730 do { \
731 plcp[1] = len & 0xff; \
732 plcp[2] = ((len >> 8) & 0xff); \
733 } while (0);
734
735#define BRCMS_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
736#define BRCMS_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
737#define BRCMS_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU)
738
739/*
740 * The dot11a PLCP header is 5 bytes. To simplify the software (so that we
741 * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header
742 * has padding added in the ucode.
743 */
744#define D11_PHY_HDR_LEN 6
745
746/* TX DMA buffer header */
747struct d11txh {
748 __le16 MacTxControlLow; /* 0x0 */
749 __le16 MacTxControlHigh; /* 0x1 */
750 __le16 MacFrameControl; /* 0x2 */
751 __le16 TxFesTimeNormal; /* 0x3 */
752 __le16 PhyTxControlWord; /* 0x4 */
753 __le16 PhyTxControlWord_1; /* 0x5 */
754 __le16 PhyTxControlWord_1_Fbr; /* 0x6 */
755 __le16 PhyTxControlWord_1_Rts; /* 0x7 */
756 __le16 PhyTxControlWord_1_FbrRts; /* 0x8 */
757 __le16 MainRates; /* 0x9 */
758 __le16 XtraFrameTypes; /* 0xa */
759 u8 IV[16]; /* 0x0b - 0x12 */
760 u8 TxFrameRA[6]; /* 0x13 - 0x15 */
761 __le16 TxFesTimeFallback; /* 0x16 */
762 u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
763 __le16 RTSDurFallback; /* 0x1a */
764 u8 FragPLCPFallback[6]; /* 0x1b - 1d */
765 __le16 FragDurFallback; /* 0x1e */
766 __le16 MModeLen; /* 0x1f */
767 __le16 MModeFbrLen; /* 0x20 */
768 __le16 TstampLow; /* 0x21 */
769 __le16 TstampHigh; /* 0x22 */
770 __le16 ABI_MimoAntSel; /* 0x23 */
771 __le16 PreloadSize; /* 0x24 */
772 __le16 AmpduSeqCtl; /* 0x25 */
773 __le16 TxFrameID; /* 0x26 */
774 __le16 TxStatus; /* 0x27 */
775 __le16 MaxNMpdus; /* 0x28 */
776 __le16 MaxABytes_MRT; /* 0x29 */
777 __le16 MaxABytes_FBR; /* 0x2a */
778 __le16 MinMBytes; /* 0x2b */
779 u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
780 struct ieee80211_rts rts_frame; /* 0x2f - 0x36 */
781 u16 PAD; /* 0x37 */
782} __packed;
783
784#define D11_TXH_LEN 112 /* bytes */
785
786/* Frame Types */
787#define FT_CCK 0
788#define FT_OFDM 1
789#define FT_HT 2
790#define FT_N 3
791
792/*
793 * Position of MPDU inside A-MPDU; indicated with bits 10:9
794 * of MacTxControlLow
795 */
796#define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */
797#define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
798#define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */
799#define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */
800#define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */
801
802/*== MacTxControlLow ==*/
803#define TXC_AMIC 0x8000
804#define TXC_SENDCTS 0x0800
805#define TXC_AMPDU_MASK 0x0600
806#define TXC_BW_40 0x0100
807#define TXC_FREQBAND_5G 0x0080
808#define TXC_DFCS 0x0040
809#define TXC_IGNOREPMQ 0x0020
810#define TXC_HWSEQ 0x0010
811#define TXC_STARTMSDU 0x0008
812#define TXC_SENDRTS 0x0004
813#define TXC_LONGFRAME 0x0002
814#define TXC_IMMEDACK 0x0001
815
816/*== MacTxControlHigh ==*/
817/* RTS fallback preamble type 1 = SHORT 0 = LONG */
818#define TXC_PREAMBLE_RTS_FB_SHORT 0x8000
819/* RTS main rate preamble type 1 = SHORT 0 = LONG */
820#define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000
821/*
822 * Main fallback rate preamble type
823 * 1 = SHORT for OFDM/GF for MIMO
824 * 0 = LONG for CCK/MM for MIMO
825 */
826#define TXC_PREAMBLE_DATA_FB_SHORT 0x2000
827
828/* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */
829/* use fallback rate for this AMPDU */
830#define TXC_AMPDU_FBR 0x1000
831#define TXC_SECKEY_MASK 0x0FF0
832#define TXC_SECKEY_SHIFT 4
833/* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
834#define TXC_ALT_TXPWR 0x0008
835#define TXC_SECTYPE_MASK 0x0007
836#define TXC_SECTYPE_SHIFT 0
837
838/* Null delimiter for Fallback rate */
839#define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */
840
841/* PhyTxControl for Mimophy */
842#define PHY_TXC_PWR_MASK 0xFC00
843#define PHY_TXC_PWR_SHIFT 10
844#define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */
845#define PHY_TXC_ANT_SHIFT 6
846#define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */
847#define PHY_TXC_LCNPHY_ANT_LAST 0x0000
848#define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */
849#define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */
850#define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */
851#define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */
852#define PHY_TXC_SHORT_HDR 0x0010
853
854#define PHY_TXC_OLD_ANT_0 0x0000
855#define PHY_TXC_OLD_ANT_1 0x0100
856#define PHY_TXC_OLD_ANT_LAST 0x0300
857
858/* PhyTxControl_1 for Mimophy */
859#define PHY_TXC1_BW_MASK 0x0007
860#define PHY_TXC1_BW_10MHZ 0
861#define PHY_TXC1_BW_10MHZ_UP 1
862#define PHY_TXC1_BW_20MHZ 2
863#define PHY_TXC1_BW_20MHZ_UP 3
864#define PHY_TXC1_BW_40MHZ 4
865#define PHY_TXC1_BW_40MHZ_DUP 5
866#define PHY_TXC1_MODE_SHIFT 3
867#define PHY_TXC1_MODE_MASK 0x0038
868#define PHY_TXC1_MODE_SISO 0
869#define PHY_TXC1_MODE_CDD 1
870#define PHY_TXC1_MODE_STBC 2
871#define PHY_TXC1_MODE_SDM 3
872
873/* PhyTxControl for HTphy that are different from Mimophy */
874#define PHY_TXC_HTANT_MASK 0x3fC0 /* bits 6-13 */
875
876/* XtraFrameTypes */
877#define XFTS_RTS_FT_SHIFT 2
878#define XFTS_FBRRTS_FT_SHIFT 4
879#define XFTS_CHANNEL_SHIFT 8
880
881/* Antenna diversity bit in ant_wr_settle */
882#define PHY_AWS_ANTDIV 0x2000
883
884/* IFS ctl */
885#define IFS_USEEDCF (1 << 2)
886
887/* IFS ctl1 */
888#define IFS_CTL1_EDCRS (1 << 3)
889#define IFS_CTL1_EDCRS_20L (1 << 4)
890#define IFS_CTL1_EDCRS_40 (1 << 5)
891
892/* ABI_MimoAntSel */
893#define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
894#define ABI_MAS_ADDR_BMP_IDX_SHIFT 8
895#define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
896#define ABI_MAS_FBR_ANT_PTN_SHIFT 4
897#define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
898
899/* tx status packet */
900struct tx_status {
901 u16 framelen;
902 u16 PAD;
903 u16 frameid;
904 u16 status;
905 u16 lasttxtime;
906 u16 sequence;
907 u16 phyerr;
908 u16 ackphyrxsh;
909} __packed;
910
911#define TXSTATUS_LEN 16
912
913/* status field bit definitions */
914#define TX_STATUS_FRM_RTX_MASK 0xF000
915#define TX_STATUS_FRM_RTX_SHIFT 12
916#define TX_STATUS_RTS_RTX_MASK 0x0F00
917#define TX_STATUS_RTS_RTX_SHIFT 8
918#define TX_STATUS_MASK 0x00FE
919#define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */
920#define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */
921#define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */
922#define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
923#define TX_STATUS_SUPR_SHIFT 2
924#define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */
925#define TX_STATUS_VALID (1 << 0) /* Tx status valid */
926#define TX_STATUS_NO_ACK 0
927
928/* suppress status reason codes */
929#define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */
930#define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */
931#define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */
932#define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe resp supr for TBTT */
933#define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */
934#define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */
935#define TX_STATUS_SUPR_UF (6 << 2) /* underflow */
936
937/* Unexpected tx status for rate update */
938#define TX_STATUS_UNEXP(status) \
939 ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \
940 TX_STATUS_UNEXP_AMPDU(status))
941
942/* Unexpected tx status for A-MPDU rate update */
943#define TX_STATUS_UNEXP_AMPDU(status) \
944 ((((status) & TX_STATUS_SUPR_MASK) != 0) && \
945 (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME))
946
947#define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */
948#define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */
949#define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */
950#define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */
951
952/* RXE (Receive Engine) */
953
954/* RCM_CTL */
955#define RCM_INC_MASK_H 0x0080
956#define RCM_INC_MASK_L 0x0040
957#define RCM_INC_DATA 0x0020
958#define RCM_INDEX_MASK 0x001F
959#define RCM_SIZE 15
960
961#define RCM_MAC_OFFSET 0 /* current MAC address */
962#define RCM_BSSID_OFFSET 3 /* current BSSID address */
963#define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */
964#define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */
965#define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */
966
967#define RCM_WEP_TA0_OFFSET 16
968#define RCM_WEP_TA1_OFFSET 19
969#define RCM_WEP_TA2_OFFSET 22
970#define RCM_WEP_TA3_OFFSET 25
971
972/* PSM Block */
973
974/* psm_phy_hdr_param bits */
975#define MAC_PHY_RESET 1
976#define MAC_PHY_CLOCK_EN 2
977#define MAC_PHY_FORCE_CLK 4
978
979/* WEP Block */
980
981/* WEP_WKEY */
982#define WKEY_START (1 << 8)
983#define WKEY_SEL_MASK 0x1F
984
985/* WEP data formats */
986
987/* the number of RCMTA entries */
988#define RCMTA_SIZE 50
989
990#define M_ADDR_BMP_BLK (0x37e * 2)
991#define M_ADDR_BMP_BLK_SZ 12
992
993#define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */
994#define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */
995#define ADDR_BMP_BSSID (1 << 2) /* BSSID */
996#define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point */
997#define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station */
998#define ADDR_BMP_RESERVED1 (1 << 5)
999#define ADDR_BMP_RESERVED2 (1 << 6)
1000#define ADDR_BMP_RESERVED3 (1 << 7)
1001#define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */
1002#define ADDR_BMP_BSS_IDX_SHIFT 8
1003
1004#define WSEC_MAX_RCMTA_KEYS 54
1005
1006/* max keys in M_TKMICKEYS_BLK */
1007#define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */
1008
1009/* max RXE match registers */
1010#define WSEC_MAX_RXE_KEYS 4
1011
1012/* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
1013/* SKL (Security Key Lookup) */
1014#define SKL_ALGO_MASK 0x0007
1015#define SKL_ALGO_SHIFT 0
1016#define SKL_KEYID_MASK 0x0008
1017#define SKL_KEYID_SHIFT 3
1018#define SKL_INDEX_MASK 0x03F0
1019#define SKL_INDEX_SHIFT 4
1020#define SKL_GRP_ALGO_MASK 0x1c00
1021#define SKL_GRP_ALGO_SHIFT 10
1022
1023/* additional bits defined for IBSS group key support */
1024#define SKL_IBSS_INDEX_MASK 0x01F0
1025#define SKL_IBSS_INDEX_SHIFT 4
1026#define SKL_IBSS_KEYID1_MASK 0x0600
1027#define SKL_IBSS_KEYID1_SHIFT 9
1028#define SKL_IBSS_KEYID2_MASK 0x1800
1029#define SKL_IBSS_KEYID2_SHIFT 11
1030#define SKL_IBSS_KEYALGO_MASK 0xE000
1031#define SKL_IBSS_KEYALGO_SHIFT 13
1032
1033#define WSEC_MODE_OFF 0
1034#define WSEC_MODE_HW 1
1035#define WSEC_MODE_SW 2
1036
1037#define WSEC_ALGO_OFF 0
1038#define WSEC_ALGO_WEP1 1
1039#define WSEC_ALGO_TKIP 2
1040#define WSEC_ALGO_AES 3
1041#define WSEC_ALGO_WEP128 4
1042#define WSEC_ALGO_AES_LEGACY 5
1043#define WSEC_ALGO_NALG 6
1044
1045#define AES_MODE_NONE 0
1046#define AES_MODE_CCM 1
1047
1048/* WEP_CTL (Rev 0) */
1049#define WECR0_KEYREG_SHIFT 0
1050#define WECR0_KEYREG_MASK 0x7
1051#define WECR0_DECRYPT (1 << 3)
1052#define WECR0_IVINLINE (1 << 4)
1053#define WECR0_WEPALG_SHIFT 5
1054#define WECR0_WEPALG_MASK (0x7 << 5)
1055#define WECR0_WKEYSEL_SHIFT 8
1056#define WECR0_WKEYSEL_MASK (0x7 << 8)
1057#define WECR0_WKEYSTART (1 << 11)
1058#define WECR0_WEPINIT (1 << 14)
1059#define WECR0_ICVERR (1 << 15)
1060
1061/* Frame template map byte offsets */
1062#define T_ACTS_TPL_BASE (0)
1063#define T_NULL_TPL_BASE (0xc * 2)
1064#define T_QNULL_TPL_BASE (0x1c * 2)
1065#define T_RR_TPL_BASE (0x2c * 2)
1066#define T_BCN0_TPL_BASE (0x34 * 2)
1067#define T_PRS_TPL_BASE (0x134 * 2)
1068#define T_BCN1_TPL_BASE (0x234 * 2)
1069#define T_TX_FIFO_TXRAM_BASE (T_ACTS_TPL_BASE + \
1070 (TXFIFO_START_BLK * TXFIFO_SIZE_UNIT))
1071
1072#define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */
1073
1074#define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */
1075
1076/* Shared Mem byte offsets */
1077
1078/* Location where the ucode expects the corerev */
1079#define M_MACHW_VER (0x00b * 2)
1080
1081/* Location where the ucode expects the MAC capabilities */
1082#define M_MACHW_CAP_L (0x060 * 2)
1083#define M_MACHW_CAP_H (0x061 * 2)
1084
1085/* WME shared memory */
1086#define M_EDCF_STATUS_OFF (0x007 * 2)
1087#define M_TXF_CUR_INDEX (0x018 * 2)
1088#define M_EDCF_QINFO (0x120 * 2)
1089
1090/* PS-mode related parameters */
1091#define M_DOT11_SLOT (0x008 * 2)
1092#define M_DOT11_DTIMPERIOD (0x009 * 2)
1093#define M_NOSLPZNATDTIM (0x026 * 2)
1094
1095/* Beacon-related parameters */
1096#define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */
1097#define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */
1098#define M_BCN_TXTSF_OFFSET (0x00e * 2)
1099#define M_TIMBPOS_INBEACON (0x00f * 2)
1100#define M_SFRMTXCNTFBRTHSD (0x022 * 2)
1101#define M_LFRMTXCNTFBRTHSD (0x023 * 2)
1102#define M_BCN_PCTLWD (0x02a * 2)
1103#define M_BCN_LI (0x05b * 2) /* beacon listen interval */
1104
1105/* MAX Rx Frame len */
1106#define M_MAXRXFRM_LEN (0x010 * 2)
1107
1108/* ACK/CTS related params */
1109#define M_RSP_PCTLWD (0x011 * 2)
1110
1111/* Hardware Power Control */
1112#define M_TXPWR_N (0x012 * 2)
1113#define M_TXPWR_TARGET (0x013 * 2)
1114#define M_TXPWR_MAX (0x014 * 2)
1115#define M_TXPWR_CUR (0x019 * 2)
1116
1117/* Rx-related parameters */
1118#define M_RX_PAD_DATA_OFFSET (0x01a * 2)
1119
1120/* WEP Shared mem data */
1121#define M_SEC_DEFIVLOC (0x01e * 2)
1122#define M_SEC_VALNUMSOFTMCHTA (0x01f * 2)
1123#define M_PHYVER (0x028 * 2)
1124#define M_PHYTYPE (0x029 * 2)
1125#define M_SECRXKEYS_PTR (0x02b * 2)
1126#define M_TKMICKEYS_PTR (0x059 * 2)
1127#define M_SECKINDXALGO_BLK (0x2ea * 2)
1128#define M_SECKINDXALGO_BLK_SZ 54
1129#define M_SECPSMRXTAMCH_BLK (0x2fa * 2)
1130#define M_TKIP_TSC_TTAK (0x18c * 2)
1131#define D11_MAX_KEY_SIZE 16
1132
1133#define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */
1134
1135/* Probe response related parameters */
1136#define M_SSIDLEN (0x024 * 2)
1137#define M_PRB_RESP_FRM_LEN (0x025 * 2)
1138#define M_PRS_MAXTIME (0x03a * 2)
1139#define M_SSID (0xb0 * 2)
1140#define M_CTXPRS_BLK (0xc0 * 2)
1141#define C_CTX_PCTLWD_POS (0x4 * 2)
1142
1143/* Delta between OFDM and CCK power in CCK power boost mode */
1144#define M_OFDM_OFFSET (0x027 * 2)
1145
1146/* TSSI for last 4 11b/g CCK packets transmitted */
1147#define M_B_TSSI_0 (0x02c * 2)
1148#define M_B_TSSI_1 (0x02d * 2)
1149
1150/* Host flags to turn on ucode options */
1151#define M_HOST_FLAGS1 (0x02f * 2)
1152#define M_HOST_FLAGS2 (0x030 * 2)
1153#define M_HOST_FLAGS3 (0x031 * 2)
1154#define M_HOST_FLAGS4 (0x03c * 2)
1155#define M_HOST_FLAGS5 (0x06a * 2)
1156#define M_HOST_FLAGS_SZ 16
1157
1158#define M_RADAR_REG (0x033 * 2)
1159
1160/* TSSI for last 4 11a OFDM packets transmitted */
1161#define M_A_TSSI_0 (0x034 * 2)
1162#define M_A_TSSI_1 (0x035 * 2)
1163
1164/* noise interference measurement */
1165#define M_NOISE_IF_COUNT (0x034 * 2)
1166#define M_NOISE_IF_TIMEOUT (0x035 * 2)
1167
1168#define M_RF_RX_SP_REG1 (0x036 * 2)
1169
1170/* TSSI for last 4 11g OFDM packets transmitted */
1171#define M_G_TSSI_0 (0x038 * 2)
1172#define M_G_TSSI_1 (0x039 * 2)
1173
1174/* Background noise measure */
1175#define M_JSSI_0 (0x44 * 2)
1176#define M_JSSI_1 (0x45 * 2)
1177#define M_JSSI_AUX (0x46 * 2)
1178
1179#define M_CUR_2050_RADIOCODE (0x47 * 2)
1180
1181/* TX fifo sizes */
1182#define M_FIFOSIZE0 (0x4c * 2)
1183#define M_FIFOSIZE1 (0x4d * 2)
1184#define M_FIFOSIZE2 (0x4e * 2)
1185#define M_FIFOSIZE3 (0x4f * 2)
1186#define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */
1187
1188/* Current channel number plus upper bits */
1189#define M_CURCHANNEL (0x50 * 2)
1190#define D11_CURCHANNEL_5G 0x0100;
1191#define D11_CURCHANNEL_40 0x0200;
1192#define D11_CURCHANNEL_MAX 0x00FF;
1193
1194/* last posted frameid on the bcmc fifo */
1195#define M_BCMC_FID (0x54 * 2)
1196#define INVALIDFID 0xffff
1197
1198/* extended beacon phyctl bytes for 11N */
1199#define M_BCN_PCTL1WD (0x058 * 2)
1200
1201/* idle busy ratio to duty_cycle requirement */
1202#define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2)
1203#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
1204
1205/* CW RSSI for LCNPHY */
1206#define M_LCN_RSSI_0 0x1332
1207#define M_LCN_RSSI_1 0x1338
1208#define M_LCN_RSSI_2 0x133e
1209#define M_LCN_RSSI_3 0x1344
1210
1211/* SNR for LCNPHY */
1212#define M_LCN_SNR_A_0 0x1334
1213#define M_LCN_SNR_B_0 0x1336
1214
1215#define M_LCN_SNR_A_1 0x133a
1216#define M_LCN_SNR_B_1 0x133c
1217
1218#define M_LCN_SNR_A_2 0x1340
1219#define M_LCN_SNR_B_2 0x1342
1220
1221#define M_LCN_SNR_A_3 0x1346
1222#define M_LCN_SNR_B_3 0x1348
1223
1224#define M_LCN_LAST_RESET (81*2)
1225#define M_LCN_LAST_LOC (63*2)
1226#define M_LCNPHY_RESET_STATUS (4902)
1227#define M_LCNPHY_DSC_TIME (0x98d*2)
1228#define M_LCNPHY_RESET_CNT_DSC (0x98b*2)
1229#define M_LCNPHY_RESET_CNT (0x98c*2)
1230
1231/* Rate table offsets */
1232#define M_RT_DIRMAP_A (0xe0 * 2)
1233#define M_RT_BBRSMAP_A (0xf0 * 2)
1234#define M_RT_DIRMAP_B (0x100 * 2)
1235#define M_RT_BBRSMAP_B (0x110 * 2)
1236
1237/* Rate table entry offsets */
1238#define M_RT_PRS_PLCP_POS 10
1239#define M_RT_PRS_DUR_POS 16
1240#define M_RT_OFDM_PCTL1_POS 18
1241
1242#define M_20IN40_IQ (0x380 * 2)
1243
1244/* SHM locations where ucode stores the current power index */
1245#define M_CURR_IDX1 (0x384 * 2)
1246#define M_CURR_IDX2 (0x387 * 2)
1247
1248#define M_BSCALE_ANT0 (0x5e * 2)
1249#define M_BSCALE_ANT1 (0x5f * 2)
1250
1251/* Antenna Diversity Testing */
1252#define M_MIMO_ANTSEL_RXDFLT (0x63 * 2)
1253#define M_ANTSEL_CLKDIV (0x61 * 2)
1254#define M_MIMO_ANTSEL_TXDFLT (0x64 * 2)
1255
1256#define M_MIMO_MAXSYM (0x5d * 2)
1257#define MIMO_MAXSYM_DEF 0x8000 /* 32k */
1258#define MIMO_MAXSYM_MAX 0xffff /* 64k */
1259
1260#define M_WATCHDOG_8TU (0x1e * 2)
1261#define WATCHDOG_8TU_DEF 5
1262#define WATCHDOG_8TU_MAX 10
1263
1264/* Manufacturing Test Variables */
1265/* PER test mode */
1266#define M_PKTENG_CTRL (0x6c * 2)
1267/* IFS for TX mode */
1268#define M_PKTENG_IFS (0x6d * 2)
1269/* Lower word of tx frmcnt/rx lostcnt */
1270#define M_PKTENG_FRMCNT_LO (0x6e * 2)
1271/* Upper word of tx frmcnt/rx lostcnt */
1272#define M_PKTENG_FRMCNT_HI (0x6f * 2)
1273
1274/* Index variation in vbat ripple */
1275#define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1276#define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1277
1278/* M_PKTENG_CTRL bit definitions */
1279#define M_PKTENG_MODE_TX 0x0001
1280#define M_PKTENG_MODE_TX_RIFS 0x0004
1281#define M_PKTENG_MODE_TX_CTS 0x0008
1282#define M_PKTENG_MODE_RX 0x0002
1283#define M_PKTENG_MODE_RX_WITH_ACK 0x0402
1284#define M_PKTENG_MODE_MASK 0x0003
1285/* TX frames indicated in the frmcnt reg */
1286#define M_PKTENG_FRMCNT_VLD 0x0100
1287
1288/* Sample Collect parameters (bitmap and type) */
1289/* Trigger bitmap for sample collect */
1290#define M_SMPL_COL_BMP (0x37d * 2)
1291/* Sample collect type */
1292#define M_SMPL_COL_CTL (0x3b2 * 2)
1293
1294#define ANTSEL_CLKDIV_4MHZ 6
1295#define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */
1296#define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */
1297#define MIMO_ANTSEL_WAIT 50 /* 50us wait */
1298#define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */
1299
1300struct shm_acparams {
1301 u16 txop;
1302 u16 cwmin;
1303 u16 cwmax;
1304 u16 cwcur;
1305 u16 aifs;
1306 u16 bslots;
1307 u16 reggap;
1308 u16 status;
1309 u16 rsvd[8];
1310} __packed;
1311#define M_EDCF_QLEN (16 * 2)
1312
1313#define WME_STATUS_NEWAC (1 << 8)
1314
1315/* M_HOST_FLAGS */
1316#define MHFMAX 5 /* Number of valid hostflag half-word (u16) */
1317#define MHF1 0 /* Hostflag 1 index */
1318#define MHF2 1 /* Hostflag 2 index */
1319#define MHF3 2 /* Hostflag 3 index */
1320#define MHF4 3 /* Hostflag 4 index */
1321#define MHF5 4 /* Hostflag 5 index */
1322
1323/* Flags in M_HOST_FLAGS */
1324/* Enable ucode antenna diversity help */
1325#define MHF1_ANTDIV 0x0001
1326/* Enable EDCF access control */
1327#define MHF1_EDCF 0x0100
1328#define MHF1_IQSWAP_WAR 0x0200
1329/* Disable Slow clock request, for corerev < 11 */
1330#define MHF1_FORCEFASTCLK 0x0400
1331
1332/* Flags in M_HOST_FLAGS2 */
1333
1334/* Flush BCMC FIFO immediately */
1335#define MHF2_TXBCMC_NOW 0x0040
1336/* Enable ucode/hw power control */
1337#define MHF2_HWPWRCTL 0x0080
1338#define MHF2_NPHY40MHZ_WAR 0x0800
1339
1340/* Flags in M_HOST_FLAGS3 */
1341/* enabled mimo antenna selection */
1342#define MHF3_ANTSEL_EN 0x0001
1343/* antenna selection mode: 0: 2x3, 1: 2x4 */
1344#define MHF3_ANTSEL_MODE 0x0002
1345#define MHF3_RESERVED1 0x0004
1346#define MHF3_RESERVED2 0x0008
1347#define MHF3_NPHY_MLADV_WAR 0x0010
1348
1349/* Flags in M_HOST_FLAGS4 */
1350/* force bphy Tx on core 0 (board level WAR) */
1351#define MHF4_BPHY_TXCORE0 0x0080
1352/* for 4313A0 FEM boards */
1353#define MHF4_EXTPA_ENABLE 0x4000
1354
1355/* Flags in M_HOST_FLAGS5 */
1356#define MHF5_4313_GPIOCTRL 0x0001
1357#define MHF5_RESERVED1 0x0002
1358#define MHF5_RESERVED2 0x0004
1359/* Radio power setting for ucode */
1360#define M_RADIO_PWR (0x32 * 2)
1361
1362/* phy noise recorded by ucode right after tx */
1363#define M_PHY_NOISE (0x037 * 2)
1364#define PHY_NOISE_MASK 0x00ff
1365
1366/*
1367 * Receive Frame Data Header for 802.11b DCF-only frames
1368 *
1369 * RxFrameSize: Actual byte length of the frame data received
1370 * PAD: padding (not used)
1371 * PhyRxStatus_0: PhyRxStatus 15:0
1372 * PhyRxStatus_1: PhyRxStatus 31:16
1373 * PhyRxStatus_2: PhyRxStatus 47:32
1374 * PhyRxStatus_3: PhyRxStatus 63:48
1375 * PhyRxStatus_4: PhyRxStatus 79:64
1376 * PhyRxStatus_5: PhyRxStatus 95:80
1377 * RxStatus1: MAC Rx Status
1378 * RxStatus2: extended MAC Rx status
1379 * RxTSFTime: RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY
1380 * RxChan: gain code, channel radio code, and phy type
1381 */
1382struct d11rxhdr_le {
1383 __le16 RxFrameSize;
1384 u16 PAD;
1385 __le16 PhyRxStatus_0;
1386 __le16 PhyRxStatus_1;
1387 __le16 PhyRxStatus_2;
1388 __le16 PhyRxStatus_3;
1389 __le16 PhyRxStatus_4;
1390 __le16 PhyRxStatus_5;
1391 __le16 RxStatus1;
1392 __le16 RxStatus2;
1393 __le16 RxTSFTime;
1394 __le16 RxChan;
1395} __packed;
1396
1397struct d11rxhdr {
1398 u16 RxFrameSize;
1399 u16 PAD;
1400 u16 PhyRxStatus_0;
1401 u16 PhyRxStatus_1;
1402 u16 PhyRxStatus_2;
1403 u16 PhyRxStatus_3;
1404 u16 PhyRxStatus_4;
1405 u16 PhyRxStatus_5;
1406 u16 RxStatus1;
1407 u16 RxStatus2;
1408 u16 RxTSFTime;
1409 u16 RxChan;
1410} __packed;
1411
1412/* PhyRxStatus_0: */
1413/* NPHY only: CCK, OFDM, preN, N */
1414#define PRXS0_FT_MASK 0x0003
1415/* NPHY only: clip count adjustment steps by AGC */
1416#define PRXS0_CLIP_MASK 0x000C
1417#define PRXS0_CLIP_SHIFT 2
1418/* PHY received a frame with unsupported rate */
1419#define PRXS0_UNSRATE 0x0010
1420/* GPHY: rx ant, NPHY: upper sideband */
1421#define PRXS0_RXANT_UPSUBBAND 0x0020
1422/* CCK frame only: lost crs during cck frame reception */
1423#define PRXS0_LCRS 0x0040
1424/* Short Preamble */
1425#define PRXS0_SHORTH 0x0080
1426/* PLCP violation */
1427#define PRXS0_PLCPFV 0x0100
1428/* PLCP header integrity check failed */
1429#define PRXS0_PLCPHCF 0x0200
1430/* legacy PHY gain control */
1431#define PRXS0_GAIN_CTL 0x4000
1432/* NPHY: Antennas used for received frame, bitmask */
1433#define PRXS0_ANTSEL_MASK 0xF000
1434#define PRXS0_ANTSEL_SHIFT 0x12
1435
1436/* subfield PRXS0_FT_MASK */
1437#define PRXS0_CCK 0x0000
1438/* valid only for G phy, use rxh->RxChan for A phy */
1439#define PRXS0_OFDM 0x0001
1440#define PRXS0_PREN 0x0002
1441#define PRXS0_STDN 0x0003
1442
1443/* subfield PRXS0_ANTSEL_MASK */
1444#define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */
1445#define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */
1446#define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */
1447#define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */
1448
1449/* PhyRxStatus_1: */
1450#define PRXS1_JSSI_MASK 0x00FF
1451#define PRXS1_JSSI_SHIFT 0
1452#define PRXS1_SQ_MASK 0xFF00
1453#define PRXS1_SQ_SHIFT 8
1454
1455/* nphy PhyRxStatus_1: */
1456#define PRXS1_nphy_PWR0_MASK 0x00FF
1457#define PRXS1_nphy_PWR1_MASK 0xFF00
1458
1459/* HTPHY Rx Status defines */
1460/* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */
1461#define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */
1462#define PRXS0_RSVD 0x0800 /* reserved; set to 0 */
1463#define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */
1464
1465/* htphy PhyRxStatus_1: */
1466/* core enables for {3..0}, 0=disabled, 1=enabled */
1467#define PRXS1_HTPHY_CORE_MASK 0x000F
1468/* antenna configation */
1469#define PRXS1_HTPHY_ANTCFG_MASK 0x00F0
1470/* Mixmode PLCP Length low byte mask */
1471#define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00
1472
1473/* htphy PhyRxStatus_2: */
1474/* Mixmode PLCP Length high byte maskw */
1475#define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F
1476/* Mixmode PLCP rate mask */
1477#define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0
1478/* Rx power on core 0 */
1479#define PRXS2_HTPHY_RXPWR_ANT0 0xFF00
1480
1481/* htphy PhyRxStatus_3: */
1482/* Rx power on core 1 */
1483#define PRXS3_HTPHY_RXPWR_ANT1 0x00FF
1484/* Rx power on core 2 */
1485#define PRXS3_HTPHY_RXPWR_ANT2 0xFF00
1486
1487/* htphy PhyRxStatus_4: */
1488/* Rx power on core 3 */
1489#define PRXS4_HTPHY_RXPWR_ANT3 0x00FF
1490/* Coarse frequency offset */
1491#define PRXS4_HTPHY_CFO 0xFF00
1492
1493/* htphy PhyRxStatus_5: */
1494/* Fine frequency offset */
1495#define PRXS5_HTPHY_FFO 0x00FF
1496/* Advance Retard */
1497#define PRXS5_HTPHY_AR 0xFF00
1498
1499#define HTPHY_MMPLCPLen(rxs) \
1500 ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
1501 (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))
1502/* Get Rx power on core 0 */
1503#define HTPHY_RXPWR_ANT0(rxs) \
1504 ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)
1505/* Get Rx power on core 1 */
1506#define HTPHY_RXPWR_ANT1(rxs) \
1507 (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)
1508/* Get Rx power on core 2 */
1509#define HTPHY_RXPWR_ANT2(rxs) \
1510 ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)
1511
1512/* ucode RxStatus1: */
1513#define RXS_BCNSENT 0x8000
1514#define RXS_SECKINDX_MASK 0x07e0
1515#define RXS_SECKINDX_SHIFT 5
1516#define RXS_DECERR (1 << 4)
1517#define RXS_DECATMPT (1 << 3)
1518/* PAD bytes to make IP data 4 bytes aligned */
1519#define RXS_PBPRES (1 << 2)
1520#define RXS_RESPFRAMETX (1 << 1)
1521#define RXS_FCSERR (1 << 0)
1522
1523/* ucode RxStatus2: */
1524#define RXS_AMSDU_MASK 1
1525#define RXS_AGGTYPE_MASK 0x6
1526#define RXS_AGGTYPE_SHIFT 1
1527#define RXS_PHYRXST_VALID (1 << 8)
1528#define RXS_RXANT_MASK 0x3
1529#define RXS_RXANT_SHIFT 12
1530
1531/* RxChan */
1532#define RXS_CHAN_40 0x1000
1533#define RXS_CHAN_5G 0x0800
1534#define RXS_CHAN_ID_MASK 0x07f8
1535#define RXS_CHAN_ID_SHIFT 3
1536#define RXS_CHAN_PHYTYPE_MASK 0x0007
1537#define RXS_CHAN_PHYTYPE_SHIFT 0
1538
1539/* Index of attenuations used during ucode power control. */
1540#define M_PWRIND_BLKS (0x184 * 2)
1541#define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0)
1542#define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2)
1543#define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4)
1544#define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6)
1545/* M_PWRIND_MAP(core) macro */
1546#define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1))
1547
1548/* PSM SHM variable offsets */
1549#define M_PSM_SOFT_REGS 0x0
1550#define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0)
1551#define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2)
1552#define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
1553#define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
1554
1555#define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */
1556#define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */
1557#define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */
1558#define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
1559#define M_PRETBTT (0x4b * 2)
1560
1561/* offset to the target txpwr */
1562#define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2))
1563#define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2))
1564#define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2))
1565#define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2))
1566
1567/* PKTENG Rx Stats Block */
1568#define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2))
1569
1570/* ucode debug status codes */
1571/* not valid really */
1572#define DBGST_INACTIVE 0
1573/* after zeroing SHM, before suspending at init */
1574#define DBGST_INIT 1
1575/* "normal" state */
1576#define DBGST_ACTIVE 2
1577/* suspended */
1578#define DBGST_SUSPENDED 3
1579/* asleep (PS mode) */
1580#define DBGST_ASLEEP 4
1581
1582/* Scratch Reg defs */
1583enum _ePsmScratchPadRegDefinitions {
1584 S_RSV0 = 0,
1585 S_RSV1,
1586 S_RSV2,
1587
1588 /* offset 0x03: scratch registers for Dot11-contants */
1589 S_DOT11_CWMIN, /* CW-minimum */
1590 S_DOT11_CWMAX, /* CW-maximum */
1591 S_DOT11_CWCUR, /* CW-current */
1592 S_DOT11_SRC_LMT, /* short retry count limit */
1593 S_DOT11_LRC_LMT, /* long retry count limit */
1594 S_DOT11_DTIMCOUNT, /* DTIM-count */
1595
1596 /* offset 0x09: Tx-side scratch registers */
1597 S_SEQ_NUM, /* hardware sequence number reg */
1598 S_SEQ_NUM_FRAG, /* seq num for frags (at the start of MSDU) */
1599 S_FRMRETX_CNT, /* frame retx count */
1600 S_SSRC, /* Station short retry count */
1601 S_SLRC, /* Station long retry count */
1602 S_EXP_RSP, /* Expected response frame */
1603 S_OLD_BREM, /* Remaining backoff ctr */
1604 S_OLD_CWWIN, /* saved-off CW-cur */
1605 S_TXECTL, /* TXE-Ctl word constructed in scr-pad */
1606 S_CTXTST, /* frm type-subtype as read from Tx-descr */
1607
1608 /* offset 0x13: Rx-side scratch registers */
1609 S_RXTST, /* Type and subtype in Rxframe */
1610
1611 /* Global state register */
1612 S_STREG, /* state storage actual bit maps below */
1613
1614 S_TXPWR_SUM, /* Tx power control: accumulator */
1615 S_TXPWR_ITER, /* Tx power control: iteration */
1616 S_RX_FRMTYPE, /* Rate and PHY type for frames */
1617 S_THIS_AGG, /* Size of this AGG (A-MSDU) */
1618
1619 S_KEYINDX,
1620 S_RXFRMLEN, /* Receive MPDU length in bytes */
1621
1622 /* offset 0x1B: Receive TSF time stored in SCR */
1623 S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx */
1624 S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx */
1625 S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx */
1626 S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx */
1627 S_RXSSN, /* Received start seq number for A-MPDU BA */
1628 S_RXQOSFLD, /* Rx-QoS field (if present) */
1629
1630 /* offset 0x21: Scratch pad regs used in microcode as temp storage */
1631 S_TMP0, /* stmp0 */
1632 S_TMP1, /* stmp1 */
1633 S_TMP2, /* stmp2 */
1634 S_TMP3, /* stmp3 */
1635 S_TMP4, /* stmp4 */
1636 S_TMP5, /* stmp5 */
1637 S_PRQPENALTY_CTR, /* Probe response queue penalty counter */
1638 S_ANTCNT, /* unsuccessful attempts on current ant. */
1639 S_SYMBOL, /* flag for possible symbol ctl frames */
1640 S_RXTP, /* rx frame type */
1641 S_STREG2, /* extra state storage */
1642 S_STREG3, /* even more extra state storage */
1643 S_STREG4, /* ... */
1644 S_STREG5, /* remember to initialize it to zero */
1645
1646 S_ADJPWR_IDX,
1647 S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table */
1648 S_REVID4, /* 0x33 */
1649 S_INDX, /* 0x34 */
1650 S_ADDR0, /* 0x35 */
1651 S_ADDR1, /* 0x36 */
1652 S_ADDR2, /* 0x37 */
1653 S_ADDR3, /* 0x38 */
1654 S_ADDR4, /* 0x39 */
1655 S_ADDR5, /* 0x3A */
1656 S_TMP6, /* 0x3B */
1657 S_KEYINDX_BU, /* Backup for Key index */
1658 S_MFGTEST_TMP0, /* Temp regs used for RX test calculations */
1659 S_RXESN, /* Received end sequence number for A-MPDU BA */
1660 S_STREG6, /* 0x3F */
1661};
1662
1663#define S_BEACON_INDX S_OLD_BREM
1664#define S_PRS_INDX S_OLD_CWWIN
1665#define S_PHYTYPE S_SSRC
1666#define S_PHYVER S_SLRC
1667
1668/* IHR SLOW_CTRL values */
1669#define SLOW_CTRL_PDE (1 << 0)
1670#define SLOW_CTRL_FD (1 << 8)
1671
1672/* ucode mac statistic counters in shared memory */
1673struct macstat {
1674 u16 txallfrm; /* 0x80 */
1675 u16 txrtsfrm; /* 0x82 */
1676 u16 txctsfrm; /* 0x84 */
1677 u16 txackfrm; /* 0x86 */
1678 u16 txdnlfrm; /* 0x88 */
1679 u16 txbcnfrm; /* 0x8a */
1680 u16 txfunfl[8]; /* 0x8c - 0x9b */
1681 u16 txtplunfl; /* 0x9c */
1682 u16 txphyerr; /* 0x9e */
1683 u16 pktengrxducast; /* 0xa0 */
1684 u16 pktengrxdmcast; /* 0xa2 */
1685 u16 rxfrmtoolong; /* 0xa4 */
1686 u16 rxfrmtooshrt; /* 0xa6 */
1687 u16 rxinvmachdr; /* 0xa8 */
1688 u16 rxbadfcs; /* 0xaa */
1689 u16 rxbadplcp; /* 0xac */
1690 u16 rxcrsglitch; /* 0xae */
1691 u16 rxstrt; /* 0xb0 */
1692 u16 rxdfrmucastmbss; /* 0xb2 */
1693 u16 rxmfrmucastmbss; /* 0xb4 */
1694 u16 rxcfrmucast; /* 0xb6 */
1695 u16 rxrtsucast; /* 0xb8 */
1696 u16 rxctsucast; /* 0xba */
1697 u16 rxackucast; /* 0xbc */
1698 u16 rxdfrmocast; /* 0xbe */
1699 u16 rxmfrmocast; /* 0xc0 */
1700 u16 rxcfrmocast; /* 0xc2 */
1701 u16 rxrtsocast; /* 0xc4 */
1702 u16 rxctsocast; /* 0xc6 */
1703 u16 rxdfrmmcast; /* 0xc8 */
1704 u16 rxmfrmmcast; /* 0xca */
1705 u16 rxcfrmmcast; /* 0xcc */
1706 u16 rxbeaconmbss; /* 0xce */
1707 u16 rxdfrmucastobss; /* 0xd0 */
1708 u16 rxbeaconobss; /* 0xd2 */
1709 u16 rxrsptmout; /* 0xd4 */
1710 u16 bcntxcancl; /* 0xd6 */
1711 u16 PAD;
1712 u16 rxf0ovfl; /* 0xda */
1713 u16 rxf1ovfl; /* 0xdc */
1714 u16 rxf2ovfl; /* 0xde */
1715 u16 txsfovfl; /* 0xe0 */
1716 u16 pmqovfl; /* 0xe2 */
1717 u16 rxcgprqfrm; /* 0xe4 */
1718 u16 rxcgprsqovfl; /* 0xe6 */
1719 u16 txcgprsfail; /* 0xe8 */
1720 u16 txcgprssuc; /* 0xea */
1721 u16 prs_timeout; /* 0xec */
1722 u16 rxnack;
1723 u16 frmscons;
1724 u16 txnack;
1725 u16 txglitch_nack;
1726 u16 txburst; /* 0xf6 # tx bursts */
1727 u16 bphy_rxcrsglitch; /* bphy rx crs glitch */
1728 u16 phywatchdog; /* 0xfa # of phy watchdog events */
1729 u16 PAD;
1730 u16 bphy_badplcp; /* bphy bad plcp */
1731};
1732
1733/* dot11 core-specific control flags */
1734#define SICF_PCLKE 0x0004 /* PHY clock enable */
1735#define SICF_PRST 0x0008 /* PHY reset */
1736#define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */
1737#define SICF_FREF 0x0020 /* PLL FreqRefSelect */
1738/* NOTE: the following bw bits only apply when the core is attached
1739 * to a NPHY
1740 */
1741#define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */
1742#define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
1743#define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
1744#define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
1745#define SICF_GMODE 0x2000 /* gmode enable */
1746
1747/* dot11 core-specific status flags */
1748#define SISF_2G_PHY 0x0001 /* 2.4G capable phy */
1749#define SISF_5G_PHY 0x0002 /* 5G capable phy */
1750#define SISF_FCLKA 0x0004 /* FastClkAvailable */
1751#define SISF_DB_PHY 0x0008 /* Dualband phy */
1752
1753/* === End of MAC reg, Beginning of PHY(b/a/g/n) reg === */
1754/* radio and LPPHY regs are separated */
1755
1756#define BPHY_REG_OFT_BASE 0x0
1757/* offsets for indirect access to bphy registers */
1758#define BPHY_BB_CONFIG 0x01
1759#define BPHY_ADCBIAS 0x02
1760#define BPHY_ANACORE 0x03
1761#define BPHY_PHYCRSTH 0x06
1762#define BPHY_TEST 0x0a
1763#define BPHY_PA_TX_TO 0x10
1764#define BPHY_SYNTH_DC_TO 0x11
1765#define BPHY_PA_TX_TIME_UP 0x12
1766#define BPHY_RX_FLTR_TIME_UP 0x13
1767#define BPHY_TX_POWER_OVERRIDE 0x14
1768#define BPHY_RF_OVERRIDE 0x15
1769#define BPHY_RF_TR_LOOKUP1 0x16
1770#define BPHY_RF_TR_LOOKUP2 0x17
1771#define BPHY_COEFFS 0x18
1772#define BPHY_PLL_OUT 0x19
1773#define BPHY_REFRESH_MAIN 0x1a
1774#define BPHY_REFRESH_TO0 0x1b
1775#define BPHY_REFRESH_TO1 0x1c
1776#define BPHY_RSSI_TRESH 0x20
1777#define BPHY_IQ_TRESH_HH 0x21
1778#define BPHY_IQ_TRESH_H 0x22
1779#define BPHY_IQ_TRESH_L 0x23
1780#define BPHY_IQ_TRESH_LL 0x24
1781#define BPHY_GAIN 0x25
1782#define BPHY_LNA_GAIN_RANGE 0x26
1783#define BPHY_JSSI 0x27
1784#define BPHY_TSSI_CTL 0x28
1785#define BPHY_TSSI 0x29
1786#define BPHY_TR_LOSS_CTL 0x2a
1787#define BPHY_LO_LEAKAGE 0x2b
1788#define BPHY_LO_RSSI_ACC 0x2c
1789#define BPHY_LO_IQMAG_ACC 0x2d
1790#define BPHY_TX_DC_OFF1 0x2e
1791#define BPHY_TX_DC_OFF2 0x2f
1792#define BPHY_PEAK_CNT_THRESH 0x30
1793#define BPHY_FREQ_OFFSET 0x31
1794#define BPHY_DIVERSITY_CTL 0x32
1795#define BPHY_PEAK_ENERGY_LO 0x33
1796#define BPHY_PEAK_ENERGY_HI 0x34
1797#define BPHY_SYNC_CTL 0x35
1798#define BPHY_TX_PWR_CTRL 0x36
1799#define BPHY_TX_EST_PWR 0x37
1800#define BPHY_STEP 0x38
1801#define BPHY_WARMUP 0x39
1802#define BPHY_LMS_CFF_READ 0x3a
1803#define BPHY_LMS_COEFF_I 0x3b
1804#define BPHY_LMS_COEFF_Q 0x3c
1805#define BPHY_SIG_POW 0x3d
1806#define BPHY_RFDC_CANCEL_CTL 0x3e
1807#define BPHY_HDR_TYPE 0x40
1808#define BPHY_SFD_TO 0x41
1809#define BPHY_SFD_CTL 0x42
1810#define BPHY_DEBUG 0x43
1811#define BPHY_RX_DELAY_COMP 0x44
1812#define BPHY_CRS_DROP_TO 0x45
1813#define BPHY_SHORT_SFD_NZEROS 0x46
1814#define BPHY_DSSS_COEFF1 0x48
1815#define BPHY_DSSS_COEFF2 0x49
1816#define BPHY_CCK_COEFF1 0x4a
1817#define BPHY_CCK_COEFF2 0x4b
1818#define BPHY_TR_CORR 0x4c
1819#define BPHY_ANGLE_SCALE 0x4d
1820#define BPHY_TX_PWR_BASE_IDX 0x4e
1821#define BPHY_OPTIONAL_MODES2 0x4f
1822#define BPHY_CCK_LMS_STEP 0x50
1823#define BPHY_BYPASS 0x51
1824#define BPHY_CCK_DELAY_LONG 0x52
1825#define BPHY_CCK_DELAY_SHORT 0x53
1826#define BPHY_PPROC_CHAN_DELAY 0x54
1827#define BPHY_DDFS_ENABLE 0x58
1828#define BPHY_PHASE_SCALE 0x59
1829#define BPHY_FREQ_CONTROL 0x5a
1830#define BPHY_LNA_GAIN_RANGE_10 0x5b
1831#define BPHY_LNA_GAIN_RANGE_32 0x5c
1832#define BPHY_OPTIONAL_MODES 0x5d
1833#define BPHY_RX_STATUS2 0x5e
1834#define BPHY_RX_STATUS3 0x5f
1835#define BPHY_DAC_CONTROL 0x60
1836#define BPHY_ANA11G_FILT_CTRL 0x62
1837#define BPHY_REFRESH_CTRL 0x64
1838#define BPHY_RF_OVERRIDE2 0x65
1839#define BPHY_SPUR_CANCEL_CTRL 0x66
1840#define BPHY_FINE_DIGIGAIN_CTRL 0x67
1841#define BPHY_RSSI_LUT 0x88
1842#define BPHY_RSSI_LUT_END 0xa7
1843#define BPHY_TSSI_LUT 0xa8
1844#define BPHY_TSSI_LUT_END 0xc7
1845#define BPHY_TSSI2PWR_LUT 0x380
1846#define BPHY_TSSI2PWR_LUT_END 0x39f
1847#define BPHY_LOCOMP_LUT 0x3a0
1848#define BPHY_LOCOMP_LUT_END 0x3bf
1849#define BPHY_TXGAIN_LUT 0x3c0
1850#define BPHY_TXGAIN_LUT_END 0x3ff
1851
1852/* Bits in BB_CONFIG: */
1853#define PHY_BBC_ANT_MASK 0x0180
1854#define PHY_BBC_ANT_SHIFT 7
1855#define BB_DARWIN 0x1000
1856#define BBCFG_RESETCCA 0x4000
1857#define BBCFG_RESETRX 0x8000
1858
1859/* Bits in phytest(0x0a): */
1860#define TST_DDFS 0x2000
1861#define TST_TXFILT1 0x0800
1862#define TST_UNSCRAM 0x0400
1863#define TST_CARR_SUPP 0x0200
1864#define TST_DC_COMP_LOOP 0x0100
1865#define TST_LOOPBACK 0x0080
1866#define TST_TXFILT0 0x0040
1867#define TST_TXTEST_ENABLE 0x0020
1868#define TST_TXTEST_RATE 0x0018
1869#define TST_TXTEST_PHASE 0x0007
1870
1871/* phytest txTestRate values */
1872#define TST_TXTEST_RATE_1MBPS 0
1873#define TST_TXTEST_RATE_2MBPS 1
1874#define TST_TXTEST_RATE_5_5MBPS 2
1875#define TST_TXTEST_RATE_11MBPS 3
1876#define TST_TXTEST_RATE_SHIFT 3
1877
1878#define SHM_BYT_CNT 0x2 /* IHR location */
1879#define MAX_BYT_CNT 0x600 /* Maximum frame len */
1880
1881struct d11cnt {
1882 u32 txfrag;
1883 u32 txmulti;
1884 u32 txfail;
1885 u32 txretry;
1886 u32 txretrie;
1887 u32 rxdup;
1888 u32 txrts;
1889 u32 txnocts;
1890 u32 txnoack;
1891 u32 rxfrag;
1892 u32 rxmulti;
1893 u32 rxcrc;
1894 u32 txfrmsnt;
1895 u32 rxundec;
1896};
1897
1898#endif /* _BRCM_D11_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/dma.c b/drivers/staging/brcm80211/brcmsmac/dma.c
deleted file mode 100644
index b56a30297c2..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/dma.c
+++ /dev/null
@@ -1,1425 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#include <linux/slab.h>
17#include <linux/skbuff.h>
18#include <linux/delay.h>
19#include <linux/pci.h>
20
21#include <brcmu_utils.h>
22#include <aiutils.h>
23#include "types.h"
24#include "dma.h"
25
26/*
27 * DMA hardware requires each descriptor ring to be 8kB aligned, and fit within
28 * a contiguous 8kB physical address.
29 */
30#define D64RINGALIGN_BITS 13
31#define D64MAXRINGSZ (1 << D64RINGALIGN_BITS)
32#define D64RINGALIGN (1 << D64RINGALIGN_BITS)
33
34#define D64MAXDD (D64MAXRINGSZ / sizeof(struct dma64desc))
35
36/* transmit channel control */
37#define D64_XC_XE 0x00000001 /* transmit enable */
38#define D64_XC_SE 0x00000002 /* transmit suspend request */
39#define D64_XC_LE 0x00000004 /* loopback enable */
40#define D64_XC_FL 0x00000010 /* flush request */
41#define D64_XC_PD 0x00000800 /* parity check disable */
42#define D64_XC_AE 0x00030000 /* address extension bits */
43#define D64_XC_AE_SHIFT 16
44
45/* transmit descriptor table pointer */
46#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
47
48/* transmit channel status */
49#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
50#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
51#define D64_XS0_XS_SHIFT 28
52#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
53#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
54#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
55#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
56#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
57
58#define D64_XS1_AD_MASK 0x00001fff /* active descriptor */
59#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
60#define D64_XS1_XE_SHIFT 28
61#define D64_XS1_XE_NOERR 0x00000000 /* no error */
62#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
63#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
64#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
65#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
66#define D64_XS1_XE_COREE 0x50000000 /* core error */
67
68/* receive channel control */
69/* receive enable */
70#define D64_RC_RE 0x00000001
71/* receive frame offset */
72#define D64_RC_RO_MASK 0x000000fe
73#define D64_RC_RO_SHIFT 1
74/* direct fifo receive (pio) mode */
75#define D64_RC_FM 0x00000100
76/* separate rx header descriptor enable */
77#define D64_RC_SH 0x00000200
78/* overflow continue */
79#define D64_RC_OC 0x00000400
80/* parity check disable */
81#define D64_RC_PD 0x00000800
82/* address extension bits */
83#define D64_RC_AE 0x00030000
84#define D64_RC_AE_SHIFT 16
85
86/* flags for dma controller */
87/* partity enable */
88#define DMA_CTRL_PEN (1 << 0)
89/* rx overflow continue */
90#define DMA_CTRL_ROC (1 << 1)
91/* allow rx scatter to multiple descriptors */
92#define DMA_CTRL_RXMULTI (1 << 2)
93/* Unframed Rx/Tx data */
94#define DMA_CTRL_UNFRAMED (1 << 3)
95
96/* receive descriptor table pointer */
97#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
98
99/* receive channel status */
100#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
101#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
102#define D64_RS0_RS_SHIFT 28
103#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
104#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
105#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
106#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
107#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
108
109#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
110#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
111#define D64_RS1_RE_SHIFT 28
112#define D64_RS1_RE_NOERR 0x00000000 /* no error */
113#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
114#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
115#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
116#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
117#define D64_RS1_RE_COREE 0x50000000 /* core error */
118
119/* fifoaddr */
120#define D64_FA_OFF_MASK 0xffff /* offset */
121#define D64_FA_SEL_MASK 0xf0000 /* select */
122#define D64_FA_SEL_SHIFT 16
123#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
124#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
125#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
126#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
127#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
128#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
129#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
130#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
131#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
132#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
133
134/* descriptor control flags 1 */
135#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */
136#define D64_CTRL1_EOT ((u32)1 << 28) /* end of descriptor table */
137#define D64_CTRL1_IOC ((u32)1 << 29) /* interrupt on completion */
138#define D64_CTRL1_EOF ((u32)1 << 30) /* end of frame */
139#define D64_CTRL1_SOF ((u32)1 << 31) /* start of frame */
140
141/* descriptor control flags 2 */
142/* buffer byte count. real data len must <= 16KB */
143#define D64_CTRL2_BC_MASK 0x00007fff
144/* address extension bits */
145#define D64_CTRL2_AE 0x00030000
146#define D64_CTRL2_AE_SHIFT 16
147/* parity bit */
148#define D64_CTRL2_PARITY 0x00040000
149
150/* control flags in the range [27:20] are core-specific and not defined here */
151#define D64_CTRL_CORE_MASK 0x0ff00000
152
153#define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */
154#define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */
155#define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1 */
156#define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */
157
158/*
159 * packet headroom necessary to accommodate the largest header
160 * in the system, (i.e TXOFF). By doing, we avoid the need to
161 * allocate an extra buffer for the header when bridging to WL.
162 * There is a compile time check in wlc.c which ensure that this
163 * value is at least as big as TXOFF. This value is used in
164 * dma_rxfill().
165 */
166
167#define BCMEXTRAHDROOM 172
168
169/* debug/trace */
170#ifdef BCMDBG
171#define DMA_ERROR(args) \
172 do { \
173 if (!(*di->msg_level & 1)) \
174 ; \
175 else \
176 printk args; \
177 } while (0)
178#define DMA_TRACE(args) \
179 do { \
180 if (!(*di->msg_level & 2)) \
181 ; \
182 else \
183 printk args; \
184 } while (0)
185#else
186#define DMA_ERROR(args)
187#define DMA_TRACE(args)
188#endif /* BCMDBG */
189
190#define DMA_NONE(args)
191
192#define MAXNAMEL 8 /* 8 char names */
193
194/* macros to convert between byte offsets and indexes */
195#define B2I(bytes, type) ((bytes) / sizeof(type))
196#define I2B(index, type) ((index) * sizeof(type))
197
198#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
199#define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
200
201#define PCI64ADDR_HIGH 0x80000000 /* address[63] */
202#define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
203
204/*
205 * DMA Descriptor
206 * Descriptors are only read by the hardware, never written back.
207 */
208struct dma64desc {
209 __le32 ctrl1; /* misc control bits & bufcount */
210 __le32 ctrl2; /* buffer count and address extension */
211 __le32 addrlow; /* memory address of the date buffer, bits 31:0 */
212 __le32 addrhigh; /* memory address of the date buffer, bits 63:32 */
213};
214
215/* dma engine software state */
216struct dma_info {
217 struct dma_pub dma; /* exported structure */
218 uint *msg_level; /* message level pointer */
219 char name[MAXNAMEL]; /* callers name for diag msgs */
220
221 struct pci_dev *pbus; /* bus handle */
222
223 bool dma64; /* this dma engine is operating in 64-bit mode */
224 bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
225
226 /* 64-bit dma tx engine registers */
227 struct dma64regs __iomem *d64txregs;
228 /* 64-bit dma rx engine registers */
229 struct dma64regs __iomem *d64rxregs;
230 /* pointer to dma64 tx descriptor ring */
231 struct dma64desc *txd64;
232 /* pointer to dma64 rx descriptor ring */
233 struct dma64desc *rxd64;
234
235 u16 dmadesc_align; /* alignment requirement for dma descriptors */
236
237 u16 ntxd; /* # tx descriptors tunable */
238 u16 txin; /* index of next descriptor to reclaim */
239 u16 txout; /* index of next descriptor to post */
240 /* pointer to parallel array of pointers to packets */
241 struct sk_buff **txp;
242 /* Aligned physical address of descriptor ring */
243 dma_addr_t txdpa;
244 /* Original physical address of descriptor ring */
245 dma_addr_t txdpaorig;
246 u16 txdalign; /* #bytes added to alloc'd mem to align txd */
247 u32 txdalloc; /* #bytes allocated for the ring */
248 u32 xmtptrbase; /* When using unaligned descriptors, the ptr register
249 * is not just an index, it needs all 13 bits to be
250 * an offset from the addr register.
251 */
252
253 u16 nrxd; /* # rx descriptors tunable */
254 u16 rxin; /* index of next descriptor to reclaim */
255 u16 rxout; /* index of next descriptor to post */
256 /* pointer to parallel array of pointers to packets */
257 struct sk_buff **rxp;
258 /* Aligned physical address of descriptor ring */
259 dma_addr_t rxdpa;
260 /* Original physical address of descriptor ring */
261 dma_addr_t rxdpaorig;
262 u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */
263 u32 rxdalloc; /* #bytes allocated for the ring */
264 u32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */
265
266 /* tunables */
267 unsigned int rxbufsize; /* rx buffer size in bytes, not including
268 * the extra headroom
269 */
270 uint rxextrahdrroom; /* extra rx headroom, reverseved to assist upper
271 * stack, e.g. some rx pkt buffers will be
272 * bridged to tx side without byte copying.
273 * The extra headroom needs to be large enough
274 * to fit txheader needs. Some dongle driver may
275 * not need it.
276 */
277 uint nrxpost; /* # rx buffers to keep posted */
278 unsigned int rxoffset; /* rxcontrol offset */
279 /* add to get dma address of descriptor ring, low 32 bits */
280 uint ddoffsetlow;
281 /* high 32 bits */
282 uint ddoffsethigh;
283 /* add to get dma address of data buffer, low 32 bits */
284 uint dataoffsetlow;
285 /* high 32 bits */
286 uint dataoffsethigh;
287 /* descriptor base need to be aligned or not */
288 bool aligndesc_4k;
289};
290
291/*
292 * default dma message level (if input msg_level
293 * pointer is null in dma_attach())
294 */
295static uint dma_msg_level;
296
297/* Check for odd number of 1's */
298static u32 parity32(__le32 data)
299{
300 /* no swap needed for counting 1's */
301 u32 par_data = *(u32 *)&data;
302
303 par_data ^= par_data >> 16;
304 par_data ^= par_data >> 8;
305 par_data ^= par_data >> 4;
306 par_data ^= par_data >> 2;
307 par_data ^= par_data >> 1;
308
309 return par_data & 1;
310}
311
312static bool dma64_dd_parity(struct dma64desc *dd)
313{
314 return parity32(dd->addrlow ^ dd->addrhigh ^ dd->ctrl1 ^ dd->ctrl2);
315}
316
317/* descriptor bumping functions */
318
319static uint xxd(uint x, uint n)
320{
321 return x & (n - 1); /* faster than %, but n must be power of 2 */
322}
323
324static uint txd(struct dma_info *di, uint x)
325{
326 return xxd(x, di->ntxd);
327}
328
329static uint rxd(struct dma_info *di, uint x)
330{
331 return xxd(x, di->nrxd);
332}
333
334static uint nexttxd(struct dma_info *di, uint i)
335{
336 return txd(di, i + 1);
337}
338
339static uint prevtxd(struct dma_info *di, uint i)
340{
341 return txd(di, i - 1);
342}
343
344static uint nextrxd(struct dma_info *di, uint i)
345{
346 return txd(di, i + 1);
347}
348
349static uint ntxdactive(struct dma_info *di, uint h, uint t)
350{
351 return txd(di, t-h);
352}
353
354static uint nrxdactive(struct dma_info *di, uint h, uint t)
355{
356 return rxd(di, t-h);
357}
358
359static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags)
360{
361 uint dmactrlflags = di->dma.dmactrlflags;
362
363 if (di == NULL) {
364 DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name));
365 return 0;
366 }
367
368 dmactrlflags &= ~mask;
369 dmactrlflags |= flags;
370
371 /* If trying to enable parity, check if parity is actually supported */
372 if (dmactrlflags & DMA_CTRL_PEN) {
373 u32 control;
374
375 control = R_REG(&di->d64txregs->control);
376 W_REG(&di->d64txregs->control,
377 control | D64_XC_PD);
378 if (R_REG(&di->d64txregs->control) & D64_XC_PD)
379 /* We *can* disable it so it is supported,
380 * restore control register
381 */
382 W_REG(&di->d64txregs->control,
383 control);
384 else
385 /* Not supported, don't allow it to be enabled */
386 dmactrlflags &= ~DMA_CTRL_PEN;
387 }
388
389 di->dma.dmactrlflags = dmactrlflags;
390
391 return dmactrlflags;
392}
393
394static bool _dma64_addrext(struct dma64regs __iomem *dma64regs)
395{
396 u32 w;
397 OR_REG(&dma64regs->control, D64_XC_AE);
398 w = R_REG(&dma64regs->control);
399 AND_REG(&dma64regs->control, ~D64_XC_AE);
400 return (w & D64_XC_AE) == D64_XC_AE;
401}
402
403/*
404 * return true if this dma engine supports DmaExtendedAddrChanges,
405 * otherwise false
406 */
407static bool _dma_isaddrext(struct dma_info *di)
408{
409 /* DMA64 supports full 32- or 64-bit operation. AE is always valid */
410
411 /* not all tx or rx channel are available */
412 if (di->d64txregs != NULL) {
413 if (!_dma64_addrext(di->d64txregs))
414 DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
415 "AE set\n", di->name));
416 return true;
417 } else if (di->d64rxregs != NULL) {
418 if (!_dma64_addrext(di->d64rxregs))
419 DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
420 "AE set\n", di->name));
421 return true;
422 }
423
424 return false;
425}
426
427static bool _dma_descriptor_align(struct dma_info *di)
428{
429 u32 addrl;
430
431 /* Check to see if the descriptors need to be aligned on 4K/8K or not */
432 if (di->d64txregs != NULL) {
433 W_REG(&di->d64txregs->addrlow, 0xff0);
434 addrl = R_REG(&di->d64txregs->addrlow);
435 if (addrl != 0)
436 return false;
437 } else if (di->d64rxregs != NULL) {
438 W_REG(&di->d64rxregs->addrlow, 0xff0);
439 addrl = R_REG(&di->d64rxregs->addrlow);
440 if (addrl != 0)
441 return false;
442 }
443 return true;
444}
445
446/*
447 * Descriptor table must start at the DMA hardware dictated alignment, so
448 * allocated memory must be large enough to support this requirement.
449 */
450static void *dma_alloc_consistent(struct pci_dev *pdev, uint size,
451 u16 align_bits, uint *alloced,
452 dma_addr_t *pap)
453{
454 if (align_bits) {
455 u16 align = (1 << align_bits);
456 if (!IS_ALIGNED(PAGE_SIZE, align))
457 size += align;
458 *alloced = size;
459 }
460 return pci_alloc_consistent(pdev, size, pap);
461}
462
463static
464u8 dma_align_sizetobits(uint size)
465{
466 u8 bitpos = 0;
467 while (size >>= 1)
468 bitpos++;
469 return bitpos;
470}
471
472/* This function ensures that the DMA descriptor ring will not get allocated
473 * across Page boundary. If the allocation is done across the page boundary
474 * at the first time, then it is freed and the allocation is done at
475 * descriptor ring size aligned location. This will ensure that the ring will
476 * not cross page boundary
477 */
478static void *dma_ringalloc(struct dma_info *di, u32 boundary, uint size,
479 u16 *alignbits, uint *alloced,
480 dma_addr_t *descpa)
481{
482 void *va;
483 u32 desc_strtaddr;
484 u32 alignbytes = 1 << *alignbits;
485
486 va = dma_alloc_consistent(di->pbus, size, *alignbits, alloced, descpa);
487
488 if (NULL == va)
489 return NULL;
490
491 desc_strtaddr = (u32) roundup((unsigned long)va, alignbytes);
492 if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr
493 & boundary)) {
494 *alignbits = dma_align_sizetobits(size);
495 pci_free_consistent(di->pbus, size, va, *descpa);
496 va = dma_alloc_consistent(di->pbus, size, *alignbits,
497 alloced, descpa);
498 }
499 return va;
500}
501
502static bool dma64_alloc(struct dma_info *di, uint direction)
503{
504 u16 size;
505 uint ddlen;
506 void *va;
507 uint alloced = 0;
508 u16 align;
509 u16 align_bits;
510
511 ddlen = sizeof(struct dma64desc);
512
513 size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
514 align_bits = di->dmadesc_align;
515 align = (1 << align_bits);
516
517 if (direction == DMA_TX) {
518 va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
519 &alloced, &di->txdpaorig);
520 if (va == NULL) {
521 DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd)"
522 " failed\n", di->name));
523 return false;
524 }
525 align = (1 << align_bits);
526 di->txd64 = (struct dma64desc *)
527 roundup((unsigned long)va, align);
528 di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
529 di->txdpa = di->txdpaorig + di->txdalign;
530 di->txdalloc = alloced;
531 } else {
532 va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
533 &alloced, &di->rxdpaorig);
534 if (va == NULL) {
535 DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd)"
536 " failed\n", di->name));
537 return false;
538 }
539 align = (1 << align_bits);
540 di->rxd64 = (struct dma64desc *)
541 roundup((unsigned long)va, align);
542 di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
543 di->rxdpa = di->rxdpaorig + di->rxdalign;
544 di->rxdalloc = alloced;
545 }
546
547 return true;
548}
549
550static bool _dma_alloc(struct dma_info *di, uint direction)
551{
552 return dma64_alloc(di, direction);
553}
554
555struct dma_pub *dma_attach(char *name, struct si_pub *sih,
556 void __iomem *dmaregstx, void __iomem *dmaregsrx,
557 uint ntxd, uint nrxd,
558 uint rxbufsize, int rxextheadroom,
559 uint nrxpost, uint rxoffset, uint *msg_level)
560{
561 struct dma_info *di;
562 uint size;
563
564 /* allocate private info structure */
565 di = kzalloc(sizeof(struct dma_info), GFP_ATOMIC);
566 if (di == NULL)
567 return NULL;
568
569 di->msg_level = msg_level ? msg_level : &dma_msg_level;
570
571
572 di->dma64 = ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
573
574 /* init dma reg pointer */
575 di->d64txregs = (struct dma64regs __iomem *) dmaregstx;
576 di->d64rxregs = (struct dma64regs __iomem *) dmaregsrx;
577
578 /*
579 * Default flags (which can be changed by the driver calling
580 * dma_ctrlflags before enable): For backwards compatibility
581 * both Rx Overflow Continue and Parity are DISABLED.
582 */
583 _dma_ctrlflags(di, DMA_CTRL_ROC | DMA_CTRL_PEN, 0);
584
585 DMA_TRACE(("%s: dma_attach: %s flags 0x%x ntxd %d nrxd %d "
586 "rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d "
587 "dmaregstx %p dmaregsrx %p\n", name, "DMA64",
588 di->dma.dmactrlflags, ntxd, nrxd, rxbufsize,
589 rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx));
590
591 /* make a private copy of our callers name */
592 strncpy(di->name, name, MAXNAMEL);
593 di->name[MAXNAMEL - 1] = '\0';
594
595 di->pbus = ((struct si_info *)sih)->pbus;
596
597 /* save tunables */
598 di->ntxd = (u16) ntxd;
599 di->nrxd = (u16) nrxd;
600
601 /* the actual dma size doesn't include the extra headroom */
602 di->rxextrahdrroom =
603 (rxextheadroom == -1) ? BCMEXTRAHDROOM : rxextheadroom;
604 if (rxbufsize > BCMEXTRAHDROOM)
605 di->rxbufsize = (u16) (rxbufsize - di->rxextrahdrroom);
606 else
607 di->rxbufsize = (u16) rxbufsize;
608
609 di->nrxpost = (u16) nrxpost;
610 di->rxoffset = (u8) rxoffset;
611
612 /*
613 * figure out the DMA physical address offset for dd and data
614 * PCI/PCIE: they map silicon backplace address to zero
615 * based memory, need offset
616 * Other bus: use zero SI_BUS BIGENDIAN kludge: use sdram
617 * swapped region for data buffer, not descriptor
618 */
619 di->ddoffsetlow = 0;
620 di->dataoffsetlow = 0;
621 /* add offset for pcie with DMA64 bus */
622 di->ddoffsetlow = 0;
623 di->ddoffsethigh = SI_PCIE_DMA_H32;
624 di->dataoffsetlow = di->ddoffsetlow;
625 di->dataoffsethigh = di->ddoffsethigh;
626 /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
627 if ((ai_coreid(sih) == SDIOD_CORE_ID)
628 && ((ai_corerev(sih) > 0) && (ai_corerev(sih) <= 2)))
629 di->addrext = 0;
630 else if ((ai_coreid(sih) == I2S_CORE_ID) &&
631 ((ai_corerev(sih) == 0) || (ai_corerev(sih) == 1)))
632 di->addrext = 0;
633 else
634 di->addrext = _dma_isaddrext(di);
635
636 /* does the descriptor need to be aligned and if yes, on 4K/8K or not */
637 di->aligndesc_4k = _dma_descriptor_align(di);
638 if (di->aligndesc_4k) {
639 di->dmadesc_align = D64RINGALIGN_BITS;
640 if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2))
641 /* for smaller dd table, HW relax alignment reqmnt */
642 di->dmadesc_align = D64RINGALIGN_BITS - 1;
643 } else {
644 di->dmadesc_align = 4; /* 16 byte alignment */
645 }
646
647 DMA_NONE(("DMA descriptor align_needed %d, align %d\n",
648 di->aligndesc_4k, di->dmadesc_align));
649
650 /* allocate tx packet pointer vector */
651 if (ntxd) {
652 size = ntxd * sizeof(void *);
653 di->txp = kzalloc(size, GFP_ATOMIC);
654 if (di->txp == NULL)
655 goto fail;
656 }
657
658 /* allocate rx packet pointer vector */
659 if (nrxd) {
660 size = nrxd * sizeof(void *);
661 di->rxp = kzalloc(size, GFP_ATOMIC);
662 if (di->rxp == NULL)
663 goto fail;
664 }
665
666 /*
667 * allocate transmit descriptor ring, only need ntxd descriptors
668 * but it must be aligned
669 */
670 if (ntxd) {
671 if (!_dma_alloc(di, DMA_TX))
672 goto fail;
673 }
674
675 /*
676 * allocate receive descriptor ring, only need nrxd descriptors
677 * but it must be aligned
678 */
679 if (nrxd) {
680 if (!_dma_alloc(di, DMA_RX))
681 goto fail;
682 }
683
684 if ((di->ddoffsetlow != 0) && !di->addrext) {
685 if (di->txdpa > SI_PCI_DMA_SZ) {
686 DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not "
687 "supported\n", di->name, (u32)di->txdpa));
688 goto fail;
689 }
690 if (di->rxdpa > SI_PCI_DMA_SZ) {
691 DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not "
692 "supported\n", di->name, (u32)di->rxdpa));
693 goto fail;
694 }
695 }
696
697 DMA_TRACE(("ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x "
698 "dataoffsethigh " "0x%x addrext %d\n", di->ddoffsetlow,
699 di->ddoffsethigh, di->dataoffsetlow, di->dataoffsethigh,
700 di->addrext));
701
702 return (struct dma_pub *) di;
703
704 fail:
705 dma_detach((struct dma_pub *)di);
706 return NULL;
707}
708
709static inline void
710dma64_dd_upd(struct dma_info *di, struct dma64desc *ddring,
711 dma_addr_t pa, uint outidx, u32 *flags, u32 bufcount)
712{
713 u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
714
715 /* PCI bus with big(>1G) physical address, use address extension */
716 if ((di->dataoffsetlow == 0) || !(pa & PCI32ADDR_HIGH)) {
717 ddring[outidx].addrlow = cpu_to_le32(pa + di->dataoffsetlow);
718 ddring[outidx].addrhigh = cpu_to_le32(di->dataoffsethigh);
719 ddring[outidx].ctrl1 = cpu_to_le32(*flags);
720 ddring[outidx].ctrl2 = cpu_to_le32(ctrl2);
721 } else {
722 /* address extension for 32-bit PCI */
723 u32 ae;
724
725 ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
726 pa &= ~PCI32ADDR_HIGH;
727
728 ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE;
729 ddring[outidx].addrlow = cpu_to_le32(pa + di->dataoffsetlow);
730 ddring[outidx].addrhigh = cpu_to_le32(di->dataoffsethigh);
731 ddring[outidx].ctrl1 = cpu_to_le32(*flags);
732 ddring[outidx].ctrl2 = cpu_to_le32(ctrl2);
733 }
734 if (di->dma.dmactrlflags & DMA_CTRL_PEN) {
735 if (dma64_dd_parity(&ddring[outidx]))
736 ddring[outidx].ctrl2 =
737 cpu_to_le32(ctrl2 | D64_CTRL2_PARITY);
738 }
739}
740
741/* !! may be called with core in reset */
742void dma_detach(struct dma_pub *pub)
743{
744 struct dma_info *di = (struct dma_info *)pub;
745
746 DMA_TRACE(("%s: dma_detach\n", di->name));
747
748 /* free dma descriptor rings */
749 if (di->txd64)
750 pci_free_consistent(di->pbus, di->txdalloc,
751 ((s8 *)di->txd64 - di->txdalign),
752 (di->txdpaorig));
753 if (di->rxd64)
754 pci_free_consistent(di->pbus, di->rxdalloc,
755 ((s8 *)di->rxd64 - di->rxdalign),
756 (di->rxdpaorig));
757
758 /* free packet pointer vectors */
759 kfree(di->txp);
760 kfree(di->rxp);
761
762 /* free our private info structure */
763 kfree(di);
764
765}
766
767/* initialize descriptor table base address */
768static void
769_dma_ddtable_init(struct dma_info *di, uint direction, dma_addr_t pa)
770{
771 if (!di->aligndesc_4k) {
772 if (direction == DMA_TX)
773 di->xmtptrbase = pa;
774 else
775 di->rcvptrbase = pa;
776 }
777
778 if ((di->ddoffsetlow == 0)
779 || !(pa & PCI32ADDR_HIGH)) {
780 if (direction == DMA_TX) {
781 W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
782 W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
783 } else {
784 W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
785 W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
786 }
787 } else {
788 /* DMA64 32bits address extension */
789 u32 ae;
790
791 /* shift the high bit(s) from pa to ae */
792 ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
793 pa &= ~PCI32ADDR_HIGH;
794
795 if (direction == DMA_TX) {
796 W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
797 W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
798 SET_REG(&di->d64txregs->control,
799 D64_XC_AE, (ae << D64_XC_AE_SHIFT));
800 } else {
801 W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
802 W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
803 SET_REG(&di->d64rxregs->control,
804 D64_RC_AE, (ae << D64_RC_AE_SHIFT));
805 }
806 }
807}
808
809static void _dma_rxenable(struct dma_info *di)
810{
811 uint dmactrlflags = di->dma.dmactrlflags;
812 u32 control;
813
814 DMA_TRACE(("%s: dma_rxenable\n", di->name));
815
816 control =
817 (R_REG(&di->d64rxregs->control) & D64_RC_AE) |
818 D64_RC_RE;
819
820 if ((dmactrlflags & DMA_CTRL_PEN) == 0)
821 control |= D64_RC_PD;
822
823 if (dmactrlflags & DMA_CTRL_ROC)
824 control |= D64_RC_OC;
825
826 W_REG(&di->d64rxregs->control,
827 ((di->rxoffset << D64_RC_RO_SHIFT) | control));
828}
829
830void dma_rxinit(struct dma_pub *pub)
831{
832 struct dma_info *di = (struct dma_info *)pub;
833
834 DMA_TRACE(("%s: dma_rxinit\n", di->name));
835
836 if (di->nrxd == 0)
837 return;
838
839 di->rxin = di->rxout = 0;
840
841 /* clear rx descriptor ring */
842 memset(di->rxd64, '\0', di->nrxd * sizeof(struct dma64desc));
843
844 /* DMA engine with out alignment requirement requires table to be inited
845 * before enabling the engine
846 */
847 if (!di->aligndesc_4k)
848 _dma_ddtable_init(di, DMA_RX, di->rxdpa);
849
850 _dma_rxenable(di);
851
852 if (di->aligndesc_4k)
853 _dma_ddtable_init(di, DMA_RX, di->rxdpa);
854}
855
856static struct sk_buff *dma64_getnextrxp(struct dma_info *di, bool forceall)
857{
858 uint i, curr;
859 struct sk_buff *rxp;
860 dma_addr_t pa;
861
862 i = di->rxin;
863
864 /* return if no packets posted */
865 if (i == di->rxout)
866 return NULL;
867
868 curr =
869 B2I(((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) -
870 di->rcvptrbase) & D64_RS0_CD_MASK, struct dma64desc);
871
872 /* ignore curr if forceall */
873 if (!forceall && (i == curr))
874 return NULL;
875
876 /* get the packet pointer that corresponds to the rx descriptor */
877 rxp = di->rxp[i];
878 di->rxp[i] = NULL;
879
880 pa = le32_to_cpu(di->rxd64[i].addrlow) - di->dataoffsetlow;
881
882 /* clear this packet from the descriptor ring */
883 pci_unmap_single(di->pbus, pa, di->rxbufsize, PCI_DMA_FROMDEVICE);
884
885 di->rxd64[i].addrlow = cpu_to_le32(0xdeadbeef);
886 di->rxd64[i].addrhigh = cpu_to_le32(0xdeadbeef);
887
888 di->rxin = nextrxd(di, i);
889
890 return rxp;
891}
892
893static struct sk_buff *_dma_getnextrxp(struct dma_info *di, bool forceall)
894{
895 if (di->nrxd == 0)
896 return NULL;
897
898 return dma64_getnextrxp(di, forceall);
899}
900
901/*
902 * !! rx entry routine
903 * returns a pointer to the next frame received, or NULL if there are no more
904 * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is
905 * supported with pkts chain
906 * otherwise, it's treated as giant pkt and will be tossed.
907 * The DMA scattering starts with normal DMA header, followed by first
908 * buffer data. After it reaches the max size of buffer, the data continues
909 * in next DMA descriptor buffer WITHOUT DMA header
910 */
911struct sk_buff *dma_rx(struct dma_pub *pub)
912{
913 struct dma_info *di = (struct dma_info *)pub;
914 struct sk_buff *p, *head, *tail;
915 uint len;
916 uint pkt_len;
917 int resid = 0;
918
919 next_frame:
920 head = _dma_getnextrxp(di, false);
921 if (head == NULL)
922 return NULL;
923
924 len = le16_to_cpu(*(__le16 *) (head->data));
925 DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
926 dma_spin_for_len(len, head);
927
928 /* set actual length */
929 pkt_len = min((di->rxoffset + len), di->rxbufsize);
930 __skb_trim(head, pkt_len);
931 resid = len - (di->rxbufsize - di->rxoffset);
932
933 /* check for single or multi-buffer rx */
934 if (resid > 0) {
935 tail = head;
936 while ((resid > 0) && (p = _dma_getnextrxp(di, false))) {
937 tail->next = p;
938 pkt_len = min_t(uint, resid, di->rxbufsize);
939 __skb_trim(p, pkt_len);
940
941 tail = p;
942 resid -= di->rxbufsize;
943 }
944
945#ifdef BCMDBG
946 if (resid > 0) {
947 uint cur;
948 cur =
949 B2I(((R_REG(&di->d64rxregs->status0) &
950 D64_RS0_CD_MASK) -
951 di->rcvptrbase) & D64_RS0_CD_MASK,
952 struct dma64desc);
953 DMA_ERROR(("dma_rx, rxin %d rxout %d, hw_curr %d\n",
954 di->rxin, di->rxout, cur));
955 }
956#endif /* BCMDBG */
957
958 if ((di->dma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) {
959 DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n",
960 di->name, len));
961 brcmu_pkt_buf_free_skb(head);
962 di->dma.rxgiants++;
963 goto next_frame;
964 }
965 }
966
967 return head;
968}
969
970static bool dma64_rxidle(struct dma_info *di)
971{
972 DMA_TRACE(("%s: dma_rxidle\n", di->name));
973
974 if (di->nrxd == 0)
975 return true;
976
977 return ((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
978 (R_REG(&di->d64rxregs->ptr) & D64_RS0_CD_MASK));
979}
980
981/*
982 * post receive buffers
983 * return false is refill failed completely and ring is empty this will stall
984 * the rx dma and user might want to call rxfill again asap. This unlikely
985 * happens on memory-rich NIC, but often on memory-constrained dongle
986 */
987bool dma_rxfill(struct dma_pub *pub)
988{
989 struct dma_info *di = (struct dma_info *)pub;
990 struct sk_buff *p;
991 u16 rxin, rxout;
992 u32 flags = 0;
993 uint n;
994 uint i;
995 dma_addr_t pa;
996 uint extra_offset = 0;
997 bool ring_empty;
998
999 ring_empty = false;
1000
1001 /*
1002 * Determine how many receive buffers we're lacking
1003 * from the full complement, allocate, initialize,
1004 * and post them, then update the chip rx lastdscr.
1005 */
1006
1007 rxin = di->rxin;
1008 rxout = di->rxout;
1009
1010 n = di->nrxpost - nrxdactive(di, rxin, rxout);
1011
1012 DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
1013
1014 if (di->rxbufsize > BCMEXTRAHDROOM)
1015 extra_offset = di->rxextrahdrroom;
1016
1017 for (i = 0; i < n; i++) {
1018 /*
1019 * the di->rxbufsize doesn't include the extra headroom,
1020 * we need to add it to the size to be allocated
1021 */
1022 p = brcmu_pkt_buf_get_skb(di->rxbufsize + extra_offset);
1023
1024 if (p == NULL) {
1025 DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n",
1026 di->name));
1027 if (i == 0 && dma64_rxidle(di)) {
1028 DMA_ERROR(("%s: rxfill64: ring is empty !\n",
1029 di->name));
1030 ring_empty = true;
1031 }
1032 di->dma.rxnobuf++;
1033 break;
1034 }
1035 /* reserve an extra headroom, if applicable */
1036 if (extra_offset)
1037 skb_pull(p, extra_offset);
1038
1039 /* Do a cached write instead of uncached write since DMA_MAP
1040 * will flush the cache.
1041 */
1042 *(u32 *) (p->data) = 0;
1043
1044 pa = pci_map_single(di->pbus, p->data,
1045 di->rxbufsize, PCI_DMA_FROMDEVICE);
1046
1047 /* save the free packet pointer */
1048 di->rxp[rxout] = p;
1049
1050 /* reset flags for each descriptor */
1051 flags = 0;
1052 if (rxout == (di->nrxd - 1))
1053 flags = D64_CTRL1_EOT;
1054
1055 dma64_dd_upd(di, di->rxd64, pa, rxout, &flags,
1056 di->rxbufsize);
1057 rxout = nextrxd(di, rxout);
1058 }
1059
1060 di->rxout = rxout;
1061
1062 /* update the chip lastdscr pointer */
1063 W_REG(&di->d64rxregs->ptr,
1064 di->rcvptrbase + I2B(rxout, struct dma64desc));
1065
1066 return ring_empty;
1067}
1068
1069void dma_rxreclaim(struct dma_pub *pub)
1070{
1071 struct dma_info *di = (struct dma_info *)pub;
1072 struct sk_buff *p;
1073
1074 DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
1075
1076 while ((p = _dma_getnextrxp(di, true)))
1077 brcmu_pkt_buf_free_skb(p);
1078}
1079
1080void dma_counterreset(struct dma_pub *pub)
1081{
1082 /* reset all software counters */
1083 pub->rxgiants = 0;
1084 pub->rxnobuf = 0;
1085 pub->txnobuf = 0;
1086}
1087
1088/* get the address of the var in order to change later */
1089unsigned long dma_getvar(struct dma_pub *pub, const char *name)
1090{
1091 struct dma_info *di = (struct dma_info *)pub;
1092
1093 if (!strcmp(name, "&txavail"))
1094 return (unsigned long)&(di->dma.txavail);
1095 return 0;
1096}
1097
1098/* 64-bit DMA functions */
1099
1100void dma_txinit(struct dma_pub *pub)
1101{
1102 struct dma_info *di = (struct dma_info *)pub;
1103 u32 control = D64_XC_XE;
1104
1105 DMA_TRACE(("%s: dma_txinit\n", di->name));
1106
1107 if (di->ntxd == 0)
1108 return;
1109
1110 di->txin = di->txout = 0;
1111 di->dma.txavail = di->ntxd - 1;
1112
1113 /* clear tx descriptor ring */
1114 memset(di->txd64, '\0', (di->ntxd * sizeof(struct dma64desc)));
1115
1116 /* DMA engine with out alignment requirement requires table to be inited
1117 * before enabling the engine
1118 */
1119 if (!di->aligndesc_4k)
1120 _dma_ddtable_init(di, DMA_TX, di->txdpa);
1121
1122 if ((di->dma.dmactrlflags & DMA_CTRL_PEN) == 0)
1123 control |= D64_XC_PD;
1124 OR_REG(&di->d64txregs->control, control);
1125
1126 /* DMA engine with alignment requirement requires table to be inited
1127 * before enabling the engine
1128 */
1129 if (di->aligndesc_4k)
1130 _dma_ddtable_init(di, DMA_TX, di->txdpa);
1131}
1132
1133void dma_txsuspend(struct dma_pub *pub)
1134{
1135 struct dma_info *di = (struct dma_info *)pub;
1136
1137 DMA_TRACE(("%s: dma_txsuspend\n", di->name));
1138
1139 if (di->ntxd == 0)
1140 return;
1141
1142 OR_REG(&di->d64txregs->control, D64_XC_SE);
1143}
1144
1145void dma_txresume(struct dma_pub *pub)
1146{
1147 struct dma_info *di = (struct dma_info *)pub;
1148
1149 DMA_TRACE(("%s: dma_txresume\n", di->name));
1150
1151 if (di->ntxd == 0)
1152 return;
1153
1154 AND_REG(&di->d64txregs->control, ~D64_XC_SE);
1155}
1156
1157bool dma_txsuspended(struct dma_pub *pub)
1158{
1159 struct dma_info *di = (struct dma_info *)pub;
1160
1161 return (di->ntxd == 0) ||
1162 ((R_REG(&di->d64txregs->control) & D64_XC_SE) ==
1163 D64_XC_SE);
1164}
1165
1166void dma_txreclaim(struct dma_pub *pub, enum txd_range range)
1167{
1168 struct dma_info *di = (struct dma_info *)pub;
1169 struct sk_buff *p;
1170
1171 DMA_TRACE(("%s: dma_txreclaim %s\n", di->name,
1172 (range == DMA_RANGE_ALL) ? "all" :
1173 ((range ==
1174 DMA_RANGE_TRANSMITTED) ? "transmitted" :
1175 "transferred")));
1176
1177 if (di->txin == di->txout)
1178 return;
1179
1180 while ((p = dma_getnexttxp(pub, range))) {
1181 /* For unframed data, we don't have any packets to free */
1182 if (!(di->dma.dmactrlflags & DMA_CTRL_UNFRAMED))
1183 brcmu_pkt_buf_free_skb(p);
1184 }
1185}
1186
1187bool dma_txreset(struct dma_pub *pub)
1188{
1189 struct dma_info *di = (struct dma_info *)pub;
1190 u32 status;
1191
1192 if (di->ntxd == 0)
1193 return true;
1194
1195 /* suspend tx DMA first */
1196 W_REG(&di->d64txregs->control, D64_XC_SE);
1197 SPINWAIT(((status =
1198 (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
1199 != D64_XS0_XS_DISABLED) && (status != D64_XS0_XS_IDLE)
1200 && (status != D64_XS0_XS_STOPPED), 10000);
1201
1202 W_REG(&di->d64txregs->control, 0);
1203 SPINWAIT(((status =
1204 (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
1205 != D64_XS0_XS_DISABLED), 10000);
1206
1207 /* wait for the last transaction to complete */
1208 udelay(300);
1209
1210 return status == D64_XS0_XS_DISABLED;
1211}
1212
1213bool dma_rxreset(struct dma_pub *pub)
1214{
1215 struct dma_info *di = (struct dma_info *)pub;
1216 u32 status;
1217
1218 if (di->nrxd == 0)
1219 return true;
1220
1221 W_REG(&di->d64rxregs->control, 0);
1222 SPINWAIT(((status =
1223 (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK))
1224 != D64_RS0_RS_DISABLED), 10000);
1225
1226 return status == D64_RS0_RS_DISABLED;
1227}
1228
1229/*
1230 * !! tx entry routine
1231 * WARNING: call must check the return value for error.
1232 * the error(toss frames) could be fatal and cause many subsequent hard
1233 * to debug problems
1234 */
1235int dma_txfast(struct dma_pub *pub, struct sk_buff *p0, bool commit)
1236{
1237 struct dma_info *di = (struct dma_info *)pub;
1238 struct sk_buff *p, *next;
1239 unsigned char *data;
1240 uint len;
1241 u16 txout;
1242 u32 flags = 0;
1243 dma_addr_t pa;
1244
1245 DMA_TRACE(("%s: dma_txfast\n", di->name));
1246
1247 txout = di->txout;
1248
1249 /*
1250 * Walk the chain of packet buffers
1251 * allocating and initializing transmit descriptor entries.
1252 */
1253 for (p = p0; p; p = next) {
1254 data = p->data;
1255 len = p->len;
1256 next = p->next;
1257
1258 /* return nonzero if out of tx descriptors */
1259 if (nexttxd(di, txout) == di->txin)
1260 goto outoftxd;
1261
1262 if (len == 0)
1263 continue;
1264
1265 /* get physical address of buffer start */
1266 pa = pci_map_single(di->pbus, data, len, PCI_DMA_TODEVICE);
1267
1268 flags = 0;
1269 if (p == p0)
1270 flags |= D64_CTRL1_SOF;
1271
1272 /* With a DMA segment list, Descriptor table is filled
1273 * using the segment list instead of looping over
1274 * buffers in multi-chain DMA. Therefore, EOF for SGLIST
1275 * is when end of segment list is reached.
1276 */
1277 if (next == NULL)
1278 flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
1279 if (txout == (di->ntxd - 1))
1280 flags |= D64_CTRL1_EOT;
1281
1282 dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
1283
1284 txout = nexttxd(di, txout);
1285 }
1286
1287 /* if last txd eof not set, fix it */
1288 if (!(flags & D64_CTRL1_EOF))
1289 di->txd64[prevtxd(di, txout)].ctrl1 =
1290 cpu_to_le32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF);
1291
1292 /* save the packet */
1293 di->txp[prevtxd(di, txout)] = p0;
1294
1295 /* bump the tx descriptor index */
1296 di->txout = txout;
1297
1298 /* kick the chip */
1299 if (commit)
1300 W_REG(&di->d64txregs->ptr,
1301 di->xmtptrbase + I2B(txout, struct dma64desc));
1302
1303 /* tx flow control */
1304 di->dma.txavail = di->ntxd - ntxdactive(di, di->txin, di->txout) - 1;
1305
1306 return 0;
1307
1308 outoftxd:
1309 DMA_ERROR(("%s: dma_txfast: out of txds !!!\n", di->name));
1310 brcmu_pkt_buf_free_skb(p0);
1311 di->dma.txavail = 0;
1312 di->dma.txnobuf++;
1313 return -1;
1314}
1315
1316/*
1317 * Reclaim next completed txd (txds if using chained buffers) in the range
1318 * specified and return associated packet.
1319 * If range is DMA_RANGE_TRANSMITTED, reclaim descriptors that have be
1320 * transmitted as noted by the hardware "CurrDescr" pointer.
1321 * If range is DMA_RANGE_TRANSFERED, reclaim descriptors that have be
1322 * transferred by the DMA as noted by the hardware "ActiveDescr" pointer.
1323 * If range is DMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
1324 * return associated packet regardless of the value of hardware pointers.
1325 */
1326struct sk_buff *dma_getnexttxp(struct dma_pub *pub, enum txd_range range)
1327{
1328 struct dma_info *di = (struct dma_info *)pub;
1329 u16 start, end, i;
1330 u16 active_desc;
1331 struct sk_buff *txp;
1332
1333 DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name,
1334 (range == DMA_RANGE_ALL) ? "all" :
1335 ((range ==
1336 DMA_RANGE_TRANSMITTED) ? "transmitted" :
1337 "transferred")));
1338
1339 if (di->ntxd == 0)
1340 return NULL;
1341
1342 txp = NULL;
1343
1344 start = di->txin;
1345 if (range == DMA_RANGE_ALL)
1346 end = di->txout;
1347 else {
1348 struct dma64regs __iomem *dregs = di->d64txregs;
1349
1350 end = (u16) (B2I(((R_REG(&dregs->status0) &
1351 D64_XS0_CD_MASK) -
1352 di->xmtptrbase) & D64_XS0_CD_MASK,
1353 struct dma64desc));
1354
1355 if (range == DMA_RANGE_TRANSFERED) {
1356 active_desc =
1357 (u16) (R_REG(&dregs->status1) &
1358 D64_XS1_AD_MASK);
1359 active_desc =
1360 (active_desc - di->xmtptrbase) & D64_XS0_CD_MASK;
1361 active_desc = B2I(active_desc, struct dma64desc);
1362 if (end != active_desc)
1363 end = prevtxd(di, active_desc);
1364 }
1365 }
1366
1367 if ((start == 0) && (end > di->txout))
1368 goto bogus;
1369
1370 for (i = start; i != end && !txp; i = nexttxd(di, i)) {
1371 dma_addr_t pa;
1372 uint size;
1373
1374 pa = le32_to_cpu(di->txd64[i].addrlow) - di->dataoffsetlow;
1375
1376 size =
1377 (le32_to_cpu(di->txd64[i].ctrl2) &
1378 D64_CTRL2_BC_MASK);
1379
1380 di->txd64[i].addrlow = cpu_to_le32(0xdeadbeef);
1381 di->txd64[i].addrhigh = cpu_to_le32(0xdeadbeef);
1382
1383 txp = di->txp[i];
1384 di->txp[i] = NULL;
1385
1386 pci_unmap_single(di->pbus, pa, size, PCI_DMA_TODEVICE);
1387 }
1388
1389 di->txin = i;
1390
1391 /* tx flow control */
1392 di->dma.txavail = di->ntxd - ntxdactive(di, di->txin, di->txout) - 1;
1393
1394 return txp;
1395
1396 bogus:
1397 DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d "
1398 "force %d\n", start, end, di->txout, forceall));
1399 return NULL;
1400}
1401
1402/*
1403 * Mac80211 initiated actions sometimes require packets in the DMA queue to be
1404 * modified. The modified portion of the packet is not under control of the DMA
1405 * engine. This function calls a caller-supplied function for each packet in
1406 * the caller specified dma chain.
1407 */
1408void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
1409 (void *pkt, void *arg_a), void *arg_a)
1410{
1411 struct dma_info *di = (struct dma_info *) dmah;
1412 uint i = di->txin;
1413 uint end = di->txout;
1414 struct sk_buff *skb;
1415 struct ieee80211_tx_info *tx_info;
1416
1417 while (i != end) {
1418 skb = (struct sk_buff *)di->txp[i];
1419 if (skb != NULL) {
1420 tx_info = (struct ieee80211_tx_info *)skb->cb;
1421 (callback_fnc)(tx_info, arg_a);
1422 }
1423 i = nexttxd(di, i);
1424 }
1425}
diff --git a/drivers/staging/brcm80211/brcmsmac/dma.h b/drivers/staging/brcm80211/brcmsmac/dma.h
deleted file mode 100644
index ebc5bc546f3..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/dma.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_DMA_H_
18#define _BRCM_DMA_H_
19
20#include <linux/delay.h>
21#include "types.h" /* forward structure declarations */
22
23/* map/unmap direction */
24#define DMA_TX 1 /* TX direction for DMA */
25#define DMA_RX 2 /* RX direction for DMA */
26
27/* DMA structure:
28 * support two DMA engines: 32 bits address or 64 bit addressing
29 * basic DMA register set is per channel(transmit or receive)
30 * a pair of channels is defined for convenience
31 */
32
33/* 32 bits addressing */
34
35struct dma32diag { /* diag access */
36 u32 fifoaddr; /* diag address */
37 u32 fifodatalow; /* low 32bits of data */
38 u32 fifodatahigh; /* high 32bits of data */
39 u32 pad; /* reserved */
40};
41
42/* 64 bits addressing */
43
44/* dma registers per channel(xmt or rcv) */
45struct dma64regs {
46 u32 control; /* enable, et al */
47 u32 ptr; /* last descriptor posted to chip */
48 u32 addrlow; /* desc ring base address low 32-bits (8K aligned) */
49 u32 addrhigh; /* desc ring base address bits 63:32 (8K aligned) */
50 u32 status0; /* current descriptor, xmt state */
51 u32 status1; /* active descriptor, xmt error */
52};
53
54/* range param for dma_getnexttxp() and dma_txreclaim */
55enum txd_range {
56 DMA_RANGE_ALL = 1,
57 DMA_RANGE_TRANSMITTED,
58 DMA_RANGE_TRANSFERED
59};
60
61/*
62 * Exported data structure (read-only)
63 */
64/* export structure */
65struct dma_pub {
66 uint txavail; /* # free tx descriptors */
67 uint dmactrlflags; /* dma control flags */
68
69 /* rx error counters */
70 uint rxgiants; /* rx giant frames */
71 uint rxnobuf; /* rx out of dma descriptors */
72 /* tx error counters */
73 uint txnobuf; /* tx out of dma descriptors */
74};
75
76extern struct dma_pub *dma_attach(char *name, struct si_pub *sih,
77 void __iomem *dmaregstx, void __iomem *dmaregsrx,
78 uint ntxd, uint nrxd,
79 uint rxbufsize, int rxextheadroom,
80 uint nrxpost, uint rxoffset, uint *msg_level);
81
82void dma_rxinit(struct dma_pub *pub);
83struct sk_buff *dma_rx(struct dma_pub *pub);
84bool dma_rxfill(struct dma_pub *pub);
85bool dma_rxreset(struct dma_pub *pub);
86bool dma_txreset(struct dma_pub *pub);
87void dma_txinit(struct dma_pub *pub);
88int dma_txfast(struct dma_pub *pub, struct sk_buff *p0, bool commit);
89void dma_txsuspend(struct dma_pub *pub);
90bool dma_txsuspended(struct dma_pub *pub);
91void dma_txresume(struct dma_pub *pub);
92void dma_txreclaim(struct dma_pub *pub, enum txd_range range);
93void dma_rxreclaim(struct dma_pub *pub);
94void dma_detach(struct dma_pub *pub);
95unsigned long dma_getvar(struct dma_pub *pub, const char *name);
96struct sk_buff *dma_getnexttxp(struct dma_pub *pub, enum txd_range range);
97void dma_counterreset(struct dma_pub *pub);
98
99void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
100 (void *pkt, void *arg_a), void *arg_a);
101
102/*
103 * DMA(Bug) on bcm47xx chips seems to declare that the packet is ready, but
104 * the packet length is not updated yet (by DMA) on the expected time.
105 * Workaround is to hold processor till DMA updates the length, and stay off
106 * the bus to allow DMA update the length in buffer
107 */
108static inline void dma_spin_for_len(uint len, struct sk_buff *head)
109{
110#if defined(CONFIG_BCM47XX)
111 if (!len) {
112 while (!(len = *(u16 *) KSEG1ADDR(head->data)))
113 udelay(1);
114
115 *(u16 *) (head->data) = cpu_to_le16((u16) len);
116 }
117#endif /* defined(CONFIG_BCM47XX) */
118}
119
120#endif /* _BRCM_DMA_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/mac80211_if.c b/drivers/staging/brcm80211/brcmsmac/mac80211_if.c
deleted file mode 100644
index 185a098dd13..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/mac80211_if.c
+++ /dev/null
@@ -1,1701 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define __UNDEF_NO_VERSION__
18
19#include <linux/etherdevice.h>
20#include <linux/pci.h>
21#include <linux/sched.h>
22#include <linux/firmware.h>
23#include <linux/interrupt.h>
24#include <net/mac80211.h>
25#include <defs.h>
26#include "nicpci.h"
27#include "phy/phy_int.h"
28#include "d11.h"
29#include "channel.h"
30#include "scb.h"
31#include "pub.h"
32#include "ucode_loader.h"
33#include "mac80211_if.h"
34#include "main.h"
35
36#define N_TX_QUEUES 4 /* #tx queues on mac80211<->driver interface */
37
38/* Flags we support */
39#define MAC_FILTERS (FIF_PROMISC_IN_BSS | \
40 FIF_ALLMULTI | \
41 FIF_FCSFAIL | \
42 FIF_PLCPFAIL | \
43 FIF_CONTROL | \
44 FIF_OTHER_BSS | \
45 FIF_BCN_PRBRESP_PROMISC)
46
47#define CHAN2GHZ(channel, freqency, chflags) { \
48 .band = IEEE80211_BAND_2GHZ, \
49 .center_freq = (freqency), \
50 .hw_value = (channel), \
51 .flags = chflags, \
52 .max_antenna_gain = 0, \
53 .max_power = 19, \
54}
55
56#define CHAN5GHZ(channel, chflags) { \
57 .band = IEEE80211_BAND_5GHZ, \
58 .center_freq = 5000 + 5*(channel), \
59 .hw_value = (channel), \
60 .flags = chflags, \
61 .max_antenna_gain = 0, \
62 .max_power = 21, \
63}
64
65#define RATE(rate100m, _flags) { \
66 .bitrate = (rate100m), \
67 .flags = (_flags), \
68 .hw_value = (rate100m / 5), \
69}
70
71struct firmware_hdr {
72 __le32 offset;
73 __le32 len;
74 __le32 idx;
75};
76
77static const char * const brcms_firmwares[MAX_FW_IMAGES] = {
78 "brcm/bcm43xx",
79 NULL
80};
81
82static int n_adapters_found;
83
84MODULE_AUTHOR("Broadcom Corporation");
85MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN driver.");
86MODULE_SUPPORTED_DEVICE("Broadcom 802.11n WLAN cards");
87MODULE_LICENSE("Dual BSD/GPL");
88
89/* recognized PCI IDs */
90static DEFINE_PCI_DEVICE_TABLE(brcms_pci_id_table) = {
91 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) }, /* 43225 2G */
92 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) }, /* 43224 DUAL */
93 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) }, /* 4313 DUAL */
94 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) }, /* 43224 Ven */
95 {0}
96};
97
98MODULE_DEVICE_TABLE(pci, brcms_pci_id_table);
99
100#ifdef BCMDBG
101static int msglevel = 0xdeadbeef;
102module_param(msglevel, int, 0);
103#endif /* BCMDBG */
104
105static struct ieee80211_channel brcms_2ghz_chantable[] = {
106 CHAN2GHZ(1, 2412, IEEE80211_CHAN_NO_HT40MINUS),
107 CHAN2GHZ(2, 2417, IEEE80211_CHAN_NO_HT40MINUS),
108 CHAN2GHZ(3, 2422, IEEE80211_CHAN_NO_HT40MINUS),
109 CHAN2GHZ(4, 2427, IEEE80211_CHAN_NO_HT40MINUS),
110 CHAN2GHZ(5, 2432, 0),
111 CHAN2GHZ(6, 2437, 0),
112 CHAN2GHZ(7, 2442, 0),
113 CHAN2GHZ(8, 2447, IEEE80211_CHAN_NO_HT40PLUS),
114 CHAN2GHZ(9, 2452, IEEE80211_CHAN_NO_HT40PLUS),
115 CHAN2GHZ(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
116 CHAN2GHZ(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
117 CHAN2GHZ(12, 2467,
118 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
119 IEEE80211_CHAN_NO_HT40PLUS),
120 CHAN2GHZ(13, 2472,
121 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
122 IEEE80211_CHAN_NO_HT40PLUS),
123 CHAN2GHZ(14, 2484,
124 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
125 IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS)
126};
127
128static struct ieee80211_channel brcms_5ghz_nphy_chantable[] = {
129 /* UNII-1 */
130 CHAN5GHZ(36, IEEE80211_CHAN_NO_HT40MINUS),
131 CHAN5GHZ(40, IEEE80211_CHAN_NO_HT40PLUS),
132 CHAN5GHZ(44, IEEE80211_CHAN_NO_HT40MINUS),
133 CHAN5GHZ(48, IEEE80211_CHAN_NO_HT40PLUS),
134 /* UNII-2 */
135 CHAN5GHZ(52,
136 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
137 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
138 CHAN5GHZ(56,
139 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
140 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
141 CHAN5GHZ(60,
142 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
143 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
144 CHAN5GHZ(64,
145 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
146 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
147 /* MID */
148 CHAN5GHZ(100,
149 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
150 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
151 CHAN5GHZ(104,
152 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
153 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
154 CHAN5GHZ(108,
155 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
156 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
157 CHAN5GHZ(112,
158 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
159 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
160 CHAN5GHZ(116,
161 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
162 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
163 CHAN5GHZ(120,
164 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
165 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
166 CHAN5GHZ(124,
167 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
168 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
169 CHAN5GHZ(128,
170 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
171 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
172 CHAN5GHZ(132,
173 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
174 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
175 CHAN5GHZ(136,
176 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
177 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
178 CHAN5GHZ(140,
179 IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
180 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS |
181 IEEE80211_CHAN_NO_HT40MINUS),
182 /* UNII-3 */
183 CHAN5GHZ(149, IEEE80211_CHAN_NO_HT40MINUS),
184 CHAN5GHZ(153, IEEE80211_CHAN_NO_HT40PLUS),
185 CHAN5GHZ(157, IEEE80211_CHAN_NO_HT40MINUS),
186 CHAN5GHZ(161, IEEE80211_CHAN_NO_HT40PLUS),
187 CHAN5GHZ(165, IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS)
188};
189
190/*
191 * The rate table is used for both 2.4G and 5G rates. The
192 * latter being a subset as it does not support CCK rates.
193 */
194static struct ieee80211_rate legacy_ratetable[] = {
195 RATE(10, 0),
196 RATE(20, IEEE80211_RATE_SHORT_PREAMBLE),
197 RATE(55, IEEE80211_RATE_SHORT_PREAMBLE),
198 RATE(110, IEEE80211_RATE_SHORT_PREAMBLE),
199 RATE(60, 0),
200 RATE(90, 0),
201 RATE(120, 0),
202 RATE(180, 0),
203 RATE(240, 0),
204 RATE(360, 0),
205 RATE(480, 0),
206 RATE(540, 0),
207};
208
209static const struct ieee80211_supported_band brcms_band_2GHz_nphy_template = {
210 .band = IEEE80211_BAND_2GHZ,
211 .channels = brcms_2ghz_chantable,
212 .n_channels = ARRAY_SIZE(brcms_2ghz_chantable),
213 .bitrates = legacy_ratetable,
214 .n_bitrates = ARRAY_SIZE(legacy_ratetable),
215 .ht_cap = {
216 /* from include/linux/ieee80211.h */
217 .cap = IEEE80211_HT_CAP_GRN_FLD |
218 IEEE80211_HT_CAP_SGI_20 |
219 IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT,
220 .ht_supported = true,
221 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
222 .ampdu_density = AMPDU_DEF_MPDU_DENSITY,
223 .mcs = {
224 /* placeholders for now */
225 .rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
226 .rx_highest = cpu_to_le16(500),
227 .tx_params = IEEE80211_HT_MCS_TX_DEFINED}
228 }
229};
230
231static const struct ieee80211_supported_band brcms_band_5GHz_nphy_template = {
232 .band = IEEE80211_BAND_5GHZ,
233 .channels = brcms_5ghz_nphy_chantable,
234 .n_channels = ARRAY_SIZE(brcms_5ghz_nphy_chantable),
235 .bitrates = legacy_ratetable + BRCMS_LEGACY_5G_RATE_OFFSET,
236 .n_bitrates = ARRAY_SIZE(legacy_ratetable) -
237 BRCMS_LEGACY_5G_RATE_OFFSET,
238 .ht_cap = {
239 .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
240 IEEE80211_HT_CAP_SGI_40 |
241 IEEE80211_HT_CAP_40MHZ_INTOLERANT, /* No 40 mhz yet */
242 .ht_supported = true,
243 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
244 .ampdu_density = AMPDU_DEF_MPDU_DENSITY,
245 .mcs = {
246 /* placeholders for now */
247 .rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
248 .rx_highest = cpu_to_le16(500),
249 .tx_params = IEEE80211_HT_MCS_TX_DEFINED}
250 }
251};
252
253/* flags the given rate in rateset as requested */
254static void brcms_set_basic_rate(struct brcm_rateset *rs, u16 rate, bool is_br)
255{
256 u32 i;
257
258 for (i = 0; i < rs->count; i++) {
259 if (rate != (rs->rates[i] & 0x7f))
260 continue;
261
262 if (is_br)
263 rs->rates[i] |= BRCMS_RATE_FLAG;
264 else
265 rs->rates[i] &= BRCMS_RATE_MASK;
266 return;
267 }
268}
269
270static void brcms_ops_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
271{
272 struct brcms_info *wl = hw->priv;
273
274 spin_lock_bh(&wl->lock);
275 if (!wl->pub->up) {
276 wiphy_err(wl->wiphy, "ops->tx called while down\n");
277 kfree_skb(skb);
278 goto done;
279 }
280 brcms_c_sendpkt_mac80211(wl->wlc, skb, hw);
281 done:
282 spin_unlock_bh(&wl->lock);
283}
284
285static int brcms_ops_start(struct ieee80211_hw *hw)
286{
287 struct brcms_info *wl = hw->priv;
288 bool blocked;
289
290 ieee80211_wake_queues(hw);
291 spin_lock_bh(&wl->lock);
292 blocked = brcms_rfkill_set_hw_state(wl);
293 spin_unlock_bh(&wl->lock);
294 if (!blocked)
295 wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy);
296
297 return 0;
298}
299
300static void brcms_ops_stop(struct ieee80211_hw *hw)
301{
302 ieee80211_stop_queues(hw);
303}
304
305static int
306brcms_ops_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
307{
308 struct brcms_info *wl;
309 int err;
310
311 /* Just STA for now */
312 if (vif->type != NL80211_IFTYPE_AP &&
313 vif->type != NL80211_IFTYPE_MESH_POINT &&
314 vif->type != NL80211_IFTYPE_STATION &&
315 vif->type != NL80211_IFTYPE_WDS &&
316 vif->type != NL80211_IFTYPE_ADHOC) {
317 wiphy_err(hw->wiphy, "%s: Attempt to add type %d, only"
318 " STA for now\n", __func__, vif->type);
319 return -EOPNOTSUPP;
320 }
321
322 wl = hw->priv;
323 spin_lock_bh(&wl->lock);
324 if (!wl->pub->up)
325 err = brcms_up(wl);
326 else
327 err = -ENODEV;
328 spin_unlock_bh(&wl->lock);
329
330 if (err != 0)
331 wiphy_err(hw->wiphy, "%s: brcms_up() returned %d\n", __func__,
332 err);
333
334 return err;
335}
336
337static void
338brcms_ops_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
339{
340 struct brcms_info *wl;
341
342 wl = hw->priv;
343
344 /* put driver in down state */
345 spin_lock_bh(&wl->lock);
346 brcms_down(wl);
347 spin_unlock_bh(&wl->lock);
348}
349
350static int brcms_ops_config(struct ieee80211_hw *hw, u32 changed)
351{
352 struct ieee80211_conf *conf = &hw->conf;
353 struct brcms_info *wl = hw->priv;
354 int err = 0;
355 int new_int;
356 struct wiphy *wiphy = hw->wiphy;
357
358 spin_lock_bh(&wl->lock);
359 if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) {
360 brcms_c_set_beacon_listen_interval(wl->wlc,
361 conf->listen_interval);
362 }
363 if (changed & IEEE80211_CONF_CHANGE_MONITOR)
364 wiphy_err(wiphy, "%s: change monitor mode: %s (implement)\n",
365 __func__, conf->flags & IEEE80211_CONF_MONITOR ?
366 "true" : "false");
367 if (changed & IEEE80211_CONF_CHANGE_PS)
368 wiphy_err(wiphy, "%s: change power-save mode: %s (implement)\n",
369 __func__, conf->flags & IEEE80211_CONF_PS ?
370 "true" : "false");
371
372 if (changed & IEEE80211_CONF_CHANGE_POWER) {
373 err = brcms_c_set_tx_power(wl->wlc, conf->power_level);
374 if (err < 0) {
375 wiphy_err(wiphy, "%s: Error setting power_level\n",
376 __func__);
377 goto config_out;
378 }
379 new_int = brcms_c_get_tx_power(wl->wlc);
380 if (new_int != conf->power_level)
381 wiphy_err(wiphy, "%s: Power level req != actual, %d %d"
382 "\n", __func__, conf->power_level,
383 new_int);
384 }
385 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
386 if (conf->channel_type == NL80211_CHAN_HT20 ||
387 conf->channel_type == NL80211_CHAN_NO_HT)
388 err = brcms_c_set_channel(wl->wlc,
389 conf->channel->hw_value);
390 else
391 err = -ENOTSUPP;
392 }
393 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
394 err = brcms_c_set_rate_limit(wl->wlc,
395 conf->short_frame_max_tx_count,
396 conf->long_frame_max_tx_count);
397
398 config_out:
399 spin_unlock_bh(&wl->lock);
400 return err;
401}
402
403static void
404brcms_ops_bss_info_changed(struct ieee80211_hw *hw,
405 struct ieee80211_vif *vif,
406 struct ieee80211_bss_conf *info, u32 changed)
407{
408 struct brcms_info *wl = hw->priv;
409 struct wiphy *wiphy = hw->wiphy;
410
411 if (changed & BSS_CHANGED_ASSOC) {
412 /* association status changed (associated/disassociated)
413 * also implies a change in the AID.
414 */
415 wiphy_err(wiphy, "%s: %s: %sassociated\n", KBUILD_MODNAME,
416 __func__, info->assoc ? "" : "dis");
417 spin_lock_bh(&wl->lock);
418 brcms_c_associate_upd(wl->wlc, info->assoc);
419 spin_unlock_bh(&wl->lock);
420 }
421 if (changed & BSS_CHANGED_ERP_SLOT) {
422 s8 val;
423
424 /* slot timing changed */
425 if (info->use_short_slot)
426 val = 1;
427 else
428 val = 0;
429 spin_lock_bh(&wl->lock);
430 brcms_c_set_shortslot_override(wl->wlc, val);
431 spin_unlock_bh(&wl->lock);
432 }
433
434 if (changed & BSS_CHANGED_HT) {
435 /* 802.11n parameters changed */
436 u16 mode = info->ht_operation_mode;
437
438 spin_lock_bh(&wl->lock);
439 brcms_c_protection_upd(wl->wlc, BRCMS_PROT_N_CFG,
440 mode & IEEE80211_HT_OP_MODE_PROTECTION);
441 brcms_c_protection_upd(wl->wlc, BRCMS_PROT_N_NONGF,
442 mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
443 brcms_c_protection_upd(wl->wlc, BRCMS_PROT_N_OBSS,
444 mode & IEEE80211_HT_OP_MODE_NON_HT_STA_PRSNT);
445 spin_unlock_bh(&wl->lock);
446 }
447 if (changed & BSS_CHANGED_BASIC_RATES) {
448 struct ieee80211_supported_band *bi;
449 u32 br_mask, i;
450 u16 rate;
451 struct brcm_rateset rs;
452 int error;
453
454 /* retrieve the current rates */
455 spin_lock_bh(&wl->lock);
456 brcms_c_get_current_rateset(wl->wlc, &rs);
457 spin_unlock_bh(&wl->lock);
458
459 br_mask = info->basic_rates;
460 bi = hw->wiphy->bands[brcms_c_get_curband(wl->wlc)];
461 for (i = 0; i < bi->n_bitrates; i++) {
462 /* convert to internal rate value */
463 rate = (bi->bitrates[i].bitrate << 1) / 10;
464
465 /* set/clear basic rate flag */
466 brcms_set_basic_rate(&rs, rate, br_mask & 1);
467 br_mask >>= 1;
468 }
469
470 /* update the rate set */
471 spin_lock_bh(&wl->lock);
472 error = brcms_c_set_rateset(wl->wlc, &rs);
473 spin_unlock_bh(&wl->lock);
474 if (error)
475 wiphy_err(wiphy, "changing basic rates failed: %d\n",
476 error);
477 }
478 if (changed & BSS_CHANGED_BEACON_INT) {
479 /* Beacon interval changed */
480 spin_lock_bh(&wl->lock);
481 brcms_c_set_beacon_period(wl->wlc, info->beacon_int);
482 spin_unlock_bh(&wl->lock);
483 }
484 if (changed & BSS_CHANGED_BSSID) {
485 /* BSSID changed, for whatever reason (IBSS and managed mode) */
486 spin_lock_bh(&wl->lock);
487 brcms_c_set_addrmatch(wl->wlc, RCM_BSSID_OFFSET, info->bssid);
488 spin_unlock_bh(&wl->lock);
489 }
490 if (changed & BSS_CHANGED_BEACON)
491 /* Beacon data changed, retrieve new beacon (beaconing modes) */
492 wiphy_err(wiphy, "%s: beacon changed\n", __func__);
493
494 if (changed & BSS_CHANGED_BEACON_ENABLED) {
495 /* Beaconing should be enabled/disabled (beaconing modes) */
496 wiphy_err(wiphy, "%s: Beacon enabled: %s\n", __func__,
497 info->enable_beacon ? "true" : "false");
498 }
499
500 if (changed & BSS_CHANGED_CQM) {
501 /* Connection quality monitor config changed */
502 wiphy_err(wiphy, "%s: cqm change: threshold %d, hys %d "
503 " (implement)\n", __func__, info->cqm_rssi_thold,
504 info->cqm_rssi_hyst);
505 }
506
507 if (changed & BSS_CHANGED_IBSS) {
508 /* IBSS join status changed */
509 wiphy_err(wiphy, "%s: IBSS joined: %s (implement)\n", __func__,
510 info->ibss_joined ? "true" : "false");
511 }
512
513 if (changed & BSS_CHANGED_ARP_FILTER) {
514 /* Hardware ARP filter address list or state changed */
515 wiphy_err(wiphy, "%s: arp filtering: enabled %s, count %d"
516 " (implement)\n", __func__, info->arp_filter_enabled ?
517 "true" : "false", info->arp_addr_cnt);
518 }
519
520 if (changed & BSS_CHANGED_QOS) {
521 /*
522 * QoS for this association was enabled/disabled.
523 * Note that it is only ever disabled for station mode.
524 */
525 wiphy_err(wiphy, "%s: qos enabled: %s (implement)\n", __func__,
526 info->qos ? "true" : "false");
527 }
528 return;
529}
530
531static void
532brcms_ops_configure_filter(struct ieee80211_hw *hw,
533 unsigned int changed_flags,
534 unsigned int *total_flags, u64 multicast)
535{
536 struct brcms_info *wl = hw->priv;
537 struct wiphy *wiphy = hw->wiphy;
538
539 changed_flags &= MAC_FILTERS;
540 *total_flags &= MAC_FILTERS;
541 if (changed_flags & FIF_PROMISC_IN_BSS)
542 wiphy_err(wiphy, "FIF_PROMISC_IN_BSS\n");
543 if (changed_flags & FIF_ALLMULTI)
544 wiphy_err(wiphy, "FIF_ALLMULTI\n");
545 if (changed_flags & FIF_FCSFAIL)
546 wiphy_err(wiphy, "FIF_FCSFAIL\n");
547 if (changed_flags & FIF_PLCPFAIL)
548 wiphy_err(wiphy, "FIF_PLCPFAIL\n");
549 if (changed_flags & FIF_CONTROL)
550 wiphy_err(wiphy, "FIF_CONTROL\n");
551 if (changed_flags & FIF_OTHER_BSS)
552 wiphy_err(wiphy, "FIF_OTHER_BSS\n");
553 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
554 spin_lock_bh(&wl->lock);
555 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
556 wl->pub->mac80211_state |= MAC80211_PROMISC_BCNS;
557 brcms_c_mac_bcn_promisc_change(wl->wlc, 1);
558 } else {
559 brcms_c_mac_bcn_promisc_change(wl->wlc, 0);
560 wl->pub->mac80211_state &= ~MAC80211_PROMISC_BCNS;
561 }
562 spin_unlock_bh(&wl->lock);
563 }
564 return;
565}
566
567static void brcms_ops_sw_scan_start(struct ieee80211_hw *hw)
568{
569 struct brcms_info *wl = hw->priv;
570 spin_lock_bh(&wl->lock);
571 brcms_c_scan_start(wl->wlc);
572 spin_unlock_bh(&wl->lock);
573 return;
574}
575
576static void brcms_ops_sw_scan_complete(struct ieee80211_hw *hw)
577{
578 struct brcms_info *wl = hw->priv;
579 spin_lock_bh(&wl->lock);
580 brcms_c_scan_stop(wl->wlc);
581 spin_unlock_bh(&wl->lock);
582 return;
583}
584
585static int
586brcms_ops_conf_tx(struct ieee80211_hw *hw, u16 queue,
587 const struct ieee80211_tx_queue_params *params)
588{
589 struct brcms_info *wl = hw->priv;
590
591 spin_lock_bh(&wl->lock);
592 brcms_c_wme_setparams(wl->wlc, queue, params, true);
593 spin_unlock_bh(&wl->lock);
594
595 return 0;
596}
597
598static int
599brcms_ops_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
600 struct ieee80211_sta *sta)
601{
602 struct brcms_info *wl = hw->priv;
603 struct scb *scb = &wl->wlc->pri_scb;
604
605 brcms_c_init_scb(scb);
606
607 wl->pub->global_ampdu = &(scb->scb_ampdu);
608 wl->pub->global_ampdu->scb = scb;
609 wl->pub->global_ampdu->max_pdu = 16;
610
611 sta->ht_cap.ht_supported = true;
612 sta->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
613 sta->ht_cap.ampdu_density = AMPDU_DEF_MPDU_DENSITY;
614 sta->ht_cap.cap = IEEE80211_HT_CAP_GRN_FLD |
615 IEEE80211_HT_CAP_SGI_20 |
616 IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT;
617
618 /*
619 * minstrel_ht initiates addBA on our behalf by calling
620 * ieee80211_start_tx_ba_session()
621 */
622 return 0;
623}
624
625static int
626brcms_ops_ampdu_action(struct ieee80211_hw *hw,
627 struct ieee80211_vif *vif,
628 enum ieee80211_ampdu_mlme_action action,
629 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
630 u8 buf_size)
631{
632 struct brcms_info *wl = hw->priv;
633 struct scb *scb = &wl->wlc->pri_scb;
634 int status;
635
636 if (WARN_ON(scb->magic != SCB_MAGIC))
637 return -EIDRM;
638 switch (action) {
639 case IEEE80211_AMPDU_RX_START:
640 break;
641 case IEEE80211_AMPDU_RX_STOP:
642 break;
643 case IEEE80211_AMPDU_TX_START:
644 spin_lock_bh(&wl->lock);
645 status = brcms_c_aggregatable(wl->wlc, tid);
646 spin_unlock_bh(&wl->lock);
647 if (!status) {
648 wiphy_err(wl->wiphy, "START: tid %d is not agg\'able\n",
649 tid);
650 return -EINVAL;
651 }
652 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
653 break;
654
655 case IEEE80211_AMPDU_TX_STOP:
656 spin_lock_bh(&wl->lock);
657 brcms_c_ampdu_flush(wl->wlc, sta, tid);
658 spin_unlock_bh(&wl->lock);
659 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
660 break;
661 case IEEE80211_AMPDU_TX_OPERATIONAL:
662 /*
663 * BA window size from ADDBA response ('buf_size') defines how
664 * many outstanding MPDUs are allowed for the BA stream by
665 * recipient and traffic class. 'ampdu_factor' gives maximum
666 * AMPDU size.
667 */
668 spin_lock_bh(&wl->lock);
669 brcms_c_ampdu_tx_operational(wl->wlc, tid, buf_size,
670 (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
671 sta->ht_cap.ampdu_factor)) - 1);
672 spin_unlock_bh(&wl->lock);
673 /* Power save wakeup */
674 break;
675 default:
676 wiphy_err(wl->wiphy, "%s: Invalid command, ignoring\n",
677 __func__);
678 }
679
680 return 0;
681}
682
683static void brcms_ops_rfkill_poll(struct ieee80211_hw *hw)
684{
685 struct brcms_info *wl = hw->priv;
686 bool blocked;
687
688 spin_lock_bh(&wl->lock);
689 blocked = brcms_c_check_radio_disabled(wl->wlc);
690 spin_unlock_bh(&wl->lock);
691
692 wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, blocked);
693}
694
695static void brcms_ops_flush(struct ieee80211_hw *hw, bool drop)
696{
697 struct brcms_info *wl = hw->priv;
698
699 no_printk("%s: drop = %s\n", __func__, drop ? "true" : "false");
700
701 /* wait for packet queue and dma fifos to run empty */
702 spin_lock_bh(&wl->lock);
703 brcms_c_wait_for_tx_completion(wl->wlc, drop);
704 spin_unlock_bh(&wl->lock);
705}
706
707static const struct ieee80211_ops brcms_ops = {
708 .tx = brcms_ops_tx,
709 .start = brcms_ops_start,
710 .stop = brcms_ops_stop,
711 .add_interface = brcms_ops_add_interface,
712 .remove_interface = brcms_ops_remove_interface,
713 .config = brcms_ops_config,
714 .bss_info_changed = brcms_ops_bss_info_changed,
715 .configure_filter = brcms_ops_configure_filter,
716 .sw_scan_start = brcms_ops_sw_scan_start,
717 .sw_scan_complete = brcms_ops_sw_scan_complete,
718 .conf_tx = brcms_ops_conf_tx,
719 .sta_add = brcms_ops_sta_add,
720 .ampdu_action = brcms_ops_ampdu_action,
721 .rfkill_poll = brcms_ops_rfkill_poll,
722 .flush = brcms_ops_flush,
723};
724
725/*
726 * is called in brcms_pci_probe() context, therefore no locking required.
727 */
728static int brcms_set_hint(struct brcms_info *wl, char *abbrev)
729{
730 return regulatory_hint(wl->pub->ieee_hw->wiphy, abbrev);
731}
732
733void brcms_dpc(unsigned long data)
734{
735 struct brcms_info *wl;
736
737 wl = (struct brcms_info *) data;
738
739 spin_lock_bh(&wl->lock);
740
741 /* call the common second level interrupt handler */
742 if (wl->pub->up) {
743 if (wl->resched) {
744 unsigned long flags;
745
746 spin_lock_irqsave(&wl->isr_lock, flags);
747 brcms_c_intrsupd(wl->wlc);
748 spin_unlock_irqrestore(&wl->isr_lock, flags);
749 }
750
751 wl->resched = brcms_c_dpc(wl->wlc, true);
752 }
753
754 /* brcms_c_dpc() may bring the driver down */
755 if (!wl->pub->up)
756 goto done;
757
758 /* re-schedule dpc */
759 if (wl->resched)
760 tasklet_schedule(&wl->tasklet);
761 else
762 /* re-enable interrupts */
763 brcms_intrson(wl);
764
765 done:
766 spin_unlock_bh(&wl->lock);
767}
768
769/*
770 * Precondition: Since this function is called in brcms_pci_probe() context,
771 * no locking is required.
772 */
773static int brcms_request_fw(struct brcms_info *wl, struct pci_dev *pdev)
774{
775 int status;
776 struct device *device = &pdev->dev;
777 char fw_name[100];
778 int i;
779
780 memset(&wl->fw, 0, sizeof(struct brcms_firmware));
781 for (i = 0; i < MAX_FW_IMAGES; i++) {
782 if (brcms_firmwares[i] == NULL)
783 break;
784 sprintf(fw_name, "%s-%d.fw", brcms_firmwares[i],
785 UCODE_LOADER_API_VER);
786 status = request_firmware(&wl->fw.fw_bin[i], fw_name, device);
787 if (status) {
788 wiphy_err(wl->wiphy, "%s: fail to load firmware %s\n",
789 KBUILD_MODNAME, fw_name);
790 return status;
791 }
792 sprintf(fw_name, "%s_hdr-%d.fw", brcms_firmwares[i],
793 UCODE_LOADER_API_VER);
794 status = request_firmware(&wl->fw.fw_hdr[i], fw_name, device);
795 if (status) {
796 wiphy_err(wl->wiphy, "%s: fail to load firmware %s\n",
797 KBUILD_MODNAME, fw_name);
798 return status;
799 }
800 wl->fw.hdr_num_entries[i] =
801 wl->fw.fw_hdr[i]->size / (sizeof(struct firmware_hdr));
802 }
803 wl->fw.fw_cnt = i;
804 return brcms_ucode_data_init(wl, &wl->ucode);
805}
806
807/*
808 * Precondition: Since this function is called in brcms_pci_probe() context,
809 * no locking is required.
810 */
811static void brcms_release_fw(struct brcms_info *wl)
812{
813 int i;
814 for (i = 0; i < MAX_FW_IMAGES; i++) {
815 release_firmware(wl->fw.fw_bin[i]);
816 release_firmware(wl->fw.fw_hdr[i]);
817 }
818}
819
820/**
821 * This function frees the WL per-device resources.
822 *
823 * This function frees resources owned by the WL device pointed to
824 * by the wl parameter.
825 *
826 * precondition: can both be called locked and unlocked
827 *
828 */
829static void brcms_free(struct brcms_info *wl)
830{
831 struct brcms_timer *t, *next;
832
833 /* free ucode data */
834 if (wl->fw.fw_cnt)
835 brcms_ucode_data_free(&wl->ucode);
836 if (wl->irq)
837 free_irq(wl->irq, wl);
838
839 /* kill dpc */
840 tasklet_kill(&wl->tasklet);
841
842 if (wl->pub)
843 brcms_c_module_unregister(wl->pub, "linux", wl);
844
845 /* free common resources */
846 if (wl->wlc) {
847 brcms_c_detach(wl->wlc);
848 wl->wlc = NULL;
849 wl->pub = NULL;
850 }
851
852 /* virtual interface deletion is deferred so we cannot spinwait */
853
854 /* wait for all pending callbacks to complete */
855 while (atomic_read(&wl->callbacks) > 0)
856 schedule();
857
858 /* free timers */
859 for (t = wl->timers; t; t = next) {
860 next = t->next;
861#ifdef BCMDBG
862 kfree(t->name);
863#endif
864 kfree(t);
865 }
866
867 /*
868 * unregister_netdev() calls get_stats() which may read chip
869 * registers so we cannot unmap the chip registers until
870 * after calling unregister_netdev() .
871 */
872 if (wl->regsva)
873 iounmap(wl->regsva);
874
875 wl->regsva = NULL;
876}
877
878/*
879* called from both kernel as from this kernel module.
880* precondition: perimeter lock is not acquired.
881*/
882static void brcms_remove(struct pci_dev *pdev)
883{
884 struct brcms_info *wl;
885 struct ieee80211_hw *hw;
886 int status;
887
888 hw = pci_get_drvdata(pdev);
889 wl = hw->priv;
890 if (!wl) {
891 pr_err("wl: brcms_remove: pci_get_drvdata failed\n");
892 return;
893 }
894
895 spin_lock_bh(&wl->lock);
896 status = brcms_c_chipmatch(pdev->vendor, pdev->device);
897 spin_unlock_bh(&wl->lock);
898 if (!status) {
899 wiphy_err(wl->wiphy, "wl: brcms_remove: chipmatch "
900 "failed\n");
901 return;
902 }
903 if (wl->wlc) {
904 wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, false);
905 wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy);
906 ieee80211_unregister_hw(hw);
907 spin_lock_bh(&wl->lock);
908 brcms_down(wl);
909 spin_unlock_bh(&wl->lock);
910 }
911 pci_disable_device(pdev);
912
913 brcms_free(wl);
914
915 pci_set_drvdata(pdev, NULL);
916 ieee80211_free_hw(hw);
917}
918
919static irqreturn_t brcms_isr(int irq, void *dev_id)
920{
921 struct brcms_info *wl;
922 bool ours, wantdpc;
923
924 wl = (struct brcms_info *) dev_id;
925
926 spin_lock(&wl->isr_lock);
927
928 /* call common first level interrupt handler */
929 ours = brcms_c_isr(wl->wlc, &wantdpc);
930 if (ours) {
931 /* if more to do... */
932 if (wantdpc) {
933
934 /* ...and call the second level interrupt handler */
935 /* schedule dpc */
936 tasklet_schedule(&wl->tasklet);
937 }
938 }
939
940 spin_unlock(&wl->isr_lock);
941
942 return IRQ_RETVAL(ours);
943}
944
945/*
946 * is called in brcms_pci_probe() context, therefore no locking required.
947 */
948static int ieee_hw_rate_init(struct ieee80211_hw *hw)
949{
950 struct brcms_info *wl = hw->priv;
951 struct brcms_c_info *wlc = wl->wlc;
952 struct ieee80211_supported_band *band;
953 int has_5g = 0;
954 u16 phy_type;
955
956 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = NULL;
957 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = NULL;
958
959 phy_type = brcms_c_get_phy_type(wl->wlc, 0);
960 if (phy_type == PHY_TYPE_N || phy_type == PHY_TYPE_LCN) {
961 band = &wlc->bandstate[BAND_2G_INDEX]->band;
962 *band = brcms_band_2GHz_nphy_template;
963 if (phy_type == PHY_TYPE_LCN) {
964 /* Single stream */
965 band->ht_cap.mcs.rx_mask[1] = 0;
966 band->ht_cap.mcs.rx_highest = 72;
967 }
968 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = band;
969 } else {
970 return -EPERM;
971 }
972
973 /* Assume all bands use the same phy. True for 11n devices. */
974 if (wl->pub->_nbands > 1) {
975 has_5g++;
976 if (phy_type == PHY_TYPE_N || phy_type == PHY_TYPE_LCN) {
977 band = &wlc->bandstate[BAND_5G_INDEX]->band;
978 *band = brcms_band_5GHz_nphy_template;
979 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = band;
980 } else {
981 return -EPERM;
982 }
983 }
984 return 0;
985}
986
987/*
988 * is called in brcms_pci_probe() context, therefore no locking required.
989 */
990static int ieee_hw_init(struct ieee80211_hw *hw)
991{
992 hw->flags = IEEE80211_HW_SIGNAL_DBM
993 /* | IEEE80211_HW_CONNECTION_MONITOR What is this? */
994 | IEEE80211_HW_REPORTS_TX_ACK_STATUS
995 | IEEE80211_HW_AMPDU_AGGREGATION;
996
997 hw->extra_tx_headroom = brcms_c_get_header_len();
998 hw->queues = N_TX_QUEUES;
999 hw->max_rates = 2; /* Primary rate and 1 fallback rate */
1000
1001 /* channel change time is dependent on chip and band */
1002 hw->channel_change_time = 7 * 1000;
1003 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1004
1005 hw->rate_control_algorithm = "minstrel_ht";
1006
1007 hw->sta_data_size = 0;
1008 return ieee_hw_rate_init(hw);
1009}
1010
1011/**
1012 * attach to the WL device.
1013 *
1014 * Attach to the WL device identified by vendor and device parameters.
1015 * regs is a host accessible memory address pointing to WL device registers.
1016 *
1017 * brcms_attach is not defined as static because in the case where no bus
1018 * is defined, wl_attach will never be called, and thus, gcc will issue
1019 * a warning that this function is defined but not used if we declare
1020 * it as static.
1021 *
1022 *
1023 * is called in brcms_pci_probe() context, therefore no locking required.
1024 */
1025static struct brcms_info *brcms_attach(u16 vendor, u16 device,
1026 resource_size_t regs,
1027 struct pci_dev *btparam, uint irq)
1028{
1029 struct brcms_info *wl = NULL;
1030 int unit, err;
1031 struct ieee80211_hw *hw;
1032 u8 perm[ETH_ALEN];
1033
1034 unit = n_adapters_found;
1035 err = 0;
1036
1037 if (unit < 0)
1038 return NULL;
1039
1040 /* allocate private info */
1041 hw = pci_get_drvdata(btparam); /* btparam == pdev */
1042 if (hw != NULL)
1043 wl = hw->priv;
1044 if (WARN_ON(hw == NULL) || WARN_ON(wl == NULL))
1045 return NULL;
1046 wl->wiphy = hw->wiphy;
1047
1048 atomic_set(&wl->callbacks, 0);
1049
1050 /* setup the bottom half handler */
1051 tasklet_init(&wl->tasklet, brcms_dpc, (unsigned long) wl);
1052
1053 wl->regsva = ioremap_nocache(regs, PCI_BAR0_WINSZ);
1054 if (wl->regsva == NULL) {
1055 wiphy_err(wl->wiphy, "wl%d: ioremap() failed\n", unit);
1056 goto fail;
1057 }
1058 spin_lock_init(&wl->lock);
1059 spin_lock_init(&wl->isr_lock);
1060
1061 /* prepare ucode */
1062 if (brcms_request_fw(wl, btparam) < 0) {
1063 wiphy_err(wl->wiphy, "%s: Failed to find firmware usually in "
1064 "%s\n", KBUILD_MODNAME, "/lib/firmware/brcm");
1065 brcms_release_fw(wl);
1066 brcms_remove(btparam);
1067 return NULL;
1068 }
1069
1070 /* common load-time initialization */
1071 wl->wlc = brcms_c_attach(wl, vendor, device, unit, false,
1072 wl->regsva, btparam, &err);
1073 brcms_release_fw(wl);
1074 if (!wl->wlc) {
1075 wiphy_err(wl->wiphy, "%s: attach() failed with code %d\n",
1076 KBUILD_MODNAME, err);
1077 goto fail;
1078 }
1079 wl->pub = brcms_c_pub(wl->wlc);
1080
1081 wl->pub->ieee_hw = hw;
1082
1083 /* disable mpc */
1084 brcms_c_set_radio_mpc(wl->wlc, false);
1085
1086 /* register our interrupt handler */
1087 if (request_irq(irq, brcms_isr, IRQF_SHARED, KBUILD_MODNAME, wl)) {
1088 wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit);
1089 goto fail;
1090 }
1091 wl->irq = irq;
1092
1093 /* register module */
1094 brcms_c_module_register(wl->pub, "linux", wl, NULL);
1095
1096 if (ieee_hw_init(hw)) {
1097 wiphy_err(wl->wiphy, "wl%d: %s: ieee_hw_init failed!\n", unit,
1098 __func__);
1099 goto fail;
1100 }
1101
1102 memcpy(perm, &wl->pub->cur_etheraddr, ETH_ALEN);
1103 if (WARN_ON(!is_valid_ether_addr(perm)))
1104 goto fail;
1105 SET_IEEE80211_PERM_ADDR(hw, perm);
1106
1107 err = ieee80211_register_hw(hw);
1108 if (err)
1109 wiphy_err(wl->wiphy, "%s: ieee80211_register_hw failed, status"
1110 "%d\n", __func__, err);
1111
1112 if (wl->pub->srom_ccode[0])
1113 err = brcms_set_hint(wl, wl->pub->srom_ccode);
1114 else
1115 err = brcms_set_hint(wl, "US");
1116 if (err)
1117 wiphy_err(wl->wiphy, "%s: regulatory_hint failed, status %d\n",
1118 __func__, err);
1119
1120 n_adapters_found++;
1121 return wl;
1122
1123fail:
1124 brcms_free(wl);
1125 return NULL;
1126}
1127
1128
1129
1130/**
1131 * determines if a device is a WL device, and if so, attaches it.
1132 *
1133 * This function determines if a device pointed to by pdev is a WL device,
1134 * and if so, performs a brcms_attach() on it.
1135 *
1136 * Perimeter lock is initialized in the course of this function.
1137 */
1138static int __devinit
1139brcms_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1140{
1141 int rc;
1142 struct brcms_info *wl;
1143 struct ieee80211_hw *hw;
1144 u32 val;
1145
1146 dev_info(&pdev->dev, "bus %d slot %d func %d irq %d\n",
1147 pdev->bus->number, PCI_SLOT(pdev->devfn),
1148 PCI_FUNC(pdev->devfn), pdev->irq);
1149
1150 if ((pdev->vendor != PCI_VENDOR_ID_BROADCOM) ||
1151 ((pdev->device != 0x0576) &&
1152 ((pdev->device & 0xff00) != 0x4300) &&
1153 ((pdev->device & 0xff00) != 0x4700) &&
1154 ((pdev->device < 43000) || (pdev->device > 43999))))
1155 return -ENODEV;
1156
1157 rc = pci_enable_device(pdev);
1158 if (rc) {
1159 pr_err("%s: Cannot enable device %d-%d_%d\n",
1160 __func__, pdev->bus->number, PCI_SLOT(pdev->devfn),
1161 PCI_FUNC(pdev->devfn));
1162 return -ENODEV;
1163 }
1164 pci_set_master(pdev);
1165
1166 pci_read_config_dword(pdev, 0x40, &val);
1167 if ((val & 0x0000ff00) != 0)
1168 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1169
1170 hw = ieee80211_alloc_hw(sizeof(struct brcms_info), &brcms_ops);
1171 if (!hw) {
1172 pr_err("%s: ieee80211_alloc_hw failed\n", __func__);
1173 return -ENOMEM;
1174 }
1175
1176 SET_IEEE80211_DEV(hw, &pdev->dev);
1177
1178 pci_set_drvdata(pdev, hw);
1179
1180 memset(hw->priv, 0, sizeof(*wl));
1181
1182 wl = brcms_attach(pdev->vendor, pdev->device,
1183 pci_resource_start(pdev, 0), pdev,
1184 pdev->irq);
1185
1186 if (!wl) {
1187 pr_err("%s: %s: brcms_attach failed!\n", KBUILD_MODNAME,
1188 __func__);
1189 return -ENODEV;
1190 }
1191 return 0;
1192}
1193
1194static int brcms_suspend(struct pci_dev *pdev, pm_message_t state)
1195{
1196 struct brcms_info *wl;
1197 struct ieee80211_hw *hw;
1198
1199 hw = pci_get_drvdata(pdev);
1200 wl = hw->priv;
1201 if (!wl) {
1202 wiphy_err(wl->wiphy,
1203 "brcms_suspend: pci_get_drvdata failed\n");
1204 return -ENODEV;
1205 }
1206
1207 /* only need to flag hw is down for proper resume */
1208 spin_lock_bh(&wl->lock);
1209 wl->pub->hw_up = false;
1210 spin_unlock_bh(&wl->lock);
1211
1212 pci_save_state(pdev);
1213 pci_disable_device(pdev);
1214 return pci_set_power_state(pdev, PCI_D3hot);
1215}
1216
1217static int brcms_resume(struct pci_dev *pdev)
1218{
1219 struct brcms_info *wl;
1220 struct ieee80211_hw *hw;
1221 int err = 0;
1222 u32 val;
1223
1224 hw = pci_get_drvdata(pdev);
1225 wl = hw->priv;
1226 if (!wl) {
1227 wiphy_err(wl->wiphy,
1228 "wl: brcms_resume: pci_get_drvdata failed\n");
1229 return -ENODEV;
1230 }
1231
1232 err = pci_set_power_state(pdev, PCI_D0);
1233 if (err)
1234 return err;
1235
1236 pci_restore_state(pdev);
1237
1238 err = pci_enable_device(pdev);
1239 if (err)
1240 return err;
1241
1242 pci_set_master(pdev);
1243
1244 pci_read_config_dword(pdev, 0x40, &val);
1245 if ((val & 0x0000ff00) != 0)
1246 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1247
1248 /*
1249 * done. driver will be put in up state
1250 * in brcms_ops_add_interface() call.
1251 */
1252 return err;
1253}
1254
1255static struct pci_driver brcms_pci_driver = {
1256 .name = KBUILD_MODNAME,
1257 .probe = brcms_pci_probe,
1258 .suspend = brcms_suspend,
1259 .resume = brcms_resume,
1260 .remove = __devexit_p(brcms_remove),
1261 .id_table = brcms_pci_id_table,
1262};
1263
1264/**
1265 * This is the main entry point for the WL driver.
1266 *
1267 * This function determines if a device pointed to by pdev is a WL device,
1268 * and if so, performs a brcms_attach() on it.
1269 *
1270 */
1271static int __init brcms_module_init(void)
1272{
1273 int error = -ENODEV;
1274
1275#ifdef BCMDBG
1276 if (msglevel != 0xdeadbeef)
1277 brcm_msg_level = msglevel;
1278#endif /* BCMDBG */
1279
1280 error = pci_register_driver(&brcms_pci_driver);
1281 if (!error)
1282 return 0;
1283
1284
1285
1286 return error;
1287}
1288
1289/**
1290 * This function unloads the WL driver from the system.
1291 *
1292 * This function unconditionally unloads the WL driver module from the
1293 * system.
1294 *
1295 */
1296static void __exit brcms_module_exit(void)
1297{
1298 pci_unregister_driver(&brcms_pci_driver);
1299
1300}
1301
1302module_init(brcms_module_init);
1303module_exit(brcms_module_exit);
1304
1305/*
1306 * precondition: perimeter lock has been acquired
1307 */
1308void brcms_txflowcontrol(struct brcms_info *wl, struct brcms_if *wlif,
1309 bool state, int prio)
1310{
1311 wiphy_err(wl->wiphy, "Shouldn't be here %s\n", __func__);
1312}
1313
1314/*
1315 * precondition: perimeter lock has been acquired
1316 */
1317void brcms_init(struct brcms_info *wl)
1318{
1319 BCMMSG(wl->pub->ieee_hw->wiphy, "wl%d\n", wl->pub->unit);
1320 brcms_reset(wl);
1321
1322 brcms_c_init(wl->wlc);
1323}
1324
1325/*
1326 * precondition: perimeter lock has been acquired
1327 */
1328uint brcms_reset(struct brcms_info *wl)
1329{
1330 BCMMSG(wl->pub->ieee_hw->wiphy, "wl%d\n", wl->pub->unit);
1331 brcms_c_reset(wl->wlc);
1332
1333 /* dpc will not be rescheduled */
1334 wl->resched = 0;
1335
1336 return 0;
1337}
1338
1339/*
1340 * These are interrupt on/off entry points. Disable interrupts
1341 * during interrupt state transition.
1342 */
1343void brcms_intrson(struct brcms_info *wl)
1344{
1345 unsigned long flags;
1346
1347 spin_lock_irqsave(&wl->isr_lock, flags);
1348 brcms_c_intrson(wl->wlc);
1349 spin_unlock_irqrestore(&wl->isr_lock, flags);
1350}
1351
1352u32 brcms_intrsoff(struct brcms_info *wl)
1353{
1354 unsigned long flags;
1355 u32 status;
1356
1357 spin_lock_irqsave(&wl->isr_lock, flags);
1358 status = brcms_c_intrsoff(wl->wlc);
1359 spin_unlock_irqrestore(&wl->isr_lock, flags);
1360 return status;
1361}
1362
1363void brcms_intrsrestore(struct brcms_info *wl, u32 macintmask)
1364{
1365 unsigned long flags;
1366
1367 spin_lock_irqsave(&wl->isr_lock, flags);
1368 brcms_c_intrsrestore(wl->wlc, macintmask);
1369 spin_unlock_irqrestore(&wl->isr_lock, flags);
1370}
1371
1372/*
1373 * precondition: perimeter lock has been acquired
1374 */
1375int brcms_up(struct brcms_info *wl)
1376{
1377 int error = 0;
1378
1379 if (wl->pub->up)
1380 return 0;
1381
1382 error = brcms_c_up(wl->wlc);
1383
1384 return error;
1385}
1386
1387/*
1388 * precondition: perimeter lock has been acquired
1389 */
1390void brcms_down(struct brcms_info *wl)
1391{
1392 uint callbacks, ret_val = 0;
1393
1394 /* call common down function */
1395 ret_val = brcms_c_down(wl->wlc);
1396 callbacks = atomic_read(&wl->callbacks) - ret_val;
1397
1398 /* wait for down callbacks to complete */
1399 spin_unlock_bh(&wl->lock);
1400
1401 /* For HIGH_only driver, it's important to actually schedule other work,
1402 * not just spin wait since everything runs at schedule level
1403 */
1404 SPINWAIT((atomic_read(&wl->callbacks) > callbacks), 100 * 1000);
1405
1406 spin_lock_bh(&wl->lock);
1407}
1408
1409/*
1410* precondition: perimeter lock is not acquired
1411 */
1412void brcms_timer(struct brcms_timer *t)
1413{
1414 spin_lock_bh(&t->wl->lock);
1415
1416 if (t->set) {
1417 if (t->periodic) {
1418 t->timer.expires = jiffies + t->ms * HZ / 1000;
1419 atomic_inc(&t->wl->callbacks);
1420 add_timer(&t->timer);
1421 t->set = true;
1422 } else
1423 t->set = false;
1424
1425 t->fn(t->arg);
1426 }
1427
1428 atomic_dec(&t->wl->callbacks);
1429
1430 spin_unlock_bh(&t->wl->lock);
1431}
1432
1433/*
1434 * is called by the kernel from software irq context
1435 */
1436static void _brcms_timer(unsigned long data)
1437{
1438 brcms_timer((struct brcms_timer *) data);
1439}
1440
1441/*
1442 * Adds a timer to the list. Caller supplies a timer function.
1443 * Is called from wlc.
1444 *
1445 * precondition: perimeter lock has been acquired
1446 */
1447struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
1448 void (*fn) (void *arg),
1449 void *arg, const char *name)
1450{
1451 struct brcms_timer *t;
1452
1453 t = kzalloc(sizeof(struct brcms_timer), GFP_ATOMIC);
1454 if (!t)
1455 return NULL;
1456
1457 init_timer(&t->timer);
1458 t->timer.data = (unsigned long) t;
1459 t->timer.function = _brcms_timer;
1460 t->wl = wl;
1461 t->fn = fn;
1462 t->arg = arg;
1463 t->next = wl->timers;
1464 wl->timers = t;
1465
1466#ifdef BCMDBG
1467 t->name = kmalloc(strlen(name) + 1, GFP_ATOMIC);
1468 if (t->name)
1469 strcpy(t->name, name);
1470#endif
1471
1472 return t;
1473}
1474
1475/*
1476 * adds only the kernel timer since it's going to be more accurate
1477 * as well as it's easier to make it periodic
1478 *
1479 * precondition: perimeter lock has been acquired
1480 */
1481void brcms_add_timer(struct brcms_info *wl, struct brcms_timer *t, uint ms,
1482 int periodic)
1483{
1484#ifdef BCMDBG
1485 if (t->set)
1486 wiphy_err(wl->wiphy, "%s: Already set. Name: %s, per %d\n",
1487 __func__, t->name, periodic);
1488
1489#endif
1490 t->ms = ms;
1491 t->periodic = (bool) periodic;
1492 t->set = true;
1493 t->timer.expires = jiffies + ms * HZ / 1000;
1494
1495 atomic_inc(&wl->callbacks);
1496 add_timer(&t->timer);
1497}
1498
1499/*
1500 * return true if timer successfully deleted, false if still pending
1501 *
1502 * precondition: perimeter lock has been acquired
1503 */
1504bool brcms_del_timer(struct brcms_info *wl, struct brcms_timer *t)
1505{
1506 if (t->set) {
1507 t->set = false;
1508 if (!del_timer(&t->timer))
1509 return false;
1510
1511 atomic_dec(&wl->callbacks);
1512 }
1513
1514 return true;
1515}
1516
1517/*
1518 * precondition: perimeter lock has been acquired
1519 */
1520void brcms_free_timer(struct brcms_info *wl, struct brcms_timer *t)
1521{
1522 struct brcms_timer *tmp;
1523
1524 /* delete the timer in case it is active */
1525 brcms_del_timer(wl, t);
1526
1527 if (wl->timers == t) {
1528 wl->timers = wl->timers->next;
1529#ifdef BCMDBG
1530 kfree(t->name);
1531#endif
1532 kfree(t);
1533 return;
1534
1535 }
1536
1537 tmp = wl->timers;
1538 while (tmp) {
1539 if (tmp->next == t) {
1540 tmp->next = t->next;
1541#ifdef BCMDBG
1542 kfree(t->name);
1543#endif
1544 kfree(t);
1545 return;
1546 }
1547 tmp = tmp->next;
1548 }
1549
1550}
1551
1552/*
1553 * precondition: perimeter lock has been acquired
1554 */
1555int brcms_ucode_init_buf(struct brcms_info *wl, void **pbuf, u32 idx)
1556{
1557 int i, entry;
1558 const u8 *pdata;
1559 struct firmware_hdr *hdr;
1560 for (i = 0; i < wl->fw.fw_cnt; i++) {
1561 hdr = (struct firmware_hdr *)wl->fw.fw_hdr[i]->data;
1562 for (entry = 0; entry < wl->fw.hdr_num_entries[i];
1563 entry++, hdr++) {
1564 u32 len = le32_to_cpu(hdr->len);
1565 if (le32_to_cpu(hdr->idx) == idx) {
1566 pdata = wl->fw.fw_bin[i]->data +
1567 le32_to_cpu(hdr->offset);
1568 *pbuf = kmalloc(len, GFP_ATOMIC);
1569 if (*pbuf == NULL)
1570 goto fail;
1571
1572 memcpy(*pbuf, pdata, len);
1573 return 0;
1574 }
1575 }
1576 }
1577 wiphy_err(wl->wiphy, "ERROR: ucode buf tag:%d can not be found!\n",
1578 idx);
1579 *pbuf = NULL;
1580fail:
1581 return -ENODATA;
1582}
1583
1584/*
1585 * Precondition: Since this function is called in brcms_pci_probe() context,
1586 * no locking is required.
1587 */
1588int brcms_ucode_init_uint(struct brcms_info *wl, size_t *n_bytes, u32 idx)
1589{
1590 int i, entry;
1591 const u8 *pdata;
1592 struct firmware_hdr *hdr;
1593 for (i = 0; i < wl->fw.fw_cnt; i++) {
1594 hdr = (struct firmware_hdr *)wl->fw.fw_hdr[i]->data;
1595 for (entry = 0; entry < wl->fw.hdr_num_entries[i];
1596 entry++, hdr++) {
1597 if (le32_to_cpu(hdr->idx) == idx) {
1598 pdata = wl->fw.fw_bin[i]->data +
1599 le32_to_cpu(hdr->offset);
1600 if (le32_to_cpu(hdr->len) != 4) {
1601 wiphy_err(wl->wiphy,
1602 "ERROR: fw hdr len\n");
1603 return -ENOMSG;
1604 }
1605 *n_bytes = le32_to_cpu(*((__le32 *) pdata));
1606 return 0;
1607 }
1608 }
1609 }
1610 wiphy_err(wl->wiphy, "ERROR: ucode tag:%d can not be found!\n", idx);
1611 return -ENOMSG;
1612}
1613
1614/*
1615 * precondition: can both be called locked and unlocked
1616 */
1617void brcms_ucode_free_buf(void *p)
1618{
1619 kfree(p);
1620}
1621
1622/*
1623 * checks validity of all firmware images loaded from user space
1624 *
1625 * Precondition: Since this function is called in brcms_pci_probe() context,
1626 * no locking is required.
1627 */
1628int brcms_check_firmwares(struct brcms_info *wl)
1629{
1630 int i;
1631 int entry;
1632 int rc = 0;
1633 const struct firmware *fw;
1634 const struct firmware *fw_hdr;
1635 struct firmware_hdr *ucode_hdr;
1636 for (i = 0; i < MAX_FW_IMAGES && rc == 0; i++) {
1637 fw = wl->fw.fw_bin[i];
1638 fw_hdr = wl->fw.fw_hdr[i];
1639 if (fw == NULL && fw_hdr == NULL) {
1640 break;
1641 } else if (fw == NULL || fw_hdr == NULL) {
1642 wiphy_err(wl->wiphy, "%s: invalid bin/hdr fw\n",
1643 __func__);
1644 rc = -EBADF;
1645 } else if (fw_hdr->size % sizeof(struct firmware_hdr)) {
1646 wiphy_err(wl->wiphy, "%s: non integral fw hdr file "
1647 "size %zu/%zu\n", __func__, fw_hdr->size,
1648 sizeof(struct firmware_hdr));
1649 rc = -EBADF;
1650 } else if (fw->size < MIN_FW_SIZE || fw->size > MAX_FW_SIZE) {
1651 wiphy_err(wl->wiphy, "%s: out of bounds fw file size "
1652 "%zu\n", __func__, fw->size);
1653 rc = -EBADF;
1654 } else {
1655 /* check if ucode section overruns firmware image */
1656 ucode_hdr = (struct firmware_hdr *)fw_hdr->data;
1657 for (entry = 0; entry < wl->fw.hdr_num_entries[i] &&
1658 !rc; entry++, ucode_hdr++) {
1659 if (le32_to_cpu(ucode_hdr->offset) +
1660 le32_to_cpu(ucode_hdr->len) >
1661 fw->size) {
1662 wiphy_err(wl->wiphy,
1663 "%s: conflicting bin/hdr\n",
1664 __func__);
1665 rc = -EBADF;
1666 }
1667 }
1668 }
1669 }
1670 if (rc == 0 && wl->fw.fw_cnt != i) {
1671 wiphy_err(wl->wiphy, "%s: invalid fw_cnt=%d\n", __func__,
1672 wl->fw.fw_cnt);
1673 rc = -EBADF;
1674 }
1675 return rc;
1676}
1677
1678/*
1679 * precondition: perimeter lock has been acquired
1680 */
1681bool brcms_rfkill_set_hw_state(struct brcms_info *wl)
1682{
1683 bool blocked = brcms_c_check_radio_disabled(wl->wlc);
1684
1685 spin_unlock_bh(&wl->lock);
1686 wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, blocked);
1687 if (blocked)
1688 wiphy_rfkill_start_polling(wl->pub->ieee_hw->wiphy);
1689 spin_lock_bh(&wl->lock);
1690 return blocked;
1691}
1692
1693/*
1694 * precondition: perimeter lock has been acquired
1695 */
1696void brcms_msleep(struct brcms_info *wl, uint ms)
1697{
1698 spin_unlock_bh(&wl->lock);
1699 msleep(ms);
1700 spin_lock_bh(&wl->lock);
1701}
diff --git a/drivers/staging/brcm80211/brcmsmac/mac80211_if.h b/drivers/staging/brcm80211/brcmsmac/mac80211_if.h
deleted file mode 100644
index 92256d0318f..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/mac80211_if.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_MAC80211_IF_H_
18#define _BRCM_MAC80211_IF_H_
19
20#include <linux/timer.h>
21#include <linux/interrupt.h>
22#include "ucode_loader.h"
23/*
24 * Starting index for 5G rates in the
25 * legacy rate table.
26 */
27#define BRCMS_LEGACY_5G_RATE_OFFSET 4
28
29/* softmac ioctl definitions */
30#define BRCMS_SET_SHORTSLOT_OVERRIDE 146
31
32struct brcms_timer {
33 struct timer_list timer;
34 struct brcms_info *wl;
35 void (*fn) (void *);
36 void *arg; /* argument to fn */
37 uint ms;
38 bool periodic;
39 bool set;
40 struct brcms_timer *next;
41#ifdef BCMDBG
42 char *name; /* Description of the timer */
43#endif
44};
45
46struct brcms_if {
47 uint subunit; /* WDS/BSS unit */
48 struct pci_dev *pci_dev;
49};
50
51#define MAX_FW_IMAGES 4
52struct brcms_firmware {
53 u32 fw_cnt;
54 const struct firmware *fw_bin[MAX_FW_IMAGES];
55 const struct firmware *fw_hdr[MAX_FW_IMAGES];
56 u32 hdr_num_entries[MAX_FW_IMAGES];
57};
58
59struct brcms_info {
60 struct brcms_pub *pub; /* pointer to public wlc state */
61 struct brcms_c_info *wlc; /* pointer to private common data */
62 u32 magic;
63
64 int irq;
65
66 spinlock_t lock; /* per-device perimeter lock */
67 spinlock_t isr_lock; /* per-device ISR synchronization lock */
68
69 /* regsva for unmap in brcms_free() */
70 void __iomem *regsva; /* opaque chip registers virtual address */
71
72 /* timer related fields */
73 atomic_t callbacks; /* # outstanding callback functions */
74 struct brcms_timer *timers; /* timer cleanup queue */
75
76 struct tasklet_struct tasklet; /* dpc tasklet */
77 bool resched; /* dpc needs to be and is rescheduled */
78 struct brcms_firmware fw;
79 struct wiphy *wiphy;
80 struct brcms_ucode ucode;
81};
82
83/* misc callbacks */
84extern void brcms_init(struct brcms_info *wl);
85extern uint brcms_reset(struct brcms_info *wl);
86extern void brcms_intrson(struct brcms_info *wl);
87extern u32 brcms_intrsoff(struct brcms_info *wl);
88extern void brcms_intrsrestore(struct brcms_info *wl, u32 macintmask);
89extern int brcms_up(struct brcms_info *wl);
90extern void brcms_down(struct brcms_info *wl);
91extern void brcms_txflowcontrol(struct brcms_info *wl, struct brcms_if *wlif,
92 bool state, int prio);
93extern bool brcms_rfkill_set_hw_state(struct brcms_info *wl);
94
95/* timer functions */
96extern struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
97 void (*fn) (void *arg), void *arg,
98 const char *name);
99extern void brcms_free_timer(struct brcms_info *wl, struct brcms_timer *timer);
100extern void brcms_add_timer(struct brcms_info *wl, struct brcms_timer *timer,
101 uint ms, int periodic);
102extern bool brcms_del_timer(struct brcms_info *wl, struct brcms_timer *timer);
103extern void brcms_msleep(struct brcms_info *wl, uint ms);
104extern void brcms_dpc(unsigned long data);
105extern void brcms_timer(struct brcms_timer *t);
106
107#endif /* _BRCM_MAC80211_IF_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/main.c b/drivers/staging/brcm80211/brcmsmac/main.c
deleted file mode 100644
index 1e35be95262..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/main.c
+++ /dev/null
@@ -1,8841 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/pci_ids.h>
18#include <linux/if_ether.h>
19#include <net/mac80211.h>
20#include <brcm_hw_ids.h>
21#include <aiutils.h>
22#include <chipcommon.h>
23#include "rate.h"
24#include "scb.h"
25#include "phy/phy_hal.h"
26#include "channel.h"
27#include "antsel.h"
28#include "stf.h"
29#include "ampdu.h"
30#include "mac80211_if.h"
31#include "ucode_loader.h"
32#include "main.h"
33
34/*
35 * Indication for txflowcontrol that all priority bits in
36 * TXQ_STOP_FOR_PRIOFC_MASK are to be considered.
37 */
38#define ALLPRIO -1
39
40/*
41 * 32 SSID chars, max of 4 chars for each SSID char "\xFF", plus NULL.
42 */
43#define SSID_FMT_BUF_LEN ((4 * IEEE80211_MAX_SSID_LEN) + 1)
44
45/* watchdog timer, in unit of ms */
46#define TIMER_INTERVAL_WATCHDOG 1000
47/* radio monitor timer, in unit of ms */
48#define TIMER_INTERVAL_RADIOCHK 800
49
50/* Max MPC timeout, in unit of watchdog */
51#ifndef BRCMS_MPC_MAX_DELAYCNT
52#define BRCMS_MPC_MAX_DELAYCNT 10
53#endif
54
55/* Min MPC timeout, in unit of watchdog */
56#define BRCMS_MPC_MIN_DELAYCNT 1
57#define BRCMS_MPC_THRESHOLD 3 /* MPC count threshold level */
58
59/* beacon interval, in unit of 1024TU */
60#define BEACON_INTERVAL_DEFAULT 100
61/* DTIM interval, in unit of beacon interval */
62#define DTIM_INTERVAL_DEFAULT 3
63
64/* Scale down delays to accommodate QT slow speed */
65/* beacon interval, in unit of 1024TU */
66#define BEACON_INTERVAL_DEF_QT 20
67/* DTIM interval, in unit of beacon interval */
68#define DTIM_INTERVAL_DEF_QT 1
69
70#define TBTT_ALIGN_LEEWAY_US 100 /* min leeway before first TBTT in us */
71
72/* n-mode support capability */
73/* 2x2 includes both 1x1 & 2x2 devices
74 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
75 * control it independently
76 */
77#define WL_11N_2x2 1
78#define WL_11N_3x3 3
79#define WL_11N_4x4 4
80
81/* define 11n feature disable flags */
82#define WLFEATURE_DISABLE_11N 0x00000001
83#define WLFEATURE_DISABLE_11N_STBC_TX 0x00000002
84#define WLFEATURE_DISABLE_11N_STBC_RX 0x00000004
85#define WLFEATURE_DISABLE_11N_SGI_TX 0x00000008
86#define WLFEATURE_DISABLE_11N_SGI_RX 0x00000010
87#define WLFEATURE_DISABLE_11N_AMPDU_TX 0x00000020
88#define WLFEATURE_DISABLE_11N_AMPDU_RX 0x00000040
89#define WLFEATURE_DISABLE_11N_GF 0x00000080
90
91#define EDCF_ACI_MASK 0x60
92#define EDCF_ACI_SHIFT 5
93#define EDCF_ECWMIN_MASK 0x0f
94#define EDCF_ECWMAX_SHIFT 4
95#define EDCF_AIFSN_MASK 0x0f
96#define EDCF_AIFSN_MAX 15
97#define EDCF_ECWMAX_MASK 0xf0
98
99#define EDCF_AC_BE_TXOP_STA 0x0000
100#define EDCF_AC_BK_TXOP_STA 0x0000
101#define EDCF_AC_VO_ACI_STA 0x62
102#define EDCF_AC_VO_ECW_STA 0x32
103#define EDCF_AC_VI_ACI_STA 0x42
104#define EDCF_AC_VI_ECW_STA 0x43
105#define EDCF_AC_BK_ECW_STA 0xA4
106#define EDCF_AC_VI_TXOP_STA 0x005e
107#define EDCF_AC_VO_TXOP_STA 0x002f
108#define EDCF_AC_BE_ACI_STA 0x03
109#define EDCF_AC_BE_ECW_STA 0xA4
110#define EDCF_AC_BK_ACI_STA 0x27
111#define EDCF_AC_VO_TXOP_AP 0x002f
112
113#define EDCF_TXOP2USEC(txop) ((txop) << 5)
114#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
115
116#define APHY_SYMBOL_TIME 4
117#define APHY_PREAMBLE_TIME 16
118#define APHY_SIGNAL_TIME 4
119#define APHY_SIFS_TIME 16
120#define APHY_SERVICE_NBITS 16
121#define APHY_TAIL_NBITS 6
122#define BPHY_SIFS_TIME 10
123#define BPHY_PLCP_SHORT_TIME 96
124
125#define PREN_PREAMBLE 24
126#define PREN_MM_EXT 12
127#define PREN_PREAMBLE_EXT 4
128
129#define DOT11_MAC_HDR_LEN 24
130#define DOT11_ACK_LEN 10
131#define DOT11_BA_LEN 4
132#define DOT11_OFDM_SIGNAL_EXTENSION 6
133#define DOT11_MIN_FRAG_LEN 256
134#define DOT11_RTS_LEN 16
135#define DOT11_CTS_LEN 10
136#define DOT11_BA_BITMAP_LEN 128
137#define DOT11_MIN_BEACON_PERIOD 1
138#define DOT11_MAX_BEACON_PERIOD 0xFFFF
139#define DOT11_MAXNUMFRAGS 16
140#define DOT11_MAX_FRAG_LEN 2346
141
142#define BPHY_PLCP_TIME 192
143#define RIFS_11N_TIME 2
144
145#define WME_VER 1
146#define WME_SUBTYPE_PARAM_IE 1
147#define WME_TYPE 2
148#define WME_OUI "\x00\x50\xf2"
149
150#define AC_BE 0
151#define AC_BK 1
152#define AC_VI 2
153#define AC_VO 3
154
155#define BCN_TMPL_LEN 512 /* length of the BCN template area */
156
157/* brcms_bss_info flag bit values */
158#define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
159
160/* Flags used in brcms_c_txq_info.stopped */
161/* per prio flow control bits */
162#define TXQ_STOP_FOR_PRIOFC_MASK 0x000000FF
163/* stop txq enqueue for packet drain */
164#define TXQ_STOP_FOR_PKT_DRAIN 0x00000100
165/* stop txq enqueue for ampdu flow control */
166#define TXQ_STOP_FOR_AMPDU_FLOW_CNTRL 0x00000200
167
168#define BRCMS_HWRXOFF 38 /* chip rx buffer offset */
169
170/* Find basic rate for a given rate */
171static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
172{
173 if (is_mcs_rate(rspec))
174 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
175 .leg_ofdm];
176 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
177}
178
179static u16 frametype(u32 rspec, u8 mimoframe)
180{
181 if (is_mcs_rate(rspec))
182 return mimoframe;
183 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
184}
185
186/* rfdisable delay timer 500 ms, runs of ALP clock */
187#define RFDISABLE_DEFAULT 10000000
188
189#define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
190
191/* precedences numbers for wlc queues. These are twice as may levels as
192 * 802.1D priorities.
193 * Odd numbers are used for HI priority traffic at same precedence levels
194 * These constants are used ONLY by wlc_prio2prec_map. Do not use them
195 * elsewhere.
196 */
197#define _BRCMS_PREC_NONE 0 /* None = - */
198#define _BRCMS_PREC_BK 2 /* BK - Background */
199#define _BRCMS_PREC_BE 4 /* BE - Best-effort */
200#define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */
201#define _BRCMS_PREC_CL 8 /* CL - Controlled Load */
202#define _BRCMS_PREC_VI 10 /* Vi - Video */
203#define _BRCMS_PREC_VO 12 /* Vo - Voice */
204#define _BRCMS_PREC_NC 14 /* NC - Network Control */
205
206/* The BSS is generating beacons in HW */
207#define BRCMS_BSSCFG_HW_BCN 0x20
208
209#define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
210#define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us */
211#define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us */
212#define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
213
214#define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
215
216#define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
217
218/* Per-AC retry limit register definitions; uses defs.h bitfield macros */
219#define EDCF_SHORT_S 0
220#define EDCF_SFB_S 4
221#define EDCF_LONG_S 8
222#define EDCF_LFB_S 12
223#define EDCF_SHORT_M BITFIELD_MASK(4)
224#define EDCF_SFB_M BITFIELD_MASK(4)
225#define EDCF_LONG_M BITFIELD_MASK(4)
226#define EDCF_LFB_M BITFIELD_MASK(4)
227
228#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
229#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
230#define RETRY_LONG_DEF 4 /* Default Long retry count */
231#define RETRY_SHORT_FB 3 /* Short count for fallback rate */
232#define RETRY_LONG_FB 2 /* Long count for fallback rate */
233
234#define APHY_CWMIN 15
235#define PHY_CWMAX 1023
236
237#define EDCF_AIFSN_MIN 1
238
239#define FRAGNUM_MASK 0xF
240
241#define APHY_SLOT_TIME 9
242#define BPHY_SLOT_TIME 20
243
244#define WL_SPURAVOID_OFF 0
245#define WL_SPURAVOID_ON1 1
246#define WL_SPURAVOID_ON2 2
247
248/* invalid core flags, use the saved coreflags */
249#define BRCMS_USE_COREFLAGS 0xffffffff
250
251/* values for PLCPHdr_override */
252#define BRCMS_PLCP_AUTO -1
253#define BRCMS_PLCP_SHORT 0
254#define BRCMS_PLCP_LONG 1
255
256/* values for g_protection_override and n_protection_override */
257#define BRCMS_PROTECTION_AUTO -1
258#define BRCMS_PROTECTION_OFF 0
259#define BRCMS_PROTECTION_ON 1
260#define BRCMS_PROTECTION_MMHDR_ONLY 2
261#define BRCMS_PROTECTION_CTS_ONLY 3
262
263/* values for g_protection_control and n_protection_control */
264#define BRCMS_PROTECTION_CTL_OFF 0
265#define BRCMS_PROTECTION_CTL_LOCAL 1
266#define BRCMS_PROTECTION_CTL_OVERLAP 2
267
268/* values for n_protection */
269#define BRCMS_N_PROTECTION_OFF 0
270#define BRCMS_N_PROTECTION_OPTIONAL 1
271#define BRCMS_N_PROTECTION_20IN40 2
272#define BRCMS_N_PROTECTION_MIXEDMODE 3
273
274/* values for band specific 40MHz capabilities */
275#define BRCMS_N_BW_20ALL 0
276#define BRCMS_N_BW_40ALL 1
277#define BRCMS_N_BW_20IN2G_40IN5G 2
278
279/* bitflags for SGI support (sgi_rx iovar) */
280#define BRCMS_N_SGI_20 0x01
281#define BRCMS_N_SGI_40 0x02
282
283/* defines used by the nrate iovar */
284/* MSC in use,indicates b0-6 holds an mcs */
285#define NRATE_MCS_INUSE 0x00000080
286/* rate/mcs value */
287#define NRATE_RATE_MASK 0x0000007f
288/* stf mode mask: siso, cdd, stbc, sdm */
289#define NRATE_STF_MASK 0x0000ff00
290/* stf mode shift */
291#define NRATE_STF_SHIFT 8
292/* bit indicates override both rate & mode */
293#define NRATE_OVERRIDE 0x80000000
294/* bit indicate to override mcs only */
295#define NRATE_OVERRIDE_MCS_ONLY 0x40000000
296#define NRATE_SGI_MASK 0x00800000 /* sgi mode */
297#define NRATE_SGI_SHIFT 23 /* sgi mode */
298#define NRATE_LDPC_CODING 0x00400000 /* bit indicates adv coding in use */
299#define NRATE_LDPC_SHIFT 22 /* ldpc shift */
300
301#define NRATE_STF_SISO 0 /* stf mode SISO */
302#define NRATE_STF_CDD 1 /* stf mode CDD */
303#define NRATE_STF_STBC 2 /* stf mode STBC */
304#define NRATE_STF_SDM 3 /* stf mode SDM */
305
306#define MAX_DMA_SEGS 4
307
308/* Max # of entries in Tx FIFO based on 4kb page size */
309#define NTXD 256
310/* Max # of entries in Rx FIFO based on 4kb page size */
311#define NRXD 256
312
313/* try to keep this # rbufs posted to the chip */
314#define NRXBUFPOST 32
315
316/* data msg txq hiwat mark */
317#define BRCMS_DATAHIWAT 50
318
319/* bounded rx loops */
320#define RXBND 8 /* max # frames to process in brcms_c_recv() */
321#define TXSBND 8 /* max # tx status to process in wlc_txstatus() */
322
323/*
324 * 32 SSID chars, max of 4 chars for each SSID char "\xFF", plus NULL.
325 */
326#define SSID_FMT_BUF_LEN ((4 * IEEE80211_MAX_SSID_LEN) + 1)
327
328/*
329 * The following table lists the buffer memory allocated to xmt fifos in HW.
330 * the size is in units of 256bytes(one block), total size is HW dependent
331 * ucode has default fifo partition, sw can overwrite if necessary
332 *
333 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
334 * the twiki is updated before making changes.
335 */
336
337/* Starting corerev for the fifo size table */
338#define XMTFIFOTBL_STARTREV 20
339
340struct d11init {
341 __le16 addr;
342 __le16 size;
343 __le32 value;
344};
345
346/* currently the best mechanism for determining SIFS is the band in use */
347static u16 get_sifs(struct brcms_band *band)
348{
349 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
350 BPHY_SIFS_TIME;
351}
352
353
354/*
355 * Detect Card removed.
356 * Even checking an sbconfig register read will not false trigger when the core
357 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
358 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
359 * reg with fixed 0/1 pattern (some platforms return all 0).
360 * If clocks are present, call the sb routine which will figure out if the
361 * device is removed.
362 */
363static bool brcms_deviceremoved(struct brcms_c_info *wlc)
364{
365 if (!wlc->hw->clk)
366 return ai_deviceremoved(wlc->hw->sih);
367 return (R_REG(&wlc->hw->regs->maccontrol) &
368 (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
369}
370
371/* sum the individual fifo tx pending packet counts */
372static s16 brcms_txpktpendtot(struct brcms_c_info *wlc)
373{
374 return wlc->core->txpktpend[0] + wlc->core->txpktpend[1] +
375 wlc->core->txpktpend[2] + wlc->core->txpktpend[3];
376}
377
378static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
379{
380 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
381}
382
383static int brcms_chspec_bw(u16 chanspec)
384{
385 if (CHSPEC_IS40(chanspec))
386 return BRCMS_40_MHZ;
387 if (CHSPEC_IS20(chanspec))
388 return BRCMS_20_MHZ;
389
390 return BRCMS_10_MHZ;
391}
392
393struct edcf_acparam {
394 u8 ACI;
395 u8 ECW;
396 u16 TXOP;
397} __packed;
398
399const u8 prio2fifo[NUMPRIO] = {
400 TX_AC_BE_FIFO, /* 0 BE AC_BE Best Effort */
401 TX_AC_BK_FIFO, /* 1 BK AC_BK Background */
402 TX_AC_BK_FIFO, /* 2 -- AC_BK Background */
403 TX_AC_BE_FIFO, /* 3 EE AC_BE Best Effort */
404 TX_AC_VI_FIFO, /* 4 CL AC_VI Video */
405 TX_AC_VI_FIFO, /* 5 VI AC_VI Video */
406 TX_AC_VO_FIFO, /* 6 VO AC_VO Voice */
407 TX_AC_VO_FIFO /* 7 NC AC_VO Voice */
408};
409
410/* debug/trace */
411uint brcm_msg_level =
412#if defined(BCMDBG)
413 LOG_ERROR_VAL;
414#else
415 0;
416#endif /* BCMDBG */
417
418/* TX FIFO number to WME/802.1E Access Category */
419static const u8 wme_fifo2ac[] = { AC_BK, AC_BE, AC_VI, AC_VO, AC_BE, AC_BE };
420
421/* WME/802.1E Access Category to TX FIFO number */
422static const u8 wme_ac2fifo[] = { 1, 0, 2, 3 };
423
424/* 802.1D Priority to precedence queue mapping */
425const u8 wlc_prio2prec_map[] = {
426 _BRCMS_PREC_BE, /* 0 BE - Best-effort */
427 _BRCMS_PREC_BK, /* 1 BK - Background */
428 _BRCMS_PREC_NONE, /* 2 None = - */
429 _BRCMS_PREC_EE, /* 3 EE - Excellent-effort */
430 _BRCMS_PREC_CL, /* 4 CL - Controlled Load */
431 _BRCMS_PREC_VI, /* 5 Vi - Video */
432 _BRCMS_PREC_VO, /* 6 Vo - Voice */
433 _BRCMS_PREC_NC, /* 7 NC - Network Control */
434};
435
436static const u16 xmtfifo_sz[][NFIFO] = {
437 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
438 {20, 192, 192, 21, 17, 5},
439 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
440 {9, 58, 22, 14, 14, 5},
441 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
442 {20, 192, 192, 21, 17, 5},
443 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
444 {20, 192, 192, 21, 17, 5},
445 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
446 {9, 58, 22, 14, 14, 5},
447};
448
449static const u8 acbitmap2maxprio[] = {
450 PRIO_8021D_BE, PRIO_8021D_BE, PRIO_8021D_BK, PRIO_8021D_BK,
451 PRIO_8021D_VI, PRIO_8021D_VI, PRIO_8021D_VI, PRIO_8021D_VI,
452 PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO,
453 PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO
454};
455
456#ifdef BCMDBG
457static const char * const fifo_names[] = {
458 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
459#else
460static const char fifo_names[6][0];
461#endif
462
463#ifdef BCMDBG
464/* pointer to most recently allocated wl/wlc */
465static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
466#endif
467
468static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
469{
470 if (cfg == NULL)
471 return;
472
473 kfree(cfg->current_bss);
474 kfree(cfg);
475}
476
477static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
478{
479 if (wlc == NULL)
480 return;
481
482 brcms_c_bsscfg_mfree(wlc->bsscfg);
483 kfree(wlc->pub);
484 kfree(wlc->modulecb);
485 kfree(wlc->default_bss);
486 kfree(wlc->protection);
487 kfree(wlc->stf);
488 kfree(wlc->bandstate[0]);
489 kfree(wlc->corestate->macstat_snapshot);
490 kfree(wlc->corestate);
491 kfree(wlc->hw->bandstate[0]);
492 kfree(wlc->hw);
493
494 /* free the wlc */
495 kfree(wlc);
496 wlc = NULL;
497}
498
499static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
500{
501 struct brcms_bss_cfg *cfg;
502
503 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
504 if (cfg == NULL)
505 goto fail;
506
507 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
508 if (cfg->current_bss == NULL)
509 goto fail;
510
511 return cfg;
512
513 fail:
514 brcms_c_bsscfg_mfree(cfg);
515 return NULL;
516}
517
518static struct brcms_c_info *
519brcms_c_attach_malloc(uint unit, uint *err, uint devid)
520{
521 struct brcms_c_info *wlc;
522
523 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
524 if (wlc == NULL) {
525 *err = 1002;
526 goto fail;
527 }
528
529 /* allocate struct brcms_c_pub state structure */
530 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
531 if (wlc->pub == NULL) {
532 *err = 1003;
533 goto fail;
534 }
535 wlc->pub->wlc = wlc;
536
537 /* allocate struct brcms_hardware state structure */
538
539 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
540 if (wlc->hw == NULL) {
541 *err = 1005;
542 goto fail;
543 }
544 wlc->hw->wlc = wlc;
545
546 wlc->hw->bandstate[0] =
547 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
548 if (wlc->hw->bandstate[0] == NULL) {
549 *err = 1006;
550 goto fail;
551 } else {
552 int i;
553
554 for (i = 1; i < MAXBANDS; i++)
555 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
556 ((unsigned long)wlc->hw->bandstate[0] +
557 (sizeof(struct brcms_hw_band) * i));
558 }
559
560 wlc->modulecb =
561 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
562 if (wlc->modulecb == NULL) {
563 *err = 1009;
564 goto fail;
565 }
566
567 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
568 if (wlc->default_bss == NULL) {
569 *err = 1010;
570 goto fail;
571 }
572
573 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
574 if (wlc->bsscfg == NULL) {
575 *err = 1011;
576 goto fail;
577 }
578
579 wlc->protection = kzalloc(sizeof(struct brcms_protection),
580 GFP_ATOMIC);
581 if (wlc->protection == NULL) {
582 *err = 1016;
583 goto fail;
584 }
585
586 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
587 if (wlc->stf == NULL) {
588 *err = 1017;
589 goto fail;
590 }
591
592 wlc->bandstate[0] =
593 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
594 if (wlc->bandstate[0] == NULL) {
595 *err = 1025;
596 goto fail;
597 } else {
598 int i;
599
600 for (i = 1; i < MAXBANDS; i++)
601 wlc->bandstate[i] = (struct brcms_band *)
602 ((unsigned long)wlc->bandstate[0]
603 + (sizeof(struct brcms_band)*i));
604 }
605
606 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
607 if (wlc->corestate == NULL) {
608 *err = 1026;
609 goto fail;
610 }
611
612 wlc->corestate->macstat_snapshot =
613 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
614 if (wlc->corestate->macstat_snapshot == NULL) {
615 *err = 1027;
616 goto fail;
617 }
618
619 return wlc;
620
621 fail:
622 brcms_c_detach_mfree(wlc);
623 return NULL;
624}
625
626/*
627 * Update the slot timing for standard 11b/g (20us slots)
628 * or shortslot 11g (9us slots)
629 * The PSM needs to be suspended for this call.
630 */
631static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
632 bool shortslot)
633{
634 struct d11regs __iomem *regs;
635
636 regs = wlc_hw->regs;
637
638 if (shortslot) {
639 /* 11g short slot: 11a timing */
640 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
641 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
642 } else {
643 /* 11g long slot: 11b timing */
644 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
645 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
646 }
647}
648
649static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
650 const struct d11init *inits)
651{
652 int i;
653 u8 __iomem *base;
654 u8 __iomem *addr;
655 u16 size;
656 u32 value;
657
658 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
659
660 base = (u8 __iomem *)wlc_hw->regs;
661
662 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
663 size = le16_to_cpu(inits[i].size);
664 addr = base + le16_to_cpu(inits[i].addr);
665 value = le32_to_cpu(inits[i].value);
666 if (size == 2)
667 W_REG((u16 __iomem *)addr, value);
668 else if (size == 4)
669 W_REG((u32 __iomem *)addr, value);
670 else
671 break;
672 }
673}
674
675static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
676{
677 u8 idx;
678 u16 addr[] = {
679 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
680 M_HOST_FLAGS5
681 };
682
683 for (idx = 0; idx < MHFMAX; idx++)
684 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
685}
686
687static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
688{
689 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
690 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
691
692 /* init microcode host flags */
693 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
694
695 /* do band-specific ucode IHR, SHM, and SCR inits */
696 if (D11REV_IS(wlc_hw->corerev, 23)) {
697 if (BRCMS_ISNPHY(wlc_hw->band))
698 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
699 else
700 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
701 " %d\n", __func__, wlc_hw->unit,
702 wlc_hw->corerev);
703 } else {
704 if (D11REV_IS(wlc_hw->corerev, 24)) {
705 if (BRCMS_ISLCNPHY(wlc_hw->band))
706 brcms_c_write_inits(wlc_hw,
707 ucode->d11lcn0bsinitvals24);
708 else
709 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
710 " core rev %d\n", __func__,
711 wlc_hw->unit, wlc_hw->corerev);
712 } else {
713 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
714 __func__, wlc_hw->unit, wlc_hw->corerev);
715 }
716 }
717}
718
719static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
720{
721 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
722
723 wlc_hw->phyclk = clk;
724
725 if (OFF == clk) { /* clear gmode bit, put phy into reset */
726
727 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
728 (SICF_PRST | SICF_FGC));
729 udelay(1);
730 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
731 udelay(1);
732
733 } else { /* take phy out of reset */
734
735 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
736 udelay(1);
737 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
738 udelay(1);
739
740 }
741}
742
743/* switch to new band but leave it inactive */
744static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
745{
746 struct brcms_hardware *wlc_hw = wlc->hw;
747 u32 macintmask;
748
749 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
750
751 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
752
753 /* disable interrupts */
754 macintmask = brcms_intrsoff(wlc->wl);
755
756 /* radio off */
757 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
758
759 brcms_b_core_phy_clk(wlc_hw, OFF);
760
761 brcms_c_setxband(wlc_hw, bandunit);
762
763 return macintmask;
764}
765
766/* Process received frames */
767/*
768 * Return true if more frames need to be processed. false otherwise.
769 * Param 'bound' indicates max. # frames to process before break out.
770 */
771static bool
772brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
773{
774 struct sk_buff *p;
775 struct sk_buff *head = NULL;
776 struct sk_buff *tail = NULL;
777 uint n = 0;
778 uint bound_limit = bound ? RXBND : -1;
779
780 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
781 /* gather received frames */
782 while ((p = dma_rx(wlc_hw->di[fifo]))) {
783
784 if (!tail)
785 head = tail = p;
786 else {
787 tail->prev = p;
788 tail = p;
789 }
790
791 /* !give others some time to run! */
792 if (++n >= bound_limit)
793 break;
794 }
795
796 /* post more rbufs */
797 dma_rxfill(wlc_hw->di[fifo]);
798
799 /* process each frame */
800 while ((p = head) != NULL) {
801 struct d11rxhdr_le *rxh_le;
802 struct d11rxhdr *rxh;
803 head = head->prev;
804 p->prev = NULL;
805
806 rxh_le = (struct d11rxhdr_le *)p->data;
807 rxh = (struct d11rxhdr *)p->data;
808
809 /* fixup rx header endianness */
810 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
811 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
812 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
813 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
814 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
815 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
816 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
817 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
818 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
819 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
820 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
821
822 brcms_c_recv(wlc_hw->wlc, p);
823 }
824
825 return n >= bound_limit;
826}
827
828/* process an individual struct tx_status */
829static bool
830brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
831{
832 struct sk_buff *p;
833 uint queue;
834 struct d11txh *txh;
835 struct scb *scb = NULL;
836 bool free_pdu;
837 int tx_rts, tx_frame_count, tx_rts_count;
838 uint totlen, supr_status;
839 bool lastframe;
840 struct ieee80211_hdr *h;
841 u16 mcl;
842 struct ieee80211_tx_info *tx_info;
843 struct ieee80211_tx_rate *txrate;
844 int i;
845
846 /* discard intermediate indications for ucode with one legitimate case:
847 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
848 * but the subsequent tx of DATA failed. so it will start rts/cts
849 * from the beginning (resetting the rts transmission count)
850 */
851 if (!(txs->status & TX_STATUS_AMPDU)
852 && (txs->status & TX_STATUS_INTERMEDIATE)) {
853 wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n",
854 __func__);
855 return false;
856 }
857
858 queue = txs->frameid & TXFID_QUEUE_MASK;
859 if (queue >= NFIFO) {
860 p = NULL;
861 goto fatal;
862 }
863
864 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
865 if (p == NULL)
866 goto fatal;
867
868 txh = (struct d11txh *) (p->data);
869 mcl = le16_to_cpu(txh->MacTxControlLow);
870
871 if (txs->phyerr) {
872 if (brcm_msg_level & LOG_ERROR_VAL) {
873 wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
874 txs->phyerr, txh->MainRates);
875 brcms_c_print_txdesc(txh);
876 }
877 brcms_c_print_txstatus(txs);
878 }
879
880 if (txs->frameid != le16_to_cpu(txh->TxFrameID))
881 goto fatal;
882 tx_info = IEEE80211_SKB_CB(p);
883 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
884
885 if (tx_info->control.sta)
886 scb = &wlc->pri_scb;
887
888 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
889 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
890 return false;
891 }
892
893 supr_status = txs->status & TX_STATUS_SUPR_MASK;
894 if (supr_status == TX_STATUS_SUPR_BADCH)
895 BCMMSG(wlc->wiphy,
896 "%s: Pkt tx suppressed, possibly channel %d\n",
897 __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
898
899 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
900 tx_frame_count =
901 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
902 tx_rts_count =
903 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
904
905 lastframe = !ieee80211_has_morefrags(h->frame_control);
906
907 if (!lastframe) {
908 wiphy_err(wlc->wiphy, "Not last frame!\n");
909 } else {
910 /*
911 * Set information to be consumed by Minstrel ht.
912 *
913 * The "fallback limit" is the number of tx attempts a given
914 * MPDU is sent at the "primary" rate. Tx attempts beyond that
915 * limit are sent at the "secondary" rate.
916 * A 'short frame' does not exceed RTS treshold.
917 */
918 u16 sfbl, /* Short Frame Rate Fallback Limit */
919 lfbl, /* Long Frame Rate Fallback Limit */
920 fbl;
921
922 if (queue < AC_COUNT) {
923 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
924 EDCF_SFB);
925 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
926 EDCF_LFB);
927 } else {
928 sfbl = wlc->SFBL;
929 lfbl = wlc->LFBL;
930 }
931
932 txrate = tx_info->status.rates;
933 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
934 fbl = lfbl;
935 else
936 fbl = sfbl;
937
938 ieee80211_tx_info_clear_status(tx_info);
939
940 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
941 /*
942 * rate selection requested a fallback rate
943 * and we used it
944 */
945 txrate[0].count = fbl;
946 txrate[1].count = tx_frame_count - fbl;
947 } else {
948 /*
949 * rate selection did not request fallback rate, or
950 * we didn't need it
951 */
952 txrate[0].count = tx_frame_count;
953 /*
954 * rc80211_minstrel.c:minstrel_tx_status() expects
955 * unused rates to be marked with idx = -1
956 */
957 txrate[1].idx = -1;
958 txrate[1].count = 0;
959 }
960
961 /* clear the rest of the rates */
962 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
963 txrate[i].idx = -1;
964 txrate[i].count = 0;
965 }
966
967 if (txs->status & TX_STATUS_ACK_RCV)
968 tx_info->flags |= IEEE80211_TX_STAT_ACK;
969 }
970
971 totlen = brcmu_pkttotlen(p);
972 free_pdu = true;
973
974 brcms_c_txfifo_complete(wlc, queue, 1);
975
976 if (lastframe) {
977 p->next = NULL;
978 p->prev = NULL;
979 /* remove PLCP & Broadcom tx descriptor header */
980 skb_pull(p, D11_PHY_HDR_LEN);
981 skb_pull(p, D11_TXH_LEN);
982 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
983 } else {
984 wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
985 "tx_status\n", __func__);
986 }
987
988 return false;
989
990 fatal:
991 if (p)
992 brcmu_pkt_buf_free_skb(p);
993
994 return true;
995
996}
997
998/* process tx completion events in BMAC
999 * Return true if more tx status need to be processed. false otherwise.
1000 */
1001static bool
1002brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1003{
1004 bool morepending = false;
1005 struct brcms_c_info *wlc = wlc_hw->wlc;
1006 struct d11regs __iomem *regs;
1007 struct tx_status txstatus, *txs;
1008 u32 s1, s2;
1009 uint n = 0;
1010 /*
1011 * Param 'max_tx_num' indicates max. # tx status to process before
1012 * break out.
1013 */
1014 uint max_tx_num = bound ? TXSBND : -1;
1015
1016 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
1017
1018 txs = &txstatus;
1019 regs = wlc_hw->regs;
1020 *fatal = false;
1021 while (!(*fatal)
1022 && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
1023
1024 if (s1 == 0xffffffff) {
1025 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
1026 wlc_hw->unit, __func__);
1027 return morepending;
1028 }
1029
1030 s2 = R_REG(&regs->frmtxstatus2);
1031
1032 txs->status = s1 & TXS_STATUS_MASK;
1033 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1034 txs->sequence = s2 & TXS_SEQ_MASK;
1035 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1036 txs->lasttxtime = 0;
1037
1038 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1039
1040 /* !give others some time to run! */
1041 if (++n >= max_tx_num)
1042 break;
1043 }
1044
1045 if (*fatal)
1046 return 0;
1047
1048 if (n >= max_tx_num)
1049 morepending = true;
1050
1051 if (!pktq_empty(&wlc->pkt_queue->q))
1052 brcms_c_send_q(wlc);
1053
1054 return morepending;
1055}
1056
1057/* second-level interrupt processing
1058 * Return true if another dpc needs to be re-scheduled. false otherwise.
1059 * Param 'bounded' indicates if applicable loops should be bounded.
1060 */
1061bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
1062{
1063 u32 macintstatus;
1064 struct brcms_hardware *wlc_hw = wlc->hw;
1065 struct d11regs __iomem *regs = wlc_hw->regs;
1066 struct wiphy *wiphy = wlc->wiphy;
1067
1068 if (brcms_deviceremoved(wlc)) {
1069 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
1070 __func__);
1071 brcms_down(wlc->wl);
1072 return false;
1073 }
1074
1075 /* grab and clear the saved software intstatus bits */
1076 macintstatus = wlc->macintstatus;
1077 wlc->macintstatus = 0;
1078
1079 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
1080 wlc_hw->unit, macintstatus);
1081
1082 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
1083
1084 /* tx status */
1085 if (macintstatus & MI_TFS) {
1086 bool fatal;
1087 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
1088 wlc->macintstatus |= MI_TFS;
1089 if (fatal) {
1090 wiphy_err(wiphy, "MI_TFS: fatal\n");
1091 goto fatal;
1092 }
1093 }
1094
1095 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
1096 brcms_c_tbtt(wlc);
1097
1098 /* ATIM window end */
1099 if (macintstatus & MI_ATIMWINEND) {
1100 BCMMSG(wlc->wiphy, "end of ATIM window\n");
1101 OR_REG(&regs->maccommand, wlc->qvalid);
1102 wlc->qvalid = 0;
1103 }
1104
1105 /*
1106 * received data or control frame, MI_DMAINT is
1107 * indication of RX_FIFO interrupt
1108 */
1109 if (macintstatus & MI_DMAINT)
1110 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
1111 wlc->macintstatus |= MI_DMAINT;
1112
1113 /* noise sample collected */
1114 if (macintstatus & MI_BG_NOISE)
1115 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
1116
1117 if (macintstatus & MI_GP0) {
1118 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
1119 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
1120
1121 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
1122 __func__, wlc_hw->sih->chip,
1123 wlc_hw->sih->chiprev);
1124 /* big hammer */
1125 brcms_init(wlc->wl);
1126 }
1127
1128 /* gptimer timeout */
1129 if (macintstatus & MI_TO)
1130 W_REG(&regs->gptimer, 0);
1131
1132 if (macintstatus & MI_RFDISABLE) {
1133 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
1134 " RF Disable Input\n", wlc_hw->unit);
1135 brcms_rfkill_set_hw_state(wlc->wl);
1136 }
1137
1138 /* send any enq'd tx packets. Just makes sure to jump start tx */
1139 if (!pktq_empty(&wlc->pkt_queue->q))
1140 brcms_c_send_q(wlc);
1141
1142 /* it isn't done and needs to be resched if macintstatus is non-zero */
1143 return wlc->macintstatus != 0;
1144
1145 fatal:
1146 brcms_init(wlc->wl);
1147 return wlc->macintstatus != 0;
1148}
1149
1150/* set initial host flags value */
1151static void
1152brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1153{
1154 struct brcms_hardware *wlc_hw = wlc->hw;
1155
1156 memset(mhfs, 0, MHFMAX * sizeof(u16));
1157
1158 mhfs[MHF2] |= mhf2_init;
1159
1160 /* prohibit use of slowclock on multifunction boards */
1161 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1162 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1163
1164 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1165 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1166 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1167 }
1168}
1169
1170static struct dma64regs __iomem *
1171dmareg(struct brcms_hardware *hw, uint direction, uint fifonum)
1172{
1173 if (direction == DMA_TX)
1174 return &(hw->regs->fifo64regs[fifonum].dmaxmt);
1175 return &(hw->regs->fifo64regs[fifonum].dmarcv);
1176}
1177
1178static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1179{
1180 uint i;
1181 char name[8];
1182 /*
1183 * ucode host flag 2 needed for pio mode, independent of band and fifo
1184 */
1185 u16 pio_mhf2 = 0;
1186 struct brcms_hardware *wlc_hw = wlc->hw;
1187 uint unit = wlc_hw->unit;
1188 struct wiphy *wiphy = wlc->wiphy;
1189
1190 /* name and offsets for dma_attach */
1191 snprintf(name, sizeof(name), "wl%d", unit);
1192
1193 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1194 int dma_attach_err = 0;
1195
1196 /*
1197 * FIFO 0
1198 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1199 * RX: RX_FIFO (RX data packets)
1200 */
1201 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
1202 (wme ? dmareg(wlc_hw, DMA_TX, 0) :
1203 NULL), dmareg(wlc_hw, DMA_RX, 0),
1204 (wme ? NTXD : 0), NRXD,
1205 RXBUFSZ, -1, NRXBUFPOST,
1206 BRCMS_HWRXOFF, &brcm_msg_level);
1207 dma_attach_err |= (NULL == wlc_hw->di[0]);
1208
1209 /*
1210 * FIFO 1
1211 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1212 * (legacy) TX_DATA_FIFO (TX data packets)
1213 * RX: UNUSED
1214 */
1215 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
1216 dmareg(wlc_hw, DMA_TX, 1), NULL,
1217 NTXD, 0, 0, -1, 0, 0,
1218 &brcm_msg_level);
1219 dma_attach_err |= (NULL == wlc_hw->di[1]);
1220
1221 /*
1222 * FIFO 2
1223 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1224 * RX: UNUSED
1225 */
1226 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
1227 dmareg(wlc_hw, DMA_TX, 2), NULL,
1228 NTXD, 0, 0, -1, 0, 0,
1229 &brcm_msg_level);
1230 dma_attach_err |= (NULL == wlc_hw->di[2]);
1231 /*
1232 * FIFO 3
1233 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1234 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1235 */
1236 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
1237 dmareg(wlc_hw, DMA_TX, 3),
1238 NULL, NTXD, 0, 0, -1,
1239 0, 0, &brcm_msg_level);
1240 dma_attach_err |= (NULL == wlc_hw->di[3]);
1241/* Cleaner to leave this as if with AP defined */
1242
1243 if (dma_attach_err) {
1244 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
1245 "\n", unit);
1246 return false;
1247 }
1248
1249 /* get pointer to dma engine tx flow control variable */
1250 for (i = 0; i < NFIFO; i++)
1251 if (wlc_hw->di[i])
1252 wlc_hw->txavail[i] =
1253 (uint *) dma_getvar(wlc_hw->di[i],
1254 "&txavail");
1255 }
1256
1257 /* initial ucode host flags */
1258 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1259
1260 return true;
1261}
1262
1263static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1264{
1265 uint j;
1266
1267 for (j = 0; j < NFIFO; j++) {
1268 if (wlc_hw->di[j]) {
1269 dma_detach(wlc_hw->di[j]);
1270 wlc_hw->di[j] = NULL;
1271 }
1272 }
1273}
1274
1275/*
1276 * Initialize brcms_c_info default values ...
1277 * may get overrides later in this function
1278 * BMAC_NOTES, move low out and resolve the dangling ones
1279 */
1280static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1281{
1282 struct brcms_c_info *wlc = wlc_hw->wlc;
1283
1284 /* set default sw macintmask value */
1285 wlc->defmacintmask = DEF_MACINTMASK;
1286
1287 /* various 802.11g modes */
1288 wlc_hw->shortslot = false;
1289
1290 wlc_hw->SFBL = RETRY_SHORT_FB;
1291 wlc_hw->LFBL = RETRY_LONG_FB;
1292
1293 /* default mac retry limits */
1294 wlc_hw->SRL = RETRY_SHORT_DEF;
1295 wlc_hw->LRL = RETRY_LONG_DEF;
1296 wlc_hw->chanspec = ch20mhz_chspec(1);
1297}
1298
1299static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1300{
1301 /* delay before first read of ucode state */
1302 udelay(40);
1303
1304 /* wait until ucode is no longer asleep */
1305 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1306 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1307}
1308
1309/* control chip clock to save power, enable dynamic clock or force fast clock */
1310static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
1311{
1312 if (wlc_hw->sih->cccaps & CC_CAP_PMU) {
1313 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1314 * on backplane, but mac core will still run on ALP(not HT) when
1315 * it enters powersave mode, which means the FCA bit may not be
1316 * set. Should wakeup mac if driver wants it to run on HT.
1317 */
1318
1319 if (wlc_hw->clk) {
1320 if (mode == CLK_FAST) {
1321 OR_REG(&wlc_hw->regs->clk_ctl_st,
1322 CCS_FORCEHT);
1323
1324 udelay(64);
1325
1326 SPINWAIT(((R_REG
1327 (&wlc_hw->regs->
1328 clk_ctl_st) & CCS_HTAVAIL) == 0),
1329 PMU_MAX_TRANSITION_DLY);
1330 WARN_ON(!(R_REG
1331 (&wlc_hw->regs->
1332 clk_ctl_st) & CCS_HTAVAIL));
1333 } else {
1334 if ((wlc_hw->sih->pmurev == 0) &&
1335 (R_REG
1336 (&wlc_hw->regs->
1337 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1338 SPINWAIT(((R_REG
1339 (&wlc_hw->regs->
1340 clk_ctl_st) & CCS_HTAVAIL)
1341 == 0),
1342 PMU_MAX_TRANSITION_DLY);
1343 AND_REG(&wlc_hw->regs->clk_ctl_st,
1344 ~CCS_FORCEHT);
1345 }
1346 }
1347 wlc_hw->forcefastclk = (mode == CLK_FAST);
1348 } else {
1349
1350 /* old chips w/o PMU, force HT through cc,
1351 * then use FCA to verify mac is running fast clock
1352 */
1353
1354 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1355
1356 /* check fast clock is available (if core is not in reset) */
1357 if (wlc_hw->forcefastclk && wlc_hw->clk)
1358 WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1359 SISF_FCLKA));
1360
1361 /*
1362 * keep the ucode wake bit on if forcefastclk is on since we
1363 * do not want ucode to put us back to slow clock when it dozes
1364 * for PM mode. Code below matches the wake override bit with
1365 * current forcefastclk state. Only setting bit in wake_override
1366 * instead of waking ucode immediately since old code had this
1367 * behavior. Older code set wlc->forcefastclk but only had the
1368 * wake happen if the wakup_ucode work (protected by an up
1369 * check) was executed just below.
1370 */
1371 if (wlc_hw->forcefastclk)
1372 mboolset(wlc_hw->wake_override,
1373 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1374 else
1375 mboolclr(wlc_hw->wake_override,
1376 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1377 }
1378}
1379
1380/* set or clear ucode host flag bits
1381 * it has an optimization for no-change write
1382 * it only writes through shared memory when the core has clock;
1383 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1384 *
1385 *
1386 * bands values are: BRCM_BAND_AUTO <--- Current band only
1387 * BRCM_BAND_5G <--- 5G band only
1388 * BRCM_BAND_2G <--- 2G band only
1389 * BRCM_BAND_ALL <--- All bands
1390 */
1391void
1392brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1393 int bands)
1394{
1395 u16 save;
1396 u16 addr[MHFMAX] = {
1397 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1398 M_HOST_FLAGS5
1399 };
1400 struct brcms_hw_band *band;
1401
1402 if ((val & ~mask) || idx >= MHFMAX)
1403 return; /* error condition */
1404
1405 switch (bands) {
1406 /* Current band only or all bands,
1407 * then set the band to current band
1408 */
1409 case BRCM_BAND_AUTO:
1410 case BRCM_BAND_ALL:
1411 band = wlc_hw->band;
1412 break;
1413 case BRCM_BAND_5G:
1414 band = wlc_hw->bandstate[BAND_5G_INDEX];
1415 break;
1416 case BRCM_BAND_2G:
1417 band = wlc_hw->bandstate[BAND_2G_INDEX];
1418 break;
1419 default:
1420 band = NULL; /* error condition */
1421 }
1422
1423 if (band) {
1424 save = band->mhfs[idx];
1425 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1426
1427 /* optimization: only write through if changed, and
1428 * changed band is the current band
1429 */
1430 if (wlc_hw->clk && (band->mhfs[idx] != save)
1431 && (band == wlc_hw->band))
1432 brcms_b_write_shm(wlc_hw, addr[idx],
1433 (u16) band->mhfs[idx]);
1434 }
1435
1436 if (bands == BRCM_BAND_ALL) {
1437 wlc_hw->bandstate[0]->mhfs[idx] =
1438 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1439 wlc_hw->bandstate[1]->mhfs[idx] =
1440 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1441 }
1442}
1443
1444/* set the maccontrol register to desired reset state and
1445 * initialize the sw cache of the register
1446 */
1447static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1448{
1449 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1450 wlc_hw->maccontrol = 0;
1451 wlc_hw->suspended_fifos = 0;
1452 wlc_hw->wake_override = 0;
1453 wlc_hw->mute_override = 0;
1454 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1455}
1456
1457/*
1458 * write the software state of maccontrol and
1459 * overrides to the maccontrol register
1460 */
1461static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1462{
1463 u32 maccontrol = wlc_hw->maccontrol;
1464
1465 /* OR in the wake bit if overridden */
1466 if (wlc_hw->wake_override)
1467 maccontrol |= MCTL_WAKE;
1468
1469 /* set AP and INFRA bits for mute if needed */
1470 if (wlc_hw->mute_override) {
1471 maccontrol &= ~(MCTL_AP);
1472 maccontrol |= MCTL_INFRA;
1473 }
1474
1475 W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1476}
1477
1478/* set or clear maccontrol bits */
1479void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1480{
1481 u32 maccontrol;
1482 u32 new_maccontrol;
1483
1484 if (val & ~mask)
1485 return; /* error condition */
1486 maccontrol = wlc_hw->maccontrol;
1487 new_maccontrol = (maccontrol & ~mask) | val;
1488
1489 /* if the new maccontrol value is the same as the old, nothing to do */
1490 if (new_maccontrol == maccontrol)
1491 return;
1492
1493 /* something changed, cache the new value */
1494 wlc_hw->maccontrol = new_maccontrol;
1495
1496 /* write the new values with overrides applied */
1497 brcms_c_mctrl_write(wlc_hw);
1498}
1499
1500void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1501 u32 override_bit)
1502{
1503 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1504 mboolset(wlc_hw->wake_override, override_bit);
1505 return;
1506 }
1507
1508 mboolset(wlc_hw->wake_override, override_bit);
1509
1510 brcms_c_mctrl_write(wlc_hw);
1511 brcms_b_wait_for_wake(wlc_hw);
1512}
1513
1514void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1515 u32 override_bit)
1516{
1517 mboolclr(wlc_hw->wake_override, override_bit);
1518
1519 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1520 return;
1521
1522 brcms_c_mctrl_write(wlc_hw);
1523}
1524
1525/* When driver needs ucode to stop beaconing, it has to make sure that
1526 * MCTL_AP is clear and MCTL_INFRA is set
1527 * Mode MCTL_AP MCTL_INFRA
1528 * AP 1 1
1529 * STA 0 1 <--- This will ensure no beacons
1530 * IBSS 0 0
1531 */
1532static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1533{
1534 wlc_hw->mute_override = 1;
1535
1536 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1537 * override, then there is no change to write
1538 */
1539 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1540 return;
1541
1542 brcms_c_mctrl_write(wlc_hw);
1543}
1544
1545/* Clear the override on AP and INFRA bits */
1546static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1547{
1548 if (wlc_hw->mute_override == 0)
1549 return;
1550
1551 wlc_hw->mute_override = 0;
1552
1553 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1554 * override, then there is no change to write
1555 */
1556 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1557 return;
1558
1559 brcms_c_mctrl_write(wlc_hw);
1560}
1561
1562/*
1563 * Write a MAC address to the given match reg offset in the RXE match engine.
1564 */
1565static void
1566brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1567 const u8 *addr)
1568{
1569 struct d11regs __iomem *regs;
1570 u16 mac_l;
1571 u16 mac_m;
1572 u16 mac_h;
1573
1574 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1575 wlc_hw->unit);
1576
1577 regs = wlc_hw->regs;
1578 mac_l = addr[0] | (addr[1] << 8);
1579 mac_m = addr[2] | (addr[3] << 8);
1580 mac_h = addr[4] | (addr[5] << 8);
1581
1582 /* enter the MAC addr into the RXE match registers */
1583 W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1584 W_REG(&regs->rcm_mat_data, mac_l);
1585 W_REG(&regs->rcm_mat_data, mac_m);
1586 W_REG(&regs->rcm_mat_data, mac_h);
1587
1588}
1589
1590void
1591brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1592 void *buf)
1593{
1594 struct d11regs __iomem *regs;
1595 u32 word;
1596 __le32 word_le;
1597 __be32 word_be;
1598 bool be_bit;
1599 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1600
1601 regs = wlc_hw->regs;
1602 W_REG(&regs->tplatewrptr, offset);
1603
1604 /* if MCTL_BIGEND bit set in mac control register,
1605 * the chip swaps data in fifo, as well as data in
1606 * template ram
1607 */
1608 be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1609
1610 while (len > 0) {
1611 memcpy(&word, buf, sizeof(u32));
1612
1613 if (be_bit) {
1614 word_be = cpu_to_be32(word);
1615 word = *(u32 *)&word_be;
1616 } else {
1617 word_le = cpu_to_le32(word);
1618 word = *(u32 *)&word_le;
1619 }
1620
1621 W_REG(&regs->tplatewrdata, word);
1622
1623 buf = (u8 *) buf + sizeof(u32);
1624 len -= sizeof(u32);
1625 }
1626}
1627
1628static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1629{
1630 wlc_hw->band->CWmin = newmin;
1631
1632 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1633 (void)R_REG(&wlc_hw->regs->objaddr);
1634 W_REG(&wlc_hw->regs->objdata, newmin);
1635}
1636
1637static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1638{
1639 wlc_hw->band->CWmax = newmax;
1640
1641 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1642 (void)R_REG(&wlc_hw->regs->objaddr);
1643 W_REG(&wlc_hw->regs->objdata, newmax);
1644}
1645
1646void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1647{
1648 bool fastclk;
1649
1650 /* request FAST clock if not on */
1651 fastclk = wlc_hw->forcefastclk;
1652 if (!fastclk)
1653 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1654
1655 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1656
1657 brcms_b_phy_reset(wlc_hw);
1658 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1659
1660 /* restore the clk */
1661 if (!fastclk)
1662 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1663}
1664
1665static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1666{
1667 u16 v;
1668 struct brcms_c_info *wlc = wlc_hw->wlc;
1669 /* update SYNTHPU_DLY */
1670
1671 if (BRCMS_ISLCNPHY(wlc->band))
1672 v = SYNTHPU_DLY_LPPHY_US;
1673 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1674 v = SYNTHPU_DLY_NPHY_US;
1675 else
1676 v = SYNTHPU_DLY_BPHY_US;
1677
1678 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1679}
1680
1681static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1682{
1683 u16 phyctl;
1684 u16 phytxant = wlc_hw->bmac_phytxant;
1685 u16 mask = PHY_TXC_ANT_MASK;
1686
1687 /* set the Probe Response frame phy control word */
1688 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1689 phyctl = (phyctl & ~mask) | phytxant;
1690 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1691
1692 /* set the Response (ACK/CTS) frame phy control word */
1693 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1694 phyctl = (phyctl & ~mask) | phytxant;
1695 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1696}
1697
1698static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1699 u8 rate)
1700{
1701 uint i;
1702 u8 plcp_rate = 0;
1703 struct plcp_signal_rate_lookup {
1704 u8 rate;
1705 u8 signal_rate;
1706 };
1707 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1708 const struct plcp_signal_rate_lookup rate_lookup[] = {
1709 {BRCM_RATE_6M, 0xB},
1710 {BRCM_RATE_9M, 0xF},
1711 {BRCM_RATE_12M, 0xA},
1712 {BRCM_RATE_18M, 0xE},
1713 {BRCM_RATE_24M, 0x9},
1714 {BRCM_RATE_36M, 0xD},
1715 {BRCM_RATE_48M, 0x8},
1716 {BRCM_RATE_54M, 0xC}
1717 };
1718
1719 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1720 if (rate == rate_lookup[i].rate) {
1721 plcp_rate = rate_lookup[i].signal_rate;
1722 break;
1723 }
1724 }
1725
1726 /* Find the SHM pointer to the rate table entry by looking in the
1727 * Direct-map Table
1728 */
1729 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1730}
1731
1732static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1733{
1734 u8 rate;
1735 u8 rates[8] = {
1736 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1737 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1738 };
1739 u16 entry_ptr;
1740 u16 pctl1;
1741 uint i;
1742
1743 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1744 return;
1745
1746 /* walk the phy rate table and update the entries */
1747 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1748 rate = rates[i];
1749
1750 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1751
1752 /* read the SHM Rate Table entry OFDM PCTL1 values */
1753 pctl1 =
1754 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1755
1756 /* modify the value */
1757 pctl1 &= ~PHY_TXC1_MODE_MASK;
1758 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1759
1760 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1761 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1762 pctl1);
1763 }
1764}
1765
1766/* band-specific init */
1767static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1768{
1769 struct brcms_hardware *wlc_hw = wlc->hw;
1770
1771 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1772 wlc_hw->band->bandunit);
1773
1774 brcms_c_ucode_bsinit(wlc_hw);
1775
1776 wlc_phy_init(wlc_hw->band->pi, chanspec);
1777
1778 brcms_c_ucode_txant_set(wlc_hw);
1779
1780 /*
1781 * cwmin is band-specific, update hardware
1782 * with value for current band
1783 */
1784 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1785 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1786
1787 brcms_b_update_slot_timing(wlc_hw,
1788 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1789 true : wlc_hw->shortslot);
1790
1791 /* write phytype and phyvers */
1792 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1793 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1794
1795 /*
1796 * initialize the txphyctl1 rate table since
1797 * shmem is shared between bands
1798 */
1799 brcms_upd_ofdm_pctl1_table(wlc_hw);
1800
1801 brcms_b_upd_synthpu(wlc_hw);
1802}
1803
1804/* Perform a soft reset of the PHY PLL */
1805void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1806{
1807 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1808
1809 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1810 offsetof(struct chipcregs, chipcontrol_addr), ~0, 0);
1811 udelay(1);
1812 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1813 offsetof(struct chipcregs, chipcontrol_data), 0x4, 0);
1814 udelay(1);
1815 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1816 offsetof(struct chipcregs, chipcontrol_data), 0x4, 4);
1817 udelay(1);
1818 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1819 offsetof(struct chipcregs, chipcontrol_data), 0x4, 0);
1820 udelay(1);
1821}
1822
1823/* light way to turn on phy clock without reset for NPHY only
1824 * refer to brcms_b_core_phy_clk for full version
1825 */
1826void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1827{
1828 /* support(necessary for NPHY and HYPHY) only */
1829 if (!BRCMS_ISNPHY(wlc_hw->band))
1830 return;
1831
1832 if (ON == clk)
1833 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1834 else
1835 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1836
1837}
1838
1839void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1840{
1841 if (ON == clk)
1842 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1843 else
1844 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1845}
1846
1847void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1848{
1849 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1850 u32 phy_bw_clkbits;
1851 bool phy_in_reset = false;
1852
1853 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1854
1855 if (pih == NULL)
1856 return;
1857
1858 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1859
1860 /* Specific reset sequence required for NPHY rev 3 and 4 */
1861 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1862 NREV_LE(wlc_hw->band->phyrev, 4)) {
1863 /* Set the PHY bandwidth */
1864 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1865
1866 udelay(1);
1867
1868 /* Perform a soft reset of the PHY PLL */
1869 brcms_b_core_phypll_reset(wlc_hw);
1870
1871 /* reset the PHY */
1872 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1873 (SICF_PRST | SICF_PCLKE));
1874 phy_in_reset = true;
1875 } else {
1876 ai_core_cflags(wlc_hw->sih,
1877 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1878 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1879 }
1880
1881 udelay(2);
1882 brcms_b_core_phy_clk(wlc_hw, ON);
1883
1884 if (pih)
1885 wlc_phy_anacore(pih, ON);
1886}
1887
1888/* switch to and initialize new band */
1889static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1890 u16 chanspec) {
1891 struct brcms_c_info *wlc = wlc_hw->wlc;
1892 u32 macintmask;
1893
1894 /* Enable the d11 core before accessing it */
1895 if (!ai_iscoreup(wlc_hw->sih)) {
1896 ai_core_reset(wlc_hw->sih, 0, 0);
1897 brcms_c_mctrl_reset(wlc_hw);
1898 }
1899
1900 macintmask = brcms_c_setband_inact(wlc, bandunit);
1901
1902 if (!wlc_hw->up)
1903 return;
1904
1905 brcms_b_core_phy_clk(wlc_hw, ON);
1906
1907 /* band-specific initializations */
1908 brcms_b_bsinit(wlc, chanspec);
1909
1910 /*
1911 * If there are any pending software interrupt bits,
1912 * then replace these with a harmless nonzero value
1913 * so brcms_c_dpc() will re-enable interrupts when done.
1914 */
1915 if (wlc->macintstatus)
1916 wlc->macintstatus = MI_DMAINT;
1917
1918 /* restore macintmask */
1919 brcms_intrsrestore(wlc->wl, macintmask);
1920
1921 /* ucode should still be suspended.. */
1922 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1923}
1924
1925/* low-level band switch utility routine */
1926void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
1927{
1928 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1929 bandunit);
1930
1931 wlc_hw->band = wlc_hw->bandstate[bandunit];
1932
1933 /*
1934 * BMAC_NOTE:
1935 * until we eliminate need for wlc->band refs in low level code
1936 */
1937 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1938
1939 /* set gmode core flag */
1940 if (wlc_hw->sbclk && !wlc_hw->noreset)
1941 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1942 ((bandunit == 0) ? SICF_GMODE : 0));
1943}
1944
1945static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1946{
1947
1948 /* reject unsupported corerev */
1949 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1950 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1951 wlc_hw->corerev);
1952 return false;
1953 }
1954
1955 return true;
1956}
1957
1958/* Validate some board info parameters */
1959static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1960{
1961 uint boardrev = wlc_hw->boardrev;
1962
1963 /* 4 bits each for board type, major, minor, and tiny version */
1964 uint brt = (boardrev & 0xf000) >> 12;
1965 uint b0 = (boardrev & 0xf00) >> 8;
1966 uint b1 = (boardrev & 0xf0) >> 4;
1967 uint b2 = boardrev & 0xf;
1968
1969 /* voards from other vendors are always considered valid */
1970 if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1971 return true;
1972
1973 /* do some boardrev sanity checks when boardvendor is Broadcom */
1974 if (boardrev == 0)
1975 return false;
1976
1977 if (boardrev <= 0xff)
1978 return true;
1979
1980 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1981 || (b2 > 9))
1982 return false;
1983
1984 return true;
1985}
1986
1987static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw)
1988{
1989 enum brcms_srom_id var_id = BRCMS_SROM_MACADDR;
1990 char *macaddr;
1991
1992 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1993 macaddr = getvar(wlc_hw->sih, var_id);
1994 if (macaddr != NULL)
1995 return macaddr;
1996
1997 if (wlc_hw->_nbands > 1)
1998 var_id = BRCMS_SROM_ET1MACADDR;
1999 else
2000 var_id = BRCMS_SROM_IL0MACADDR;
2001
2002 macaddr = getvar(wlc_hw->sih, var_id);
2003 if (macaddr == NULL)
2004 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
2005 "getvar(%d) not found\n", wlc_hw->unit, var_id);
2006
2007 return macaddr;
2008}
2009
2010/* power both the pll and external oscillator on/off */
2011static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
2012{
2013 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
2014
2015 /*
2016 * dont power down if plldown is false or
2017 * we must poll hw radio disable
2018 */
2019 if (!want && wlc_hw->pllreq)
2020 return;
2021
2022 if (wlc_hw->sih)
2023 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
2024
2025 wlc_hw->sbclk = want;
2026 if (!wlc_hw->sbclk) {
2027 wlc_hw->clk = false;
2028 if (wlc_hw->band && wlc_hw->band->pi)
2029 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2030 }
2031}
2032
2033/*
2034 * Return true if radio is disabled, otherwise false.
2035 * hw radio disable signal is an external pin, users activate it asynchronously
2036 * this function could be called when driver is down and w/o clock
2037 * it operates on different registers depending on corerev and boardflag.
2038 */
2039static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
2040{
2041 bool v, clk, xtal;
2042 u32 resetbits = 0, flags = 0;
2043
2044 xtal = wlc_hw->sbclk;
2045 if (!xtal)
2046 brcms_b_xtal(wlc_hw, ON);
2047
2048 /* may need to take core out of reset first */
2049 clk = wlc_hw->clk;
2050 if (!clk) {
2051 /*
2052 * mac no longer enables phyclk automatically when driver
2053 * accesses phyreg throughput mac. This can be skipped since
2054 * only mac reg is accessed below
2055 */
2056 flags |= SICF_PCLKE;
2057
2058 /*
2059 * AI chip doesn't restore bar0win2 on
2060 * hibernation/resume, need sw fixup
2061 */
2062 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2063 (wlc_hw->sih->chip == BCM43225_CHIP_ID))
2064 wlc_hw->regs = (struct d11regs __iomem *)
2065 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
2066 ai_core_reset(wlc_hw->sih, flags, resetbits);
2067 brcms_c_mctrl_reset(wlc_hw);
2068 }
2069
2070 v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2071
2072 /* put core back into reset */
2073 if (!clk)
2074 ai_core_disable(wlc_hw->sih, 0);
2075
2076 if (!xtal)
2077 brcms_b_xtal(wlc_hw, OFF);
2078
2079 return v;
2080}
2081
2082static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
2083{
2084 struct dma_pub *di = wlc_hw->di[fifo];
2085 return dma_rxreset(di);
2086}
2087
2088/* d11 core reset
2089 * ensure fask clock during reset
2090 * reset dma
2091 * reset d11(out of reset)
2092 * reset phy(out of reset)
2093 * clear software macintstatus for fresh new start
2094 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2095 */
2096void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2097{
2098 struct d11regs __iomem *regs;
2099 uint i;
2100 bool fastclk;
2101 u32 resetbits = 0;
2102
2103 if (flags == BRCMS_USE_COREFLAGS)
2104 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2105
2106 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2107
2108 regs = wlc_hw->regs;
2109
2110 /* request FAST clock if not on */
2111 fastclk = wlc_hw->forcefastclk;
2112 if (!fastclk)
2113 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2114
2115 /* reset the dma engines except first time thru */
2116 if (ai_iscoreup(wlc_hw->sih)) {
2117 for (i = 0; i < NFIFO; i++)
2118 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2119 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2120 "dma_txreset[%d]: cannot stop dma\n",
2121 wlc_hw->unit, __func__, i);
2122
2123 if ((wlc_hw->di[RX_FIFO])
2124 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2125 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2126 "[%d]: cannot stop dma\n",
2127 wlc_hw->unit, __func__, RX_FIFO);
2128 }
2129 /* if noreset, just stop the psm and return */
2130 if (wlc_hw->noreset) {
2131 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2132 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2133 return;
2134 }
2135
2136 /*
2137 * mac no longer enables phyclk automatically when driver accesses
2138 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2139 * band->pi is invalid. need to enable PHY CLK
2140 */
2141 flags |= SICF_PCLKE;
2142
2143 /*
2144 * reset the core
2145 * In chips with PMU, the fastclk request goes through d11 core
2146 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2147 *
2148 * This adds some delay and we can optimize it by also requesting
2149 * fastclk through chipcommon during this period if necessary. But
2150 * that has to work coordinate with other driver like mips/arm since
2151 * they may touch chipcommon as well.
2152 */
2153 wlc_hw->clk = false;
2154 ai_core_reset(wlc_hw->sih, flags, resetbits);
2155 wlc_hw->clk = true;
2156 if (wlc_hw->band && wlc_hw->band->pi)
2157 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2158
2159 brcms_c_mctrl_reset(wlc_hw);
2160
2161 if (wlc_hw->sih->cccaps & CC_CAP_PMU)
2162 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2163
2164 brcms_b_phy_reset(wlc_hw);
2165
2166 /* turn on PHY_PLL */
2167 brcms_b_core_phypll_ctl(wlc_hw, true);
2168
2169 /* clear sw intstatus */
2170 wlc_hw->wlc->macintstatus = 0;
2171
2172 /* restore the clk setting */
2173 if (!fastclk)
2174 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2175}
2176
2177/* txfifo sizes needs to be modified(increased) since the newer cores
2178 * have more memory.
2179 */
2180static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2181{
2182 struct d11regs __iomem *regs = wlc_hw->regs;
2183 u16 fifo_nu;
2184 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2185 u16 txfifo_def, txfifo_def1;
2186 u16 txfifo_cmd;
2187
2188 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2189 txfifo_startblk = TXFIFO_START_BLK;
2190
2191 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2192 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2193
2194 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2195 txfifo_def = (txfifo_startblk & 0xff) |
2196 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2197 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2198 ((((txfifo_endblk -
2199 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2200 txfifo_cmd =
2201 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2202
2203 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2204 W_REG(&regs->xmtfifodef, txfifo_def);
2205 W_REG(&regs->xmtfifodef1, txfifo_def1);
2206
2207 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2208
2209 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2210 }
2211 /*
2212 * need to propagate to shm location to be in sync since ucode/hw won't
2213 * do this
2214 */
2215 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2216 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2217 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2218 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2219 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2220 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2221 xmtfifo_sz[TX_AC_BK_FIFO]));
2222 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2223 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2224 xmtfifo_sz[TX_BCMC_FIFO]));
2225}
2226
2227/* This function is used for changing the tsf frac register
2228 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2229 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2230 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2231 * HTPHY Formula is 2^26/freq(MHz) e.g.
2232 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2233 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2234 * For spuron: 123MHz -> 2^26/123 = 545600.5
2235 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2236 * For spur off: 120MHz -> 2^26/120 = 559240.5
2237 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2238 */
2239
2240void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2241{
2242 struct d11regs __iomem *regs = wlc_hw->regs;
2243
2244 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2245 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2246 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2247 W_REG(&regs->tsf_clk_frac_l, 0x2082);
2248 W_REG(&regs->tsf_clk_frac_h, 0x8);
2249 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2250 W_REG(&regs->tsf_clk_frac_l, 0x5341);
2251 W_REG(&regs->tsf_clk_frac_h, 0x8);
2252 } else { /* 120Mhz */
2253 W_REG(&regs->tsf_clk_frac_l, 0x8889);
2254 W_REG(&regs->tsf_clk_frac_h, 0x8);
2255 }
2256 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2257 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2258 W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2259 W_REG(&regs->tsf_clk_frac_h, 0xC);
2260 } else { /* 80Mhz */
2261 W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2262 W_REG(&regs->tsf_clk_frac_h, 0xC);
2263 }
2264 }
2265}
2266
2267/* Initialize GPIOs that are controlled by D11 core */
2268static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2269{
2270 struct brcms_hardware *wlc_hw = wlc->hw;
2271 struct d11regs __iomem *regs;
2272 u32 gc, gm;
2273
2274 regs = wlc_hw->regs;
2275
2276 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2277 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2278
2279 /*
2280 * Common GPIO setup:
2281 * G0 = LED 0 = WLAN Activity
2282 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2283 * G2 = LED 2 = WLAN 5 GHz Radio State
2284 * G4 = radio disable input (HI enabled, LO disabled)
2285 */
2286
2287 gc = gm = 0;
2288
2289 /* Allocate GPIOs for mimo antenna diversity feature */
2290 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2291 /* Enable antenna diversity, use 2x3 mode */
2292 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2293 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2294 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2295 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2296
2297 /* init superswitch control */
2298 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2299
2300 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2301 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2302 /*
2303 * The board itself is powered by these GPIOs
2304 * (when not sending pattern) so set them high
2305 */
2306 OR_REG(&regs->psm_gpio_oe,
2307 (BOARD_GPIO_12 | BOARD_GPIO_13));
2308 OR_REG(&regs->psm_gpio_out,
2309 (BOARD_GPIO_12 | BOARD_GPIO_13));
2310
2311 /* Enable antenna diversity, use 2x4 mode */
2312 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2313 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2314 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2315 BRCM_BAND_ALL);
2316
2317 /* Configure the desired clock to be 4Mhz */
2318 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2319 ANTSEL_CLKDIV_4MHZ);
2320 }
2321
2322 /*
2323 * gpio 9 controls the PA. ucode is responsible
2324 * for wiggling out and oe
2325 */
2326 if (wlc_hw->boardflags & BFL_PACTRL)
2327 gm |= gc |= BOARD_GPIO_PACTRL;
2328
2329 /* apply to gpiocontrol register */
2330 ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2331}
2332
2333static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2334 const __le32 ucode[], const size_t nbytes)
2335{
2336 struct d11regs __iomem *regs = wlc_hw->regs;
2337 uint i;
2338 uint count;
2339
2340 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2341
2342 count = (nbytes / sizeof(u32));
2343
2344 W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2345 (void)R_REG(&regs->objaddr);
2346 for (i = 0; i < count; i++)
2347 W_REG(&regs->objdata, le32_to_cpu(ucode[i]));
2348
2349}
2350
2351static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2352{
2353 struct brcms_c_info *wlc;
2354 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2355
2356 wlc = wlc_hw->wlc;
2357
2358 if (wlc_hw->ucode_loaded)
2359 return;
2360
2361 if (D11REV_IS(wlc_hw->corerev, 23)) {
2362 if (BRCMS_ISNPHY(wlc_hw->band)) {
2363 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2364 ucode->bcm43xx_16_mimosz);
2365 wlc_hw->ucode_loaded = true;
2366 } else
2367 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2368 "corerev %d\n",
2369 __func__, wlc_hw->unit, wlc_hw->corerev);
2370 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2371 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2372 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2373 ucode->bcm43xx_24_lcnsz);
2374 wlc_hw->ucode_loaded = true;
2375 } else {
2376 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2377 "corerev %d\n",
2378 __func__, wlc_hw->unit, wlc_hw->corerev);
2379 }
2380 }
2381}
2382
2383void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2384{
2385 /* update sw state */
2386 wlc_hw->bmac_phytxant = phytxant;
2387
2388 /* push to ucode if up */
2389 if (!wlc_hw->up)
2390 return;
2391 brcms_c_ucode_txant_set(wlc_hw);
2392
2393}
2394
2395u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2396{
2397 return (u16) wlc_hw->wlc->stf->txant;
2398}
2399
2400void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2401{
2402 wlc_hw->antsel_type = antsel_type;
2403
2404 /* Update the antsel type for phy module to use */
2405 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2406}
2407
2408static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2409{
2410 bool fatal = false;
2411 uint unit;
2412 uint intstatus, idx;
2413 struct d11regs __iomem *regs = wlc_hw->regs;
2414 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2415
2416 unit = wlc_hw->unit;
2417
2418 for (idx = 0; idx < NFIFO; idx++) {
2419 /* read intstatus register and ignore any non-error bits */
2420 intstatus =
2421 R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2422 if (!intstatus)
2423 continue;
2424
2425 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2426 unit, idx, intstatus);
2427
2428 if (intstatus & I_RO) {
2429 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2430 "overflow\n", unit, idx);
2431 fatal = true;
2432 }
2433
2434 if (intstatus & I_PC) {
2435 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2436 unit, idx);
2437 fatal = true;
2438 }
2439
2440 if (intstatus & I_PD) {
2441 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2442 idx);
2443 fatal = true;
2444 }
2445
2446 if (intstatus & I_DE) {
2447 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2448 "error\n", unit, idx);
2449 fatal = true;
2450 }
2451
2452 if (intstatus & I_RU)
2453 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2454 "underflow\n", idx, unit);
2455
2456 if (intstatus & I_XU) {
2457 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2458 "underflow\n", idx, unit);
2459 fatal = true;
2460 }
2461
2462 if (fatal) {
2463 brcms_c_fatal_error(wlc_hw->wlc); /* big hammer */
2464 break;
2465 } else
2466 W_REG(&regs->intctrlregs[idx].intstatus,
2467 intstatus);
2468 }
2469}
2470
2471void brcms_c_intrson(struct brcms_c_info *wlc)
2472{
2473 struct brcms_hardware *wlc_hw = wlc->hw;
2474 wlc->macintmask = wlc->defmacintmask;
2475 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2476}
2477
2478/*
2479 * callback for siutils.c, which has only wlc handler, no wl they both check
2480 * up, not only because there is no need to off/restore d11 interrupt but also
2481 * because per-port code may require sync with valid interrupt.
2482 */
2483static u32 brcms_c_wlintrsoff(struct brcms_c_info *wlc)
2484{
2485 if (!wlc->hw->up)
2486 return 0;
2487
2488 return brcms_intrsoff(wlc->wl);
2489}
2490
2491static void brcms_c_wlintrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2492{
2493 if (!wlc->hw->up)
2494 return;
2495
2496 brcms_intrsrestore(wlc->wl, macintmask);
2497}
2498
2499u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2500{
2501 struct brcms_hardware *wlc_hw = wlc->hw;
2502 u32 macintmask;
2503
2504 if (!wlc_hw->clk)
2505 return 0;
2506
2507 macintmask = wlc->macintmask; /* isr can still happen */
2508
2509 W_REG(&wlc_hw->regs->macintmask, 0);
2510 (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2511 udelay(1); /* ensure int line is no longer driven */
2512 wlc->macintmask = 0;
2513
2514 /* return previous macintmask; resolve race between us and our isr */
2515 return wlc->macintstatus ? 0 : macintmask;
2516}
2517
2518void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2519{
2520 struct brcms_hardware *wlc_hw = wlc->hw;
2521 if (!wlc_hw->clk)
2522 return;
2523
2524 wlc->macintmask = macintmask;
2525 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2526}
2527
2528static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2529 uint tx_fifo)
2530{
2531 u8 fifo = 1 << tx_fifo;
2532
2533 /* Two clients of this code, 11h Quiet period and scanning. */
2534
2535 /* only suspend if not already suspended */
2536 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2537 return;
2538
2539 /* force the core awake only if not already */
2540 if (wlc_hw->suspended_fifos == 0)
2541 brcms_c_ucode_wake_override_set(wlc_hw,
2542 BRCMS_WAKE_OVERRIDE_TXFIFO);
2543
2544 wlc_hw->suspended_fifos |= fifo;
2545
2546 if (wlc_hw->di[tx_fifo]) {
2547 /*
2548 * Suspending AMPDU transmissions in the middle can cause
2549 * underflow which may result in mismatch between ucode and
2550 * driver so suspend the mac before suspending the FIFO
2551 */
2552 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2553 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2554
2555 dma_txsuspend(wlc_hw->di[tx_fifo]);
2556
2557 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2558 brcms_c_enable_mac(wlc_hw->wlc);
2559 }
2560}
2561
2562static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2563 uint tx_fifo)
2564{
2565 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2566 * but need to be done here for PIO otherwise the watchdog will catch
2567 * the inconsistency and fire
2568 */
2569 /* Two clients of this code, 11h Quiet period and scanning. */
2570 if (wlc_hw->di[tx_fifo])
2571 dma_txresume(wlc_hw->di[tx_fifo]);
2572
2573 /* allow core to sleep again */
2574 if (wlc_hw->suspended_fifos == 0)
2575 return;
2576 else {
2577 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2578 if (wlc_hw->suspended_fifos == 0)
2579 brcms_c_ucode_wake_override_clear(wlc_hw,
2580 BRCMS_WAKE_OVERRIDE_TXFIFO);
2581 }
2582}
2583
2584static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool on, u32 flags)
2585{
2586 const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2587
2588 if (on) {
2589 /* suspend tx fifos */
2590 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2591 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2592 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2593 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2594
2595 /* zero the address match register so we do not send ACKs */
2596 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2597 null_ether_addr);
2598 } else {
2599 /* resume tx fifos */
2600 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2601 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2602 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2603 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2604
2605 /* Restore address */
2606 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2607 wlc_hw->etheraddr);
2608 }
2609
2610 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2611
2612 if (on)
2613 brcms_c_ucode_mute_override_set(wlc_hw);
2614 else
2615 brcms_c_ucode_mute_override_clear(wlc_hw);
2616}
2617
2618/*
2619 * Read and clear macintmask and macintstatus and intstatus registers.
2620 * This routine should be called with interrupts off
2621 * Return:
2622 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2623 * 0 if the interrupt is not for us, or we are in some special cases;
2624 * device interrupt status bits otherwise.
2625 */
2626static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2627{
2628 struct brcms_hardware *wlc_hw = wlc->hw;
2629 struct d11regs __iomem *regs = wlc_hw->regs;
2630 u32 macintstatus;
2631
2632 /* macintstatus includes a DMA interrupt summary bit */
2633 macintstatus = R_REG(&regs->macintstatus);
2634
2635 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2636 macintstatus);
2637
2638 /* detect cardbus removed, in power down(suspend) and in reset */
2639 if (brcms_deviceremoved(wlc))
2640 return -1;
2641
2642 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2643 * handle that case here.
2644 */
2645 if (macintstatus == 0xffffffff)
2646 return 0;
2647
2648 /* defer unsolicited interrupts */
2649 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2650
2651 /* if not for us */
2652 if (macintstatus == 0)
2653 return 0;
2654
2655 /* interrupts are already turned off for CFE build
2656 * Caution: For CFE Turning off the interrupts again has some undesired
2657 * consequences
2658 */
2659 /* turn off the interrupts */
2660 W_REG(&regs->macintmask, 0);
2661 (void)R_REG(&regs->macintmask); /* sync readback */
2662 wlc->macintmask = 0;
2663
2664 /* clear device interrupts */
2665 W_REG(&regs->macintstatus, macintstatus);
2666
2667 /* MI_DMAINT is indication of non-zero intstatus */
2668 if (macintstatus & MI_DMAINT)
2669 /*
2670 * only fifo interrupt enabled is I_RI in
2671 * RX_FIFO. If MI_DMAINT is set, assume it
2672 * is set and clear the interrupt.
2673 */
2674 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
2675 DEF_RXINTMASK);
2676
2677 return macintstatus;
2678}
2679
2680/* Update wlc->macintstatus and wlc->intstatus[]. */
2681/* Return true if they are updated successfully. false otherwise */
2682bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2683{
2684 u32 macintstatus;
2685
2686 /* read and clear macintstatus and intstatus registers */
2687 macintstatus = wlc_intstatus(wlc, false);
2688
2689 /* device is removed */
2690 if (macintstatus == 0xffffffff)
2691 return false;
2692
2693 /* update interrupt status in software */
2694 wlc->macintstatus |= macintstatus;
2695
2696 return true;
2697}
2698
2699/*
2700 * First-level interrupt processing.
2701 * Return true if this was our interrupt, false otherwise.
2702 * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2703 * false otherwise.
2704 */
2705bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
2706{
2707 struct brcms_hardware *wlc_hw = wlc->hw;
2708 u32 macintstatus;
2709
2710 *wantdpc = false;
2711
2712 if (!wlc_hw->up || !wlc->macintmask)
2713 return false;
2714
2715 /* read and clear macintstatus and intstatus registers */
2716 macintstatus = wlc_intstatus(wlc, true);
2717
2718 if (macintstatus == 0xffffffff)
2719 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2720 " path\n");
2721
2722 /* it is not for us */
2723 if (macintstatus == 0)
2724 return false;
2725
2726 *wantdpc = true;
2727
2728 /* save interrupt status bits */
2729 wlc->macintstatus = macintstatus;
2730
2731 return true;
2732
2733}
2734
2735void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2736{
2737 struct brcms_hardware *wlc_hw = wlc->hw;
2738 struct d11regs __iomem *regs = wlc_hw->regs;
2739 u32 mc, mi;
2740 struct wiphy *wiphy = wlc->wiphy;
2741
2742 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2743 wlc_hw->band->bandunit);
2744
2745 /*
2746 * Track overlapping suspend requests
2747 */
2748 wlc_hw->mac_suspend_depth++;
2749 if (wlc_hw->mac_suspend_depth > 1)
2750 return;
2751
2752 /* force the core awake */
2753 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2754
2755 mc = R_REG(&regs->maccontrol);
2756
2757 if (mc == 0xffffffff) {
2758 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2759 __func__);
2760 brcms_down(wlc->wl);
2761 return;
2762 }
2763 WARN_ON(mc & MCTL_PSM_JMP_0);
2764 WARN_ON(!(mc & MCTL_PSM_RUN));
2765 WARN_ON(!(mc & MCTL_EN_MAC));
2766
2767 mi = R_REG(&regs->macintstatus);
2768 if (mi == 0xffffffff) {
2769 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2770 __func__);
2771 brcms_down(wlc->wl);
2772 return;
2773 }
2774 WARN_ON(mi & MI_MACSSPNDD);
2775
2776 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2777
2778 SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
2779 BRCMS_MAX_MAC_SUSPEND);
2780
2781 if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
2782 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2783 " and MI_MACSSPNDD is still not on.\n",
2784 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2785 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2786 "psm_brc 0x%04x\n", wlc_hw->unit,
2787 R_REG(&regs->psmdebug),
2788 R_REG(&regs->phydebug),
2789 R_REG(&regs->psm_brc));
2790 }
2791
2792 mc = R_REG(&regs->maccontrol);
2793 if (mc == 0xffffffff) {
2794 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2795 __func__);
2796 brcms_down(wlc->wl);
2797 return;
2798 }
2799 WARN_ON(mc & MCTL_PSM_JMP_0);
2800 WARN_ON(!(mc & MCTL_PSM_RUN));
2801 WARN_ON(mc & MCTL_EN_MAC);
2802}
2803
2804void brcms_c_enable_mac(struct brcms_c_info *wlc)
2805{
2806 struct brcms_hardware *wlc_hw = wlc->hw;
2807 struct d11regs __iomem *regs = wlc_hw->regs;
2808 u32 mc, mi;
2809
2810 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2811 wlc->band->bandunit);
2812
2813 /*
2814 * Track overlapping suspend requests
2815 */
2816 wlc_hw->mac_suspend_depth--;
2817 if (wlc_hw->mac_suspend_depth > 0)
2818 return;
2819
2820 mc = R_REG(&regs->maccontrol);
2821 WARN_ON(mc & MCTL_PSM_JMP_0);
2822 WARN_ON(mc & MCTL_EN_MAC);
2823 WARN_ON(!(mc & MCTL_PSM_RUN));
2824
2825 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2826 W_REG(&regs->macintstatus, MI_MACSSPNDD);
2827
2828 mc = R_REG(&regs->maccontrol);
2829 WARN_ON(mc & MCTL_PSM_JMP_0);
2830 WARN_ON(!(mc & MCTL_EN_MAC));
2831 WARN_ON(!(mc & MCTL_PSM_RUN));
2832
2833 mi = R_REG(&regs->macintstatus);
2834 WARN_ON(mi & MI_MACSSPNDD);
2835
2836 brcms_c_ucode_wake_override_clear(wlc_hw,
2837 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2838}
2839
2840void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2841{
2842 wlc_hw->hw_stf_ss_opmode = stf_mode;
2843
2844 if (wlc_hw->clk)
2845 brcms_upd_ofdm_pctl1_table(wlc_hw);
2846}
2847
2848static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2849{
2850 struct d11regs __iomem *regs;
2851 u32 w, val;
2852 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2853
2854 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
2855
2856 regs = wlc_hw->regs;
2857
2858 /* Validate dchip register access */
2859
2860 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
2861 (void)R_REG(&regs->objaddr);
2862 w = R_REG(&regs->objdata);
2863
2864 /* Can we write and read back a 32bit register? */
2865 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
2866 (void)R_REG(&regs->objaddr);
2867 W_REG(&regs->objdata, (u32) 0xaa5555aa);
2868
2869 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
2870 (void)R_REG(&regs->objaddr);
2871 val = R_REG(&regs->objdata);
2872 if (val != (u32) 0xaa5555aa) {
2873 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2874 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2875 return false;
2876 }
2877
2878 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
2879 (void)R_REG(&regs->objaddr);
2880 W_REG(&regs->objdata, (u32) 0x55aaaa55);
2881
2882 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
2883 (void)R_REG(&regs->objaddr);
2884 val = R_REG(&regs->objdata);
2885 if (val != (u32) 0x55aaaa55) {
2886 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2887 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2888 return false;
2889 }
2890
2891 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
2892 (void)R_REG(&regs->objaddr);
2893 W_REG(&regs->objdata, w);
2894
2895 /* clear CFPStart */
2896 W_REG(&regs->tsf_cfpstart, 0);
2897
2898 w = R_REG(&regs->maccontrol);
2899 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2900 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2901 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2902 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2903 (MCTL_IHR_EN | MCTL_WAKE),
2904 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2905 return false;
2906 }
2907
2908 return true;
2909}
2910
2911#define PHYPLL_WAIT_US 100000
2912
2913void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2914{
2915 struct d11regs __iomem *regs;
2916 u32 tmp;
2917
2918 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2919
2920 tmp = 0;
2921 regs = wlc_hw->regs;
2922
2923 if (on) {
2924 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2925 OR_REG(&regs->clk_ctl_st,
2926 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
2927 CCS_ERSRC_REQ_PHYPLL));
2928 SPINWAIT((R_REG(&regs->clk_ctl_st) &
2929 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
2930 PHYPLL_WAIT_US);
2931
2932 tmp = R_REG(&regs->clk_ctl_st);
2933 if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
2934 (CCS_ERSRC_AVAIL_HT))
2935 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
2936 " PLL failed\n", __func__);
2937 } else {
2938 OR_REG(&regs->clk_ctl_st,
2939 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
2940 SPINWAIT((R_REG(&regs->clk_ctl_st) &
2941 (CCS_ERSRC_AVAIL_D11PLL |
2942 CCS_ERSRC_AVAIL_PHYPLL)) !=
2943 (CCS_ERSRC_AVAIL_D11PLL |
2944 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2945
2946 tmp = R_REG(&regs->clk_ctl_st);
2947 if ((tmp &
2948 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2949 !=
2950 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2951 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
2952 "PHY PLL failed\n", __func__);
2953 }
2954 } else {
2955 /*
2956 * Since the PLL may be shared, other cores can still
2957 * be requesting it; so we'll deassert the request but
2958 * not wait for status to comply.
2959 */
2960 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
2961 tmp = R_REG(&regs->clk_ctl_st);
2962 }
2963}
2964
2965void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2966{
2967 bool dev_gone;
2968
2969 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2970
2971 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2972
2973 if (dev_gone)
2974 return;
2975
2976 if (wlc_hw->noreset)
2977 return;
2978
2979 /* radio off */
2980 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2981
2982 /* turn off analog core */
2983 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2984
2985 /* turn off PHYPLL to save power */
2986 brcms_b_core_phypll_ctl(wlc_hw, false);
2987
2988 wlc_hw->clk = false;
2989 ai_core_disable(wlc_hw->sih, 0);
2990 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2991}
2992
2993static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2994{
2995 struct brcms_hardware *wlc_hw = wlc->hw;
2996 uint i;
2997
2998 /* free any posted tx packets */
2999 for (i = 0; i < NFIFO; i++)
3000 if (wlc_hw->di[i]) {
3001 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
3002 wlc->core->txpktpend[i] = 0;
3003 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3004 }
3005
3006 /* free any posted rx packets */
3007 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3008}
3009
3010static u16
3011brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
3012{
3013 struct d11regs __iomem *regs = wlc_hw->regs;
3014 u16 __iomem *objdata_lo = (u16 __iomem *)&regs->objdata;
3015 u16 __iomem *objdata_hi = objdata_lo + 1;
3016 u16 v;
3017
3018 W_REG(&regs->objaddr, sel | (offset >> 2));
3019 (void)R_REG(&regs->objaddr);
3020 if (offset & 2)
3021 v = R_REG(objdata_hi);
3022 else
3023 v = R_REG(objdata_lo);
3024
3025 return v;
3026}
3027
3028static void
3029brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
3030 u32 sel)
3031{
3032 struct d11regs __iomem *regs = wlc_hw->regs;
3033 u16 __iomem *objdata_lo = (u16 __iomem *)&regs->objdata;
3034 u16 __iomem *objdata_hi = objdata_lo + 1;
3035
3036 W_REG(&regs->objaddr, sel | (offset >> 2));
3037 (void)R_REG(&regs->objaddr);
3038 if (offset & 2)
3039 W_REG(objdata_hi, v);
3040 else
3041 W_REG(objdata_lo, v);
3042}
3043
3044/*
3045 * Read a single u16 from shared memory.
3046 * SHM 'offset' needs to be an even address
3047 */
3048u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
3049{
3050 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3051}
3052
3053/*
3054 * Write a single u16 to shared memory.
3055 * SHM 'offset' needs to be an even address
3056 */
3057void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
3058{
3059 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3060}
3061
3062/*
3063 * Copy a buffer to shared memory of specified type .
3064 * SHM 'offset' needs to be an even address and
3065 * Buffer length 'len' must be an even number of bytes
3066 * 'sel' selects the type of memory
3067 */
3068void
3069brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
3070 const void *buf, int len, u32 sel)
3071{
3072 u16 v;
3073 const u8 *p = (const u8 *)buf;
3074 int i;
3075
3076 if (len <= 0 || (offset & 1) || (len & 1))
3077 return;
3078
3079 for (i = 0; i < len; i += 2) {
3080 v = p[i] | (p[i + 1] << 8);
3081 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
3082 }
3083}
3084
3085/*
3086 * Copy a piece of shared memory of specified type to a buffer .
3087 * SHM 'offset' needs to be an even address and
3088 * Buffer length 'len' must be an even number of bytes
3089 * 'sel' selects the type of memory
3090 */
3091void
3092brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
3093 int len, u32 sel)
3094{
3095 u16 v;
3096 u8 *p = (u8 *) buf;
3097 int i;
3098
3099 if (len <= 0 || (offset & 1) || (len & 1))
3100 return;
3101
3102 for (i = 0; i < len; i += 2) {
3103 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
3104 p[i] = v & 0xFF;
3105 p[i + 1] = (v >> 8) & 0xFF;
3106 }
3107}
3108
3109static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3110 u16 SRL, u16 LRL)
3111{
3112 wlc_hw->SRL = SRL;
3113 wlc_hw->LRL = LRL;
3114
3115 /* write retry limit to SCR, shouldn't need to suspend */
3116 if (wlc_hw->up) {
3117 W_REG(&wlc_hw->regs->objaddr,
3118 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3119 (void)R_REG(&wlc_hw->regs->objaddr);
3120 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3121 W_REG(&wlc_hw->regs->objaddr,
3122 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3123 (void)R_REG(&wlc_hw->regs->objaddr);
3124 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3125 }
3126}
3127
3128static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3129{
3130 if (set) {
3131 if (mboolisset(wlc_hw->pllreq, req_bit))
3132 return;
3133
3134 mboolset(wlc_hw->pllreq, req_bit);
3135
3136 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3137 if (!wlc_hw->sbclk)
3138 brcms_b_xtal(wlc_hw, ON);
3139 }
3140 } else {
3141 if (!mboolisset(wlc_hw->pllreq, req_bit))
3142 return;
3143
3144 mboolclr(wlc_hw->pllreq, req_bit);
3145
3146 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3147 if (wlc_hw->sbclk)
3148 brcms_b_xtal(wlc_hw, OFF);
3149 }
3150 }
3151}
3152
3153static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3154{
3155 wlc_hw->antsel_avail = antsel_avail;
3156}
3157
3158/*
3159 * conditions under which the PM bit should be set in outgoing frames
3160 * and STAY_AWAKE is meaningful
3161 */
3162bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3163{
3164 struct brcms_bss_cfg *cfg = wlc->bsscfg;
3165
3166 /* disallow PS when one of the following global conditions meets */
3167 if (!wlc->pub->associated)
3168 return false;
3169
3170 /* disallow PS when one of these meets when not scanning */
3171 if (wlc->monitor)
3172 return false;
3173
3174 if (cfg->associated) {
3175 /*
3176 * disallow PS when one of the following
3177 * bsscfg specific conditions meets
3178 */
3179 if (!cfg->BSS)
3180 return false;
3181
3182 return false;
3183 }
3184
3185 return true;
3186}
3187
3188static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3189{
3190 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3191
3192 /* reset the core */
3193 if (!brcms_deviceremoved(wlc_hw->wlc))
3194 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3195
3196 /* purge the dma rings */
3197 brcms_c_flushqueues(wlc_hw->wlc);
3198}
3199
3200void brcms_c_reset(struct brcms_c_info *wlc)
3201{
3202 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3203
3204 /* slurp up hw mac counters before core reset */
3205 brcms_c_statsupd(wlc);
3206
3207 /* reset our snapshot of macstat counters */
3208 memset((char *)wlc->core->macstat_snapshot, 0,
3209 sizeof(struct macstat));
3210
3211 brcms_b_reset(wlc->hw);
3212}
3213
3214void brcms_c_fatal_error(struct brcms_c_info *wlc)
3215{
3216 wiphy_err(wlc->wiphy, "wl%d: fatal error, reinitializing\n",
3217 wlc->pub->unit);
3218 brcms_init(wlc->wl);
3219}
3220
3221/* Return the channel the driver should initialize during brcms_c_init.
3222 * the channel may have to be changed from the currently configured channel
3223 * if other configurations are in conflict (bandlocked, 11n mode disabled,
3224 * invalid channel for current country, etc.)
3225 */
3226static u16 brcms_c_init_chanspec(struct brcms_c_info *wlc)
3227{
3228 u16 chanspec =
3229 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE |
3230 WL_CHANSPEC_BAND_2G;
3231
3232 return chanspec;
3233}
3234
3235void brcms_c_init_scb(struct scb *scb)
3236{
3237 int i;
3238
3239 memset(scb, 0, sizeof(struct scb));
3240 scb->flags = SCB_WMECAP | SCB_HTCAP;
3241 for (i = 0; i < NUMPRIO; i++) {
3242 scb->seqnum[i] = 0;
3243 scb->seqctl[i] = 0xFFFF;
3244 }
3245
3246 scb->seqctl_nonqos = 0xFFFF;
3247 scb->magic = SCB_MAGIC;
3248}
3249
3250/* d11 core init
3251 * reset PSM
3252 * download ucode/PCM
3253 * let ucode run to suspended
3254 * download ucode inits
3255 * config other core registers
3256 * init dma
3257 */
3258static void brcms_b_coreinit(struct brcms_c_info *wlc)
3259{
3260 struct brcms_hardware *wlc_hw = wlc->hw;
3261 struct d11regs __iomem *regs;
3262 u32 sflags;
3263 uint bcnint_us;
3264 uint i = 0;
3265 bool fifosz_fixup = false;
3266 int err = 0;
3267 u16 buf[NFIFO];
3268 struct wiphy *wiphy = wlc->wiphy;
3269 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3270
3271 regs = wlc_hw->regs;
3272
3273 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3274
3275 /* reset PSM */
3276 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3277
3278 brcms_ucode_download(wlc_hw);
3279 /*
3280 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3281 */
3282 fifosz_fixup = true;
3283
3284 /* let the PSM run to the suspended state, set mode to BSS STA */
3285 W_REG(&regs->macintstatus, -1);
3286 brcms_b_mctrl(wlc_hw, ~0,
3287 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3288
3289 /* wait for ucode to self-suspend after auto-init */
3290 SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
3291 1000 * 1000);
3292 if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
3293 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
3294 "suspend!\n", wlc_hw->unit);
3295
3296 brcms_c_gpio_init(wlc);
3297
3298 sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
3299
3300 if (D11REV_IS(wlc_hw->corerev, 23)) {
3301 if (BRCMS_ISNPHY(wlc_hw->band))
3302 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3303 else
3304 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3305 " %d\n", __func__, wlc_hw->unit,
3306 wlc_hw->corerev);
3307 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3308 if (BRCMS_ISLCNPHY(wlc_hw->band))
3309 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3310 else
3311 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3312 " %d\n", __func__, wlc_hw->unit,
3313 wlc_hw->corerev);
3314 } else {
3315 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
3316 __func__, wlc_hw->unit, wlc_hw->corerev);
3317 }
3318
3319 /* For old ucode, txfifo sizes needs to be modified(increased) */
3320 if (fifosz_fixup == true)
3321 brcms_b_corerev_fifofixup(wlc_hw);
3322
3323 /* check txfifo allocations match between ucode and driver */
3324 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3325 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3326 i = TX_AC_BE_FIFO;
3327 err = -1;
3328 }
3329 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3330 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3331 i = TX_AC_VI_FIFO;
3332 err = -1;
3333 }
3334 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3335 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3336 buf[TX_AC_BK_FIFO] &= 0xff;
3337 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3338 i = TX_AC_BK_FIFO;
3339 err = -1;
3340 }
3341 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3342 i = TX_AC_VO_FIFO;
3343 err = -1;
3344 }
3345 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3346 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3347 buf[TX_BCMC_FIFO] &= 0xff;
3348 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3349 i = TX_BCMC_FIFO;
3350 err = -1;
3351 }
3352 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3353 i = TX_ATIM_FIFO;
3354 err = -1;
3355 }
3356 if (err != 0)
3357 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
3358 " driver size %d index %d\n", buf[i],
3359 wlc_hw->xmtfifo_sz[i], i);
3360
3361 /* make sure we can still talk to the mac */
3362 WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff);
3363
3364 /* band-specific inits done by wlc_bsinit() */
3365
3366 /* Set up frame burst size and antenna swap threshold init values */
3367 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3368 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3369
3370 /* enable one rx interrupt per received frame */
3371 W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
3372
3373 /* set the station mode (BSS STA) */
3374 brcms_b_mctrl(wlc_hw,
3375 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3376 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3377
3378 /* set up Beacon interval */
3379 bcnint_us = 0x8000 << 10;
3380 W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
3381 W_REG(&regs->tsf_cfpstart, bcnint_us);
3382 W_REG(&regs->macintstatus, MI_GP1);
3383
3384 /* write interrupt mask */
3385 W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
3386
3387 /* allow the MAC to control the PHY clock (dynamic on/off) */
3388 brcms_b_macphyclk_set(wlc_hw, ON);
3389
3390 /* program dynamic clock control fast powerup delay register */
3391 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3392 W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
3393
3394 /* tell the ucode the corerev */
3395 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3396
3397 /* tell the ucode MAC capabilities */
3398 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3399 (u16) (wlc_hw->machwcap & 0xffff));
3400 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3401 (u16) ((wlc_hw->
3402 machwcap >> 16) & 0xffff));
3403
3404 /* write retry limits to SCR, this done after PSM init */
3405 W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3406 (void)R_REG(&regs->objaddr);
3407 W_REG(&regs->objdata, wlc_hw->SRL);
3408 W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3409 (void)R_REG(&regs->objaddr);
3410 W_REG(&regs->objdata, wlc_hw->LRL);
3411
3412 /* write rate fallback retry limits */
3413 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3414 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3415
3416 AND_REG(&regs->ifs_ctl, 0x0FFF);
3417 W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
3418
3419 /* init the tx dma engines */
3420 for (i = 0; i < NFIFO; i++) {
3421 if (wlc_hw->di[i])
3422 dma_txinit(wlc_hw->di[i]);
3423 }
3424
3425 /* init the rx dma engine(s) and post receive buffers */
3426 dma_rxinit(wlc_hw->di[RX_FIFO]);
3427 dma_rxfill(wlc_hw->di[RX_FIFO]);
3428}
3429
3430void
3431static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec,
3432 bool mute) {
3433 u32 macintmask;
3434 bool fastclk;
3435 struct brcms_c_info *wlc = wlc_hw->wlc;
3436
3437 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3438
3439 /* request FAST clock if not on */
3440 fastclk = wlc_hw->forcefastclk;
3441 if (!fastclk)
3442 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
3443
3444 /* disable interrupts */
3445 macintmask = brcms_intrsoff(wlc->wl);
3446
3447 /* set up the specified band and chanspec */
3448 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3449 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3450
3451 /* do one-time phy inits and calibration */
3452 wlc_phy_cal_init(wlc_hw->band->pi);
3453
3454 /* core-specific initialization */
3455 brcms_b_coreinit(wlc);
3456
3457 /* suspend the tx fifos and mute the phy for preism cac time */
3458 if (mute)
3459 brcms_b_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
3460
3461 /* band-specific inits */
3462 brcms_b_bsinit(wlc, chanspec);
3463
3464 /* restore macintmask */
3465 brcms_intrsrestore(wlc->wl, macintmask);
3466
3467 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3468 * is suspended and brcms_c_enable_mac() will clear this override bit.
3469 */
3470 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3471
3472 /*
3473 * initialize mac_suspend_depth to 1 to match ucode
3474 * initial suspended state
3475 */
3476 wlc_hw->mac_suspend_depth = 1;
3477
3478 /* restore the clk */
3479 if (!fastclk)
3480 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
3481}
3482
3483static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3484 u16 chanspec)
3485{
3486 /* Save our copy of the chanspec */
3487 wlc->chanspec = chanspec;
3488
3489 /* Set the chanspec and power limits for this locale */
3490 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3491
3492 if (wlc->stf->ss_algosel_auto)
3493 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3494 chanspec);
3495
3496 brcms_c_stf_ss_update(wlc, wlc->band);
3497
3498}
3499
3500static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3501 u16 chanspec)
3502{
3503 struct brcms_c_rateset default_rateset;
3504 uint parkband;
3505 uint i, band_order[2];
3506
3507 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3508 /*
3509 * We might have been bandlocked during down and the chip
3510 * power-cycled (hibernate). Figure out the right band to park on
3511 */
3512 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3513 /* updated in brcms_c_bandlock() */
3514 parkband = wlc->band->bandunit;
3515 band_order[0] = band_order[1] = parkband;
3516 } else {
3517 /* park on the band of the specified chanspec */
3518 parkband = chspec_bandunit(chanspec);
3519
3520 /* order so that parkband initialize last */
3521 band_order[0] = parkband ^ 1;
3522 band_order[1] = parkband;
3523 }
3524
3525 /* make each band operational, software state init */
3526 for (i = 0; i < wlc->pub->_nbands; i++) {
3527 uint j = band_order[i];
3528
3529 wlc->band = wlc->bandstate[j];
3530
3531 brcms_default_rateset(wlc, &default_rateset);
3532
3533 /* fill in hw_rate */
3534 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3535 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3536 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3537
3538 /* init basic rate lookup */
3539 brcms_c_rate_lookup_init(wlc, &default_rateset);
3540 }
3541
3542 /* sync up phy/radio chanspec */
3543 brcms_c_set_phy_chanspec(wlc, chanspec);
3544}
3545
3546/*
3547 * ucode, hwmac update
3548 * Channel dependent updates for ucode and hw
3549 */
3550static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3551{
3552 /* enable or disable any active IBSSs depending on whether or not
3553 * we are on the home channel
3554 */
3555 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3556 if (wlc->pub->associated) {
3557 /*
3558 * BMAC_NOTE: This is something that should be fixed
3559 * in ucode inits. I think that the ucode inits set
3560 * up the bcn templates and shm values with a bogus
3561 * beacon. This should not be done in the inits. If
3562 * ucode needs to set up a beacon for testing, the
3563 * test routines should write it down, not expect the
3564 * inits to populate a bogus beacon.
3565 */
3566 if (BRCMS_PHY_11N_CAP(wlc->band))
3567 brcms_b_write_shm(wlc->hw,
3568 M_BCN_TXTSF_OFFSET, 0);
3569 }
3570 } else {
3571 /* disable an active IBSS if we are not on the home channel */
3572 }
3573
3574 /* update the various promisc bits */
3575 brcms_c_mac_bcn_promisc(wlc);
3576 brcms_c_mac_promisc(wlc);
3577}
3578
3579/* band-specific init */
3580static void brcms_c_bsinit(struct brcms_c_info *wlc)
3581{
3582 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
3583 wlc->pub->unit, wlc->band->bandunit);
3584
3585 /* write ucode ACK/CTS rate table */
3586 brcms_c_set_ratetable(wlc);
3587
3588 /* update some band specific mac configuration */
3589 brcms_c_ucode_mac_upd(wlc);
3590
3591 /* init antenna selection */
3592 brcms_c_antsel_init(wlc->asi);
3593
3594}
3595
3596/* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3597static int
3598brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3599 bool writeToShm)
3600{
3601 int idle_busy_ratio_x_16 = 0;
3602 uint offset =
3603 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3604 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3605 if (duty_cycle > 100 || duty_cycle < 0) {
3606 wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
3607 wlc->pub->unit);
3608 return -EINVAL;
3609 }
3610 if (duty_cycle)
3611 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3612 /* Only write to shared memory when wl is up */
3613 if (writeToShm)
3614 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3615
3616 if (isOFDM)
3617 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3618 else
3619 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3620
3621 return 0;
3622}
3623
3624/*
3625 * Initialize the base precedence map for dequeueing
3626 * from txq based on WME settings
3627 */
3628static void brcms_c_tx_prec_map_init(struct brcms_c_info *wlc)
3629{
3630 wlc->tx_prec_map = BRCMS_PREC_BMP_ALL;
3631 memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16));
3632
3633 wlc->fifo2prec_map[TX_AC_BK_FIFO] = BRCMS_PREC_BMP_AC_BK;
3634 wlc->fifo2prec_map[TX_AC_BE_FIFO] = BRCMS_PREC_BMP_AC_BE;
3635 wlc->fifo2prec_map[TX_AC_VI_FIFO] = BRCMS_PREC_BMP_AC_VI;
3636 wlc->fifo2prec_map[TX_AC_VO_FIFO] = BRCMS_PREC_BMP_AC_VO;
3637}
3638
3639static void
3640brcms_c_txflowcontrol_signal(struct brcms_c_info *wlc,
3641 struct brcms_txq_info *qi, bool on, int prio)
3642{
3643 /* transmit flowcontrol is not yet implemented */
3644}
3645
3646static void brcms_c_txflowcontrol_reset(struct brcms_c_info *wlc)
3647{
3648 struct brcms_txq_info *qi;
3649
3650 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
3651 if (qi->stopped) {
3652 brcms_c_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
3653 qi->stopped = 0;
3654 }
3655 }
3656}
3657
3658void brcms_c_init(struct brcms_c_info *wlc)
3659{
3660 struct d11regs __iomem *regs;
3661 u16 chanspec;
3662 bool mute = false;
3663
3664 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3665
3666 regs = wlc->regs;
3667
3668 /*
3669 * This will happen if a big-hammer was executed. In
3670 * that case, we want to go back to the channel that
3671 * we were on and not new channel
3672 */
3673 if (wlc->pub->associated)
3674 chanspec = wlc->home_chanspec;
3675 else
3676 chanspec = brcms_c_init_chanspec(wlc);
3677
3678 brcms_b_init(wlc->hw, chanspec, mute);
3679
3680 /* update beacon listen interval */
3681 brcms_c_bcn_li_upd(wlc);
3682
3683 /* write ethernet address to core */
3684 brcms_c_set_mac(wlc->bsscfg);
3685 brcms_c_set_bssid(wlc->bsscfg);
3686
3687 /* Update tsf_cfprep if associated and up */
3688 if (wlc->pub->associated && wlc->bsscfg->up) {
3689 u32 bi;
3690
3691 /* get beacon period and convert to uS */
3692 bi = wlc->bsscfg->current_bss->beacon_period << 10;
3693 /*
3694 * update since init path would reset
3695 * to default value
3696 */
3697 W_REG(&regs->tsf_cfprep,
3698 (bi << CFPREP_CBI_SHIFT));
3699
3700 /* Update maccontrol PM related bits */
3701 brcms_c_set_ps_ctrl(wlc);
3702 }
3703
3704 brcms_c_bandinit_ordered(wlc, chanspec);
3705
3706 /* init probe response timeout */
3707 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
3708
3709 /* init max burst txop (framebursting) */
3710 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
3711 (wlc->
3712 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
3713
3714 /* initialize maximum allowed duty cycle */
3715 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
3716 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
3717
3718 /*
3719 * Update some shared memory locations related to
3720 * max AMPDU size allowed to received
3721 */
3722 brcms_c_ampdu_shm_upd(wlc->ampdu);
3723
3724 /* band-specific inits */
3725 brcms_c_bsinit(wlc);
3726
3727 /* Enable EDCF mode (while the MAC is suspended) */
3728 OR_REG(&regs->ifs_ctl, IFS_USEEDCF);
3729 brcms_c_edcf_setparams(wlc, false);
3730
3731 /* Init precedence maps for empty FIFOs */
3732 brcms_c_tx_prec_map_init(wlc);
3733
3734 /* read the ucode version if we have not yet done so */
3735 if (wlc->ucode_rev == 0) {
3736 wlc->ucode_rev =
3737 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
3738 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
3739 }
3740
3741 /* ..now really unleash hell (allow the MAC out of suspend) */
3742 brcms_c_enable_mac(wlc);
3743
3744 /* clear tx flow control */
3745 brcms_c_txflowcontrol_reset(wlc);
3746
3747 /* enable the RF Disable Delay timer */
3748 W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
3749
3750 /* initialize mpc delay */
3751 wlc->mpc_delay_off = wlc->mpc_dlycnt = BRCMS_MPC_MIN_DELAYCNT;
3752
3753 /*
3754 * Initialize WME parameters; if they haven't been set by some other
3755 * mechanism (IOVar, etc) then read them from the hardware.
3756 */
3757 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
3758 /* Uninitialized; read from HW */
3759 int ac;
3760
3761 for (ac = 0; ac < AC_COUNT; ac++)
3762 wlc->wme_retries[ac] =
3763 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
3764 }
3765}
3766
3767void brcms_c_mac_bcn_promisc_change(struct brcms_c_info *wlc, bool promisc)
3768{
3769 wlc->bcnmisc_monitor = promisc;
3770 brcms_c_mac_bcn_promisc(wlc);
3771}
3772
3773void brcms_c_mac_bcn_promisc(struct brcms_c_info *wlc)
3774{
3775 if (wlc->bcnmisc_monitor)
3776 brcms_b_mctrl(wlc->hw, MCTL_BCNS_PROMISC, MCTL_BCNS_PROMISC);
3777 else
3778 brcms_b_mctrl(wlc->hw, MCTL_BCNS_PROMISC, 0);
3779}
3780
3781/* set or clear maccontrol bits MCTL_PROMISC and MCTL_KEEPCONTROL */
3782void brcms_c_mac_promisc(struct brcms_c_info *wlc)
3783{
3784 u32 promisc_bits = 0;
3785
3786 /*
3787 * promiscuous mode just sets MCTL_PROMISC
3788 * Note: APs get all BSS traffic without the need to set
3789 * the MCTL_PROMISC bit since all BSS data traffic is
3790 * directed at the AP
3791 */
3792 if (wlc->pub->promisc)
3793 promisc_bits |= MCTL_PROMISC;
3794
3795 /* monitor mode needs both MCTL_PROMISC and MCTL_KEEPCONTROL
3796 * Note: monitor mode also needs MCTL_BCNS_PROMISC, but that is
3797 * handled in brcms_c_mac_bcn_promisc()
3798 */
3799 if (wlc->monitor)
3800 promisc_bits |= MCTL_PROMISC | MCTL_KEEPCONTROL;
3801
3802 brcms_b_mctrl(wlc->hw, MCTL_PROMISC | MCTL_KEEPCONTROL, promisc_bits);
3803}
3804
3805/* push sw hps and wake state through hardware */
3806void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3807{
3808 u32 v1, v2;
3809 bool hps;
3810 bool awake_before;
3811
3812 hps = brcms_c_ps_allowed(wlc);
3813
3814 BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
3815
3816 v1 = R_REG(&wlc->regs->maccontrol);
3817 v2 = MCTL_WAKE;
3818 if (hps)
3819 v2 |= MCTL_HPS;
3820
3821 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3822
3823 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3824
3825 if (!awake_before)
3826 brcms_b_wait_for_wake(wlc->hw);
3827
3828}
3829
3830/*
3831 * Write this BSS config's MAC address to core.
3832 * Updates RXE match engine.
3833 */
3834int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3835{
3836 int err = 0;
3837 struct brcms_c_info *wlc = bsscfg->wlc;
3838
3839 /* enter the MAC addr into the RXE match registers */
3840 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3841
3842 brcms_c_ampdu_macaddr_upd(wlc);
3843
3844 return err;
3845}
3846
3847/* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3848 * Updates RXE match engine.
3849 */
3850void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3851{
3852 /* we need to update BSSID in RXE match registers */
3853 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3854}
3855
3856static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3857{
3858 wlc_hw->shortslot = shortslot;
3859
3860 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3861 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3862 brcms_b_update_slot_timing(wlc_hw, shortslot);
3863 brcms_c_enable_mac(wlc_hw->wlc);
3864 }
3865}
3866
3867/*
3868 * Suspend the the MAC and update the slot timing
3869 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3870 */
3871void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3872{
3873 /* use the override if it is set */
3874 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3875 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3876
3877 if (wlc->shortslot == shortslot)
3878 return;
3879
3880 wlc->shortslot = shortslot;
3881
3882 brcms_b_set_shortslot(wlc->hw, shortslot);
3883}
3884
3885void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3886{
3887 if (wlc->home_chanspec != chanspec) {
3888 wlc->home_chanspec = chanspec;
3889
3890 if (wlc->bsscfg->associated)
3891 wlc->bsscfg->current_bss->chanspec = chanspec;
3892 }
3893}
3894
3895void
3896brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3897 bool mute, struct txpwr_limits *txpwr)
3898{
3899 uint bandunit;
3900
3901 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
3902
3903 wlc_hw->chanspec = chanspec;
3904
3905 /* Switch bands if necessary */
3906 if (wlc_hw->_nbands > 1) {
3907 bandunit = chspec_bandunit(chanspec);
3908 if (wlc_hw->band->bandunit != bandunit) {
3909 /* brcms_b_setband disables other bandunit,
3910 * use light band switch if not up yet
3911 */
3912 if (wlc_hw->up) {
3913 wlc_phy_chanspec_radio_set(wlc_hw->
3914 bandstate[bandunit]->
3915 pi, chanspec);
3916 brcms_b_setband(wlc_hw, bandunit, chanspec);
3917 } else {
3918 brcms_c_setxband(wlc_hw, bandunit);
3919 }
3920 }
3921 }
3922
3923 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
3924
3925 if (!wlc_hw->up) {
3926 if (wlc_hw->clk)
3927 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3928 chanspec);
3929 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3930 } else {
3931 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3932 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3933
3934 /* Update muting of the channel */
3935 brcms_b_mute(wlc_hw, mute, 0);
3936 }
3937}
3938
3939/* switch to and initialize new band */
3940static void brcms_c_setband(struct brcms_c_info *wlc,
3941 uint bandunit)
3942{
3943 wlc->band = wlc->bandstate[bandunit];
3944
3945 if (!wlc->pub->up)
3946 return;
3947
3948 /* wait for at least one beacon before entering sleeping state */
3949 brcms_c_set_ps_ctrl(wlc);
3950
3951 /* band-specific initializations */
3952 brcms_c_bsinit(wlc);
3953}
3954
3955void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3956{
3957 uint bandunit;
3958 bool switchband = false;
3959 u16 old_chanspec = wlc->chanspec;
3960
3961 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3962 wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
3963 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3964 return;
3965 }
3966
3967 /* Switch bands if necessary */
3968 if (wlc->pub->_nbands > 1) {
3969 bandunit = chspec_bandunit(chanspec);
3970 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3971 switchband = true;
3972 if (wlc->bandlocked) {
3973 wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
3974 "band is locked!\n",
3975 wlc->pub->unit, __func__,
3976 CHSPEC_CHANNEL(chanspec));
3977 return;
3978 }
3979 /*
3980 * should the setband call come after the
3981 * brcms_b_chanspec() ? if the setband updates
3982 * (brcms_c_bsinit) use low level calls to inspect and
3983 * set state, the state inspected may be from the wrong
3984 * band, or the following brcms_b_set_chanspec() may
3985 * undo the work.
3986 */
3987 brcms_c_setband(wlc, bandunit);
3988 }
3989 }
3990
3991 /* sync up phy/radio chanspec */
3992 brcms_c_set_phy_chanspec(wlc, chanspec);
3993
3994 /* init antenna selection */
3995 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3996 brcms_c_antsel_init(wlc->asi);
3997
3998 /* Fix the hardware rateset based on bw.
3999 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
4000 */
4001 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
4002 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
4003 }
4004
4005 /* update some mac configuration since chanspec changed */
4006 brcms_c_ucode_mac_upd(wlc);
4007}
4008
4009u32 brcms_c_lowest_basic_rspec(struct brcms_c_info *wlc,
4010 struct brcms_c_rateset *rs)
4011{
4012 u32 lowest_basic_rspec;
4013 uint i;
4014
4015 /* Use the lowest basic rate */
4016 lowest_basic_rspec = rs->rates[0] & BRCMS_RATE_MASK;
4017 for (i = 0; i < rs->count; i++) {
4018 if (rs->rates[i] & BRCMS_RATE_FLAG) {
4019 lowest_basic_rspec = rs->rates[i] & BRCMS_RATE_MASK;
4020 break;
4021 }
4022 }
4023
4024 /*
4025 * pick siso/cdd as default for OFDM (note no basic
4026 * rate MCSs are supported yet)
4027 */
4028 if (is_ofdm_rate(lowest_basic_rspec))
4029 lowest_basic_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
4030
4031 return lowest_basic_rspec;
4032}
4033
4034/*
4035 * This function changes the phytxctl for beacon based on current
4036 * beacon ratespec AND txant setting as per this table:
4037 * ratespec CCK ant = wlc->stf->txant
4038 * OFDM ant = 3
4039 */
4040void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
4041 u32 bcn_rspec)
4042{
4043 u16 phyctl;
4044 u16 phytxant = wlc->stf->phytxant;
4045 u16 mask = PHY_TXC_ANT_MASK;
4046
4047 /* for non-siso rates or default setting, use the available chains */
4048 if (BRCMS_PHY_11N_CAP(wlc->band))
4049 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
4050
4051 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
4052 phyctl = (phyctl & ~mask) | phytxant;
4053 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
4054}
4055
4056/*
4057 * centralized protection config change function to simplify debugging, no
4058 * consistency checking this should be called only on changes to avoid overhead
4059 * in periodic function
4060 */
4061void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
4062{
4063 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
4064
4065 switch (idx) {
4066 case BRCMS_PROT_G_SPEC:
4067 wlc->protection->_g = (bool) val;
4068 break;
4069 case BRCMS_PROT_G_OVR:
4070 wlc->protection->g_override = (s8) val;
4071 break;
4072 case BRCMS_PROT_G_USER:
4073 wlc->protection->gmode_user = (u8) val;
4074 break;
4075 case BRCMS_PROT_OVERLAP:
4076 wlc->protection->overlap = (s8) val;
4077 break;
4078 case BRCMS_PROT_N_USER:
4079 wlc->protection->nmode_user = (s8) val;
4080 break;
4081 case BRCMS_PROT_N_CFG:
4082 wlc->protection->n_cfg = (s8) val;
4083 break;
4084 case BRCMS_PROT_N_CFG_OVR:
4085 wlc->protection->n_cfg_override = (s8) val;
4086 break;
4087 case BRCMS_PROT_N_NONGF:
4088 wlc->protection->nongf = (bool) val;
4089 break;
4090 case BRCMS_PROT_N_NONGF_OVR:
4091 wlc->protection->nongf_override = (s8) val;
4092 break;
4093 case BRCMS_PROT_N_PAM_OVR:
4094 wlc->protection->n_pam_override = (s8) val;
4095 break;
4096 case BRCMS_PROT_N_OBSS:
4097 wlc->protection->n_obss = (bool) val;
4098 break;
4099
4100 default:
4101 break;
4102 }
4103
4104}
4105
4106static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4107{
4108 if (wlc->pub->up) {
4109 brcms_c_update_beacon(wlc);
4110 brcms_c_update_probe_resp(wlc, true);
4111 }
4112}
4113
4114static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4115{
4116 wlc->stf->ldpc = val;
4117
4118 if (wlc->pub->up) {
4119 brcms_c_update_beacon(wlc);
4120 brcms_c_update_probe_resp(wlc, true);
4121 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4122 }
4123}
4124
4125void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4126 const struct ieee80211_tx_queue_params *params,
4127 bool suspend)
4128{
4129 int i;
4130 struct shm_acparams acp_shm;
4131 u16 *shm_entry;
4132
4133 /* Only apply params if the core is out of reset and has clocks */
4134 if (!wlc->clk) {
4135 wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
4136 __func__);
4137 return;
4138 }
4139
4140 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
4141 /* fill in shm ac params struct */
4142 acp_shm.txop = params->txop;
4143 /* convert from units of 32us to us for ucode */
4144 wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4145 EDCF_TXOP2USEC(acp_shm.txop);
4146 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4147
4148 if (aci == AC_VI && acp_shm.txop == 0
4149 && acp_shm.aifs < EDCF_AIFSN_MAX)
4150 acp_shm.aifs++;
4151
4152 if (acp_shm.aifs < EDCF_AIFSN_MIN
4153 || acp_shm.aifs > EDCF_AIFSN_MAX) {
4154 wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad "
4155 "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4156 } else {
4157 acp_shm.cwmin = params->cw_min;
4158 acp_shm.cwmax = params->cw_max;
4159 acp_shm.cwcur = acp_shm.cwmin;
4160 acp_shm.bslots =
4161 R_REG(&wlc->regs->tsf_random) & acp_shm.cwcur;
4162 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4163 /* Indicate the new params to the ucode */
4164 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4165 wme_ac2fifo[aci] *
4166 M_EDCF_QLEN +
4167 M_EDCF_STATUS_OFF));
4168 acp_shm.status |= WME_STATUS_NEWAC;
4169
4170 /* Fill in shm acparam table */
4171 shm_entry = (u16 *) &acp_shm;
4172 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4173 brcms_b_write_shm(wlc->hw,
4174 M_EDCF_QINFO +
4175 wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4176 *shm_entry++);
4177 }
4178
4179 if (suspend) {
4180 brcms_c_suspend_mac_and_wait(wlc);
4181 brcms_c_enable_mac(wlc);
4182 }
4183}
4184
4185void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4186{
4187 u16 aci;
4188 int i_ac;
4189 struct ieee80211_tx_queue_params txq_pars;
4190 static const struct edcf_acparam default_edcf_acparams[] = {
4191 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4192 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4193 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4194 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4195 }; /* ucode needs these parameters during its initialization */
4196 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4197
4198 for (i_ac = 0; i_ac < AC_COUNT; i_ac++, edcf_acp++) {
4199 /* find out which ac this set of params applies to */
4200 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4201
4202 /* fill in shm ac params struct */
4203 txq_pars.txop = edcf_acp->TXOP;
4204 txq_pars.aifs = edcf_acp->ACI;
4205
4206 /* CWmin = 2^(ECWmin) - 1 */
4207 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4208 /* CWmax = 2^(ECWmax) - 1 */
4209 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4210 >> EDCF_ECWMAX_SHIFT);
4211 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4212 }
4213
4214 if (suspend) {
4215 brcms_c_suspend_mac_and_wait(wlc);
4216 brcms_c_enable_mac(wlc);
4217 }
4218}
4219
4220/* maintain LED behavior in down state */
4221static void brcms_c_down_led_upd(struct brcms_c_info *wlc)
4222{
4223 /*
4224 * maintain LEDs while in down state, turn on sbclk if
4225 * not available yet. Turn on sbclk if necessary
4226 */
4227 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_FLIP);
4228 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_FLIP);
4229}
4230
4231static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4232{
4233 /* Don't start the timer if HWRADIO feature is disabled */
4234 if (wlc->radio_monitor)
4235 return;
4236
4237 wlc->radio_monitor = true;
4238 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4239 brcms_add_timer(wlc->wl, wlc->radio_timer, TIMER_INTERVAL_RADIOCHK,
4240 true);
4241}
4242
4243void brcms_c_radio_disable(struct brcms_c_info *wlc)
4244{
4245 if (!wlc->pub->up) {
4246 brcms_c_down_led_upd(wlc);
4247 return;
4248 }
4249
4250 brcms_c_radio_monitor_start(wlc);
4251 brcms_down(wlc->wl);
4252}
4253
4254static void brcms_c_radio_enable(struct brcms_c_info *wlc)
4255{
4256 if (wlc->pub->up)
4257 return;
4258
4259 if (brcms_deviceremoved(wlc))
4260 return;
4261
4262 brcms_up(wlc->wl);
4263}
4264
4265bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4266{
4267 if (!wlc->radio_monitor)
4268 return true;
4269
4270 wlc->radio_monitor = false;
4271 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4272 return brcms_del_timer(wlc->wl, wlc->radio_timer);
4273}
4274
4275/* read hwdisable state and propagate to wlc flag */
4276static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4277{
4278 if (wlc->pub->hw_off)
4279 return;
4280
4281 if (brcms_b_radio_read_hwdisabled(wlc->hw))
4282 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4283 else
4284 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4285}
4286
4287/*
4288 * centralized radio disable/enable function,
4289 * invoke radio enable/disable after updating hwradio status
4290 */
4291static void brcms_c_radio_upd(struct brcms_c_info *wlc)
4292{
4293 if (wlc->pub->radio_disabled)
4294 brcms_c_radio_disable(wlc);
4295 else
4296 brcms_c_radio_enable(wlc);
4297}
4298
4299/* update hwradio status and return it */
4300bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4301{
4302 brcms_c_radio_hwdisable_upd(wlc);
4303
4304 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4305 true : false;
4306}
4307
4308/* periodical query hw radio button while driver is "down" */
4309static void brcms_c_radio_timer(void *arg)
4310{
4311 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4312
4313 if (brcms_deviceremoved(wlc)) {
4314 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4315 __func__);
4316 brcms_down(wlc->wl);
4317 return;
4318 }
4319
4320 /* cap mpc off count */
4321 if (wlc->mpc_offcnt < BRCMS_MPC_MAX_DELAYCNT)
4322 wlc->mpc_offcnt++;
4323
4324 brcms_c_radio_hwdisable_upd(wlc);
4325 brcms_c_radio_upd(wlc);
4326}
4327
4328/* common low-level watchdog code */
4329static void brcms_b_watchdog(void *arg)
4330{
4331 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4332 struct brcms_hardware *wlc_hw = wlc->hw;
4333
4334 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
4335
4336 if (!wlc_hw->up)
4337 return;
4338
4339 /* increment second count */
4340 wlc_hw->now++;
4341
4342 /* Check for FIFO error interrupts */
4343 brcms_b_fifoerrors(wlc_hw);
4344
4345 /* make sure RX dma has buffers */
4346 dma_rxfill(wlc->hw->di[RX_FIFO]);
4347
4348 wlc_phy_watchdog(wlc_hw->band->pi);
4349}
4350
4351/* common watchdog code */
4352static void brcms_c_watchdog(void *arg)
4353{
4354 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4355
4356 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4357
4358 if (!wlc->pub->up)
4359 return;
4360
4361 if (brcms_deviceremoved(wlc)) {
4362 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4363 __func__);
4364 brcms_down(wlc->wl);
4365 return;
4366 }
4367
4368 /* increment second count */
4369 wlc->pub->now++;
4370
4371 /* delay radio disable */
4372 if (wlc->mpc_delay_off) {
4373 if (--wlc->mpc_delay_off == 0) {
4374 mboolset(wlc->pub->radio_disabled,
4375 WL_RADIO_MPC_DISABLE);
4376 if (wlc->mpc && brcms_c_ismpc(wlc))
4377 wlc->mpc_offcnt = 0;
4378 }
4379 }
4380
4381 /* mpc sync */
4382 brcms_c_radio_mpc_upd(wlc);
4383 /* radio sync: sw/hw/mpc --> radio_disable/radio_enable */
4384 brcms_c_radio_hwdisable_upd(wlc);
4385 brcms_c_radio_upd(wlc);
4386 /* if radio is disable, driver may be down, quit here */
4387 if (wlc->pub->radio_disabled)
4388 return;
4389
4390 brcms_b_watchdog(wlc);
4391
4392 /*
4393 * occasionally sample mac stat counters to
4394 * detect 16-bit counter wrap
4395 */
4396 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4397 brcms_c_statsupd(wlc);
4398
4399 if (BRCMS_ISNPHY(wlc->band) &&
4400 ((wlc->pub->now - wlc->tempsense_lasttime) >=
4401 BRCMS_TEMPSENSE_PERIOD)) {
4402 wlc->tempsense_lasttime = wlc->pub->now;
4403 brcms_c_tempsense_upd(wlc);
4404 }
4405}
4406
4407static void brcms_c_watchdog_by_timer(void *arg)
4408{
4409 brcms_c_watchdog(arg);
4410}
4411
4412bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4413{
4414 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4415 wlc, "watchdog");
4416 if (!wlc->wdtimer) {
4417 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
4418 "failed\n", unit);
4419 goto fail;
4420 }
4421
4422 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4423 wlc, "radio");
4424 if (!wlc->radio_timer) {
4425 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
4426 "failed\n", unit);
4427 goto fail;
4428 }
4429
4430 return true;
4431
4432 fail:
4433 return false;
4434}
4435
4436/*
4437 * Initialize brcms_c_info default values ...
4438 * may get overrides later in this function
4439 */
4440void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4441{
4442 int i;
4443
4444 /* Save our copy of the chanspec */
4445 wlc->chanspec = ch20mhz_chspec(1);
4446
4447 /* various 802.11g modes */
4448 wlc->shortslot = false;
4449 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4450
4451 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4452 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4453
4454 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4455 BRCMS_PROTECTION_AUTO);
4456 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4457 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4458 BRCMS_PROTECTION_AUTO);
4459 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4460 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4461
4462 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4463 BRCMS_PROTECTION_CTL_OVERLAP);
4464
4465 /* 802.11g draft 4.0 NonERP elt advertisement */
4466 wlc->include_legacy_erp = true;
4467
4468 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4469 wlc->stf->txant = ANT_TX_DEF;
4470
4471 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4472
4473 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4474 for (i = 0; i < NFIFO; i++)
4475 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4476 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4477
4478 /* default rate fallback retry limits */
4479 wlc->SFBL = RETRY_SHORT_FB;
4480 wlc->LFBL = RETRY_LONG_FB;
4481
4482 /* default mac retry limits */
4483 wlc->SRL = RETRY_SHORT_DEF;
4484 wlc->LRL = RETRY_LONG_DEF;
4485
4486 /* WME QoS mode is Auto by default */
4487 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4488 wlc->pub->bcmerror = 0;
4489
4490 /* initialize mpc delay */
4491 wlc->mpc_delay_off = wlc->mpc_dlycnt = BRCMS_MPC_MIN_DELAYCNT;
4492}
4493
4494static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4495{
4496 uint err = 0;
4497 uint unit;
4498 unit = wlc->pub->unit;
4499
4500 wlc->asi = brcms_c_antsel_attach(wlc);
4501 if (wlc->asi == NULL) {
4502 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4503 "failed\n", unit);
4504 err = 44;
4505 goto fail;
4506 }
4507
4508 wlc->ampdu = brcms_c_ampdu_attach(wlc);
4509 if (wlc->ampdu == NULL) {
4510 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4511 "failed\n", unit);
4512 err = 50;
4513 goto fail;
4514 }
4515
4516 if ((brcms_c_stf_attach(wlc) != 0)) {
4517 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4518 "failed\n", unit);
4519 err = 68;
4520 goto fail;
4521 }
4522 fail:
4523 return err;
4524}
4525
4526struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4527{
4528 return wlc->pub;
4529}
4530
4531/* low level attach
4532 * run backplane attach, init nvram
4533 * run phy attach
4534 * initialize software state for each core and band
4535 * put the whole chip in reset(driver down state), no clock
4536 */
4537static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
4538 uint unit, bool piomode, void __iomem *regsva,
4539 struct pci_dev *btparam)
4540{
4541 struct brcms_hardware *wlc_hw;
4542 struct d11regs __iomem *regs;
4543 char *macaddr = NULL;
4544 uint err = 0;
4545 uint j;
4546 bool wme = false;
4547 struct shared_phy_params sha_params;
4548 struct wiphy *wiphy = wlc->wiphy;
4549
4550 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
4551 device);
4552
4553 wme = true;
4554
4555 wlc_hw = wlc->hw;
4556 wlc_hw->wlc = wlc;
4557 wlc_hw->unit = unit;
4558 wlc_hw->band = wlc_hw->bandstate[0];
4559 wlc_hw->_piomode = piomode;
4560
4561 /* populate struct brcms_hardware with default values */
4562 brcms_b_info_init(wlc_hw);
4563
4564 /*
4565 * Do the hardware portion of the attach. Also initialize software
4566 * state that depends on the particular hardware we are running.
4567 */
4568 wlc_hw->sih = ai_attach(regsva, btparam);
4569 if (wlc_hw->sih == NULL) {
4570 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4571 unit);
4572 err = 11;
4573 goto fail;
4574 }
4575
4576 /* verify again the device is supported */
4577 if (!brcms_c_chipmatch(vendor, device)) {
4578 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
4579 "vendor/device (0x%x/0x%x)\n",
4580 unit, vendor, device);
4581 err = 12;
4582 goto fail;
4583 }
4584
4585 wlc_hw->vendorid = vendor;
4586 wlc_hw->deviceid = device;
4587
4588 /* set bar0 window to point at D11 core */
4589 wlc_hw->regs = (struct d11regs __iomem *)
4590 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
4591 wlc_hw->corerev = ai_corerev(wlc_hw->sih);
4592
4593 regs = wlc_hw->regs;
4594
4595 wlc->regs = wlc_hw->regs;
4596
4597 /* validate chip, chiprev and corerev */
4598 if (!brcms_c_isgoodchip(wlc_hw)) {
4599 err = 13;
4600 goto fail;
4601 }
4602
4603 /* initialize power control registers */
4604 ai_clkctl_init(wlc_hw->sih);
4605
4606 /* request fastclock and force fastclock for the rest of attach
4607 * bring the d11 core out of reset.
4608 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4609 * is still false; But it will be called again inside wlc_corereset,
4610 * after d11 is out of reset.
4611 */
4612 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
4613 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4614
4615 if (!brcms_b_validate_chip_access(wlc_hw)) {
4616 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4617 "failed\n", unit);
4618 err = 14;
4619 goto fail;
4620 }
4621
4622 /* get the board rev, used just below */
4623 j = getintvar(wlc_hw->sih, BRCMS_SROM_BOARDREV);
4624 /* promote srom boardrev of 0xFF to 1 */
4625 if (j == BOARDREV_PROMOTABLE)
4626 j = BOARDREV_PROMOTED;
4627 wlc_hw->boardrev = (u16) j;
4628 if (!brcms_c_validboardtype(wlc_hw)) {
4629 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4630 "board type (0x%x)" " or revision level (0x%x)\n",
4631 unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
4632 err = 15;
4633 goto fail;
4634 }
4635 wlc_hw->sromrev = (u8) getintvar(wlc_hw->sih, BRCMS_SROM_REV);
4636 wlc_hw->boardflags = (u32) getintvar(wlc_hw->sih,
4637 BRCMS_SROM_BOARDFLAGS);
4638 wlc_hw->boardflags2 = (u32) getintvar(wlc_hw->sih,
4639 BRCMS_SROM_BOARDFLAGS2);
4640
4641 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4642 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4643
4644 /* check device id(srom, nvram etc.) to set bands */
4645 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4646 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
4647 /* Dualband boards */
4648 wlc_hw->_nbands = 2;
4649 else
4650 wlc_hw->_nbands = 1;
4651
4652 if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
4653 wlc_hw->_nbands = 1;
4654
4655 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4656 * unconditionally does the init of these values
4657 */
4658 wlc->vendorid = wlc_hw->vendorid;
4659 wlc->deviceid = wlc_hw->deviceid;
4660 wlc->pub->sih = wlc_hw->sih;
4661 wlc->pub->corerev = wlc_hw->corerev;
4662 wlc->pub->sromrev = wlc_hw->sromrev;
4663 wlc->pub->boardrev = wlc_hw->boardrev;
4664 wlc->pub->boardflags = wlc_hw->boardflags;
4665 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4666 wlc->pub->_nbands = wlc_hw->_nbands;
4667
4668 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4669
4670 if (wlc_hw->physhim == NULL) {
4671 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4672 "failed\n", unit);
4673 err = 25;
4674 goto fail;
4675 }
4676
4677 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4678 sha_params.sih = wlc_hw->sih;
4679 sha_params.physhim = wlc_hw->physhim;
4680 sha_params.unit = unit;
4681 sha_params.corerev = wlc_hw->corerev;
4682 sha_params.vid = wlc_hw->vendorid;
4683 sha_params.did = wlc_hw->deviceid;
4684 sha_params.chip = wlc_hw->sih->chip;
4685 sha_params.chiprev = wlc_hw->sih->chiprev;
4686 sha_params.chippkg = wlc_hw->sih->chippkg;
4687 sha_params.sromrev = wlc_hw->sromrev;
4688 sha_params.boardtype = wlc_hw->sih->boardtype;
4689 sha_params.boardrev = wlc_hw->boardrev;
4690 sha_params.boardvendor = wlc_hw->sih->boardvendor;
4691 sha_params.boardflags = wlc_hw->boardflags;
4692 sha_params.boardflags2 = wlc_hw->boardflags2;
4693 sha_params.buscorerev = wlc_hw->sih->buscorerev;
4694
4695 /* alloc and save pointer to shared phy state area */
4696 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4697 if (!wlc_hw->phy_sh) {
4698 err = 16;
4699 goto fail;
4700 }
4701
4702 /* initialize software state for each core and band */
4703 for (j = 0; j < wlc_hw->_nbands; j++) {
4704 /*
4705 * band0 is always 2.4Ghz
4706 * band1, if present, is 5Ghz
4707 */
4708
4709 brcms_c_setxband(wlc_hw, j);
4710
4711 wlc_hw->band->bandunit = j;
4712 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4713 wlc->band->bandunit = j;
4714 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4715 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
4716
4717 wlc_hw->machwcap = R_REG(&regs->machwcap);
4718 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4719
4720 /* init tx fifo size */
4721 wlc_hw->xmtfifo_sz =
4722 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4723
4724 /* Get a phy for this band */
4725 wlc_hw->band->pi =
4726 wlc_phy_attach(wlc_hw->phy_sh, regs,
4727 wlc_hw->band->bandtype,
4728 wlc->wiphy);
4729 if (wlc_hw->band->pi == NULL) {
4730 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4731 "attach failed\n", unit);
4732 err = 17;
4733 goto fail;
4734 }
4735
4736 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4737
4738 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4739 &wlc_hw->band->phyrev,
4740 &wlc_hw->band->radioid,
4741 &wlc_hw->band->radiorev);
4742 wlc_hw->band->abgphy_encore =
4743 wlc_phy_get_encore(wlc_hw->band->pi);
4744 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4745 wlc_hw->band->core_flags =
4746 wlc_phy_get_coreflags(wlc_hw->band->pi);
4747
4748 /* verify good phy_type & supported phy revision */
4749 if (BRCMS_ISNPHY(wlc_hw->band)) {
4750 if (NCONF_HAS(wlc_hw->band->phyrev))
4751 goto good_phy;
4752 else
4753 goto bad_phy;
4754 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4755 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4756 goto good_phy;
4757 else
4758 goto bad_phy;
4759 } else {
4760 bad_phy:
4761 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4762 "phy type/rev (%d/%d)\n", unit,
4763 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4764 err = 18;
4765 goto fail;
4766 }
4767
4768 good_phy:
4769 /*
4770 * BMAC_NOTE: wlc->band->pi should not be set below and should
4771 * be done in the high level attach. However we can not make
4772 * that change until all low level access is changed to
4773 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4774 * keeping wlc_hw->band->pi as well for incremental update of
4775 * low level fns, and cut over low only init when all fns
4776 * updated.
4777 */
4778 wlc->band->pi = wlc_hw->band->pi;
4779 wlc->band->phytype = wlc_hw->band->phytype;
4780 wlc->band->phyrev = wlc_hw->band->phyrev;
4781 wlc->band->radioid = wlc_hw->band->radioid;
4782 wlc->band->radiorev = wlc_hw->band->radiorev;
4783
4784 /* default contention windows size limits */
4785 wlc_hw->band->CWmin = APHY_CWMIN;
4786 wlc_hw->band->CWmax = PHY_CWMAX;
4787
4788 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4789 err = 19;
4790 goto fail;
4791 }
4792 }
4793
4794 /* disable core to match driver "down" state */
4795 brcms_c_coredisable(wlc_hw);
4796
4797 /* Match driver "down" state */
4798 ai_pci_down(wlc_hw->sih);
4799
4800 /* register sb interrupt callback functions */
4801 ai_register_intr_callback(wlc_hw->sih, (void *)brcms_c_wlintrsoff,
4802 (void *)brcms_c_wlintrsrestore, NULL, wlc);
4803
4804 /* turn off pll and xtal to match driver "down" state */
4805 brcms_b_xtal(wlc_hw, OFF);
4806
4807 /* *******************************************************************
4808 * The hardware is in the DOWN state at this point. D11 core
4809 * or cores are in reset with clocks off, and the board PLLs
4810 * are off if possible.
4811 *
4812 * Beyond this point, wlc->sbclk == false and chip registers
4813 * should not be touched.
4814 *********************************************************************
4815 */
4816
4817 /* init etheraddr state variables */
4818 macaddr = brcms_c_get_macaddr(wlc_hw);
4819 if (macaddr == NULL) {
4820 wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n",
4821 unit);
4822 err = 21;
4823 goto fail;
4824 }
4825 if (!mac_pton(macaddr, wlc_hw->etheraddr) ||
4826 is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4827 is_zero_ether_addr(wlc_hw->etheraddr)) {
4828 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n",
4829 unit, macaddr);
4830 err = 22;
4831 goto fail;
4832 }
4833
4834 BCMMSG(wlc->wiphy,
4835 "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
4836 wlc_hw->deviceid, wlc_hw->_nbands,
4837 wlc_hw->sih->boardtype, macaddr);
4838
4839 return err;
4840
4841 fail:
4842 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4843 err);
4844 return err;
4845}
4846
4847static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4848{
4849 uint unit;
4850 unit = wlc->pub->unit;
4851
4852 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4853 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4854 wlc->band->antgain = 8;
4855 } else if (wlc->band->antgain == -1) {
4856 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4857 " srom, using 2dB\n", unit, __func__);
4858 wlc->band->antgain = 8;
4859 } else {
4860 s8 gain, fract;
4861 /* Older sroms specified gain in whole dbm only. In order
4862 * be able to specify qdbm granularity and remain backward
4863 * compatible the whole dbms are now encoded in only
4864 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4865 * 6 bit signed number ranges from -32 - 31.
4866 *
4867 * Examples:
4868 * 0x1 = 1 db,
4869 * 0xc1 = 1.75 db (1 + 3 quarters),
4870 * 0x3f = -1 (-1 + 0 quarters),
4871 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4872 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4873 */
4874 gain = wlc->band->antgain & 0x3f;
4875 gain <<= 2; /* Sign extend */
4876 gain >>= 2;
4877 fract = (wlc->band->antgain & 0xc0) >> 6;
4878 wlc->band->antgain = 4 * gain + fract;
4879 }
4880}
4881
4882static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4883{
4884 int aa;
4885 uint unit;
4886 int bandtype;
4887 struct si_pub *sih = wlc->hw->sih;
4888
4889 unit = wlc->pub->unit;
4890 bandtype = wlc->band->bandtype;
4891
4892 /* get antennas available */
4893 if (bandtype == BRCM_BAND_5G)
4894 aa = (s8) getintvar(sih, BRCMS_SROM_AA5G);
4895 else
4896 aa = (s8) getintvar(sih, BRCMS_SROM_AA2G);
4897
4898 if ((aa < 1) || (aa > 15)) {
4899 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4900 " srom (0x%x), using 3\n", unit, __func__, aa);
4901 aa = 3;
4902 }
4903
4904 /* reset the defaults if we have a single antenna */
4905 if (aa == 1) {
4906 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4907 wlc->stf->txant = ANT_TX_FORCE_0;
4908 } else if (aa == 2) {
4909 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4910 wlc->stf->txant = ANT_TX_FORCE_1;
4911 } else {
4912 }
4913
4914 /* Compute Antenna Gain */
4915 if (bandtype == BRCM_BAND_5G)
4916 wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG1);
4917 else
4918 wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG0);
4919
4920 brcms_c_attach_antgain_init(wlc);
4921
4922 return true;
4923}
4924
4925static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4926{
4927 u16 chanspec;
4928 struct brcms_band *band;
4929 struct brcms_bss_info *bi = wlc->default_bss;
4930
4931 /* init default and target BSS with some sane initial values */
4932 memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
4933 bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4934
4935 /* fill the default channel as the first valid channel
4936 * starting from the 2G channels
4937 */
4938 chanspec = ch20mhz_chspec(1);
4939 wlc->home_chanspec = bi->chanspec = chanspec;
4940
4941 /* find the band of our default channel */
4942 band = wlc->band;
4943 if (wlc->pub->_nbands > 1 &&
4944 band->bandunit != chspec_bandunit(chanspec))
4945 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4946
4947 /* init bss rates to the band specific default rate set */
4948 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4949 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4950 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4951 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4952
4953 if (wlc->pub->_n_enab & SUPPORT_11N)
4954 bi->flags |= BRCMS_BSS_HT;
4955}
4956
4957static struct brcms_txq_info *brcms_c_txq_alloc(struct brcms_c_info *wlc)
4958{
4959 struct brcms_txq_info *qi, *p;
4960
4961 qi = kzalloc(sizeof(struct brcms_txq_info), GFP_ATOMIC);
4962 if (qi != NULL) {
4963 /*
4964 * Have enough room for control packets along with HI watermark
4965 * Also, add room to txq for total psq packets if all the SCBs
4966 * leave PS mode. The watermark for flowcontrol to OS packets
4967 * will remain the same
4968 */
4969 brcmu_pktq_init(&qi->q, BRCMS_PREC_COUNT,
4970 2 * BRCMS_DATAHIWAT + PKTQ_LEN_DEFAULT);
4971
4972 /* add this queue to the the global list */
4973 p = wlc->tx_queues;
4974 if (p == NULL) {
4975 wlc->tx_queues = qi;
4976 } else {
4977 while (p->next != NULL)
4978 p = p->next;
4979 p->next = qi;
4980 }
4981 }
4982 return qi;
4983}
4984
4985static void brcms_c_txq_free(struct brcms_c_info *wlc,
4986 struct brcms_txq_info *qi)
4987{
4988 struct brcms_txq_info *p;
4989
4990 if (qi == NULL)
4991 return;
4992
4993 /* remove the queue from the linked list */
4994 p = wlc->tx_queues;
4995 if (p == qi)
4996 wlc->tx_queues = p->next;
4997 else {
4998 while (p != NULL && p->next != qi)
4999 p = p->next;
5000 if (p != NULL)
5001 p->next = p->next->next;
5002 }
5003
5004 kfree(qi);
5005}
5006
5007static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
5008{
5009 uint i;
5010 struct brcms_band *band;
5011
5012 for (i = 0; i < wlc->pub->_nbands; i++) {
5013 band = wlc->bandstate[i];
5014 if (band->bandtype == BRCM_BAND_5G) {
5015 if ((bwcap == BRCMS_N_BW_40ALL)
5016 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
5017 band->mimo_cap_40 = true;
5018 else
5019 band->mimo_cap_40 = false;
5020 } else {
5021 if (bwcap == BRCMS_N_BW_40ALL)
5022 band->mimo_cap_40 = true;
5023 else
5024 band->mimo_cap_40 = false;
5025 }
5026 }
5027}
5028
5029/*
5030 * The common driver entry routine. Error codes should be unique
5031 */
5032struct brcms_c_info *
5033brcms_c_attach(struct brcms_info *wl, u16 vendor, u16 device, uint unit,
5034 bool piomode, void __iomem *regsva, struct pci_dev *btparam,
5035 uint *perr)
5036{
5037 struct brcms_c_info *wlc;
5038 uint err = 0;
5039 uint i, j;
5040 struct brcms_pub *pub;
5041
5042 /* allocate struct brcms_c_info state and its substructures */
5043 wlc = (struct brcms_c_info *) brcms_c_attach_malloc(unit, &err, device);
5044 if (wlc == NULL)
5045 goto fail;
5046 wlc->wiphy = wl->wiphy;
5047 pub = wlc->pub;
5048
5049#if defined(BCMDBG)
5050 wlc_info_dbg = wlc;
5051#endif
5052
5053 wlc->band = wlc->bandstate[0];
5054 wlc->core = wlc->corestate;
5055 wlc->wl = wl;
5056 pub->unit = unit;
5057 pub->_piomode = piomode;
5058 wlc->bandinit_pending = false;
5059
5060 /* populate struct brcms_c_info with default values */
5061 brcms_c_info_init(wlc, unit);
5062
5063 /* update sta/ap related parameters */
5064 brcms_c_ap_upd(wlc);
5065
5066 /*
5067 * low level attach steps(all hw accesses go
5068 * inside, no more in rest of the attach)
5069 */
5070 err = brcms_b_attach(wlc, vendor, device, unit, piomode, regsva,
5071 btparam);
5072 if (err)
5073 goto fail;
5074
5075 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
5076
5077 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
5078
5079 /* disable allowed duty cycle */
5080 wlc->tx_duty_cycle_ofdm = 0;
5081 wlc->tx_duty_cycle_cck = 0;
5082
5083 brcms_c_stf_phy_chain_calc(wlc);
5084
5085 /* txchain 1: txant 0, txchain 2: txant 1 */
5086 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
5087 wlc->stf->txant = wlc->stf->hw_txchain - 1;
5088
5089 /* push to BMAC driver */
5090 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
5091 wlc->stf->hw_rxchain);
5092
5093 /* pull up some info resulting from the low attach */
5094 for (i = 0; i < NFIFO; i++)
5095 wlc->core->txavail[i] = wlc->hw->txavail[i];
5096
5097 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
5098 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
5099
5100 for (j = 0; j < wlc->pub->_nbands; j++) {
5101 wlc->band = wlc->bandstate[j];
5102
5103 if (!brcms_c_attach_stf_ant_init(wlc)) {
5104 err = 24;
5105 goto fail;
5106 }
5107
5108 /* default contention windows size limits */
5109 wlc->band->CWmin = APHY_CWMIN;
5110 wlc->band->CWmax = PHY_CWMAX;
5111
5112 /* init gmode value */
5113 if (wlc->band->bandtype == BRCM_BAND_2G) {
5114 wlc->band->gmode = GMODE_AUTO;
5115 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
5116 wlc->band->gmode);
5117 }
5118
5119 /* init _n_enab supported mode */
5120 if (BRCMS_PHY_11N_CAP(wlc->band)) {
5121 pub->_n_enab = SUPPORT_11N;
5122 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
5123 ((pub->_n_enab ==
5124 SUPPORT_11N) ? WL_11N_2x2 :
5125 WL_11N_3x3));
5126 }
5127
5128 /* init per-band default rateset, depend on band->gmode */
5129 brcms_default_rateset(wlc, &wlc->band->defrateset);
5130
5131 /* fill in hw_rateset */
5132 brcms_c_rateset_filter(&wlc->band->defrateset,
5133 &wlc->band->hw_rateset, false,
5134 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
5135 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
5136 }
5137
5138 /*
5139 * update antenna config due to
5140 * wlc->stf->txant/txchain/ant_rx_ovr change
5141 */
5142 brcms_c_stf_phy_txant_upd(wlc);
5143
5144 /* attach each modules */
5145 err = brcms_c_attach_module(wlc);
5146 if (err != 0)
5147 goto fail;
5148
5149 if (!brcms_c_timers_init(wlc, unit)) {
5150 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
5151 __func__);
5152 err = 32;
5153 goto fail;
5154 }
5155
5156 /* depend on rateset, gmode */
5157 wlc->cmi = brcms_c_channel_mgr_attach(wlc);
5158 if (!wlc->cmi) {
5159 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
5160 "\n", unit, __func__);
5161 err = 33;
5162 goto fail;
5163 }
5164
5165 /* init default when all parameters are ready, i.e. ->rateset */
5166 brcms_c_bss_default_init(wlc);
5167
5168 /*
5169 * Complete the wlc default state initializations..
5170 */
5171
5172 /* allocate our initial queue */
5173 wlc->pkt_queue = brcms_c_txq_alloc(wlc);
5174 if (wlc->pkt_queue == NULL) {
5175 wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n",
5176 unit, __func__);
5177 err = 100;
5178 goto fail;
5179 }
5180
5181 wlc->bsscfg->wlc = wlc;
5182
5183 wlc->mimoft = FT_HT;
5184 wlc->mimo_40txbw = AUTO;
5185 wlc->ofdm_40txbw = AUTO;
5186 wlc->cck_40txbw = AUTO;
5187 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
5188
5189 /* Set default values of SGI */
5190 if (BRCMS_SGI_CAP_PHY(wlc)) {
5191 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
5192 BRCMS_N_SGI_40));
5193 } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
5194 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
5195 BRCMS_N_SGI_40));
5196 } else {
5197 brcms_c_ht_update_sgi_rx(wlc, 0);
5198 }
5199
5200 /* initialize radio_mpc_disable according to wlc->mpc */
5201 brcms_c_radio_mpc_upd(wlc);
5202 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
5203
5204 if (perr)
5205 *perr = 0;
5206
5207 return wlc;
5208
5209 fail:
5210 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
5211 unit, __func__, err);
5212 if (wlc)
5213 brcms_c_detach(wlc);
5214
5215 if (perr)
5216 *perr = err;
5217 return NULL;
5218}
5219
5220static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
5221{
5222 /* free timer state */
5223 if (wlc->wdtimer) {
5224 brcms_free_timer(wlc->wl, wlc->wdtimer);
5225 wlc->wdtimer = NULL;
5226 }
5227 if (wlc->radio_timer) {
5228 brcms_free_timer(wlc->wl, wlc->radio_timer);
5229 wlc->radio_timer = NULL;
5230 }
5231}
5232
5233static void brcms_c_detach_module(struct brcms_c_info *wlc)
5234{
5235 if (wlc->asi) {
5236 brcms_c_antsel_detach(wlc->asi);
5237 wlc->asi = NULL;
5238 }
5239
5240 if (wlc->ampdu) {
5241 brcms_c_ampdu_detach(wlc->ampdu);
5242 wlc->ampdu = NULL;
5243 }
5244
5245 brcms_c_stf_detach(wlc);
5246}
5247
5248/*
5249 * low level detach
5250 */
5251static int brcms_b_detach(struct brcms_c_info *wlc)
5252{
5253 uint i;
5254 struct brcms_hw_band *band;
5255 struct brcms_hardware *wlc_hw = wlc->hw;
5256 int callbacks;
5257
5258 callbacks = 0;
5259
5260 if (wlc_hw->sih) {
5261 /*
5262 * detach interrupt sync mechanism since interrupt is disabled
5263 * and per-port interrupt object may has been freed. this must
5264 * be done before sb core switch
5265 */
5266 ai_deregister_intr_callback(wlc_hw->sih);
5267 ai_pci_sleep(wlc_hw->sih);
5268 }
5269
5270 brcms_b_detach_dmapio(wlc_hw);
5271
5272 band = wlc_hw->band;
5273 for (i = 0; i < wlc_hw->_nbands; i++) {
5274 if (band->pi) {
5275 /* Detach this band's phy */
5276 wlc_phy_detach(band->pi);
5277 band->pi = NULL;
5278 }
5279 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
5280 }
5281
5282 /* Free shared phy state */
5283 kfree(wlc_hw->phy_sh);
5284
5285 wlc_phy_shim_detach(wlc_hw->physhim);
5286
5287 if (wlc_hw->sih) {
5288 ai_detach(wlc_hw->sih);
5289 wlc_hw->sih = NULL;
5290 }
5291
5292 return callbacks;
5293
5294}
5295
5296/*
5297 * Return a count of the number of driver callbacks still pending.
5298 *
5299 * General policy is that brcms_c_detach can only dealloc/free software states.
5300 * It can NOT touch hardware registers since the d11core may be in reset and
5301 * clock may not be available.
5302 * One exception is sb register access, which is possible if crystal is turned
5303 * on after "down" state, driver should avoid software timer with the exception
5304 * of radio_monitor.
5305 */
5306uint brcms_c_detach(struct brcms_c_info *wlc)
5307{
5308 uint callbacks = 0;
5309
5310 if (wlc == NULL)
5311 return 0;
5312
5313 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5314
5315 callbacks += brcms_b_detach(wlc);
5316
5317 /* delete software timers */
5318 if (!brcms_c_radio_monitor_stop(wlc))
5319 callbacks++;
5320
5321 brcms_c_channel_mgr_detach(wlc->cmi);
5322
5323 brcms_c_timers_deinit(wlc);
5324
5325 brcms_c_detach_module(wlc);
5326
5327
5328 while (wlc->tx_queues != NULL)
5329 brcms_c_txq_free(wlc, wlc->tx_queues);
5330
5331 brcms_c_detach_mfree(wlc);
5332 return callbacks;
5333}
5334
5335/* update state that depends on the current value of "ap" */
5336void brcms_c_ap_upd(struct brcms_c_info *wlc)
5337{
5338 /* STA-BSS; short capable */
5339 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
5340
5341 /* fixup mpc */
5342 wlc->mpc = true;
5343}
5344
5345/*
5346 * return true if Minimum Power Consumption should
5347 * be entered, false otherwise
5348 */
5349bool brcms_c_is_non_delay_mpc(struct brcms_c_info *wlc)
5350{
5351 return false;
5352}
5353
5354bool brcms_c_ismpc(struct brcms_c_info *wlc)
5355{
5356 return (wlc->mpc_delay_off == 0) && (brcms_c_is_non_delay_mpc(wlc));
5357}
5358
5359void brcms_c_radio_mpc_upd(struct brcms_c_info *wlc)
5360{
5361 bool mpc_radio, radio_state;
5362
5363 /*
5364 * Clear the WL_RADIO_MPC_DISABLE bit when mpc feature is disabled
5365 * in case the WL_RADIO_MPC_DISABLE bit was set. Stop the radio
5366 * monitor also when WL_RADIO_MPC_DISABLE is the only reason that
5367 * the radio is going down.
5368 */
5369 if (!wlc->mpc) {
5370 if (!wlc->pub->radio_disabled)
5371 return;
5372 mboolclr(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE);
5373 brcms_c_radio_upd(wlc);
5374 if (!wlc->pub->radio_disabled)
5375 brcms_c_radio_monitor_stop(wlc);
5376 return;
5377 }
5378
5379 /*
5380 * sync ismpc logic with WL_RADIO_MPC_DISABLE bit in
5381 * wlc->pub->radio_disabled to go ON, always call radio_upd
5382 * synchronously to go OFF, postpone radio_upd to later when
5383 * context is safe(e.g. watchdog)
5384 */
5385 radio_state =
5386 (mboolisset(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE) ? OFF :
5387 ON);
5388 mpc_radio = (brcms_c_ismpc(wlc) == true) ? OFF : ON;
5389
5390 if (radio_state == ON && mpc_radio == OFF)
5391 wlc->mpc_delay_off = wlc->mpc_dlycnt;
5392 else if (radio_state == OFF && mpc_radio == ON) {
5393 mboolclr(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE);
5394 brcms_c_radio_upd(wlc);
5395 if (wlc->mpc_offcnt < BRCMS_MPC_THRESHOLD)
5396 wlc->mpc_dlycnt = BRCMS_MPC_MAX_DELAYCNT;
5397 else
5398 wlc->mpc_dlycnt = BRCMS_MPC_MIN_DELAYCNT;
5399 }
5400 /*
5401 * Below logic is meant to capture the transition from mpc off
5402 * to mpc on for reasons other than wlc->mpc_delay_off keeping
5403 * the mpc off. In that case reset wlc->mpc_delay_off to
5404 * wlc->mpc_dlycnt, so that we restart the countdown of mpc_delay_off
5405 */
5406 if ((wlc->prev_non_delay_mpc == false) &&
5407 (brcms_c_is_non_delay_mpc(wlc) == true) && wlc->mpc_delay_off)
5408 wlc->mpc_delay_off = wlc->mpc_dlycnt;
5409
5410 wlc->prev_non_delay_mpc = brcms_c_is_non_delay_mpc(wlc);
5411}
5412/* Initialize just the hardware when coming out of POR or S3/S5 system states */
5413static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
5414{
5415 if (wlc_hw->wlc->pub->hw_up)
5416 return;
5417
5418 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5419
5420 /*
5421 * Enable pll and xtal, initialize the power control registers,
5422 * and force fastclock for the remainder of brcms_c_up().
5423 */
5424 brcms_b_xtal(wlc_hw, ON);
5425 ai_clkctl_init(wlc_hw->sih);
5426 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
5427
5428 ai_pci_fixcfg(wlc_hw->sih);
5429
5430 /*
5431 * AI chip doesn't restore bar0win2 on
5432 * hibernation/resume, need sw fixup
5433 */
5434 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
5435 (wlc_hw->sih->chip == BCM43225_CHIP_ID))
5436 wlc_hw->regs = (struct d11regs __iomem *)
5437 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
5438
5439 /*
5440 * Inform phy that a POR reset has occurred so
5441 * it does a complete phy init
5442 */
5443 wlc_phy_por_inform(wlc_hw->band->pi);
5444
5445 wlc_hw->ucode_loaded = false;
5446 wlc_hw->wlc->pub->hw_up = true;
5447
5448 if ((wlc_hw->boardflags & BFL_FEM)
5449 && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
5450 if (!
5451 (wlc_hw->boardrev >= 0x1250
5452 && (wlc_hw->boardflags & BFL_FEM_BT)))
5453 ai_epa_4313war(wlc_hw->sih);
5454 }
5455}
5456
5457static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
5458{
5459 uint coremask;
5460
5461 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5462
5463 /*
5464 * Enable pll and xtal, initialize the power control registers,
5465 * and force fastclock for the remainder of brcms_c_up().
5466 */
5467 brcms_b_xtal(wlc_hw, ON);
5468 ai_clkctl_init(wlc_hw->sih);
5469 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
5470
5471 /*
5472 * Configure pci/pcmcia here instead of in brcms_c_attach()
5473 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
5474 */
5475 coremask = (1 << wlc_hw->wlc->core->coreidx);
5476
5477 ai_pci_setup(wlc_hw->sih, coremask);
5478
5479 /*
5480 * Need to read the hwradio status here to cover the case where the
5481 * system is loaded with the hw radio disabled. We do not want to
5482 * bring the driver up in this case.
5483 */
5484 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
5485 /* put SB PCI in down state again */
5486 ai_pci_down(wlc_hw->sih);
5487 brcms_b_xtal(wlc_hw, OFF);
5488 return -ENOMEDIUM;
5489 }
5490
5491 ai_pci_up(wlc_hw->sih);
5492
5493 /* reset the d11 core */
5494 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5495
5496 return 0;
5497}
5498
5499static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5500{
5501 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5502
5503 wlc_hw->up = true;
5504 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5505
5506 /* FULLY enable dynamic power control and d11 core interrupt */
5507 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
5508 brcms_intrson(wlc_hw->wlc->wl);
5509 return 0;
5510}
5511
5512/*
5513 * Write WME tunable parameters for retransmit/max rate
5514 * from wlc struct to ucode
5515 */
5516static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5517{
5518 int ac;
5519
5520 /* Need clock to do this */
5521 if (!wlc->clk)
5522 return;
5523
5524 for (ac = 0; ac < AC_COUNT; ac++)
5525 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5526 wlc->wme_retries[ac]);
5527}
5528
5529/* make interface operational */
5530int brcms_c_up(struct brcms_c_info *wlc)
5531{
5532 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5533
5534 /* HW is turned off so don't try to access it */
5535 if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5536 return -ENOMEDIUM;
5537
5538 if (!wlc->pub->hw_up) {
5539 brcms_b_hw_up(wlc->hw);
5540 wlc->pub->hw_up = true;
5541 }
5542
5543 if ((wlc->pub->boardflags & BFL_FEM)
5544 && (wlc->pub->sih->chip == BCM4313_CHIP_ID)) {
5545 if (wlc->pub->boardrev >= 0x1250
5546 && (wlc->pub->boardflags & BFL_FEM_BT))
5547 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5548 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5549 else
5550 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5551 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5552 }
5553
5554 /*
5555 * Need to read the hwradio status here to cover the case where the
5556 * system is loaded with the hw radio disabled. We do not want to bring
5557 * the driver up in this case. If radio is disabled, abort up, lower
5558 * power, start radio timer and return 0(for NDIS) don't call
5559 * radio_update to avoid looping brcms_c_up.
5560 *
5561 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5562 */
5563 if (!wlc->pub->radio_disabled) {
5564 int status = brcms_b_up_prep(wlc->hw);
5565 if (status == -ENOMEDIUM) {
5566 if (!mboolisset
5567 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5568 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5569 mboolset(wlc->pub->radio_disabled,
5570 WL_RADIO_HW_DISABLE);
5571
5572 if (bsscfg->enable && bsscfg->BSS)
5573 wiphy_err(wlc->wiphy, "wl%d: up"
5574 ": rfdisable -> "
5575 "bsscfg_disable()\n",
5576 wlc->pub->unit);
5577 }
5578 }
5579 }
5580
5581 if (wlc->pub->radio_disabled) {
5582 brcms_c_radio_monitor_start(wlc);
5583 return 0;
5584 }
5585
5586 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5587 wlc->clk = true;
5588
5589 brcms_c_radio_monitor_stop(wlc);
5590
5591 /* Set EDCF hostflags */
5592 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5593
5594 brcms_init(wlc->wl);
5595 wlc->pub->up = true;
5596
5597 if (wlc->bandinit_pending) {
5598 brcms_c_suspend_mac_and_wait(wlc);
5599 brcms_c_set_chanspec(wlc, wlc->default_bss->chanspec);
5600 wlc->bandinit_pending = false;
5601 brcms_c_enable_mac(wlc);
5602 }
5603
5604 brcms_b_up_finish(wlc->hw);
5605
5606 /* Program the TX wme params with the current settings */
5607 brcms_c_wme_retries_write(wlc);
5608
5609 /* start one second watchdog timer */
5610 brcms_add_timer(wlc->wl, wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5611 wlc->WDarmed = true;
5612
5613 /* ensure antenna config is up to date */
5614 brcms_c_stf_phy_txant_upd(wlc);
5615 /* ensure LDPC config is in sync */
5616 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5617
5618 return 0;
5619}
5620
5621static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5622{
5623 uint callbacks = 0;
5624
5625 return callbacks;
5626}
5627
5628static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5629{
5630 bool dev_gone;
5631 uint callbacks = 0;
5632
5633 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5634
5635 if (!wlc_hw->up)
5636 return callbacks;
5637
5638 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5639
5640 /* disable interrupts */
5641 if (dev_gone)
5642 wlc_hw->wlc->macintmask = 0;
5643 else {
5644 /* now disable interrupts */
5645 brcms_intrsoff(wlc_hw->wlc->wl);
5646
5647 /* ensure we're running on the pll clock again */
5648 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
5649 }
5650 /* down phy at the last of this stage */
5651 callbacks += wlc_phy_down(wlc_hw->band->pi);
5652
5653 return callbacks;
5654}
5655
5656static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5657{
5658 uint callbacks = 0;
5659 bool dev_gone;
5660
5661 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5662
5663 if (!wlc_hw->up)
5664 return callbacks;
5665
5666 wlc_hw->up = false;
5667 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5668
5669 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5670
5671 if (dev_gone) {
5672 wlc_hw->sbclk = false;
5673 wlc_hw->clk = false;
5674 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5675
5676 /* reclaim any posted packets */
5677 brcms_c_flushqueues(wlc_hw->wlc);
5678 } else {
5679
5680 /* Reset and disable the core */
5681 if (ai_iscoreup(wlc_hw->sih)) {
5682 if (R_REG(&wlc_hw->regs->maccontrol) &
5683 MCTL_EN_MAC)
5684 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5685 callbacks += brcms_reset(wlc_hw->wlc->wl);
5686 brcms_c_coredisable(wlc_hw);
5687 }
5688
5689 /* turn off primary xtal and pll */
5690 if (!wlc_hw->noreset) {
5691 ai_pci_down(wlc_hw->sih);
5692 brcms_b_xtal(wlc_hw, OFF);
5693 }
5694 }
5695
5696 return callbacks;
5697}
5698
5699/*
5700 * Mark the interface nonoperational, stop the software mechanisms,
5701 * disable the hardware, free any transient buffer state.
5702 * Return a count of the number of driver callbacks still pending.
5703 */
5704uint brcms_c_down(struct brcms_c_info *wlc)
5705{
5706
5707 uint callbacks = 0;
5708 int i;
5709 bool dev_gone = false;
5710 struct brcms_txq_info *qi;
5711
5712 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5713
5714 /* check if we are already in the going down path */
5715 if (wlc->going_down) {
5716 wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
5717 "\n", wlc->pub->unit, __func__);
5718 return 0;
5719 }
5720 if (!wlc->pub->up)
5721 return callbacks;
5722
5723 /* in between, mpc could try to bring down again.. */
5724 wlc->going_down = true;
5725
5726 callbacks += brcms_b_bmac_down_prep(wlc->hw);
5727
5728 dev_gone = brcms_deviceremoved(wlc);
5729
5730 /* Call any registered down handlers */
5731 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5732 if (wlc->modulecb[i].down_fn)
5733 callbacks +=
5734 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5735 }
5736
5737 /* cancel the watchdog timer */
5738 if (wlc->WDarmed) {
5739 if (!brcms_del_timer(wlc->wl, wlc->wdtimer))
5740 callbacks++;
5741 wlc->WDarmed = false;
5742 }
5743 /* cancel all other timers */
5744 callbacks += brcms_c_down_del_timer(wlc);
5745
5746 wlc->pub->up = false;
5747
5748 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5749
5750 /* clear txq flow control */
5751 brcms_c_txflowcontrol_reset(wlc);
5752
5753 /* flush tx queues */
5754 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next)
5755 brcmu_pktq_flush(&qi->q, true, NULL, NULL);
5756
5757 callbacks += brcms_b_down_finish(wlc->hw);
5758
5759 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5760 wlc->clk = false;
5761
5762 wlc->going_down = false;
5763 return callbacks;
5764}
5765
5766/* Set the current gmode configuration */
5767int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5768{
5769 int ret = 0;
5770 uint i;
5771 struct brcms_c_rateset rs;
5772 /* Default to 54g Auto */
5773 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5774 s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5775 bool shortslot_restrict = false; /* Restrict association to stations
5776 * that support shortslot
5777 */
5778 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
5779 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5780 int preamble = BRCMS_PLCP_LONG;
5781 bool preamble_restrict = false; /* Restrict association to stations
5782 * that support short preambles
5783 */
5784 struct brcms_band *band;
5785
5786 /* if N-support is enabled, allow Gmode set as long as requested
5787 * Gmode is not GMODE_LEGACY_B
5788 */
5789 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5790 return -ENOTSUPP;
5791
5792 /* verify that we are dealing with 2G band and grab the band pointer */
5793 if (wlc->band->bandtype == BRCM_BAND_2G)
5794 band = wlc->band;
5795 else if ((wlc->pub->_nbands > 1) &&
5796 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5797 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5798 else
5799 return -EINVAL;
5800
5801 /* Legacy or bust when no OFDM is supported by regulatory */
5802 if ((brcms_c_channel_locale_flags_in_band(wlc->cmi, band->bandunit) &
5803 BRCMS_NO_OFDM) && (gmode != GMODE_LEGACY_B))
5804 return -EINVAL;
5805
5806 /* update configuration value */
5807 if (config == true)
5808 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5809
5810 /* Clear rateset override */
5811 memset(&rs, 0, sizeof(struct brcms_c_rateset));
5812
5813 switch (gmode) {
5814 case GMODE_LEGACY_B:
5815 shortslot = BRCMS_SHORTSLOT_OFF;
5816 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5817
5818 break;
5819
5820 case GMODE_LRS:
5821 break;
5822
5823 case GMODE_AUTO:
5824 /* Accept defaults */
5825 break;
5826
5827 case GMODE_ONLY:
5828 ofdm_basic = true;
5829 preamble = BRCMS_PLCP_SHORT;
5830 preamble_restrict = true;
5831 break;
5832
5833 case GMODE_PERFORMANCE:
5834 shortslot = BRCMS_SHORTSLOT_ON;
5835 shortslot_restrict = true;
5836 ofdm_basic = true;
5837 preamble = BRCMS_PLCP_SHORT;
5838 preamble_restrict = true;
5839 break;
5840
5841 default:
5842 /* Error */
5843 wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
5844 wlc->pub->unit, __func__, gmode);
5845 return -ENOTSUPP;
5846 }
5847
5848 band->gmode = gmode;
5849
5850 wlc->shortslot_override = shortslot;
5851
5852 /* Use the default 11g rateset */
5853 if (!rs.count)
5854 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5855
5856 if (ofdm_basic) {
5857 for (i = 0; i < rs.count; i++) {
5858 if (rs.rates[i] == BRCM_RATE_6M
5859 || rs.rates[i] == BRCM_RATE_12M
5860 || rs.rates[i] == BRCM_RATE_24M)
5861 rs.rates[i] |= BRCMS_RATE_FLAG;
5862 }
5863 }
5864
5865 /* Set default bss rateset */
5866 wlc->default_bss->rateset.count = rs.count;
5867 memcpy(wlc->default_bss->rateset.rates, rs.rates,
5868 sizeof(wlc->default_bss->rateset.rates));
5869
5870 return ret;
5871}
5872
5873int brcms_c_set_nmode(struct brcms_c_info *wlc)
5874{
5875 uint i;
5876 s32 nmode = AUTO;
5877
5878 if (wlc->stf->txstreams == WL_11N_3x3)
5879 nmode = WL_11N_3x3;
5880 else
5881 nmode = WL_11N_2x2;
5882
5883 /* force GMODE_AUTO if NMODE is ON */
5884 brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5885 if (nmode == WL_11N_3x3)
5886 wlc->pub->_n_enab = SUPPORT_HT;
5887 else
5888 wlc->pub->_n_enab = SUPPORT_11N;
5889 wlc->default_bss->flags |= BRCMS_BSS_HT;
5890 /* add the mcs rates to the default and hw ratesets */
5891 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5892 wlc->stf->txstreams);
5893 for (i = 0; i < wlc->pub->_nbands; i++)
5894 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5895 wlc->default_bss->rateset.mcs, MCSSET_LEN);
5896
5897 return 0;
5898}
5899
5900static int
5901brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5902 struct brcms_c_rateset *rs_arg)
5903{
5904 struct brcms_c_rateset rs, new;
5905 uint bandunit;
5906
5907 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5908
5909 /* check for bad count value */
5910 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5911 return -EINVAL;
5912
5913 /* try the current band */
5914 bandunit = wlc->band->bandunit;
5915 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5916 if (brcms_c_rate_hwrs_filter_sort_validate
5917 (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5918 wlc->stf->txstreams))
5919 goto good;
5920
5921 /* try the other band */
5922 if (brcms_is_mband_unlocked(wlc)) {
5923 bandunit = OTHERBANDUNIT(wlc);
5924 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5925 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5926 &wlc->
5927 bandstate[bandunit]->
5928 hw_rateset, true,
5929 wlc->stf->txstreams))
5930 goto good;
5931 }
5932
5933 return -EBADE;
5934
5935 good:
5936 /* apply new rateset */
5937 memcpy(&wlc->default_bss->rateset, &new,
5938 sizeof(struct brcms_c_rateset));
5939 memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5940 sizeof(struct brcms_c_rateset));
5941 return 0;
5942}
5943
5944static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5945{
5946 u8 r;
5947 bool war = false;
5948
5949 if (wlc->bsscfg->associated)
5950 r = wlc->bsscfg->current_bss->rateset.rates[0];
5951 else
5952 r = wlc->default_bss->rateset.rates[0];
5953
5954 wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5955}
5956
5957int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5958{
5959 u16 chspec = ch20mhz_chspec(channel);
5960
5961 if (channel < 0 || channel > MAXCHANNEL)
5962 return -EINVAL;
5963
5964 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5965 return -EINVAL;
5966
5967
5968 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5969 if (wlc->band->bandunit != chspec_bandunit(chspec))
5970 wlc->bandinit_pending = true;
5971 else
5972 wlc->bandinit_pending = false;
5973 }
5974
5975 wlc->default_bss->chanspec = chspec;
5976 /* brcms_c_BSSinit() will sanitize the rateset before
5977 * using it.. */
5978 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5979 brcms_c_set_home_chanspec(wlc, chspec);
5980 brcms_c_suspend_mac_and_wait(wlc);
5981 brcms_c_set_chanspec(wlc, chspec);
5982 brcms_c_enable_mac(wlc);
5983 }
5984 return 0;
5985}
5986
5987int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5988{
5989 int ac;
5990
5991 if (srl < 1 || srl > RETRY_SHORT_MAX ||
5992 lrl < 1 || lrl > RETRY_SHORT_MAX)
5993 return -EINVAL;
5994
5995 wlc->SRL = srl;
5996 wlc->LRL = lrl;
5997
5998 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5999
6000 for (ac = 0; ac < AC_COUNT; ac++) {
6001 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
6002 EDCF_SHORT, wlc->SRL);
6003 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
6004 EDCF_LONG, wlc->LRL);
6005 }
6006 brcms_c_wme_retries_write(wlc);
6007
6008 return 0;
6009}
6010
6011void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
6012 struct brcm_rateset *currs)
6013{
6014 struct brcms_c_rateset *rs;
6015
6016 if (wlc->pub->associated)
6017 rs = &wlc->bsscfg->current_bss->rateset;
6018 else
6019 rs = &wlc->default_bss->rateset;
6020
6021 /* Copy only legacy rateset section */
6022 currs->count = rs->count;
6023 memcpy(&currs->rates, &rs->rates, rs->count);
6024}
6025
6026int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
6027{
6028 struct brcms_c_rateset internal_rs;
6029 int bcmerror;
6030
6031 if (rs->count > BRCMS_NUMRATES)
6032 return -ENOBUFS;
6033
6034 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
6035
6036 /* Copy only legacy rateset section */
6037 internal_rs.count = rs->count;
6038 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
6039
6040 /* merge rateset coming in with the current mcsset */
6041 if (wlc->pub->_n_enab & SUPPORT_11N) {
6042 struct brcms_bss_info *mcsset_bss;
6043 if (wlc->bsscfg->associated)
6044 mcsset_bss = wlc->bsscfg->current_bss;
6045 else
6046 mcsset_bss = wlc->default_bss;
6047 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
6048 MCSSET_LEN);
6049 }
6050
6051 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
6052 if (!bcmerror)
6053 brcms_c_ofdm_rateset_war(wlc);
6054
6055 return bcmerror;
6056}
6057
6058int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
6059{
6060 if (period < DOT11_MIN_BEACON_PERIOD ||
6061 period > DOT11_MAX_BEACON_PERIOD)
6062 return -EINVAL;
6063
6064 wlc->default_bss->beacon_period = period;
6065 return 0;
6066}
6067
6068u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
6069{
6070 return wlc->band->phytype;
6071}
6072
6073void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
6074{
6075 wlc->shortslot_override = sslot_override;
6076
6077 /*
6078 * shortslot is an 11g feature, so no more work if we are
6079 * currently on the 5G band
6080 */
6081 if (wlc->band->bandtype == BRCM_BAND_5G)
6082 return;
6083
6084 if (wlc->pub->up && wlc->pub->associated) {
6085 /* let watchdog or beacon processing update shortslot */
6086 } else if (wlc->pub->up) {
6087 /* unassociated shortslot is off */
6088 brcms_c_switch_shortslot(wlc, false);
6089 } else {
6090 /* driver is down, so just update the brcms_c_info
6091 * value */
6092 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
6093 wlc->shortslot = false;
6094 else
6095 wlc->shortslot =
6096 (wlc->shortslot_override ==
6097 BRCMS_SHORTSLOT_ON);
6098 }
6099}
6100
6101/*
6102 * register watchdog and down handlers.
6103 */
6104int brcms_c_module_register(struct brcms_pub *pub,
6105 const char *name, struct brcms_info *hdl,
6106 int (*d_fn)(void *handle))
6107{
6108 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
6109 int i;
6110
6111 /* find an empty entry and just add, no duplication check! */
6112 for (i = 0; i < BRCMS_MAXMODULES; i++) {
6113 if (wlc->modulecb[i].name[0] == '\0') {
6114 strncpy(wlc->modulecb[i].name, name,
6115 sizeof(wlc->modulecb[i].name) - 1);
6116 wlc->modulecb[i].hdl = hdl;
6117 wlc->modulecb[i].down_fn = d_fn;
6118 return 0;
6119 }
6120 }
6121
6122 return -ENOSR;
6123}
6124
6125/* unregister module callbacks */
6126int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
6127 struct brcms_info *hdl)
6128{
6129 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
6130 int i;
6131
6132 if (wlc == NULL)
6133 return -ENODATA;
6134
6135 for (i = 0; i < BRCMS_MAXMODULES; i++) {
6136 if (!strcmp(wlc->modulecb[i].name, name) &&
6137 (wlc->modulecb[i].hdl == hdl)) {
6138 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
6139 return 0;
6140 }
6141 }
6142
6143 /* table not found! */
6144 return -ENODATA;
6145}
6146
6147#ifdef BCMDBG
6148static const char * const supr_reason[] = {
6149 "None", "PMQ Entry", "Flush request",
6150 "Previous frag failure", "Channel mismatch",
6151 "Lifetime Expiry", "Underflow"
6152};
6153
6154static void brcms_c_print_txs_status(u16 s)
6155{
6156 printk(KERN_DEBUG "[15:12] %d frame attempts\n",
6157 (s & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT);
6158 printk(KERN_DEBUG " [11:8] %d rts attempts\n",
6159 (s & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT);
6160 printk(KERN_DEBUG " [7] %d PM mode indicated\n",
6161 ((s & TX_STATUS_PMINDCTD) ? 1 : 0));
6162 printk(KERN_DEBUG " [6] %d intermediate status\n",
6163 ((s & TX_STATUS_INTERMEDIATE) ? 1 : 0));
6164 printk(KERN_DEBUG " [5] %d AMPDU\n",
6165 (s & TX_STATUS_AMPDU) ? 1 : 0);
6166 printk(KERN_DEBUG " [4:2] %d Frame Suppressed Reason (%s)\n",
6167 ((s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT),
6168 supr_reason[(s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT]);
6169 printk(KERN_DEBUG " [1] %d acked\n",
6170 ((s & TX_STATUS_ACK_RCV) ? 1 : 0));
6171}
6172#endif /* BCMDBG */
6173
6174void brcms_c_print_txstatus(struct tx_status *txs)
6175{
6176#if defined(BCMDBG)
6177 u16 s = txs->status;
6178 u16 ackphyrxsh = txs->ackphyrxsh;
6179
6180 printk(KERN_DEBUG "\ntxpkt (MPDU) Complete\n");
6181
6182 printk(KERN_DEBUG "FrameID: %04x ", txs->frameid);
6183 printk(KERN_DEBUG "TxStatus: %04x", s);
6184 printk(KERN_DEBUG "\n");
6185
6186 brcms_c_print_txs_status(s);
6187
6188 printk(KERN_DEBUG "LastTxTime: %04x ", txs->lasttxtime);
6189 printk(KERN_DEBUG "Seq: %04x ", txs->sequence);
6190 printk(KERN_DEBUG "PHYTxStatus: %04x ", txs->phyerr);
6191 printk(KERN_DEBUG "RxAckRSSI: %04x ",
6192 (ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT);
6193 printk(KERN_DEBUG "RxAckSQ: %04x",
6194 (ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
6195 printk(KERN_DEBUG "\n");
6196#endif /* defined(BCMDBG) */
6197}
6198
6199void brcms_c_statsupd(struct brcms_c_info *wlc)
6200{
6201 int i;
6202 struct macstat macstats;
6203#ifdef BCMDBG
6204 u16 delta;
6205 u16 rxf0ovfl;
6206 u16 txfunfl[NFIFO];
6207#endif /* BCMDBG */
6208
6209 /* if driver down, make no sense to update stats */
6210 if (!wlc->pub->up)
6211 return;
6212
6213#ifdef BCMDBG
6214 /* save last rx fifo 0 overflow count */
6215 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
6216
6217 /* save last tx fifo underflow count */
6218 for (i = 0; i < NFIFO; i++)
6219 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
6220#endif /* BCMDBG */
6221
6222 /* Read mac stats from contiguous shared memory */
6223 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
6224 sizeof(struct macstat), OBJADDR_SHM_SEL);
6225
6226#ifdef BCMDBG
6227 /* check for rx fifo 0 overflow */
6228 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
6229 if (delta)
6230 wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
6231 wlc->pub->unit, delta);
6232
6233 /* check for tx fifo underflows */
6234 for (i = 0; i < NFIFO; i++) {
6235 delta =
6236 (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
6237 txfunfl[i]);
6238 if (delta)
6239 wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
6240 "\n", wlc->pub->unit, delta, i);
6241 }
6242#endif /* BCMDBG */
6243
6244 /* merge counters from dma module */
6245 for (i = 0; i < NFIFO; i++) {
6246 if (wlc->hw->di[i])
6247 dma_counterreset(wlc->hw->di[i]);
6248 }
6249}
6250
6251bool brcms_c_chipmatch(u16 vendor, u16 device)
6252{
6253 if (vendor != PCI_VENDOR_ID_BROADCOM) {
6254 pr_err("chipmatch: unknown vendor id %04x\n", vendor);
6255 return false;
6256 }
6257
6258 if (device == BCM43224_D11N_ID_VEN1)
6259 return true;
6260 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
6261 return true;
6262 if (device == BCM4313_D11N2G_ID)
6263 return true;
6264 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
6265 return true;
6266
6267 pr_err("chipmatch: unknown device id %04x\n", device);
6268 return false;
6269}
6270
6271#if defined(BCMDBG)
6272void brcms_c_print_txdesc(struct d11txh *txh)
6273{
6274 u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
6275 u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
6276 u16 mfc = le16_to_cpu(txh->MacFrameControl);
6277 u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
6278 u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
6279 u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
6280 u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
6281 u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
6282 u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
6283 u16 mainrates = le16_to_cpu(txh->MainRates);
6284 u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
6285 u8 *iv = txh->IV;
6286 u8 *ra = txh->TxFrameRA;
6287 u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
6288 u8 *rtspfb = txh->RTSPLCPFallback;
6289 u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
6290 u8 *fragpfb = txh->FragPLCPFallback;
6291 u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
6292 u16 mmodelen = le16_to_cpu(txh->MModeLen);
6293 u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
6294 u16 tfid = le16_to_cpu(txh->TxFrameID);
6295 u16 txs = le16_to_cpu(txh->TxStatus);
6296 u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
6297 u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
6298 u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
6299 u16 mmbyte = le16_to_cpu(txh->MinMBytes);
6300
6301 u8 *rtsph = txh->RTSPhyHeader;
6302 struct ieee80211_rts rts = txh->rts_frame;
6303 char hexbuf[256];
6304
6305 /* add plcp header along with txh descriptor */
6306 printk(KERN_DEBUG "Raw TxDesc + plcp header:\n");
6307 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
6308 txh, sizeof(struct d11txh) + 48);
6309
6310 printk(KERN_DEBUG "TxCtlLow: %04x ", mtcl);
6311 printk(KERN_DEBUG "TxCtlHigh: %04x ", mtch);
6312 printk(KERN_DEBUG "FC: %04x ", mfc);
6313 printk(KERN_DEBUG "FES Time: %04x\n", tfest);
6314 printk(KERN_DEBUG "PhyCtl: %04x%s ", ptcw,
6315 (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
6316 printk(KERN_DEBUG "PhyCtl_1: %04x ", ptcw_1);
6317 printk(KERN_DEBUG "PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
6318 printk(KERN_DEBUG "PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
6319 printk(KERN_DEBUG "PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
6320 printk(KERN_DEBUG "MainRates: %04x ", mainrates);
6321 printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft);
6322 printk(KERN_DEBUG "\n");
6323
6324 brcmu_format_hex(hexbuf, iv, sizeof(txh->IV));
6325 printk(KERN_DEBUG "SecIV: %s\n", hexbuf);
6326 brcmu_format_hex(hexbuf, ra, sizeof(txh->TxFrameRA));
6327 printk(KERN_DEBUG "RA: %s\n", hexbuf);
6328
6329 printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb);
6330 brcmu_format_hex(hexbuf, rtspfb, sizeof(txh->RTSPLCPFallback));
6331 printk(KERN_DEBUG "RTS PLCP: %s ", hexbuf);
6332 printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb);
6333 brcmu_format_hex(hexbuf, fragpfb, sizeof(txh->FragPLCPFallback));
6334 printk(KERN_DEBUG "PLCP: %s ", hexbuf);
6335 printk(KERN_DEBUG "DUR: %04x", fragdfb);
6336 printk(KERN_DEBUG "\n");
6337
6338 printk(KERN_DEBUG "MModeLen: %04x ", mmodelen);
6339 printk(KERN_DEBUG "MModeFbrLen: %04x\n", mmodefbrlen);
6340
6341 printk(KERN_DEBUG "FrameID: %04x\n", tfid);
6342 printk(KERN_DEBUG "TxStatus: %04x\n", txs);
6343
6344 printk(KERN_DEBUG "MaxNumMpdu: %04x\n", mnmpdu);
6345 printk(KERN_DEBUG "MaxAggbyte: %04x\n", mabyte);
6346 printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f);
6347 printk(KERN_DEBUG "MinByte: %04x\n", mmbyte);
6348
6349 brcmu_format_hex(hexbuf, rtsph, sizeof(txh->RTSPhyHeader));
6350 printk(KERN_DEBUG "RTS PLCP: %s ", hexbuf);
6351 brcmu_format_hex(hexbuf, (u8 *) &rts, sizeof(txh->rts_frame));
6352 printk(KERN_DEBUG "RTS Frame: %s", hexbuf);
6353 printk(KERN_DEBUG "\n");
6354}
6355#endif /* defined(BCMDBG) */
6356
6357#if defined(BCMDBG)
6358void brcms_c_print_rxh(struct d11rxhdr *rxh)
6359{
6360 u16 len = rxh->RxFrameSize;
6361 u16 phystatus_0 = rxh->PhyRxStatus_0;
6362 u16 phystatus_1 = rxh->PhyRxStatus_1;
6363 u16 phystatus_2 = rxh->PhyRxStatus_2;
6364 u16 phystatus_3 = rxh->PhyRxStatus_3;
6365 u16 macstatus1 = rxh->RxStatus1;
6366 u16 macstatus2 = rxh->RxStatus2;
6367 char flagstr[64];
6368 char lenbuf[20];
6369 static const struct brcmu_bit_desc macstat_flags[] = {
6370 {RXS_FCSERR, "FCSErr"},
6371 {RXS_RESPFRAMETX, "Reply"},
6372 {RXS_PBPRES, "PADDING"},
6373 {RXS_DECATMPT, "DeCr"},
6374 {RXS_DECERR, "DeCrErr"},
6375 {RXS_BCNSENT, "Bcn"},
6376 {0, NULL}
6377 };
6378
6379 printk(KERN_DEBUG "Raw RxDesc:\n");
6380 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, rxh,
6381 sizeof(struct d11rxhdr));
6382
6383 brcmu_format_flags(macstat_flags, macstatus1, flagstr, 64);
6384
6385 snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
6386
6387 printk(KERN_DEBUG "RxFrameSize: %6s (%d)%s\n", lenbuf, len,
6388 (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
6389 printk(KERN_DEBUG "RxPHYStatus: %04x %04x %04x %04x\n",
6390 phystatus_0, phystatus_1, phystatus_2, phystatus_3);
6391 printk(KERN_DEBUG "RxMACStatus: %x %s\n", macstatus1, flagstr);
6392 printk(KERN_DEBUG "RXMACaggtype: %x\n",
6393 (macstatus2 & RXS_AGGTYPE_MASK));
6394 printk(KERN_DEBUG "RxTSFTime: %04x\n", rxh->RxTSFTime);
6395}
6396#endif /* defined(BCMDBG) */
6397
6398u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
6399{
6400 u16 table_ptr;
6401 u8 phy_rate, index;
6402
6403 /* get the phy specific rate encoding for the PLCP SIGNAL field */
6404 if (is_ofdm_rate(rate))
6405 table_ptr = M_RT_DIRMAP_A;
6406 else
6407 table_ptr = M_RT_DIRMAP_B;
6408
6409 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
6410 * the index into the rate table.
6411 */
6412 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
6413 index = phy_rate & 0xf;
6414
6415 /* Find the SHM pointer to the rate table entry by looking in the
6416 * Direct-map Table
6417 */
6418 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
6419}
6420
6421/* Callback for device removed */
6422
6423/*
6424 * Attempts to queue a packet onto a multiple-precedence queue,
6425 * if necessary evicting a lower precedence packet from the queue.
6426 *
6427 * 'prec' is the precedence number that has already been mapped
6428 * from the packet priority.
6429 *
6430 * Returns true if packet consumed (queued), false if not.
6431 */
6432static bool brcms_c_prec_enq(struct brcms_c_info *wlc, struct pktq *q,
6433 struct sk_buff *pkt, int prec)
6434{
6435 return brcms_c_prec_enq_head(wlc, q, pkt, prec, false);
6436}
6437
6438bool
6439brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q,
6440 struct sk_buff *pkt, int prec, bool head)
6441{
6442 struct sk_buff *p;
6443 int eprec = -1; /* precedence to evict from */
6444
6445 /* Determine precedence from which to evict packet, if any */
6446 if (pktq_pfull(q, prec))
6447 eprec = prec;
6448 else if (pktq_full(q)) {
6449 p = brcmu_pktq_peek_tail(q, &eprec);
6450 if (eprec > prec) {
6451 wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
6452 "\n", __func__, eprec, prec);
6453 return false;
6454 }
6455 }
6456
6457 /* Evict if needed */
6458 if (eprec >= 0) {
6459 bool discard_oldest;
6460
6461 discard_oldest = ac_bitmap_tst(0, eprec);
6462
6463 /* Refuse newer packet unless configured to discard oldest */
6464 if (eprec == prec && !discard_oldest) {
6465 wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
6466 "\n", __func__, prec);
6467 return false;
6468 }
6469
6470 /* Evict packet according to discard policy */
6471 p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
6472 brcmu_pktq_pdeq_tail(q, eprec);
6473 brcmu_pkt_buf_free_skb(p);
6474 }
6475
6476 /* Enqueue */
6477 if (head)
6478 p = brcmu_pktq_penq_head(q, prec, pkt);
6479 else
6480 p = brcmu_pktq_penq(q, prec, pkt);
6481
6482 return true;
6483}
6484
6485void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb,
6486 struct sk_buff *sdu, uint prec)
6487{
6488 struct brcms_txq_info *qi = wlc->pkt_queue; /* Check me */
6489 struct pktq *q = &qi->q;
6490 int prio;
6491
6492 prio = sdu->priority;
6493
6494 if (!brcms_c_prec_enq(wlc, q, sdu, prec)) {
6495 /*
6496 * we might hit this condtion in case
6497 * packet flooding from mac80211 stack
6498 */
6499 brcmu_pkt_buf_free_skb(sdu);
6500 }
6501}
6502
6503/*
6504 * bcmc_fid_generate:
6505 * Generate frame ID for a BCMC packet. The frag field is not used
6506 * for MC frames so is used as part of the sequence number.
6507 */
6508static inline u16
6509bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
6510 struct d11txh *txh)
6511{
6512 u16 frameid;
6513
6514 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
6515 TXFID_QUEUE_MASK);
6516 frameid |=
6517 (((wlc->
6518 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6519 TX_BCMC_FIFO;
6520
6521 return frameid;
6522}
6523
6524static uint
6525brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
6526 u8 preamble_type)
6527{
6528 uint dur = 0;
6529
6530 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
6531 wlc->pub->unit, rspec, preamble_type);
6532 /*
6533 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6534 * is less than or equal to the rate of the immediately previous
6535 * frame in the FES
6536 */
6537 rspec = brcms_basic_rate(wlc, rspec);
6538 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
6539 dur =
6540 brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6541 (DOT11_ACK_LEN + FCS_LEN));
6542 return dur;
6543}
6544
6545static uint
6546brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
6547 u8 preamble_type)
6548{
6549 BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
6550 wlc->pub->unit, rspec, preamble_type);
6551 return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
6552}
6553
6554static uint
6555brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
6556 u8 preamble_type)
6557{
6558 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
6559 "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
6560 /*
6561 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6562 * is less than or equal to the rate of the immediately previous
6563 * frame in the FES
6564 */
6565 rspec = brcms_basic_rate(wlc, rspec);
6566 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
6567 return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6568 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
6569 FCS_LEN));
6570}
6571
6572/* brcms_c_compute_frame_dur()
6573 *
6574 * Calculate the 802.11 MAC header DUR field for MPDU
6575 * DUR for a single frame = 1 SIFS + 1 ACK
6576 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
6577 *
6578 * rate MPDU rate in unit of 500kbps
6579 * next_frag_len next MPDU length in bytes
6580 * preamble_type use short/GF or long/MM PLCP header
6581 */
6582static u16
6583brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
6584 u8 preamble_type, uint next_frag_len)
6585{
6586 u16 dur, sifs;
6587
6588 sifs = get_sifs(wlc->band);
6589
6590 dur = sifs;
6591 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
6592
6593 if (next_frag_len) {
6594 /* Double the current DUR to get 2 SIFS + 2 ACKs */
6595 dur *= 2;
6596 /* add another SIFS and the frag time */
6597 dur += sifs;
6598 dur +=
6599 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
6600 next_frag_len);
6601 }
6602 return dur;
6603}
6604
6605/* The opposite of brcms_c_calc_frame_time */
6606static uint
6607brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
6608 u8 preamble_type, uint dur)
6609{
6610 uint nsyms, mac_len, Ndps, kNdps;
6611 uint rate = rspec2rate(ratespec);
6612
6613 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
6614 wlc->pub->unit, ratespec, preamble_type, dur);
6615
6616 if (is_mcs_rate(ratespec)) {
6617 uint mcs = ratespec & RSPEC_RATE_MASK;
6618 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
6619 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
6620 /* payload calculation matches that of regular ofdm */
6621 if (wlc->band->bandtype == BRCM_BAND_2G)
6622 dur -= DOT11_OFDM_SIGNAL_EXTENSION;
6623 /* kNdbps = kbps * 4 */
6624 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
6625 rspec_issgi(ratespec)) * 4;
6626 nsyms = dur / APHY_SYMBOL_TIME;
6627 mac_len =
6628 ((nsyms * kNdps) -
6629 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
6630 } else if (is_ofdm_rate(ratespec)) {
6631 dur -= APHY_PREAMBLE_TIME;
6632 dur -= APHY_SIGNAL_TIME;
6633 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
6634 Ndps = rate * 2;
6635 nsyms = dur / APHY_SYMBOL_TIME;
6636 mac_len =
6637 ((nsyms * Ndps) -
6638 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
6639 } else {
6640 if (preamble_type & BRCMS_SHORT_PREAMBLE)
6641 dur -= BPHY_PLCP_SHORT_TIME;
6642 else
6643 dur -= BPHY_PLCP_TIME;
6644 mac_len = dur * rate;
6645 /* divide out factor of 2 in rate (1/2 mbps) */
6646 mac_len = mac_len / 8 / 2;
6647 }
6648 return mac_len;
6649}
6650
6651static u32
6652mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
6653 u32 int_val)
6654{
6655 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
6656 u8 rate = int_val & NRATE_RATE_MASK;
6657 u32 rspec;
6658 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
6659 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
6660 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
6661 == NRATE_OVERRIDE_MCS_ONLY);
6662 int bcmerror = 0;
6663
6664 if (!ismcs)
6665 return (u32) rate;
6666
6667 /* validate the combination of rate/mcs/stf is allowed */
6668 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
6669 /* mcs only allowed when nmode */
6670 if (stf > PHY_TXC1_MODE_SDM) {
6671 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
6672 wlc->pub->unit, __func__);
6673 bcmerror = -EINVAL;
6674 goto done;
6675 }
6676
6677 /* mcs 32 is a special case, DUP mode 40 only */
6678 if (rate == 32) {
6679 if (!CHSPEC_IS40(wlc->home_chanspec) ||
6680 ((stf != PHY_TXC1_MODE_SISO)
6681 && (stf != PHY_TXC1_MODE_CDD))) {
6682 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
6683 "32\n", wlc->pub->unit, __func__);
6684 bcmerror = -EINVAL;
6685 goto done;
6686 }
6687 /* mcs > 7 must use stf SDM */
6688 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
6689 /* mcs > 7 must use stf SDM */
6690 if (stf != PHY_TXC1_MODE_SDM) {
6691 BCMMSG(wlc->wiphy, "wl%d: enabling "
6692 "SDM mode for mcs %d\n",
6693 wlc->pub->unit, rate);
6694 stf = PHY_TXC1_MODE_SDM;
6695 }
6696 } else {
6697 /*
6698 * MCS 0-7 may use SISO, CDD, and for
6699 * phy_rev >= 3 STBC
6700 */
6701 if ((stf > PHY_TXC1_MODE_STBC) ||
6702 (!BRCMS_STBC_CAP_PHY(wlc)
6703 && (stf == PHY_TXC1_MODE_STBC))) {
6704 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
6705 "\n", wlc->pub->unit, __func__);
6706 bcmerror = -EINVAL;
6707 goto done;
6708 }
6709 }
6710 } else if (is_ofdm_rate(rate)) {
6711 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
6712 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
6713 wlc->pub->unit, __func__);
6714 bcmerror = -EINVAL;
6715 goto done;
6716 }
6717 } else if (is_cck_rate(rate)) {
6718 if ((cur_band->bandtype != BRCM_BAND_2G)
6719 || (stf != PHY_TXC1_MODE_SISO)) {
6720 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
6721 wlc->pub->unit, __func__);
6722 bcmerror = -EINVAL;
6723 goto done;
6724 }
6725 } else {
6726 wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
6727 wlc->pub->unit, __func__);
6728 bcmerror = -EINVAL;
6729 goto done;
6730 }
6731 /* make sure multiple antennae are available for non-siso rates */
6732 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
6733 wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
6734 "request\n", wlc->pub->unit, __func__);
6735 bcmerror = -EINVAL;
6736 goto done;
6737 }
6738
6739 rspec = rate;
6740 if (ismcs) {
6741 rspec |= RSPEC_MIMORATE;
6742 /* For STBC populate the STC field of the ratespec */
6743 if (stf == PHY_TXC1_MODE_STBC) {
6744 u8 stc;
6745 stc = 1; /* Nss for single stream is always 1 */
6746 rspec |= (stc << RSPEC_STC_SHIFT);
6747 }
6748 }
6749
6750 rspec |= (stf << RSPEC_STF_SHIFT);
6751
6752 if (override_mcs_only)
6753 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
6754
6755 if (issgi)
6756 rspec |= RSPEC_SHORT_GI;
6757
6758 if ((rate != 0)
6759 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6760 return rate;
6761
6762 return rspec;
6763done:
6764 return rate;
6765}
6766
6767/*
6768 * Add struct d11txh, struct cck_phy_hdr.
6769 *
6770 * 'p' data must start with 802.11 MAC header
6771 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6772 *
6773 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6774 *
6775 */
6776static u16
6777brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6778 struct sk_buff *p, struct scb *scb, uint frag,
6779 uint nfrags, uint queue, uint next_frag_len)
6780{
6781 struct ieee80211_hdr *h;
6782 struct d11txh *txh;
6783 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6784 int len, phylen, rts_phylen;
6785 u16 mch, phyctl, xfts, mainrates;
6786 u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6787 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6788 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6789 bool use_rts = false;
6790 bool use_cts = false;
6791 bool use_rifs = false;
6792 bool short_preamble[2] = { false, false };
6793 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6794 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6795 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6796 struct ieee80211_rts *rts = NULL;
6797 bool qos;
6798 uint ac;
6799 bool hwtkmic = false;
6800 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6801#define ANTCFG_NONE 0xFF
6802 u8 antcfg = ANTCFG_NONE;
6803 u8 fbantcfg = ANTCFG_NONE;
6804 uint phyctl1_stf = 0;
6805 u16 durid = 0;
6806 struct ieee80211_tx_rate *txrate[2];
6807 int k;
6808 struct ieee80211_tx_info *tx_info;
6809 bool is_mcs;
6810 u16 mimo_txbw;
6811 u8 mimo_preamble_type;
6812
6813 /* locate 802.11 MAC header */
6814 h = (struct ieee80211_hdr *)(p->data);
6815 qos = ieee80211_is_data_qos(h->frame_control);
6816
6817 /* compute length of frame in bytes for use in PLCP computations */
6818 len = brcmu_pkttotlen(p);
6819 phylen = len + FCS_LEN;
6820
6821 /* Get tx_info */
6822 tx_info = IEEE80211_SKB_CB(p);
6823
6824 /* add PLCP */
6825 plcp = skb_push(p, D11_PHY_HDR_LEN);
6826
6827 /* add Broadcom tx descriptor header */
6828 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6829 memset(txh, 0, D11_TXH_LEN);
6830
6831 /* setup frameid */
6832 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6833 /* non-AP STA should never use BCMC queue */
6834 if (queue == TX_BCMC_FIFO) {
6835 wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
6836 "TX_BCMC!\n", wlc->pub->unit, __func__);
6837 frameid = bcmc_fid_generate(wlc, NULL, txh);
6838 } else {
6839 /* Increment the counter for first fragment */
6840 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6841 scb->seqnum[p->priority]++;
6842
6843 /* extract fragment number from frame first */
6844 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6845 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6846 h->seq_ctrl = cpu_to_le16(seq);
6847
6848 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6849 (queue & TXFID_QUEUE_MASK);
6850 }
6851 }
6852 frameid |= queue & TXFID_QUEUE_MASK;
6853
6854 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6855 if (ieee80211_is_beacon(h->frame_control))
6856 mcl |= TXC_IGNOREPMQ;
6857
6858 txrate[0] = tx_info->control.rates;
6859 txrate[1] = txrate[0] + 1;
6860
6861 /*
6862 * if rate control algorithm didn't give us a fallback
6863 * rate, use the primary rate
6864 */
6865 if (txrate[1]->idx < 0)
6866 txrate[1] = txrate[0];
6867
6868 for (k = 0; k < hw->max_rates; k++) {
6869 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6870 if (!is_mcs) {
6871 if ((txrate[k]->idx >= 0)
6872 && (txrate[k]->idx <
6873 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6874 rspec[k] =
6875 hw->wiphy->bands[tx_info->band]->
6876 bitrates[txrate[k]->idx].hw_value;
6877 short_preamble[k] =
6878 txrate[k]->
6879 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6880 true : false;
6881 } else {
6882 rspec[k] = BRCM_RATE_1M;
6883 }
6884 } else {
6885 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6886 NRATE_MCS_INUSE | txrate[k]->idx);
6887 }
6888
6889 /*
6890 * Currently only support same setting for primay and
6891 * fallback rates. Unify flags for each rate into a
6892 * single value for the frame
6893 */
6894 use_rts |=
6895 txrate[k]->
6896 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6897 use_cts |=
6898 txrate[k]->
6899 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6900
6901
6902 /*
6903 * (1) RATE:
6904 * determine and validate primary rate
6905 * and fallback rates
6906 */
6907 if (!rspec_active(rspec[k])) {
6908 rspec[k] = BRCM_RATE_1M;
6909 } else {
6910 if (!is_multicast_ether_addr(h->addr1)) {
6911 /* set tx antenna config */
6912 brcms_c_antsel_antcfg_get(wlc->asi, false,
6913 false, 0, 0, &antcfg, &fbantcfg);
6914 }
6915 }
6916 }
6917
6918 phyctl1_stf = wlc->stf->ss_opmode;
6919
6920 if (wlc->pub->_n_enab & SUPPORT_11N) {
6921 for (k = 0; k < hw->max_rates; k++) {
6922 /*
6923 * apply siso/cdd to single stream mcs's or ofdm
6924 * if rspec is auto selected
6925 */
6926 if (((is_mcs_rate(rspec[k]) &&
6927 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6928 is_ofdm_rate(rspec[k]))
6929 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6930 || !(rspec[k] & RSPEC_OVERRIDE))) {
6931 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6932
6933 /* For SISO MCS use STBC if possible */
6934 if (is_mcs_rate(rspec[k])
6935 && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6936 u8 stc;
6937
6938 /* Nss for single stream is always 1 */
6939 stc = 1;
6940 rspec[k] |= (PHY_TXC1_MODE_STBC <<
6941 RSPEC_STF_SHIFT) |
6942 (stc << RSPEC_STC_SHIFT);
6943 } else
6944 rspec[k] |=
6945 (phyctl1_stf << RSPEC_STF_SHIFT);
6946 }
6947
6948 /*
6949 * Is the phy configured to use 40MHZ frames? If
6950 * so then pick the desired txbw
6951 */
6952 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6953 /* default txbw is 20in40 SB */
6954 mimo_ctlchbw = mimo_txbw =
6955 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6956 wlc->band->pi))
6957 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6958
6959 if (is_mcs_rate(rspec[k])) {
6960 /* mcs 32 must be 40b/w DUP */
6961 if ((rspec[k] & RSPEC_RATE_MASK)
6962 == 32) {
6963 mimo_txbw =
6964 PHY_TXC1_BW_40MHZ_DUP;
6965 /* use override */
6966 } else if (wlc->mimo_40txbw != AUTO)
6967 mimo_txbw = wlc->mimo_40txbw;
6968 /* else check if dst is using 40 Mhz */
6969 else if (scb->flags & SCB_IS40)
6970 mimo_txbw = PHY_TXC1_BW_40MHZ;
6971 } else if (is_ofdm_rate(rspec[k])) {
6972 if (wlc->ofdm_40txbw != AUTO)
6973 mimo_txbw = wlc->ofdm_40txbw;
6974 } else if (wlc->cck_40txbw != AUTO) {
6975 mimo_txbw = wlc->cck_40txbw;
6976 }
6977 } else {
6978 /*
6979 * mcs32 is 40 b/w only.
6980 * This is possible for probe packets on
6981 * a STA during SCAN
6982 */
6983 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6984 /* mcs 0 */
6985 rspec[k] = RSPEC_MIMORATE;
6986
6987 mimo_txbw = PHY_TXC1_BW_20MHZ;
6988 }
6989
6990 /* Set channel width */
6991 rspec[k] &= ~RSPEC_BW_MASK;
6992 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6993 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6994 else
6995 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6996
6997 /* Disable short GI, not supported yet */
6998 rspec[k] &= ~RSPEC_SHORT_GI;
6999
7000 mimo_preamble_type = BRCMS_MM_PREAMBLE;
7001 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
7002 mimo_preamble_type = BRCMS_GF_PREAMBLE;
7003
7004 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
7005 && (!is_mcs_rate(rspec[k]))) {
7006 wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
7007 "RC_MCS != is_mcs_rate(rspec)\n",
7008 wlc->pub->unit, __func__);
7009 }
7010
7011 if (is_mcs_rate(rspec[k])) {
7012 preamble_type[k] = mimo_preamble_type;
7013
7014 /*
7015 * if SGI is selected, then forced mm
7016 * for single stream
7017 */
7018 if ((rspec[k] & RSPEC_SHORT_GI)
7019 && is_single_stream(rspec[k] &
7020 RSPEC_RATE_MASK))
7021 preamble_type[k] = BRCMS_MM_PREAMBLE;
7022 }
7023
7024 /* should be better conditionalized */
7025 if (!is_mcs_rate(rspec[0])
7026 && (tx_info->control.rates[0].
7027 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
7028 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
7029 }
7030 } else {
7031 for (k = 0; k < hw->max_rates; k++) {
7032 /* Set ctrlchbw as 20Mhz */
7033 rspec[k] &= ~RSPEC_BW_MASK;
7034 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
7035
7036 /* for nphy, stf of ofdm frames must follow policies */
7037 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
7038 rspec[k] &= ~RSPEC_STF_MASK;
7039 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
7040 }
7041 }
7042 }
7043
7044 /* Reset these for use with AMPDU's */
7045 txrate[0]->count = 0;
7046 txrate[1]->count = 0;
7047
7048 /* (2) PROTECTION, may change rspec */
7049 if ((ieee80211_is_data(h->frame_control) ||
7050 ieee80211_is_mgmt(h->frame_control)) &&
7051 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
7052 use_rts = true;
7053
7054 /* (3) PLCP: determine PLCP header and MAC duration,
7055 * fill struct d11txh */
7056 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
7057 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
7058 memcpy(&txh->FragPLCPFallback,
7059 plcp_fallback, sizeof(txh->FragPLCPFallback));
7060
7061 /* Length field now put in CCK FBR CRC field */
7062 if (is_cck_rate(rspec[1])) {
7063 txh->FragPLCPFallback[4] = phylen & 0xff;
7064 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
7065 }
7066
7067 /* MIMO-RATE: need validation ?? */
7068 mainrates = is_ofdm_rate(rspec[0]) ?
7069 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
7070 plcp[0];
7071
7072 /* DUR field for main rate */
7073 if (!ieee80211_is_pspoll(h->frame_control) &&
7074 !is_multicast_ether_addr(h->addr1) && !use_rifs) {
7075 durid =
7076 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
7077 next_frag_len);
7078 h->duration_id = cpu_to_le16(durid);
7079 } else if (use_rifs) {
7080 /* NAV protect to end of next max packet size */
7081 durid =
7082 (u16) brcms_c_calc_frame_time(wlc, rspec[0],
7083 preamble_type[0],
7084 DOT11_MAX_FRAG_LEN);
7085 durid += RIFS_11N_TIME;
7086 h->duration_id = cpu_to_le16(durid);
7087 }
7088
7089 /* DUR field for fallback rate */
7090 if (ieee80211_is_pspoll(h->frame_control))
7091 txh->FragDurFallback = h->duration_id;
7092 else if (is_multicast_ether_addr(h->addr1) || use_rifs)
7093 txh->FragDurFallback = 0;
7094 else {
7095 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
7096 preamble_type[1], next_frag_len);
7097 txh->FragDurFallback = cpu_to_le16(durid);
7098 }
7099
7100 /* (4) MAC-HDR: MacTxControlLow */
7101 if (frag == 0)
7102 mcl |= TXC_STARTMSDU;
7103
7104 if (!is_multicast_ether_addr(h->addr1))
7105 mcl |= TXC_IMMEDACK;
7106
7107 if (wlc->band->bandtype == BRCM_BAND_5G)
7108 mcl |= TXC_FREQBAND_5G;
7109
7110 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
7111 mcl |= TXC_BW_40;
7112
7113 /* set AMIC bit if using hardware TKIP MIC */
7114 if (hwtkmic)
7115 mcl |= TXC_AMIC;
7116
7117 txh->MacTxControlLow = cpu_to_le16(mcl);
7118
7119 /* MacTxControlHigh */
7120 mch = 0;
7121
7122 /* Set fallback rate preamble type */
7123 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
7124 (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
7125 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
7126 mch |= TXC_PREAMBLE_DATA_FB_SHORT;
7127 }
7128
7129 /* MacFrameControl */
7130 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
7131 txh->TxFesTimeNormal = cpu_to_le16(0);
7132
7133 txh->TxFesTimeFallback = cpu_to_le16(0);
7134
7135 /* TxFrameRA */
7136 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
7137
7138 /* TxFrameID */
7139 txh->TxFrameID = cpu_to_le16(frameid);
7140
7141 /*
7142 * TxStatus, Note the case of recreating the first frag of a suppressed
7143 * frame then we may need to reset the retry cnt's via the status reg
7144 */
7145 txh->TxStatus = cpu_to_le16(status);
7146
7147 /*
7148 * extra fields for ucode AMPDU aggregation, the new fields are added to
7149 * the END of previous structure so that it's compatible in driver.
7150 */
7151 txh->MaxNMpdus = cpu_to_le16(0);
7152 txh->MaxABytes_MRT = cpu_to_le16(0);
7153 txh->MaxABytes_FBR = cpu_to_le16(0);
7154 txh->MinMBytes = cpu_to_le16(0);
7155
7156 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
7157 * furnish struct d11txh */
7158 /* RTS PLCP header and RTS frame */
7159 if (use_rts || use_cts) {
7160 if (use_rts && use_cts)
7161 use_cts = false;
7162
7163 for (k = 0; k < 2; k++) {
7164 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
7165 false,
7166 mimo_ctlchbw);
7167 }
7168
7169 if (!is_ofdm_rate(rts_rspec[0]) &&
7170 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
7171 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
7172 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
7173 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
7174 }
7175
7176 if (!is_ofdm_rate(rts_rspec[1]) &&
7177 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
7178 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
7179 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
7180 mch |= TXC_PREAMBLE_RTS_FB_SHORT;
7181 }
7182
7183 /* RTS/CTS additions to MacTxControlLow */
7184 if (use_cts) {
7185 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
7186 } else {
7187 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
7188 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
7189 }
7190
7191 /* RTS PLCP header */
7192 rts_plcp = txh->RTSPhyHeader;
7193 if (use_cts)
7194 rts_phylen = DOT11_CTS_LEN + FCS_LEN;
7195 else
7196 rts_phylen = DOT11_RTS_LEN + FCS_LEN;
7197
7198 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
7199
7200 /* fallback rate version of RTS PLCP header */
7201 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
7202 rts_plcp_fallback);
7203 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
7204 sizeof(txh->RTSPLCPFallback));
7205
7206 /* RTS frame fields... */
7207 rts = (struct ieee80211_rts *)&txh->rts_frame;
7208
7209 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
7210 rspec[0], rts_preamble_type[0],
7211 preamble_type[0], phylen, false);
7212 rts->duration = cpu_to_le16(durid);
7213 /* fallback rate version of RTS DUR field */
7214 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
7215 rts_rspec[1], rspec[1],
7216 rts_preamble_type[1],
7217 preamble_type[1], phylen, false);
7218 txh->RTSDurFallback = cpu_to_le16(durid);
7219
7220 if (use_cts) {
7221 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
7222 IEEE80211_STYPE_CTS);
7223
7224 memcpy(&rts->ra, &h->addr2, ETH_ALEN);
7225 } else {
7226 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
7227 IEEE80211_STYPE_RTS);
7228
7229 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
7230 }
7231
7232 /* mainrate
7233 * low 8 bits: main frag rate/mcs,
7234 * high 8 bits: rts/cts rate/mcs
7235 */
7236 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
7237 D11A_PHY_HDR_GRATE(
7238 (struct ofdm_phy_hdr *) rts_plcp) :
7239 rts_plcp[0]) << 8;
7240 } else {
7241 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
7242 memset((char *)&txh->rts_frame, 0,
7243 sizeof(struct ieee80211_rts));
7244 memset((char *)txh->RTSPLCPFallback, 0,
7245 sizeof(txh->RTSPLCPFallback));
7246 txh->RTSDurFallback = 0;
7247 }
7248
7249#ifdef SUPPORT_40MHZ
7250 /* add null delimiter count */
7251 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
7252 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
7253 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
7254
7255#endif
7256
7257 /*
7258 * Now that RTS/RTS FB preamble types are updated, write
7259 * the final value
7260 */
7261 txh->MacTxControlHigh = cpu_to_le16(mch);
7262
7263 /*
7264 * MainRates (both the rts and frag plcp rates have
7265 * been calculated now)
7266 */
7267 txh->MainRates = cpu_to_le16(mainrates);
7268
7269 /* XtraFrameTypes */
7270 xfts = frametype(rspec[1], wlc->mimoft);
7271 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
7272 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
7273 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
7274 XFTS_CHANNEL_SHIFT;
7275 txh->XtraFrameTypes = cpu_to_le16(xfts);
7276
7277 /* PhyTxControlWord */
7278 phyctl = frametype(rspec[0], wlc->mimoft);
7279 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
7280 (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
7281 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
7282 phyctl |= PHY_TXC_SHORT_HDR;
7283 }
7284
7285 /* phytxant is properly bit shifted */
7286 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
7287 txh->PhyTxControlWord = cpu_to_le16(phyctl);
7288
7289 /* PhyTxControlWord_1 */
7290 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7291 u16 phyctl1 = 0;
7292
7293 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
7294 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
7295 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
7296 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
7297
7298 if (use_rts || use_cts) {
7299 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
7300 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
7301 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
7302 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
7303 }
7304
7305 /*
7306 * For mcs frames, if mixedmode(overloaded with long preamble)
7307 * is going to be set, fill in non-zero MModeLen and/or
7308 * MModeFbrLen it will be unnecessary if they are separated
7309 */
7310 if (is_mcs_rate(rspec[0]) &&
7311 (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
7312 u16 mmodelen =
7313 brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
7314 txh->MModeLen = cpu_to_le16(mmodelen);
7315 }
7316
7317 if (is_mcs_rate(rspec[1]) &&
7318 (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
7319 u16 mmodefbrlen =
7320 brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
7321 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
7322 }
7323 }
7324
7325 ac = skb_get_queue_mapping(p);
7326 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
7327 uint frag_dur, dur, dur_fallback;
7328
7329 /* WME: Update TXOP threshold */
7330 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
7331 frag_dur =
7332 brcms_c_calc_frame_time(wlc, rspec[0],
7333 preamble_type[0], phylen);
7334
7335 if (rts) {
7336 /* 1 RTS or CTS-to-self frame */
7337 dur =
7338 brcms_c_calc_cts_time(wlc, rts_rspec[0],
7339 rts_preamble_type[0]);
7340 dur_fallback =
7341 brcms_c_calc_cts_time(wlc, rts_rspec[1],
7342 rts_preamble_type[1]);
7343 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
7344 dur += le16_to_cpu(rts->duration);
7345 dur_fallback +=
7346 le16_to_cpu(txh->RTSDurFallback);
7347 } else if (use_rifs) {
7348 dur = frag_dur;
7349 dur_fallback = 0;
7350 } else {
7351 /* frame + SIFS + ACK */
7352 dur = frag_dur;
7353 dur +=
7354 brcms_c_compute_frame_dur(wlc, rspec[0],
7355 preamble_type[0], 0);
7356
7357 dur_fallback =
7358 brcms_c_calc_frame_time(wlc, rspec[1],
7359 preamble_type[1],
7360 phylen);
7361 dur_fallback +=
7362 brcms_c_compute_frame_dur(wlc, rspec[1],
7363 preamble_type[1], 0);
7364 }
7365 /* NEED to set TxFesTimeNormal (hard) */
7366 txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
7367 /*
7368 * NEED to set fallback rate version of
7369 * TxFesTimeNormal (hard)
7370 */
7371 txh->TxFesTimeFallback =
7372 cpu_to_le16((u16) dur_fallback);
7373
7374 /*
7375 * update txop byte threshold (txop minus intraframe
7376 * overhead)
7377 */
7378 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
7379 uint newfragthresh;
7380
7381 newfragthresh =
7382 brcms_c_calc_frame_len(wlc,
7383 rspec[0], preamble_type[0],
7384 (wlc->edcf_txop[ac] -
7385 (dur - frag_dur)));
7386 /* range bound the fragthreshold */
7387 if (newfragthresh < DOT11_MIN_FRAG_LEN)
7388 newfragthresh =
7389 DOT11_MIN_FRAG_LEN;
7390 else if (newfragthresh >
7391 wlc->usr_fragthresh)
7392 newfragthresh =
7393 wlc->usr_fragthresh;
7394 /* update the fragthresh and do txc update */
7395 if (wlc->fragthresh[queue] !=
7396 (u16) newfragthresh)
7397 wlc->fragthresh[queue] =
7398 (u16) newfragthresh;
7399 } else {
7400 wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
7401 "for rate %d\n",
7402 wlc->pub->unit, fifo_names[queue],
7403 rspec2rate(rspec[0]));
7404 }
7405
7406 if (dur > wlc->edcf_txop[ac])
7407 wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
7408 "exceeded phylen %d/%d dur %d/%d\n",
7409 wlc->pub->unit, __func__,
7410 fifo_names[queue],
7411 phylen, wlc->fragthresh[queue],
7412 dur, wlc->edcf_txop[ac]);
7413 }
7414 }
7415
7416 return 0;
7417}
7418
7419void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
7420 struct ieee80211_hw *hw)
7421{
7422 u8 prio;
7423 uint fifo;
7424 struct scb *scb = &wlc->pri_scb;
7425 struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data);
7426
7427 /*
7428 * 802.11 standard requires management traffic
7429 * to go at highest priority
7430 */
7431 prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority :
7432 MAXPRIO;
7433 fifo = prio2fifo[prio];
7434 if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0))
7435 return;
7436 brcms_c_txq_enq(wlc, scb, sdu, BRCMS_PRIO_TO_PREC(prio));
7437 brcms_c_send_q(wlc);
7438}
7439
7440void brcms_c_send_q(struct brcms_c_info *wlc)
7441{
7442 struct sk_buff *pkt[DOT11_MAXNUMFRAGS];
7443 int prec;
7444 u16 prec_map;
7445 int err = 0, i, count;
7446 uint fifo;
7447 struct brcms_txq_info *qi = wlc->pkt_queue;
7448 struct pktq *q = &qi->q;
7449 struct ieee80211_tx_info *tx_info;
7450
7451 prec_map = wlc->tx_prec_map;
7452
7453 /* Send all the enq'd pkts that we can.
7454 * Dequeue packets with precedence with empty HW fifo only
7455 */
7456 while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) {
7457 tx_info = IEEE80211_SKB_CB(pkt[0]);
7458 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
7459 err = brcms_c_sendampdu(wlc->ampdu, qi, pkt, prec);
7460 } else {
7461 count = 1;
7462 err = brcms_c_prep_pdu(wlc, pkt[0], &fifo);
7463 if (!err) {
7464 for (i = 0; i < count; i++)
7465 brcms_c_txfifo(wlc, fifo, pkt[i], true,
7466 1);
7467 }
7468 }
7469
7470 if (err == -EBUSY) {
7471 brcmu_pktq_penq_head(q, prec, pkt[0]);
7472 /*
7473 * If send failed due to any other reason than a
7474 * change in HW FIFO condition, quit. Otherwise,
7475 * read the new prec_map!
7476 */
7477 if (prec_map == wlc->tx_prec_map)
7478 break;
7479 prec_map = wlc->tx_prec_map;
7480 }
7481 }
7482}
7483
7484void
7485brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p,
7486 bool commit, s8 txpktpend)
7487{
7488 u16 frameid = INVALIDFID;
7489 struct d11txh *txh;
7490
7491 txh = (struct d11txh *) (p->data);
7492
7493 /* When a BC/MC frame is being committed to the BCMC fifo
7494 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
7495 */
7496 if (fifo == TX_BCMC_FIFO)
7497 frameid = le16_to_cpu(txh->TxFrameID);
7498
7499 /*
7500 * Bump up pending count for if not using rpc. If rpc is
7501 * used, this will be handled in brcms_b_txfifo()
7502 */
7503 if (commit) {
7504 wlc->core->txpktpend[fifo] += txpktpend;
7505 BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n",
7506 txpktpend, wlc->core->txpktpend[fifo]);
7507 }
7508
7509 /* Commit BCMC sequence number in the SHM frame ID location */
7510 if (frameid != INVALIDFID) {
7511 /*
7512 * To inform the ucode of the last mcast frame posted
7513 * so that it can clear moredata bit
7514 */
7515 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
7516 }
7517
7518 if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0)
7519 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
7520}
7521
7522/*
7523 * Compute PLCP, but only requires actual rate and length of pkt.
7524 * Rate is given in the driver standard multiple of 500 kbps.
7525 * le is set for 11 Mbps rate if necessary.
7526 * Broken out for PRQ.
7527 */
7528
7529static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
7530 uint length, u8 *plcp)
7531{
7532 u16 usec = 0;
7533 u8 le = 0;
7534
7535 switch (rate_500) {
7536 case BRCM_RATE_1M:
7537 usec = length << 3;
7538 break;
7539 case BRCM_RATE_2M:
7540 usec = length << 2;
7541 break;
7542 case BRCM_RATE_5M5:
7543 usec = (length << 4) / 11;
7544 if ((length << 4) - (usec * 11) > 0)
7545 usec++;
7546 break;
7547 case BRCM_RATE_11M:
7548 usec = (length << 3) / 11;
7549 if ((length << 3) - (usec * 11) > 0) {
7550 usec++;
7551 if ((usec * 11) - (length << 3) >= 8)
7552 le = D11B_PLCP_SIGNAL_LE;
7553 }
7554 break;
7555
7556 default:
7557 wiphy_err(wlc->wiphy,
7558 "brcms_c_cck_plcp_set: unsupported rate %d\n",
7559 rate_500);
7560 rate_500 = BRCM_RATE_1M;
7561 usec = length << 3;
7562 break;
7563 }
7564 /* PLCP signal byte */
7565 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
7566 /* PLCP service byte */
7567 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
7568 /* PLCP length u16, little endian */
7569 plcp[2] = usec & 0xff;
7570 plcp[3] = (usec >> 8) & 0xff;
7571 /* PLCP CRC16 */
7572 plcp[4] = 0;
7573 plcp[5] = 0;
7574}
7575
7576/* Rate: 802.11 rate code, length: PSDU length in octets */
7577static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
7578{
7579 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
7580 plcp[0] = mcs;
7581 if (rspec_is40mhz(rspec) || (mcs == 32))
7582 plcp[0] |= MIMO_PLCP_40MHZ;
7583 BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
7584 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
7585 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
7586 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
7587 plcp[5] = 0;
7588}
7589
7590/* Rate: 802.11 rate code, length: PSDU length in octets */
7591static void
7592brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
7593{
7594 u8 rate_signal;
7595 u32 tmp = 0;
7596 int rate = rspec2rate(rspec);
7597
7598 /*
7599 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
7600 * transmitted first
7601 */
7602 rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
7603 memset(plcp, 0, D11_PHY_HDR_LEN);
7604 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
7605
7606 tmp = (length & 0xfff) << 5;
7607 plcp[2] |= (tmp >> 16) & 0xff;
7608 plcp[1] |= (tmp >> 8) & 0xff;
7609 plcp[0] |= tmp & 0xff;
7610}
7611
7612/* Rate: 802.11 rate code, length: PSDU length in octets */
7613static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
7614 uint length, u8 *plcp)
7615{
7616 int rate = rspec2rate(rspec);
7617
7618 brcms_c_cck_plcp_set(wlc, rate, length, plcp);
7619}
7620
7621void
7622brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
7623 uint length, u8 *plcp)
7624{
7625 if (is_mcs_rate(rspec))
7626 brcms_c_compute_mimo_plcp(rspec, length, plcp);
7627 else if (is_ofdm_rate(rspec))
7628 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
7629 else
7630 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
7631}
7632
7633/* brcms_c_compute_rtscts_dur()
7634 *
7635 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
7636 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
7637 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
7638 *
7639 * cts cts-to-self or rts/cts
7640 * rts_rate rts or cts rate in unit of 500kbps
7641 * rate next MPDU rate in unit of 500kbps
7642 * frame_len next MPDU frame length in bytes
7643 */
7644u16
7645brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
7646 u32 rts_rate,
7647 u32 frame_rate, u8 rts_preamble_type,
7648 u8 frame_preamble_type, uint frame_len, bool ba)
7649{
7650 u16 dur, sifs;
7651
7652 sifs = get_sifs(wlc->band);
7653
7654 if (!cts_only) {
7655 /* RTS/CTS */
7656 dur = 3 * sifs;
7657 dur +=
7658 (u16) brcms_c_calc_cts_time(wlc, rts_rate,
7659 rts_preamble_type);
7660 } else {
7661 /* CTS-TO-SELF */
7662 dur = 2 * sifs;
7663 }
7664
7665 dur +=
7666 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
7667 frame_len);
7668 if (ba)
7669 dur +=
7670 (u16) brcms_c_calc_ba_time(wlc, frame_rate,
7671 BRCMS_SHORT_PREAMBLE);
7672 else
7673 dur +=
7674 (u16) brcms_c_calc_ack_time(wlc, frame_rate,
7675 frame_preamble_type);
7676 return dur;
7677}
7678
7679u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
7680{
7681 u16 phyctl1 = 0;
7682 u16 bw;
7683
7684 if (BRCMS_ISLCNPHY(wlc->band)) {
7685 bw = PHY_TXC1_BW_20MHZ;
7686 } else {
7687 bw = rspec_get_bw(rspec);
7688 /* 10Mhz is not supported yet */
7689 if (bw < PHY_TXC1_BW_20MHZ) {
7690 wiphy_err(wlc->wiphy, "phytxctl1_calc: bw %d is "
7691 "not supported yet, set to 20L\n", bw);
7692 bw = PHY_TXC1_BW_20MHZ;
7693 }
7694 }
7695
7696 if (is_mcs_rate(rspec)) {
7697 uint mcs = rspec & RSPEC_RATE_MASK;
7698
7699 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
7700 phyctl1 = rspec_phytxbyte2(rspec);
7701 /* set the upper byte of phyctl1 */
7702 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
7703 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
7704 && !BRCMS_ISSSLPNPHY(wlc->band)) {
7705 /*
7706 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
7707 * Data Rate. Eventually MIMOPHY would also be converted to
7708 * this format
7709 */
7710 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
7711 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
7712 } else { /* legacy OFDM/CCK */
7713 s16 phycfg;
7714 /* get the phyctl byte from rate phycfg table */
7715 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
7716 if (phycfg == -1) {
7717 wiphy_err(wlc->wiphy, "phytxctl1_calc: wrong "
7718 "legacy OFDM/CCK rate\n");
7719 phycfg = 0;
7720 }
7721 /* set the upper byte of phyctl1 */
7722 phyctl1 =
7723 (bw | (phycfg << 8) |
7724 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
7725 }
7726 return phyctl1;
7727}
7728
7729u32
7730brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
7731 bool use_rspec, u16 mimo_ctlchbw)
7732{
7733 u32 rts_rspec = 0;
7734
7735 if (use_rspec)
7736 /* use frame rate as rts rate */
7737 rts_rspec = rspec;
7738 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
7739 /* Use 11Mbps as the g protection RTS target rate and fallback.
7740 * Use the brcms_basic_rate() lookup to find the best basic rate
7741 * under the target in case 11 Mbps is not Basic.
7742 * 6 and 9 Mbps are not usually selected by rate selection, but
7743 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
7744 * is more robust.
7745 */
7746 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
7747 else
7748 /* calculate RTS rate and fallback rate based on the frame rate
7749 * RTS must be sent at a basic rate since it is a
7750 * control frame, sec 9.6 of 802.11 spec
7751 */
7752 rts_rspec = brcms_basic_rate(wlc, rspec);
7753
7754 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7755 /* set rts txbw to correct side band */
7756 rts_rspec &= ~RSPEC_BW_MASK;
7757
7758 /*
7759 * if rspec/rspec_fallback is 40MHz, then send RTS on both
7760 * 20MHz channel (DUP), otherwise send RTS on control channel
7761 */
7762 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
7763 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
7764 else
7765 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7766
7767 /* pick siso/cdd as default for ofdm */
7768 if (is_ofdm_rate(rts_rspec)) {
7769 rts_rspec &= ~RSPEC_STF_MASK;
7770 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7771 }
7772 }
7773 return rts_rspec;
7774}
7775
7776void brcms_c_tbtt(struct brcms_c_info *wlc)
7777{
7778 if (!wlc->bsscfg->BSS)
7779 /*
7780 * DirFrmQ is now valid...defer setting until end
7781 * of ATIM window
7782 */
7783 wlc->qvalid |= MCMD_DIRFRMQVAL;
7784}
7785
7786void
7787brcms_c_txfifo_complete(struct brcms_c_info *wlc, uint fifo, s8 txpktpend)
7788{
7789 wlc->core->txpktpend[fifo] -= txpktpend;
7790 BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend,
7791 wlc->core->txpktpend[fifo]);
7792
7793 /* There is more room; mark precedences related to this FIFO sendable */
7794 wlc->tx_prec_map |= wlc->fifo2prec_map[fifo];
7795
7796 /* figure out which bsscfg is being worked on... */
7797}
7798
7799/* Update beacon listen interval in shared memory */
7800void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7801{
7802 /* wake up every DTIM is the default */
7803 if (wlc->bcn_li_dtim == 1)
7804 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7805 else
7806 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7807 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7808}
7809
7810static void
7811brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7812 u32 *tsf_h_ptr)
7813{
7814 struct d11regs __iomem *regs = wlc_hw->regs;
7815
7816 /* read the tsf timer low, then high to get an atomic read */
7817 *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
7818 *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
7819}
7820
7821/*
7822 * recover 64bit TSF value from the 16bit TSF value in the rx header
7823 * given the assumption that the TSF passed in header is within 65ms
7824 * of the current tsf.
7825 *
7826 * 6 5 4 4 3 2 1
7827 * 3.......6.......8.......0.......2.......4.......6.......8......0
7828 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7829 *
7830 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7831 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7832 * receive call sequence after rx interrupt. Only the higher 16 bits
7833 * are used. Finally, the tsf_h is read from the tsf register.
7834 */
7835static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7836 struct d11rxhdr *rxh)
7837{
7838 u32 tsf_h, tsf_l;
7839 u16 rx_tsf_0_15, rx_tsf_16_31;
7840
7841 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7842
7843 rx_tsf_16_31 = (u16)(tsf_l >> 16);
7844 rx_tsf_0_15 = rxh->RxTSFTime;
7845
7846 /*
7847 * a greater tsf time indicates the low 16 bits of
7848 * tsf_l wrapped, so decrement the high 16 bits.
7849 */
7850 if ((u16)tsf_l < rx_tsf_0_15) {
7851 rx_tsf_16_31 -= 1;
7852 if (rx_tsf_16_31 == 0xffff)
7853 tsf_h -= 1;
7854 }
7855
7856 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7857}
7858
7859static void
7860prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7861 struct sk_buff *p,
7862 struct ieee80211_rx_status *rx_status)
7863{
7864 int preamble;
7865 int channel;
7866 u32 rspec;
7867 unsigned char *plcp;
7868
7869 /* fill in TSF and flag its presence */
7870 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7871 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
7872
7873 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7874
7875 if (channel > 14) {
7876 rx_status->band = IEEE80211_BAND_5GHZ;
7877 rx_status->freq = ieee80211_ofdm_chan_to_freq(
7878 WF_CHAN_FACTOR_5_G/2, channel);
7879
7880 } else {
7881 rx_status->band = IEEE80211_BAND_2GHZ;
7882 rx_status->freq = ieee80211_dsss_chan_to_freq(channel);
7883 }
7884
7885 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7886
7887 /* noise */
7888 /* qual */
7889 rx_status->antenna =
7890 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7891
7892 plcp = p->data;
7893
7894 rspec = brcms_c_compute_rspec(rxh, plcp);
7895 if (is_mcs_rate(rspec)) {
7896 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7897 rx_status->flag |= RX_FLAG_HT;
7898 if (rspec_is40mhz(rspec))
7899 rx_status->flag |= RX_FLAG_40MHZ;
7900 } else {
7901 switch (rspec2rate(rspec)) {
7902 case BRCM_RATE_1M:
7903 rx_status->rate_idx = 0;
7904 break;
7905 case BRCM_RATE_2M:
7906 rx_status->rate_idx = 1;
7907 break;
7908 case BRCM_RATE_5M5:
7909 rx_status->rate_idx = 2;
7910 break;
7911 case BRCM_RATE_11M:
7912 rx_status->rate_idx = 3;
7913 break;
7914 case BRCM_RATE_6M:
7915 rx_status->rate_idx = 4;
7916 break;
7917 case BRCM_RATE_9M:
7918 rx_status->rate_idx = 5;
7919 break;
7920 case BRCM_RATE_12M:
7921 rx_status->rate_idx = 6;
7922 break;
7923 case BRCM_RATE_18M:
7924 rx_status->rate_idx = 7;
7925 break;
7926 case BRCM_RATE_24M:
7927 rx_status->rate_idx = 8;
7928 break;
7929 case BRCM_RATE_36M:
7930 rx_status->rate_idx = 9;
7931 break;
7932 case BRCM_RATE_48M:
7933 rx_status->rate_idx = 10;
7934 break;
7935 case BRCM_RATE_54M:
7936 rx_status->rate_idx = 11;
7937 break;
7938 default:
7939 wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
7940 }
7941
7942 /*
7943 * For 5GHz, we should decrease the index as it is
7944 * a subset of the 2.4G rates. See bitrates field
7945 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7946 */
7947 if (rx_status->band == IEEE80211_BAND_5GHZ)
7948 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7949
7950 /* Determine short preamble and rate_idx */
7951 preamble = 0;
7952 if (is_cck_rate(rspec)) {
7953 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7954 rx_status->flag |= RX_FLAG_SHORTPRE;
7955 } else if (is_ofdm_rate(rspec)) {
7956 rx_status->flag |= RX_FLAG_SHORTPRE;
7957 } else {
7958 wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
7959 __func__);
7960 }
7961 }
7962
7963 if (plcp3_issgi(plcp[3]))
7964 rx_status->flag |= RX_FLAG_SHORT_GI;
7965
7966 if (rxh->RxStatus1 & RXS_DECERR) {
7967 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7968 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7969 __func__);
7970 }
7971 if (rxh->RxStatus1 & RXS_FCSERR) {
7972 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7973 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7974 __func__);
7975 }
7976}
7977
7978static void
7979brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7980 struct sk_buff *p)
7981{
7982 int len_mpdu;
7983 struct ieee80211_rx_status rx_status;
7984
7985 memset(&rx_status, 0, sizeof(rx_status));
7986 prep_mac80211_status(wlc, rxh, p, &rx_status);
7987
7988 /* mac header+body length, exclude CRC and plcp header */
7989 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7990 skb_pull(p, D11_PHY_HDR_LEN);
7991 __skb_trim(p, len_mpdu);
7992
7993 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7994 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7995}
7996
7997/* Process received frames */
7998/*
7999 * Return true if more frames need to be processed. false otherwise.
8000 * Param 'bound' indicates max. # frames to process before break out.
8001 */
8002void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
8003{
8004 struct d11rxhdr *rxh;
8005 struct ieee80211_hdr *h;
8006 uint len;
8007 bool is_amsdu;
8008
8009 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8010
8011 /* frame starts with rxhdr */
8012 rxh = (struct d11rxhdr *) (p->data);
8013
8014 /* strip off rxhdr */
8015 skb_pull(p, BRCMS_HWRXOFF);
8016
8017 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
8018 if (rxh->RxStatus1 & RXS_PBPRES) {
8019 if (p->len < 2) {
8020 wiphy_err(wlc->wiphy, "wl%d: recv: rcvd runt of "
8021 "len %d\n", wlc->pub->unit, p->len);
8022 goto toss;
8023 }
8024 skb_pull(p, 2);
8025 }
8026
8027 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
8028 len = p->len;
8029
8030 if (rxh->RxStatus1 & RXS_FCSERR) {
8031 if (wlc->pub->mac80211_state & MAC80211_PROMISC_BCNS) {
8032 wiphy_err(wlc->wiphy, "FCSERR while scanning******* -"
8033 " tossing\n");
8034 goto toss;
8035 } else {
8036 wiphy_err(wlc->wiphy, "RCSERR!!!\n");
8037 goto toss;
8038 }
8039 }
8040
8041 /* check received pkt has at least frame control field */
8042 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
8043 goto toss;
8044
8045 /* not supporting A-MSDU */
8046 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
8047 if (is_amsdu)
8048 goto toss;
8049
8050 brcms_c_recvctl(wlc, rxh, p);
8051 return;
8052
8053 toss:
8054 brcmu_pkt_buf_free_skb(p);
8055}
8056
8057/* calculate frame duration for Mixed-mode L-SIG spoofing, return
8058 * number of bytes goes in the length field
8059 *
8060 * Formula given by HT PHY Spec v 1.13
8061 * len = 3(nsyms + nstream + 3) - 3
8062 */
8063u16
8064brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
8065 uint mac_len)
8066{
8067 uint nsyms, len = 0, kNdps;
8068
8069 BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
8070 wlc->pub->unit, rspec2rate(ratespec), mac_len);
8071
8072 if (is_mcs_rate(ratespec)) {
8073 uint mcs = ratespec & RSPEC_RATE_MASK;
8074 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
8075 rspec_stc(ratespec);
8076
8077 /*
8078 * the payload duration calculation matches that
8079 * of regular ofdm
8080 */
8081 /* 1000Ndbps = kbps * 4 */
8082 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
8083 rspec_issgi(ratespec)) * 4;
8084
8085 if (rspec_stc(ratespec) == 0)
8086 nsyms =
8087 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
8088 APHY_TAIL_NBITS) * 1000, kNdps);
8089 else
8090 /* STBC needs to have even number of symbols */
8091 nsyms =
8092 2 *
8093 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
8094 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
8095
8096 /* (+3) account for HT-SIG(2) and HT-STF(1) */
8097 nsyms += (tot_streams + 3);
8098 /*
8099 * 3 bytes/symbol @ legacy 6Mbps rate
8100 * (-3) excluding service bits and tail bits
8101 */
8102 len = (3 * nsyms) - 3;
8103 }
8104
8105 return (u16) len;
8106}
8107
8108/*
8109 * calculate frame duration of a given rate and length, return
8110 * time in usec unit
8111 */
8112uint
8113brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
8114 u8 preamble_type, uint mac_len)
8115{
8116 uint nsyms, dur = 0, Ndps, kNdps;
8117 uint rate = rspec2rate(ratespec);
8118
8119 if (rate == 0) {
8120 wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
8121 wlc->pub->unit);
8122 rate = BRCM_RATE_1M;
8123 }
8124
8125 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
8126 wlc->pub->unit, ratespec, preamble_type, mac_len);
8127
8128 if (is_mcs_rate(ratespec)) {
8129 uint mcs = ratespec & RSPEC_RATE_MASK;
8130 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
8131
8132 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
8133 if (preamble_type == BRCMS_MM_PREAMBLE)
8134 dur += PREN_MM_EXT;
8135 /* 1000Ndbps = kbps * 4 */
8136 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
8137 rspec_issgi(ratespec)) * 4;
8138
8139 if (rspec_stc(ratespec) == 0)
8140 nsyms =
8141 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
8142 APHY_TAIL_NBITS) * 1000, kNdps);
8143 else
8144 /* STBC needs to have even number of symbols */
8145 nsyms =
8146 2 *
8147 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
8148 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
8149
8150 dur += APHY_SYMBOL_TIME * nsyms;
8151 if (wlc->band->bandtype == BRCM_BAND_2G)
8152 dur += DOT11_OFDM_SIGNAL_EXTENSION;
8153 } else if (is_ofdm_rate(rate)) {
8154 dur = APHY_PREAMBLE_TIME;
8155 dur += APHY_SIGNAL_TIME;
8156 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
8157 Ndps = rate * 2;
8158 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
8159 nsyms =
8160 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
8161 Ndps);
8162 dur += APHY_SYMBOL_TIME * nsyms;
8163 if (wlc->band->bandtype == BRCM_BAND_2G)
8164 dur += DOT11_OFDM_SIGNAL_EXTENSION;
8165 } else {
8166 /*
8167 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
8168 * will divide out
8169 */
8170 mac_len = mac_len * 8 * 2;
8171 /* calc ceiling of bits/rate = microseconds of air time */
8172 dur = (mac_len + rate - 1) / rate;
8173 if (preamble_type & BRCMS_SHORT_PREAMBLE)
8174 dur += BPHY_PLCP_SHORT_TIME;
8175 else
8176 dur += BPHY_PLCP_TIME;
8177 }
8178 return dur;
8179}
8180
8181/* derive wlc->band->basic_rate[] table from 'rateset' */
8182void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
8183 struct brcms_c_rateset *rateset)
8184{
8185 u8 rate;
8186 u8 mandatory;
8187 u8 cck_basic = 0;
8188 u8 ofdm_basic = 0;
8189 u8 *br = wlc->band->basic_rate;
8190 uint i;
8191
8192 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
8193 memset(br, 0, BRCM_MAXRATE + 1);
8194
8195 /* For each basic rate in the rates list, make an entry in the
8196 * best basic lookup.
8197 */
8198 for (i = 0; i < rateset->count; i++) {
8199 /* only make an entry for a basic rate */
8200 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
8201 continue;
8202
8203 /* mask off basic bit */
8204 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
8205
8206 if (rate > BRCM_MAXRATE) {
8207 wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: "
8208 "invalid rate 0x%X in rate set\n",
8209 rateset->rates[i]);
8210 continue;
8211 }
8212
8213 br[rate] = rate;
8214 }
8215
8216 /* The rate lookup table now has non-zero entries for each
8217 * basic rate, equal to the basic rate: br[basicN] = basicN
8218 *
8219 * To look up the best basic rate corresponding to any
8220 * particular rate, code can use the basic_rate table
8221 * like this
8222 *
8223 * basic_rate = wlc->band->basic_rate[tx_rate]
8224 *
8225 * Make sure there is a best basic rate entry for
8226 * every rate by walking up the table from low rates
8227 * to high, filling in holes in the lookup table
8228 */
8229
8230 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
8231 rate = wlc->band->hw_rateset.rates[i];
8232
8233 if (br[rate] != 0) {
8234 /* This rate is a basic rate.
8235 * Keep track of the best basic rate so far by
8236 * modulation type.
8237 */
8238 if (is_ofdm_rate(rate))
8239 ofdm_basic = rate;
8240 else
8241 cck_basic = rate;
8242
8243 continue;
8244 }
8245
8246 /* This rate is not a basic rate so figure out the
8247 * best basic rate less than this rate and fill in
8248 * the hole in the table
8249 */
8250
8251 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
8252
8253 if (br[rate] != 0)
8254 continue;
8255
8256 if (is_ofdm_rate(rate)) {
8257 /*
8258 * In 11g and 11a, the OFDM mandatory rates
8259 * are 6, 12, and 24 Mbps
8260 */
8261 if (rate >= BRCM_RATE_24M)
8262 mandatory = BRCM_RATE_24M;
8263 else if (rate >= BRCM_RATE_12M)
8264 mandatory = BRCM_RATE_12M;
8265 else
8266 mandatory = BRCM_RATE_6M;
8267 } else {
8268 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
8269 mandatory = rate;
8270 }
8271
8272 br[rate] = mandatory;
8273 }
8274}
8275
8276static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
8277 u8 basic_rate)
8278{
8279 u8 phy_rate, index;
8280 u8 basic_phy_rate, basic_index;
8281 u16 dir_table, basic_table;
8282 u16 basic_ptr;
8283
8284 /* Shared memory address for the table we are reading */
8285 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
8286
8287 /* Shared memory address for the table we are writing */
8288 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
8289
8290 /*
8291 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
8292 * the index into the rate table.
8293 */
8294 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
8295 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
8296 index = phy_rate & 0xf;
8297 basic_index = basic_phy_rate & 0xf;
8298
8299 /* Find the SHM pointer to the ACK rate entry by looking in the
8300 * Direct-map Table
8301 */
8302 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
8303
8304 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
8305 * to the correct basic rate for the given incoming rate
8306 */
8307 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
8308}
8309
8310static const struct brcms_c_rateset *
8311brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
8312{
8313 const struct brcms_c_rateset *rs_dflt;
8314
8315 if (BRCMS_PHY_11N_CAP(wlc->band)) {
8316 if (wlc->band->bandtype == BRCM_BAND_5G)
8317 rs_dflt = &ofdm_mimo_rates;
8318 else
8319 rs_dflt = &cck_ofdm_mimo_rates;
8320 } else if (wlc->band->gmode)
8321 rs_dflt = &cck_ofdm_rates;
8322 else
8323 rs_dflt = &cck_rates;
8324
8325 return rs_dflt;
8326}
8327
8328void brcms_c_set_ratetable(struct brcms_c_info *wlc)
8329{
8330 const struct brcms_c_rateset *rs_dflt;
8331 struct brcms_c_rateset rs;
8332 u8 rate, basic_rate;
8333 uint i;
8334
8335 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
8336
8337 brcms_c_rateset_copy(rs_dflt, &rs);
8338 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
8339
8340 /* walk the phy rate table and update SHM basic rate lookup table */
8341 for (i = 0; i < rs.count; i++) {
8342 rate = rs.rates[i] & BRCMS_RATE_MASK;
8343
8344 /* for a given rate brcms_basic_rate returns the rate at
8345 * which a response ACK/CTS should be sent.
8346 */
8347 basic_rate = brcms_basic_rate(wlc, rate);
8348 if (basic_rate == 0)
8349 /* This should only happen if we are using a
8350 * restricted rateset.
8351 */
8352 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
8353
8354 brcms_c_write_rate_shm(wlc, rate, basic_rate);
8355 }
8356}
8357
8358/*
8359 * Return true if the specified rate is supported by the specified band.
8360 * BRCM_BAND_AUTO indicates the current band.
8361 */
8362bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
8363 bool verbose)
8364{
8365 struct brcms_c_rateset *hw_rateset;
8366 uint i;
8367
8368 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
8369 hw_rateset = &wlc->band->hw_rateset;
8370 else if (wlc->pub->_nbands > 1)
8371 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
8372 else
8373 /* other band specified and we are a single band device */
8374 return false;
8375
8376 /* check if this is a mimo rate */
8377 if (is_mcs_rate(rspec)) {
8378 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
8379 goto error;
8380
8381 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
8382 }
8383
8384 for (i = 0; i < hw_rateset->count; i++)
8385 if (hw_rateset->rates[i] == rspec2rate(rspec))
8386 return true;
8387 error:
8388 if (verbose)
8389 wiphy_err(wlc->wiphy, "wl%d: valid_rate: rate spec 0x%x "
8390 "not in hw_rateset\n", wlc->pub->unit, rspec);
8391
8392 return false;
8393}
8394
8395void brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
8396{
8397 const struct brcms_c_rateset *rs_dflt;
8398 struct brcms_c_rateset rs;
8399 u8 rate;
8400 u16 entry_ptr;
8401 u8 plcp[D11_PHY_HDR_LEN];
8402 u16 dur, sifs;
8403 uint i;
8404
8405 sifs = get_sifs(wlc->band);
8406
8407 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
8408
8409 brcms_c_rateset_copy(rs_dflt, &rs);
8410 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
8411
8412 /*
8413 * walk the phy rate table and update MAC core SHM
8414 * basic rate table entries
8415 */
8416 for (i = 0; i < rs.count; i++) {
8417 rate = rs.rates[i] & BRCMS_RATE_MASK;
8418
8419 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
8420
8421 /* Calculate the Probe Response PLCP for the given rate */
8422 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
8423
8424 /*
8425 * Calculate the duration of the Probe Response
8426 * frame plus SIFS for the MAC
8427 */
8428 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
8429 BRCMS_LONG_PREAMBLE, frame_len);
8430 dur += sifs;
8431
8432 /* Update the SHM Rate Table entry Probe Response values */
8433 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
8434 (u16) (plcp[0] + (plcp[1] << 8)));
8435 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
8436 (u16) (plcp[2] + (plcp[3] << 8)));
8437 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
8438 }
8439}
8440
8441/* Max buffering needed for beacon template/prb resp template is 142 bytes.
8442 *
8443 * PLCP header is 6 bytes.
8444 * 802.11 A3 header is 24 bytes.
8445 * Max beacon frame body template length is 112 bytes.
8446 * Max probe resp frame body template length is 110 bytes.
8447 *
8448 * *len on input contains the max length of the packet available.
8449 *
8450 * The *len value is set to the number of bytes in buf used, and starts
8451 * with the PLCP and included up to, but not including, the 4 byte FCS.
8452 */
8453static void
8454brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
8455 u32 bcn_rspec,
8456 struct brcms_bss_cfg *cfg, u16 *buf, int *len)
8457{
8458 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
8459 struct cck_phy_hdr *plcp;
8460 struct ieee80211_mgmt *h;
8461 int hdr_len, body_len;
8462
8463 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
8464
8465 /* calc buffer size provided for frame body */
8466 body_len = *len - hdr_len;
8467 /* return actual size */
8468 *len = hdr_len + body_len;
8469
8470 /* format PHY and MAC headers */
8471 memset((char *)buf, 0, hdr_len);
8472
8473 plcp = (struct cck_phy_hdr *) buf;
8474
8475 /*
8476 * PLCP for Probe Response frames are filled in from
8477 * core's rate table
8478 */
8479 if (type == IEEE80211_STYPE_BEACON)
8480 /* fill in PLCP */
8481 brcms_c_compute_plcp(wlc, bcn_rspec,
8482 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
8483 (u8 *) plcp);
8484
8485 /* "Regular" and 16 MBSS but not for 4 MBSS */
8486 /* Update the phytxctl for the beacon based on the rspec */
8487 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
8488
8489 h = (struct ieee80211_mgmt *)&plcp[1];
8490
8491 /* fill in 802.11 header */
8492 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
8493
8494 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
8495 /* A1 filled in by MAC for prb resp, broadcast for bcn */
8496 if (type == IEEE80211_STYPE_BEACON)
8497 memcpy(&h->da, &ether_bcast, ETH_ALEN);
8498 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
8499 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
8500
8501 /* SEQ filled in by MAC */
8502}
8503
8504int brcms_c_get_header_len(void)
8505{
8506 return TXOFF;
8507}
8508
8509/*
8510 * Update all beacons for the system.
8511 */
8512void brcms_c_update_beacon(struct brcms_c_info *wlc)
8513{
8514 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
8515
8516 if (bsscfg->up && !bsscfg->BSS)
8517 /* Clear the soft intmask */
8518 wlc->defmacintmask &= ~MI_BCNTPL;
8519}
8520
8521/* Write ssid into shared memory */
8522void brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
8523{
8524 u8 *ssidptr = cfg->SSID;
8525 u16 base = M_SSID;
8526 u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
8527
8528 /* padding the ssid with zero and copy it into shm */
8529 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
8530 memcpy(ssidbuf, ssidptr, cfg->SSID_len);
8531
8532 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
8533 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
8534}
8535
8536void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
8537{
8538 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
8539
8540 /* update AP or IBSS probe responses */
8541 if (bsscfg->up && !bsscfg->BSS)
8542 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
8543}
8544
8545void
8546brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
8547 struct brcms_bss_cfg *cfg,
8548 bool suspend)
8549{
8550 u16 prb_resp[BCN_TMPL_LEN / 2];
8551 int len = BCN_TMPL_LEN;
8552
8553 /*
8554 * write the probe response to hardware, or save in
8555 * the config structure
8556 */
8557
8558 /* create the probe response template */
8559 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
8560 cfg, prb_resp, &len);
8561
8562 if (suspend)
8563 brcms_c_suspend_mac_and_wait(wlc);
8564
8565 /* write the probe response into the template region */
8566 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
8567 (len + 3) & ~3, prb_resp);
8568
8569 /* write the length of the probe response frame (+PLCP/-FCS) */
8570 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
8571
8572 /* write the SSID and SSID length */
8573 brcms_c_shm_ssid_upd(wlc, cfg);
8574
8575 /*
8576 * Write PLCP headers and durations for probe response frames
8577 * at all rates. Use the actual frame length covered by the
8578 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
8579 * by subtracting the PLCP len and adding the FCS.
8580 */
8581 len += (-D11_PHY_HDR_LEN + FCS_LEN);
8582 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
8583
8584 if (suspend)
8585 brcms_c_enable_mac(wlc);
8586}
8587
8588/* prepares pdu for transmission. returns BCM error codes */
8589int brcms_c_prep_pdu(struct brcms_c_info *wlc, struct sk_buff *pdu, uint *fifop)
8590{
8591 uint fifo;
8592 struct d11txh *txh;
8593 struct ieee80211_hdr *h;
8594 struct scb *scb;
8595
8596 txh = (struct d11txh *) (pdu->data);
8597 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
8598
8599 /* get the pkt queue info. This was put at brcms_c_sendctl or
8600 * brcms_c_send for PDU */
8601 fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
8602
8603 scb = NULL;
8604
8605 *fifop = fifo;
8606
8607 /* return if insufficient dma resources */
8608 if (*wlc->core->txavail[fifo] < MAX_DMA_SEGS) {
8609 /* Mark precedences related to this FIFO, unsendable */
8610 /* A fifo is full. Clear precedences related to that FIFO */
8611 wlc->tx_prec_map &= ~(wlc->fifo2prec_map[fifo]);
8612 return -EBUSY;
8613 }
8614 return 0;
8615}
8616
8617void brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
8618{
8619 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
8620 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
8621 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
8622 brcms_chspec_bw(wlc->default_bss->chanspec),
8623 wlc->stf->txstreams);
8624}
8625
8626/* Copy a buffer to shared memory.
8627 * SHM 'offset' needs to be an even address and
8628 * Buffer length 'len' must be an even number of bytes
8629 */
8630void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset, const void *buf,
8631 int len)
8632{
8633 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
8634}
8635
8636int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
8637 uint *blocks)
8638{
8639 if (fifo >= NFIFO)
8640 return -EINVAL;
8641
8642 *blocks = wlc_hw->xmtfifo_sz[fifo];
8643
8644 return 0;
8645}
8646
8647void
8648brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
8649 const u8 *addr)
8650{
8651 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
8652 if (match_reg_offset == RCM_BSSID_OFFSET)
8653 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
8654}
8655
8656/* check for the particular priority flow control bit being set */
8657bool
8658brcms_c_txflowcontrol_prio_isset(struct brcms_c_info *wlc,
8659 struct brcms_txq_info *q,
8660 int prio)
8661{
8662 uint prio_mask;
8663
8664 if (prio == ALLPRIO)
8665 prio_mask = TXQ_STOP_FOR_PRIOFC_MASK;
8666 else
8667 prio_mask = NBITVAL(prio);
8668
8669 return (q->stopped & prio_mask) == prio_mask;
8670}
8671
8672/* propagate the flow control to all interfaces using the given tx queue */
8673void brcms_c_txflowcontrol(struct brcms_c_info *wlc,
8674 struct brcms_txq_info *qi,
8675 bool on, int prio)
8676{
8677 uint prio_bits;
8678 uint cur_bits;
8679
8680 BCMMSG(wlc->wiphy, "flow control kicks in\n");
8681
8682 if (prio == ALLPRIO)
8683 prio_bits = TXQ_STOP_FOR_PRIOFC_MASK;
8684 else
8685 prio_bits = NBITVAL(prio);
8686
8687 cur_bits = qi->stopped & prio_bits;
8688
8689 /* Check for the case of no change and return early
8690 * Otherwise update the bit and continue
8691 */
8692 if (on) {
8693 if (cur_bits == prio_bits)
8694 return;
8695
8696 mboolset(qi->stopped, prio_bits);
8697 } else {
8698 if (cur_bits == 0)
8699 return;
8700
8701 mboolclr(qi->stopped, prio_bits);
8702 }
8703
8704 /* If there is a flow control override we will not change the external
8705 * flow control state.
8706 */
8707 if (qi->stopped & ~TXQ_STOP_FOR_PRIOFC_MASK)
8708 return;
8709
8710 brcms_c_txflowcontrol_signal(wlc, qi, on, prio);
8711}
8712
8713void
8714brcms_c_txflowcontrol_override(struct brcms_c_info *wlc,
8715 struct brcms_txq_info *qi,
8716 bool on, uint override)
8717{
8718 uint prev_override;
8719
8720 prev_override = (qi->stopped & ~TXQ_STOP_FOR_PRIOFC_MASK);
8721
8722 /* Update the flow control bits and do an early return if there is
8723 * no change in the external flow control state.
8724 */
8725 if (on) {
8726 mboolset(qi->stopped, override);
8727 /* if there was a previous override bit on, then setting this
8728 * makes no difference.
8729 */
8730 if (prev_override)
8731 return;
8732
8733 brcms_c_txflowcontrol_signal(wlc, qi, ON, ALLPRIO);
8734 } else {
8735 mboolclr(qi->stopped, override);
8736 /* clearing an override bit will only make a difference for
8737 * flow control if it was the only bit set. For any other
8738 * override setting, just return
8739 */
8740 if (prev_override != override)
8741 return;
8742
8743 if (qi->stopped == 0) {
8744 brcms_c_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
8745 } else {
8746 int prio;
8747
8748 for (prio = MAXPRIO; prio >= 0; prio--) {
8749 if (!mboolisset(qi->stopped, NBITVAL(prio)))
8750 brcms_c_txflowcontrol_signal(
8751 wlc, qi, OFF, prio);
8752 }
8753 }
8754 }
8755}
8756
8757/*
8758 * Flag 'scan in progress' to withhold dynamic phy calibration
8759 */
8760void brcms_c_scan_start(struct brcms_c_info *wlc)
8761{
8762 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
8763}
8764
8765void brcms_c_scan_stop(struct brcms_c_info *wlc)
8766{
8767 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
8768}
8769
8770void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
8771{
8772 wlc->pub->associated = state;
8773 wlc->bsscfg->associated = state;
8774}
8775
8776/*
8777 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
8778 * AMPDU traffic, packets pending in hardware have to be invalidated so that
8779 * when later on hardware releases them, they can be handled appropriately.
8780 */
8781void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
8782 struct ieee80211_sta *sta,
8783 void (*dma_callback_fn))
8784{
8785 struct dma_pub *dmah;
8786 int i;
8787 for (i = 0; i < NFIFO; i++) {
8788 dmah = hw->di[i];
8789 if (dmah != NULL)
8790 dma_walk_packets(dmah, dma_callback_fn, sta);
8791 }
8792}
8793
8794int brcms_c_get_curband(struct brcms_c_info *wlc)
8795{
8796 return wlc->band->bandunit;
8797}
8798
8799void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
8800{
8801 /* flush packet queue when requested */
8802 if (drop)
8803 brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL);
8804
8805 /* wait for queue and DMA fifos to run dry */
8806 while (!pktq_empty(&wlc->pkt_queue->q) || brcms_txpktpendtot(wlc) > 0)
8807 brcms_msleep(wlc->wl, 1);
8808}
8809
8810void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
8811{
8812 wlc->bcn_li_bcn = interval;
8813 if (wlc->pub->up)
8814 brcms_c_bcn_li_upd(wlc);
8815}
8816
8817int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
8818{
8819 uint qdbm;
8820
8821 /* Remove override bit and clip to max qdbm value */
8822 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
8823 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
8824}
8825
8826int brcms_c_get_tx_power(struct brcms_c_info *wlc)
8827{
8828 uint qdbm;
8829 bool override;
8830
8831 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
8832
8833 /* Return qdbm units */
8834 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
8835}
8836
8837void brcms_c_set_radio_mpc(struct brcms_c_info *wlc, bool mpc)
8838{
8839 wlc->mpc = mpc;
8840 brcms_c_radio_mpc_upd(wlc);
8841}
diff --git a/drivers/staging/brcm80211/brcmsmac/main.h b/drivers/staging/brcm80211/brcmsmac/main.h
deleted file mode 100644
index 7a2554f611a..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/main.h
+++ /dev/null
@@ -1,819 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_MAIN_H_
18#define _BRCM_MAIN_H_
19
20#include <linux/etherdevice.h>
21
22#include <brcmu_utils.h>
23#include "types.h"
24#include "d11.h"
25#include "scb.h"
26
27#define INVCHANNEL 255 /* invalid channel */
28
29/* max # brcms_c_module_register() calls */
30#define BRCMS_MAXMODULES 22
31
32#define SEQNUM_SHIFT 4
33#define SEQNUM_MAX 0x1000
34
35#define NTXRATE 64 /* # tx MPDUs rate is reported for */
36
37/* Maximum wait time for a MAC suspend */
38/* uS: 83mS is max packet time (64KB ampdu @ 6Mbps) */
39#define BRCMS_MAX_MAC_SUSPEND 83000
40
41/* responses for probe requests older that this are tossed, zero to disable */
42#define BRCMS_PRB_RESP_TIMEOUT 0 /* Disable probe response timeout */
43
44/* transmit buffer max headroom for protocol headers */
45#define TXOFF (D11_TXH_LEN + D11_PHY_HDR_LEN)
46
47#define AC_COUNT 4
48
49/* Macros for doing definition and get/set of bitfields
50 * Usage example, e.g. a three-bit field (bits 4-6):
51 * #define <NAME>_M BITFIELD_MASK(3)
52 * #define <NAME>_S 4
53 * ...
54 * regval = R_REG(osh, &regs->regfoo);
55 * field = GFIELD(regval, <NAME>);
56 * regval = SFIELD(regval, <NAME>, 1);
57 * W_REG(osh, &regs->regfoo, regval);
58 */
59#define BITFIELD_MASK(width) \
60 (((unsigned)1 << (width)) - 1)
61#define GFIELD(val, field) \
62 (((val) >> field ## _S) & field ## _M)
63#define SFIELD(val, field, bits) \
64 (((val) & (~(field ## _M << field ## _S))) | \
65 ((unsigned)(bits) << field ## _S))
66
67#define SW_TIMER_MAC_STAT_UPD 30 /* periodic MAC stats update */
68
69/* max # supported core revisions (0 .. MAXCOREREV - 1) */
70#define MAXCOREREV 28
71
72/* Double check that unsupported cores are not enabled */
73#if CONF_MSK(D11CONF, 0x4f) || CONF_GE(D11CONF, MAXCOREREV)
74#error "Configuration for D11CONF includes unsupported versions."
75#endif /* Bad versions */
76
77/* values for shortslot_override */
78#define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
79#define BRCMS_SHORTSLOT_OFF 0 /* Turn off short slot */
80#define BRCMS_SHORTSLOT_ON 1 /* Turn on short slot */
81
82/* value for short/long and mixmode/greenfield preamble */
83#define BRCMS_LONG_PREAMBLE (0)
84#define BRCMS_SHORT_PREAMBLE (1 << 0)
85#define BRCMS_GF_PREAMBLE (1 << 1)
86#define BRCMS_MM_PREAMBLE (1 << 2)
87#define BRCMS_IS_MIMO_PREAMBLE(_pre) (((_pre) == BRCMS_GF_PREAMBLE) || \
88 ((_pre) == BRCMS_MM_PREAMBLE))
89
90/* TxFrameID */
91/* seq and frag bits: SEQNUM_SHIFT, FRAGNUM_MASK (802.11.h) */
92/* rate epoch bits: TXFID_RATE_SHIFT, TXFID_RATE_MASK ((wlc_rate.c) */
93#define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
94#define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
95#define TXFID_SEQ_SHIFT 5 /* Number of bit shifts */
96#define TXFID_RATE_PROBE_MASK 0x8000 /* Bit 15 for rate probe */
97#define TXFID_RATE_MASK 0x0018 /* Mask for bits 3 and 4 */
98#define TXFID_RATE_SHIFT 3 /* Shift 3 bits for rate mask */
99
100/* promote boardrev */
101#define BOARDREV_PROMOTABLE 0xFF /* from */
102#define BOARDREV_PROMOTED 1 /* to */
103
104#define DATA_BLOCK_TX_SUPR (1 << 4)
105
106/* 802.1D Priority to TX FIFO number for wme */
107extern const u8 prio2fifo[];
108
109/* Ucode MCTL_WAKE override bits */
110#define BRCMS_WAKE_OVERRIDE_CLKCTL 0x01
111#define BRCMS_WAKE_OVERRIDE_PHYREG 0x02
112#define BRCMS_WAKE_OVERRIDE_MACSUSPEND 0x04
113#define BRCMS_WAKE_OVERRIDE_TXFIFO 0x08
114#define BRCMS_WAKE_OVERRIDE_FORCEFAST 0x10
115
116/* stuff pulled in from wlc.c */
117
118/* Interrupt bit error summary. Don't include I_RU: we refill DMA at other
119 * times; and if we run out, constant I_RU interrupts may cause lockup. We
120 * will still get error counts from rx0ovfl.
121 */
122#define I_ERRORS (I_PC | I_PD | I_DE | I_RO | I_XU)
123/* default software intmasks */
124#define DEF_RXINTMASK (I_RI) /* enable rx int on rxfifo only */
125#define DEF_MACINTMASK (MI_TXSTOP | MI_TBTT | MI_ATIMWINEND | MI_PMQ | \
126 MI_PHYTXERR | MI_DMAINT | MI_TFS | MI_BG_NOISE | \
127 MI_CCA | MI_TO | MI_GP0 | MI_RFDISABLE | MI_PWRUP)
128
129#define MAXTXPKTS 6 /* max # pkts pending */
130
131/* frameburst */
132#define MAXTXFRAMEBURST 8 /* vanilla xpress mode: max frames/burst */
133#define MAXFRAMEBURST_TXOP 10000 /* Frameburst TXOP in usec */
134
135#define NFIFO 6 /* # tx/rx fifopairs */
136
137/* PLL requests */
138
139/* pll is shared on old chips */
140#define BRCMS_PLLREQ_SHARED 0x1
141/* hold pll for radio monitor register checking */
142#define BRCMS_PLLREQ_RADIO_MON 0x2
143/* hold/release pll for some short operation */
144#define BRCMS_PLLREQ_FLIP 0x4
145
146#define CHANNEL_BANDUNIT(wlc, ch) \
147 (((ch) <= CH_MAX_2G_CHANNEL) ? BAND_2G_INDEX : BAND_5G_INDEX)
148
149#define OTHERBANDUNIT(wlc) \
150 ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))
151
152/*
153 * 802.11 protection information
154 *
155 * _g: use g spec protection, driver internal.
156 * g_override: override for use of g spec protection.
157 * gmode_user: user config gmode, operating band->gmode is different.
158 * overlap: Overlap BSS/IBSS protection for both 11g and 11n.
159 * nmode_user: user config nmode, operating pub->nmode is different.
160 * n_cfg: use OFDM protection on MIMO frames.
161 * n_cfg_override: override for use of N protection.
162 * nongf: non-GF present protection.
163 * nongf_override: override for use of GF protection.
164 * n_pam_override: override for preamble: MM or GF.
165 * n_obss: indicated OBSS Non-HT STA present.
166*/
167struct brcms_protection {
168 bool _g;
169 s8 g_override;
170 u8 gmode_user;
171 s8 overlap;
172 s8 nmode_user;
173 s8 n_cfg;
174 s8 n_cfg_override;
175 bool nongf;
176 s8 nongf_override;
177 s8 n_pam_override;
178 bool n_obss;
179};
180
181/*
182 * anything affecting the single/dual streams/antenna operation
183 *
184 * hw_txchain: HW txchain bitmap cfg.
185 * txchain: txchain bitmap being used.
186 * txstreams: number of txchains being used.
187 * hw_rxchain: HW rxchain bitmap cfg.
188 * rxchain: rxchain bitmap being used.
189 * rxstreams: number of rxchains being used.
190 * ant_rx_ovr: rx antenna override.
191 * txant: userTx antenna setting.
192 * phytxant: phyTx antenna setting in txheader.
193 * ss_opmode: singlestream Operational mode, 0:siso; 1:cdd.
194 * ss_algosel_auto: if true, use wlc->stf->ss_algo_channel;
195 * else use wlc->band->stf->ss_mode_band.
196 * ss_algo_channel: ss based on per-channel algo: 0: SISO, 1: CDD 2: STBC.
197 * rxchain_restore_delay: delay time to restore default rxchain.
198 * ldpc: AUTO/ON/OFF ldpc cap supported.
199 * txcore[MAX_STREAMS_SUPPORTED + 1]: bitmap of selected core for each Nsts.
200 * spatial_policy:
201 */
202struct brcms_stf {
203 u8 hw_txchain;
204 u8 txchain;
205 u8 txstreams;
206 u8 hw_rxchain;
207 u8 rxchain;
208 u8 rxstreams;
209 u8 ant_rx_ovr;
210 s8 txant;
211 u16 phytxant;
212 u8 ss_opmode;
213 bool ss_algosel_auto;
214 u16 ss_algo_channel;
215 u8 rxchain_restore_delay;
216 s8 ldpc;
217 u8 txcore[MAX_STREAMS_SUPPORTED + 1];
218 s8 spatial_policy;
219};
220
221#define BRCMS_STF_SS_STBC_TX(wlc, scb) \
222 (((wlc)->stf->txstreams > 1) && (((wlc)->band->band_stf_stbc_tx == ON) \
223 || (((scb)->flags & SCB_STBCCAP) && \
224 (wlc)->band->band_stf_stbc_tx == AUTO && \
225 isset(&((wlc)->stf->ss_algo_channel), PHY_TXC1_MODE_STBC))))
226
227#define BRCMS_STBC_CAP_PHY(wlc) (BRCMS_ISNPHY(wlc->band) && \
228 NREV_GE(wlc->band->phyrev, 3))
229
230#define BRCMS_SGI_CAP_PHY(wlc) ((BRCMS_ISNPHY(wlc->band) && \
231 NREV_GE(wlc->band->phyrev, 3)) || \
232 BRCMS_ISLCNPHY(wlc->band))
233
234#define BRCMS_CHAN_PHYTYPE(x) (((x) & RXS_CHAN_PHYTYPE_MASK) \
235 >> RXS_CHAN_PHYTYPE_SHIFT)
236#define BRCMS_CHAN_CHANNEL(x) (((x) & RXS_CHAN_ID_MASK) \
237 >> RXS_CHAN_ID_SHIFT)
238
239/*
240 * core state (mac)
241 */
242struct brcms_core {
243 uint coreidx; /* # sb enumerated core */
244
245 /* fifo */
246 uint *txavail[NFIFO]; /* # tx descriptors available */
247 s16 txpktpend[NFIFO]; /* tx admission control */
248
249 struct macstat *macstat_snapshot; /* mac hw prev read values */
250};
251
252/*
253 * band state (phy+ana+radio)
254 */
255struct brcms_band {
256 int bandtype; /* BRCM_BAND_2G, BRCM_BAND_5G */
257 uint bandunit; /* bandstate[] index */
258
259 u16 phytype; /* phytype */
260 u16 phyrev;
261 u16 radioid;
262 u16 radiorev;
263 struct brcms_phy_pub *pi; /* pointer to phy specific information */
264 bool abgphy_encore;
265
266 u8 gmode; /* currently active gmode */
267
268 struct scb *hwrs_scb; /* permanent scb for hw rateset */
269
270 /* band-specific copy of default_bss.rateset */
271 struct brcms_c_rateset defrateset;
272
273 u8 band_stf_ss_mode; /* Configured STF type, 0:siso; 1:cdd */
274 s8 band_stf_stbc_tx; /* STBC TX 0:off; 1:force on; -1:auto */
275 /* rates supported by chip (phy-specific) */
276 struct brcms_c_rateset hw_rateset;
277 u8 basic_rate[BRCM_MAXRATE + 1]; /* basic rates indexed by rate */
278 bool mimo_cap_40; /* 40 MHz cap enabled on this band */
279 s8 antgain; /* antenna gain from srom */
280
281 u16 CWmin; /* minimum size of contention window, in unit of aSlotTime */
282 u16 CWmax; /* maximum size of contention window, in unit of aSlotTime */
283 struct ieee80211_supported_band band;
284};
285
286/* module control blocks */
287struct modulecb {
288 /* module name : NULL indicates empty array member */
289 char name[32];
290 /* handle passed when handler 'doiovar' is called */
291 struct brcms_info *hdl;
292
293 int (*down_fn)(void *handle); /* down handler. Note: the int returned
294 * by the down function is a count of the
295 * number of timers that could not be
296 * freed.
297 */
298
299};
300
301struct brcms_hw_band {
302 int bandtype; /* BRCM_BAND_2G, BRCM_BAND_5G */
303 uint bandunit; /* bandstate[] index */
304 u16 mhfs[MHFMAX]; /* MHF array shadow */
305 u8 bandhw_stf_ss_mode; /* HW configured STF type, 0:siso; 1:cdd */
306 u16 CWmin;
307 u16 CWmax;
308 u32 core_flags;
309
310 u16 phytype; /* phytype */
311 u16 phyrev;
312 u16 radioid;
313 u16 radiorev;
314 struct brcms_phy_pub *pi; /* pointer to phy specific information */
315 bool abgphy_encore;
316};
317
318struct brcms_hardware {
319 bool _piomode; /* true if pio mode */
320 struct brcms_c_info *wlc;
321
322 /* fifo */
323 struct dma_pub *di[NFIFO]; /* dma handles, per fifo */
324
325 uint unit; /* device instance number */
326
327 /* version info */
328 u16 vendorid; /* PCI vendor id */
329 u16 deviceid; /* PCI device id */
330 uint corerev; /* core revision */
331 u8 sromrev; /* version # of the srom */
332 u16 boardrev; /* version # of particular board */
333 u32 boardflags; /* Board specific flags from srom */
334 u32 boardflags2; /* More board flags if sromrev >= 4 */
335 u32 machwcap; /* MAC capabilities */
336 u32 machwcap_backup; /* backup of machwcap */
337
338 struct si_pub *sih; /* SI handle (cookie for siutils calls) */
339 struct d11regs __iomem *regs; /* pointer to device registers */
340 struct phy_shim_info *physhim; /* phy shim layer handler */
341 struct shared_phy *phy_sh; /* pointer to shared phy state */
342 struct brcms_hw_band *band;/* pointer to active per-band state */
343 /* band state per phy/radio */
344 struct brcms_hw_band *bandstate[MAXBANDS];
345 u16 bmac_phytxant; /* cache of high phytxant state */
346 bool shortslot; /* currently using 11g ShortSlot timing */
347 u16 SRL; /* 802.11 dot11ShortRetryLimit */
348 u16 LRL; /* 802.11 dot11LongRetryLimit */
349 u16 SFBL; /* Short Frame Rate Fallback Limit */
350 u16 LFBL; /* Long Frame Rate Fallback Limit */
351
352 bool up; /* d11 hardware up and running */
353 uint now; /* # elapsed seconds */
354 uint _nbands; /* # bands supported */
355 u16 chanspec; /* bmac chanspec shadow */
356
357 uint *txavail[NFIFO]; /* # tx descriptors available */
358 const u16 *xmtfifo_sz; /* fifo size in 256B for each xmt fifo */
359
360 u32 pllreq; /* pll requests to keep PLL on */
361
362 u8 suspended_fifos; /* Which TX fifo to remain awake for */
363 u32 maccontrol; /* Cached value of maccontrol */
364 uint mac_suspend_depth; /* current depth of mac_suspend levels */
365 u32 wake_override; /* bit flags to force MAC to WAKE mode */
366 u32 mute_override; /* Prevent ucode from sending beacons */
367 u8 etheraddr[ETH_ALEN]; /* currently configured ethernet address */
368 bool noreset; /* true= do not reset hw, used by WLC_OUT */
369 bool forcefastclk; /* true if h/w is forcing to use fast clk */
370 bool clk; /* core is out of reset and has clock */
371 bool sbclk; /* sb has clock */
372 bool phyclk; /* phy is out of reset and has clock */
373
374 bool ucode_loaded; /* true after ucode downloaded */
375
376
377 u8 hw_stf_ss_opmode; /* STF single stream operation mode */
378 u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic
379 * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board
380 */
381 u32 antsel_avail; /*
382 * put struct antsel_info here if more info is
383 * needed
384 */
385};
386
387/* TX Queue information
388 *
389 * Each flow of traffic out of the device has a TX Queue with independent
390 * flow control. Several interfaces may be associated with a single TX Queue
391 * if they belong to the same flow of traffic from the device. For multi-channel
392 * operation there are independent TX Queues for each channel.
393 */
394struct brcms_txq_info {
395 struct brcms_txq_info *next;
396 struct pktq q;
397 uint stopped; /* tx flow control bits */
398};
399
400/*
401 * Principal common driver data structure.
402 *
403 * pub: pointer to driver public state.
404 * wl: pointer to specific private state.
405 * regs: pointer to device registers.
406 * hw: HW related state.
407 * clkreq_override: setting for clkreq for PCIE : Auto, 0, 1.
408 * fastpwrup_dly: time in us needed to bring up d11 fast clock.
409 * macintstatus: bit channel between isr and dpc.
410 * macintmask: sw runtime master macintmask value.
411 * defmacintmask: default "on" macintmask value.
412 * clk: core is out of reset and has clock.
413 * core: pointer to active io core.
414 * band: pointer to active per-band state.
415 * corestate: per-core state (one per hw core).
416 * bandstate: per-band state (one per phy/radio).
417 * qvalid: DirFrmQValid and BcMcFrmQValid.
418 * ampdu: ampdu module handler.
419 * asi: antsel module handler.
420 * cmi: channel manager module handler.
421 * vendorid: PCI vendor id.
422 * deviceid: PCI device id.
423 * ucode_rev: microcode revision.
424 * machwcap: MAC capabilities, BMAC shadow.
425 * perm_etheraddr: original sprom local ethernet address.
426 * bandlocked: disable auto multi-band switching.
427 * bandinit_pending: track band init in auto band.
428 * radio_monitor: radio timer is running.
429 * going_down: down path intermediate variable.
430 * mpc: enable minimum power consumption.
431 * mpc_dlycnt: # of watchdog cnt before turn disable radio.
432 * mpc_offcnt: # of watchdog cnt that radio is disabled.
433 * mpc_delay_off: delay radio disable by # of watchdog cnt.
434 * prev_non_delay_mpc: prev state brcms_c_is_non_delay_mpc.
435 * wdtimer: timer for watchdog routine.
436 * radio_timer: timer for hw radio button monitor routine.
437 * monitor: monitor (MPDU sniffing) mode.
438 * bcnmisc_monitor: bcns promisc mode override for monitor.
439 * _rifs: enable per-packet rifs.
440 * bcn_li_bcn: beacon listen interval in # beacons.
441 * bcn_li_dtim: beacon listen interval in # dtims.
442 * WDarmed: watchdog timer is armed.
443 * WDlast: last time wlc_watchdog() was called.
444 * edcf_txop[AC_COUNT]: current txop for each ac.
445 * wme_retries: per-AC retry limits.
446 * tx_prec_map: Precedence map based on HW FIFO space.
447 * fifo2prec_map[NFIFO]: pointer to fifo2_prec map based on WME.
448 * bsscfg: set of BSS configurations, idx 0 is default and always valid.
449 * cfg: the primary bsscfg (can be AP or STA).
450 * tx_queues: common TX Queue list.
451 * modulecb:
452 * mimoft: SIGN or 11N.
453 * cck_40txbw: 11N, cck tx b/w override when in 40MHZ mode.
454 * ofdm_40txbw: 11N, ofdm tx b/w override when in 40MHZ mode.
455 * mimo_40txbw: 11N, mimo tx b/w override when in 40MHZ mode.
456 * default_bss: configured BSS parameters.
457 * mc_fid_counter: BC/MC FIFO frame ID counter.
458 * country_default: saved country for leaving 802.11d auto-country mode.
459 * autocountry_default: initial country for 802.11d auto-country mode.
460 * prb_resp_timeout: do not send prb resp if request older
461 * than this, 0 = disable.
462 * home_chanspec: shared home chanspec.
463 * chanspec: target operational channel.
464 * usr_fragthresh: user configured fragmentation threshold.
465 * fragthresh[NFIFO]: per-fifo fragmentation thresholds.
466 * RTSThresh: 802.11 dot11RTSThreshold.
467 * SRL: 802.11 dot11ShortRetryLimit.
468 * LRL: 802.11 dot11LongRetryLimit.
469 * SFBL: Short Frame Rate Fallback Limit.
470 * LFBL: Long Frame Rate Fallback Limit.
471 * shortslot: currently using 11g ShortSlot timing.
472 * shortslot_override: 11g ShortSlot override.
473 * include_legacy_erp: include Legacy ERP info elt ID 47 as well as g ID 42.
474 * PLCPHdr_override: 802.11b Preamble Type override.
475 * stf:
476 * bcn_rspec: save bcn ratespec purpose.
477 * tempsense_lasttime;
478 * tx_duty_cycle_ofdm: maximum allowed duty cycle for OFDM.
479 * tx_duty_cycle_cck: maximum allowed duty cycle for CCK.
480 * pkt_queue: txq for transmit packets.
481 * wiphy:
482 * pri_scb: primary Station Control Block
483 */
484struct brcms_c_info {
485 struct brcms_pub *pub;
486 struct brcms_info *wl;
487 struct d11regs __iomem *regs;
488 struct brcms_hardware *hw;
489
490 /* clock */
491 u16 fastpwrup_dly;
492
493 /* interrupt */
494 u32 macintstatus;
495 u32 macintmask;
496 u32 defmacintmask;
497
498 bool clk;
499
500 /* multiband */
501 struct brcms_core *core;
502 struct brcms_band *band;
503 struct brcms_core *corestate;
504 struct brcms_band *bandstate[MAXBANDS];
505
506 /* packet queue */
507 uint qvalid;
508
509 struct ampdu_info *ampdu;
510 struct antsel_info *asi;
511 struct brcms_cm_info *cmi;
512
513 u16 vendorid;
514 u16 deviceid;
515 uint ucode_rev;
516
517 u8 perm_etheraddr[ETH_ALEN];
518
519 bool bandlocked;
520 bool bandinit_pending;
521
522 bool radio_monitor;
523 bool going_down;
524
525 bool mpc;
526 u8 mpc_dlycnt;
527 u8 mpc_offcnt;
528 u8 mpc_delay_off;
529 u8 prev_non_delay_mpc;
530
531 struct brcms_timer *wdtimer;
532 struct brcms_timer *radio_timer;
533
534 /* promiscuous */
535 bool monitor;
536 bool bcnmisc_monitor;
537
538 /* driver feature */
539 bool _rifs;
540
541 /* AP-STA synchronization, power save */
542 u8 bcn_li_bcn;
543 u8 bcn_li_dtim;
544
545 bool WDarmed;
546 u32 WDlast;
547
548 /* WME */
549 u16 edcf_txop[AC_COUNT];
550
551 u16 wme_retries[AC_COUNT];
552 u16 tx_prec_map;
553 u16 fifo2prec_map[NFIFO];
554
555 struct brcms_bss_cfg *bsscfg;
556
557 /* tx queue */
558 struct brcms_txq_info *tx_queues;
559
560 struct modulecb *modulecb;
561
562 u8 mimoft;
563 s8 cck_40txbw;
564 s8 ofdm_40txbw;
565 s8 mimo_40txbw;
566
567 struct brcms_bss_info *default_bss;
568
569 u16 mc_fid_counter;
570
571 char country_default[BRCM_CNTRY_BUF_SZ];
572 char autocountry_default[BRCM_CNTRY_BUF_SZ];
573 u16 prb_resp_timeout;
574
575 u16 home_chanspec;
576
577 /* PHY parameters */
578 u16 chanspec;
579 u16 usr_fragthresh;
580 u16 fragthresh[NFIFO];
581 u16 RTSThresh;
582 u16 SRL;
583 u16 LRL;
584 u16 SFBL;
585 u16 LFBL;
586
587 /* network config */
588 bool shortslot;
589 s8 shortslot_override;
590 bool include_legacy_erp;
591
592 struct brcms_protection *protection;
593 s8 PLCPHdr_override;
594
595 struct brcms_stf *stf;
596
597 u32 bcn_rspec;
598
599 uint tempsense_lasttime;
600
601 u16 tx_duty_cycle_ofdm;
602 u16 tx_duty_cycle_cck;
603
604 struct brcms_txq_info *pkt_queue;
605 struct wiphy *wiphy;
606 struct scb pri_scb;
607};
608
609/* antsel module specific state */
610struct antsel_info {
611 struct brcms_c_info *wlc; /* pointer to main wlc structure */
612 struct brcms_pub *pub; /* pointer to public fn */
613 u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic
614 * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board
615 */
616 u8 antsel_antswitch; /* board level antenna switch type */
617 bool antsel_avail; /* Ant selection availability (SROM based) */
618 struct brcms_antselcfg antcfg_11n; /* antenna configuration */
619 struct brcms_antselcfg antcfg_cur; /* current antenna config (auto) */
620};
621
622/*
623 * BSS configuration state
624 *
625 * wlc: wlc to which this bsscfg belongs to.
626 * up: is this configuration up operational
627 * enable: is this configuration enabled
628 * associated: is BSS in ASSOCIATED state
629 * BSS: infraustructure or adhoc
630 * SSID_len: the length of SSID
631 * SSID: SSID string
632 *
633 *
634 * BSSID: BSSID (associated)
635 * cur_etheraddr: h/w address
636 * flags: BSSCFG flags; see below
637 *
638 * current_bss: BSS parms in ASSOCIATED state
639 *
640 *
641 * ID: 'unique' ID of this bsscfg, assigned at bsscfg allocation
642 */
643struct brcms_bss_cfg {
644 struct brcms_c_info *wlc;
645 bool up;
646 bool enable;
647 bool associated;
648 bool BSS;
649 u8 SSID_len;
650 u8 SSID[IEEE80211_MAX_SSID_LEN];
651 u8 BSSID[ETH_ALEN];
652 u8 cur_etheraddr[ETH_ALEN];
653 struct brcms_bss_info *current_bss;
654};
655
656extern void brcms_c_fatal_error(struct brcms_c_info *wlc);
657extern void brcms_b_rpc_watchdog(struct brcms_c_info *wlc);
658extern void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p);
659extern void brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo,
660 struct sk_buff *p,
661 bool commit, s8 txpktpend);
662extern void brcms_c_txfifo_complete(struct brcms_c_info *wlc, uint fifo,
663 s8 txpktpend);
664extern void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb,
665 struct sk_buff *sdu, uint prec);
666extern void brcms_c_info_init(struct brcms_c_info *wlc, int unit);
667extern void brcms_c_print_txstatus(struct tx_status *txs);
668extern int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
669 uint *blocks);
670
671#if defined(BCMDBG)
672extern void brcms_c_print_rxh(struct d11rxhdr *rxh);
673extern void brcms_c_print_txdesc(struct d11txh *txh);
674#else
675#define brcms_c_print_txdesc(a)
676#endif
677
678extern void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit);
679extern void brcms_c_coredisable(struct brcms_hardware *wlc_hw);
680
681extern bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rate,
682 int band, bool verbose);
683extern void brcms_c_ap_upd(struct brcms_c_info *wlc);
684
685/* helper functions */
686extern void brcms_c_shm_ssid_upd(struct brcms_c_info *wlc,
687 struct brcms_bss_cfg *cfg);
688extern int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config);
689
690extern void brcms_c_mac_bcn_promisc_change(struct brcms_c_info *wlc,
691 bool promisc);
692extern void brcms_c_mac_bcn_promisc(struct brcms_c_info *wlc);
693extern void brcms_c_mac_promisc(struct brcms_c_info *wlc);
694extern void brcms_c_txflowcontrol(struct brcms_c_info *wlc,
695 struct brcms_txq_info *qi,
696 bool on, int prio);
697extern void brcms_c_txflowcontrol_override(struct brcms_c_info *wlc,
698 struct brcms_txq_info *qi,
699 bool on, uint override);
700extern bool brcms_c_txflowcontrol_prio_isset(struct brcms_c_info *wlc,
701 struct brcms_txq_info *qi,
702 int prio);
703extern void brcms_c_send_q(struct brcms_c_info *wlc);
704extern int brcms_c_prep_pdu(struct brcms_c_info *wlc, struct sk_buff *pdu,
705 uint *fifo);
706
707extern u16 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
708 uint mac_len);
709extern u32 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc,
710 u32 rspec,
711 bool use_rspec, u16 mimo_ctlchbw);
712extern u16 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
713 u32 rts_rate,
714 u32 frame_rate,
715 u8 rts_preamble_type,
716 u8 frame_preamble_type, uint frame_len,
717 bool ba);
718
719extern void brcms_c_tbtt(struct brcms_c_info *wlc);
720extern void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
721 struct ieee80211_sta *sta,
722 void (*dma_callback_fn));
723
724/* Shared memory access */
725extern void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
726 const void *buf, int len);
727
728extern void brcms_c_update_beacon(struct brcms_c_info *wlc);
729
730extern void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend);
731extern void brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
732 struct brcms_bss_cfg *cfg,
733 bool suspend);
734extern bool brcms_c_ismpc(struct brcms_c_info *wlc);
735extern bool brcms_c_is_non_delay_mpc(struct brcms_c_info *wlc);
736extern void brcms_c_radio_mpc_upd(struct brcms_c_info *wlc);
737extern bool brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q,
738 struct sk_buff *pkt, int prec, bool head);
739extern u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec);
740extern void brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rate,
741 uint length, u8 *plcp);
742extern uint brcms_c_calc_frame_time(struct brcms_c_info *wlc,
743 u32 ratespec,
744 u8 preamble_type, uint mac_len);
745
746extern void brcms_c_set_chanspec(struct brcms_c_info *wlc,
747 u16 chanspec);
748
749extern bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit);
750
751extern int brcms_c_set_nmode(struct brcms_c_info *wlc);
752extern void brcms_c_mimops_action_ht_send(struct brcms_c_info *wlc,
753 struct brcms_bss_cfg *bsscfg,
754 u8 mimops_mode);
755
756extern void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot);
757extern void brcms_c_set_bssid(struct brcms_bss_cfg *cfg);
758extern void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend);
759
760extern void brcms_c_set_ratetable(struct brcms_c_info *wlc);
761extern int brcms_c_set_mac(struct brcms_bss_cfg *cfg);
762extern void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
763 u32 bcn_rate);
764extern void brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc,
765 uint frame_len);
766extern u32 brcms_c_lowest_basic_rspec(struct brcms_c_info *wlc,
767 struct brcms_c_rateset *rs);
768extern void brcms_c_radio_disable(struct brcms_c_info *wlc);
769extern void brcms_c_bcn_li_upd(struct brcms_c_info *wlc);
770extern void brcms_c_set_home_chanspec(struct brcms_c_info *wlc,
771 u16 chanspec);
772extern bool brcms_c_ps_allowed(struct brcms_c_info *wlc);
773extern bool brcms_c_stay_awake(struct brcms_c_info *wlc);
774
775extern void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw,
776 u8 antsel_type);
777
778/* chanspec, ucode interface */
779extern void brcms_b_set_chanspec(struct brcms_hardware *wlc_hw,
780 u16 chanspec,
781 bool mute, struct txpwr_limits *txpwr);
782
783extern void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset,
784 u16 v);
785extern u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset);
786
787extern void brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask,
788 u16 val, int bands);
789
790extern void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags);
791
792extern void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val);
793
794extern void brcms_b_phy_reset(struct brcms_hardware *wlc_hw);
795extern void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw);
796extern void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw);
797extern void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
798 u32 override_bit);
799extern void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
800 u32 override_bit);
801extern void brcms_b_write_template_ram(struct brcms_hardware *wlc_hw,
802 int offset, int len, void *buf);
803extern u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate);
804extern void brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw,
805 uint offset, const void *buf, int len,
806 u32 sel);
807extern void brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset,
808 void *buf, int len, u32 sel);
809extern void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode);
810extern u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw);
811extern void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk);
812extern void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk);
813extern void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on);
814extern void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant);
815extern void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw,
816 u8 stf_mode);
817extern void brcms_c_init_scb(struct scb *scb);
818
819#endif /* _BRCM_MAIN_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/nicpci.c b/drivers/staging/brcm80211/brcmsmac/nicpci.c
deleted file mode 100644
index 0bcb2679204..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/nicpci.c
+++ /dev/null
@@ -1,835 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/pci.h>
20
21#include <defs.h>
22#include <soc.h>
23#include <chipcommon.h>
24#include "aiutils.h"
25#include "pub.h"
26#include "nicpci.h"
27
28/* SPROM offsets */
29#define SRSH_ASPM_OFFSET 4 /* word 4 */
30#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
31#define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */
32#define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */
33
34#define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */
35#define SRSH_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
36#define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
37#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
38#define SRSH_BD_OFFSET 6 /* word 6 */
39
40/* chipcontrol */
41#define CHIPCTRL_4321_PLL_DOWN 0x800000/* serdes PLL down override */
42
43/* MDIO control */
44#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
45#define MDIOCTL_DIVISOR_VAL 0x2
46#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
47#define MDIOCTL_ACCESS_DONE 0x100 /* Transaction complete */
48
49/* MDIO Data */
50#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
51#define MDIODATA_TA 0x00020000 /* Turnaround */
52
53#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
54#define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
55#define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
56#define MDIODATA_DEVADDR_MASK 0x0f800000
57 /* Physmedia devaddr Mask */
58
59/* MDIO Data for older revisions < 10 */
60#define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift */
61#define MDIODATA_REGADDR_MASK_OLD 0x003c0000
62 /* Regaddr Mask */
63#define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift */
64#define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000
65 /* Physmedia devaddr Mask */
66
67/* Transactions flags */
68#define MDIODATA_WRITE 0x10000000
69#define MDIODATA_READ 0x20000000
70#define MDIODATA_START 0x40000000
71
72#define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
73#define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
74
75/* serdes regs (rev < 10) */
76#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
77#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
78#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
79
80/* SERDES RX registers */
81#define SERDES_RX_CTRL 1 /* Rx cntrl */
82#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
83#define SERDES_RX_CDR 6 /* CDR */
84#define SERDES_RX_CDRBW 7 /* CDR BW */
85/* SERDES RX control register */
86#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
87#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
88
89/* SERDES PLL registers */
90#define SERDES_PLL_CTRL 1 /* PLL control reg */
91#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
92
93/* Linkcontrol reg offset in PCIE Cap */
94#define PCIE_CAP_LINKCTRL_OFFSET 16 /* offset in pcie cap */
95#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
96#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
97#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
98
99#define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */
100#define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */
101#define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */
102#define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */
103
104/* Power management threshold */
105#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
106#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
107#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
108#define PCIE_ASPMTIMER_EXTEND 0x01000000
109 /* > rev7:
110 * enable extend ASPM timer
111 */
112
113/* different register spaces to access thru pcie indirect access */
114#define PCIE_CONFIGREGS 1 /* Access to config space */
115#define PCIE_PCIEREGS 2 /* Access to pcie registers */
116
117/* PCIE protocol PHY diagnostic registers */
118#define PCIE_PLP_STATUSREG 0x204 /* Status */
119
120/* Status reg PCIE_PLP_STATUSREG */
121#define PCIE_PLP_POLARITYINV_STAT 0x10
122
123/* PCIE protocol DLLP diagnostic registers */
124#define PCIE_DLLP_LCREG 0x100 /* Link Control */
125#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
126
127/* PCIE protocol TLP diagnostic registers */
128#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
129
130/* Sonics to PCI translation types */
131#define SBTOPCI_PREF 0x4 /* prefetch enable */
132#define SBTOPCI_BURST 0x8 /* burst enable */
133#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
134
135#define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */
136
137/* PCI core index in SROM shadow area */
138#define SRSH_PI_OFFSET 0 /* first word */
139#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
140#define SRSH_PI_SHIFT 12 /* bit 15:12 */
141
142/* Sonics side: PCI core and host control registers */
143struct sbpciregs {
144 u32 control; /* PCI control */
145 u32 PAD[3];
146 u32 arbcontrol; /* PCI arbiter control */
147 u32 clkrun; /* Clkrun Control (>=rev11) */
148 u32 PAD[2];
149 u32 intstatus; /* Interrupt status */
150 u32 intmask; /* Interrupt mask */
151 u32 sbtopcimailbox; /* Sonics to PCI mailbox */
152 u32 PAD[9];
153 u32 bcastaddr; /* Sonics broadcast address */
154 u32 bcastdata; /* Sonics broadcast data */
155 u32 PAD[2];
156 u32 gpioin; /* ro: gpio input (>=rev2) */
157 u32 gpioout; /* rw: gpio output (>=rev2) */
158 u32 gpioouten; /* rw: gpio output enable (>= rev2) */
159 u32 gpiocontrol; /* rw: gpio control (>= rev2) */
160 u32 PAD[36];
161 u32 sbtopci0; /* Sonics to PCI translation 0 */
162 u32 sbtopci1; /* Sonics to PCI translation 1 */
163 u32 sbtopci2; /* Sonics to PCI translation 2 */
164 u32 PAD[189];
165 u32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
166 u16 sprom[36]; /* SPROM shadow Area */
167 u32 PAD[46];
168};
169
170/* SB side: PCIE core and host control registers */
171struct sbpcieregs {
172 u32 control; /* host mode only */
173 u32 PAD[2];
174 u32 biststatus; /* bist Status: 0x00C */
175 u32 gpiosel; /* PCIE gpio sel: 0x010 */
176 u32 gpioouten; /* PCIE gpio outen: 0x14 */
177 u32 PAD[2];
178 u32 intstatus; /* Interrupt status: 0x20 */
179 u32 intmask; /* Interrupt mask: 0x24 */
180 u32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
181 u32 PAD[53];
182 u32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
183 u32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
184 u32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
185 u32 PAD[5];
186
187 /* pcie core supports in direct access to config space */
188 u32 configaddr; /* pcie config space access: Address field: 0x120 */
189 u32 configdata; /* pcie config space access: Data field: 0x124 */
190
191 /* mdio access to serdes */
192 u32 mdiocontrol; /* controls the mdio access: 0x128 */
193 u32 mdiodata; /* Data to the mdio access: 0x12c */
194
195 /* pcie protocol phy/dllp/tlp register indirect access mechanism */
196 u32 pcieindaddr; /* indirect access to
197 * the internal register: 0x130
198 */
199 u32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
200
201 u32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
202 u32 PAD[177];
203 u32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */
204 u16 sprom[64]; /* SPROM shadow Area */
205};
206
207struct pcicore_info {
208 union {
209 struct sbpcieregs __iomem *pcieregs;
210 struct sbpciregs __iomem *pciregs;
211 } regs; /* Memory mapped register to the core */
212
213 struct si_pub *sih; /* System interconnect handle */
214 struct pci_dev *dev;
215 u8 pciecap_lcreg_offset;/* PCIE capability LCreg offset
216 * in the config space
217 */
218 bool pcie_pr42767;
219 u8 pcie_polarity;
220 u8 pcie_war_aspm_ovr; /* Override ASPM/Clkreq settings */
221
222 u8 pmecap_offset; /* PM Capability offset in the config space */
223 bool pmecap; /* Capable of generating PME */
224};
225
226#define PCIE_ASPM(sih) \
227 (((sih)->buscoretype == PCIE_CORE_ID) && \
228 (((sih)->buscorerev >= 3) && \
229 ((sih)->buscorerev <= 5)))
230
231
232/* delay needed between the mdio control/ mdiodata register data access */
233static void pr28829_delay(void)
234{
235 udelay(10);
236}
237
238/* Initialize the PCI core.
239 * It's caller's responsibility to make sure that this is done only once
240 */
241struct pcicore_info *pcicore_init(struct si_pub *sih, struct pci_dev *pdev,
242 void __iomem *regs)
243{
244 struct pcicore_info *pi;
245
246 /* alloc struct pcicore_info */
247 pi = kzalloc(sizeof(struct pcicore_info), GFP_ATOMIC);
248 if (pi == NULL)
249 return NULL;
250
251 pi->sih = sih;
252 pi->dev = pdev;
253
254 if (sih->buscoretype == PCIE_CORE_ID) {
255 u8 cap_ptr;
256 pi->regs.pcieregs = regs;
257 cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
258 NULL, NULL);
259 pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
260 } else
261 pi->regs.pciregs = regs;
262
263 return pi;
264}
265
266void pcicore_deinit(struct pcicore_info *pch)
267{
268 kfree(pch);
269}
270
271/* return cap_offset if requested capability exists in the PCI config space */
272/* Note that it's caller's responsibility to make sure it's a pci bus */
273u8
274pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
275 unsigned char *buf, u32 *buflen)
276{
277 u8 cap_id;
278 u8 cap_ptr = 0;
279 u32 bufsize;
280 u8 byte_val;
281
282 /* check for Header type 0 */
283 pci_read_config_byte(dev, PCI_HEADER_TYPE, &byte_val);
284 if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
285 goto end;
286
287 /* check if the capability pointer field exists */
288 pci_read_config_byte(dev, PCI_STATUS, &byte_val);
289 if (!(byte_val & PCI_STATUS_CAP_LIST))
290 goto end;
291
292 pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &cap_ptr);
293 /* check if the capability pointer is 0x00 */
294 if (cap_ptr == 0x00)
295 goto end;
296
297 /* loop thru the capability list
298 * and see if the pcie capability exists
299 */
300
301 pci_read_config_byte(dev, cap_ptr, &cap_id);
302
303 while (cap_id != req_cap_id) {
304 pci_read_config_byte(dev, cap_ptr + 1, &cap_ptr);
305 if (cap_ptr == 0x00)
306 break;
307 pci_read_config_byte(dev, cap_ptr, &cap_id);
308 }
309 if (cap_id != req_cap_id)
310 goto end;
311
312 /* found the caller requested capability */
313 if (buf != NULL && buflen != NULL) {
314 u8 cap_data;
315
316 bufsize = *buflen;
317 if (!bufsize)
318 goto end;
319 *buflen = 0;
320 /* copy the capability data excluding cap ID and next ptr */
321 cap_data = cap_ptr + 2;
322 if ((bufsize + cap_data) > PCI_SZPCR)
323 bufsize = PCI_SZPCR - cap_data;
324 *buflen = bufsize;
325 while (bufsize--) {
326 pci_read_config_byte(dev, cap_data, buf);
327 cap_data++;
328 buf++;
329 }
330 }
331end:
332 return cap_ptr;
333}
334
335/* ***** Register Access API */
336static uint
337pcie_readreg(struct sbpcieregs __iomem *pcieregs, uint addrtype, uint offset)
338{
339 uint retval = 0xFFFFFFFF;
340
341 switch (addrtype) {
342 case PCIE_CONFIGREGS:
343 W_REG(&pcieregs->configaddr, offset);
344 (void)R_REG((&pcieregs->configaddr));
345 retval = R_REG(&pcieregs->configdata);
346 break;
347 case PCIE_PCIEREGS:
348 W_REG(&pcieregs->pcieindaddr, offset);
349 (void)R_REG(&pcieregs->pcieindaddr);
350 retval = R_REG(&pcieregs->pcieinddata);
351 break;
352 }
353
354 return retval;
355}
356
357static uint pcie_writereg(struct sbpcieregs __iomem *pcieregs, uint addrtype,
358 uint offset, uint val)
359{
360 switch (addrtype) {
361 case PCIE_CONFIGREGS:
362 W_REG((&pcieregs->configaddr), offset);
363 W_REG((&pcieregs->configdata), val);
364 break;
365 case PCIE_PCIEREGS:
366 W_REG((&pcieregs->pcieindaddr), offset);
367 W_REG((&pcieregs->pcieinddata), val);
368 break;
369 default:
370 break;
371 }
372 return 0;
373}
374
375static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk)
376{
377 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
378 uint mdiodata, i = 0;
379 uint pcie_serdes_spinwait = 200;
380
381 mdiodata = (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
382 (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
383 (MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) |
384 (blk << 4));
385 W_REG(&pcieregs->mdiodata, mdiodata);
386
387 pr28829_delay();
388 /* retry till the transaction is complete */
389 while (i < pcie_serdes_spinwait) {
390 if (R_REG(&pcieregs->mdiocontrol) & MDIOCTL_ACCESS_DONE)
391 break;
392
393 udelay(1000);
394 i++;
395 }
396
397 if (i >= pcie_serdes_spinwait)
398 return false;
399
400 return true;
401}
402
403static int
404pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
405 uint *val)
406{
407 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
408 uint mdiodata;
409 uint i = 0;
410 uint pcie_serdes_spinwait = 10;
411
412 /* enable mdio access to SERDES */
413 W_REG(&pcieregs->mdiocontrol, MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
414
415 if (pi->sih->buscorerev >= 10) {
416 /* new serdes is slower in rw,
417 * using two layers of reg address mapping
418 */
419 if (!pcie_mdiosetblock(pi, physmedia))
420 return 1;
421 mdiodata = ((MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
422 (regaddr << MDIODATA_REGADDR_SHF));
423 pcie_serdes_spinwait *= 20;
424 } else {
425 mdiodata = ((physmedia << MDIODATA_DEVADDR_SHF_OLD) |
426 (regaddr << MDIODATA_REGADDR_SHF_OLD));
427 }
428
429 if (!write)
430 mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
431 else
432 mdiodata |= (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
433 *val);
434
435 W_REG(&pcieregs->mdiodata, mdiodata);
436
437 pr28829_delay();
438
439 /* retry till the transaction is complete */
440 while (i < pcie_serdes_spinwait) {
441 if (R_REG(&pcieregs->mdiocontrol) & MDIOCTL_ACCESS_DONE) {
442 if (!write) {
443 pr28829_delay();
444 *val = (R_REG(&pcieregs->mdiodata) &
445 MDIODATA_MASK);
446 }
447 /* Disable mdio access to SERDES */
448 W_REG(&pcieregs->mdiocontrol, 0);
449 return 0;
450 }
451 udelay(1000);
452 i++;
453 }
454
455 /* Timed out. Disable mdio access to SERDES. */
456 W_REG(&pcieregs->mdiocontrol, 0);
457 return 1;
458}
459
460/* use the mdio interface to read from mdio slaves */
461static int
462pcie_mdioread(struct pcicore_info *pi, uint physmedia, uint regaddr,
463 uint *regval)
464{
465 return pcie_mdioop(pi, physmedia, regaddr, false, regval);
466}
467
468/* use the mdio interface to write to mdio slaves */
469static int
470pcie_mdiowrite(struct pcicore_info *pi, uint physmedia, uint regaddr, uint val)
471{
472 return pcie_mdioop(pi, physmedia, regaddr, true, &val);
473}
474
475/* ***** Support functions ***** */
476static u8 pcie_clkreq(struct pcicore_info *pi, u32 mask, u32 val)
477{
478 u32 reg_val;
479 u8 offset;
480
481 offset = pi->pciecap_lcreg_offset;
482 if (!offset)
483 return 0;
484
485 pci_read_config_dword(pi->dev, offset, &reg_val);
486 /* set operation */
487 if (mask) {
488 if (val)
489 reg_val |= PCIE_CLKREQ_ENAB;
490 else
491 reg_val &= ~PCIE_CLKREQ_ENAB;
492 pci_write_config_dword(pi->dev, offset, reg_val);
493 pci_read_config_dword(pi->dev, offset, &reg_val);
494 }
495 if (reg_val & PCIE_CLKREQ_ENAB)
496 return 1;
497 else
498 return 0;
499}
500
501static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
502{
503 u32 w;
504 struct si_pub *sih = pi->sih;
505 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
506
507 if (sih->buscoretype != PCIE_CORE_ID || sih->buscorerev < 7)
508 return;
509
510 w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
511 if (extend)
512 w |= PCIE_ASPMTIMER_EXTEND;
513 else
514 w &= ~PCIE_ASPMTIMER_EXTEND;
515 pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
516 w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
517}
518
519/* centralized clkreq control policy */
520static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
521{
522 struct si_pub *sih = pi->sih;
523
524 switch (state) {
525 case SI_DOATTACH:
526 if (PCIE_ASPM(sih))
527 pcie_clkreq(pi, 1, 0);
528 break;
529 case SI_PCIDOWN:
530 if (sih->buscorerev == 6) { /* turn on serdes PLL down */
531 ai_corereg(sih, SI_CC_IDX,
532 offsetof(struct chipcregs, chipcontrol_addr),
533 ~0, 0);
534 ai_corereg(sih, SI_CC_IDX,
535 offsetof(struct chipcregs, chipcontrol_data),
536 ~0x40, 0);
537 } else if (pi->pcie_pr42767) {
538 pcie_clkreq(pi, 1, 1);
539 }
540 break;
541 case SI_PCIUP:
542 if (sih->buscorerev == 6) { /* turn off serdes PLL down */
543 ai_corereg(sih, SI_CC_IDX,
544 offsetof(struct chipcregs, chipcontrol_addr),
545 ~0, 0);
546 ai_corereg(sih, SI_CC_IDX,
547 offsetof(struct chipcregs, chipcontrol_data),
548 ~0x40, 0x40);
549 } else if (PCIE_ASPM(sih)) { /* disable clkreq */
550 pcie_clkreq(pi, 1, 0);
551 }
552 break;
553 }
554}
555
556/* ***** PCI core WARs ***** */
557/* Done only once at attach time */
558static void pcie_war_polarity(struct pcicore_info *pi)
559{
560 u32 w;
561
562 if (pi->pcie_polarity != 0)
563 return;
564
565 w = pcie_readreg(pi->regs.pcieregs, PCIE_PCIEREGS, PCIE_PLP_STATUSREG);
566
567 /* Detect the current polarity at attach and force that polarity and
568 * disable changing the polarity
569 */
570 if ((w & PCIE_PLP_POLARITYINV_STAT) == 0)
571 pi->pcie_polarity = SERDES_RX_CTRL_FORCE;
572 else
573 pi->pcie_polarity = (SERDES_RX_CTRL_FORCE |
574 SERDES_RX_CTRL_POLARITY);
575}
576
577/* enable ASPM and CLKREQ if srom doesn't have it */
578/* Needs to happen when update to shadow SROM is needed
579 * : Coming out of 'standby'/'hibernate'
580 * : If pcie_war_aspm_ovr state changed
581 */
582static void pcie_war_aspm_clkreq(struct pcicore_info *pi)
583{
584 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
585 struct si_pub *sih = pi->sih;
586 u16 val16;
587 u16 __iomem *reg16;
588 u32 w;
589
590 if (!PCIE_ASPM(sih))
591 return;
592
593 /* bypass this on QT or VSIM */
594 reg16 = &pcieregs->sprom[SRSH_ASPM_OFFSET];
595 val16 = R_REG(reg16);
596
597 val16 &= ~SRSH_ASPM_ENB;
598 if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB)
599 val16 |= SRSH_ASPM_ENB;
600 else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L1_ENAB)
601 val16 |= SRSH_ASPM_L1_ENB;
602 else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB)
603 val16 |= SRSH_ASPM_L0s_ENB;
604
605 W_REG(reg16, val16);
606
607 pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
608 w &= ~PCIE_ASPM_ENAB;
609 w |= pi->pcie_war_aspm_ovr;
610 pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
611
612 reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
613 val16 = R_REG(reg16);
614
615 if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) {
616 val16 |= SRSH_CLKREQ_ENB;
617 pi->pcie_pr42767 = true;
618 } else
619 val16 &= ~SRSH_CLKREQ_ENB;
620
621 W_REG(reg16, val16);
622}
623
624/* Apply the polarity determined at the start */
625/* Needs to happen when coming out of 'standby'/'hibernate' */
626static void pcie_war_serdes(struct pcicore_info *pi)
627{
628 u32 w = 0;
629
630 if (pi->pcie_polarity != 0)
631 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
632 pi->pcie_polarity);
633
634 pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
635 if (w & PLL_CTRL_FREQDET_EN) {
636 w &= ~PLL_CTRL_FREQDET_EN;
637 pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
638 }
639}
640
641/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
642/* Needs to happen when coming out of 'standby'/'hibernate' */
643static void pcie_misc_config_fixup(struct pcicore_info *pi)
644{
645 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
646 u16 val16;
647 u16 __iomem *reg16;
648
649 reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG];
650 val16 = R_REG(reg16);
651
652 if ((val16 & SRSH_L23READY_EXIT_NOPERST) == 0) {
653 val16 |= SRSH_L23READY_EXIT_NOPERST;
654 W_REG(reg16, val16);
655 }
656}
657
658/* quick hack for testing */
659/* Needs to happen when coming out of 'standby'/'hibernate' */
660static void pcie_war_noplldown(struct pcicore_info *pi)
661{
662 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
663 u16 __iomem *reg16;
664
665 /* turn off serdes PLL down */
666 ai_corereg(pi->sih, SI_CC_IDX, offsetof(struct chipcregs, chipcontrol),
667 CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
668
669 /* clear srom shadow backdoor */
670 reg16 = &pcieregs->sprom[SRSH_BD_OFFSET];
671 W_REG(reg16, 0);
672}
673
674/* Needs to happen when coming out of 'standby'/'hibernate' */
675static void pcie_war_pci_setup(struct pcicore_info *pi)
676{
677 struct si_pub *sih = pi->sih;
678 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
679 u32 w;
680
681 if (sih->buscorerev == 0 || sih->buscorerev == 1) {
682 w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
683 PCIE_TLP_WORKAROUNDSREG);
684 w |= 0x8;
685 pcie_writereg(pcieregs, PCIE_PCIEREGS,
686 PCIE_TLP_WORKAROUNDSREG, w);
687 }
688
689 if (sih->buscorerev == 1) {
690 w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
691 w |= 0x40;
692 pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
693 }
694
695 if (sih->buscorerev == 0) {
696 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
697 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
698 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
699 } else if (PCIE_ASPM(sih)) {
700 /* Change the L1 threshold for better performance */
701 w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
702 PCIE_DLLP_PMTHRESHREG);
703 w &= ~PCIE_L1THRESHOLDTIME_MASK;
704 w |= PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT;
705 pcie_writereg(pcieregs, PCIE_PCIEREGS,
706 PCIE_DLLP_PMTHRESHREG, w);
707
708 pcie_war_serdes(pi);
709
710 pcie_war_aspm_clkreq(pi);
711 } else if (pi->sih->buscorerev == 7)
712 pcie_war_noplldown(pi);
713
714 /* Note that the fix is actually in the SROM,
715 * that's why this is open-ended
716 */
717 if (pi->sih->buscorerev >= 6)
718 pcie_misc_config_fixup(pi);
719}
720
721/* ***** Functions called during driver state changes ***** */
722void pcicore_attach(struct pcicore_info *pi, int state)
723{
724 struct si_pub *sih = pi->sih;
725 u32 bfl2 = (u32)getintvar(sih, BRCMS_SROM_BOARDFLAGS2);
726
727 /* Determine if this board needs override */
728 if (PCIE_ASPM(sih)) {
729 if (bfl2 & BFL2_PCIEWAR_OVR)
730 pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
731 else
732 pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
733 }
734
735 /* These need to happen in this order only */
736 pcie_war_polarity(pi);
737
738 pcie_war_serdes(pi);
739
740 pcie_war_aspm_clkreq(pi);
741
742 pcie_clkreq_upd(pi, state);
743
744}
745
746void pcicore_hwup(struct pcicore_info *pi)
747{
748 if (!pi || pi->sih->buscoretype != PCIE_CORE_ID)
749 return;
750
751 pcie_war_pci_setup(pi);
752}
753
754void pcicore_up(struct pcicore_info *pi, int state)
755{
756 if (!pi || pi->sih->buscoretype != PCIE_CORE_ID)
757 return;
758
759 /* Restore L1 timer for better performance */
760 pcie_extendL1timer(pi, true);
761
762 pcie_clkreq_upd(pi, state);
763}
764
765/* When the device is going to enter D3 state
766 * (or the system is going to enter S3/S4 states)
767 */
768void pcicore_sleep(struct pcicore_info *pi)
769{
770 u32 w;
771
772 if (!pi || !PCIE_ASPM(pi->sih))
773 return;
774
775 pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
776 w &= ~PCIE_CAP_LCREG_ASPML1;
777 pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
778
779 pi->pcie_pr42767 = false;
780}
781
782void pcicore_down(struct pcicore_info *pi, int state)
783{
784 if (!pi || pi->sih->buscoretype != PCIE_CORE_ID)
785 return;
786
787 pcie_clkreq_upd(pi, state);
788
789 /* Reduce L1 timer for better power savings */
790 pcie_extendL1timer(pi, false);
791}
792
793/* precondition: current core is sii->buscoretype */
794static void pcicore_fixcfg(struct pcicore_info *pi, u16 __iomem *reg16)
795{
796 struct si_info *sii = (struct si_info *)(pi->sih);
797 u16 val16;
798 uint pciidx;
799
800 pciidx = ai_coreidx(&sii->pub);
801 val16 = R_REG(reg16);
802 if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16)pciidx) {
803 val16 = (u16)(pciidx << SRSH_PI_SHIFT) |
804 (val16 & ~SRSH_PI_MASK);
805 W_REG(reg16, val16);
806 }
807}
808
809void
810pcicore_fixcfg_pci(struct pcicore_info *pi, struct sbpciregs __iomem *pciregs)
811{
812 pcicore_fixcfg(pi, &pciregs->sprom[SRSH_PI_OFFSET]);
813}
814
815void pcicore_fixcfg_pcie(struct pcicore_info *pi,
816 struct sbpcieregs __iomem *pcieregs)
817{
818 pcicore_fixcfg(pi, &pcieregs->sprom[SRSH_PI_OFFSET]);
819}
820
821/* precondition: current core is pci core */
822void
823pcicore_pci_setup(struct pcicore_info *pi, struct sbpciregs __iomem *pciregs)
824{
825 u32 w;
826
827 OR_REG(&pciregs->sbtopci2, SBTOPCI_PREF | SBTOPCI_BURST);
828
829 if (((struct si_info *)(pi->sih))->pub.buscorerev >= 11) {
830 OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
831 w = R_REG(&pciregs->clkrun);
832 W_REG(&pciregs->clkrun, w | PCI_CLKRUN_DSBL);
833 w = R_REG(&pciregs->clkrun);
834 }
835}
diff --git a/drivers/staging/brcm80211/brcmsmac/nicpci.h b/drivers/staging/brcm80211/brcmsmac/nicpci.h
deleted file mode 100644
index 58aa80dc332..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/nicpci.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_NICPCI_H_
18#define _BRCM_NICPCI_H_
19
20#include "types.h"
21
22/* PCI configuration address space size */
23#define PCI_SZPCR 256
24
25/* Brcm PCI configuration registers */
26/* backplane address space accessed by BAR0 */
27#define PCI_BAR0_WIN 0x80
28/* sprom property control */
29#define PCI_SPROM_CONTROL 0x88
30/* mask of PCI and other cores interrupts */
31#define PCI_INT_MASK 0x94
32/* backplane core interrupt mask bits offset */
33#define PCI_SBIM_SHIFT 8
34/* backplane address space accessed by second 4KB of BAR0 */
35#define PCI_BAR0_WIN2 0xac
36/* pci config space gpio input (>=rev3) */
37#define PCI_GPIO_IN 0xb0
38/* pci config space gpio output (>=rev3) */
39#define PCI_GPIO_OUT 0xb4
40/* pci config space gpio output enable (>=rev3) */
41#define PCI_GPIO_OUTEN 0xb8
42
43/* bar0 + 4K accesses external sprom */
44#define PCI_BAR0_SPROM_OFFSET (4 * 1024)
45/* bar0 + 6K accesses pci core registers */
46#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)
47/*
48 * pci core SB registers are at the end of the
49 * 8KB window, so their address is the "regular"
50 * address plus 4K
51 */
52#define PCI_BAR0_PCISBR_OFFSET (4 * 1024)
53/* bar0 window size Match with corerev 13 */
54#define PCI_BAR0_WINSZ (16 * 1024)
55/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
56/* bar0 + 8K accesses pci/pcie core registers */
57#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
58/* bar0 + 12K accesses chipc core registers */
59#define PCI_16KB0_CCREGS_OFFSET (12 * 1024)
60
61struct sbpciregs;
62struct sbpcieregs;
63
64extern struct pcicore_info *pcicore_init(struct si_pub *sih,
65 struct pci_dev *pdev,
66 void __iomem *regs);
67extern void pcicore_deinit(struct pcicore_info *pch);
68extern void pcicore_attach(struct pcicore_info *pch, int state);
69extern void pcicore_hwup(struct pcicore_info *pch);
70extern void pcicore_up(struct pcicore_info *pch, int state);
71extern void pcicore_sleep(struct pcicore_info *pch);
72extern void pcicore_down(struct pcicore_info *pch, int state);
73extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
74 unsigned char *buf, u32 *buflen);
75extern void pcicore_fixcfg_pci(struct pcicore_info *pch,
76 struct sbpciregs __iomem *pciregs);
77extern void pcicore_fixcfg_pcie(struct pcicore_info *pch,
78 struct sbpcieregs __iomem *pciregs);
79extern void pcicore_pci_setup(struct pcicore_info *pch,
80 struct sbpciregs __iomem *pciregs);
81
82#endif /* _BRCM_NICPCI_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/otp.c b/drivers/staging/brcm80211/brcmsmac/otp.c
deleted file mode 100644
index edf551561fd..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/otp.c
+++ /dev/null
@@ -1,426 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <linux/errno.h>
19#include <linux/string.h>
20
21#include <brcm_hw_ids.h>
22#include <chipcommon.h>
23#include "aiutils.h"
24#include "otp.h"
25
26#define OTPS_GUP_MASK 0x00000f00
27#define OTPS_GUP_SHIFT 8
28/* h/w subregion is programmed */
29#define OTPS_GUP_HW 0x00000100
30/* s/w subregion is programmed */
31#define OTPS_GUP_SW 0x00000200
32/* chipid/pkgopt subregion is programmed */
33#define OTPS_GUP_CI 0x00000400
34/* fuse subregion is programmed */
35#define OTPS_GUP_FUSE 0x00000800
36
37/* Fields in otpprog in rev >= 21 */
38#define OTPP_COL_MASK 0x000000ff
39#define OTPP_COL_SHIFT 0
40#define OTPP_ROW_MASK 0x0000ff00
41#define OTPP_ROW_SHIFT 8
42#define OTPP_OC_MASK 0x0f000000
43#define OTPP_OC_SHIFT 24
44#define OTPP_READERR 0x10000000
45#define OTPP_VALUE_MASK 0x20000000
46#define OTPP_VALUE_SHIFT 29
47#define OTPP_START_BUSY 0x80000000
48#define OTPP_READ 0x40000000
49
50/* Opcodes for OTPP_OC field */
51#define OTPPOC_READ 0
52#define OTPPOC_BIT_PROG 1
53#define OTPPOC_VERIFY 3
54#define OTPPOC_INIT 4
55#define OTPPOC_SET 5
56#define OTPPOC_RESET 6
57#define OTPPOC_OCST 7
58#define OTPPOC_ROW_LOCK 8
59#define OTPPOC_PRESCN_TEST 9
60
61#define OTPTYPE_IPX(ccrev) ((ccrev) == 21 || (ccrev) >= 23)
62
63#define OTPP_TRIES 10000000 /* # of tries for OTPP */
64
65#define MAXNUMRDES 9 /* Maximum OTP redundancy entries */
66
67/* Fixed size subregions sizes in words */
68#define OTPGU_CI_SZ 2
69
70struct otpinfo;
71
72/* OTP function struct */
73struct otp_fn_s {
74 int (*init)(struct si_pub *sih, struct otpinfo *oi);
75 int (*read_region)(struct otpinfo *oi, int region, u16 *data,
76 uint *wlen);
77};
78
79struct otpinfo {
80 uint ccrev; /* chipc revision */
81 const struct otp_fn_s *fn; /* OTP functions */
82 struct si_pub *sih; /* Saved sb handle */
83
84 /* IPX OTP section */
85 u16 wsize; /* Size of otp in words */
86 u16 rows; /* Geometry */
87 u16 cols; /* Geometry */
88 u32 status; /* Flag bits (lock/prog/rv).
89 * (Reflected only when OTP is power cycled)
90 */
91 u16 hwbase; /* hardware subregion offset */
92 u16 hwlim; /* hardware subregion boundary */
93 u16 swbase; /* software subregion offset */
94 u16 swlim; /* software subregion boundary */
95 u16 fbase; /* fuse subregion offset */
96 u16 flim; /* fuse subregion boundary */
97 int otpgu_base; /* offset to General Use Region */
98};
99
100/* OTP layout */
101/* CC revs 21, 24 and 27 OTP General Use Region word offset */
102#define REVA4_OTPGU_BASE 12
103
104/* CC revs 23, 25, 26, 28 and above OTP General Use Region word offset */
105#define REVB8_OTPGU_BASE 20
106
107/* CC rev 36 OTP General Use Region word offset */
108#define REV36_OTPGU_BASE 12
109
110/* Subregion word offsets in General Use region */
111#define OTPGU_HSB_OFF 0
112#define OTPGU_SFB_OFF 1
113#define OTPGU_CI_OFF 2
114#define OTPGU_P_OFF 3
115#define OTPGU_SROM_OFF 4
116
117/* Flag bit offsets in General Use region */
118#define OTPGU_HWP_OFF 60
119#define OTPGU_SWP_OFF 61
120#define OTPGU_CIP_OFF 62
121#define OTPGU_FUSEP_OFF 63
122#define OTPGU_CIP_MSK 0x4000
123#define OTPGU_P_MSK 0xf000
124#define OTPGU_P_SHIFT (OTPGU_HWP_OFF % 16)
125
126/* OTP Size */
127#define OTP_SZ_FU_324 ((roundup(324, 8))/8) /* 324 bits */
128#define OTP_SZ_FU_288 (288/8) /* 288 bits */
129#define OTP_SZ_FU_216 (216/8) /* 216 bits */
130#define OTP_SZ_FU_72 (72/8) /* 72 bits */
131#define OTP_SZ_CHECKSUM (16/8) /* 16 bits */
132#define OTP4315_SWREG_SZ 178 /* 178 bytes */
133#define OTP_SZ_FU_144 (144/8) /* 144 bits */
134
135static u16
136ipxotp_otpr(struct otpinfo *oi, struct chipcregs __iomem *cc, uint wn)
137{
138 return R_REG(&cc->sromotp[wn]);
139}
140
141/*
142 * Calculate max HW/SW region byte size by subtracting fuse region
143 * and checksum size, osizew is oi->wsize (OTP size - GU size) in words
144 */
145static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
146{
147 int ret = 0;
148
149 switch (sih->chip) {
150 case BCM43224_CHIP_ID:
151 case BCM43225_CHIP_ID:
152 ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
153 break;
154 case BCM4313_CHIP_ID:
155 ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
156 break;
157 default:
158 break; /* Don't know about this chip */
159 }
160
161 return ret;
162}
163
164static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc)
165{
166 uint k;
167 u32 otpp, st;
168
169 /*
170 * record word offset of General Use Region
171 * for various chipcommon revs
172 */
173 if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24
174 || oi->sih->ccrev == 27) {
175 oi->otpgu_base = REVA4_OTPGU_BASE;
176 } else if (oi->sih->ccrev == 36) {
177 /*
178 * OTP size greater than equal to 2KB (128 words),
179 * otpgu_base is similar to rev23
180 */
181 if (oi->wsize >= 128)
182 oi->otpgu_base = REVB8_OTPGU_BASE;
183 else
184 oi->otpgu_base = REV36_OTPGU_BASE;
185 } else if (oi->sih->ccrev == 23 || oi->sih->ccrev >= 25) {
186 oi->otpgu_base = REVB8_OTPGU_BASE;
187 }
188
189 /* First issue an init command so the status is up to date */
190 otpp =
191 OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK);
192
193 W_REG(&cc->otpprog, otpp);
194 for (k = 0;
195 ((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
196 && (k < OTPP_TRIES); k++)
197 ;
198 if (k >= OTPP_TRIES)
199 return;
200
201 /* Read OTP lock bits and subregion programmed indication bits */
202 oi->status = R_REG(&cc->otpstatus);
203
204 if ((oi->sih->chip == BCM43224_CHIP_ID)
205 || (oi->sih->chip == BCM43225_CHIP_ID)) {
206 u32 p_bits;
207 p_bits =
208 (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) &
209 OTPGU_P_MSK)
210 >> OTPGU_P_SHIFT;
211 oi->status |= (p_bits << OTPS_GUP_SHIFT);
212 }
213
214 /*
215 * h/w region base and fuse region limit are fixed to
216 * the top and the bottom of the general use region.
217 * Everything else can be flexible.
218 */
219 oi->hwbase = oi->otpgu_base + OTPGU_SROM_OFF;
220 oi->hwlim = oi->wsize;
221 if (oi->status & OTPS_GUP_HW) {
222 oi->hwlim =
223 ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_HSB_OFF) / 16;
224 oi->swbase = oi->hwlim;
225 } else
226 oi->swbase = oi->hwbase;
227
228 /* subtract fuse and checksum from beginning */
229 oi->swlim = ipxotp_max_rgnsz(oi->sih, oi->wsize) / 2;
230
231 if (oi->status & OTPS_GUP_SW) {
232 oi->swlim =
233 ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_SFB_OFF) / 16;
234 oi->fbase = oi->swlim;
235 } else
236 oi->fbase = oi->swbase;
237
238 oi->flim = oi->wsize;
239}
240
241static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi)
242{
243 uint idx;
244 struct chipcregs __iomem *cc;
245
246 /* Make sure we're running IPX OTP */
247 if (!OTPTYPE_IPX(sih->ccrev))
248 return -EBADE;
249
250 /* Make sure OTP is not disabled */
251 if (ai_is_otp_disabled(sih))
252 return -EBADE;
253
254 /* Check for otp size */
255 switch ((sih->cccaps & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
256 case 0:
257 /* Nothing there */
258 return -EBADE;
259 case 1: /* 32x64 */
260 oi->rows = 32;
261 oi->cols = 64;
262 oi->wsize = 128;
263 break;
264 case 2: /* 64x64 */
265 oi->rows = 64;
266 oi->cols = 64;
267 oi->wsize = 256;
268 break;
269 case 5: /* 96x64 */
270 oi->rows = 96;
271 oi->cols = 64;
272 oi->wsize = 384;
273 break;
274 case 7: /* 16x64 *//* 1024 bits */
275 oi->rows = 16;
276 oi->cols = 64;
277 oi->wsize = 64;
278 break;
279 default:
280 /* Don't know the geometry */
281 return -EBADE;
282 }
283
284 /* Retrieve OTP region info */
285 idx = ai_coreidx(sih);
286 cc = ai_setcoreidx(sih, SI_CC_IDX);
287
288 _ipxotp_init(oi, cc);
289
290 ai_setcoreidx(sih, idx);
291
292 return 0;
293}
294
295static int
296ipxotp_read_region(struct otpinfo *oi, int region, u16 *data, uint *wlen)
297{
298 uint idx;
299 struct chipcregs __iomem *cc;
300 uint base, i, sz;
301
302 /* Validate region selection */
303 switch (region) {
304 case OTP_HW_RGN:
305 sz = (uint) oi->hwlim - oi->hwbase;
306 if (!(oi->status & OTPS_GUP_HW)) {
307 *wlen = sz;
308 return -ENODATA;
309 }
310 if (*wlen < sz) {
311 *wlen = sz;
312 return -EOVERFLOW;
313 }
314 base = oi->hwbase;
315 break;
316 case OTP_SW_RGN:
317 sz = ((uint) oi->swlim - oi->swbase);
318 if (!(oi->status & OTPS_GUP_SW)) {
319 *wlen = sz;
320 return -ENODATA;
321 }
322 if (*wlen < sz) {
323 *wlen = sz;
324 return -EOVERFLOW;
325 }
326 base = oi->swbase;
327 break;
328 case OTP_CI_RGN:
329 sz = OTPGU_CI_SZ;
330 if (!(oi->status & OTPS_GUP_CI)) {
331 *wlen = sz;
332 return -ENODATA;
333 }
334 if (*wlen < sz) {
335 *wlen = sz;
336 return -EOVERFLOW;
337 }
338 base = oi->otpgu_base + OTPGU_CI_OFF;
339 break;
340 case OTP_FUSE_RGN:
341 sz = (uint) oi->flim - oi->fbase;
342 if (!(oi->status & OTPS_GUP_FUSE)) {
343 *wlen = sz;
344 return -ENODATA;
345 }
346 if (*wlen < sz) {
347 *wlen = sz;
348 return -EOVERFLOW;
349 }
350 base = oi->fbase;
351 break;
352 case OTP_ALL_RGN:
353 sz = ((uint) oi->flim - oi->hwbase);
354 if (!(oi->status & (OTPS_GUP_HW | OTPS_GUP_SW))) {
355 *wlen = sz;
356 return -ENODATA;
357 }
358 if (*wlen < sz) {
359 *wlen = sz;
360 return -EOVERFLOW;
361 }
362 base = oi->hwbase;
363 break;
364 default:
365 return -EINVAL;
366 }
367
368 idx = ai_coreidx(oi->sih);
369 cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
370
371 /* Read the data */
372 for (i = 0; i < sz; i++)
373 data[i] = ipxotp_otpr(oi, cc, base + i);
374
375 ai_setcoreidx(oi->sih, idx);
376 *wlen = sz;
377 return 0;
378}
379
380static const struct otp_fn_s ipxotp_fn = {
381 (int (*)(struct si_pub *, struct otpinfo *)) ipxotp_init,
382 (int (*)(struct otpinfo *, int, u16 *, uint *)) ipxotp_read_region,
383};
384
385static int otp_init(struct si_pub *sih, struct otpinfo *oi)
386{
387
388 int ret;
389
390 memset(oi, 0, sizeof(struct otpinfo));
391
392 oi->ccrev = sih->ccrev;
393
394 if (OTPTYPE_IPX(oi->ccrev))
395 oi->fn = &ipxotp_fn;
396
397 if (oi->fn == NULL)
398 return -EBADE;
399
400 oi->sih = sih;
401
402 ret = (oi->fn->init) (sih, oi);
403
404 return ret;
405}
406
407int
408otp_read_region(struct si_pub *sih, int region, u16 *data, uint *wlen) {
409 struct otpinfo otpinfo;
410 struct otpinfo *oi = &otpinfo;
411 int err = 0;
412
413 if (ai_is_otp_disabled(sih)) {
414 err = -EPERM;
415 goto out;
416 }
417
418 err = otp_init(sih, oi);
419 if (err)
420 goto out;
421
422 err = ((oi)->fn->read_region)(oi, region, data, wlen);
423
424 out:
425 return err;
426}
diff --git a/drivers/staging/brcm80211/brcmsmac/otp.h b/drivers/staging/brcm80211/brcmsmac/otp.h
deleted file mode 100644
index 6b6d31cf956..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/otp.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_OTP_H_
18#define _BRCM_OTP_H_
19
20#include "types.h"
21
22/* OTP regions */
23#define OTP_HW_RGN 1
24#define OTP_SW_RGN 2
25#define OTP_CI_RGN 4
26#define OTP_FUSE_RGN 8
27/* From h/w region to end of OTP including checksum */
28#define OTP_ALL_RGN 0xf
29
30/* OTP Size */
31#define OTP_SZ_MAX (6144/8) /* maximum bytes in one CIS */
32
33extern int otp_read_region(struct si_pub *sih, int region, u16 *data,
34 uint *wlen);
35
36#endif /* _BRCM_OTP_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c b/drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c
deleted file mode 100644
index d54cfdb0a8e..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c
+++ /dev/null
@@ -1,2988 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/bitops.h>
19
20#include <brcm_hw_ids.h>
21#include <chipcommon.h>
22#include <aiutils.h>
23#include <d11.h>
24#include <phy_shim.h>
25#include "phy_hal.h"
26#include "phy_int.h"
27#include "phy_radio.h"
28#include "phy_lcn.h"
29#include "phyreg_n.h"
30
31#define VALID_N_RADIO(radioid) ((radioid == BCM2055_ID) || \
32 (radioid == BCM2056_ID) || \
33 (radioid == BCM2057_ID))
34
35#define VALID_LCN_RADIO(radioid) (radioid == BCM2064_ID)
36
37#define VALID_RADIO(pi, radioid) ( \
38 (ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
39 (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
40
41/* basic mux operation - can be optimized on several architectures */
42#define MUX(pred, true, false) ((pred) ? (true) : (false))
43
44/* modulo inc/dec - assumes x E [0, bound - 1] */
45#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
46
47/* modulo inc/dec, bound = 2^k */
48#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
49#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
50
51struct chan_info_basic {
52 u16 chan;
53 u16 freq;
54};
55
56static const struct chan_info_basic chan_info_all[] = {
57 {1, 2412},
58 {2, 2417},
59 {3, 2422},
60 {4, 2427},
61 {5, 2432},
62 {6, 2437},
63 {7, 2442},
64 {8, 2447},
65 {9, 2452},
66 {10, 2457},
67 {11, 2462},
68 {12, 2467},
69 {13, 2472},
70 {14, 2484},
71
72 {34, 5170},
73 {38, 5190},
74 {42, 5210},
75 {46, 5230},
76
77 {36, 5180},
78 {40, 5200},
79 {44, 5220},
80 {48, 5240},
81 {52, 5260},
82 {56, 5280},
83 {60, 5300},
84 {64, 5320},
85
86 {100, 5500},
87 {104, 5520},
88 {108, 5540},
89 {112, 5560},
90 {116, 5580},
91 {120, 5600},
92 {124, 5620},
93 {128, 5640},
94 {132, 5660},
95 {136, 5680},
96 {140, 5700},
97
98 {149, 5745},
99 {153, 5765},
100 {157, 5785},
101 {161, 5805},
102 {165, 5825},
103
104 {184, 4920},
105 {188, 4940},
106 {192, 4960},
107 {196, 4980},
108 {200, 5000},
109 {204, 5020},
110 {208, 5040},
111 {212, 5060},
112 {216, 50800}
113};
114
115const u8 ofdm_rate_lookup[] = {
116
117 BRCM_RATE_48M,
118 BRCM_RATE_24M,
119 BRCM_RATE_12M,
120 BRCM_RATE_6M,
121 BRCM_RATE_54M,
122 BRCM_RATE_36M,
123 BRCM_RATE_18M,
124 BRCM_RATE_9M
125};
126
127#define PHY_WREG_LIMIT 24
128
129void wlc_phyreg_enter(struct brcms_phy_pub *pih)
130{
131 struct brcms_phy *pi = (struct brcms_phy *) pih;
132 wlapi_bmac_ucode_wake_override_phyreg_set(pi->sh->physhim);
133}
134
135void wlc_phyreg_exit(struct brcms_phy_pub *pih)
136{
137 struct brcms_phy *pi = (struct brcms_phy *) pih;
138 wlapi_bmac_ucode_wake_override_phyreg_clear(pi->sh->physhim);
139}
140
141void wlc_radioreg_enter(struct brcms_phy_pub *pih)
142{
143 struct brcms_phy *pi = (struct brcms_phy *) pih;
144 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, MCTL_LOCK_RADIO);
145
146 udelay(10);
147}
148
149void wlc_radioreg_exit(struct brcms_phy_pub *pih)
150{
151 struct brcms_phy *pi = (struct brcms_phy *) pih;
152 u16 dummy;
153
154 dummy = R_REG(&pi->regs->phyversion);
155 pi->phy_wreg = 0;
156 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0);
157}
158
159u16 read_radio_reg(struct brcms_phy *pi, u16 addr)
160{
161 u16 data;
162
163 if ((addr == RADIO_IDCODE))
164 return 0xffff;
165
166 switch (pi->pubpi.phy_type) {
167 case PHY_TYPE_N:
168 if (!CONF_HAS(PHYTYPE, PHY_TYPE_N))
169 break;
170 if (NREV_GE(pi->pubpi.phy_rev, 7))
171 addr |= RADIO_2057_READ_OFF;
172 else
173 addr |= RADIO_2055_READ_OFF;
174 break;
175
176 case PHY_TYPE_LCN:
177 if (!CONF_HAS(PHYTYPE, PHY_TYPE_LCN))
178 break;
179 addr |= RADIO_2064_READ_OFF;
180 break;
181
182 default:
183 break;
184 }
185
186 if ((D11REV_GE(pi->sh->corerev, 24)) ||
187 (D11REV_IS(pi->sh->corerev, 22)
188 && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
189 W_REG_FLUSH(&pi->regs->radioregaddr, addr);
190 data = R_REG(&pi->regs->radioregdata);
191 } else {
192 W_REG_FLUSH(&pi->regs->phy4waddr, addr);
193
194#ifdef __ARM_ARCH_4T__
195 __asm__(" .align 4 ");
196 __asm__(" nop ");
197 data = R_REG(&pi->regs->phy4wdatalo);
198#else
199 data = R_REG(&pi->regs->phy4wdatalo);
200#endif
201
202 }
203 pi->phy_wreg = 0;
204
205 return data;
206}
207
208void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
209{
210 if ((D11REV_GE(pi->sh->corerev, 24)) ||
211 (D11REV_IS(pi->sh->corerev, 22)
212 && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
213
214 W_REG_FLUSH(&pi->regs->radioregaddr, addr);
215 W_REG(&pi->regs->radioregdata, val);
216 } else {
217 W_REG_FLUSH(&pi->regs->phy4waddr, addr);
218 W_REG(&pi->regs->phy4wdatalo, val);
219 }
220
221 if (++pi->phy_wreg >= pi->phy_wreg_limit) {
222 (void)R_REG(&pi->regs->maccontrol);
223 pi->phy_wreg = 0;
224 }
225}
226
227static u32 read_radio_id(struct brcms_phy *pi)
228{
229 u32 id;
230
231 if (D11REV_GE(pi->sh->corerev, 24)) {
232 u32 b0, b1, b2;
233
234 W_REG_FLUSH(&pi->regs->radioregaddr, 0);
235 b0 = (u32) R_REG(&pi->regs->radioregdata);
236 W_REG_FLUSH(&pi->regs->radioregaddr, 1);
237 b1 = (u32) R_REG(&pi->regs->radioregdata);
238 W_REG_FLUSH(&pi->regs->radioregaddr, 2);
239 b2 = (u32) R_REG(&pi->regs->radioregdata);
240
241 id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
242 & 0xf);
243 } else {
244 W_REG_FLUSH(&pi->regs->phy4waddr, RADIO_IDCODE);
245 id = (u32) R_REG(&pi->regs->phy4wdatalo);
246 id |= (u32) R_REG(&pi->regs->phy4wdatahi) << 16;
247 }
248 pi->phy_wreg = 0;
249 return id;
250}
251
252void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
253{
254 u16 rval;
255
256 rval = read_radio_reg(pi, addr);
257 write_radio_reg(pi, addr, (rval & val));
258}
259
260void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
261{
262 u16 rval;
263
264 rval = read_radio_reg(pi, addr);
265 write_radio_reg(pi, addr, (rval | val));
266}
267
268void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask)
269{
270 u16 rval;
271
272 rval = read_radio_reg(pi, addr);
273 write_radio_reg(pi, addr, (rval ^ mask));
274}
275
276void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val)
277{
278 u16 rval;
279
280 rval = read_radio_reg(pi, addr);
281 write_radio_reg(pi, addr, (rval & ~mask) | (val & mask));
282}
283
284void write_phy_channel_reg(struct brcms_phy *pi, uint val)
285{
286 W_REG(&pi->regs->phychannel, val);
287}
288
289u16 read_phy_reg(struct brcms_phy *pi, u16 addr)
290{
291 struct d11regs __iomem *regs;
292
293 regs = pi->regs;
294
295 W_REG_FLUSH(&regs->phyregaddr, addr);
296
297 pi->phy_wreg = 0;
298 return R_REG(&regs->phyregdata);
299}
300
301void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
302{
303 struct d11regs __iomem *regs;
304
305 regs = pi->regs;
306
307#ifdef CONFIG_BCM47XX
308 W_REG_FLUSH(&regs->phyregaddr, addr);
309 W_REG(&regs->phyregdata, val);
310 if (addr == 0x72)
311 (void)R_REG(&regs->phyregdata);
312#else
313 W_REG((u32 __iomem *)(&regs->phyregaddr), addr | (val << 16));
314 if (++pi->phy_wreg >= pi->phy_wreg_limit) {
315 pi->phy_wreg = 0;
316 (void)R_REG(&regs->phyversion);
317 }
318#endif
319}
320
321void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
322{
323 struct d11regs __iomem *regs;
324
325 regs = pi->regs;
326
327 W_REG_FLUSH(&regs->phyregaddr, addr);
328
329 W_REG(&regs->phyregdata, (R_REG(&regs->phyregdata) & val));
330 pi->phy_wreg = 0;
331}
332
333void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
334{
335 struct d11regs __iomem *regs;
336
337 regs = pi->regs;
338
339 W_REG_FLUSH(&regs->phyregaddr, addr);
340
341 W_REG(&regs->phyregdata, (R_REG(&regs->phyregdata) | val));
342 pi->phy_wreg = 0;
343}
344
345void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val)
346{
347 struct d11regs __iomem *regs;
348
349 regs = pi->regs;
350
351 W_REG_FLUSH(&regs->phyregaddr, addr);
352
353 W_REG(&regs->phyregdata,
354 ((R_REG(&regs->phyregdata) & ~mask) | (val & mask)));
355 pi->phy_wreg = 0;
356}
357
358static void wlc_set_phy_uninitted(struct brcms_phy *pi)
359{
360 int i, j;
361
362 pi->initialized = false;
363
364 pi->tx_vos = 0xffff;
365 pi->nrssi_table_delta = 0x7fffffff;
366 pi->rc_cal = 0xffff;
367 pi->mintxbias = 0xffff;
368 pi->txpwridx = -1;
369 if (ISNPHY(pi)) {
370 pi->phy_spuravoid = SPURAVOID_DISABLE;
371
372 if (NREV_GE(pi->pubpi.phy_rev, 3)
373 && NREV_LT(pi->pubpi.phy_rev, 7))
374 pi->phy_spuravoid = SPURAVOID_AUTO;
375
376 pi->nphy_papd_skip = 0;
377 pi->nphy_papd_epsilon_offset[0] = 0xf588;
378 pi->nphy_papd_epsilon_offset[1] = 0xf588;
379 pi->nphy_txpwr_idx[0] = 128;
380 pi->nphy_txpwr_idx[1] = 128;
381 pi->nphy_txpwrindex[0].index_internal = 40;
382 pi->nphy_txpwrindex[1].index_internal = 40;
383 pi->phy_pabias = 0;
384 } else {
385 pi->phy_spuravoid = SPURAVOID_AUTO;
386 }
387 pi->radiopwr = 0xffff;
388 for (i = 0; i < STATIC_NUM_RF; i++) {
389 for (j = 0; j < STATIC_NUM_BB; j++)
390 pi->stats_11b_txpower[i][j] = -1;
391 }
392}
393
394struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp)
395{
396 struct shared_phy *sh;
397
398 sh = kzalloc(sizeof(struct shared_phy), GFP_ATOMIC);
399 if (sh == NULL)
400 return NULL;
401
402 sh->sih = shp->sih;
403 sh->physhim = shp->physhim;
404 sh->unit = shp->unit;
405 sh->corerev = shp->corerev;
406
407 sh->vid = shp->vid;
408 sh->did = shp->did;
409 sh->chip = shp->chip;
410 sh->chiprev = shp->chiprev;
411 sh->chippkg = shp->chippkg;
412 sh->sromrev = shp->sromrev;
413 sh->boardtype = shp->boardtype;
414 sh->boardrev = shp->boardrev;
415 sh->boardvendor = shp->boardvendor;
416 sh->boardflags = shp->boardflags;
417 sh->boardflags2 = shp->boardflags2;
418 sh->buscorerev = shp->buscorerev;
419
420 sh->fast_timer = PHY_SW_TIMER_FAST;
421 sh->slow_timer = PHY_SW_TIMER_SLOW;
422 sh->glacial_timer = PHY_SW_TIMER_GLACIAL;
423
424 sh->rssi_mode = RSSI_ANT_MERGE_MAX;
425
426 return sh;
427}
428
429static void wlc_phy_timercb_phycal(struct brcms_phy *pi)
430{
431 uint delay = 5;
432
433 if (PHY_PERICAL_MPHASE_PENDING(pi)) {
434 if (!pi->sh->up) {
435 wlc_phy_cal_perical_mphase_reset(pi);
436 return;
437 }
438
439 if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)) {
440
441 delay = 1000;
442 wlc_phy_cal_perical_mphase_restart(pi);
443 } else
444 wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_AUTO);
445 wlapi_add_timer(pi->sh->physhim, pi->phycal_timer, delay, 0);
446 return;
447 }
448
449}
450
451static u32 wlc_phy_get_radio_ver(struct brcms_phy *pi)
452{
453 u32 ver;
454
455 ver = read_radio_id(pi);
456
457 return ver;
458}
459
460struct brcms_phy_pub *
461wlc_phy_attach(struct shared_phy *sh, struct d11regs __iomem *regs,
462 int bandtype, struct wiphy *wiphy)
463{
464 struct brcms_phy *pi;
465 u32 sflags = 0;
466 uint phyversion;
467 u32 idcode;
468 int i;
469
470 if (D11REV_IS(sh->corerev, 4))
471 sflags = SISF_2G_PHY | SISF_5G_PHY;
472 else
473 sflags = ai_core_sflags(sh->sih, 0, 0);
474
475 if (bandtype == BRCM_BAND_5G) {
476 if ((sflags & (SISF_5G_PHY | SISF_DB_PHY)) == 0)
477 return NULL;
478 }
479
480 pi = sh->phy_head;
481 if ((sflags & SISF_DB_PHY) && pi) {
482 wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
483 pi->refcnt++;
484 return &pi->pubpi_ro;
485 }
486
487 pi = kzalloc(sizeof(struct brcms_phy), GFP_ATOMIC);
488 if (pi == NULL)
489 return NULL;
490 pi->wiphy = wiphy;
491 pi->regs = regs;
492 pi->sh = sh;
493 pi->phy_init_por = true;
494 pi->phy_wreg_limit = PHY_WREG_LIMIT;
495
496 pi->txpwr_percent = 100;
497
498 pi->do_initcal = true;
499
500 pi->phycal_tempdelta = 0;
501
502 if (bandtype == BRCM_BAND_2G && (sflags & SISF_2G_PHY))
503 pi->pubpi.coreflags = SICF_GMODE;
504
505 wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
506 phyversion = R_REG(&pi->regs->phyversion);
507
508 pi->pubpi.phy_type = PHY_TYPE(phyversion);
509 pi->pubpi.phy_rev = phyversion & PV_PV_MASK;
510
511 if (pi->pubpi.phy_type == PHY_TYPE_LCNXN) {
512 pi->pubpi.phy_type = PHY_TYPE_N;
513 pi->pubpi.phy_rev += LCNXN_BASEREV;
514 }
515 pi->pubpi.phy_corenum = PHY_CORE_NUM_2;
516 pi->pubpi.ana_rev = (phyversion & PV_AV_MASK) >> PV_AV_SHIFT;
517
518 if (!pi->pubpi.phy_type == PHY_TYPE_N &&
519 !pi->pubpi.phy_type == PHY_TYPE_LCN)
520 goto err;
521
522 if (bandtype == BRCM_BAND_5G) {
523 if (!ISNPHY(pi))
524 goto err;
525 } else if (!ISNPHY(pi) && !ISLCNPHY(pi)) {
526 goto err;
527 }
528
529 wlc_phy_anacore((struct brcms_phy_pub *) pi, ON);
530
531 idcode = wlc_phy_get_radio_ver(pi);
532 pi->pubpi.radioid =
533 (idcode & IDCODE_ID_MASK) >> IDCODE_ID_SHIFT;
534 pi->pubpi.radiorev =
535 (idcode & IDCODE_REV_MASK) >> IDCODE_REV_SHIFT;
536 pi->pubpi.radiover =
537 (idcode & IDCODE_VER_MASK) >> IDCODE_VER_SHIFT;
538 if (!VALID_RADIO(pi, pi->pubpi.radioid))
539 goto err;
540
541 wlc_phy_switch_radio((struct brcms_phy_pub *) pi, OFF);
542
543 wlc_set_phy_uninitted(pi);
544
545 pi->bw = WL_CHANSPEC_BW_20;
546 pi->radio_chanspec = (bandtype == BRCM_BAND_2G) ?
547 ch20mhz_chspec(1) : ch20mhz_chspec(36);
548
549 pi->rxiq_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
550 pi->rxiq_antsel = ANT_RX_DIV_DEF;
551
552 pi->watchdog_override = true;
553
554 pi->cal_type_override = PHY_PERICAL_AUTO;
555
556 pi->nphy_saved_noisevars.bufcount = 0;
557
558 if (ISNPHY(pi))
559 pi->min_txpower = PHY_TXPWR_MIN_NPHY;
560 else
561 pi->min_txpower = PHY_TXPWR_MIN;
562
563 pi->sh->phyrxchain = 0x3;
564
565 pi->rx2tx_biasentry = -1;
566
567 pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
568 pi->phy_txcore_enable_temp =
569 PHY_CHAIN_TX_DISABLE_TEMP - PHY_HYSTERESIS_DELTATEMP;
570 pi->phy_tempsense_offset = 0;
571 pi->phy_txcore_heatedup = false;
572
573 pi->nphy_lastcal_temp = -50;
574
575 pi->phynoise_polling = true;
576 if (ISNPHY(pi) || ISLCNPHY(pi))
577 pi->phynoise_polling = false;
578
579 for (i = 0; i < TXP_NUM_RATES; i++) {
580 pi->txpwr_limit[i] = BRCMS_TXPWR_MAX;
581 pi->txpwr_env_limit[i] = BRCMS_TXPWR_MAX;
582 pi->tx_user_target[i] = BRCMS_TXPWR_MAX;
583 }
584
585 pi->radiopwr_override = RADIOPWR_OVERRIDE_DEF;
586
587 pi->user_txpwr_at_rfport = false;
588
589 if (ISNPHY(pi)) {
590
591 pi->phycal_timer = wlapi_init_timer(pi->sh->physhim,
592 wlc_phy_timercb_phycal,
593 pi, "phycal");
594 if (!pi->phycal_timer)
595 goto err;
596
597 if (!wlc_phy_attach_nphy(pi))
598 goto err;
599
600 } else if (ISLCNPHY(pi)) {
601 if (!wlc_phy_attach_lcnphy(pi))
602 goto err;
603
604 }
605
606 pi->refcnt++;
607 pi->next = pi->sh->phy_head;
608 sh->phy_head = pi;
609
610 memcpy(&pi->pubpi_ro, &pi->pubpi, sizeof(struct brcms_phy_pub));
611
612 return &pi->pubpi_ro;
613
614err:
615 kfree(pi);
616 return NULL;
617}
618
619void wlc_phy_detach(struct brcms_phy_pub *pih)
620{
621 struct brcms_phy *pi = (struct brcms_phy *) pih;
622
623 if (pih) {
624 if (--pi->refcnt)
625 return;
626
627 if (pi->phycal_timer) {
628 wlapi_free_timer(pi->sh->physhim, pi->phycal_timer);
629 pi->phycal_timer = NULL;
630 }
631
632 if (pi->sh->phy_head == pi)
633 pi->sh->phy_head = pi->next;
634 else if (pi->sh->phy_head->next == pi)
635 pi->sh->phy_head->next = NULL;
636
637 if (pi->pi_fptr.detach)
638 (pi->pi_fptr.detach)(pi);
639
640 kfree(pi);
641 }
642}
643
644bool
645wlc_phy_get_phyversion(struct brcms_phy_pub *pih, u16 *phytype, u16 *phyrev,
646 u16 *radioid, u16 *radiover)
647{
648 struct brcms_phy *pi = (struct brcms_phy *) pih;
649 *phytype = (u16) pi->pubpi.phy_type;
650 *phyrev = (u16) pi->pubpi.phy_rev;
651 *radioid = pi->pubpi.radioid;
652 *radiover = pi->pubpi.radiorev;
653
654 return true;
655}
656
657bool wlc_phy_get_encore(struct brcms_phy_pub *pih)
658{
659 struct brcms_phy *pi = (struct brcms_phy *) pih;
660 return pi->pubpi.abgphy_encore;
661}
662
663u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih)
664{
665 struct brcms_phy *pi = (struct brcms_phy *) pih;
666 return pi->pubpi.coreflags;
667}
668
669void wlc_phy_anacore(struct brcms_phy_pub *pih, bool on)
670{
671 struct brcms_phy *pi = (struct brcms_phy *) pih;
672
673 if (ISNPHY(pi)) {
674 if (on) {
675 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
676 write_phy_reg(pi, 0xa6, 0x0d);
677 write_phy_reg(pi, 0x8f, 0x0);
678 write_phy_reg(pi, 0xa7, 0x0d);
679 write_phy_reg(pi, 0xa5, 0x0);
680 } else {
681 write_phy_reg(pi, 0xa5, 0x0);
682 }
683 } else {
684 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
685 write_phy_reg(pi, 0x8f, 0x07ff);
686 write_phy_reg(pi, 0xa6, 0x0fd);
687 write_phy_reg(pi, 0xa5, 0x07ff);
688 write_phy_reg(pi, 0xa7, 0x0fd);
689 } else {
690 write_phy_reg(pi, 0xa5, 0x7fff);
691 }
692 }
693 } else if (ISLCNPHY(pi)) {
694 if (on) {
695 and_phy_reg(pi, 0x43b,
696 ~((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
697 } else {
698 or_phy_reg(pi, 0x43c,
699 (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
700 or_phy_reg(pi, 0x43b,
701 (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
702 }
703 }
704}
705
706u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih)
707{
708 struct brcms_phy *pi = (struct brcms_phy *) pih;
709
710 u32 phy_bw_clkbits = 0;
711
712 if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) {
713 switch (pi->bw) {
714 case WL_CHANSPEC_BW_10:
715 phy_bw_clkbits = SICF_BW10;
716 break;
717 case WL_CHANSPEC_BW_20:
718 phy_bw_clkbits = SICF_BW20;
719 break;
720 case WL_CHANSPEC_BW_40:
721 phy_bw_clkbits = SICF_BW40;
722 break;
723 default:
724 break;
725 }
726 }
727
728 return phy_bw_clkbits;
729}
730
731void wlc_phy_por_inform(struct brcms_phy_pub *ppi)
732{
733 struct brcms_phy *pi = (struct brcms_phy *) ppi;
734
735 pi->phy_init_por = true;
736}
737
738void wlc_phy_edcrs_lock(struct brcms_phy_pub *pih, bool lock)
739{
740 struct brcms_phy *pi = (struct brcms_phy *) pih;
741
742 pi->edcrs_threshold_lock = lock;
743
744 write_phy_reg(pi, 0x22c, 0x46b);
745 write_phy_reg(pi, 0x22d, 0x46b);
746 write_phy_reg(pi, 0x22e, 0x3c0);
747 write_phy_reg(pi, 0x22f, 0x3c0);
748}
749
750void wlc_phy_initcal_enable(struct brcms_phy_pub *pih, bool initcal)
751{
752 struct brcms_phy *pi = (struct brcms_phy *) pih;
753
754 pi->do_initcal = initcal;
755}
756
757void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *pih, bool newstate)
758{
759 struct brcms_phy *pi = (struct brcms_phy *) pih;
760
761 if (!pi || !pi->sh)
762 return;
763
764 pi->sh->clk = newstate;
765}
766
767void wlc_phy_hw_state_upd(struct brcms_phy_pub *pih, bool newstate)
768{
769 struct brcms_phy *pi = (struct brcms_phy *) pih;
770
771 if (!pi || !pi->sh)
772 return;
773
774 pi->sh->up = newstate;
775}
776
777void wlc_phy_init(struct brcms_phy_pub *pih, u16 chanspec)
778{
779 u32 mc;
780 void (*phy_init)(struct brcms_phy *) = NULL;
781 struct brcms_phy *pi = (struct brcms_phy *) pih;
782
783 if (pi->init_in_progress)
784 return;
785
786 pi->init_in_progress = true;
787
788 pi->radio_chanspec = chanspec;
789
790 mc = R_REG(&pi->regs->maccontrol);
791 if (WARN(mc & MCTL_EN_MAC, "HW error MAC running on init"))
792 return;
793
794 if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN))
795 pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
796
797 if (WARN(!(ai_core_sflags(pi->sh->sih, 0, 0) & SISF_FCLKA),
798 "HW error SISF_FCLKA\n"))
799 return;
800
801 phy_init = pi->pi_fptr.init;
802
803 if (phy_init == NULL)
804 return;
805
806 wlc_phy_anacore(pih, ON);
807
808 if (CHSPEC_BW(pi->radio_chanspec) != pi->bw)
809 wlapi_bmac_bw_set(pi->sh->physhim,
810 CHSPEC_BW(pi->radio_chanspec));
811
812 pi->nphy_gain_boost = true;
813
814 wlc_phy_switch_radio((struct brcms_phy_pub *) pi, ON);
815
816 (*phy_init)(pi);
817
818 pi->phy_init_por = false;
819
820 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
821 wlc_phy_do_dummy_tx(pi, true, OFF);
822
823 if (!(ISNPHY(pi)))
824 wlc_phy_txpower_update_shm(pi);
825
826 wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi, pi->sh->rx_antdiv);
827
828 pi->init_in_progress = false;
829}
830
831void wlc_phy_cal_init(struct brcms_phy_pub *pih)
832{
833 struct brcms_phy *pi = (struct brcms_phy *) pih;
834 void (*cal_init)(struct brcms_phy *) = NULL;
835
836 if (WARN((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) != 0,
837 "HW error: MAC enabled during phy cal\n"))
838 return;
839
840 if (!pi->initialized) {
841 cal_init = pi->pi_fptr.calinit;
842 if (cal_init)
843 (*cal_init)(pi);
844
845 pi->initialized = true;
846 }
847}
848
849int wlc_phy_down(struct brcms_phy_pub *pih)
850{
851 struct brcms_phy *pi = (struct brcms_phy *) pih;
852 int callbacks = 0;
853
854 if (pi->phycal_timer
855 && !wlapi_del_timer(pi->sh->physhim, pi->phycal_timer))
856 callbacks++;
857
858 pi->nphy_iqcal_chanspec_2G = 0;
859 pi->nphy_iqcal_chanspec_5G = 0;
860
861 return callbacks;
862}
863
864void
865wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id, uint tbl_offset,
866 u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
867{
868 write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
869
870 pi->tbl_data_hi = tblDataHi;
871 pi->tbl_data_lo = tblDataLo;
872
873 if (pi->sh->chip == BCM43224_CHIP_ID &&
874 pi->sh->chiprev == 1) {
875 pi->tbl_addr = tblAddr;
876 pi->tbl_save_id = tbl_id;
877 pi->tbl_save_offset = tbl_offset;
878 }
879}
880
881void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val)
882{
883 if ((pi->sh->chip == BCM43224_CHIP_ID) &&
884 (pi->sh->chiprev == 1) &&
885 (pi->tbl_save_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
886 read_phy_reg(pi, pi->tbl_data_lo);
887
888 write_phy_reg(pi, pi->tbl_addr,
889 (pi->tbl_save_id << 10) | pi->tbl_save_offset);
890 pi->tbl_save_offset++;
891 }
892
893 if (width == 32) {
894 write_phy_reg(pi, pi->tbl_data_hi, (u16) (val >> 16));
895 write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
896 } else {
897 write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
898 }
899}
900
901void
902wlc_phy_write_table(struct brcms_phy *pi, const struct phytbl_info *ptbl_info,
903 u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
904{
905 uint idx;
906 uint tbl_id = ptbl_info->tbl_id;
907 uint tbl_offset = ptbl_info->tbl_offset;
908 uint tbl_width = ptbl_info->tbl_width;
909 const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr;
910 const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr;
911 const u32 *ptbl_32b = (const u32 *)ptbl_info->tbl_ptr;
912
913 write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
914
915 for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
916
917 if ((pi->sh->chip == BCM43224_CHIP_ID) &&
918 (pi->sh->chiprev == 1) &&
919 (tbl_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
920 read_phy_reg(pi, tblDataLo);
921
922 write_phy_reg(pi, tblAddr,
923 (tbl_id << 10) | (tbl_offset + idx));
924 }
925
926 if (tbl_width == 32) {
927 write_phy_reg(pi, tblDataHi,
928 (u16) (ptbl_32b[idx] >> 16));
929 write_phy_reg(pi, tblDataLo, (u16) ptbl_32b[idx]);
930 } else if (tbl_width == 16) {
931 write_phy_reg(pi, tblDataLo, ptbl_16b[idx]);
932 } else {
933 write_phy_reg(pi, tblDataLo, ptbl_8b[idx]);
934 }
935 }
936}
937
938void
939wlc_phy_read_table(struct brcms_phy *pi, const struct phytbl_info *ptbl_info,
940 u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
941{
942 uint idx;
943 uint tbl_id = ptbl_info->tbl_id;
944 uint tbl_offset = ptbl_info->tbl_offset;
945 uint tbl_width = ptbl_info->tbl_width;
946 u8 *ptbl_8b = (u8 *)ptbl_info->tbl_ptr;
947 u16 *ptbl_16b = (u16 *)ptbl_info->tbl_ptr;
948 u32 *ptbl_32b = (u32 *)ptbl_info->tbl_ptr;
949
950 write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
951
952 for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
953
954 if ((pi->sh->chip == BCM43224_CHIP_ID) &&
955 (pi->sh->chiprev == 1)) {
956 (void)read_phy_reg(pi, tblDataLo);
957
958 write_phy_reg(pi, tblAddr,
959 (tbl_id << 10) | (tbl_offset + idx));
960 }
961
962 if (tbl_width == 32) {
963 ptbl_32b[idx] = read_phy_reg(pi, tblDataLo);
964 ptbl_32b[idx] |= (read_phy_reg(pi, tblDataHi) << 16);
965 } else if (tbl_width == 16) {
966 ptbl_16b[idx] = read_phy_reg(pi, tblDataLo);
967 } else {
968 ptbl_8b[idx] = (u8) read_phy_reg(pi, tblDataLo);
969 }
970 }
971}
972
973uint
974wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
975 struct radio_20xx_regs *radioregs)
976{
977 uint i = 0;
978
979 do {
980 if (radioregs[i].do_init)
981 write_radio_reg(pi, radioregs[i].address,
982 (u16) radioregs[i].init);
983
984 i++;
985 } while (radioregs[i].address != 0xffff);
986
987 return i;
988}
989
990uint
991wlc_phy_init_radio_regs(struct brcms_phy *pi,
992 const struct radio_regs *radioregs,
993 u16 core_offset)
994{
995 uint i = 0;
996 uint count = 0;
997
998 do {
999 if (CHSPEC_IS5G(pi->radio_chanspec)) {
1000 if (radioregs[i].do_init_a) {
1001 write_radio_reg(pi,
1002 radioregs[i].
1003 address | core_offset,
1004 (u16) radioregs[i].init_a);
1005 if (ISNPHY(pi) && (++count % 4 == 0))
1006 BRCMS_PHY_WAR_PR51571(pi);
1007 }
1008 } else {
1009 if (radioregs[i].do_init_g) {
1010 write_radio_reg(pi,
1011 radioregs[i].
1012 address | core_offset,
1013 (u16) radioregs[i].init_g);
1014 if (ISNPHY(pi) && (++count % 4 == 0))
1015 BRCMS_PHY_WAR_PR51571(pi);
1016 }
1017 }
1018
1019 i++;
1020 } while (radioregs[i].address != 0xffff);
1021
1022 return i;
1023}
1024
1025void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on)
1026{
1027#define DUMMY_PKT_LEN 20
1028 struct d11regs __iomem *regs = pi->regs;
1029 int i, count;
1030 u8 ofdmpkt[DUMMY_PKT_LEN] = {
1031 0xcc, 0x01, 0x02, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
1032 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
1033 };
1034 u8 cckpkt[DUMMY_PKT_LEN] = {
1035 0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
1036 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
1037 };
1038 u32 *dummypkt;
1039
1040 dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
1041 wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
1042 dummypkt);
1043
1044 W_REG(&regs->xmtsel, 0);
1045
1046 if (D11REV_GE(pi->sh->corerev, 11))
1047 W_REG(&regs->wepctl, 0x100);
1048 else
1049 W_REG(&regs->wepctl, 0);
1050
1051 W_REG(&regs->txe_phyctl, (ofdm ? 1 : 0) | PHY_TXC_ANT_0);
1052 if (ISNPHY(pi) || ISLCNPHY(pi))
1053 W_REG(&regs->txe_phyctl1, 0x1A02);
1054
1055 W_REG(&regs->txe_wm_0, 0);
1056 W_REG(&regs->txe_wm_1, 0);
1057
1058 W_REG(&regs->xmttplatetxptr, 0);
1059 W_REG(&regs->xmttxcnt, DUMMY_PKT_LEN);
1060
1061 W_REG(&regs->xmtsel, ((8 << 8) | (1 << 5) | (1 << 2) | 2));
1062
1063 W_REG(&regs->txe_ctl, 0);
1064
1065 if (!pa_on) {
1066 if (ISNPHY(pi))
1067 wlc_phy_pa_override_nphy(pi, OFF);
1068 }
1069
1070 if (ISNPHY(pi) || ISLCNPHY(pi))
1071 W_REG(&regs->txe_aux, 0xD0);
1072 else
1073 W_REG(&regs->txe_aux, ((1 << 5) | (1 << 4)));
1074
1075 (void)R_REG(&regs->txe_aux);
1076
1077 i = 0;
1078 count = ofdm ? 30 : 250;
1079 while ((i++ < count)
1080 && (R_REG(&regs->txe_status) & (1 << 7)))
1081 udelay(10);
1082
1083 i = 0;
1084
1085 while ((i++ < 10)
1086 && ((R_REG(&regs->txe_status) & (1 << 10)) == 0))
1087 udelay(10);
1088
1089 i = 0;
1090
1091 while ((i++ < 10) && ((R_REG(&regs->ifsstat) & (1 << 8))))
1092 udelay(10);
1093
1094 if (!pa_on) {
1095 if (ISNPHY(pi))
1096 wlc_phy_pa_override_nphy(pi, ON);
1097 }
1098}
1099
1100void wlc_phy_hold_upd(struct brcms_phy_pub *pih, u32 id, bool set)
1101{
1102 struct brcms_phy *pi = (struct brcms_phy *) pih;
1103
1104 if (set)
1105 mboolset(pi->measure_hold, id);
1106 else
1107 mboolclr(pi->measure_hold, id);
1108
1109 return;
1110}
1111
1112void wlc_phy_mute_upd(struct brcms_phy_pub *pih, bool mute, u32 flags)
1113{
1114 struct brcms_phy *pi = (struct brcms_phy *) pih;
1115
1116 if (mute)
1117 mboolset(pi->measure_hold, PHY_HOLD_FOR_MUTE);
1118 else
1119 mboolclr(pi->measure_hold, PHY_HOLD_FOR_MUTE);
1120
1121 if (!mute && (flags & PHY_MUTE_FOR_PREISM))
1122 pi->nphy_perical_last = pi->sh->now - pi->sh->glacial_timer;
1123 return;
1124}
1125
1126void wlc_phy_clear_tssi(struct brcms_phy_pub *pih)
1127{
1128 struct brcms_phy *pi = (struct brcms_phy *) pih;
1129
1130 if (ISNPHY(pi)) {
1131 return;
1132 } else {
1133 wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_0, NULL_TSSI_W);
1134 wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_1, NULL_TSSI_W);
1135 wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_0, NULL_TSSI_W);
1136 wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_1, NULL_TSSI_W);
1137 }
1138}
1139
1140static bool wlc_phy_cal_txpower_recalc_sw(struct brcms_phy *pi)
1141{
1142 return false;
1143}
1144
1145void wlc_phy_switch_radio(struct brcms_phy_pub *pih, bool on)
1146{
1147 struct brcms_phy *pi = (struct brcms_phy *) pih;
1148 (void)R_REG(&pi->regs->maccontrol);
1149
1150 if (ISNPHY(pi)) {
1151 wlc_phy_switch_radio_nphy(pi, on);
1152 } else if (ISLCNPHY(pi)) {
1153 if (on) {
1154 and_phy_reg(pi, 0x44c,
1155 ~((0x1 << 8) |
1156 (0x1 << 9) |
1157 (0x1 << 10) | (0x1 << 11) | (0x1 << 12)));
1158 and_phy_reg(pi, 0x4b0, ~((0x1 << 3) | (0x1 << 11)));
1159 and_phy_reg(pi, 0x4f9, ~(0x1 << 3));
1160 } else {
1161 and_phy_reg(pi, 0x44d,
1162 ~((0x1 << 10) |
1163 (0x1 << 11) |
1164 (0x1 << 12) | (0x1 << 13) | (0x1 << 14)));
1165 or_phy_reg(pi, 0x44c,
1166 (0x1 << 8) |
1167 (0x1 << 9) |
1168 (0x1 << 10) | (0x1 << 11) | (0x1 << 12));
1169
1170 and_phy_reg(pi, 0x4b7, ~((0x7f << 8)));
1171 and_phy_reg(pi, 0x4b1, ~((0x1 << 13)));
1172 or_phy_reg(pi, 0x4b0, (0x1 << 3) | (0x1 << 11));
1173 and_phy_reg(pi, 0x4fa, ~((0x1 << 3)));
1174 or_phy_reg(pi, 0x4f9, (0x1 << 3));
1175 }
1176 }
1177}
1178
1179u16 wlc_phy_bw_state_get(struct brcms_phy_pub *ppi)
1180{
1181 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1182
1183 return pi->bw;
1184}
1185
1186void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi, u16 bw)
1187{
1188 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1189
1190 pi->bw = bw;
1191}
1192
1193void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi, u16 newch)
1194{
1195 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1196 pi->radio_chanspec = newch;
1197
1198}
1199
1200u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi)
1201{
1202 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1203
1204 return pi->radio_chanspec;
1205}
1206
1207void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi, u16 chanspec)
1208{
1209 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1210 u16 m_cur_channel;
1211 void (*chanspec_set)(struct brcms_phy *, u16) = NULL;
1212 m_cur_channel = CHSPEC_CHANNEL(chanspec);
1213 if (CHSPEC_IS5G(chanspec))
1214 m_cur_channel |= D11_CURCHANNEL_5G;
1215 if (CHSPEC_IS40(chanspec))
1216 m_cur_channel |= D11_CURCHANNEL_40;
1217 wlapi_bmac_write_shm(pi->sh->physhim, M_CURCHANNEL, m_cur_channel);
1218
1219 chanspec_set = pi->pi_fptr.chanset;
1220 if (chanspec_set)
1221 (*chanspec_set)(pi, chanspec);
1222
1223}
1224
1225int wlc_phy_chanspec_freq2bandrange_lpssn(uint freq)
1226{
1227 int range = -1;
1228
1229 if (freq < 2500)
1230 range = WL_CHAN_FREQ_RANGE_2G;
1231 else if (freq <= 5320)
1232 range = WL_CHAN_FREQ_RANGE_5GL;
1233 else if (freq <= 5700)
1234 range = WL_CHAN_FREQ_RANGE_5GM;
1235 else
1236 range = WL_CHAN_FREQ_RANGE_5GH;
1237
1238 return range;
1239}
1240
1241int wlc_phy_chanspec_bandrange_get(struct brcms_phy *pi, u16 chanspec)
1242{
1243 int range = -1;
1244 uint channel = CHSPEC_CHANNEL(chanspec);
1245 uint freq = wlc_phy_channel2freq(channel);
1246
1247 if (ISNPHY(pi))
1248 range = wlc_phy_get_chan_freq_range_nphy(pi, channel);
1249 else if (ISLCNPHY(pi))
1250 range = wlc_phy_chanspec_freq2bandrange_lpssn(freq);
1251
1252 return range;
1253}
1254
1255void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi,
1256 bool wide_filter)
1257{
1258 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1259
1260 pi->channel_14_wide_filter = wide_filter;
1261
1262}
1263
1264int wlc_phy_channel2freq(uint channel)
1265{
1266 uint i;
1267
1268 for (i = 0; i < ARRAY_SIZE(chan_info_all); i++)
1269 if (chan_info_all[i].chan == channel)
1270 return chan_info_all[i].freq;
1271 return 0;
1272}
1273
1274void
1275wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi, uint band,
1276 struct brcms_chanvec *channels)
1277{
1278 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1279 uint i;
1280 uint channel;
1281
1282 memset(channels, 0, sizeof(struct brcms_chanvec));
1283
1284 for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
1285 channel = chan_info_all[i].chan;
1286
1287 if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
1288 && (channel <= LAST_REF5_CHANNUM))
1289 continue;
1290
1291 if ((band == BRCM_BAND_2G && channel <= CH_MAX_2G_CHANNEL) ||
1292 (band == BRCM_BAND_5G && channel > CH_MAX_2G_CHANNEL))
1293 setbit(channels->vec, channel);
1294 }
1295}
1296
1297u16 wlc_phy_chanspec_band_firstch(struct brcms_phy_pub *ppi, uint band)
1298{
1299 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1300 uint i;
1301 uint channel;
1302 u16 chspec;
1303
1304 for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
1305 channel = chan_info_all[i].chan;
1306
1307 if (ISNPHY(pi) && pi->bw == WL_CHANSPEC_BW_40) {
1308 uint j;
1309
1310 for (j = 0; j < ARRAY_SIZE(chan_info_all); j++) {
1311 if (chan_info_all[j].chan ==
1312 channel + CH_10MHZ_APART)
1313 break;
1314 }
1315
1316 if (j == ARRAY_SIZE(chan_info_all))
1317 continue;
1318
1319 channel = upper_20_sb(channel);
1320 chspec = channel | WL_CHANSPEC_BW_40 |
1321 WL_CHANSPEC_CTL_SB_LOWER;
1322 if (band == BRCM_BAND_2G)
1323 chspec |= WL_CHANSPEC_BAND_2G;
1324 else
1325 chspec |= WL_CHANSPEC_BAND_5G;
1326 } else
1327 chspec = ch20mhz_chspec(channel);
1328
1329 if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
1330 && (channel <= LAST_REF5_CHANNUM))
1331 continue;
1332
1333 if ((band == BRCM_BAND_2G && channel <= CH_MAX_2G_CHANNEL) ||
1334 (band == BRCM_BAND_5G && channel > CH_MAX_2G_CHANNEL))
1335 return chspec;
1336 }
1337
1338 return (u16) INVCHANSPEC;
1339}
1340
1341int wlc_phy_txpower_get(struct brcms_phy_pub *ppi, uint *qdbm, bool *override)
1342{
1343 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1344
1345 *qdbm = pi->tx_user_target[0];
1346 if (override != NULL)
1347 *override = pi->txpwroverride;
1348 return 0;
1349}
1350
1351void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi,
1352 struct txpwr_limits *txpwr)
1353{
1354 bool mac_enabled = false;
1355 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1356
1357 memcpy(&pi->tx_user_target[TXP_FIRST_CCK],
1358 &txpwr->cck[0], BRCMS_NUM_RATES_CCK);
1359
1360 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM],
1361 &txpwr->ofdm[0], BRCMS_NUM_RATES_OFDM);
1362 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_20_CDD],
1363 &txpwr->ofdm_cdd[0], BRCMS_NUM_RATES_OFDM);
1364
1365 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_SISO],
1366 &txpwr->ofdm_40_siso[0], BRCMS_NUM_RATES_OFDM);
1367 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_CDD],
1368 &txpwr->ofdm_40_cdd[0], BRCMS_NUM_RATES_OFDM);
1369
1370 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SISO],
1371 &txpwr->mcs_20_siso[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1372 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_CDD],
1373 &txpwr->mcs_20_cdd[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1374 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_STBC],
1375 &txpwr->mcs_20_stbc[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1376 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SDM],
1377 &txpwr->mcs_20_mimo[0], BRCMS_NUM_RATES_MCS_2_STREAM);
1378
1379 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SISO],
1380 &txpwr->mcs_40_siso[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1381 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_CDD],
1382 &txpwr->mcs_40_cdd[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1383 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_STBC],
1384 &txpwr->mcs_40_stbc[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1385 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SDM],
1386 &txpwr->mcs_40_mimo[0], BRCMS_NUM_RATES_MCS_2_STREAM);
1387
1388 if (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC)
1389 mac_enabled = true;
1390
1391 if (mac_enabled)
1392 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1393
1394 wlc_phy_txpower_recalc_target(pi);
1395 wlc_phy_cal_txpower_recalc_sw(pi);
1396
1397 if (mac_enabled)
1398 wlapi_enable_mac(pi->sh->physhim);
1399}
1400
1401int wlc_phy_txpower_set(struct brcms_phy_pub *ppi, uint qdbm, bool override)
1402{
1403 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1404 int i;
1405
1406 if (qdbm > 127)
1407 return -EINVAL;
1408
1409 for (i = 0; i < TXP_NUM_RATES; i++)
1410 pi->tx_user_target[i] = (u8) qdbm;
1411
1412 pi->txpwroverride = false;
1413
1414 if (pi->sh->up) {
1415 if (!SCAN_INPROG_PHY(pi)) {
1416 bool suspend;
1417
1418 suspend = (0 == (R_REG(&pi->regs->maccontrol) &
1419 MCTL_EN_MAC));
1420
1421 if (!suspend)
1422 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1423
1424 wlc_phy_txpower_recalc_target(pi);
1425 wlc_phy_cal_txpower_recalc_sw(pi);
1426
1427 if (!suspend)
1428 wlapi_enable_mac(pi->sh->physhim);
1429 }
1430 }
1431 return 0;
1432}
1433
1434void
1435wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi, uint channel, u8 *min_pwr,
1436 u8 *max_pwr, int txp_rate_idx)
1437{
1438 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1439 uint i;
1440
1441 *min_pwr = pi->min_txpower * BRCMS_TXPWR_DB_FACTOR;
1442
1443 if (ISNPHY(pi)) {
1444 if (txp_rate_idx < 0)
1445 txp_rate_idx = TXP_FIRST_CCK;
1446 wlc_phy_txpower_sromlimit_get_nphy(pi, channel, max_pwr,
1447 (u8) txp_rate_idx);
1448
1449 } else if ((channel <= CH_MAX_2G_CHANNEL)) {
1450 if (txp_rate_idx < 0)
1451 txp_rate_idx = TXP_FIRST_CCK;
1452 *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
1453 } else {
1454
1455 *max_pwr = BRCMS_TXPWR_MAX;
1456
1457 if (txp_rate_idx < 0)
1458 txp_rate_idx = TXP_FIRST_OFDM;
1459
1460 for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
1461 if (channel == chan_info_all[i].chan)
1462 break;
1463 }
1464
1465 if (pi->hwtxpwr) {
1466 *max_pwr = pi->hwtxpwr[i];
1467 } else {
1468
1469 if ((i >= FIRST_MID_5G_CHAN) && (i <= LAST_MID_5G_CHAN))
1470 *max_pwr =
1471 pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
1472 if ((i >= FIRST_HIGH_5G_CHAN)
1473 && (i <= LAST_HIGH_5G_CHAN))
1474 *max_pwr =
1475 pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
1476 if ((i >= FIRST_LOW_5G_CHAN) && (i <= LAST_LOW_5G_CHAN))
1477 *max_pwr =
1478 pi->tx_srom_max_rate_5g_low[txp_rate_idx];
1479 }
1480 }
1481}
1482
1483void
1484wlc_phy_txpower_sromlimit_max_get(struct brcms_phy_pub *ppi, uint chan,
1485 u8 *max_txpwr, u8 *min_txpwr)
1486{
1487 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1488 u8 tx_pwr_max = 0;
1489 u8 tx_pwr_min = 255;
1490 u8 max_num_rate;
1491 u8 maxtxpwr, mintxpwr, rate, pactrl;
1492
1493 pactrl = 0;
1494
1495 max_num_rate = ISNPHY(pi) ? TXP_NUM_RATES :
1496 ISLCNPHY(pi) ? (TXP_LAST_SISO_MCS_20 +
1497 1) : (TXP_LAST_OFDM + 1);
1498
1499 for (rate = 0; rate < max_num_rate; rate++) {
1500
1501 wlc_phy_txpower_sromlimit(ppi, chan, &mintxpwr, &maxtxpwr,
1502 rate);
1503
1504 maxtxpwr = (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
1505
1506 maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
1507
1508 tx_pwr_max = max(tx_pwr_max, maxtxpwr);
1509 tx_pwr_min = min(tx_pwr_min, maxtxpwr);
1510 }
1511 *max_txpwr = tx_pwr_max;
1512 *min_txpwr = tx_pwr_min;
1513}
1514
1515void
1516wlc_phy_txpower_boardlimit_band(struct brcms_phy_pub *ppi, uint bandunit,
1517 s32 *max_pwr, s32 *min_pwr, u32 *step_pwr)
1518{
1519 return;
1520}
1521
1522u8 wlc_phy_txpower_get_target_min(struct brcms_phy_pub *ppi)
1523{
1524 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1525
1526 return pi->tx_power_min;
1527}
1528
1529u8 wlc_phy_txpower_get_target_max(struct brcms_phy_pub *ppi)
1530{
1531 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1532
1533 return pi->tx_power_max;
1534}
1535
1536static s8 wlc_phy_env_measure_vbat(struct brcms_phy *pi)
1537{
1538 if (ISLCNPHY(pi))
1539 return wlc_lcnphy_vbatsense(pi, 0);
1540 else
1541 return 0;
1542}
1543
1544static s8 wlc_phy_env_measure_temperature(struct brcms_phy *pi)
1545{
1546 if (ISLCNPHY(pi))
1547 return wlc_lcnphy_tempsense_degree(pi, 0);
1548 else
1549 return 0;
1550}
1551
1552static void wlc_phy_upd_env_txpwr_rate_limits(struct brcms_phy *pi, u32 band)
1553{
1554 u8 i;
1555 s8 temp, vbat;
1556
1557 for (i = 0; i < TXP_NUM_RATES; i++)
1558 pi->txpwr_env_limit[i] = BRCMS_TXPWR_MAX;
1559
1560 vbat = wlc_phy_env_measure_vbat(pi);
1561 temp = wlc_phy_env_measure_temperature(pi);
1562
1563}
1564
1565static s8
1566wlc_user_txpwr_antport_to_rfport(struct brcms_phy *pi, uint chan, u32 band,
1567 u8 rate)
1568{
1569 s8 offset = 0;
1570
1571 if (!pi->user_txpwr_at_rfport)
1572 return offset;
1573 return offset;
1574}
1575
1576void wlc_phy_txpower_recalc_target(struct brcms_phy *pi)
1577{
1578 u8 maxtxpwr, mintxpwr, rate, pactrl;
1579 uint target_chan;
1580 u8 tx_pwr_target[TXP_NUM_RATES];
1581 u8 tx_pwr_max = 0;
1582 u8 tx_pwr_min = 255;
1583 u8 tx_pwr_max_rate_ind = 0;
1584 u8 max_num_rate;
1585 u8 start_rate = 0;
1586 u16 chspec;
1587 u32 band = CHSPEC2BAND(pi->radio_chanspec);
1588 void (*txpwr_recalc_fn)(struct brcms_phy *) = NULL;
1589
1590 chspec = pi->radio_chanspec;
1591 if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_NONE)
1592 target_chan = CHSPEC_CHANNEL(chspec);
1593 else if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_UPPER)
1594 target_chan = upper_20_sb(CHSPEC_CHANNEL(chspec));
1595 else
1596 target_chan = lower_20_sb(CHSPEC_CHANNEL(chspec));
1597
1598 pactrl = 0;
1599 if (ISLCNPHY(pi)) {
1600 u32 offset_mcs, i;
1601
1602 if (CHSPEC_IS40(pi->radio_chanspec)) {
1603 offset_mcs = pi->mcs40_po;
1604 for (i = TXP_FIRST_SISO_MCS_20;
1605 i <= TXP_LAST_SISO_MCS_20; i++) {
1606 pi->tx_srom_max_rate_2g[i - 8] =
1607 pi->tx_srom_max_2g -
1608 ((offset_mcs & 0xf) * 2);
1609 offset_mcs >>= 4;
1610 }
1611 } else {
1612 offset_mcs = pi->mcs20_po;
1613 for (i = TXP_FIRST_SISO_MCS_20;
1614 i <= TXP_LAST_SISO_MCS_20; i++) {
1615 pi->tx_srom_max_rate_2g[i - 8] =
1616 pi->tx_srom_max_2g -
1617 ((offset_mcs & 0xf) * 2);
1618 offset_mcs >>= 4;
1619 }
1620 }
1621 }
1622
1623 max_num_rate = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
1624 ((ISLCNPHY(pi)) ?
1625 (TXP_LAST_SISO_MCS_20 + 1) : (TXP_LAST_OFDM + 1)));
1626
1627 wlc_phy_upd_env_txpwr_rate_limits(pi, band);
1628
1629 for (rate = start_rate; rate < max_num_rate; rate++) {
1630
1631 tx_pwr_target[rate] = pi->tx_user_target[rate];
1632
1633 if (pi->user_txpwr_at_rfport)
1634 tx_pwr_target[rate] +=
1635 wlc_user_txpwr_antport_to_rfport(pi,
1636 target_chan,
1637 band,
1638 rate);
1639
1640 wlc_phy_txpower_sromlimit((struct brcms_phy_pub *) pi,
1641 target_chan,
1642 &mintxpwr, &maxtxpwr, rate);
1643
1644 maxtxpwr = min(maxtxpwr, pi->txpwr_limit[rate]);
1645
1646 maxtxpwr = (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
1647
1648 maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
1649
1650 maxtxpwr = min(maxtxpwr, tx_pwr_target[rate]);
1651
1652 if (pi->txpwr_percent <= 100)
1653 maxtxpwr = (maxtxpwr * pi->txpwr_percent) / 100;
1654
1655 tx_pwr_target[rate] = max(maxtxpwr, mintxpwr);
1656
1657 tx_pwr_target[rate] =
1658 min(tx_pwr_target[rate], pi->txpwr_env_limit[rate]);
1659
1660 if (tx_pwr_target[rate] > tx_pwr_max)
1661 tx_pwr_max_rate_ind = rate;
1662
1663 tx_pwr_max = max(tx_pwr_max, tx_pwr_target[rate]);
1664 tx_pwr_min = min(tx_pwr_min, tx_pwr_target[rate]);
1665 }
1666
1667 memset(pi->tx_power_offset, 0, sizeof(pi->tx_power_offset));
1668 pi->tx_power_max = tx_pwr_max;
1669 pi->tx_power_min = tx_pwr_min;
1670 pi->tx_power_max_rate_ind = tx_pwr_max_rate_ind;
1671 for (rate = 0; rate < max_num_rate; rate++) {
1672
1673 pi->tx_power_target[rate] = tx_pwr_target[rate];
1674
1675 if (!pi->hwpwrctrl || ISNPHY(pi))
1676 pi->tx_power_offset[rate] =
1677 pi->tx_power_max - pi->tx_power_target[rate];
1678 else
1679 pi->tx_power_offset[rate] =
1680 pi->tx_power_target[rate] - pi->tx_power_min;
1681 }
1682
1683 txpwr_recalc_fn = pi->pi_fptr.txpwrrecalc;
1684 if (txpwr_recalc_fn)
1685 (*txpwr_recalc_fn)(pi);
1686}
1687
1688static void
1689wlc_phy_txpower_reg_limit_calc(struct brcms_phy *pi, struct txpwr_limits *txpwr,
1690 u16 chanspec)
1691{
1692 u8 tmp_txpwr_limit[2 * BRCMS_NUM_RATES_OFDM];
1693 u8 *txpwr_ptr1 = NULL, *txpwr_ptr2 = NULL;
1694 int rate_start_index = 0, rate1, rate2, k;
1695
1696 for (rate1 = WL_TX_POWER_CCK_FIRST, rate2 = 0;
1697 rate2 < WL_TX_POWER_CCK_NUM; rate1++, rate2++)
1698 pi->txpwr_limit[rate1] = txpwr->cck[rate2];
1699
1700 for (rate1 = WL_TX_POWER_OFDM_FIRST, rate2 = 0;
1701 rate2 < WL_TX_POWER_OFDM_NUM; rate1++, rate2++)
1702 pi->txpwr_limit[rate1] = txpwr->ofdm[rate2];
1703
1704 if (ISNPHY(pi)) {
1705
1706 for (k = 0; k < 4; k++) {
1707 switch (k) {
1708 case 0:
1709
1710 txpwr_ptr1 = txpwr->mcs_20_siso;
1711 txpwr_ptr2 = txpwr->ofdm;
1712 rate_start_index = WL_TX_POWER_OFDM_FIRST;
1713 break;
1714 case 1:
1715
1716 txpwr_ptr1 = txpwr->mcs_20_cdd;
1717 txpwr_ptr2 = txpwr->ofdm_cdd;
1718 rate_start_index = WL_TX_POWER_OFDM20_CDD_FIRST;
1719 break;
1720 case 2:
1721
1722 txpwr_ptr1 = txpwr->mcs_40_siso;
1723 txpwr_ptr2 = txpwr->ofdm_40_siso;
1724 rate_start_index =
1725 WL_TX_POWER_OFDM40_SISO_FIRST;
1726 break;
1727 case 3:
1728
1729 txpwr_ptr1 = txpwr->mcs_40_cdd;
1730 txpwr_ptr2 = txpwr->ofdm_40_cdd;
1731 rate_start_index = WL_TX_POWER_OFDM40_CDD_FIRST;
1732 break;
1733 }
1734
1735 for (rate2 = 0; rate2 < BRCMS_NUM_RATES_OFDM;
1736 rate2++) {
1737 tmp_txpwr_limit[rate2] = 0;
1738 tmp_txpwr_limit[BRCMS_NUM_RATES_OFDM + rate2] =
1739 txpwr_ptr1[rate2];
1740 }
1741 wlc_phy_mcs_to_ofdm_powers_nphy(
1742 tmp_txpwr_limit, 0,
1743 BRCMS_NUM_RATES_OFDM -
1744 1, BRCMS_NUM_RATES_OFDM);
1745 for (rate1 = rate_start_index, rate2 = 0;
1746 rate2 < BRCMS_NUM_RATES_OFDM; rate1++, rate2++)
1747 pi->txpwr_limit[rate1] =
1748 min(txpwr_ptr2[rate2],
1749 tmp_txpwr_limit[rate2]);
1750 }
1751
1752 for (k = 0; k < 4; k++) {
1753 switch (k) {
1754 case 0:
1755
1756 txpwr_ptr1 = txpwr->ofdm;
1757 txpwr_ptr2 = txpwr->mcs_20_siso;
1758 rate_start_index = WL_TX_POWER_MCS20_SISO_FIRST;
1759 break;
1760 case 1:
1761
1762 txpwr_ptr1 = txpwr->ofdm_cdd;
1763 txpwr_ptr2 = txpwr->mcs_20_cdd;
1764 rate_start_index = WL_TX_POWER_MCS20_CDD_FIRST;
1765 break;
1766 case 2:
1767
1768 txpwr_ptr1 = txpwr->ofdm_40_siso;
1769 txpwr_ptr2 = txpwr->mcs_40_siso;
1770 rate_start_index = WL_TX_POWER_MCS40_SISO_FIRST;
1771 break;
1772 case 3:
1773
1774 txpwr_ptr1 = txpwr->ofdm_40_cdd;
1775 txpwr_ptr2 = txpwr->mcs_40_cdd;
1776 rate_start_index = WL_TX_POWER_MCS40_CDD_FIRST;
1777 break;
1778 }
1779 for (rate2 = 0; rate2 < BRCMS_NUM_RATES_OFDM;
1780 rate2++) {
1781 tmp_txpwr_limit[rate2] = 0;
1782 tmp_txpwr_limit[BRCMS_NUM_RATES_OFDM + rate2] =
1783 txpwr_ptr1[rate2];
1784 }
1785 wlc_phy_ofdm_to_mcs_powers_nphy(
1786 tmp_txpwr_limit, 0,
1787 BRCMS_NUM_RATES_OFDM -
1788 1, BRCMS_NUM_RATES_OFDM);
1789 for (rate1 = rate_start_index, rate2 = 0;
1790 rate2 < BRCMS_NUM_RATES_MCS_1_STREAM;
1791 rate1++, rate2++)
1792 pi->txpwr_limit[rate1] =
1793 min(txpwr_ptr2[rate2],
1794 tmp_txpwr_limit[rate2]);
1795 }
1796
1797 for (k = 0; k < 2; k++) {
1798 switch (k) {
1799 case 0:
1800
1801 rate_start_index = WL_TX_POWER_MCS20_STBC_FIRST;
1802 txpwr_ptr1 = txpwr->mcs_20_stbc;
1803 break;
1804 case 1:
1805
1806 rate_start_index = WL_TX_POWER_MCS40_STBC_FIRST;
1807 txpwr_ptr1 = txpwr->mcs_40_stbc;
1808 break;
1809 }
1810 for (rate1 = rate_start_index, rate2 = 0;
1811 rate2 < BRCMS_NUM_RATES_MCS_1_STREAM;
1812 rate1++, rate2++)
1813 pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
1814 }
1815
1816 for (k = 0; k < 2; k++) {
1817 switch (k) {
1818 case 0:
1819
1820 rate_start_index = WL_TX_POWER_MCS20_SDM_FIRST;
1821 txpwr_ptr1 = txpwr->mcs_20_mimo;
1822 break;
1823 case 1:
1824
1825 rate_start_index = WL_TX_POWER_MCS40_SDM_FIRST;
1826 txpwr_ptr1 = txpwr->mcs_40_mimo;
1827 break;
1828 }
1829 for (rate1 = rate_start_index, rate2 = 0;
1830 rate2 < BRCMS_NUM_RATES_MCS_2_STREAM;
1831 rate1++, rate2++)
1832 pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
1833 }
1834
1835 pi->txpwr_limit[WL_TX_POWER_MCS_32] = txpwr->mcs32;
1836
1837 pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST] =
1838 min(pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST],
1839 pi->txpwr_limit[WL_TX_POWER_MCS_32]);
1840 pi->txpwr_limit[WL_TX_POWER_MCS_32] =
1841 pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST];
1842 }
1843}
1844
1845void wlc_phy_txpwr_percent_set(struct brcms_phy_pub *ppi, u8 txpwr_percent)
1846{
1847 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1848
1849 pi->txpwr_percent = txpwr_percent;
1850}
1851
1852void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi, u32 machwcap)
1853{
1854 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1855
1856 pi->sh->machwcap = machwcap;
1857}
1858
1859void wlc_phy_runbist_config(struct brcms_phy_pub *ppi, bool start_end)
1860{
1861 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1862 u16 rxc;
1863 rxc = 0;
1864
1865 if (start_end == ON) {
1866 if (!ISNPHY(pi))
1867 return;
1868
1869 if (NREV_IS(pi->pubpi.phy_rev, 3)
1870 || NREV_IS(pi->pubpi.phy_rev, 4)) {
1871 W_REG(&pi->regs->phyregaddr, 0xa0);
1872 (void)R_REG(&pi->regs->phyregaddr);
1873 rxc = R_REG(&pi->regs->phyregdata);
1874 W_REG(&pi->regs->phyregdata,
1875 (0x1 << 15) | rxc);
1876 }
1877 } else {
1878 if (NREV_IS(pi->pubpi.phy_rev, 3)
1879 || NREV_IS(pi->pubpi.phy_rev, 4)) {
1880 W_REG(&pi->regs->phyregaddr, 0xa0);
1881 (void)R_REG(&pi->regs->phyregaddr);
1882 W_REG(&pi->regs->phyregdata, rxc);
1883 }
1884
1885 wlc_phy_por_inform(ppi);
1886 }
1887}
1888
1889void
1890wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi, struct txpwr_limits *txpwr,
1891 u16 chanspec)
1892{
1893 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1894
1895 wlc_phy_txpower_reg_limit_calc(pi, txpwr, chanspec);
1896
1897 if (ISLCNPHY(pi)) {
1898 int i, j;
1899 for (i = TXP_FIRST_OFDM_20_CDD, j = 0;
1900 j < BRCMS_NUM_RATES_MCS_1_STREAM; i++, j++) {
1901 if (txpwr->mcs_20_siso[j])
1902 pi->txpwr_limit[i] = txpwr->mcs_20_siso[j];
1903 else
1904 pi->txpwr_limit[i] = txpwr->ofdm[j];
1905 }
1906 }
1907
1908 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1909
1910 wlc_phy_txpower_recalc_target(pi);
1911 wlc_phy_cal_txpower_recalc_sw(pi);
1912 wlapi_enable_mac(pi->sh->physhim);
1913}
1914
1915void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih, bool war)
1916{
1917 struct brcms_phy *pi = (struct brcms_phy *) pih;
1918
1919 pi->ofdm_rateset_war = war;
1920}
1921
1922void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih, bool bf_preempt)
1923{
1924 struct brcms_phy *pi = (struct brcms_phy *) pih;
1925
1926 pi->bf_preempt_4306 = bf_preempt;
1927}
1928
1929void wlc_phy_txpower_update_shm(struct brcms_phy *pi)
1930{
1931 int j;
1932 if (ISNPHY(pi))
1933 return;
1934
1935 if (!pi->sh->clk)
1936 return;
1937
1938 if (pi->hwpwrctrl) {
1939 u16 offset;
1940
1941 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_MAX, 63);
1942 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_N,
1943 1 << NUM_TSSI_FRAMES);
1944
1945 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_TARGET,
1946 pi->tx_power_min << NUM_TSSI_FRAMES);
1947
1948 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_CUR,
1949 pi->hwpwr_txcur);
1950
1951 for (j = TXP_FIRST_OFDM; j <= TXP_LAST_OFDM; j++) {
1952 const u8 ucode_ofdm_rates[] = {
1953 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c
1954 };
1955 offset = wlapi_bmac_rate_shm_offset(
1956 pi->sh->physhim,
1957 ucode_ofdm_rates[j - TXP_FIRST_OFDM]);
1958 wlapi_bmac_write_shm(pi->sh->physhim, offset + 6,
1959 pi->tx_power_offset[j]);
1960 wlapi_bmac_write_shm(pi->sh->physhim, offset + 14,
1961 -(pi->tx_power_offset[j] / 2));
1962 }
1963
1964 wlapi_bmac_mhf(pi->sh->physhim, MHF2, MHF2_HWPWRCTL,
1965 MHF2_HWPWRCTL, BRCM_BAND_ALL);
1966 } else {
1967 int i;
1968
1969 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++)
1970 pi->tx_power_offset[i] =
1971 (u8) roundup(pi->tx_power_offset[i], 8);
1972 wlapi_bmac_write_shm(pi->sh->physhim, M_OFDM_OFFSET,
1973 (u16)
1974 ((pi->tx_power_offset[TXP_FIRST_OFDM]
1975 + 7) >> 3));
1976 }
1977}
1978
1979bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi)
1980{
1981 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1982
1983 if (ISNPHY(pi))
1984 return pi->nphy_txpwrctrl;
1985 else
1986 return pi->hwpwrctrl;
1987}
1988
1989void wlc_phy_txpower_hw_ctrl_set(struct brcms_phy_pub *ppi, bool hwpwrctrl)
1990{
1991 struct brcms_phy *pi = (struct brcms_phy *) ppi;
1992 bool suspend;
1993
1994 if (!pi->hwpwrctrl_capable)
1995 return;
1996
1997 pi->hwpwrctrl = hwpwrctrl;
1998 pi->nphy_txpwrctrl = hwpwrctrl;
1999 pi->txpwrctrl = hwpwrctrl;
2000
2001 if (ISNPHY(pi)) {
2002 suspend = (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
2003 if (!suspend)
2004 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2005
2006 wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
2007 if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF)
2008 wlc_phy_txpwr_fixpower_nphy(pi);
2009 else
2010 mod_phy_reg(pi, 0x1e7, (0x7f << 0),
2011 pi->saved_txpwr_idx);
2012
2013 if (!suspend)
2014 wlapi_enable_mac(pi->sh->physhim);
2015 }
2016}
2017
2018void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi)
2019{
2020
2021 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
2022 pi->ipa2g_on = (pi->srom_fem2g.extpagain == 2);
2023 pi->ipa5g_on = (pi->srom_fem5g.extpagain == 2);
2024 } else {
2025 pi->ipa2g_on = false;
2026 pi->ipa5g_on = false;
2027 }
2028}
2029
2030static u32 wlc_phy_txpower_est_power_nphy(struct brcms_phy *pi)
2031{
2032 s16 tx0_status, tx1_status;
2033 u16 estPower1, estPower2;
2034 u8 pwr0, pwr1, adj_pwr0, adj_pwr1;
2035 u32 est_pwr;
2036
2037 estPower1 = read_phy_reg(pi, 0x118);
2038 estPower2 = read_phy_reg(pi, 0x119);
2039
2040 if ((estPower1 & (0x1 << 8)) == (0x1 << 8))
2041 pwr0 = (u8) (estPower1 & (0xff << 0)) >> 0;
2042 else
2043 pwr0 = 0x80;
2044
2045 if ((estPower2 & (0x1 << 8)) == (0x1 << 8))
2046 pwr1 = (u8) (estPower2 & (0xff << 0)) >> 0;
2047 else
2048 pwr1 = 0x80;
2049
2050 tx0_status = read_phy_reg(pi, 0x1ed);
2051 tx1_status = read_phy_reg(pi, 0x1ee);
2052
2053 if ((tx0_status & (0x1 << 15)) == (0x1 << 15))
2054 adj_pwr0 = (u8) (tx0_status & (0xff << 0)) >> 0;
2055 else
2056 adj_pwr0 = 0x80;
2057 if ((tx1_status & (0x1 << 15)) == (0x1 << 15))
2058 adj_pwr1 = (u8) (tx1_status & (0xff << 0)) >> 0;
2059 else
2060 adj_pwr1 = 0x80;
2061
2062 est_pwr = (u32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) |
2063 adj_pwr1);
2064
2065 return est_pwr;
2066}
2067
2068void
2069wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi, struct tx_power *power,
2070 uint channel)
2071{
2072 struct brcms_phy *pi = (struct brcms_phy *) ppi;
2073 uint rate, num_rates;
2074 u8 min_pwr, max_pwr;
2075
2076#if WL_TX_POWER_RATES != TXP_NUM_RATES
2077#error "struct tx_power out of sync with this fn"
2078#endif
2079
2080 if (ISNPHY(pi)) {
2081 power->rf_cores = 2;
2082 power->flags |= (WL_TX_POWER_F_MIMO);
2083 if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
2084 power->flags |=
2085 (WL_TX_POWER_F_ENABLED | WL_TX_POWER_F_HW);
2086 } else if (ISLCNPHY(pi)) {
2087 power->rf_cores = 1;
2088 power->flags |= (WL_TX_POWER_F_SISO);
2089 if (pi->radiopwr_override == RADIOPWR_OVERRIDE_DEF)
2090 power->flags |= WL_TX_POWER_F_ENABLED;
2091 if (pi->hwpwrctrl)
2092 power->flags |= WL_TX_POWER_F_HW;
2093 }
2094
2095 num_rates = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
2096 ((ISLCNPHY(pi)) ?
2097 (TXP_LAST_OFDM_20_CDD + 1) : (TXP_LAST_OFDM + 1)));
2098
2099 for (rate = 0; rate < num_rates; rate++) {
2100 power->user_limit[rate] = pi->tx_user_target[rate];
2101 wlc_phy_txpower_sromlimit(ppi, channel, &min_pwr, &max_pwr,
2102 rate);
2103 power->board_limit[rate] = (u8) max_pwr;
2104 power->target[rate] = pi->tx_power_target[rate];
2105 }
2106
2107 if (ISNPHY(pi)) {
2108 u32 est_pout;
2109
2110 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2111 wlc_phyreg_enter((struct brcms_phy_pub *) pi);
2112 est_pout = wlc_phy_txpower_est_power_nphy(pi);
2113 wlc_phyreg_exit((struct brcms_phy_pub *) pi);
2114 wlapi_enable_mac(pi->sh->physhim);
2115
2116 power->est_Pout[0] = (est_pout >> 8) & 0xff;
2117 power->est_Pout[1] = est_pout & 0xff;
2118
2119 power->est_Pout_act[0] = est_pout >> 24;
2120 power->est_Pout_act[1] = (est_pout >> 16) & 0xff;
2121
2122 if (power->est_Pout[0] == 0x80)
2123 power->est_Pout[0] = 0;
2124 if (power->est_Pout[1] == 0x80)
2125 power->est_Pout[1] = 0;
2126
2127 if (power->est_Pout_act[0] == 0x80)
2128 power->est_Pout_act[0] = 0;
2129 if (power->est_Pout_act[1] == 0x80)
2130 power->est_Pout_act[1] = 0;
2131
2132 power->est_Pout_cck = 0;
2133
2134 power->tx_power_max[0] = pi->tx_power_max;
2135 power->tx_power_max[1] = pi->tx_power_max;
2136
2137 power->tx_power_max_rate_ind[0] = pi->tx_power_max_rate_ind;
2138 power->tx_power_max_rate_ind[1] = pi->tx_power_max_rate_ind;
2139 } else if (pi->hwpwrctrl && pi->sh->up) {
2140
2141 wlc_phyreg_enter(ppi);
2142 if (ISLCNPHY(pi)) {
2143
2144 power->tx_power_max[0] = pi->tx_power_max;
2145 power->tx_power_max[1] = pi->tx_power_max;
2146
2147 power->tx_power_max_rate_ind[0] =
2148 pi->tx_power_max_rate_ind;
2149 power->tx_power_max_rate_ind[1] =
2150 pi->tx_power_max_rate_ind;
2151
2152 if (wlc_phy_tpc_isenabled_lcnphy(pi))
2153 power->flags |=
2154 (WL_TX_POWER_F_HW |
2155 WL_TX_POWER_F_ENABLED);
2156 else
2157 power->flags &=
2158 ~(WL_TX_POWER_F_HW |
2159 WL_TX_POWER_F_ENABLED);
2160
2161 wlc_lcnphy_get_tssi(pi, (s8 *) &power->est_Pout[0],
2162 (s8 *) &power->est_Pout_cck);
2163 }
2164 wlc_phyreg_exit(ppi);
2165 }
2166}
2167
2168void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi, u8 antsel_type)
2169{
2170 struct brcms_phy *pi = (struct brcms_phy *) ppi;
2171
2172 pi->antsel_type = antsel_type;
2173}
2174
2175bool wlc_phy_test_ison(struct brcms_phy_pub *ppi)
2176{
2177 struct brcms_phy *pi = (struct brcms_phy *) ppi;
2178
2179 return pi->phytest_on;
2180}
2181
2182void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val)
2183{
2184 struct brcms_phy *pi = (struct brcms_phy *) ppi;
2185 bool suspend;
2186
2187 pi->sh->rx_antdiv = val;
2188
2189 if (!(ISNPHY(pi) && D11REV_IS(pi->sh->corerev, 16))) {
2190 if (val > ANT_RX_DIV_FORCE_1)
2191 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV,
2192 MHF1_ANTDIV, BRCM_BAND_ALL);
2193 else
2194 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV, 0,
2195 BRCM_BAND_ALL);
2196 }
2197
2198 if (ISNPHY(pi))
2199 return;
2200
2201 if (!pi->sh->clk)
2202 return;
2203
2204 suspend = (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
2205 if (!suspend)
2206 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2207
2208 if (ISLCNPHY(pi)) {
2209 if (val > ANT_RX_DIV_FORCE_1) {
2210 mod_phy_reg(pi, 0x410, (0x1 << 1), 0x01 << 1);
2211 mod_phy_reg(pi, 0x410,
2212 (0x1 << 0),
2213 ((ANT_RX_DIV_START_1 == val) ? 1 : 0) << 0);
2214 } else {
2215 mod_phy_reg(pi, 0x410, (0x1 << 1), 0x00 << 1);
2216 mod_phy_reg(pi, 0x410, (0x1 << 0), (u16) val << 0);
2217 }
2218 }
2219
2220 if (!suspend)
2221 wlapi_enable_mac(pi->sh->physhim);
2222
2223 return;
2224}
2225
2226static bool
2227wlc_phy_noise_calc_phy(struct brcms_phy *pi, u32 *cmplx_pwr, s8 *pwr_ant)
2228{
2229 s8 cmplx_pwr_dbm[PHY_CORE_MAX];
2230 u8 i;
2231
2232 memset((u8 *) cmplx_pwr_dbm, 0, sizeof(cmplx_pwr_dbm));
2233 wlc_phy_compute_dB(cmplx_pwr, cmplx_pwr_dbm, pi->pubpi.phy_corenum);
2234
2235 for (i = 0; i < pi->pubpi.phy_corenum; i++) {
2236 if (NREV_GE(pi->pubpi.phy_rev, 3))
2237 cmplx_pwr_dbm[i] += (s8) PHY_NOISE_OFFSETFACT_4322;
2238 else
2239
2240 cmplx_pwr_dbm[i] += (s8) (16 - (15) * 3 - 70);
2241 }
2242
2243 for (i = 0; i < pi->pubpi.phy_corenum; i++) {
2244 pi->nphy_noise_win[i][pi->nphy_noise_index] = cmplx_pwr_dbm[i];
2245 pwr_ant[i] = cmplx_pwr_dbm[i];
2246 }
2247 pi->nphy_noise_index =
2248 MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
2249 return true;
2250}
2251
2252static void wlc_phy_noise_cb(struct brcms_phy *pi, u8 channel, s8 noise_dbm)
2253{
2254 if (!pi->phynoise_state)
2255 return;
2256
2257 if (pi->phynoise_state & PHY_NOISE_STATE_MON) {
2258 if (pi->phynoise_chan_watchdog == channel) {
2259 pi->sh->phy_noise_window[pi->sh->phy_noise_index] =
2260 noise_dbm;
2261 pi->sh->phy_noise_index =
2262 MODINC(pi->sh->phy_noise_index, MA_WINDOW_SZ);
2263 }
2264 pi->phynoise_state &= ~PHY_NOISE_STATE_MON;
2265 }
2266
2267 if (pi->phynoise_state & PHY_NOISE_STATE_EXTERNAL)
2268 pi->phynoise_state &= ~PHY_NOISE_STATE_EXTERNAL;
2269
2270}
2271
2272static s8 wlc_phy_noise_read_shmem(struct brcms_phy *pi)
2273{
2274 u32 cmplx_pwr[PHY_CORE_MAX];
2275 s8 noise_dbm_ant[PHY_CORE_MAX];
2276 u16 lo, hi;
2277 u32 cmplx_pwr_tot = 0;
2278 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2279 u8 idx, core;
2280
2281 memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
2282 memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
2283
2284 for (idx = 0, core = 0; core < pi->pubpi.phy_corenum; idx += 2,
2285 core++) {
2286 lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP(idx));
2287 hi = wlapi_bmac_read_shm(pi->sh->physhim,
2288 M_PWRIND_MAP(idx + 1));
2289 cmplx_pwr[core] = (hi << 16) + lo;
2290 cmplx_pwr_tot += cmplx_pwr[core];
2291 if (cmplx_pwr[core] == 0)
2292 noise_dbm_ant[core] = PHY_NOISE_FIXED_VAL_NPHY;
2293 else
2294 cmplx_pwr[core] >>= PHY_NOISE_SAMPLE_LOG_NUM_UCODE;
2295 }
2296
2297 if (cmplx_pwr_tot != 0)
2298 wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
2299
2300 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
2301 pi->nphy_noise_win[core][pi->nphy_noise_index] =
2302 noise_dbm_ant[core];
2303
2304 if (noise_dbm_ant[core] > noise_dbm)
2305 noise_dbm = noise_dbm_ant[core];
2306 }
2307 pi->nphy_noise_index =
2308 MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
2309
2310 return noise_dbm;
2311
2312}
2313
2314void wlc_phy_noise_sample_intr(struct brcms_phy_pub *pih)
2315{
2316 struct brcms_phy *pi = (struct brcms_phy *) pih;
2317 u16 jssi_aux;
2318 u8 channel = 0;
2319 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2320
2321 if (ISLCNPHY(pi)) {
2322 u32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1;
2323 u16 lo, hi;
2324 s32 pwr_offset_dB, gain_dB;
2325 u16 status_0, status_1;
2326
2327 jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
2328 channel = jssi_aux & D11_CURCHANNEL_MAX;
2329
2330 lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP0);
2331 hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP1);
2332 cmplx_pwr0 = (hi << 16) + lo;
2333
2334 lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP2);
2335 hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP3);
2336 cmplx_pwr1 = (hi << 16) + lo;
2337 cmplx_pwr = (cmplx_pwr0 + cmplx_pwr1) >> 6;
2338
2339 status_0 = 0x44;
2340 status_1 = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_0);
2341 if ((cmplx_pwr > 0 && cmplx_pwr < 500)
2342 && ((status_1 & 0xc000) == 0x4000)) {
2343
2344 wlc_phy_compute_dB(&cmplx_pwr, &noise_dbm,
2345 pi->pubpi.phy_corenum);
2346 pwr_offset_dB = (read_phy_reg(pi, 0x434) & 0xFF);
2347 if (pwr_offset_dB > 127)
2348 pwr_offset_dB -= 256;
2349
2350 noise_dbm += (s8) (pwr_offset_dB - 30);
2351
2352 gain_dB = (status_0 & 0x1ff);
2353 noise_dbm -= (s8) (gain_dB);
2354 } else {
2355 noise_dbm = PHY_NOISE_FIXED_VAL_LCNPHY;
2356 }
2357 } else if (ISNPHY(pi)) {
2358
2359 jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
2360 channel = jssi_aux & D11_CURCHANNEL_MAX;
2361
2362 noise_dbm = wlc_phy_noise_read_shmem(pi);
2363 }
2364
2365 wlc_phy_noise_cb(pi, channel, noise_dbm);
2366
2367}
2368
2369static void
2370wlc_phy_noise_sample_request(struct brcms_phy_pub *pih, u8 reason, u8 ch)
2371{
2372 struct brcms_phy *pi = (struct brcms_phy *) pih;
2373 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2374 bool sampling_in_progress = (pi->phynoise_state != 0);
2375 bool wait_for_intr = true;
2376
2377 switch (reason) {
2378 case PHY_NOISE_SAMPLE_MON:
2379 pi->phynoise_chan_watchdog = ch;
2380 pi->phynoise_state |= PHY_NOISE_STATE_MON;
2381 break;
2382
2383 case PHY_NOISE_SAMPLE_EXTERNAL:
2384 pi->phynoise_state |= PHY_NOISE_STATE_EXTERNAL;
2385 break;
2386
2387 default:
2388 break;
2389 }
2390
2391 if (sampling_in_progress)
2392 return;
2393
2394 pi->phynoise_now = pi->sh->now;
2395
2396 if (pi->phy_fixed_noise) {
2397 if (ISNPHY(pi)) {
2398 pi->nphy_noise_win[WL_ANT_IDX_1][pi->nphy_noise_index] =
2399 PHY_NOISE_FIXED_VAL_NPHY;
2400 pi->nphy_noise_win[WL_ANT_IDX_2][pi->nphy_noise_index] =
2401 PHY_NOISE_FIXED_VAL_NPHY;
2402 pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
2403 PHY_NOISE_WINDOW_SZ);
2404 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2405 } else {
2406 noise_dbm = PHY_NOISE_FIXED_VAL;
2407 }
2408
2409 wait_for_intr = false;
2410 goto done;
2411 }
2412
2413 if (ISLCNPHY(pi)) {
2414 if (!pi->phynoise_polling
2415 || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
2416 wlapi_bmac_write_shm(pi->sh->physhim, M_JSSI_0, 0);
2417 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
2418 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
2419 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
2420 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
2421
2422 OR_REG(&pi->regs->maccommand,
2423 MCMD_BG_NOISE);
2424 } else {
2425 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2426 wlc_lcnphy_deaf_mode(pi, (bool) 0);
2427 noise_dbm = (s8) wlc_lcnphy_rx_signal_power(pi, 20);
2428 wlc_lcnphy_deaf_mode(pi, (bool) 1);
2429 wlapi_enable_mac(pi->sh->physhim);
2430 wait_for_intr = false;
2431 }
2432 } else if (ISNPHY(pi)) {
2433 if (!pi->phynoise_polling
2434 || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
2435
2436 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
2437 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
2438 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
2439 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
2440
2441 OR_REG(&pi->regs->maccommand,
2442 MCMD_BG_NOISE);
2443 } else {
2444 struct phy_iq_est est[PHY_CORE_MAX];
2445 u32 cmplx_pwr[PHY_CORE_MAX];
2446 s8 noise_dbm_ant[PHY_CORE_MAX];
2447 u16 log_num_samps, num_samps, classif_state = 0;
2448 u8 wait_time = 32;
2449 u8 wait_crs = 0;
2450 u8 i;
2451
2452 memset((u8 *) est, 0, sizeof(est));
2453 memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
2454 memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
2455
2456 log_num_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
2457 num_samps = 1 << log_num_samps;
2458
2459 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2460 classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
2461 wlc_phy_classifier_nphy(pi, 3, 0);
2462 wlc_phy_rx_iq_est_nphy(pi, est, num_samps, wait_time,
2463 wait_crs);
2464 wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
2465 wlapi_enable_mac(pi->sh->physhim);
2466
2467 for (i = 0; i < pi->pubpi.phy_corenum; i++)
2468 cmplx_pwr[i] = (est[i].i_pwr + est[i].q_pwr) >>
2469 log_num_samps;
2470
2471 wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
2472
2473 for (i = 0; i < pi->pubpi.phy_corenum; i++) {
2474 pi->nphy_noise_win[i][pi->nphy_noise_index] =
2475 noise_dbm_ant[i];
2476
2477 if (noise_dbm_ant[i] > noise_dbm)
2478 noise_dbm = noise_dbm_ant[i];
2479 }
2480 pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
2481 PHY_NOISE_WINDOW_SZ);
2482
2483 wait_for_intr = false;
2484 }
2485 }
2486
2487done:
2488
2489 if (!wait_for_intr)
2490 wlc_phy_noise_cb(pi, ch, noise_dbm);
2491
2492}
2493
2494void wlc_phy_noise_sample_request_external(struct brcms_phy_pub *pih)
2495{
2496 u8 channel;
2497
2498 channel = CHSPEC_CHANNEL(wlc_phy_chanspec_get(pih));
2499
2500 wlc_phy_noise_sample_request(pih, PHY_NOISE_SAMPLE_EXTERNAL, channel);
2501}
2502
2503static const s8 lcnphy_gain_index_offset_for_pkt_rssi[] = {
2504 8,
2505 8,
2506 8,
2507 8,
2508 8,
2509 8,
2510 8,
2511 9,
2512 10,
2513 8,
2514 8,
2515 7,
2516 7,
2517 1,
2518 2,
2519 2,
2520 2,
2521 2,
2522 2,
2523 2,
2524 2,
2525 2,
2526 2,
2527 2,
2528 2,
2529 2,
2530 2,
2531 2,
2532 2,
2533 2,
2534 2,
2535 2,
2536 1,
2537 1,
2538 0,
2539 0,
2540 0,
2541 0
2542};
2543
2544void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
2545{
2546 u8 msb, secondmsb, i;
2547 u32 tmp;
2548
2549 for (i = 0; i < core; i++) {
2550 secondmsb = 0;
2551 tmp = cmplx_pwr[i];
2552 msb = fls(tmp);
2553 if (msb)
2554 secondmsb = (u8) ((tmp >> (--msb - 1)) & 1);
2555 p_cmplx_pwr_dB[i] = (s8) (3 * msb + 2 * secondmsb);
2556 }
2557}
2558
2559int wlc_phy_rssi_compute(struct brcms_phy_pub *pih,
2560 struct d11rxhdr *rxh)
2561{
2562 int rssi = rxh->PhyRxStatus_1 & PRXS1_JSSI_MASK;
2563 uint radioid = pih->radioid;
2564 struct brcms_phy *pi = (struct brcms_phy *) pih;
2565
2566 if ((pi->sh->corerev >= 11)
2567 && !(rxh->RxStatus2 & RXS_PHYRXST_VALID)) {
2568 rssi = BRCMS_RSSI_INVALID;
2569 goto end;
2570 }
2571
2572 if (ISLCNPHY(pi)) {
2573 u8 gidx = (rxh->PhyRxStatus_2 & 0xFC00) >> 10;
2574 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2575
2576 if (rssi > 127)
2577 rssi -= 256;
2578
2579 rssi = rssi + lcnphy_gain_index_offset_for_pkt_rssi[gidx];
2580 if ((rssi > -46) && (gidx > 18))
2581 rssi = rssi + 7;
2582
2583 rssi = rssi + pi_lcn->lcnphy_pkteng_rssi_slope;
2584
2585 rssi = rssi + 2;
2586
2587 }
2588
2589 if (ISLCNPHY(pi)) {
2590 if (rssi > 127)
2591 rssi -= 256;
2592 } else if (radioid == BCM2055_ID || radioid == BCM2056_ID
2593 || radioid == BCM2057_ID) {
2594 rssi = wlc_phy_rssi_compute_nphy(pi, rxh);
2595 }
2596
2597end:
2598 return rssi;
2599}
2600
2601void wlc_phy_freqtrack_start(struct brcms_phy_pub *pih)
2602{
2603 return;
2604}
2605
2606void wlc_phy_freqtrack_end(struct brcms_phy_pub *pih)
2607{
2608 return;
2609}
2610
2611void wlc_phy_set_deaf(struct brcms_phy_pub *ppi, bool user_flag)
2612{
2613 struct brcms_phy *pi;
2614 pi = (struct brcms_phy *) ppi;
2615
2616 if (ISLCNPHY(pi))
2617 wlc_lcnphy_deaf_mode(pi, true);
2618 else if (ISNPHY(pi))
2619 wlc_nphy_deaf_mode(pi, true);
2620}
2621
2622void wlc_phy_watchdog(struct brcms_phy_pub *pih)
2623{
2624 struct brcms_phy *pi = (struct brcms_phy *) pih;
2625 bool delay_phy_cal = false;
2626 pi->sh->now++;
2627
2628 if (!pi->watchdog_override)
2629 return;
2630
2631 if (!(SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)))
2632 wlc_phy_noise_sample_request((struct brcms_phy_pub *) pi,
2633 PHY_NOISE_SAMPLE_MON,
2634 CHSPEC_CHANNEL(pi->
2635 radio_chanspec));
2636
2637 if (pi->phynoise_state && (pi->sh->now - pi->phynoise_now) > 5)
2638 pi->phynoise_state = 0;
2639
2640 if ((!pi->phycal_txpower) ||
2641 ((pi->sh->now - pi->phycal_txpower) >= pi->sh->fast_timer)) {
2642
2643 if (!SCAN_INPROG_PHY(pi) && wlc_phy_cal_txpower_recalc_sw(pi))
2644 pi->phycal_txpower = pi->sh->now;
2645 }
2646
2647 if ((SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
2648 || ASSOC_INPROG_PHY(pi)))
2649 return;
2650
2651 if (ISNPHY(pi) && !pi->disable_percal && !delay_phy_cal) {
2652
2653 if ((pi->nphy_perical != PHY_PERICAL_DISABLE) &&
2654 (pi->nphy_perical != PHY_PERICAL_MANUAL) &&
2655 ((pi->sh->now - pi->nphy_perical_last) >=
2656 pi->sh->glacial_timer))
2657 wlc_phy_cal_perical((struct brcms_phy_pub *) pi,
2658 PHY_PERICAL_WATCHDOG);
2659
2660 wlc_phy_txpwr_papd_cal_nphy(pi);
2661 }
2662
2663 if (ISLCNPHY(pi)) {
2664 if (pi->phy_forcecal ||
2665 ((pi->sh->now - pi->phy_lastcal) >=
2666 pi->sh->glacial_timer)) {
2667 if (!(SCAN_RM_IN_PROGRESS(pi) || ASSOC_INPROG_PHY(pi)))
2668 wlc_lcnphy_calib_modes(
2669 pi,
2670 LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL);
2671 if (!
2672 (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
2673 || ASSOC_INPROG_PHY(pi)
2674 || pi->carrier_suppr_disable
2675 || pi->disable_percal))
2676 wlc_lcnphy_calib_modes(pi,
2677 PHY_PERICAL_WATCHDOG);
2678 }
2679 }
2680}
2681
2682void wlc_phy_BSSinit(struct brcms_phy_pub *pih, bool bonlyap, int rssi)
2683{
2684 struct brcms_phy *pi = (struct brcms_phy *) pih;
2685 uint i;
2686 uint k;
2687
2688 for (i = 0; i < MA_WINDOW_SZ; i++)
2689 pi->sh->phy_noise_window[i] = (s8) (rssi & 0xff);
2690 if (ISLCNPHY(pi)) {
2691 for (i = 0; i < MA_WINDOW_SZ; i++)
2692 pi->sh->phy_noise_window[i] =
2693 PHY_NOISE_FIXED_VAL_LCNPHY;
2694 }
2695 pi->sh->phy_noise_index = 0;
2696
2697 for (i = 0; i < PHY_NOISE_WINDOW_SZ; i++) {
2698 for (k = WL_ANT_IDX_1; k < WL_ANT_RX_MAX; k++)
2699 pi->nphy_noise_win[k][i] = PHY_NOISE_FIXED_VAL_NPHY;
2700 }
2701 pi->nphy_noise_index = 0;
2702}
2703
2704void
2705wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag)
2706{
2707 *eps_imag = (epsilon >> 13);
2708 if (*eps_imag > 0xfff)
2709 *eps_imag -= 0x2000;
2710
2711 *eps_real = (epsilon & 0x1fff);
2712 if (*eps_real > 0xfff)
2713 *eps_real -= 0x2000;
2714}
2715
2716void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi)
2717{
2718 wlapi_del_timer(pi->sh->physhim, pi->phycal_timer);
2719
2720 pi->cal_type_override = PHY_PERICAL_AUTO;
2721 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
2722 pi->mphase_txcal_cmdidx = 0;
2723}
2724
2725static void
2726wlc_phy_cal_perical_mphase_schedule(struct brcms_phy *pi, uint delay)
2727{
2728
2729 if ((pi->nphy_perical != PHY_PERICAL_MPHASE) &&
2730 (pi->nphy_perical != PHY_PERICAL_MANUAL))
2731 return;
2732
2733 wlapi_del_timer(pi->sh->physhim, pi->phycal_timer);
2734
2735 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
2736 wlapi_add_timer(pi->sh->physhim, pi->phycal_timer, delay, 0);
2737}
2738
2739void wlc_phy_cal_perical(struct brcms_phy_pub *pih, u8 reason)
2740{
2741 s16 nphy_currtemp = 0;
2742 s16 delta_temp = 0;
2743 bool do_periodic_cal = true;
2744 struct brcms_phy *pi = (struct brcms_phy *) pih;
2745
2746 if (!ISNPHY(pi))
2747 return;
2748
2749 if ((pi->nphy_perical == PHY_PERICAL_DISABLE) ||
2750 (pi->nphy_perical == PHY_PERICAL_MANUAL))
2751 return;
2752
2753 switch (reason) {
2754 case PHY_PERICAL_DRIVERUP:
2755 break;
2756
2757 case PHY_PERICAL_PHYINIT:
2758 if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
2759 if (PHY_PERICAL_MPHASE_PENDING(pi))
2760 wlc_phy_cal_perical_mphase_reset(pi);
2761
2762 wlc_phy_cal_perical_mphase_schedule(
2763 pi,
2764 PHY_PERICAL_INIT_DELAY);
2765 }
2766 break;
2767
2768 case PHY_PERICAL_JOIN_BSS:
2769 case PHY_PERICAL_START_IBSS:
2770 case PHY_PERICAL_UP_BSS:
2771 if ((pi->nphy_perical == PHY_PERICAL_MPHASE) &&
2772 PHY_PERICAL_MPHASE_PENDING(pi))
2773 wlc_phy_cal_perical_mphase_reset(pi);
2774
2775 pi->first_cal_after_assoc = true;
2776
2777 pi->cal_type_override = PHY_PERICAL_FULL;
2778
2779 if (pi->phycal_tempdelta)
2780 pi->nphy_lastcal_temp = wlc_phy_tempsense_nphy(pi);
2781
2782 wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_FULL);
2783 break;
2784
2785 case PHY_PERICAL_WATCHDOG:
2786 if (pi->phycal_tempdelta) {
2787 nphy_currtemp = wlc_phy_tempsense_nphy(pi);
2788 delta_temp =
2789 (nphy_currtemp > pi->nphy_lastcal_temp) ?
2790 nphy_currtemp - pi->nphy_lastcal_temp :
2791 pi->nphy_lastcal_temp - nphy_currtemp;
2792
2793 if ((delta_temp < (s16) pi->phycal_tempdelta) &&
2794 (pi->nphy_txiqlocal_chanspec ==
2795 pi->radio_chanspec))
2796 do_periodic_cal = false;
2797 else
2798 pi->nphy_lastcal_temp = nphy_currtemp;
2799 }
2800
2801 if (do_periodic_cal) {
2802 if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
2803 if (!PHY_PERICAL_MPHASE_PENDING(pi))
2804 wlc_phy_cal_perical_mphase_schedule(
2805 pi,
2806 PHY_PERICAL_WDOG_DELAY);
2807 } else if (pi->nphy_perical == PHY_PERICAL_SPHASE)
2808 wlc_phy_cal_perical_nphy_run(pi,
2809 PHY_PERICAL_AUTO);
2810 }
2811 break;
2812 default:
2813 break;
2814 }
2815}
2816
2817void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi)
2818{
2819 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
2820 pi->mphase_txcal_cmdidx = 0;
2821}
2822
2823u8 wlc_phy_nbits(s32 value)
2824{
2825 s32 abs_val;
2826 u8 nbits = 0;
2827
2828 abs_val = abs(value);
2829 while ((abs_val >> nbits) > 0)
2830 nbits++;
2831
2832 return nbits;
2833}
2834
2835void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain)
2836{
2837 struct brcms_phy *pi = (struct brcms_phy *) pih;
2838
2839 pi->sh->hw_phytxchain = txchain;
2840 pi->sh->hw_phyrxchain = rxchain;
2841 pi->sh->phytxchain = txchain;
2842 pi->sh->phyrxchain = rxchain;
2843 pi->pubpi.phy_corenum = (u8)hweight8(pi->sh->phyrxchain);
2844}
2845
2846void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain)
2847{
2848 struct brcms_phy *pi = (struct brcms_phy *) pih;
2849
2850 pi->sh->phytxchain = txchain;
2851
2852 if (ISNPHY(pi))
2853 wlc_phy_rxcore_setstate_nphy(pih, rxchain);
2854
2855 pi->pubpi.phy_corenum = (u8)hweight8(pi->sh->phyrxchain);
2856}
2857
2858void wlc_phy_stf_chain_get(struct brcms_phy_pub *pih, u8 *txchain, u8 *rxchain)
2859{
2860 struct brcms_phy *pi = (struct brcms_phy *) pih;
2861
2862 *txchain = pi->sh->phytxchain;
2863 *rxchain = pi->sh->phyrxchain;
2864}
2865
2866u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih)
2867{
2868 s16 nphy_currtemp;
2869 u8 active_bitmap;
2870 struct brcms_phy *pi = (struct brcms_phy *) pih;
2871
2872 active_bitmap = (pi->phy_txcore_heatedup) ? 0x31 : 0x33;
2873
2874 if (!pi->watchdog_override)
2875 return active_bitmap;
2876
2877 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
2878 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2879 nphy_currtemp = wlc_phy_tempsense_nphy(pi);
2880 wlapi_enable_mac(pi->sh->physhim);
2881
2882 if (!pi->phy_txcore_heatedup) {
2883 if (nphy_currtemp >= pi->phy_txcore_disable_temp) {
2884 active_bitmap &= 0xFD;
2885 pi->phy_txcore_heatedup = true;
2886 }
2887 } else {
2888 if (nphy_currtemp <= pi->phy_txcore_enable_temp) {
2889 active_bitmap |= 0x2;
2890 pi->phy_txcore_heatedup = false;
2891 }
2892 }
2893 }
2894
2895 return active_bitmap;
2896}
2897
2898s8 wlc_phy_stf_ssmode_get(struct brcms_phy_pub *pih, u16 chanspec)
2899{
2900 struct brcms_phy *pi = (struct brcms_phy *) pih;
2901 u8 siso_mcs_id, cdd_mcs_id;
2902
2903 siso_mcs_id =
2904 (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_SISO :
2905 TXP_FIRST_MCS_20_SISO;
2906 cdd_mcs_id =
2907 (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_CDD :
2908 TXP_FIRST_MCS_20_CDD;
2909
2910 if (pi->tx_power_target[siso_mcs_id] >
2911 (pi->tx_power_target[cdd_mcs_id] + 12))
2912 return PHY_TXC1_MODE_SISO;
2913 else
2914 return PHY_TXC1_MODE_CDD;
2915}
2916
2917const u8 *wlc_phy_get_ofdm_rate_lookup(void)
2918{
2919 return ofdm_rate_lookup;
2920}
2921
2922void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode)
2923{
2924 if ((pi->sh->chip == BCM4313_CHIP_ID) &&
2925 (pi->sh->boardflags & BFL_FEM)) {
2926 if (mode) {
2927 u16 txant = 0;
2928 txant = wlapi_bmac_get_txant(pi->sh->physhim);
2929 if (txant == 1) {
2930 mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
2931
2932 mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
2933
2934 }
2935 ai_corereg(pi->sh->sih, SI_CC_IDX,
2936 offsetof(struct chipcregs, gpiocontrol),
2937 ~0x0, 0x0);
2938 ai_corereg(pi->sh->sih, SI_CC_IDX,
2939 offsetof(struct chipcregs, gpioout), 0x40,
2940 0x40);
2941 ai_corereg(pi->sh->sih, SI_CC_IDX,
2942 offsetof(struct chipcregs, gpioouten), 0x40,
2943 0x40);
2944 } else {
2945 mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);
2946
2947 mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
2948
2949 ai_corereg(pi->sh->sih, SI_CC_IDX,
2950 offsetof(struct chipcregs, gpioout), 0x40,
2951 0x00);
2952 ai_corereg(pi->sh->sih, SI_CC_IDX,
2953 offsetof(struct chipcregs, gpioouten), 0x40,
2954 0x0);
2955 ai_corereg(pi->sh->sih, SI_CC_IDX,
2956 offsetof(struct chipcregs, gpiocontrol),
2957 ~0x0, 0x40);
2958 }
2959 }
2960}
2961
2962void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi, bool ldpc)
2963{
2964 return;
2965}
2966
2967void
2968wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset, s8 *ofdmoffset)
2969{
2970 *cckoffset = 0;
2971 *ofdmoffset = 0;
2972}
2973
2974s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi, u16 chanspec)
2975{
2976
2977 return rssi;
2978}
2979
2980bool wlc_phy_txpower_ipa_ison(struct brcms_phy_pub *ppi)
2981{
2982 struct brcms_phy *pi = (struct brcms_phy *) ppi;
2983
2984 if (ISNPHY(pi))
2985 return wlc_phy_n_txpower_ipa_ison(pi);
2986 else
2987 return 0;
2988}
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h b/drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h
deleted file mode 100644
index 96e15163222..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h
+++ /dev/null
@@ -1,301 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*
18 * phy_hal.h: functionality exported from the phy to higher layers
19 */
20
21#ifndef _BRCM_PHY_HAL_H_
22#define _BRCM_PHY_HAL_H_
23
24#include <brcmu_utils.h>
25#include <brcmu_wifi.h>
26#include <phy_shim.h>
27
28#define IDCODE_VER_MASK 0x0000000f
29#define IDCODE_VER_SHIFT 0
30#define IDCODE_MFG_MASK 0x00000fff
31#define IDCODE_MFG_SHIFT 0
32#define IDCODE_ID_MASK 0x0ffff000
33#define IDCODE_ID_SHIFT 12
34#define IDCODE_REV_MASK 0xf0000000
35#define IDCODE_REV_SHIFT 28
36
37#define NORADIO_ID 0xe4f5
38#define NORADIO_IDCODE 0x4e4f5246
39
40#define BCM2055_ID 0x2055
41#define BCM2055_IDCODE 0x02055000
42#define BCM2055A0_IDCODE 0x1205517f
43
44#define BCM2056_ID 0x2056
45#define BCM2056_IDCODE 0x02056000
46#define BCM2056A0_IDCODE 0x1205617f
47
48#define BCM2057_ID 0x2057
49#define BCM2057_IDCODE 0x02057000
50#define BCM2057A0_IDCODE 0x1205717f
51
52#define BCM2064_ID 0x2064
53#define BCM2064_IDCODE 0x02064000
54#define BCM2064A0_IDCODE 0x0206417f
55
56#define PHY_TPC_HW_OFF false
57#define PHY_TPC_HW_ON true
58
59#define PHY_PERICAL_DRIVERUP 1
60#define PHY_PERICAL_WATCHDOG 2
61#define PHY_PERICAL_PHYINIT 3
62#define PHY_PERICAL_JOIN_BSS 4
63#define PHY_PERICAL_START_IBSS 5
64#define PHY_PERICAL_UP_BSS 6
65#define PHY_PERICAL_CHAN 7
66#define PHY_FULLCAL 8
67
68#define PHY_PERICAL_DISABLE 0
69#define PHY_PERICAL_SPHASE 1
70#define PHY_PERICAL_MPHASE 2
71#define PHY_PERICAL_MANUAL 3
72
73#define PHY_HOLD_FOR_ASSOC 1
74#define PHY_HOLD_FOR_SCAN 2
75#define PHY_HOLD_FOR_RM 4
76#define PHY_HOLD_FOR_PLT 8
77#define PHY_HOLD_FOR_MUTE 16
78#define PHY_HOLD_FOR_NOT_ASSOC 0x20
79
80#define PHY_MUTE_FOR_PREISM 1
81#define PHY_MUTE_ALL 0xffffffff
82
83#define PHY_NOISE_FIXED_VAL (-95)
84#define PHY_NOISE_FIXED_VAL_NPHY (-92)
85#define PHY_NOISE_FIXED_VAL_LCNPHY (-92)
86
87#define PHY_MODE_CAL 0x0002
88#define PHY_MODE_NOISEM 0x0004
89
90#define BRCMS_TXPWR_DB_FACTOR 4
91
92/* a large TX Power as an init value to factor out of min() calculations,
93 * keep low enough to fit in an s8, units are .25 dBm
94 */
95#define BRCMS_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */
96
97#define BRCMS_NUM_RATES_CCK 4
98#define BRCMS_NUM_RATES_OFDM 8
99#define BRCMS_NUM_RATES_MCS_1_STREAM 8
100#define BRCMS_NUM_RATES_MCS_2_STREAM 8
101#define BRCMS_NUM_RATES_MCS_3_STREAM 8
102#define BRCMS_NUM_RATES_MCS_4_STREAM 8
103
104#define BRCMS_RSSI_INVALID 0 /* invalid RSSI value */
105
106struct d11regs;
107struct phy_shim_info;
108
109struct txpwr_limits {
110 u8 cck[BRCMS_NUM_RATES_CCK];
111 u8 ofdm[BRCMS_NUM_RATES_OFDM];
112
113 u8 ofdm_cdd[BRCMS_NUM_RATES_OFDM];
114
115 u8 ofdm_40_siso[BRCMS_NUM_RATES_OFDM];
116 u8 ofdm_40_cdd[BRCMS_NUM_RATES_OFDM];
117
118 u8 mcs_20_siso[BRCMS_NUM_RATES_MCS_1_STREAM];
119 u8 mcs_20_cdd[BRCMS_NUM_RATES_MCS_1_STREAM];
120 u8 mcs_20_stbc[BRCMS_NUM_RATES_MCS_1_STREAM];
121 u8 mcs_20_mimo[BRCMS_NUM_RATES_MCS_2_STREAM];
122
123 u8 mcs_40_siso[BRCMS_NUM_RATES_MCS_1_STREAM];
124 u8 mcs_40_cdd[BRCMS_NUM_RATES_MCS_1_STREAM];
125 u8 mcs_40_stbc[BRCMS_NUM_RATES_MCS_1_STREAM];
126 u8 mcs_40_mimo[BRCMS_NUM_RATES_MCS_2_STREAM];
127 u8 mcs32;
128};
129
130struct tx_power {
131 u32 flags;
132 u16 chanspec; /* txpwr report for this channel */
133 u16 local_chanspec; /* channel on which we are associated */
134 u8 local_max; /* local max according to the AP */
135 u8 local_constraint; /* local constraint according to the AP */
136 s8 antgain[2]; /* Ant gain for each band - from SROM */
137 u8 rf_cores; /* count of RF Cores being reported */
138 u8 est_Pout[4]; /* Latest tx power out estimate per RF chain */
139 u8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain
140 * without adjustment */
141 u8 est_Pout_cck; /* Latest CCK tx power out estimate */
142 u8 tx_power_max[4]; /* Maximum target power among all rates */
143 /* Index of the rate with the max target power */
144 u8 tx_power_max_rate_ind[4];
145 /* User limit */
146 u8 user_limit[WL_TX_POWER_RATES];
147 /* Regulatory power limit */
148 u8 reg_limit[WL_TX_POWER_RATES];
149 /* Max power board can support (SROM) */
150 u8 board_limit[WL_TX_POWER_RATES];
151 /* Latest target power */
152 u8 target[WL_TX_POWER_RATES];
153};
154
155struct tx_inst_power {
156 u8 txpwr_est_Pout[2]; /* Latest estimate for 2.4 and 5 Ghz */
157 u8 txpwr_est_Pout_gofdm; /* Pwr estimate for 2.4 OFDM */
158};
159
160struct brcms_chanvec {
161 u8 vec[MAXCHANNEL / NBBY];
162};
163
164struct shared_phy_params {
165 struct si_pub *sih;
166 struct phy_shim_info *physhim;
167 uint unit;
168 uint corerev;
169 uint buscorerev;
170 u16 vid;
171 u16 did;
172 uint chip;
173 uint chiprev;
174 uint chippkg;
175 uint sromrev;
176 uint boardtype;
177 uint boardrev;
178 uint boardvendor;
179 u32 boardflags;
180 u32 boardflags2;
181};
182
183
184extern struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp);
185extern struct brcms_phy_pub *wlc_phy_attach(struct shared_phy *sh,
186 struct d11regs __iomem *regs,
187 int bandtype, struct wiphy *wiphy);
188extern void wlc_phy_detach(struct brcms_phy_pub *ppi);
189
190extern bool wlc_phy_get_phyversion(struct brcms_phy_pub *pih, u16 *phytype,
191 u16 *phyrev, u16 *radioid,
192 u16 *radiover);
193extern bool wlc_phy_get_encore(struct brcms_phy_pub *pih);
194extern u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih);
195
196extern void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *ppi, bool newstate);
197extern void wlc_phy_hw_state_upd(struct brcms_phy_pub *ppi, bool newstate);
198extern void wlc_phy_init(struct brcms_phy_pub *ppi, u16 chanspec);
199extern void wlc_phy_watchdog(struct brcms_phy_pub *ppi);
200extern int wlc_phy_down(struct brcms_phy_pub *ppi);
201extern u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih);
202extern void wlc_phy_cal_init(struct brcms_phy_pub *ppi);
203extern void wlc_phy_antsel_init(struct brcms_phy_pub *ppi, bool lut_init);
204
205extern void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi,
206 u16 chanspec);
207extern u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi);
208extern void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi,
209 u16 newch);
210extern u16 wlc_phy_bw_state_get(struct brcms_phy_pub *ppi);
211extern void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi, u16 bw);
212
213extern int wlc_phy_rssi_compute(struct brcms_phy_pub *pih,
214 struct d11rxhdr *rxh);
215extern void wlc_phy_por_inform(struct brcms_phy_pub *ppi);
216extern void wlc_phy_noise_sample_intr(struct brcms_phy_pub *ppi);
217extern bool wlc_phy_bist_check_phy(struct brcms_phy_pub *ppi);
218
219extern void wlc_phy_set_deaf(struct brcms_phy_pub *ppi, bool user_flag);
220
221extern void wlc_phy_switch_radio(struct brcms_phy_pub *ppi, bool on);
222extern void wlc_phy_anacore(struct brcms_phy_pub *ppi, bool on);
223
224
225extern void wlc_phy_BSSinit(struct brcms_phy_pub *ppi, bool bonlyap, int rssi);
226
227extern void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi,
228 bool wide_filter);
229extern void wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi, uint band,
230 struct brcms_chanvec *channels);
231extern u16 wlc_phy_chanspec_band_firstch(struct brcms_phy_pub *ppi,
232 uint band);
233
234extern void wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi, uint chan,
235 u8 *_min_, u8 *_max_, int rate);
236extern void wlc_phy_txpower_sromlimit_max_get(struct brcms_phy_pub *ppi,
237 uint chan, u8 *_max_, u8 *_min_);
238extern void wlc_phy_txpower_boardlimit_band(struct brcms_phy_pub *ppi,
239 uint band, s32 *, s32 *, u32 *);
240extern void wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi,
241 struct txpwr_limits *,
242 u16 chanspec);
243extern int wlc_phy_txpower_get(struct brcms_phy_pub *ppi, uint *qdbm,
244 bool *override);
245extern int wlc_phy_txpower_set(struct brcms_phy_pub *ppi, uint qdbm,
246 bool override);
247extern void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi,
248 struct txpwr_limits *);
249extern bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi);
250extern void wlc_phy_txpower_hw_ctrl_set(struct brcms_phy_pub *ppi,
251 bool hwpwrctrl);
252extern u8 wlc_phy_txpower_get_target_min(struct brcms_phy_pub *ppi);
253extern u8 wlc_phy_txpower_get_target_max(struct brcms_phy_pub *ppi);
254extern bool wlc_phy_txpower_ipa_ison(struct brcms_phy_pub *pih);
255
256extern void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih, u8 txchain,
257 u8 rxchain);
258extern void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih, u8 txchain,
259 u8 rxchain);
260extern void wlc_phy_stf_chain_get(struct brcms_phy_pub *pih, u8 *txchain,
261 u8 *rxchain);
262extern u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih);
263extern s8 wlc_phy_stf_ssmode_get(struct brcms_phy_pub *pih,
264 u16 chanspec);
265extern void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi, bool val);
266
267extern void wlc_phy_cal_perical(struct brcms_phy_pub *ppi, u8 reason);
268extern void wlc_phy_noise_sample_request_external(struct brcms_phy_pub *ppi);
269extern void wlc_phy_edcrs_lock(struct brcms_phy_pub *pih, bool lock);
270extern void wlc_phy_cal_papd_recal(struct brcms_phy_pub *ppi);
271
272extern void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val);
273extern void wlc_phy_clear_tssi(struct brcms_phy_pub *ppi);
274extern void wlc_phy_hold_upd(struct brcms_phy_pub *ppi, u32 id, bool val);
275extern void wlc_phy_mute_upd(struct brcms_phy_pub *ppi, bool val, u32 flags);
276
277extern void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi, u8 antsel_type);
278
279extern void wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi,
280 struct tx_power *power, uint channel);
281
282extern void wlc_phy_initcal_enable(struct brcms_phy_pub *pih, bool initcal);
283extern bool wlc_phy_test_ison(struct brcms_phy_pub *ppi);
284extern void wlc_phy_txpwr_percent_set(struct brcms_phy_pub *ppi,
285 u8 txpwr_percent);
286extern void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih, bool war);
287extern void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih,
288 bool bf_preempt);
289extern void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi, u32 machwcap);
290
291extern void wlc_phy_runbist_config(struct brcms_phy_pub *ppi, bool start_end);
292
293extern void wlc_phy_freqtrack_start(struct brcms_phy_pub *ppi);
294extern void wlc_phy_freqtrack_end(struct brcms_phy_pub *ppi);
295
296extern const u8 *wlc_phy_get_ofdm_rate_lookup(void);
297
298extern s8 wlc_phy_get_tx_power_offset_by_mcs(struct brcms_phy_pub *ppi,
299 u8 mcs_offset);
300extern s8 wlc_phy_get_tx_power_offset(struct brcms_phy_pub *ppi, u8 tbl_offset);
301#endif /* _BRCM_PHY_HAL_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_int.h b/drivers/staging/brcm80211/brcmsmac/phy/phy_int.h
deleted file mode 100644
index bea85241a24..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_int.h
+++ /dev/null
@@ -1,1169 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_PHY_INT_H_
18#define _BRCM_PHY_INT_H_
19
20#include <types.h>
21#include <brcmu_utils.h>
22#include <brcmu_wifi.h>
23
24#define PHY_VERSION { 1, 82, 8, 0 }
25
26#define LCNXN_BASEREV 16
27
28struct phy_shim_info;
29
30struct brcms_phy_srom_fem {
31 /* TSSI positive slope, 1: positive, 0: negative */
32 u8 tssipos;
33 /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
34 u8 extpagain;
35 /* support 32 combinations of different Pdet dynamic ranges */
36 u8 pdetrange;
37 /* TR switch isolation */
38 u8 triso;
39 /* antswctrl lookup table configuration: 32 possible choices */
40 u8 antswctrllut;
41};
42
43#define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
44#define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
45
46#define PHY_GET_RFATTN(rfgain) ((rfgain) & 0x0f)
47#define PHY_GET_PADMIX(rfgain) (((rfgain) & 0x10) >> 4)
48#define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width)))
49#define PHY_SAT(x, n) ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
50 ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
51#define PHY_SHIFT_ROUND(x, n) ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
52#define PHY_HW_ROUND(x, s) ((x >> s) + ((x >> (s-1)) & (s != 0)))
53
54#define CH_5G_GROUP 3
55#define A_LOW_CHANS 0
56#define A_MID_CHANS 1
57#define A_HIGH_CHANS 2
58#define CH_2G_GROUP 1
59#define G_ALL_CHANS 0
60
61#define FIRST_REF5_CHANNUM 149
62#define LAST_REF5_CHANNUM 165
63#define FIRST_5G_CHAN 14
64#define LAST_5G_CHAN 50
65#define FIRST_MID_5G_CHAN 14
66#define LAST_MID_5G_CHAN 35
67#define FIRST_HIGH_5G_CHAN 36
68#define LAST_HIGH_5G_CHAN 41
69#define FIRST_LOW_5G_CHAN 42
70#define LAST_LOW_5G_CHAN 50
71
72#define BASE_LOW_5G_CHAN 4900
73#define BASE_MID_5G_CHAN 5100
74#define BASE_HIGH_5G_CHAN 5500
75
76#define CHAN5G_FREQ(chan) (5000 + chan*5)
77#define CHAN2G_FREQ(chan) (2407 + chan*5)
78
79#define TXP_FIRST_CCK 0
80#define TXP_LAST_CCK 3
81#define TXP_FIRST_OFDM 4
82#define TXP_LAST_OFDM 11
83#define TXP_FIRST_OFDM_20_CDD 12
84#define TXP_LAST_OFDM_20_CDD 19
85#define TXP_FIRST_MCS_20_SISO 20
86#define TXP_LAST_MCS_20_SISO 27
87#define TXP_FIRST_MCS_20_CDD 28
88#define TXP_LAST_MCS_20_CDD 35
89#define TXP_FIRST_MCS_20_STBC 36
90#define TXP_LAST_MCS_20_STBC 43
91#define TXP_FIRST_MCS_20_SDM 44
92#define TXP_LAST_MCS_20_SDM 51
93#define TXP_FIRST_OFDM_40_SISO 52
94#define TXP_LAST_OFDM_40_SISO 59
95#define TXP_FIRST_OFDM_40_CDD 60
96#define TXP_LAST_OFDM_40_CDD 67
97#define TXP_FIRST_MCS_40_SISO 68
98#define TXP_LAST_MCS_40_SISO 75
99#define TXP_FIRST_MCS_40_CDD 76
100#define TXP_LAST_MCS_40_CDD 83
101#define TXP_FIRST_MCS_40_STBC 84
102#define TXP_LAST_MCS_40_STBC 91
103#define TXP_FIRST_MCS_40_SDM 92
104#define TXP_LAST_MCS_40_SDM 99
105#define TXP_MCS_32 100
106#define TXP_NUM_RATES 101
107#define ADJ_PWR_TBL_LEN 84
108
109#define TXP_FIRST_SISO_MCS_20 20
110#define TXP_LAST_SISO_MCS_20 27
111
112#define PHY_CORE_NUM_1 1
113#define PHY_CORE_NUM_2 2
114#define PHY_CORE_NUM_3 3
115#define PHY_CORE_NUM_4 4
116#define PHY_CORE_MAX PHY_CORE_NUM_4
117#define PHY_CORE_0 0
118#define PHY_CORE_1 1
119#define PHY_CORE_2 2
120#define PHY_CORE_3 3
121
122#define MA_WINDOW_SZ 8
123
124#define PHY_NOISE_SAMPLE_MON 1
125#define PHY_NOISE_SAMPLE_EXTERNAL 2
126#define PHY_NOISE_WINDOW_SZ 16
127#define PHY_NOISE_GLITCH_INIT_MA 10
128#define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
129#define PHY_NOISE_STATE_MON 0x1
130#define PHY_NOISE_STATE_EXTERNAL 0x2
131#define PHY_NOISE_SAMPLE_LOG_NUM_NPHY 10
132#define PHY_NOISE_SAMPLE_LOG_NUM_UCODE 9
133
134#define PHY_NOISE_OFFSETFACT_4322 (-103)
135#define PHY_NOISE_MA_WINDOW_SZ 2
136
137#define PHY_RSSI_TABLE_SIZE 64
138#define RSSI_ANT_MERGE_MAX 0
139#define RSSI_ANT_MERGE_MIN 1
140#define RSSI_ANT_MERGE_AVG 2
141
142#define PHY_TSSI_TABLE_SIZE 64
143#define APHY_TSSI_TABLE_SIZE 256
144#define TX_GAIN_TABLE_LENGTH 64
145#define DEFAULT_11A_TXP_IDX 24
146#define NUM_TSSI_FRAMES 4
147#define NULL_TSSI 0x7f
148#define NULL_TSSI_W 0x7f7f
149
150#define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
151
152#define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
153
154#define PHY_TXPWR_MIN 10
155#define PHY_TXPWR_MIN_NPHY 8
156#define RADIOPWR_OVERRIDE_DEF (-1)
157
158#define PWRTBL_NUM_COEFF 3
159
160#define SPURAVOID_DISABLE 0
161#define SPURAVOID_AUTO 1
162#define SPURAVOID_FORCEON 2
163#define SPURAVOID_FORCEON2 3
164
165#define PHY_SW_TIMER_FAST 15
166#define PHY_SW_TIMER_SLOW 60
167#define PHY_SW_TIMER_GLACIAL 120
168
169#define PHY_PERICAL_AUTO 0
170#define PHY_PERICAL_FULL 1
171#define PHY_PERICAL_PARTIAL 2
172
173#define PHY_PERICAL_NODELAY 0
174#define PHY_PERICAL_INIT_DELAY 5
175#define PHY_PERICAL_ASSOC_DELAY 5
176#define PHY_PERICAL_WDOG_DELAY 5
177
178#define MPHASE_TXCAL_NUMCMDS 2
179
180#define PHY_PERICAL_MPHASE_PENDING(pi) \
181 (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
182
183enum {
184 MPHASE_CAL_STATE_IDLE = 0,
185 MPHASE_CAL_STATE_INIT = 1,
186 MPHASE_CAL_STATE_TXPHASE0,
187 MPHASE_CAL_STATE_TXPHASE1,
188 MPHASE_CAL_STATE_TXPHASE2,
189 MPHASE_CAL_STATE_TXPHASE3,
190 MPHASE_CAL_STATE_TXPHASE4,
191 MPHASE_CAL_STATE_TXPHASE5,
192 MPHASE_CAL_STATE_PAPDCAL,
193 MPHASE_CAL_STATE_RXCAL,
194 MPHASE_CAL_STATE_RSSICAL,
195 MPHASE_CAL_STATE_IDLETSSI
196};
197
198enum phy_cal_mode {
199 CAL_FULL,
200 CAL_RECAL,
201 CAL_CURRECAL,
202 CAL_DIGCAL,
203 CAL_GCTRL,
204 CAL_SOFT,
205 CAL_DIGLO
206};
207
208#define RDR_NTIERS 1
209#define RDR_TIER_SIZE 64
210#define RDR_LIST_SIZE (512/3)
211#define RDR_EPOCH_SIZE 40
212#define RDR_NANTENNAS 2
213#define RDR_NTIER_SIZE RDR_LIST_SIZE
214#define RDR_LP_BUFFER_SIZE 64
215#define LP_LEN_HIS_SIZE 10
216
217#define STATIC_NUM_RF 32
218#define STATIC_NUM_BB 9
219
220#define BB_MULT_MASK 0x0000ffff
221#define BB_MULT_VALID_MASK 0x80000000
222
223#define CORDIC_AG 39797
224#define CORDIC_NI 18
225#define FIXED(X) ((s32)((X) << 16))
226
227#define FLOAT(X) \
228 (((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
229
230#define PHY_CHAIN_TX_DISABLE_TEMP 115
231#define PHY_HYSTERESIS_DELTATEMP 5
232
233#define SCAN_INPROG_PHY(pi) \
234 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
235
236#define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
237
238#define ASSOC_INPROG_PHY(pi) \
239 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
240
241#define SCAN_RM_IN_PROGRESS(pi) \
242 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
243
244#define PHY_MUTED(pi) \
245 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
246
247#define PUB_NOT_ASSOC(pi) \
248 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
249
250struct phy_table_info {
251 uint table;
252 int q;
253 uint max;
254};
255
256struct phytbl_info {
257 const void *tbl_ptr;
258 u32 tbl_len;
259 u32 tbl_id;
260 u32 tbl_offset;
261 u32 tbl_width;
262};
263
264struct interference_info {
265 u8 curr_home_channel;
266 u16 crsminpwrthld_40_stored;
267 u16 crsminpwrthld_20L_stored;
268 u16 crsminpwrthld_20U_stored;
269 u16 init_gain_code_core1_stored;
270 u16 init_gain_code_core2_stored;
271 u16 init_gain_codeb_core1_stored;
272 u16 init_gain_codeb_core2_stored;
273 u16 init_gain_table_stored[4];
274
275 u16 clip1_hi_gain_code_core1_stored;
276 u16 clip1_hi_gain_code_core2_stored;
277 u16 clip1_hi_gain_codeb_core1_stored;
278 u16 clip1_hi_gain_codeb_core2_stored;
279 u16 nb_clip_thresh_core1_stored;
280 u16 nb_clip_thresh_core2_stored;
281 u16 init_ofdmlna2gainchange_stored[4];
282 u16 init_ccklna2gainchange_stored[4];
283 u16 clip1_lo_gain_code_core1_stored;
284 u16 clip1_lo_gain_code_core2_stored;
285 u16 clip1_lo_gain_codeb_core1_stored;
286 u16 clip1_lo_gain_codeb_core2_stored;
287 u16 w1_clip_thresh_core1_stored;
288 u16 w1_clip_thresh_core2_stored;
289 u16 radio_2056_core1_rssi_gain_stored;
290 u16 radio_2056_core2_rssi_gain_stored;
291 u16 energy_drop_timeout_len_stored;
292
293 u16 ed_crs40_assertthld0_stored;
294 u16 ed_crs40_assertthld1_stored;
295 u16 ed_crs40_deassertthld0_stored;
296 u16 ed_crs40_deassertthld1_stored;
297 u16 ed_crs20L_assertthld0_stored;
298 u16 ed_crs20L_assertthld1_stored;
299 u16 ed_crs20L_deassertthld0_stored;
300 u16 ed_crs20L_deassertthld1_stored;
301 u16 ed_crs20U_assertthld0_stored;
302 u16 ed_crs20U_assertthld1_stored;
303 u16 ed_crs20U_deassertthld0_stored;
304 u16 ed_crs20U_deassertthld1_stored;
305
306 u16 badplcp_ma;
307 u16 badplcp_ma_previous;
308 u16 badplcp_ma_total;
309 u16 badplcp_ma_list[MA_WINDOW_SZ];
310 int badplcp_ma_index;
311 s16 pre_badplcp_cnt;
312 s16 bphy_pre_badplcp_cnt;
313
314 u16 init_gain_core1;
315 u16 init_gain_core2;
316 u16 init_gainb_core1;
317 u16 init_gainb_core2;
318 u16 init_gain_rfseq[4];
319
320 u16 crsminpwr0;
321 u16 crsminpwrl0;
322 u16 crsminpwru0;
323
324 s16 crsminpwr_index;
325
326 u16 radio_2057_core1_rssi_wb1a_gc_stored;
327 u16 radio_2057_core2_rssi_wb1a_gc_stored;
328 u16 radio_2057_core1_rssi_wb1g_gc_stored;
329 u16 radio_2057_core2_rssi_wb1g_gc_stored;
330 u16 radio_2057_core1_rssi_wb2_gc_stored;
331 u16 radio_2057_core2_rssi_wb2_gc_stored;
332 u16 radio_2057_core1_rssi_nb_gc_stored;
333 u16 radio_2057_core2_rssi_nb_gc_stored;
334};
335
336struct aci_save_gphy {
337 u16 rc_cal_ovr;
338 u16 phycrsth1;
339 u16 phycrsth2;
340 u16 init_n1p1_gain;
341 u16 p1_p2_gain;
342 u16 n1_n2_gain;
343 u16 n1_p1_gain;
344 u16 div_search_gain;
345 u16 div_p1_p2_gain;
346 u16 div_search_gn_change;
347 u16 table_7_2;
348 u16 table_7_3;
349 u16 cckshbits_gnref;
350 u16 clip_thresh;
351 u16 clip2_thresh;
352 u16 clip3_thresh;
353 u16 clip_p2_thresh;
354 u16 clip_pwdn_thresh;
355 u16 clip_n1p1_thresh;
356 u16 clip_n1_pwdn_thresh;
357 u16 bbconfig;
358 u16 cthr_sthr_shdin;
359 u16 energy;
360 u16 clip_p1_p2_thresh;
361 u16 threshold;
362 u16 reg15;
363 u16 reg16;
364 u16 reg17;
365 u16 div_srch_idx;
366 u16 div_srch_p1_p2;
367 u16 div_srch_gn_back;
368 u16 ant_dwell;
369 u16 ant_wr_settle;
370};
371
372struct lo_complex_abgphy_info {
373 s8 i;
374 s8 q;
375};
376
377struct nphy_iq_comp {
378 s16 a0;
379 s16 b0;
380 s16 a1;
381 s16 b1;
382};
383
384struct nphy_txpwrindex {
385 s8 index;
386 s8 index_internal;
387 s8 index_internal_save;
388 u16 AfectrlOverride;
389 u16 AfeCtrlDacGain;
390 u16 rad_gain;
391 u8 bbmult;
392 u16 iqcomp_a;
393 u16 iqcomp_b;
394 u16 locomp;
395};
396
397struct txiqcal_cache {
398
399 u16 txcal_coeffs_2G[8];
400 u16 txcal_radio_regs_2G[8];
401 struct nphy_iq_comp rxcal_coeffs_2G;
402
403 u16 txcal_coeffs_5G[8];
404 u16 txcal_radio_regs_5G[8];
405 struct nphy_iq_comp rxcal_coeffs_5G;
406};
407
408struct nphy_pwrctrl {
409 s8 max_pwr_2g;
410 s8 idle_targ_2g;
411 s16 pwrdet_2g_a1;
412 s16 pwrdet_2g_b0;
413 s16 pwrdet_2g_b1;
414 s8 max_pwr_5gm;
415 s8 idle_targ_5gm;
416 s8 max_pwr_5gh;
417 s8 max_pwr_5gl;
418 s16 pwrdet_5gm_a1;
419 s16 pwrdet_5gm_b0;
420 s16 pwrdet_5gm_b1;
421 s16 pwrdet_5gl_a1;
422 s16 pwrdet_5gl_b0;
423 s16 pwrdet_5gl_b1;
424 s16 pwrdet_5gh_a1;
425 s16 pwrdet_5gh_b0;
426 s16 pwrdet_5gh_b1;
427 s8 idle_targ_5gl;
428 s8 idle_targ_5gh;
429 s8 idle_tssi_2g;
430 s8 idle_tssi_5g;
431 s8 idle_tssi;
432 s16 a1;
433 s16 b0;
434 s16 b1;
435};
436
437struct nphy_txgains {
438 u16 txlpf[2];
439 u16 txgm[2];
440 u16 pga[2];
441 u16 pad[2];
442 u16 ipa[2];
443};
444
445#define PHY_NOISEVAR_BUFSIZE 10
446
447struct nphy_noisevar_buf {
448 int bufcount;
449 int tone_id[PHY_NOISEVAR_BUFSIZE];
450 u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
451 u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
452};
453
454struct rssical_cache {
455 u16 rssical_radio_regs_2G[2];
456 u16 rssical_phyregs_2G[12];
457
458 u16 rssical_radio_regs_5G[2];
459 u16 rssical_phyregs_5G[12];
460};
461
462struct lcnphy_cal_results {
463
464 u16 txiqlocal_a;
465 u16 txiqlocal_b;
466 u16 txiqlocal_didq;
467 u8 txiqlocal_ei0;
468 u8 txiqlocal_eq0;
469 u8 txiqlocal_fi0;
470 u8 txiqlocal_fq0;
471
472 u16 txiqlocal_bestcoeffs[11];
473 u16 txiqlocal_bestcoeffs_valid;
474
475 u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
476 u16 analog_gain_ref;
477 u16 lut_begin;
478 u16 lut_end;
479 u16 lut_step;
480 u16 rxcompdbm;
481 u16 papdctrl;
482 u16 sslpnCalibClkEnCtrl;
483
484 u16 rxiqcal_coeff_a0;
485 u16 rxiqcal_coeff_b0;
486};
487
488struct shared_phy {
489 struct brcms_phy *phy_head;
490 uint unit;
491 struct si_pub *sih;
492 struct phy_shim_info *physhim;
493 uint corerev;
494 u32 machwcap;
495 bool up;
496 bool clk;
497 uint now;
498 u16 vid;
499 u16 did;
500 uint chip;
501 uint chiprev;
502 uint chippkg;
503 uint sromrev;
504 uint boardtype;
505 uint boardrev;
506 uint boardvendor;
507 u32 boardflags;
508 u32 boardflags2;
509 uint buscorerev;
510 uint fast_timer;
511 uint slow_timer;
512 uint glacial_timer;
513 u8 rx_antdiv;
514 s8 phy_noise_window[MA_WINDOW_SZ];
515 uint phy_noise_index;
516 u8 hw_phytxchain;
517 u8 hw_phyrxchain;
518 u8 phytxchain;
519 u8 phyrxchain;
520 u8 rssi_mode;
521 bool _rifs_phy;
522};
523
524struct brcms_phy_pub {
525 uint phy_type;
526 uint phy_rev;
527 u8 phy_corenum;
528 u16 radioid;
529 u8 radiorev;
530 u8 radiover;
531
532 uint coreflags;
533 uint ana_rev;
534 bool abgphy_encore;
535};
536
537struct phy_func_ptr {
538 void (*init)(struct brcms_phy *);
539 void (*calinit)(struct brcms_phy *);
540 void (*chanset)(struct brcms_phy *, u16 chanspec);
541 void (*txpwrrecalc)(struct brcms_phy *);
542 int (*longtrn)(struct brcms_phy *, int);
543 void (*txiqccget)(struct brcms_phy *, u16 *, u16 *);
544 void (*txiqccset)(struct brcms_phy *, u16, u16);
545 u16 (*txloccget)(struct brcms_phy *);
546 void (*radioloftget)(struct brcms_phy *, u8 *, u8 *, u8 *, u8 *);
547 void (*carrsuppr)(struct brcms_phy *);
548 s32 (*rxsigpwr)(struct brcms_phy *, s32);
549 void (*detach)(struct brcms_phy *);
550};
551
552struct brcms_phy {
553 struct brcms_phy_pub pubpi_ro;
554 struct shared_phy *sh;
555 struct phy_func_ptr pi_fptr;
556
557 union {
558 struct brcms_phy_lcnphy *pi_lcnphy;
559 } u;
560 bool user_txpwr_at_rfport;
561
562 struct d11regs __iomem *regs;
563 struct brcms_phy *next;
564 struct brcms_phy_pub pubpi;
565
566 bool do_initcal;
567 bool phytest_on;
568 bool ofdm_rateset_war;
569 bool bf_preempt_4306;
570 u16 radio_chanspec;
571 u8 antsel_type;
572 u16 bw;
573 u8 txpwr_percent;
574 bool phy_init_por;
575
576 bool init_in_progress;
577 bool initialized;
578 bool sbtml_gm;
579 uint refcnt;
580 bool watchdog_override;
581 u8 phynoise_state;
582 uint phynoise_now;
583 int phynoise_chan_watchdog;
584 bool phynoise_polling;
585 bool disable_percal;
586 u32 measure_hold;
587
588 s16 txpa_2g[PWRTBL_NUM_COEFF];
589 s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
590 s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
591 s16 txpa_5g_low[PWRTBL_NUM_COEFF];
592 s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
593 s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
594
595 u8 tx_srom_max_2g;
596 u8 tx_srom_max_5g_low;
597 u8 tx_srom_max_5g_mid;
598 u8 tx_srom_max_5g_hi;
599 u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
600 u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
601 u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
602 u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
603 u8 tx_user_target[TXP_NUM_RATES];
604 s8 tx_power_offset[TXP_NUM_RATES];
605 u8 tx_power_target[TXP_NUM_RATES];
606
607 struct brcms_phy_srom_fem srom_fem2g;
608 struct brcms_phy_srom_fem srom_fem5g;
609
610 u8 tx_power_max;
611 u8 tx_power_max_rate_ind;
612 bool hwpwrctrl;
613 u8 nphy_txpwrctrl;
614 s8 nphy_txrx_chain;
615 bool phy_5g_pwrgain;
616
617 u16 phy_wreg;
618 u16 phy_wreg_limit;
619
620 s8 n_preamble_override;
621 u8 antswitch;
622 u8 aa2g, aa5g;
623
624 s8 idle_tssi[CH_5G_GROUP];
625 s8 target_idle_tssi;
626 s8 txpwr_est_Pout;
627 u8 tx_power_min;
628 u8 txpwr_limit[TXP_NUM_RATES];
629 u8 txpwr_env_limit[TXP_NUM_RATES];
630 u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
631
632 bool channel_14_wide_filter;
633
634 bool txpwroverride;
635 bool txpwridx_override_aphy;
636 s16 radiopwr_override;
637 u16 hwpwr_txcur;
638 u8 saved_txpwr_idx;
639
640 bool edcrs_threshold_lock;
641
642 u32 tr_R_gain_val;
643 u32 tr_T_gain_val;
644
645 s16 ofdm_analog_filt_bw_override;
646 s16 cck_analog_filt_bw_override;
647 s16 ofdm_rccal_override;
648 s16 cck_rccal_override;
649 u16 extlna_type;
650
651 uint interference_mode_crs_time;
652 u16 crsglitch_prev;
653 bool interference_mode_crs;
654
655 u32 phy_tx_tone_freq;
656 uint phy_lastcal;
657 bool phy_forcecal;
658 bool phy_fixed_noise;
659 u32 xtalfreq;
660 u8 pdiv;
661 s8 carrier_suppr_disable;
662
663 bool phy_bphy_evm;
664 bool phy_bphy_rfcs;
665 s8 phy_scraminit;
666 u8 phy_gpiosel;
667
668 s16 phy_txcore_disable_temp;
669 s16 phy_txcore_enable_temp;
670 s8 phy_tempsense_offset;
671 bool phy_txcore_heatedup;
672
673 u16 radiopwr;
674 u16 bb_atten;
675 u16 txctl1;
676
677 u16 mintxbias;
678 u16 mintxmag;
679 struct lo_complex_abgphy_info gphy_locomp_iq
680 [STATIC_NUM_RF][STATIC_NUM_BB];
681 s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
682 u16 gain_table[TX_GAIN_TABLE_LENGTH];
683 bool loopback_gain;
684 s16 max_lpback_gain_hdB;
685 s16 trsw_rx_gain_hdB;
686 u8 power_vec[8];
687
688 u16 rc_cal;
689 int nrssi_table_delta;
690 int nrssi_slope_scale;
691 int nrssi_slope_offset;
692 int min_rssi;
693 int max_rssi;
694
695 s8 txpwridx;
696 u8 min_txpower;
697
698 u8 a_band_high_disable;
699
700 u16 tx_vos;
701 u16 global_tx_bb_dc_bias_loft;
702
703 int rf_max;
704 int bb_max;
705 int rf_list_size;
706 int bb_list_size;
707 u16 *rf_attn_list;
708 u16 *bb_attn_list;
709 u16 padmix_mask;
710 u16 padmix_reg;
711 u16 *txmag_list;
712 uint txmag_len;
713 bool txmag_enable;
714
715 s8 *a_tssi_to_dbm;
716 s8 *m_tssi_to_dbm;
717 s8 *l_tssi_to_dbm;
718 s8 *h_tssi_to_dbm;
719 u8 *hwtxpwr;
720
721 u16 freqtrack_saved_regs[2];
722 int cur_interference_mode;
723 bool hwpwrctrl_capable;
724 bool temppwrctrl_capable;
725
726 uint phycal_nslope;
727 uint phycal_noffset;
728 uint phycal_mlo;
729 uint phycal_txpower;
730
731 u8 phy_aa2g;
732
733 bool nphy_tableloaded;
734 s8 nphy_rssisel;
735 u32 nphy_bb_mult_save;
736 u16 nphy_txiqlocal_bestc[11];
737 bool nphy_txiqlocal_coeffsvalid;
738 struct nphy_txpwrindex nphy_txpwrindex[PHY_CORE_NUM_2];
739 struct nphy_pwrctrl nphy_pwrctrl_info[PHY_CORE_NUM_2];
740 u16 cck2gpo;
741 u32 ofdm2gpo;
742 u32 ofdm5gpo;
743 u32 ofdm5glpo;
744 u32 ofdm5ghpo;
745 u8 bw402gpo;
746 u8 bw405gpo;
747 u8 bw405glpo;
748 u8 bw405ghpo;
749 u8 cdd2gpo;
750 u8 cdd5gpo;
751 u8 cdd5glpo;
752 u8 cdd5ghpo;
753 u8 stbc2gpo;
754 u8 stbc5gpo;
755 u8 stbc5glpo;
756 u8 stbc5ghpo;
757 u8 bwdup2gpo;
758 u8 bwdup5gpo;
759 u8 bwdup5glpo;
760 u8 bwdup5ghpo;
761 u16 mcs2gpo[8];
762 u16 mcs5gpo[8];
763 u16 mcs5glpo[8];
764 u16 mcs5ghpo[8];
765 u32 nphy_rxcalparams;
766
767 u8 phy_spuravoid;
768 bool phy_isspuravoid;
769
770 u8 phy_pabias;
771 u8 nphy_papd_skip;
772 u8 nphy_tssi_slope;
773
774 s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
775 u8 nphy_noise_index;
776
777 u8 nphy_txpid2g[PHY_CORE_NUM_2];
778 u8 nphy_txpid5g[PHY_CORE_NUM_2];
779 u8 nphy_txpid5gl[PHY_CORE_NUM_2];
780 u8 nphy_txpid5gh[PHY_CORE_NUM_2];
781
782 bool nphy_gain_boost;
783 bool nphy_elna_gain_config;
784 u16 old_bphy_test;
785 u16 old_bphy_testcontrol;
786
787 bool phyhang_avoid;
788
789 bool rssical_nphy;
790 u8 nphy_perical;
791 uint nphy_perical_last;
792 u8 cal_type_override;
793 u8 mphase_cal_phase_id;
794 u8 mphase_txcal_cmdidx;
795 u8 mphase_txcal_numcmds;
796 u16 mphase_txcal_bestcoeffs[11];
797 u16 nphy_txiqlocal_chanspec;
798 u16 nphy_iqcal_chanspec_2G;
799 u16 nphy_iqcal_chanspec_5G;
800 u16 nphy_rssical_chanspec_2G;
801 u16 nphy_rssical_chanspec_5G;
802 struct wlapi_timer *phycal_timer;
803 bool use_int_tx_iqlo_cal_nphy;
804 bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
805 s16 nphy_lastcal_temp;
806
807 struct txiqcal_cache calibration_cache;
808 struct rssical_cache rssical_cache;
809
810 u8 nphy_txpwr_idx[2];
811 u8 nphy_papd_cal_type;
812 uint nphy_papd_last_cal;
813 u16 nphy_papd_tx_gain_at_last_cal[2];
814 u8 nphy_papd_cal_gain_index[2];
815 s16 nphy_papd_epsilon_offset[2];
816 bool nphy_papd_recal_enable;
817 u32 nphy_papd_recal_counter;
818 bool nphy_force_papd_cal;
819 bool nphy_papdcomp;
820 bool ipa2g_on;
821 bool ipa5g_on;
822
823 u16 classifier_state;
824 u16 clip_state[2];
825 uint nphy_deaf_count;
826 u8 rxiq_samps;
827 u8 rxiq_antsel;
828
829 u16 rfctrlIntc1_save;
830 u16 rfctrlIntc2_save;
831 bool first_cal_after_assoc;
832 u16 tx_rx_cal_radio_saveregs[22];
833 u16 tx_rx_cal_phy_saveregs[15];
834
835 u8 nphy_cal_orig_pwr_idx[2];
836 u8 nphy_txcal_pwr_idx[2];
837 u8 nphy_rxcal_pwr_idx[2];
838 u16 nphy_cal_orig_tx_gain[2];
839 struct nphy_txgains nphy_cal_target_gain;
840 u16 nphy_txcal_bbmult;
841 u16 nphy_gmval;
842
843 u16 nphy_saved_bbconf;
844
845 bool nphy_gband_spurwar_en;
846 bool nphy_gband_spurwar2_en;
847 bool nphy_aband_spurwar_en;
848 u16 nphy_rccal_value;
849 u16 nphy_crsminpwr[3];
850 struct nphy_noisevar_buf nphy_saved_noisevars;
851 bool nphy_anarxlpf_adjusted;
852 bool nphy_crsminpwr_adjusted;
853 bool nphy_noisevars_adjusted;
854
855 bool nphy_rxcal_active;
856 u16 radar_percal_mask;
857 bool dfs_lp_buffer_nphy;
858
859 u16 nphy_fineclockgatecontrol;
860
861 s8 rx2tx_biasentry;
862
863 u16 crsminpwr0;
864 u16 crsminpwrl0;
865 u16 crsminpwru0;
866 s16 noise_crsminpwr_index;
867 u16 init_gain_core1;
868 u16 init_gain_core2;
869 u16 init_gainb_core1;
870 u16 init_gainb_core2;
871 u8 aci_noise_curr_channel;
872 u16 init_gain_rfseq[4];
873
874 bool radio_is_on;
875
876 bool nphy_sample_play_lpf_bw_ctl_ovr;
877
878 u16 tbl_data_hi;
879 u16 tbl_data_lo;
880 u16 tbl_addr;
881
882 uint tbl_save_id;
883 uint tbl_save_offset;
884
885 u8 txpwrctrl;
886 s8 txpwrindex[PHY_CORE_MAX];
887
888 u8 phycal_tempdelta;
889 u32 mcs20_po;
890 u32 mcs40_po;
891 struct wiphy *wiphy;
892};
893
894struct cs32 {
895 s32 q;
896 s32 i;
897};
898
899struct radio_regs {
900 u16 address;
901 u32 init_a;
902 u32 init_g;
903 u8 do_init_a;
904 u8 do_init_g;
905};
906
907struct radio_20xx_regs {
908 u16 address;
909 u8 init;
910 u8 do_init;
911};
912
913struct lcnphy_radio_regs {
914 u16 address;
915 u8 init_a;
916 u8 init_g;
917 u8 do_init_a;
918 u8 do_init_g;
919};
920
921extern u16 read_phy_reg(struct brcms_phy *pi, u16 addr);
922extern void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
923extern void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
924extern void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
925extern void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
926
927extern u16 read_radio_reg(struct brcms_phy *pi, u16 addr);
928extern void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
929extern void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
930extern void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask,
931 u16 val);
932extern void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask);
933
934extern void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
935
936extern void wlc_phyreg_enter(struct brcms_phy_pub *pih);
937extern void wlc_phyreg_exit(struct brcms_phy_pub *pih);
938extern void wlc_radioreg_enter(struct brcms_phy_pub *pih);
939extern void wlc_radioreg_exit(struct brcms_phy_pub *pih);
940
941extern void wlc_phy_read_table(struct brcms_phy *pi,
942 const struct phytbl_info *ptbl_info,
943 u16 tblAddr, u16 tblDataHi,
944 u16 tblDatalo);
945extern void wlc_phy_write_table(struct brcms_phy *pi,
946 const struct phytbl_info *ptbl_info,
947 u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
948extern void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id,
949 uint tbl_offset, u16 tblAddr, u16 tblDataHi,
950 u16 tblDataLo);
951extern void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val);
952
953extern void write_phy_channel_reg(struct brcms_phy *pi, uint val);
954extern void wlc_phy_txpower_update_shm(struct brcms_phy *pi);
955
956extern u8 wlc_phy_nbits(s32 value);
957extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
958
959extern uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
960 struct radio_20xx_regs *radioregs);
961extern uint wlc_phy_init_radio_regs(struct brcms_phy *pi,
962 const struct radio_regs *radioregs,
963 u16 core_offset);
964
965extern void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi);
966
967extern void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on);
968extern void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real,
969 s32 *eps_imag);
970
971extern void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi);
972extern void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi);
973
974extern bool wlc_phy_attach_nphy(struct brcms_phy *pi);
975extern bool wlc_phy_attach_lcnphy(struct brcms_phy *pi);
976
977extern void wlc_phy_detach_lcnphy(struct brcms_phy *pi);
978
979extern void wlc_phy_init_nphy(struct brcms_phy *pi);
980extern void wlc_phy_init_lcnphy(struct brcms_phy *pi);
981
982extern void wlc_phy_cal_init_nphy(struct brcms_phy *pi);
983extern void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi);
984
985extern void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi,
986 u16 chanspec);
987extern void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi,
988 u16 chanspec);
989extern void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi,
990 u16 chanspec);
991extern int wlc_phy_channel2freq(uint channel);
992extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
993extern int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, u16 chanspec);
994
995extern void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode);
996extern s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi);
997
998extern void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi);
999extern void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi);
1000extern void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi);
1001
1002extern void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index);
1003extern void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable);
1004extern void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi);
1005extern void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz,
1006 u16 max_val, bool iqcalmode);
1007
1008extern void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan,
1009 u8 *max_pwr, u8 rate_id);
1010extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
1011 u8 rate_mcs_end,
1012 u8 rate_ofdm_start);
1013extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
1014 u8 rate_ofdm_start,
1015 u8 rate_ofdm_end,
1016 u8 rate_mcs_start);
1017
1018extern u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode);
1019extern s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode);
1020extern s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode);
1021extern s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode);
1022extern void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi);
1023extern void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel);
1024extern void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode);
1025extern void wlc_2064_vco_cal(struct brcms_phy *pi);
1026
1027extern void wlc_phy_txpower_recalc_target(struct brcms_phy *pi);
1028
1029#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
1030#define LCNPHY_TX_POWER_TABLE_SIZE 128
1031#define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1)
1032#define LCNPHY_TBL_ID_TXPWRCTL 0x07
1033#define LCNPHY_TX_PWR_CTRL_OFF 0
1034#define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15)
1035#define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \
1036 (0x1 << 14) | \
1037 (0x1 << 13))
1038
1039#define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001
1040
1041extern void wlc_lcnphy_write_table(struct brcms_phy *pi,
1042 const struct phytbl_info *pti);
1043extern void wlc_lcnphy_read_table(struct brcms_phy *pi,
1044 struct phytbl_info *pti);
1045extern void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b);
1046extern void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq);
1047extern void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b);
1048extern u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi);
1049extern void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0,
1050 u8 *eq0, u8 *fi0, u8 *fq0);
1051extern void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode);
1052extern void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode);
1053extern bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi);
1054extern void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi);
1055extern s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
1056extern void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr,
1057 s8 *cck_pwr);
1058extern void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi);
1059
1060extern s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index);
1061
1062#define NPHY_MAX_HPVGA1_INDEX 10
1063#define NPHY_DEF_HPVGA1_INDEXLIMIT 7
1064
1065struct phy_iq_est {
1066 s32 iq_prod;
1067 u32 i_pwr;
1068 u32 q_pwr;
1069};
1070
1071extern void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi,
1072 bool enable);
1073extern void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode);
1074
1075#define wlc_phy_write_table_nphy(pi, pti) \
1076 wlc_phy_write_table(pi, pti, 0x72, 0x74, 0x73)
1077
1078#define wlc_phy_read_table_nphy(pi, pti) \
1079 wlc_phy_read_table(pi, pti, 0x72, 0x74, 0x73)
1080
1081#define wlc_nphy_table_addr(pi, id, off) \
1082 wlc_phy_table_addr((pi), (id), (off), 0x72, 0x74, 0x73)
1083
1084#define wlc_nphy_table_data_write(pi, w, v) \
1085 wlc_phy_table_data_write((pi), (w), (v))
1086
1087extern void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o,
1088 u32 w, void *d);
1089extern void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32,
1090 u32, const void *);
1091
1092#define PHY_IPA(pi) \
1093 ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1094 (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1095
1096#define BRCMS_PHY_WAR_PR51571(pi) \
1097 if (NREV_LT((pi)->pubpi.phy_rev, 3)) \
1098 (void)R_REG(&(pi)->regs->maccontrol)
1099
1100extern void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype);
1101extern void wlc_phy_aci_reset_nphy(struct brcms_phy *pi);
1102extern void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en);
1103
1104extern u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan);
1105extern void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on);
1106
1107extern void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi);
1108
1109extern void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd);
1110extern s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi);
1111
1112extern u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val);
1113
1114extern void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
1115 u16 num_samps, u8 wait_time,
1116 u8 wait_for_crs);
1117
1118extern void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
1119 struct nphy_iq_comp *comp);
1120extern void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi);
1121
1122extern void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih,
1123 u8 rxcore_bitmask);
1124extern u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih);
1125
1126extern void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type);
1127extern void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi);
1128extern void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi);
1129extern void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi);
1130extern u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi);
1131
1132extern struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi);
1133extern int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi,
1134 struct nphy_txgains target_gain,
1135 bool full, bool m);
1136extern int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi,
1137 struct nphy_txgains target_gain,
1138 u8 type, bool d);
1139extern void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask,
1140 s8 txpwrindex, bool res);
1141extern void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type);
1142extern int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type,
1143 s32 *rssi_buf, u8 nsamps);
1144extern void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi);
1145extern int wlc_phy_aci_scan_nphy(struct brcms_phy *pi);
1146extern void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi,
1147 s32 dBm_targetpower, bool debug);
1148extern int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val,
1149 u8 mode, u8, bool);
1150extern void wlc_phy_stopplayback_nphy(struct brcms_phy *pi);
1151extern void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf,
1152 u8 num_samps);
1153extern void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi);
1154
1155extern int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi,
1156 struct d11rxhdr *rxh);
1157
1158#define NPHY_TESTPATTERN_BPHY_EVM 0
1159#define NPHY_TESTPATTERN_BPHY_RFCS 1
1160
1161extern void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs);
1162
1163void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset,
1164 s8 *ofdmoffset);
1165extern s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi,
1166 u16 chanspec);
1167
1168extern bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih);
1169#endif /* _BRCM_PHY_INT_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c b/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c
deleted file mode 100644
index a63aa99d981..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c
+++ /dev/null
@@ -1,5154 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/kernel.h>
18#include <linux/delay.h>
19#include <linux/cordic.h>
20
21#include <pmu.h>
22#include <d11.h>
23#include <phy_shim.h>
24#include "phy_qmath.h"
25#include "phy_hal.h"
26#include "phy_radio.h"
27#include "phytbl_lcn.h"
28#include "phy_lcn.h"
29
30#define PLL_2064_NDIV 90
31#define PLL_2064_LOW_END_VCO 3000
32#define PLL_2064_LOW_END_KVCO 27
33#define PLL_2064_HIGH_END_VCO 4200
34#define PLL_2064_HIGH_END_KVCO 68
35#define PLL_2064_LOOP_BW_DOUBLER 200
36#define PLL_2064_D30_DOUBLER 10500
37#define PLL_2064_LOOP_BW 260
38#define PLL_2064_D30 8000
39#define PLL_2064_CAL_REF_TO 8
40#define PLL_2064_MHZ 1000000
41#define PLL_2064_OPEN_LOOP_DELAY 5
42
43#define TEMPSENSE 1
44#define VBATSENSE 2
45
46#define NOISE_IF_UPD_CHK_INTERVAL 1
47#define NOISE_IF_UPD_RST_INTERVAL 60
48#define NOISE_IF_UPD_THRESHOLD_CNT 1
49#define NOISE_IF_UPD_TRHRESHOLD 50
50#define NOISE_IF_UPD_TIMEOUT 1000
51#define NOISE_IF_OFF 0
52#define NOISE_IF_CHK 1
53#define NOISE_IF_ON 2
54
55#define PAPD_BLANKING_PROFILE 3
56#define PAPD2LUT 0
57#define PAPD_CORR_NORM 0
58#define PAPD_BLANKING_THRESHOLD 0
59#define PAPD_STOP_AFTER_LAST_UPDATE 0
60
61#define LCN_TARGET_PWR 60
62
63#define LCN_VBAT_OFFSET_433X 34649679
64#define LCN_VBAT_SLOPE_433X 8258032
65
66#define LCN_VBAT_SCALE_NOM 53
67#define LCN_VBAT_SCALE_DEN 432
68
69#define LCN_TEMPSENSE_OFFSET 80812
70#define LCN_TEMPSENSE_DEN 2647
71
72#define LCN_BW_LMT 200
73#define LCN_CUR_LMT 1250
74#define LCN_MULT 1
75#define LCN_VCO_DIV 30
76#define LCN_OFFSET 680
77#define LCN_FACT 490
78#define LCN_CUR_DIV 2640
79
80#define LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT \
81 (0 + 8)
82#define LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK \
83 (0x7f << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT)
84
85#define LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT \
86 (0 + 8)
87#define LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_MASK \
88 (0x7f << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT)
89
90#define wlc_lcnphy_enable_tx_gain_override(pi) \
91 wlc_lcnphy_set_tx_gain_override(pi, true)
92#define wlc_lcnphy_disable_tx_gain_override(pi) \
93 wlc_lcnphy_set_tx_gain_override(pi, false)
94
95#define wlc_lcnphy_iqcal_active(pi) \
96 (read_phy_reg((pi), 0x451) & \
97 ((0x1 << 15) | (0x1 << 14)))
98
99#define txpwrctrl_off(pi) (0x7 != ((read_phy_reg(pi, 0x4a4) & 0xE000) >> 13))
100#define wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) \
101 (pi->temppwrctrl_capable)
102#define wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) \
103 (pi->hwpwrctrl_capable)
104
105#define SWCTRL_BT_TX 0x18
106#define SWCTRL_OVR_DISABLE 0x40
107
108#define AFE_CLK_INIT_MODE_TXRX2X 1
109#define AFE_CLK_INIT_MODE_PAPD 0
110
111#define LCNPHY_TBL_ID_IQLOCAL 0x00
112
113#define LCNPHY_TBL_ID_RFSEQ 0x08
114#define LCNPHY_TBL_ID_GAIN_IDX 0x0d
115#define LCNPHY_TBL_ID_SW_CTRL 0x0f
116#define LCNPHY_TBL_ID_GAIN_TBL 0x12
117#define LCNPHY_TBL_ID_SPUR 0x14
118#define LCNPHY_TBL_ID_SAMPLEPLAY 0x15
119#define LCNPHY_TBL_ID_SAMPLEPLAY1 0x16
120
121#define LCNPHY_TX_PWR_CTRL_RATE_OFFSET 832
122#define LCNPHY_TX_PWR_CTRL_MAC_OFFSET 128
123#define LCNPHY_TX_PWR_CTRL_GAIN_OFFSET 192
124#define LCNPHY_TX_PWR_CTRL_IQ_OFFSET 320
125#define LCNPHY_TX_PWR_CTRL_LO_OFFSET 448
126#define LCNPHY_TX_PWR_CTRL_PWR_OFFSET 576
127
128#define LCNPHY_TX_PWR_CTRL_START_INDEX_2G_4313 140
129
130#define LCNPHY_TX_PWR_CTRL_START_NPT 1
131#define LCNPHY_TX_PWR_CTRL_MAX_NPT 7
132
133#define LCNPHY_NOISE_SAMPLES_DEFAULT 5000
134
135#define LCNPHY_ACI_DETECT_START 1
136#define LCNPHY_ACI_DETECT_PROGRESS 2
137#define LCNPHY_ACI_DETECT_STOP 3
138
139#define LCNPHY_ACI_CRSHIFRMLO_TRSH 100
140#define LCNPHY_ACI_GLITCH_TRSH 2000
141#define LCNPHY_ACI_TMOUT 250
142#define LCNPHY_ACI_DETECT_TIMEOUT 2
143#define LCNPHY_ACI_START_DELAY 0
144
145#define wlc_lcnphy_tx_gain_override_enabled(pi) \
146 (0 != (read_phy_reg((pi), 0x43b) & (0x1 << 6)))
147
148#define wlc_lcnphy_total_tx_frames(pi) \
149 wlapi_bmac_read_shm((pi)->sh->physhim, M_UCODE_MACSTAT + \
150 offsetof(struct macstat, txallfrm))
151
152struct lcnphy_txgains {
153 u16 gm_gain;
154 u16 pga_gain;
155 u16 pad_gain;
156 u16 dac_gain;
157};
158
159enum lcnphy_cal_mode {
160 LCNPHY_CAL_FULL,
161 LCNPHY_CAL_RECAL,
162 LCNPHY_CAL_CURRECAL,
163 LCNPHY_CAL_DIGCAL,
164 LCNPHY_CAL_GCTRL
165};
166
167struct lcnphy_rx_iqcomp {
168 u8 chan;
169 s16 a;
170 s16 b;
171};
172
173struct lcnphy_spb_tone {
174 s16 re;
175 s16 im;
176};
177
178struct lcnphy_unsign16_struct {
179 u16 re;
180 u16 im;
181};
182
183struct lcnphy_iq_est {
184 u32 iq_prod;
185 u32 i_pwr;
186 u32 q_pwr;
187};
188
189struct lcnphy_sfo_cfg {
190 u16 ptcentreTs20;
191 u16 ptcentreFactor;
192};
193
194enum lcnphy_papd_cal_type {
195 LCNPHY_PAPD_CAL_CW,
196 LCNPHY_PAPD_CAL_OFDM
197};
198
199typedef u16 iqcal_gain_params_lcnphy[9];
200
201static const iqcal_gain_params_lcnphy tbl_iqcal_gainparams_lcnphy_2G[] = {
202 {0, 0, 0, 0, 0, 0, 0, 0, 0},
203};
204
205static const iqcal_gain_params_lcnphy *tbl_iqcal_gainparams_lcnphy[1] = {
206 tbl_iqcal_gainparams_lcnphy_2G,
207};
208
209static const u16 iqcal_gainparams_numgains_lcnphy[1] = {
210 sizeof(tbl_iqcal_gainparams_lcnphy_2G) /
211 sizeof(*tbl_iqcal_gainparams_lcnphy_2G),
212};
213
214static const struct lcnphy_sfo_cfg lcnphy_sfo_cfg[] = {
215 {965, 1087},
216 {967, 1085},
217 {969, 1082},
218 {971, 1080},
219 {973, 1078},
220 {975, 1076},
221 {977, 1073},
222 {979, 1071},
223 {981, 1069},
224 {983, 1067},
225 {985, 1065},
226 {987, 1063},
227 {989, 1060},
228 {994, 1055}
229};
230
231static const
232u16 lcnphy_iqcal_loft_gainladder[] = {
233 ((2 << 8) | 0),
234 ((3 << 8) | 0),
235 ((4 << 8) | 0),
236 ((6 << 8) | 0),
237 ((8 << 8) | 0),
238 ((11 << 8) | 0),
239 ((16 << 8) | 0),
240 ((16 << 8) | 1),
241 ((16 << 8) | 2),
242 ((16 << 8) | 3),
243 ((16 << 8) | 4),
244 ((16 << 8) | 5),
245 ((16 << 8) | 6),
246 ((16 << 8) | 7),
247 ((23 << 8) | 7),
248 ((32 << 8) | 7),
249 ((45 << 8) | 7),
250 ((64 << 8) | 7),
251 ((91 << 8) | 7),
252 ((128 << 8) | 7)
253};
254
255static const
256u16 lcnphy_iqcal_ir_gainladder[] = {
257 ((1 << 8) | 0),
258 ((2 << 8) | 0),
259 ((4 << 8) | 0),
260 ((6 << 8) | 0),
261 ((8 << 8) | 0),
262 ((11 << 8) | 0),
263 ((16 << 8) | 0),
264 ((23 << 8) | 0),
265 ((32 << 8) | 0),
266 ((45 << 8) | 0),
267 ((64 << 8) | 0),
268 ((64 << 8) | 1),
269 ((64 << 8) | 2),
270 ((64 << 8) | 3),
271 ((64 << 8) | 4),
272 ((64 << 8) | 5),
273 ((64 << 8) | 6),
274 ((64 << 8) | 7),
275 ((91 << 8) | 7),
276 ((128 << 8) | 7)
277};
278
279static const
280struct lcnphy_spb_tone lcnphy_spb_tone_3750[] = {
281 {88, 0},
282 {73, 49},
283 {34, 81},
284 {-17, 86},
285 {-62, 62},
286 {-86, 17},
287 {-81, -34},
288 {-49, -73},
289 {0, -88},
290 {49, -73},
291 {81, -34},
292 {86, 17},
293 {62, 62},
294 {17, 86},
295 {-34, 81},
296 {-73, 49},
297 {-88, 0},
298 {-73, -49},
299 {-34, -81},
300 {17, -86},
301 {62, -62},
302 {86, -17},
303 {81, 34},
304 {49, 73},
305 {0, 88},
306 {-49, 73},
307 {-81, 34},
308 {-86, -17},
309 {-62, -62},
310 {-17, -86},
311 {34, -81},
312 {73, -49},
313};
314
315static const
316u16 iqlo_loopback_rf_regs[20] = {
317 RADIO_2064_REG036,
318 RADIO_2064_REG11A,
319 RADIO_2064_REG03A,
320 RADIO_2064_REG025,
321 RADIO_2064_REG028,
322 RADIO_2064_REG005,
323 RADIO_2064_REG112,
324 RADIO_2064_REG0FF,
325 RADIO_2064_REG11F,
326 RADIO_2064_REG00B,
327 RADIO_2064_REG113,
328 RADIO_2064_REG007,
329 RADIO_2064_REG0FC,
330 RADIO_2064_REG0FD,
331 RADIO_2064_REG012,
332 RADIO_2064_REG057,
333 RADIO_2064_REG059,
334 RADIO_2064_REG05C,
335 RADIO_2064_REG078,
336 RADIO_2064_REG092,
337};
338
339static const
340u16 tempsense_phy_regs[14] = {
341 0x503,
342 0x4a4,
343 0x4d0,
344 0x4d9,
345 0x4da,
346 0x4a6,
347 0x938,
348 0x939,
349 0x4d8,
350 0x4d0,
351 0x4d7,
352 0x4a5,
353 0x40d,
354 0x4a2,
355};
356
357static const
358u16 rxiq_cal_rf_reg[11] = {
359 RADIO_2064_REG098,
360 RADIO_2064_REG116,
361 RADIO_2064_REG12C,
362 RADIO_2064_REG06A,
363 RADIO_2064_REG00B,
364 RADIO_2064_REG01B,
365 RADIO_2064_REG113,
366 RADIO_2064_REG01D,
367 RADIO_2064_REG114,
368 RADIO_2064_REG02E,
369 RADIO_2064_REG12A,
370};
371
372static const
373struct lcnphy_rx_iqcomp lcnphy_rx_iqcomp_table_rev0[] = {
374 {1, 0, 0},
375 {2, 0, 0},
376 {3, 0, 0},
377 {4, 0, 0},
378 {5, 0, 0},
379 {6, 0, 0},
380 {7, 0, 0},
381 {8, 0, 0},
382 {9, 0, 0},
383 {10, 0, 0},
384 {11, 0, 0},
385 {12, 0, 0},
386 {13, 0, 0},
387 {14, 0, 0},
388 {34, 0, 0},
389 {38, 0, 0},
390 {42, 0, 0},
391 {46, 0, 0},
392 {36, 0, 0},
393 {40, 0, 0},
394 {44, 0, 0},
395 {48, 0, 0},
396 {52, 0, 0},
397 {56, 0, 0},
398 {60, 0, 0},
399 {64, 0, 0},
400 {100, 0, 0},
401 {104, 0, 0},
402 {108, 0, 0},
403 {112, 0, 0},
404 {116, 0, 0},
405 {120, 0, 0},
406 {124, 0, 0},
407 {128, 0, 0},
408 {132, 0, 0},
409 {136, 0, 0},
410 {140, 0, 0},
411 {149, 0, 0},
412 {153, 0, 0},
413 {157, 0, 0},
414 {161, 0, 0},
415 {165, 0, 0},
416 {184, 0, 0},
417 {188, 0, 0},
418 {192, 0, 0},
419 {196, 0, 0},
420 {200, 0, 0},
421 {204, 0, 0},
422 {208, 0, 0},
423 {212, 0, 0},
424 {216, 0, 0},
425};
426
427static const u32 lcnphy_23bitgaincode_table[] = {
428 0x200100,
429 0x200200,
430 0x200004,
431 0x200014,
432 0x200024,
433 0x200034,
434 0x200134,
435 0x200234,
436 0x200334,
437 0x200434,
438 0x200037,
439 0x200137,
440 0x200237,
441 0x200337,
442 0x200437,
443 0x000035,
444 0x000135,
445 0x000235,
446 0x000037,
447 0x000137,
448 0x000237,
449 0x000337,
450 0x00013f,
451 0x00023f,
452 0x00033f,
453 0x00034f,
454 0x00044f,
455 0x00144f,
456 0x00244f,
457 0x00254f,
458 0x00354f,
459 0x00454f,
460 0x00464f,
461 0x01464f,
462 0x02464f,
463 0x03464f,
464 0x04464f,
465};
466
467static const s8 lcnphy_gain_table[] = {
468 -16,
469 -13,
470 10,
471 7,
472 4,
473 0,
474 3,
475 6,
476 9,
477 12,
478 15,
479 18,
480 21,
481 24,
482 27,
483 30,
484 33,
485 36,
486 39,
487 42,
488 45,
489 48,
490 50,
491 53,
492 56,
493 59,
494 62,
495 65,
496 68,
497 71,
498 74,
499 77,
500 80,
501 83,
502 86,
503 89,
504 92,
505};
506
507static const s8 lcnphy_gain_index_offset_for_rssi[] = {
508 7,
509 7,
510 7,
511 7,
512 7,
513 7,
514 7,
515 8,
516 7,
517 7,
518 6,
519 7,
520 7,
521 4,
522 4,
523 4,
524 4,
525 4,
526 4,
527 4,
528 4,
529 3,
530 3,
531 3,
532 3,
533 3,
534 3,
535 4,
536 2,
537 2,
538 2,
539 2,
540 2,
541 2,
542 -1,
543 -2,
544 -2,
545 -2
546};
547
548struct chan_info_2064_lcnphy {
549 uint chan;
550 uint freq;
551 u8 logen_buftune;
552 u8 logen_rccr_tx;
553 u8 txrf_mix_tune_ctrl;
554 u8 pa_input_tune_g;
555 u8 logen_rccr_rx;
556 u8 pa_rxrf_lna1_freq_tune;
557 u8 pa_rxrf_lna2_freq_tune;
558 u8 rxrf_rxrf_spare1;
559};
560
561static const struct chan_info_2064_lcnphy chan_info_2064_lcnphy[] = {
562 {1, 2412, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
563 {2, 2417, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
564 {3, 2422, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
565 {4, 2427, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
566 {5, 2432, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
567 {6, 2437, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
568 {7, 2442, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
569 {8, 2447, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
570 {9, 2452, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
571 {10, 2457, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
572 {11, 2462, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
573 {12, 2467, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
574 {13, 2472, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
575 {14, 2484, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
576};
577
578static const struct lcnphy_radio_regs lcnphy_radio_regs_2064[] = {
579 {0x00, 0, 0, 0, 0},
580 {0x01, 0x64, 0x64, 0, 0},
581 {0x02, 0x20, 0x20, 0, 0},
582 {0x03, 0x66, 0x66, 0, 0},
583 {0x04, 0xf8, 0xf8, 0, 0},
584 {0x05, 0, 0, 0, 0},
585 {0x06, 0x10, 0x10, 0, 0},
586 {0x07, 0, 0, 0, 0},
587 {0x08, 0, 0, 0, 0},
588 {0x09, 0, 0, 0, 0},
589 {0x0A, 0x37, 0x37, 0, 0},
590 {0x0B, 0x6, 0x6, 0, 0},
591 {0x0C, 0x55, 0x55, 0, 0},
592 {0x0D, 0x8b, 0x8b, 0, 0},
593 {0x0E, 0, 0, 0, 0},
594 {0x0F, 0x5, 0x5, 0, 0},
595 {0x10, 0, 0, 0, 0},
596 {0x11, 0xe, 0xe, 0, 0},
597 {0x12, 0, 0, 0, 0},
598 {0x13, 0xb, 0xb, 0, 0},
599 {0x14, 0x2, 0x2, 0, 0},
600 {0x15, 0x12, 0x12, 0, 0},
601 {0x16, 0x12, 0x12, 0, 0},
602 {0x17, 0xc, 0xc, 0, 0},
603 {0x18, 0xc, 0xc, 0, 0},
604 {0x19, 0xc, 0xc, 0, 0},
605 {0x1A, 0x8, 0x8, 0, 0},
606 {0x1B, 0x2, 0x2, 0, 0},
607 {0x1C, 0, 0, 0, 0},
608 {0x1D, 0x1, 0x1, 0, 0},
609 {0x1E, 0x12, 0x12, 0, 0},
610 {0x1F, 0x6e, 0x6e, 0, 0},
611 {0x20, 0x2, 0x2, 0, 0},
612 {0x21, 0x23, 0x23, 0, 0},
613 {0x22, 0x8, 0x8, 0, 0},
614 {0x23, 0, 0, 0, 0},
615 {0x24, 0, 0, 0, 0},
616 {0x25, 0xc, 0xc, 0, 0},
617 {0x26, 0x33, 0x33, 0, 0},
618 {0x27, 0x55, 0x55, 0, 0},
619 {0x28, 0, 0, 0, 0},
620 {0x29, 0x30, 0x30, 0, 0},
621 {0x2A, 0xb, 0xb, 0, 0},
622 {0x2B, 0x1b, 0x1b, 0, 0},
623 {0x2C, 0x3, 0x3, 0, 0},
624 {0x2D, 0x1b, 0x1b, 0, 0},
625 {0x2E, 0, 0, 0, 0},
626 {0x2F, 0x20, 0x20, 0, 0},
627 {0x30, 0xa, 0xa, 0, 0},
628 {0x31, 0, 0, 0, 0},
629 {0x32, 0x62, 0x62, 0, 0},
630 {0x33, 0x19, 0x19, 0, 0},
631 {0x34, 0x33, 0x33, 0, 0},
632 {0x35, 0x77, 0x77, 0, 0},
633 {0x36, 0, 0, 0, 0},
634 {0x37, 0x70, 0x70, 0, 0},
635 {0x38, 0x3, 0x3, 0, 0},
636 {0x39, 0xf, 0xf, 0, 0},
637 {0x3A, 0x6, 0x6, 0, 0},
638 {0x3B, 0xcf, 0xcf, 0, 0},
639 {0x3C, 0x1a, 0x1a, 0, 0},
640 {0x3D, 0x6, 0x6, 0, 0},
641 {0x3E, 0x42, 0x42, 0, 0},
642 {0x3F, 0, 0, 0, 0},
643 {0x40, 0xfb, 0xfb, 0, 0},
644 {0x41, 0x9a, 0x9a, 0, 0},
645 {0x42, 0x7a, 0x7a, 0, 0},
646 {0x43, 0x29, 0x29, 0, 0},
647 {0x44, 0, 0, 0, 0},
648 {0x45, 0x8, 0x8, 0, 0},
649 {0x46, 0xce, 0xce, 0, 0},
650 {0x47, 0x27, 0x27, 0, 0},
651 {0x48, 0x62, 0x62, 0, 0},
652 {0x49, 0x6, 0x6, 0, 0},
653 {0x4A, 0x58, 0x58, 0, 0},
654 {0x4B, 0xf7, 0xf7, 0, 0},
655 {0x4C, 0, 0, 0, 0},
656 {0x4D, 0xb3, 0xb3, 0, 0},
657 {0x4E, 0, 0, 0, 0},
658 {0x4F, 0x2, 0x2, 0, 0},
659 {0x50, 0, 0, 0, 0},
660 {0x51, 0x9, 0x9, 0, 0},
661 {0x52, 0x5, 0x5, 0, 0},
662 {0x53, 0x17, 0x17, 0, 0},
663 {0x54, 0x38, 0x38, 0, 0},
664 {0x55, 0, 0, 0, 0},
665 {0x56, 0, 0, 0, 0},
666 {0x57, 0xb, 0xb, 0, 0},
667 {0x58, 0, 0, 0, 0},
668 {0x59, 0, 0, 0, 0},
669 {0x5A, 0, 0, 0, 0},
670 {0x5B, 0, 0, 0, 0},
671 {0x5C, 0, 0, 0, 0},
672 {0x5D, 0, 0, 0, 0},
673 {0x5E, 0x88, 0x88, 0, 0},
674 {0x5F, 0xcc, 0xcc, 0, 0},
675 {0x60, 0x74, 0x74, 0, 0},
676 {0x61, 0x74, 0x74, 0, 0},
677 {0x62, 0x74, 0x74, 0, 0},
678 {0x63, 0x44, 0x44, 0, 0},
679 {0x64, 0x77, 0x77, 0, 0},
680 {0x65, 0x44, 0x44, 0, 0},
681 {0x66, 0x77, 0x77, 0, 0},
682 {0x67, 0x55, 0x55, 0, 0},
683 {0x68, 0x77, 0x77, 0, 0},
684 {0x69, 0x77, 0x77, 0, 0},
685 {0x6A, 0, 0, 0, 0},
686 {0x6B, 0x7f, 0x7f, 0, 0},
687 {0x6C, 0x8, 0x8, 0, 0},
688 {0x6D, 0, 0, 0, 0},
689 {0x6E, 0x88, 0x88, 0, 0},
690 {0x6F, 0x66, 0x66, 0, 0},
691 {0x70, 0x66, 0x66, 0, 0},
692 {0x71, 0x28, 0x28, 0, 0},
693 {0x72, 0x55, 0x55, 0, 0},
694 {0x73, 0x4, 0x4, 0, 0},
695 {0x74, 0, 0, 0, 0},
696 {0x75, 0, 0, 0, 0},
697 {0x76, 0, 0, 0, 0},
698 {0x77, 0x1, 0x1, 0, 0},
699 {0x78, 0xd6, 0xd6, 0, 0},
700 {0x79, 0, 0, 0, 0},
701 {0x7A, 0, 0, 0, 0},
702 {0x7B, 0, 0, 0, 0},
703 {0x7C, 0, 0, 0, 0},
704 {0x7D, 0, 0, 0, 0},
705 {0x7E, 0, 0, 0, 0},
706 {0x7F, 0, 0, 0, 0},
707 {0x80, 0, 0, 0, 0},
708 {0x81, 0, 0, 0, 0},
709 {0x82, 0, 0, 0, 0},
710 {0x83, 0xb4, 0xb4, 0, 0},
711 {0x84, 0x1, 0x1, 0, 0},
712 {0x85, 0x20, 0x20, 0, 0},
713 {0x86, 0x5, 0x5, 0, 0},
714 {0x87, 0xff, 0xff, 0, 0},
715 {0x88, 0x7, 0x7, 0, 0},
716 {0x89, 0x77, 0x77, 0, 0},
717 {0x8A, 0x77, 0x77, 0, 0},
718 {0x8B, 0x77, 0x77, 0, 0},
719 {0x8C, 0x77, 0x77, 0, 0},
720 {0x8D, 0x8, 0x8, 0, 0},
721 {0x8E, 0xa, 0xa, 0, 0},
722 {0x8F, 0x8, 0x8, 0, 0},
723 {0x90, 0x18, 0x18, 0, 0},
724 {0x91, 0x5, 0x5, 0, 0},
725 {0x92, 0x1f, 0x1f, 0, 0},
726 {0x93, 0x10, 0x10, 0, 0},
727 {0x94, 0x3, 0x3, 0, 0},
728 {0x95, 0, 0, 0, 0},
729 {0x96, 0, 0, 0, 0},
730 {0x97, 0xaa, 0xaa, 0, 0},
731 {0x98, 0, 0, 0, 0},
732 {0x99, 0x23, 0x23, 0, 0},
733 {0x9A, 0x7, 0x7, 0, 0},
734 {0x9B, 0xf, 0xf, 0, 0},
735 {0x9C, 0x10, 0x10, 0, 0},
736 {0x9D, 0x3, 0x3, 0, 0},
737 {0x9E, 0x4, 0x4, 0, 0},
738 {0x9F, 0x20, 0x20, 0, 0},
739 {0xA0, 0, 0, 0, 0},
740 {0xA1, 0, 0, 0, 0},
741 {0xA2, 0, 0, 0, 0},
742 {0xA3, 0, 0, 0, 0},
743 {0xA4, 0x1, 0x1, 0, 0},
744 {0xA5, 0x77, 0x77, 0, 0},
745 {0xA6, 0x77, 0x77, 0, 0},
746 {0xA7, 0x77, 0x77, 0, 0},
747 {0xA8, 0x77, 0x77, 0, 0},
748 {0xA9, 0x8c, 0x8c, 0, 0},
749 {0xAA, 0x88, 0x88, 0, 0},
750 {0xAB, 0x78, 0x78, 0, 0},
751 {0xAC, 0x57, 0x57, 0, 0},
752 {0xAD, 0x88, 0x88, 0, 0},
753 {0xAE, 0, 0, 0, 0},
754 {0xAF, 0x8, 0x8, 0, 0},
755 {0xB0, 0x88, 0x88, 0, 0},
756 {0xB1, 0, 0, 0, 0},
757 {0xB2, 0x1b, 0x1b, 0, 0},
758 {0xB3, 0x3, 0x3, 0, 0},
759 {0xB4, 0x24, 0x24, 0, 0},
760 {0xB5, 0x3, 0x3, 0, 0},
761 {0xB6, 0x1b, 0x1b, 0, 0},
762 {0xB7, 0x24, 0x24, 0, 0},
763 {0xB8, 0x3, 0x3, 0, 0},
764 {0xB9, 0, 0, 0, 0},
765 {0xBA, 0xaa, 0xaa, 0, 0},
766 {0xBB, 0, 0, 0, 0},
767 {0xBC, 0x4, 0x4, 0, 0},
768 {0xBD, 0, 0, 0, 0},
769 {0xBE, 0x8, 0x8, 0, 0},
770 {0xBF, 0x11, 0x11, 0, 0},
771 {0xC0, 0, 0, 0, 0},
772 {0xC1, 0, 0, 0, 0},
773 {0xC2, 0x62, 0x62, 0, 0},
774 {0xC3, 0x1e, 0x1e, 0, 0},
775 {0xC4, 0x33, 0x33, 0, 0},
776 {0xC5, 0x37, 0x37, 0, 0},
777 {0xC6, 0, 0, 0, 0},
778 {0xC7, 0x70, 0x70, 0, 0},
779 {0xC8, 0x1e, 0x1e, 0, 0},
780 {0xC9, 0x6, 0x6, 0, 0},
781 {0xCA, 0x4, 0x4, 0, 0},
782 {0xCB, 0x2f, 0x2f, 0, 0},
783 {0xCC, 0xf, 0xf, 0, 0},
784 {0xCD, 0, 0, 0, 0},
785 {0xCE, 0xff, 0xff, 0, 0},
786 {0xCF, 0x8, 0x8, 0, 0},
787 {0xD0, 0x3f, 0x3f, 0, 0},
788 {0xD1, 0x3f, 0x3f, 0, 0},
789 {0xD2, 0x3f, 0x3f, 0, 0},
790 {0xD3, 0, 0, 0, 0},
791 {0xD4, 0, 0, 0, 0},
792 {0xD5, 0, 0, 0, 0},
793 {0xD6, 0xcc, 0xcc, 0, 0},
794 {0xD7, 0, 0, 0, 0},
795 {0xD8, 0x8, 0x8, 0, 0},
796 {0xD9, 0x8, 0x8, 0, 0},
797 {0xDA, 0x8, 0x8, 0, 0},
798 {0xDB, 0x11, 0x11, 0, 0},
799 {0xDC, 0, 0, 0, 0},
800 {0xDD, 0x87, 0x87, 0, 0},
801 {0xDE, 0x88, 0x88, 0, 0},
802 {0xDF, 0x8, 0x8, 0, 0},
803 {0xE0, 0x8, 0x8, 0, 0},
804 {0xE1, 0x8, 0x8, 0, 0},
805 {0xE2, 0, 0, 0, 0},
806 {0xE3, 0, 0, 0, 0},
807 {0xE4, 0, 0, 0, 0},
808 {0xE5, 0xf5, 0xf5, 0, 0},
809 {0xE6, 0x30, 0x30, 0, 0},
810 {0xE7, 0x1, 0x1, 0, 0},
811 {0xE8, 0, 0, 0, 0},
812 {0xE9, 0xff, 0xff, 0, 0},
813 {0xEA, 0, 0, 0, 0},
814 {0xEB, 0, 0, 0, 0},
815 {0xEC, 0x22, 0x22, 0, 0},
816 {0xED, 0, 0, 0, 0},
817 {0xEE, 0, 0, 0, 0},
818 {0xEF, 0, 0, 0, 0},
819 {0xF0, 0x3, 0x3, 0, 0},
820 {0xF1, 0x1, 0x1, 0, 0},
821 {0xF2, 0, 0, 0, 0},
822 {0xF3, 0, 0, 0, 0},
823 {0xF4, 0, 0, 0, 0},
824 {0xF5, 0, 0, 0, 0},
825 {0xF6, 0, 0, 0, 0},
826 {0xF7, 0x6, 0x6, 0, 0},
827 {0xF8, 0, 0, 0, 0},
828 {0xF9, 0, 0, 0, 0},
829 {0xFA, 0x40, 0x40, 0, 0},
830 {0xFB, 0, 0, 0, 0},
831 {0xFC, 0x1, 0x1, 0, 0},
832 {0xFD, 0x80, 0x80, 0, 0},
833 {0xFE, 0x2, 0x2, 0, 0},
834 {0xFF, 0x10, 0x10, 0, 0},
835 {0x100, 0x2, 0x2, 0, 0},
836 {0x101, 0x1e, 0x1e, 0, 0},
837 {0x102, 0x1e, 0x1e, 0, 0},
838 {0x103, 0, 0, 0, 0},
839 {0x104, 0x1f, 0x1f, 0, 0},
840 {0x105, 0, 0x8, 0, 1},
841 {0x106, 0x2a, 0x2a, 0, 0},
842 {0x107, 0xf, 0xf, 0, 0},
843 {0x108, 0, 0, 0, 0},
844 {0x109, 0, 0, 0, 0},
845 {0x10A, 0, 0, 0, 0},
846 {0x10B, 0, 0, 0, 0},
847 {0x10C, 0, 0, 0, 0},
848 {0x10D, 0, 0, 0, 0},
849 {0x10E, 0, 0, 0, 0},
850 {0x10F, 0, 0, 0, 0},
851 {0x110, 0, 0, 0, 0},
852 {0x111, 0, 0, 0, 0},
853 {0x112, 0, 0, 0, 0},
854 {0x113, 0, 0, 0, 0},
855 {0x114, 0, 0, 0, 0},
856 {0x115, 0, 0, 0, 0},
857 {0x116, 0, 0, 0, 0},
858 {0x117, 0, 0, 0, 0},
859 {0x118, 0, 0, 0, 0},
860 {0x119, 0, 0, 0, 0},
861 {0x11A, 0, 0, 0, 0},
862 {0x11B, 0, 0, 0, 0},
863 {0x11C, 0x1, 0x1, 0, 0},
864 {0x11D, 0, 0, 0, 0},
865 {0x11E, 0, 0, 0, 0},
866 {0x11F, 0, 0, 0, 0},
867 {0x120, 0, 0, 0, 0},
868 {0x121, 0, 0, 0, 0},
869 {0x122, 0x80, 0x80, 0, 0},
870 {0x123, 0, 0, 0, 0},
871 {0x124, 0xf8, 0xf8, 0, 0},
872 {0x125, 0, 0, 0, 0},
873 {0x126, 0, 0, 0, 0},
874 {0x127, 0, 0, 0, 0},
875 {0x128, 0, 0, 0, 0},
876 {0x129, 0, 0, 0, 0},
877 {0x12A, 0, 0, 0, 0},
878 {0x12B, 0, 0, 0, 0},
879 {0x12C, 0, 0, 0, 0},
880 {0x12D, 0, 0, 0, 0},
881 {0x12E, 0, 0, 0, 0},
882 {0x12F, 0, 0, 0, 0},
883 {0x130, 0, 0, 0, 0},
884 {0xFFFF, 0, 0, 0, 0}
885};
886
887#define LCNPHY_NUM_DIG_FILT_COEFFS 16
888#define LCNPHY_NUM_TX_DIG_FILTERS_CCK 13
889
890static const u16 LCNPHY_txdigfiltcoeffs_cck[LCNPHY_NUM_TX_DIG_FILTERS_CCK]
891 [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = {
892 {0, 1, 415, 1874, 64, 128, 64, 792, 1656, 64, 128, 64, 778, 1582, 64,
893 128, 64,},
894 {1, 1, 402, 1847, 259, 59, 259, 671, 1794, 68, 54, 68, 608, 1863, 93,
895 167, 93,},
896 {2, 1, 415, 1874, 64, 128, 64, 792, 1656, 192, 384, 192, 778, 1582, 64,
897 128, 64,},
898 {3, 1, 302, 1841, 129, 258, 129, 658, 1720, 205, 410, 205, 754, 1760,
899 170, 340, 170,},
900 {20, 1, 360, 1884, 242, 1734, 242, 752, 1720, 205, 1845, 205, 767, 1760,
901 256, 185, 256,},
902 {21, 1, 360, 1884, 149, 1874, 149, 752, 1720, 205, 1883, 205, 767, 1760,
903 256, 273, 256,},
904 {22, 1, 360, 1884, 98, 1948, 98, 752, 1720, 205, 1924, 205, 767, 1760,
905 256, 352, 256,},
906 {23, 1, 350, 1884, 116, 1966, 116, 752, 1720, 205, 2008, 205, 767, 1760,
907 128, 233, 128,},
908 {24, 1, 325, 1884, 32, 40, 32, 756, 1720, 256, 471, 256, 766, 1760, 256,
909 1881, 256,},
910 {25, 1, 299, 1884, 51, 64, 51, 736, 1720, 256, 471, 256, 765, 1760, 256,
911 1881, 256,},
912 {26, 1, 277, 1943, 39, 117, 88, 637, 1838, 64, 192, 144, 614, 1864, 128,
913 384, 288,},
914 {27, 1, 245, 1943, 49, 147, 110, 626, 1838, 256, 768, 576, 613, 1864,
915 128, 384, 288,},
916 {30, 1, 302, 1841, 61, 122, 61, 658, 1720, 205, 410, 205, 754, 1760,
917 170, 340, 170,},
918};
919
920#define LCNPHY_NUM_TX_DIG_FILTERS_OFDM 3
921static const u16 LCNPHY_txdigfiltcoeffs_ofdm[LCNPHY_NUM_TX_DIG_FILTERS_OFDM]
922 [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = {
923 {0, 0, 0xa2, 0x0, 0x100, 0x100, 0x0, 0x0, 0x0, 0x100, 0x0, 0x0,
924 0x278, 0xfea0, 0x80, 0x100, 0x80,},
925 {1, 0, 374, 0xFF79, 16, 32, 16, 799, 0xFE74, 50, 32, 50,
926 750, 0xFE2B, 212, 0xFFCE, 212,},
927 {2, 0, 375, 0xFF16, 37, 76, 37, 799, 0xFE74, 32, 20, 32, 748,
928 0xFEF2, 128, 0xFFE2, 128}
929};
930
931#define wlc_lcnphy_set_start_tx_pwr_idx(pi, idx) \
932 mod_phy_reg(pi, 0x4a4, \
933 (0x1ff << 0), \
934 (u16)(idx) << 0)
935
936#define wlc_lcnphy_set_tx_pwr_npt(pi, npt) \
937 mod_phy_reg(pi, 0x4a5, \
938 (0x7 << 8), \
939 (u16)(npt) << 8)
940
941#define wlc_lcnphy_get_tx_pwr_ctrl(pi) \
942 (read_phy_reg((pi), 0x4a4) & \
943 ((0x1 << 15) | \
944 (0x1 << 14) | \
945 (0x1 << 13)))
946
947#define wlc_lcnphy_get_tx_pwr_npt(pi) \
948 ((read_phy_reg(pi, 0x4a5) & \
949 (0x7 << 8)) >> \
950 8)
951
952#define wlc_lcnphy_get_current_tx_pwr_idx_if_pwrctrl_on(pi) \
953 (read_phy_reg(pi, 0x473) & 0x1ff)
954
955#define wlc_lcnphy_get_target_tx_pwr(pi) \
956 ((read_phy_reg(pi, 0x4a7) & \
957 (0xff << 0)) >> \
958 0)
959
960#define wlc_lcnphy_set_target_tx_pwr(pi, target) \
961 mod_phy_reg(pi, 0x4a7, \
962 (0xff << 0), \
963 (u16)(target) << 0)
964
965#define wlc_radio_2064_rcal_done(pi) \
966 (0 != (read_radio_reg(pi, RADIO_2064_REG05C) & 0x20))
967
968#define tempsense_done(pi) \
969 (0x8000 == (read_phy_reg(pi, 0x476) & 0x8000))
970
971#define LCNPHY_IQLOCC_READ(val) \
972 ((u8)(-(s8)(((val) & 0xf0) >> 4) + (s8)((val) & 0x0f)))
973
974#define FIXED_TXPWR 78
975#define LCNPHY_TEMPSENSE(val) ((s16)((val > 255) ? (val - 512) : val))
976
977void wlc_lcnphy_write_table(struct brcms_phy *pi, const struct phytbl_info *pti)
978{
979 wlc_phy_write_table(pi, pti, 0x455, 0x457, 0x456);
980}
981
982void wlc_lcnphy_read_table(struct brcms_phy *pi, struct phytbl_info *pti)
983{
984 wlc_phy_read_table(pi, pti, 0x455, 0x457, 0x456);
985}
986
987static void
988wlc_lcnphy_common_read_table(struct brcms_phy *pi, u32 tbl_id,
989 const u16 *tbl_ptr, u32 tbl_len,
990 u32 tbl_width, u32 tbl_offset)
991{
992 struct phytbl_info tab;
993 tab.tbl_id = tbl_id;
994 tab.tbl_ptr = tbl_ptr;
995 tab.tbl_len = tbl_len;
996 tab.tbl_width = tbl_width;
997 tab.tbl_offset = tbl_offset;
998 wlc_lcnphy_read_table(pi, &tab);
999}
1000
1001static void
1002wlc_lcnphy_common_write_table(struct brcms_phy *pi, u32 tbl_id,
1003 const u16 *tbl_ptr, u32 tbl_len,
1004 u32 tbl_width, u32 tbl_offset)
1005{
1006
1007 struct phytbl_info tab;
1008 tab.tbl_id = tbl_id;
1009 tab.tbl_ptr = tbl_ptr;
1010 tab.tbl_len = tbl_len;
1011 tab.tbl_width = tbl_width;
1012 tab.tbl_offset = tbl_offset;
1013 wlc_lcnphy_write_table(pi, &tab);
1014}
1015
1016static u32
1017wlc_lcnphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1018{
1019 u32 quotient, remainder, roundup, rbit;
1020
1021 quotient = dividend / divisor;
1022 remainder = dividend % divisor;
1023 rbit = divisor & 1;
1024 roundup = (divisor >> 1) + rbit;
1025
1026 while (precision--) {
1027 quotient <<= 1;
1028 if (remainder >= roundup) {
1029 quotient++;
1030 remainder = ((remainder - roundup) << 1) + rbit;
1031 } else {
1032 remainder <<= 1;
1033 }
1034 }
1035
1036 if (remainder >= roundup)
1037 quotient++;
1038
1039 return quotient;
1040}
1041
1042static int wlc_lcnphy_calc_floor(s16 coeff_x, int type)
1043{
1044 int k;
1045 k = 0;
1046 if (type == 0) {
1047 if (coeff_x < 0)
1048 k = (coeff_x - 1) / 2;
1049 else
1050 k = coeff_x / 2;
1051 }
1052
1053 if (type == 1) {
1054 if ((coeff_x + 1) < 0)
1055 k = (coeff_x) / 2;
1056 else
1057 k = (coeff_x + 1) / 2;
1058 }
1059 return k;
1060}
1061
1062static void
1063wlc_lcnphy_get_tx_gain(struct brcms_phy *pi, struct lcnphy_txgains *gains)
1064{
1065 u16 dac_gain, rfgain0, rfgain1;
1066
1067 dac_gain = read_phy_reg(pi, 0x439) >> 0;
1068 gains->dac_gain = (dac_gain & 0x380) >> 7;
1069
1070 rfgain0 = (read_phy_reg(pi, 0x4b5) & (0xffff << 0)) >> 0;
1071 rfgain1 = (read_phy_reg(pi, 0x4fb) & (0x7fff << 0)) >> 0;
1072
1073 gains->gm_gain = rfgain0 & 0xff;
1074 gains->pga_gain = (rfgain0 >> 8) & 0xff;
1075 gains->pad_gain = rfgain1 & 0xff;
1076}
1077
1078
1079static void wlc_lcnphy_set_dac_gain(struct brcms_phy *pi, u16 dac_gain)
1080{
1081 u16 dac_ctrl;
1082
1083 dac_ctrl = (read_phy_reg(pi, 0x439) >> 0);
1084 dac_ctrl = dac_ctrl & 0xc7f;
1085 dac_ctrl = dac_ctrl | (dac_gain << 7);
1086 mod_phy_reg(pi, 0x439, (0xfff << 0), (dac_ctrl) << 0);
1087
1088}
1089
1090static void wlc_lcnphy_set_tx_gain_override(struct brcms_phy *pi, bool bEnable)
1091{
1092 u16 bit = bEnable ? 1 : 0;
1093
1094 mod_phy_reg(pi, 0x4b0, (0x1 << 7), bit << 7);
1095
1096 mod_phy_reg(pi, 0x4b0, (0x1 << 14), bit << 14);
1097
1098 mod_phy_reg(pi, 0x43b, (0x1 << 6), bit << 6);
1099}
1100
1101static void
1102wlc_lcnphy_rx_gain_override_enable(struct brcms_phy *pi, bool enable)
1103{
1104 u16 ebit = enable ? 1 : 0;
1105
1106 mod_phy_reg(pi, 0x4b0, (0x1 << 8), ebit << 8);
1107
1108 mod_phy_reg(pi, 0x44c, (0x1 << 0), ebit << 0);
1109
1110 if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
1111 mod_phy_reg(pi, 0x44c, (0x1 << 4), ebit << 4);
1112 mod_phy_reg(pi, 0x44c, (0x1 << 6), ebit << 6);
1113 mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5);
1114 mod_phy_reg(pi, 0x4b0, (0x1 << 6), ebit << 6);
1115 } else {
1116 mod_phy_reg(pi, 0x4b0, (0x1 << 12), ebit << 12);
1117 mod_phy_reg(pi, 0x4b0, (0x1 << 13), ebit << 13);
1118 mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5);
1119 }
1120
1121 if (CHSPEC_IS2G(pi->radio_chanspec)) {
1122 mod_phy_reg(pi, 0x4b0, (0x1 << 10), ebit << 10);
1123 mod_phy_reg(pi, 0x4e5, (0x1 << 3), ebit << 3);
1124 }
1125}
1126
1127static void
1128wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi,
1129 u16 trsw,
1130 u16 ext_lna,
1131 u16 biq2,
1132 u16 biq1,
1133 u16 tia, u16 lna2, u16 lna1)
1134{
1135 u16 gain0_15, gain16_19;
1136
1137 gain16_19 = biq2 & 0xf;
1138 gain0_15 = ((biq1 & 0xf) << 12) |
1139 ((tia & 0xf) << 8) |
1140 ((lna2 & 0x3) << 6) |
1141 ((lna2 &
1142 0x3) << 4) | ((lna1 & 0x3) << 2) | ((lna1 & 0x3) << 0);
1143
1144 mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
1145 mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
1146 mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
1147
1148 if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
1149 mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
1150 mod_phy_reg(pi, 0x4b1, (0x1 << 10), ext_lna << 10);
1151 } else {
1152 mod_phy_reg(pi, 0x4b1, (0x1 << 10), 0 << 10);
1153
1154 mod_phy_reg(pi, 0x4b1, (0x1 << 15), 0 << 15);
1155
1156 mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
1157 }
1158
1159 mod_phy_reg(pi, 0x44d, (0x1 << 0), (!trsw) << 0);
1160
1161}
1162
1163static void wlc_lcnphy_set_trsw_override(struct brcms_phy *pi, bool tx, bool rx)
1164{
1165
1166 mod_phy_reg(pi, 0x44d,
1167 (0x1 << 1) |
1168 (0x1 << 0), (tx ? (0x1 << 1) : 0) | (rx ? (0x1 << 0) : 0));
1169
1170 or_phy_reg(pi, 0x44c, (0x1 << 1) | (0x1 << 0));
1171}
1172
1173static void wlc_lcnphy_clear_trsw_override(struct brcms_phy *pi)
1174{
1175
1176 and_phy_reg(pi, 0x44c, (u16) ~((0x1 << 1) | (0x1 << 0)));
1177}
1178
1179static void wlc_lcnphy_set_rx_iq_comp(struct brcms_phy *pi, u16 a, u16 b)
1180{
1181 mod_phy_reg(pi, 0x645, (0x3ff << 0), (a) << 0);
1182
1183 mod_phy_reg(pi, 0x646, (0x3ff << 0), (b) << 0);
1184
1185 mod_phy_reg(pi, 0x647, (0x3ff << 0), (a) << 0);
1186
1187 mod_phy_reg(pi, 0x648, (0x3ff << 0), (b) << 0);
1188
1189 mod_phy_reg(pi, 0x649, (0x3ff << 0), (a) << 0);
1190
1191 mod_phy_reg(pi, 0x64a, (0x3ff << 0), (b) << 0);
1192
1193}
1194
1195static bool
1196wlc_lcnphy_rx_iq_est(struct brcms_phy *pi,
1197 u16 num_samps,
1198 u8 wait_time, struct lcnphy_iq_est *iq_est)
1199{
1200 int wait_count = 0;
1201 bool result = true;
1202 u8 phybw40;
1203 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
1204
1205 mod_phy_reg(pi, 0x6da, (0x1 << 5), (1) << 5);
1206
1207 mod_phy_reg(pi, 0x410, (0x1 << 3), (0) << 3);
1208
1209 mod_phy_reg(pi, 0x482, (0xffff << 0), (num_samps) << 0);
1210
1211 mod_phy_reg(pi, 0x481, (0xff << 0), ((u16) wait_time) << 0);
1212
1213 mod_phy_reg(pi, 0x481, (0x1 << 8), (0) << 8);
1214
1215 mod_phy_reg(pi, 0x481, (0x1 << 9), (1) << 9);
1216
1217 while (read_phy_reg(pi, 0x481) & (0x1 << 9)) {
1218
1219 if (wait_count > (10 * 500)) {
1220 result = false;
1221 goto cleanup;
1222 }
1223 udelay(100);
1224 wait_count++;
1225 }
1226
1227 iq_est->iq_prod = ((u32) read_phy_reg(pi, 0x483) << 16) |
1228 (u32) read_phy_reg(pi, 0x484);
1229 iq_est->i_pwr = ((u32) read_phy_reg(pi, 0x485) << 16) |
1230 (u32) read_phy_reg(pi, 0x486);
1231 iq_est->q_pwr = ((u32) read_phy_reg(pi, 0x487) << 16) |
1232 (u32) read_phy_reg(pi, 0x488);
1233
1234cleanup:
1235 mod_phy_reg(pi, 0x410, (0x1 << 3), (1) << 3);
1236
1237 mod_phy_reg(pi, 0x6da, (0x1 << 5), (0) << 5);
1238
1239 return result;
1240}
1241
1242static bool wlc_lcnphy_calc_rx_iq_comp(struct brcms_phy *pi, u16 num_samps)
1243{
1244#define LCNPHY_MIN_RXIQ_PWR 2
1245 bool result;
1246 u16 a0_new, b0_new;
1247 struct lcnphy_iq_est iq_est = { 0, 0, 0 };
1248 s32 a, b, temp;
1249 s16 iq_nbits, qq_nbits, arsh, brsh;
1250 s32 iq;
1251 u32 ii, qq;
1252 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1253
1254 a0_new = ((read_phy_reg(pi, 0x645) & (0x3ff << 0)) >> 0);
1255 b0_new = ((read_phy_reg(pi, 0x646) & (0x3ff << 0)) >> 0);
1256 mod_phy_reg(pi, 0x6d1, (0x1 << 2), (0) << 2);
1257
1258 mod_phy_reg(pi, 0x64b, (0x1 << 6), (1) << 6);
1259
1260 wlc_lcnphy_set_rx_iq_comp(pi, 0, 0);
1261
1262 result = wlc_lcnphy_rx_iq_est(pi, num_samps, 32, &iq_est);
1263 if (!result)
1264 goto cleanup;
1265
1266 iq = (s32) iq_est.iq_prod;
1267 ii = iq_est.i_pwr;
1268 qq = iq_est.q_pwr;
1269
1270 if ((ii + qq) < LCNPHY_MIN_RXIQ_PWR) {
1271 result = false;
1272 goto cleanup;
1273 }
1274
1275 iq_nbits = wlc_phy_nbits(iq);
1276 qq_nbits = wlc_phy_nbits(qq);
1277
1278 arsh = 10 - (30 - iq_nbits);
1279 if (arsh >= 0) {
1280 a = (-(iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
1281 temp = (s32) (ii >> arsh);
1282 if (temp == 0)
1283 return false;
1284 } else {
1285 a = (-(iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
1286 temp = (s32) (ii << -arsh);
1287 if (temp == 0)
1288 return false;
1289 }
1290 a /= temp;
1291 brsh = qq_nbits - 31 + 20;
1292 if (brsh >= 0) {
1293 b = (qq << (31 - qq_nbits));
1294 temp = (s32) (ii >> brsh);
1295 if (temp == 0)
1296 return false;
1297 } else {
1298 b = (qq << (31 - qq_nbits));
1299 temp = (s32) (ii << -brsh);
1300 if (temp == 0)
1301 return false;
1302 }
1303 b /= temp;
1304 b -= a * a;
1305 b = (s32) int_sqrt((unsigned long) b);
1306 b -= (1 << 10);
1307 a0_new = (u16) (a & 0x3ff);
1308 b0_new = (u16) (b & 0x3ff);
1309cleanup:
1310
1311 wlc_lcnphy_set_rx_iq_comp(pi, a0_new, b0_new);
1312
1313 mod_phy_reg(pi, 0x64b, (0x1 << 0), (1) << 0);
1314
1315 mod_phy_reg(pi, 0x64b, (0x1 << 3), (1) << 3);
1316
1317 pi_lcn->lcnphy_cal_results.rxiqcal_coeff_a0 = a0_new;
1318 pi_lcn->lcnphy_cal_results.rxiqcal_coeff_b0 = b0_new;
1319
1320 return result;
1321}
1322
1323static u32 wlc_lcnphy_measure_digital_power(struct brcms_phy *pi, u16 nsamples)
1324{
1325 struct lcnphy_iq_est iq_est = { 0, 0, 0 };
1326
1327 if (!wlc_lcnphy_rx_iq_est(pi, nsamples, 32, &iq_est))
1328 return 0;
1329 return (iq_est.i_pwr + iq_est.q_pwr) / nsamples;
1330}
1331
1332static bool
1333wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi,
1334 const struct lcnphy_rx_iqcomp *iqcomp,
1335 int iqcomp_sz, bool tx_switch, bool rx_switch, int module,
1336 int tx_gain_idx)
1337{
1338 struct lcnphy_txgains old_gains;
1339 u16 tx_pwr_ctrl;
1340 u8 tx_gain_index_old = 0;
1341 bool result = false, tx_gain_override_old = false;
1342 u16 i, Core1TxControl_old, RFOverride0_old,
1343 RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old,
1344 rfoverride3_old, rfoverride3val_old, rfoverride4_old,
1345 rfoverride4val_old, afectrlovr_old, afectrlovrval_old;
1346 int tia_gain;
1347 u32 received_power, rx_pwr_threshold;
1348 u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl;
1349 u16 values_to_save[11];
1350 s16 *ptr;
1351 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1352
1353 ptr = kmalloc(sizeof(s16) * 131, GFP_ATOMIC);
1354 if (NULL == ptr)
1355 return false;
1356 if (module == 2) {
1357 while (iqcomp_sz--) {
1358 if (iqcomp[iqcomp_sz].chan ==
1359 CHSPEC_CHANNEL(pi->radio_chanspec)) {
1360 wlc_lcnphy_set_rx_iq_comp(pi,
1361 (u16)
1362 iqcomp[iqcomp_sz].a,
1363 (u16)
1364 iqcomp[iqcomp_sz].b);
1365 result = true;
1366 break;
1367 }
1368 }
1369 goto cal_done;
1370 }
1371
1372 if (module == 1) {
1373
1374 tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
1375 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
1376
1377 for (i = 0; i < 11; i++)
1378 values_to_save[i] =
1379 read_radio_reg(pi, rxiq_cal_rf_reg[i]);
1380 Core1TxControl_old = read_phy_reg(pi, 0x631);
1381
1382 or_phy_reg(pi, 0x631, 0x0015);
1383
1384 RFOverride0_old = read_phy_reg(pi, 0x44c);
1385 RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
1386 rfoverride2_old = read_phy_reg(pi, 0x4b0);
1387 rfoverride2val_old = read_phy_reg(pi, 0x4b1);
1388 rfoverride3_old = read_phy_reg(pi, 0x4f9);
1389 rfoverride3val_old = read_phy_reg(pi, 0x4fa);
1390 rfoverride4_old = read_phy_reg(pi, 0x938);
1391 rfoverride4val_old = read_phy_reg(pi, 0x939);
1392 afectrlovr_old = read_phy_reg(pi, 0x43b);
1393 afectrlovrval_old = read_phy_reg(pi, 0x43c);
1394 old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
1395 old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
1396
1397 tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
1398 if (tx_gain_override_old) {
1399 wlc_lcnphy_get_tx_gain(pi, &old_gains);
1400 tx_gain_index_old = pi_lcn->lcnphy_current_index;
1401 }
1402
1403 wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
1404
1405 mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
1406 mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
1407
1408 mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
1409 mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
1410
1411 write_radio_reg(pi, RADIO_2064_REG116, 0x06);
1412 write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
1413 write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
1414 write_radio_reg(pi, RADIO_2064_REG098, 0x03);
1415 write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
1416 mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
1417 write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
1418 write_radio_reg(pi, RADIO_2064_REG114, 0x01);
1419 write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
1420 write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
1421
1422 mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
1423 mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
1424 mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
1425 mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
1426 mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
1427 mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
1428 mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
1429 mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
1430 mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
1431 mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
1432
1433 mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
1434 mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
1435
1436 wlc_lcnphy_start_tx_tone(pi, 2000, 120, 0);
1437 write_phy_reg(pi, 0x6da, 0xffff);
1438 or_phy_reg(pi, 0x6db, 0x3);
1439 wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
1440 wlc_lcnphy_rx_gain_override_enable(pi, true);
1441
1442 tia_gain = 8;
1443 rx_pwr_threshold = 950;
1444 while (tia_gain > 0) {
1445 tia_gain -= 1;
1446 wlc_lcnphy_set_rx_gain_by_distribution(pi,
1447 0, 0, 2, 2,
1448 (u16)
1449 tia_gain, 1, 0);
1450 udelay(500);
1451
1452 received_power =
1453 wlc_lcnphy_measure_digital_power(pi, 2000);
1454 if (received_power < rx_pwr_threshold)
1455 break;
1456 }
1457 result = wlc_lcnphy_calc_rx_iq_comp(pi, 0xffff);
1458
1459 wlc_lcnphy_stop_tx_tone(pi);
1460
1461 write_phy_reg(pi, 0x631, Core1TxControl_old);
1462
1463 write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
1464 write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
1465 write_phy_reg(pi, 0x4b0, rfoverride2_old);
1466 write_phy_reg(pi, 0x4b1, rfoverride2val_old);
1467 write_phy_reg(pi, 0x4f9, rfoverride3_old);
1468 write_phy_reg(pi, 0x4fa, rfoverride3val_old);
1469 write_phy_reg(pi, 0x938, rfoverride4_old);
1470 write_phy_reg(pi, 0x939, rfoverride4val_old);
1471 write_phy_reg(pi, 0x43b, afectrlovr_old);
1472 write_phy_reg(pi, 0x43c, afectrlovrval_old);
1473 write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
1474 write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
1475
1476 wlc_lcnphy_clear_trsw_override(pi);
1477
1478 mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
1479
1480 for (i = 0; i < 11; i++)
1481 write_radio_reg(pi, rxiq_cal_rf_reg[i],
1482 values_to_save[i]);
1483
1484 if (tx_gain_override_old)
1485 wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
1486 else
1487 wlc_lcnphy_disable_tx_gain_override(pi);
1488
1489 wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
1490 wlc_lcnphy_rx_gain_override_enable(pi, false);
1491 }
1492
1493cal_done:
1494 kfree(ptr);
1495 return result;
1496}
1497
1498s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi)
1499{
1500 s8 index;
1501 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1502
1503 if (txpwrctrl_off(pi))
1504 index = pi_lcn->lcnphy_current_index;
1505 else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
1506 index = (s8) (wlc_lcnphy_get_current_tx_pwr_idx_if_pwrctrl_on(
1507 pi) / 2);
1508 else
1509 index = pi_lcn->lcnphy_current_index;
1510 return index;
1511}
1512
1513void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel)
1514{
1515 u16 afectrlovr, afectrlovrval;
1516 afectrlovr = read_phy_reg(pi, 0x43b);
1517 afectrlovrval = read_phy_reg(pi, 0x43c);
1518 if (channel != 0) {
1519 mod_phy_reg(pi, 0x43b, (0x1 << 1), (1) << 1);
1520
1521 mod_phy_reg(pi, 0x43c, (0x1 << 1), (0) << 1);
1522
1523 mod_phy_reg(pi, 0x43b, (0x1 << 4), (1) << 4);
1524
1525 mod_phy_reg(pi, 0x43c, (0x1 << 6), (0) << 6);
1526
1527 write_phy_reg(pi, 0x44b, 0xffff);
1528 wlc_lcnphy_tx_pu(pi, 1);
1529
1530 mod_phy_reg(pi, 0x634, (0xff << 8), (0) << 8);
1531
1532 or_phy_reg(pi, 0x6da, 0x0080);
1533
1534 or_phy_reg(pi, 0x00a, 0x228);
1535 } else {
1536 and_phy_reg(pi, 0x00a, ~(0x228));
1537
1538 and_phy_reg(pi, 0x6da, 0xFF7F);
1539 write_phy_reg(pi, 0x43b, afectrlovr);
1540 write_phy_reg(pi, 0x43c, afectrlovrval);
1541 }
1542}
1543
1544static void wlc_lcnphy_toggle_afe_pwdn(struct brcms_phy *pi)
1545{
1546 u16 save_AfeCtrlOvrVal, save_AfeCtrlOvr;
1547
1548 save_AfeCtrlOvrVal = read_phy_reg(pi, 0x43c);
1549 save_AfeCtrlOvr = read_phy_reg(pi, 0x43b);
1550
1551 write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal | 0x1);
1552 write_phy_reg(pi, 0x43b, save_AfeCtrlOvr | 0x1);
1553
1554 write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal & 0xfffe);
1555 write_phy_reg(pi, 0x43b, save_AfeCtrlOvr & 0xfffe);
1556
1557 write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal);
1558 write_phy_reg(pi, 0x43b, save_AfeCtrlOvr);
1559}
1560
1561static void
1562wlc_lcnphy_txrx_spur_avoidance_mode(struct brcms_phy *pi, bool enable)
1563{
1564 if (enable) {
1565 write_phy_reg(pi, 0x942, 0x7);
1566 write_phy_reg(pi, 0x93b, ((1 << 13) + 23));
1567 write_phy_reg(pi, 0x93c, ((1 << 13) + 1989));
1568
1569 write_phy_reg(pi, 0x44a, 0x084);
1570 write_phy_reg(pi, 0x44a, 0x080);
1571 write_phy_reg(pi, 0x6d3, 0x2222);
1572 write_phy_reg(pi, 0x6d3, 0x2220);
1573 } else {
1574 write_phy_reg(pi, 0x942, 0x0);
1575 write_phy_reg(pi, 0x93b, ((0 << 13) + 23));
1576 write_phy_reg(pi, 0x93c, ((0 << 13) + 1989));
1577 }
1578 wlapi_switch_macfreq(pi->sh->physhim, enable);
1579}
1580
1581static void
1582wlc_lcnphy_set_chanspec_tweaks(struct brcms_phy *pi, u16 chanspec)
1583{
1584 u8 channel = CHSPEC_CHANNEL(chanspec);
1585 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1586
1587 if (channel == 14)
1588 mod_phy_reg(pi, 0x448, (0x3 << 8), (2) << 8);
1589 else
1590 mod_phy_reg(pi, 0x448, (0x3 << 8), (1) << 8);
1591
1592 pi_lcn->lcnphy_bandedge_corr = 2;
1593 if (channel == 1)
1594 pi_lcn->lcnphy_bandedge_corr = 4;
1595
1596 if (channel == 1 || channel == 2 || channel == 3 ||
1597 channel == 4 || channel == 9 ||
1598 channel == 10 || channel == 11 || channel == 12) {
1599 si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03000c04);
1600 si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x0);
1601 si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x200005c0);
1602
1603 si_pmu_pllupd(pi->sh->sih);
1604 write_phy_reg(pi, 0x942, 0);
1605 wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
1606 pi_lcn->lcnphy_spurmod = 0;
1607 mod_phy_reg(pi, 0x424, (0xff << 8), (0x1b) << 8);
1608
1609 write_phy_reg(pi, 0x425, 0x5907);
1610 } else {
1611 si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03140c04);
1612 si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x333333);
1613 si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x202c2820);
1614
1615 si_pmu_pllupd(pi->sh->sih);
1616 write_phy_reg(pi, 0x942, 0);
1617 wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
1618
1619 pi_lcn->lcnphy_spurmod = 0;
1620 mod_phy_reg(pi, 0x424, (0xff << 8), (0x1f) << 8);
1621
1622 write_phy_reg(pi, 0x425, 0x590a);
1623 }
1624
1625 or_phy_reg(pi, 0x44a, 0x44);
1626 write_phy_reg(pi, 0x44a, 0x80);
1627}
1628
1629static void
1630wlc_lcnphy_radio_2064_channel_tune_4313(struct brcms_phy *pi, u8 channel)
1631{
1632 uint i;
1633 const struct chan_info_2064_lcnphy *ci;
1634 u8 rfpll_doubler = 0;
1635 u8 pll_pwrup, pll_pwrup_ovr;
1636 s32 qFxtal, qFref, qFvco, qFcal;
1637 u8 d15, d16, f16, e44, e45;
1638 u32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div;
1639 u16 loop_bw, d30, setCount;
1640
1641 u8 h29, h28_ten, e30, h30_ten, cp_current;
1642 u16 g30, d28;
1643
1644 ci = &chan_info_2064_lcnphy[0];
1645 rfpll_doubler = 1;
1646
1647 mod_radio_reg(pi, RADIO_2064_REG09D, 0x4, 0x1 << 2);
1648
1649 write_radio_reg(pi, RADIO_2064_REG09E, 0xf);
1650 if (!rfpll_doubler) {
1651 loop_bw = PLL_2064_LOOP_BW;
1652 d30 = PLL_2064_D30;
1653 } else {
1654 loop_bw = PLL_2064_LOOP_BW_DOUBLER;
1655 d30 = PLL_2064_D30_DOUBLER;
1656 }
1657
1658 if (CHSPEC_IS2G(pi->radio_chanspec)) {
1659 for (i = 0; i < ARRAY_SIZE(chan_info_2064_lcnphy); i++)
1660 if (chan_info_2064_lcnphy[i].chan == channel)
1661 break;
1662
1663 if (i >= ARRAY_SIZE(chan_info_2064_lcnphy))
1664 return;
1665
1666 ci = &chan_info_2064_lcnphy[i];
1667 }
1668
1669 write_radio_reg(pi, RADIO_2064_REG02A, ci->logen_buftune);
1670
1671 mod_radio_reg(pi, RADIO_2064_REG030, 0x3, ci->logen_rccr_tx);
1672
1673 mod_radio_reg(pi, RADIO_2064_REG091, 0x3, ci->txrf_mix_tune_ctrl);
1674
1675 mod_radio_reg(pi, RADIO_2064_REG038, 0xf, ci->pa_input_tune_g);
1676
1677 mod_radio_reg(pi, RADIO_2064_REG030, 0x3 << 2,
1678 (ci->logen_rccr_rx) << 2);
1679
1680 mod_radio_reg(pi, RADIO_2064_REG05E, 0xf, ci->pa_rxrf_lna1_freq_tune);
1681
1682 mod_radio_reg(pi, RADIO_2064_REG05E, (0xf) << 4,
1683 (ci->pa_rxrf_lna2_freq_tune) << 4);
1684
1685 write_radio_reg(pi, RADIO_2064_REG06C, ci->rxrf_rxrf_spare1);
1686
1687 pll_pwrup = (u8) read_radio_reg(pi, RADIO_2064_REG044);
1688 pll_pwrup_ovr = (u8) read_radio_reg(pi, RADIO_2064_REG12B);
1689
1690 or_radio_reg(pi, RADIO_2064_REG044, 0x07);
1691
1692 or_radio_reg(pi, RADIO_2064_REG12B, (0x07) << 1);
1693 e44 = 0;
1694 e45 = 0;
1695
1696 fpfd = rfpll_doubler ? (pi->xtalfreq << 1) : (pi->xtalfreq);
1697 if (pi->xtalfreq > 26000000)
1698 e44 = 1;
1699 if (pi->xtalfreq > 52000000)
1700 e45 = 1;
1701 if (e44 == 0)
1702 fcal_div = 1;
1703 else if (e45 == 0)
1704 fcal_div = 2;
1705 else
1706 fcal_div = 4;
1707 fvco3 = (ci->freq * 3);
1708 fref3 = 2 * fpfd;
1709
1710 qFxtal = wlc_lcnphy_qdiv_roundup(pi->xtalfreq, PLL_2064_MHZ, 16);
1711 qFref = wlc_lcnphy_qdiv_roundup(fpfd, PLL_2064_MHZ, 16);
1712 qFcal = pi->xtalfreq * fcal_div / PLL_2064_MHZ;
1713 qFvco = wlc_lcnphy_qdiv_roundup(fvco3, 2, 16);
1714
1715 write_radio_reg(pi, RADIO_2064_REG04F, 0x02);
1716
1717 d15 = (pi->xtalfreq * fcal_div * 4 / 5) / PLL_2064_MHZ - 1;
1718 write_radio_reg(pi, RADIO_2064_REG052, (0x07 & (d15 >> 2)));
1719 write_radio_reg(pi, RADIO_2064_REG053, (d15 & 0x3) << 5);
1720
1721 d16 = (qFcal * 8 / (d15 + 1)) - 1;
1722 write_radio_reg(pi, RADIO_2064_REG051, d16);
1723
1724 f16 = ((d16 + 1) * (d15 + 1)) / qFcal;
1725 setCount = f16 * 3 * (ci->freq) / 32 - 1;
1726 mod_radio_reg(pi, RADIO_2064_REG053, (0x0f << 0),
1727 (u8) (setCount >> 8));
1728
1729 or_radio_reg(pi, RADIO_2064_REG053, 0x10);
1730 write_radio_reg(pi, RADIO_2064_REG054, (u8) (setCount & 0xff));
1731
1732 div_int = ((fvco3 * (PLL_2064_MHZ >> 4)) / fref3) << 4;
1733
1734 div_frac = ((fvco3 * (PLL_2064_MHZ >> 4)) % fref3) << 4;
1735 while (div_frac >= fref3) {
1736 div_int++;
1737 div_frac -= fref3;
1738 }
1739 div_frac = wlc_lcnphy_qdiv_roundup(div_frac, fref3, 20);
1740
1741 mod_radio_reg(pi, RADIO_2064_REG045, (0x1f << 0),
1742 (u8) (div_int >> 4));
1743 mod_radio_reg(pi, RADIO_2064_REG046, (0x1f << 4),
1744 (u8) (div_int << 4));
1745 mod_radio_reg(pi, RADIO_2064_REG046, (0x0f << 0),
1746 (u8) (div_frac >> 16));
1747 write_radio_reg(pi, RADIO_2064_REG047, (u8) (div_frac >> 8) & 0xff);
1748 write_radio_reg(pi, RADIO_2064_REG048, (u8) div_frac & 0xff);
1749
1750 write_radio_reg(pi, RADIO_2064_REG040, 0xfb);
1751
1752 write_radio_reg(pi, RADIO_2064_REG041, 0x9A);
1753 write_radio_reg(pi, RADIO_2064_REG042, 0xA3);
1754 write_radio_reg(pi, RADIO_2064_REG043, 0x0C);
1755
1756 h29 = LCN_BW_LMT / loop_bw;
1757 d28 = (((PLL_2064_HIGH_END_KVCO - PLL_2064_LOW_END_KVCO) *
1758 (fvco3 / 2 - PLL_2064_LOW_END_VCO)) /
1759 (PLL_2064_HIGH_END_VCO - PLL_2064_LOW_END_VCO))
1760 + PLL_2064_LOW_END_KVCO;
1761 h28_ten = (d28 * 10) / LCN_VCO_DIV;
1762 e30 = (d30 - LCN_OFFSET) / LCN_FACT;
1763 g30 = LCN_OFFSET + (e30 * LCN_FACT);
1764 h30_ten = (g30 * 10) / LCN_CUR_DIV;
1765 cp_current = ((LCN_CUR_LMT * h29 * LCN_MULT * 100) / h28_ten) / h30_ten;
1766 mod_radio_reg(pi, RADIO_2064_REG03C, 0x3f, cp_current);
1767
1768 if (channel >= 1 && channel <= 5)
1769 write_radio_reg(pi, RADIO_2064_REG03C, 0x8);
1770 else
1771 write_radio_reg(pi, RADIO_2064_REG03C, 0x7);
1772 write_radio_reg(pi, RADIO_2064_REG03D, 0x3);
1773
1774 mod_radio_reg(pi, RADIO_2064_REG044, 0x0c, 0x0c);
1775 udelay(1);
1776
1777 wlc_2064_vco_cal(pi);
1778
1779 write_radio_reg(pi, RADIO_2064_REG044, pll_pwrup);
1780 write_radio_reg(pi, RADIO_2064_REG12B, pll_pwrup_ovr);
1781 if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
1782 write_radio_reg(pi, RADIO_2064_REG038, 3);
1783 write_radio_reg(pi, RADIO_2064_REG091, 7);
1784 }
1785}
1786
1787static int
1788wlc_lcnphy_load_tx_iir_filter(struct brcms_phy *pi, bool is_ofdm, s16 filt_type)
1789{
1790 s16 filt_index = -1;
1791 int j;
1792
1793 u16 addr[] = {
1794 0x910,
1795 0x91e,
1796 0x91f,
1797 0x924,
1798 0x925,
1799 0x926,
1800 0x920,
1801 0x921,
1802 0x927,
1803 0x928,
1804 0x929,
1805 0x922,
1806 0x923,
1807 0x930,
1808 0x931,
1809 0x932
1810 };
1811
1812 u16 addr_ofdm[] = {
1813 0x90f,
1814 0x900,
1815 0x901,
1816 0x906,
1817 0x907,
1818 0x908,
1819 0x902,
1820 0x903,
1821 0x909,
1822 0x90a,
1823 0x90b,
1824 0x904,
1825 0x905,
1826 0x90c,
1827 0x90d,
1828 0x90e
1829 };
1830
1831 if (!is_ofdm) {
1832 for (j = 0; j < LCNPHY_NUM_TX_DIG_FILTERS_CCK; j++) {
1833 if (filt_type == LCNPHY_txdigfiltcoeffs_cck[j][0]) {
1834 filt_index = (s16) j;
1835 break;
1836 }
1837 }
1838
1839 if (filt_index != -1) {
1840 for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++)
1841 write_phy_reg(pi, addr[j],
1842 LCNPHY_txdigfiltcoeffs_cck
1843 [filt_index][j + 1]);
1844 }
1845 } else {
1846 for (j = 0; j < LCNPHY_NUM_TX_DIG_FILTERS_OFDM; j++) {
1847 if (filt_type == LCNPHY_txdigfiltcoeffs_ofdm[j][0]) {
1848 filt_index = (s16) j;
1849 break;
1850 }
1851 }
1852
1853 if (filt_index != -1) {
1854 for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++)
1855 write_phy_reg(pi, addr_ofdm[j],
1856 LCNPHY_txdigfiltcoeffs_ofdm
1857 [filt_index][j + 1]);
1858 }
1859 }
1860
1861 return (filt_index != -1) ? 0 : -1;
1862}
1863
1864void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec)
1865{
1866 u8 channel = CHSPEC_CHANNEL(chanspec);
1867
1868 wlc_phy_chanspec_radio_set((struct brcms_phy_pub *) pi, chanspec);
1869
1870 wlc_lcnphy_set_chanspec_tweaks(pi, pi->radio_chanspec);
1871
1872 or_phy_reg(pi, 0x44a, 0x44);
1873 write_phy_reg(pi, 0x44a, 0x80);
1874
1875 wlc_lcnphy_radio_2064_channel_tune_4313(pi, channel);
1876 udelay(1000);
1877
1878 wlc_lcnphy_toggle_afe_pwdn(pi);
1879
1880 write_phy_reg(pi, 0x657, lcnphy_sfo_cfg[channel - 1].ptcentreTs20);
1881 write_phy_reg(pi, 0x658, lcnphy_sfo_cfg[channel - 1].ptcentreFactor);
1882
1883 if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
1884 mod_phy_reg(pi, 0x448, (0x3 << 8), (2) << 8);
1885
1886 wlc_lcnphy_load_tx_iir_filter(pi, false, 3);
1887 } else {
1888 mod_phy_reg(pi, 0x448, (0x3 << 8), (1) << 8);
1889
1890 wlc_lcnphy_load_tx_iir_filter(pi, false, 2);
1891 }
1892
1893 wlc_lcnphy_load_tx_iir_filter(pi, true, 0);
1894
1895 mod_phy_reg(pi, 0x4eb, (0x7 << 3), (1) << 3);
1896
1897}
1898
1899static u16 wlc_lcnphy_get_pa_gain(struct brcms_phy *pi)
1900{
1901 u16 pa_gain;
1902
1903 pa_gain = (read_phy_reg(pi, 0x4fb) &
1904 LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK) >>
1905 LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT;
1906
1907 return pa_gain;
1908}
1909
1910static void wlc_lcnphy_set_tx_gain(struct brcms_phy *pi,
1911 struct lcnphy_txgains *target_gains)
1912{
1913 u16 pa_gain = wlc_lcnphy_get_pa_gain(pi);
1914
1915 mod_phy_reg(
1916 pi, 0x4b5,
1917 (0xffff << 0),
1918 ((target_gains->gm_gain) |
1919 (target_gains->pga_gain << 8)) <<
1920 0);
1921 mod_phy_reg(pi, 0x4fb,
1922 (0x7fff << 0),
1923 ((target_gains->pad_gain) | (pa_gain << 8)) << 0);
1924
1925 mod_phy_reg(
1926 pi, 0x4fc,
1927 (0xffff << 0),
1928 ((target_gains->gm_gain) |
1929 (target_gains->pga_gain << 8)) <<
1930 0);
1931 mod_phy_reg(pi, 0x4fd,
1932 (0x7fff << 0),
1933 ((target_gains->pad_gain) | (pa_gain << 8)) << 0);
1934
1935 wlc_lcnphy_set_dac_gain(pi, target_gains->dac_gain);
1936
1937 wlc_lcnphy_enable_tx_gain_override(pi);
1938}
1939
1940static void wlc_lcnphy_set_bbmult(struct brcms_phy *pi, u8 m0)
1941{
1942 u16 m0m1 = (u16) m0 << 8;
1943 struct phytbl_info tab;
1944
1945 tab.tbl_ptr = &m0m1;
1946 tab.tbl_len = 1;
1947 tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
1948 tab.tbl_offset = 87;
1949 tab.tbl_width = 16;
1950 wlc_lcnphy_write_table(pi, &tab);
1951}
1952
1953static void wlc_lcnphy_clear_tx_power_offsets(struct brcms_phy *pi)
1954{
1955 u32 data_buf[64];
1956 struct phytbl_info tab;
1957
1958 memset(data_buf, 0, sizeof(data_buf));
1959
1960 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
1961 tab.tbl_width = 32;
1962 tab.tbl_ptr = data_buf;
1963
1964 if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
1965
1966 tab.tbl_len = 30;
1967 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
1968 wlc_lcnphy_write_table(pi, &tab);
1969 }
1970
1971 tab.tbl_len = 64;
1972 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_MAC_OFFSET;
1973 wlc_lcnphy_write_table(pi, &tab);
1974}
1975
1976enum lcnphy_tssi_mode {
1977 LCNPHY_TSSI_PRE_PA,
1978 LCNPHY_TSSI_POST_PA,
1979 LCNPHY_TSSI_EXT
1980};
1981
1982static void
1983wlc_lcnphy_set_tssi_mux(struct brcms_phy *pi, enum lcnphy_tssi_mode pos)
1984{
1985 mod_phy_reg(pi, 0x4d7, (0x1 << 0), (0x1) << 0);
1986
1987 mod_phy_reg(pi, 0x4d7, (0x1 << 6), (1) << 6);
1988
1989 if (LCNPHY_TSSI_POST_PA == pos) {
1990 mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0) << 2);
1991
1992 mod_phy_reg(pi, 0x4d9, (0x1 << 3), (1) << 3);
1993
1994 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
1995 mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
1996 } else {
1997 mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1);
1998 mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
1999 }
2000 } else {
2001 mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2);
2002
2003 mod_phy_reg(pi, 0x4d9, (0x1 << 3), (0) << 3);
2004
2005 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
2006 mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
2007 } else {
2008 mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0);
2009 mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
2010 }
2011 }
2012 mod_phy_reg(pi, 0x637, (0x3 << 14), (0) << 14);
2013
2014 if (LCNPHY_TSSI_EXT == pos) {
2015 write_radio_reg(pi, RADIO_2064_REG07F, 1);
2016 mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 0x2);
2017 mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 0x1 << 7);
2018 mod_radio_reg(pi, RADIO_2064_REG028, 0x1f, 0x3);
2019 }
2020}
2021
2022static u16 wlc_lcnphy_rfseq_tbl_adc_pwrup(struct brcms_phy *pi)
2023{
2024 u16 N1, N2, N3, N4, N5, N6, N;
2025 N1 = ((read_phy_reg(pi, 0x4a5) & (0xff << 0))
2026 >> 0);
2027 N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12))
2028 >> 12);
2029 N3 = ((read_phy_reg(pi, 0x40d) & (0xff << 0))
2030 >> 0);
2031 N4 = 1 << ((read_phy_reg(pi, 0x40d) & (0x7 << 8))
2032 >> 8);
2033 N5 = ((read_phy_reg(pi, 0x4a2) & (0xff << 0))
2034 >> 0);
2035 N6 = 1 << ((read_phy_reg(pi, 0x4a2) & (0x7 << 8))
2036 >> 8);
2037 N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80;
2038 if (N < 1600)
2039 N = 1600;
2040 return N;
2041}
2042
2043static void wlc_lcnphy_pwrctrl_rssiparams(struct brcms_phy *pi)
2044{
2045 u16 auxpga_vmid, auxpga_vmid_temp, auxpga_gain_temp;
2046 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2047
2048 auxpga_vmid = (2 << 8) |
2049 (pi_lcn->lcnphy_rssi_vc << 4) | pi_lcn->lcnphy_rssi_vf;
2050 auxpga_vmid_temp = (2 << 8) | (8 << 4) | 4;
2051 auxpga_gain_temp = 2;
2052
2053 mod_phy_reg(pi, 0x4d8, (0x1 << 0), (0) << 0);
2054
2055 mod_phy_reg(pi, 0x4d8, (0x1 << 1), (0) << 1);
2056
2057 mod_phy_reg(pi, 0x4d7, (0x1 << 3), (0) << 3);
2058
2059 mod_phy_reg(pi, 0x4db,
2060 (0x3ff << 0) |
2061 (0x7 << 12),
2062 (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
2063
2064 mod_phy_reg(pi, 0x4dc,
2065 (0x3ff << 0) |
2066 (0x7 << 12),
2067 (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
2068
2069 mod_phy_reg(pi, 0x40a,
2070 (0x3ff << 0) |
2071 (0x7 << 12),
2072 (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
2073
2074 mod_phy_reg(pi, 0x40b,
2075 (0x3ff << 0) |
2076 (0x7 << 12),
2077 (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
2078
2079 mod_phy_reg(pi, 0x40c,
2080 (0x3ff << 0) |
2081 (0x7 << 12),
2082 (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
2083
2084 mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5));
2085}
2086
2087static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
2088{
2089 struct phytbl_info tab;
2090 u32 rfseq, ind;
2091
2092 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
2093 tab.tbl_width = 32;
2094 tab.tbl_ptr = &ind;
2095 tab.tbl_len = 1;
2096 tab.tbl_offset = 0;
2097 for (ind = 0; ind < 128; ind++) {
2098 wlc_lcnphy_write_table(pi, &tab);
2099 tab.tbl_offset++;
2100 }
2101 tab.tbl_offset = 704;
2102 for (ind = 0; ind < 128; ind++) {
2103 wlc_lcnphy_write_table(pi, &tab);
2104 tab.tbl_offset++;
2105 }
2106 mod_phy_reg(pi, 0x503, (0x1 << 0), (0) << 0);
2107
2108 mod_phy_reg(pi, 0x503, (0x1 << 2), (0) << 2);
2109
2110 mod_phy_reg(pi, 0x503, (0x1 << 4), (1) << 4);
2111
2112 wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT);
2113 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
2114
2115 mod_phy_reg(pi, 0x4a4, (0x1 << 15), (1) << 15);
2116
2117 mod_phy_reg(pi, 0x4d0, (0x1 << 5), (0) << 5);
2118
2119 mod_phy_reg(pi, 0x4a4, (0x1ff << 0), (0) << 0);
2120
2121 mod_phy_reg(pi, 0x4a5, (0xff << 0), (255) << 0);
2122
2123 mod_phy_reg(pi, 0x4a5, (0x7 << 12), (5) << 12);
2124
2125 mod_phy_reg(pi, 0x4a5, (0x7 << 8), (0) << 8);
2126
2127 mod_phy_reg(pi, 0x40d, (0xff << 0), (64) << 0);
2128
2129 mod_phy_reg(pi, 0x40d, (0x7 << 8), (4) << 8);
2130
2131 mod_phy_reg(pi, 0x4a2, (0xff << 0), (64) << 0);
2132
2133 mod_phy_reg(pi, 0x4a2, (0x7 << 8), (4) << 8);
2134
2135 mod_phy_reg(pi, 0x4d0, (0x1ff << 6), (0) << 6);
2136
2137 mod_phy_reg(pi, 0x4a8, (0xff << 0), (0x1) << 0);
2138
2139 wlc_lcnphy_clear_tx_power_offsets(pi);
2140
2141 mod_phy_reg(pi, 0x4a6, (0x1 << 15), (1) << 15);
2142
2143 mod_phy_reg(pi, 0x4a6, (0x1ff << 0), (0xff) << 0);
2144
2145 mod_phy_reg(pi, 0x49a, (0x1ff << 0), (0xff) << 0);
2146
2147 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
2148 mod_radio_reg(pi, RADIO_2064_REG028, 0xf, 0xe);
2149 mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
2150 } else {
2151 mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
2152 mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 1 << 3);
2153 }
2154
2155 write_radio_reg(pi, RADIO_2064_REG025, 0xc);
2156
2157 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
2158 mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
2159 } else {
2160 if (CHSPEC_IS2G(pi->radio_chanspec))
2161 mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 1 << 1);
2162 else
2163 mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 0 << 1);
2164 }
2165
2166 if (LCNREV_IS(pi->pubpi.phy_rev, 2))
2167 mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 1 << 1);
2168 else
2169 mod_radio_reg(pi, RADIO_2064_REG03A, 0x4, 1 << 2);
2170
2171 mod_radio_reg(pi, RADIO_2064_REG11A, 0x1, 1 << 0);
2172
2173 mod_radio_reg(pi, RADIO_2064_REG005, 0x8, 1 << 3);
2174
2175 if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
2176 mod_phy_reg(pi, 0x4d7,
2177 (0x1 << 3) | (0x7 << 12), 0 << 3 | 2 << 12);
2178
2179 rfseq = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi);
2180 tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
2181 tab.tbl_width = 16;
2182 tab.tbl_ptr = &rfseq;
2183 tab.tbl_len = 1;
2184 tab.tbl_offset = 6;
2185 wlc_lcnphy_write_table(pi, &tab);
2186
2187 mod_phy_reg(pi, 0x938, (0x1 << 2), (1) << 2);
2188
2189 mod_phy_reg(pi, 0x939, (0x1 << 2), (1) << 2);
2190
2191 mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
2192
2193 mod_phy_reg(pi, 0x4d7, (0x1 << 2), (1) << 2);
2194
2195 mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8);
2196
2197 wlc_lcnphy_pwrctrl_rssiparams(pi);
2198}
2199
2200void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi)
2201{
2202 u16 tx_cnt, tx_total, npt;
2203 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2204
2205 tx_total = wlc_lcnphy_total_tx_frames(pi);
2206 tx_cnt = tx_total - pi_lcn->lcnphy_tssi_tx_cnt;
2207 npt = wlc_lcnphy_get_tx_pwr_npt(pi);
2208
2209 if (tx_cnt > (1 << npt)) {
2210
2211 pi_lcn->lcnphy_tssi_tx_cnt = tx_total;
2212
2213 pi_lcn->lcnphy_tssi_idx = wlc_lcnphy_get_current_tx_pwr_idx(pi);
2214 pi_lcn->lcnphy_tssi_npt = npt;
2215
2216 }
2217}
2218
2219s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1)
2220{
2221 s32 a, b, p;
2222
2223 a = 32768 + (a1 * tssi);
2224 b = (1024 * b0) + (64 * b1 * tssi);
2225 p = ((2 * b) + a) / (2 * a);
2226
2227 return p;
2228}
2229
2230static void wlc_lcnphy_txpower_reset_npt(struct brcms_phy *pi)
2231{
2232 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2233 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
2234 return;
2235
2236 pi_lcn->lcnphy_tssi_idx = LCNPHY_TX_PWR_CTRL_START_INDEX_2G_4313;
2237 pi_lcn->lcnphy_tssi_npt = LCNPHY_TX_PWR_CTRL_START_NPT;
2238}
2239
2240void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi)
2241{
2242 struct phytbl_info tab;
2243 u32 rate_table[BRCMS_NUM_RATES_CCK + BRCMS_NUM_RATES_OFDM +
2244 BRCMS_NUM_RATES_MCS_1_STREAM];
2245 uint i, j;
2246 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
2247 return;
2248
2249 for (i = 0, j = 0; i < ARRAY_SIZE(rate_table); i++, j++) {
2250
2251 if (i == BRCMS_NUM_RATES_CCK + BRCMS_NUM_RATES_OFDM)
2252 j = TXP_FIRST_MCS_20_SISO;
2253
2254 rate_table[i] = (u32) ((s32) (-pi->tx_power_offset[j]));
2255 }
2256
2257 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
2258 tab.tbl_width = 32;
2259 tab.tbl_len = ARRAY_SIZE(rate_table);
2260 tab.tbl_ptr = rate_table;
2261 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
2262 wlc_lcnphy_write_table(pi, &tab);
2263
2264 if (wlc_lcnphy_get_target_tx_pwr(pi) != pi->tx_power_min) {
2265 wlc_lcnphy_set_target_tx_pwr(pi, pi->tx_power_min);
2266
2267 wlc_lcnphy_txpower_reset_npt(pi);
2268 }
2269}
2270
2271static void wlc_lcnphy_set_tx_pwr_soft_ctrl(struct brcms_phy *pi, s8 index)
2272{
2273 u32 cck_offset[4] = { 22, 22, 22, 22 };
2274 u32 ofdm_offset, reg_offset_cck;
2275 int i;
2276 u16 index2;
2277 struct phytbl_info tab;
2278
2279 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
2280 return;
2281
2282 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x1) << 14);
2283
2284 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x0) << 14);
2285
2286 or_phy_reg(pi, 0x6da, 0x0040);
2287
2288 reg_offset_cck = 0;
2289 for (i = 0; i < 4; i++)
2290 cck_offset[i] -= reg_offset_cck;
2291 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
2292 tab.tbl_width = 32;
2293 tab.tbl_len = 4;
2294 tab.tbl_ptr = cck_offset;
2295 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
2296 wlc_lcnphy_write_table(pi, &tab);
2297 ofdm_offset = 0;
2298 tab.tbl_len = 1;
2299 tab.tbl_ptr = &ofdm_offset;
2300 for (i = 836; i < 862; i++) {
2301 tab.tbl_offset = i;
2302 wlc_lcnphy_write_table(pi, &tab);
2303 }
2304
2305 mod_phy_reg(pi, 0x4a4, (0x1 << 15), (0x1) << 15);
2306
2307 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x1) << 14);
2308
2309 mod_phy_reg(pi, 0x4a4, (0x1 << 13), (0x1) << 13);
2310
2311 mod_phy_reg(pi, 0x4b0, (0x1 << 7), (0) << 7);
2312
2313 mod_phy_reg(pi, 0x43b, (0x1 << 6), (0) << 6);
2314
2315 mod_phy_reg(pi, 0x4a9, (0x1 << 15), (1) << 15);
2316
2317 index2 = (u16) (index * 2);
2318 mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0);
2319
2320 mod_phy_reg(pi, 0x6a3, (0x1 << 4), (0) << 4);
2321
2322}
2323
2324static s8 wlc_lcnphy_tempcompensated_txpwrctrl(struct brcms_phy *pi)
2325{
2326 s8 index, delta_brd, delta_temp, new_index, tempcorrx;
2327 s16 manp, meas_temp, temp_diff;
2328 bool neg = 0;
2329 u16 temp;
2330 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2331
2332 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
2333 return pi_lcn->lcnphy_current_index;
2334
2335 index = FIXED_TXPWR;
2336
2337 if (pi_lcn->lcnphy_tempsense_slope == 0)
2338 return index;
2339
2340 temp = (u16) wlc_lcnphy_tempsense(pi, 0);
2341 meas_temp = LCNPHY_TEMPSENSE(temp);
2342
2343 if (pi->tx_power_min != 0)
2344 delta_brd = (pi_lcn->lcnphy_measPower - pi->tx_power_min);
2345 else
2346 delta_brd = 0;
2347
2348 manp = LCNPHY_TEMPSENSE(pi_lcn->lcnphy_rawtempsense);
2349 temp_diff = manp - meas_temp;
2350 if (temp_diff < 0) {
2351 neg = 1;
2352 temp_diff = -temp_diff;
2353 }
2354
2355 delta_temp = (s8) wlc_lcnphy_qdiv_roundup((u32) (temp_diff * 192),
2356 (u32) (pi_lcn->
2357 lcnphy_tempsense_slope
2358 * 10), 0);
2359 if (neg)
2360 delta_temp = -delta_temp;
2361
2362 if (pi_lcn->lcnphy_tempsense_option == 3
2363 && LCNREV_IS(pi->pubpi.phy_rev, 0))
2364 delta_temp = 0;
2365 if (pi_lcn->lcnphy_tempcorrx > 31)
2366 tempcorrx = (s8) (pi_lcn->lcnphy_tempcorrx - 64);
2367 else
2368 tempcorrx = (s8) pi_lcn->lcnphy_tempcorrx;
2369 if (LCNREV_IS(pi->pubpi.phy_rev, 1))
2370 tempcorrx = 4;
2371 new_index =
2372 index + delta_brd + delta_temp - pi_lcn->lcnphy_bandedge_corr;
2373 new_index += tempcorrx;
2374
2375 if (LCNREV_IS(pi->pubpi.phy_rev, 1))
2376 index = 127;
2377
2378 if (new_index < 0 || new_index > 126)
2379 return index;
2380
2381 return new_index;
2382}
2383
2384static u16 wlc_lcnphy_set_tx_pwr_ctrl_mode(struct brcms_phy *pi, u16 mode)
2385{
2386
2387 u16 current_mode = mode;
2388 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) &&
2389 mode == LCNPHY_TX_PWR_CTRL_HW)
2390 current_mode = LCNPHY_TX_PWR_CTRL_TEMPBASED;
2391 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) &&
2392 mode == LCNPHY_TX_PWR_CTRL_TEMPBASED)
2393 current_mode = LCNPHY_TX_PWR_CTRL_HW;
2394 return current_mode;
2395}
2396
2397void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode)
2398{
2399 u16 old_mode = wlc_lcnphy_get_tx_pwr_ctrl(pi);
2400 s8 index;
2401 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2402
2403 mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, mode);
2404 old_mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, old_mode);
2405
2406 mod_phy_reg(pi, 0x6da, (0x1 << 6),
2407 ((LCNPHY_TX_PWR_CTRL_HW == mode) ? 1 : 0) << 6);
2408
2409 mod_phy_reg(pi, 0x6a3, (0x1 << 4),
2410 ((LCNPHY_TX_PWR_CTRL_HW == mode) ? 0 : 1) << 4);
2411
2412 if (old_mode != mode) {
2413 if (LCNPHY_TX_PWR_CTRL_HW == old_mode) {
2414
2415 wlc_lcnphy_tx_pwr_update_npt(pi);
2416
2417 wlc_lcnphy_clear_tx_power_offsets(pi);
2418 }
2419 if (LCNPHY_TX_PWR_CTRL_HW == mode) {
2420
2421 wlc_lcnphy_txpower_recalc_target(pi);
2422
2423 wlc_lcnphy_set_start_tx_pwr_idx(pi,
2424 pi_lcn->
2425 lcnphy_tssi_idx);
2426 wlc_lcnphy_set_tx_pwr_npt(pi, pi_lcn->lcnphy_tssi_npt);
2427 mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 0);
2428
2429 pi_lcn->lcnphy_tssi_tx_cnt =
2430 wlc_lcnphy_total_tx_frames(pi);
2431
2432 wlc_lcnphy_disable_tx_gain_override(pi);
2433 pi_lcn->lcnphy_tx_power_idx_override = -1;
2434 } else
2435 wlc_lcnphy_enable_tx_gain_override(pi);
2436
2437 mod_phy_reg(pi, 0x4a4,
2438 ((0x1 << 15) | (0x1 << 14) | (0x1 << 13)), mode);
2439 if (mode == LCNPHY_TX_PWR_CTRL_TEMPBASED) {
2440 index = wlc_lcnphy_tempcompensated_txpwrctrl(pi);
2441 wlc_lcnphy_set_tx_pwr_soft_ctrl(pi, index);
2442 pi_lcn->lcnphy_current_index = (s8)
2443 ((read_phy_reg(pi,
2444 0x4a9) &
2445 0xFF) / 2);
2446 }
2447 }
2448}
2449
2450static void
2451wlc_lcnphy_tx_iqlo_loopback(struct brcms_phy *pi, u16 *values_to_save)
2452{
2453 u16 vmid;
2454 int i;
2455 for (i = 0; i < 20; i++)
2456 values_to_save[i] =
2457 read_radio_reg(pi, iqlo_loopback_rf_regs[i]);
2458
2459 mod_phy_reg(pi, 0x44c, (0x1 << 12), 1 << 12);
2460 mod_phy_reg(pi, 0x44d, (0x1 << 14), 1 << 14);
2461
2462 mod_phy_reg(pi, 0x44c, (0x1 << 11), 1 << 11);
2463 mod_phy_reg(pi, 0x44d, (0x1 << 13), 0 << 13);
2464
2465 mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
2466 mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
2467
2468 mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
2469 mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
2470
2471 if (LCNREV_IS(pi->pubpi.phy_rev, 2))
2472 and_radio_reg(pi, RADIO_2064_REG03A, 0xFD);
2473 else
2474 and_radio_reg(pi, RADIO_2064_REG03A, 0xF9);
2475 or_radio_reg(pi, RADIO_2064_REG11A, 0x1);
2476
2477 or_radio_reg(pi, RADIO_2064_REG036, 0x01);
2478 or_radio_reg(pi, RADIO_2064_REG11A, 0x18);
2479 udelay(20);
2480
2481 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
2482 if (CHSPEC_IS5G(pi->radio_chanspec))
2483 mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0);
2484 else
2485 or_radio_reg(pi, RADIO_2064_REG03A, 1);
2486 } else {
2487 if (CHSPEC_IS5G(pi->radio_chanspec))
2488 mod_radio_reg(pi, RADIO_2064_REG03A, 3, 1);
2489 else
2490 or_radio_reg(pi, RADIO_2064_REG03A, 0x3);
2491 }
2492
2493 udelay(20);
2494
2495 write_radio_reg(pi, RADIO_2064_REG025, 0xF);
2496 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
2497 if (CHSPEC_IS5G(pi->radio_chanspec))
2498 mod_radio_reg(pi, RADIO_2064_REG028, 0xF, 0x4);
2499 else
2500 mod_radio_reg(pi, RADIO_2064_REG028, 0xF, 0x6);
2501 } else {
2502 if (CHSPEC_IS5G(pi->radio_chanspec))
2503 mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0x4 << 1);
2504 else
2505 mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0x6 << 1);
2506 }
2507
2508 udelay(20);
2509
2510 write_radio_reg(pi, RADIO_2064_REG005, 0x8);
2511 or_radio_reg(pi, RADIO_2064_REG112, 0x80);
2512 udelay(20);
2513
2514 or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
2515 or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
2516 udelay(20);
2517
2518 or_radio_reg(pi, RADIO_2064_REG00B, 0x7);
2519 or_radio_reg(pi, RADIO_2064_REG113, 0x10);
2520 udelay(20);
2521
2522 write_radio_reg(pi, RADIO_2064_REG007, 0x1);
2523 udelay(20);
2524
2525 vmid = 0x2A6;
2526 mod_radio_reg(pi, RADIO_2064_REG0FC, 0x3 << 0, (vmid >> 8) & 0x3);
2527 write_radio_reg(pi, RADIO_2064_REG0FD, (vmid & 0xff));
2528 or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
2529 udelay(20);
2530
2531 or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
2532 udelay(20);
2533 write_radio_reg(pi, RADIO_2064_REG012, 0x02);
2534 or_radio_reg(pi, RADIO_2064_REG112, 0x06);
2535 write_radio_reg(pi, RADIO_2064_REG036, 0x11);
2536 write_radio_reg(pi, RADIO_2064_REG059, 0xcc);
2537 write_radio_reg(pi, RADIO_2064_REG05C, 0x2e);
2538 write_radio_reg(pi, RADIO_2064_REG078, 0xd7);
2539 write_radio_reg(pi, RADIO_2064_REG092, 0x15);
2540}
2541
2542static bool wlc_lcnphy_iqcal_wait(struct brcms_phy *pi)
2543{
2544 uint delay_count = 0;
2545
2546 while (wlc_lcnphy_iqcal_active(pi)) {
2547 udelay(100);
2548 delay_count++;
2549
2550 if (delay_count > (10 * 500))
2551 break;
2552 }
2553
2554 return (0 == wlc_lcnphy_iqcal_active(pi));
2555}
2556
2557static void
2558wlc_lcnphy_tx_iqlo_loopback_cleanup(struct brcms_phy *pi, u16 *values_to_save)
2559{
2560 int i;
2561
2562 and_phy_reg(pi, 0x44c, 0x0 >> 11);
2563
2564 and_phy_reg(pi, 0x43b, 0xC);
2565
2566 for (i = 0; i < 20; i++)
2567 write_radio_reg(pi, iqlo_loopback_rf_regs[i],
2568 values_to_save[i]);
2569}
2570
2571static void
2572wlc_lcnphy_tx_iqlo_cal(struct brcms_phy *pi,
2573 struct lcnphy_txgains *target_gains,
2574 enum lcnphy_cal_mode cal_mode, bool keep_tone)
2575{
2576
2577 struct lcnphy_txgains cal_gains, temp_gains;
2578 u16 hash;
2579 u8 band_idx;
2580 int j;
2581 u16 ncorr_override[5];
2582 u16 syst_coeffs[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2583 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
2584
2585 u16 commands_fullcal[] = {
2586 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234
2587 };
2588
2589 u16 commands_recal[] = {
2590 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234
2591 };
2592
2593 u16 command_nums_fullcal[] = {
2594 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97
2595 };
2596
2597 u16 command_nums_recal[] = {
2598 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97
2599 };
2600 u16 *command_nums = command_nums_fullcal;
2601
2602 u16 *start_coeffs = NULL, *cal_cmds = NULL, cal_type, diq_start;
2603 u16 tx_pwr_ctrl_old, save_txpwrctrlrfctrl2;
2604 u16 save_sslpnCalibClkEnCtrl, save_sslpnRxFeClkEnCtrl;
2605 bool tx_gain_override_old;
2606 struct lcnphy_txgains old_gains;
2607 uint i, n_cal_cmds = 0, n_cal_start = 0;
2608 u16 *values_to_save;
2609 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2610
2611 values_to_save = kmalloc(sizeof(u16) * 20, GFP_ATOMIC);
2612 if (NULL == values_to_save)
2613 return;
2614
2615 save_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
2616 save_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
2617
2618 or_phy_reg(pi, 0x6da, 0x40);
2619 or_phy_reg(pi, 0x6db, 0x3);
2620
2621 switch (cal_mode) {
2622 case LCNPHY_CAL_FULL:
2623 start_coeffs = syst_coeffs;
2624 cal_cmds = commands_fullcal;
2625 n_cal_cmds = ARRAY_SIZE(commands_fullcal);
2626 break;
2627
2628 case LCNPHY_CAL_RECAL:
2629 start_coeffs = syst_coeffs;
2630 cal_cmds = commands_recal;
2631 n_cal_cmds = ARRAY_SIZE(commands_recal);
2632 command_nums = command_nums_recal;
2633 break;
2634
2635 default:
2636 break;
2637 }
2638
2639 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2640 start_coeffs, 11, 16, 64);
2641
2642 write_phy_reg(pi, 0x6da, 0xffff);
2643 mod_phy_reg(pi, 0x503, (0x1 << 3), (1) << 3);
2644
2645 tx_pwr_ctrl_old = wlc_lcnphy_get_tx_pwr_ctrl(pi);
2646
2647 mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
2648
2649 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
2650
2651 save_txpwrctrlrfctrl2 = read_phy_reg(pi, 0x4db);
2652
2653 mod_phy_reg(pi, 0x4db, (0x3ff << 0), (0x2a6) << 0);
2654
2655 mod_phy_reg(pi, 0x4db, (0x7 << 12), (2) << 12);
2656
2657 wlc_lcnphy_tx_iqlo_loopback(pi, values_to_save);
2658
2659 tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
2660 if (tx_gain_override_old)
2661 wlc_lcnphy_get_tx_gain(pi, &old_gains);
2662
2663 if (!target_gains) {
2664 if (!tx_gain_override_old)
2665 wlc_lcnphy_set_tx_pwr_by_index(pi,
2666 pi_lcn->lcnphy_tssi_idx);
2667 wlc_lcnphy_get_tx_gain(pi, &temp_gains);
2668 target_gains = &temp_gains;
2669 }
2670
2671 hash = (target_gains->gm_gain << 8) |
2672 (target_gains->pga_gain << 4) | (target_gains->pad_gain);
2673
2674 band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0);
2675
2676 cal_gains = *target_gains;
2677 memset(ncorr_override, 0, sizeof(ncorr_override));
2678 for (j = 0; j < iqcal_gainparams_numgains_lcnphy[band_idx]; j++) {
2679 if (hash == tbl_iqcal_gainparams_lcnphy[band_idx][j][0]) {
2680 cal_gains.gm_gain =
2681 tbl_iqcal_gainparams_lcnphy[band_idx][j][1];
2682 cal_gains.pga_gain =
2683 tbl_iqcal_gainparams_lcnphy[band_idx][j][2];
2684 cal_gains.pad_gain =
2685 tbl_iqcal_gainparams_lcnphy[band_idx][j][3];
2686 memcpy(ncorr_override,
2687 &tbl_iqcal_gainparams_lcnphy[band_idx][j][3],
2688 sizeof(ncorr_override));
2689 break;
2690 }
2691 }
2692
2693 wlc_lcnphy_set_tx_gain(pi, &cal_gains);
2694
2695 write_phy_reg(pi, 0x453, 0xaa9);
2696 write_phy_reg(pi, 0x93d, 0xc0);
2697
2698 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2699 lcnphy_iqcal_loft_gainladder,
2700 ARRAY_SIZE(lcnphy_iqcal_loft_gainladder),
2701 16, 0);
2702
2703 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2704 lcnphy_iqcal_ir_gainladder,
2705 ARRAY_SIZE(
2706 lcnphy_iqcal_ir_gainladder), 16,
2707 32);
2708
2709 if (pi->phy_tx_tone_freq) {
2710
2711 wlc_lcnphy_stop_tx_tone(pi);
2712 udelay(5);
2713 wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
2714 } else {
2715 wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
2716 }
2717
2718 write_phy_reg(pi, 0x6da, 0xffff);
2719
2720 for (i = n_cal_start; i < n_cal_cmds; i++) {
2721 u16 zero_diq = 0;
2722 u16 best_coeffs[11];
2723 u16 command_num;
2724
2725 cal_type = (cal_cmds[i] & 0x0f00) >> 8;
2726
2727 command_num = command_nums[i];
2728 if (ncorr_override[cal_type])
2729 command_num =
2730 ncorr_override[cal_type] << 8 | (command_num &
2731 0xff);
2732
2733 write_phy_reg(pi, 0x452, command_num);
2734
2735 if ((cal_type == 3) || (cal_type == 4)) {
2736 wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2737 &diq_start, 1, 16, 69);
2738
2739 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2740 &zero_diq, 1, 16, 69);
2741 }
2742
2743 write_phy_reg(pi, 0x451, cal_cmds[i]);
2744
2745 if (!wlc_lcnphy_iqcal_wait(pi))
2746 goto cleanup;
2747
2748 wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2749 best_coeffs,
2750 ARRAY_SIZE(best_coeffs), 16, 96);
2751 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2752 best_coeffs,
2753 ARRAY_SIZE(best_coeffs), 16, 64);
2754
2755 if ((cal_type == 3) || (cal_type == 4))
2756 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2757 &diq_start, 1, 16, 69);
2758 wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2759 pi_lcn->lcnphy_cal_results.
2760 txiqlocal_bestcoeffs,
2761 ARRAY_SIZE(pi_lcn->
2762 lcnphy_cal_results.
2763 txiqlocal_bestcoeffs),
2764 16, 96);
2765 }
2766
2767 wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2768 pi_lcn->lcnphy_cal_results.
2769 txiqlocal_bestcoeffs,
2770 ARRAY_SIZE(pi_lcn->lcnphy_cal_results.
2771 txiqlocal_bestcoeffs), 16, 96);
2772 pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs_valid = true;
2773
2774 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2775 &pi_lcn->lcnphy_cal_results.
2776 txiqlocal_bestcoeffs[0], 4, 16, 80);
2777
2778 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2779 &pi_lcn->lcnphy_cal_results.
2780 txiqlocal_bestcoeffs[5], 2, 16, 85);
2781
2782cleanup:
2783 wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, values_to_save);
2784 kfree(values_to_save);
2785
2786 if (!keep_tone)
2787 wlc_lcnphy_stop_tx_tone(pi);
2788
2789 write_phy_reg(pi, 0x4db, save_txpwrctrlrfctrl2);
2790
2791 write_phy_reg(pi, 0x453, 0);
2792
2793 if (tx_gain_override_old)
2794 wlc_lcnphy_set_tx_gain(pi, &old_gains);
2795 wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl_old);
2796
2797 write_phy_reg(pi, 0x6da, save_sslpnCalibClkEnCtrl);
2798 write_phy_reg(pi, 0x6db, save_sslpnRxFeClkEnCtrl);
2799
2800}
2801
2802static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi)
2803{
2804 bool suspend, tx_gain_override_old;
2805 struct lcnphy_txgains old_gains;
2806 struct brcms_phy *pi = (struct brcms_phy *) ppi;
2807 u16 idleTssi, idleTssi0_2C, idleTssi0_OB, idleTssi0_regvalue_OB,
2808 idleTssi0_regvalue_2C;
2809 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
2810 u16 SAVE_lpfgain = read_radio_reg(pi, RADIO_2064_REG112);
2811 u16 SAVE_jtag_bb_afe_switch =
2812 read_radio_reg(pi, RADIO_2064_REG007) & 1;
2813 u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10;
2814 u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4;
2815 idleTssi = read_phy_reg(pi, 0x4ab);
2816 suspend =
2817 (0 ==
2818 (R_REG(&((struct brcms_phy *) pi)->regs->maccontrol) &
2819 MCTL_EN_MAC));
2820 if (!suspend)
2821 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2822 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
2823
2824 tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
2825 wlc_lcnphy_get_tx_gain(pi, &old_gains);
2826
2827 wlc_lcnphy_enable_tx_gain_override(pi);
2828 wlc_lcnphy_set_tx_pwr_by_index(pi, 127);
2829 write_radio_reg(pi, RADIO_2064_REG112, 0x6);
2830 mod_radio_reg(pi, RADIO_2064_REG007, 0x1, 1);
2831 mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 1 << 4);
2832 mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 1 << 2);
2833 wlc_lcnphy_tssi_setup(pi);
2834 wlc_phy_do_dummy_tx(pi, true, OFF);
2835 idleTssi = ((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
2836 >> 0);
2837
2838 idleTssi0_2C = ((read_phy_reg(pi, 0x63e) & (0x1ff << 0))
2839 >> 0);
2840
2841 if (idleTssi0_2C >= 256)
2842 idleTssi0_OB = idleTssi0_2C - 256;
2843 else
2844 idleTssi0_OB = idleTssi0_2C + 256;
2845
2846 idleTssi0_regvalue_OB = idleTssi0_OB;
2847 if (idleTssi0_regvalue_OB >= 256)
2848 idleTssi0_regvalue_2C = idleTssi0_regvalue_OB - 256;
2849 else
2850 idleTssi0_regvalue_2C = idleTssi0_regvalue_OB + 256;
2851 mod_phy_reg(pi, 0x4a6, (0x1ff << 0), (idleTssi0_regvalue_2C) << 0);
2852
2853 mod_phy_reg(pi, 0x44c, (0x1 << 12), (0) << 12);
2854
2855 wlc_lcnphy_set_tx_gain_override(pi, tx_gain_override_old);
2856 wlc_lcnphy_set_tx_gain(pi, &old_gains);
2857 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
2858
2859 write_radio_reg(pi, RADIO_2064_REG112, SAVE_lpfgain);
2860 mod_radio_reg(pi, RADIO_2064_REG007, 0x1, SAVE_jtag_bb_afe_switch);
2861 mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, SAVE_jtag_auxpga);
2862 mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, SAVE_iqadc_aux_en);
2863 mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1 << 7);
2864 if (!suspend)
2865 wlapi_enable_mac(pi->sh->physhim);
2866}
2867
2868static void wlc_lcnphy_vbat_temp_sense_setup(struct brcms_phy *pi, u8 mode)
2869{
2870 bool suspend;
2871 u16 save_txpwrCtrlEn;
2872 u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain;
2873 u16 auxpga_vmid;
2874 struct phytbl_info tab;
2875 u32 val;
2876 u8 save_reg007, save_reg0FF, save_reg11F, save_reg005, save_reg025,
2877 save_reg112;
2878 u16 values_to_save[14];
2879 s8 index;
2880 int i;
2881 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2882 udelay(999);
2883
2884 save_reg007 = (u8) read_radio_reg(pi, RADIO_2064_REG007);
2885 save_reg0FF = (u8) read_radio_reg(pi, RADIO_2064_REG0FF);
2886 save_reg11F = (u8) read_radio_reg(pi, RADIO_2064_REG11F);
2887 save_reg005 = (u8) read_radio_reg(pi, RADIO_2064_REG005);
2888 save_reg025 = (u8) read_radio_reg(pi, RADIO_2064_REG025);
2889 save_reg112 = (u8) read_radio_reg(pi, RADIO_2064_REG112);
2890
2891 for (i = 0; i < 14; i++)
2892 values_to_save[i] = read_phy_reg(pi, tempsense_phy_regs[i]);
2893 suspend = (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
2894 if (!suspend)
2895 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2896 save_txpwrCtrlEn = read_radio_reg(pi, 0x4a4);
2897
2898 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
2899 index = pi_lcn->lcnphy_current_index;
2900 wlc_lcnphy_set_tx_pwr_by_index(pi, 127);
2901 mod_radio_reg(pi, RADIO_2064_REG007, 0x1, 0x1);
2902 mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 0x1 << 4);
2903 mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 0x1 << 2);
2904 mod_phy_reg(pi, 0x503, (0x1 << 0), (0) << 0);
2905
2906 mod_phy_reg(pi, 0x503, (0x1 << 2), (0) << 2);
2907
2908 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
2909
2910 mod_phy_reg(pi, 0x4a4, (0x1 << 15), (0) << 15);
2911
2912 mod_phy_reg(pi, 0x4d0, (0x1 << 5), (0) << 5);
2913
2914 mod_phy_reg(pi, 0x4a5, (0xff << 0), (255) << 0);
2915
2916 mod_phy_reg(pi, 0x4a5, (0x7 << 12), (5) << 12);
2917
2918 mod_phy_reg(pi, 0x4a5, (0x7 << 8), (0) << 8);
2919
2920 mod_phy_reg(pi, 0x40d, (0xff << 0), (64) << 0);
2921
2922 mod_phy_reg(pi, 0x40d, (0x7 << 8), (6) << 8);
2923
2924 mod_phy_reg(pi, 0x4a2, (0xff << 0), (64) << 0);
2925
2926 mod_phy_reg(pi, 0x4a2, (0x7 << 8), (6) << 8);
2927
2928 mod_phy_reg(pi, 0x4d9, (0x7 << 4), (2) << 4);
2929
2930 mod_phy_reg(pi, 0x4d9, (0x7 << 8), (3) << 8);
2931
2932 mod_phy_reg(pi, 0x4d9, (0x7 << 12), (1) << 12);
2933
2934 mod_phy_reg(pi, 0x4da, (0x1 << 12), (0) << 12);
2935
2936 mod_phy_reg(pi, 0x4da, (0x1 << 13), (1) << 13);
2937
2938 mod_phy_reg(pi, 0x4a6, (0x1 << 15), (1) << 15);
2939
2940 write_radio_reg(pi, RADIO_2064_REG025, 0xC);
2941
2942 mod_radio_reg(pi, RADIO_2064_REG005, 0x8, 0x1 << 3);
2943
2944 mod_phy_reg(pi, 0x938, (0x1 << 2), (1) << 2);
2945
2946 mod_phy_reg(pi, 0x939, (0x1 << 2), (1) << 2);
2947
2948 mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
2949
2950 val = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi);
2951 tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
2952 tab.tbl_width = 16;
2953 tab.tbl_len = 1;
2954 tab.tbl_ptr = &val;
2955 tab.tbl_offset = 6;
2956 wlc_lcnphy_write_table(pi, &tab);
2957 if (mode == TEMPSENSE) {
2958 mod_phy_reg(pi, 0x4d7, (0x1 << 3), (1) << 3);
2959
2960 mod_phy_reg(pi, 0x4d7, (0x7 << 12), (1) << 12);
2961
2962 auxpga_vmidcourse = 8;
2963 auxpga_vmidfine = 0x4;
2964 auxpga_gain = 2;
2965 mod_radio_reg(pi, RADIO_2064_REG082, 0x20, 1 << 5);
2966 } else {
2967 mod_phy_reg(pi, 0x4d7, (0x1 << 3), (1) << 3);
2968
2969 mod_phy_reg(pi, 0x4d7, (0x7 << 12), (3) << 12);
2970
2971 auxpga_vmidcourse = 7;
2972 auxpga_vmidfine = 0xa;
2973 auxpga_gain = 2;
2974 }
2975 auxpga_vmid =
2976 (u16) ((2 << 8) | (auxpga_vmidcourse << 4) | auxpga_vmidfine);
2977 mod_phy_reg(pi, 0x4d8, (0x1 << 0), (1) << 0);
2978
2979 mod_phy_reg(pi, 0x4d8, (0x3ff << 2), (auxpga_vmid) << 2);
2980
2981 mod_phy_reg(pi, 0x4d8, (0x1 << 1), (1) << 1);
2982
2983 mod_phy_reg(pi, 0x4d8, (0x7 << 12), (auxpga_gain) << 12);
2984
2985 mod_phy_reg(pi, 0x4d0, (0x1 << 5), (1) << 5);
2986
2987 write_radio_reg(pi, RADIO_2064_REG112, 0x6);
2988
2989 wlc_phy_do_dummy_tx(pi, true, OFF);
2990 if (!tempsense_done(pi))
2991 udelay(10);
2992
2993 write_radio_reg(pi, RADIO_2064_REG007, (u16) save_reg007);
2994 write_radio_reg(pi, RADIO_2064_REG0FF, (u16) save_reg0FF);
2995 write_radio_reg(pi, RADIO_2064_REG11F, (u16) save_reg11F);
2996 write_radio_reg(pi, RADIO_2064_REG005, (u16) save_reg005);
2997 write_radio_reg(pi, RADIO_2064_REG025, (u16) save_reg025);
2998 write_radio_reg(pi, RADIO_2064_REG112, (u16) save_reg112);
2999 for (i = 0; i < 14; i++)
3000 write_phy_reg(pi, tempsense_phy_regs[i], values_to_save[i]);
3001 wlc_lcnphy_set_tx_pwr_by_index(pi, (int)index);
3002
3003 write_radio_reg(pi, 0x4a4, save_txpwrCtrlEn);
3004 if (!suspend)
3005 wlapi_enable_mac(pi->sh->physhim);
3006 udelay(999);
3007}
3008
3009static void wlc_lcnphy_tx_pwr_ctrl_init(struct brcms_phy_pub *ppi)
3010{
3011 struct lcnphy_txgains tx_gains;
3012 u8 bbmult;
3013 struct phytbl_info tab;
3014 s32 a1, b0, b1;
3015 s32 tssi, pwr, maxtargetpwr, mintargetpwr;
3016 bool suspend;
3017 struct brcms_phy *pi = (struct brcms_phy *) ppi;
3018
3019 suspend =
3020 (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
3021 if (!suspend)
3022 wlapi_suspend_mac_and_wait(pi->sh->physhim);
3023
3024 if (!pi->hwpwrctrl_capable) {
3025 if (CHSPEC_IS2G(pi->radio_chanspec)) {
3026 tx_gains.gm_gain = 4;
3027 tx_gains.pga_gain = 12;
3028 tx_gains.pad_gain = 12;
3029 tx_gains.dac_gain = 0;
3030
3031 bbmult = 150;
3032 } else {
3033 tx_gains.gm_gain = 7;
3034 tx_gains.pga_gain = 15;
3035 tx_gains.pad_gain = 14;
3036 tx_gains.dac_gain = 0;
3037
3038 bbmult = 150;
3039 }
3040 wlc_lcnphy_set_tx_gain(pi, &tx_gains);
3041 wlc_lcnphy_set_bbmult(pi, bbmult);
3042 wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
3043 } else {
3044
3045 wlc_lcnphy_idle_tssi_est(ppi);
3046
3047 wlc_lcnphy_clear_tx_power_offsets(pi);
3048
3049 b0 = pi->txpa_2g[0];
3050 b1 = pi->txpa_2g[1];
3051 a1 = pi->txpa_2g[2];
3052 maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1);
3053 mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1);
3054
3055 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
3056 tab.tbl_width = 32;
3057 tab.tbl_ptr = &pwr;
3058 tab.tbl_len = 1;
3059 tab.tbl_offset = 0;
3060 for (tssi = 0; tssi < 128; tssi++) {
3061 pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1);
3062
3063 pwr = (pwr < mintargetpwr) ? mintargetpwr : pwr;
3064 wlc_lcnphy_write_table(pi, &tab);
3065 tab.tbl_offset++;
3066 }
3067
3068 mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7);
3069
3070 write_phy_reg(pi, 0x4a8, 10);
3071
3072 wlc_lcnphy_set_target_tx_pwr(pi, LCN_TARGET_PWR);
3073
3074 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_HW);
3075 }
3076 if (!suspend)
3077 wlapi_enable_mac(pi->sh->physhim);
3078}
3079
3080static u8 wlc_lcnphy_get_bbmult(struct brcms_phy *pi)
3081{
3082 u16 m0m1;
3083 struct phytbl_info tab;
3084
3085 tab.tbl_ptr = &m0m1;
3086 tab.tbl_len = 1;
3087 tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
3088 tab.tbl_offset = 87;
3089 tab.tbl_width = 16;
3090 wlc_lcnphy_read_table(pi, &tab);
3091
3092 return (u8) ((m0m1 & 0xff00) >> 8);
3093}
3094
3095static void wlc_lcnphy_set_pa_gain(struct brcms_phy *pi, u16 gain)
3096{
3097 mod_phy_reg(pi, 0x4fb,
3098 LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK,
3099 gain << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT);
3100 mod_phy_reg(pi, 0x4fd,
3101 LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_MASK,
3102 gain << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT);
3103}
3104
3105void
3106wlc_lcnphy_get_radio_loft(struct brcms_phy *pi,
3107 u8 *ei0, u8 *eq0, u8 *fi0, u8 *fq0)
3108{
3109 *ei0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG089));
3110 *eq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08A));
3111 *fi0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08B));
3112 *fq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08C));
3113}
3114
3115void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b)
3116{
3117 struct phytbl_info tab;
3118 u16 iqcc[2];
3119
3120 iqcc[0] = a;
3121 iqcc[1] = b;
3122
3123 tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
3124 tab.tbl_width = 16;
3125 tab.tbl_ptr = iqcc;
3126 tab.tbl_len = 2;
3127 tab.tbl_offset = 80;
3128 wlc_lcnphy_write_table(pi, &tab);
3129}
3130
3131void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq)
3132{
3133 struct phytbl_info tab;
3134
3135 tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
3136 tab.tbl_width = 16;
3137 tab.tbl_ptr = &didq;
3138 tab.tbl_len = 1;
3139 tab.tbl_offset = 85;
3140 wlc_lcnphy_write_table(pi, &tab);
3141}
3142
3143void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index)
3144{
3145 struct phytbl_info tab;
3146 u16 a, b;
3147 u8 bb_mult;
3148 u32 bbmultiqcomp, txgain, locoeffs, rfpower;
3149 struct lcnphy_txgains gains;
3150 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3151
3152 pi_lcn->lcnphy_tx_power_idx_override = (s8) index;
3153 pi_lcn->lcnphy_current_index = (u8) index;
3154
3155 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
3156 tab.tbl_width = 32;
3157 tab.tbl_len = 1;
3158
3159 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
3160
3161 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + index;
3162 tab.tbl_ptr = &bbmultiqcomp;
3163 wlc_lcnphy_read_table(pi, &tab);
3164
3165 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + index;
3166 tab.tbl_width = 32;
3167 tab.tbl_ptr = &txgain;
3168 wlc_lcnphy_read_table(pi, &tab);
3169
3170 gains.gm_gain = (u16) (txgain & 0xff);
3171 gains.pga_gain = (u16) (txgain >> 8) & 0xff;
3172 gains.pad_gain = (u16) (txgain >> 16) & 0xff;
3173 gains.dac_gain = (u16) (bbmultiqcomp >> 28) & 0x07;
3174 wlc_lcnphy_set_tx_gain(pi, &gains);
3175 wlc_lcnphy_set_pa_gain(pi, (u16) (txgain >> 24) & 0x7f);
3176
3177 bb_mult = (u8) ((bbmultiqcomp >> 20) & 0xff);
3178 wlc_lcnphy_set_bbmult(pi, bb_mult);
3179
3180 wlc_lcnphy_enable_tx_gain_override(pi);
3181
3182 if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
3183
3184 a = (u16) ((bbmultiqcomp >> 10) & 0x3ff);
3185 b = (u16) (bbmultiqcomp & 0x3ff);
3186 wlc_lcnphy_set_tx_iqcc(pi, a, b);
3187
3188 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + index;
3189 tab.tbl_ptr = &locoeffs;
3190 wlc_lcnphy_read_table(pi, &tab);
3191
3192 wlc_lcnphy_set_tx_locc(pi, (u16) locoeffs);
3193
3194 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index;
3195 tab.tbl_ptr = &rfpower;
3196 wlc_lcnphy_read_table(pi, &tab);
3197 mod_phy_reg(pi, 0x6a6, (0x1fff << 0), (rfpower * 8) << 0);
3198
3199 }
3200}
3201
3202static void wlc_lcnphy_clear_papd_comptable(struct brcms_phy *pi)
3203{
3204 u32 j;
3205 struct phytbl_info tab;
3206 u32 temp_offset[128];
3207 tab.tbl_ptr = temp_offset;
3208 tab.tbl_len = 128;
3209 tab.tbl_id = LCNPHY_TBL_ID_PAPDCOMPDELTATBL;
3210 tab.tbl_width = 32;
3211 tab.tbl_offset = 0;
3212
3213 memset(temp_offset, 0, sizeof(temp_offset));
3214 for (j = 1; j < 128; j += 2)
3215 temp_offset[j] = 0x80000;
3216
3217 wlc_lcnphy_write_table(pi, &tab);
3218 return;
3219}
3220
3221void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable)
3222{
3223 if (!bEnable) {
3224
3225 and_phy_reg(pi, 0x43b, ~(u16) ((0x1 << 1) | (0x1 << 4)));
3226
3227 mod_phy_reg(pi, 0x43c, (0x1 << 1), 1 << 1);
3228
3229 and_phy_reg(pi, 0x44c,
3230 ~(u16) ((0x1 << 3) |
3231 (0x1 << 5) |
3232 (0x1 << 12) |
3233 (0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
3234
3235 and_phy_reg(pi, 0x44d,
3236 ~(u16) ((0x1 << 3) | (0x1 << 5) | (0x1 << 14)));
3237 mod_phy_reg(pi, 0x44d, (0x1 << 2), 1 << 2);
3238
3239 mod_phy_reg(pi, 0x44d, (0x1 << 1) | (0x1 << 0), (0x1 << 0));
3240
3241 and_phy_reg(pi, 0x4f9,
3242 ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
3243
3244 and_phy_reg(pi, 0x4fa,
3245 ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
3246 } else {
3247
3248 mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
3249 mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
3250
3251 mod_phy_reg(pi, 0x43b, (0x1 << 4), 1 << 4);
3252 mod_phy_reg(pi, 0x43c, (0x1 << 6), 0 << 6);
3253
3254 mod_phy_reg(pi, 0x44c, (0x1 << 12), 1 << 12);
3255 mod_phy_reg(pi, 0x44d, (0x1 << 14), 1 << 14);
3256
3257 wlc_lcnphy_set_trsw_override(pi, true, false);
3258
3259 mod_phy_reg(pi, 0x44d, (0x1 << 2), 0 << 2);
3260 mod_phy_reg(pi, 0x44c, (0x1 << 2), 1 << 2);
3261
3262 if (CHSPEC_IS2G(pi->radio_chanspec)) {
3263
3264 mod_phy_reg(pi, 0x44c, (0x1 << 3), 1 << 3);
3265 mod_phy_reg(pi, 0x44d, (0x1 << 3), 1 << 3);
3266
3267 mod_phy_reg(pi, 0x44c, (0x1 << 5), 1 << 5);
3268 mod_phy_reg(pi, 0x44d, (0x1 << 5), 0 << 5);
3269
3270 mod_phy_reg(pi, 0x4f9, (0x1 << 1), 1 << 1);
3271 mod_phy_reg(pi, 0x4fa, (0x1 << 1), 1 << 1);
3272
3273 mod_phy_reg(pi, 0x4f9, (0x1 << 2), 1 << 2);
3274 mod_phy_reg(pi, 0x4fa, (0x1 << 2), 1 << 2);
3275
3276 mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
3277 mod_phy_reg(pi, 0x4fa, (0x1 << 0), 1 << 0);
3278 } else {
3279
3280 mod_phy_reg(pi, 0x44c, (0x1 << 3), 1 << 3);
3281 mod_phy_reg(pi, 0x44d, (0x1 << 3), 0 << 3);
3282
3283 mod_phy_reg(pi, 0x44c, (0x1 << 5), 1 << 5);
3284 mod_phy_reg(pi, 0x44d, (0x1 << 5), 1 << 5);
3285
3286 mod_phy_reg(pi, 0x4f9, (0x1 << 1), 1 << 1);
3287 mod_phy_reg(pi, 0x4fa, (0x1 << 1), 0 << 1);
3288
3289 mod_phy_reg(pi, 0x4f9, (0x1 << 2), 1 << 2);
3290 mod_phy_reg(pi, 0x4fa, (0x1 << 2), 0 << 2);
3291
3292 mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
3293 mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
3294 }
3295 }
3296}
3297
3298static void
3299wlc_lcnphy_run_samples(struct brcms_phy *pi,
3300 u16 num_samps,
3301 u16 num_loops, u16 wait, bool iqcalmode)
3302{
3303
3304 or_phy_reg(pi, 0x6da, 0x8080);
3305
3306 mod_phy_reg(pi, 0x642, (0x7f << 0), (num_samps - 1) << 0);
3307 if (num_loops != 0xffff)
3308 num_loops--;
3309 mod_phy_reg(pi, 0x640, (0xffff << 0), num_loops << 0);
3310
3311 mod_phy_reg(pi, 0x641, (0xffff << 0), wait << 0);
3312
3313 if (iqcalmode) {
3314
3315 and_phy_reg(pi, 0x453, (u16) ~(0x1 << 15));
3316 or_phy_reg(pi, 0x453, (0x1 << 15));
3317 } else {
3318 write_phy_reg(pi, 0x63f, 1);
3319 wlc_lcnphy_tx_pu(pi, 1);
3320 }
3321
3322 or_radio_reg(pi, RADIO_2064_REG112, 0x6);
3323}
3324
3325void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode)
3326{
3327
3328 u8 phybw40;
3329 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
3330
3331 if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
3332 mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
3333 mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
3334 } else {
3335 mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
3336 mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
3337 }
3338
3339 if (phybw40 == 0) {
3340 mod_phy_reg((pi), 0x410,
3341 (0x1 << 6) |
3342 (0x1 << 5),
3343 ((CHSPEC_IS2G(
3344 pi->radio_chanspec)) ? (!mode) : 0) <<
3345 6 | (!mode) << 5);
3346 mod_phy_reg(pi, 0x410, (0x1 << 7), (mode) << 7);
3347 }
3348}
3349
3350void
3351wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz, u16 max_val,
3352 bool iqcalmode)
3353{
3354 u8 phy_bw;
3355 u16 num_samps, t, k;
3356 u32 bw;
3357 s32 theta = 0, rot = 0;
3358 struct cordic_iq tone_samp;
3359 u32 data_buf[64];
3360 u16 i_samp, q_samp;
3361 struct phytbl_info tab;
3362 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3363
3364 pi->phy_tx_tone_freq = f_kHz;
3365
3366 wlc_lcnphy_deaf_mode(pi, true);
3367
3368 phy_bw = 40;
3369 if (pi_lcn->lcnphy_spurmod) {
3370 write_phy_reg(pi, 0x942, 0x2);
3371 write_phy_reg(pi, 0x93b, 0x0);
3372 write_phy_reg(pi, 0x93c, 0x0);
3373 wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
3374 }
3375
3376 if (f_kHz) {
3377 k = 1;
3378 do {
3379 bw = phy_bw * 1000 * k;
3380 num_samps = bw / abs(f_kHz);
3381 k++;
3382 } while ((num_samps * (u32) (abs(f_kHz))) != bw);
3383 } else
3384 num_samps = 2;
3385
3386 rot = ((f_kHz * 36) / phy_bw) / 100;
3387 theta = 0;
3388
3389 for (t = 0; t < num_samps; t++) {
3390
3391 tone_samp = cordic_calc_iq(theta);
3392
3393 theta += rot;
3394
3395 i_samp = (u16) (FLOAT(tone_samp.i * max_val) & 0x3ff);
3396 q_samp = (u16) (FLOAT(tone_samp.q * max_val) & 0x3ff);
3397 data_buf[t] = (i_samp << 10) | q_samp;
3398 }
3399
3400 mod_phy_reg(pi, 0x6d6, (0x3 << 0), 0 << 0);
3401
3402 mod_phy_reg(pi, 0x6da, (0x1 << 3), 1 << 3);
3403
3404 tab.tbl_ptr = data_buf;
3405 tab.tbl_len = num_samps;
3406 tab.tbl_id = LCNPHY_TBL_ID_SAMPLEPLAY;
3407 tab.tbl_offset = 0;
3408 tab.tbl_width = 32;
3409 wlc_lcnphy_write_table(pi, &tab);
3410
3411 wlc_lcnphy_run_samples(pi, num_samps, 0xffff, 0, iqcalmode);
3412}
3413
3414void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi)
3415{
3416 s16 playback_status;
3417 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3418
3419 pi->phy_tx_tone_freq = 0;
3420 if (pi_lcn->lcnphy_spurmod) {
3421 write_phy_reg(pi, 0x942, 0x7);
3422 write_phy_reg(pi, 0x93b, 0x2017);
3423 write_phy_reg(pi, 0x93c, 0x27c5);
3424 wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
3425 }
3426
3427 playback_status = read_phy_reg(pi, 0x644);
3428 if (playback_status & (0x1 << 0)) {
3429 wlc_lcnphy_tx_pu(pi, 0);
3430 mod_phy_reg(pi, 0x63f, (0x1 << 1), 1 << 1);
3431 } else if (playback_status & (0x1 << 1))
3432 mod_phy_reg(pi, 0x453, (0x1 << 15), 0 << 15);
3433
3434 mod_phy_reg(pi, 0x6d6, (0x3 << 0), 1 << 0);
3435
3436 mod_phy_reg(pi, 0x6da, (0x1 << 3), 0 << 3);
3437
3438 mod_phy_reg(pi, 0x6da, (0x1 << 7), 0 << 7);
3439
3440 and_radio_reg(pi, RADIO_2064_REG112, 0xFFF9);
3441
3442 wlc_lcnphy_deaf_mode(pi, false);
3443}
3444
3445static void
3446wlc_lcnphy_set_cc(struct brcms_phy *pi, int cal_type, s16 coeff_x, s16 coeff_y)
3447{
3448 u16 di0dq0;
3449 u16 x, y, data_rf;
3450 int k;
3451 switch (cal_type) {
3452 case 0:
3453 wlc_lcnphy_set_tx_iqcc(pi, coeff_x, coeff_y);
3454 break;
3455 case 2:
3456 di0dq0 = (coeff_x & 0xff) << 8 | (coeff_y & 0xff);
3457 wlc_lcnphy_set_tx_locc(pi, di0dq0);
3458 break;
3459 case 3:
3460 k = wlc_lcnphy_calc_floor(coeff_x, 0);
3461 y = 8 + k;
3462 k = wlc_lcnphy_calc_floor(coeff_x, 1);
3463 x = 8 - k;
3464 data_rf = (x * 16 + y);
3465 write_radio_reg(pi, RADIO_2064_REG089, data_rf);
3466 k = wlc_lcnphy_calc_floor(coeff_y, 0);
3467 y = 8 + k;
3468 k = wlc_lcnphy_calc_floor(coeff_y, 1);
3469 x = 8 - k;
3470 data_rf = (x * 16 + y);
3471 write_radio_reg(pi, RADIO_2064_REG08A, data_rf);
3472 break;
3473 case 4:
3474 k = wlc_lcnphy_calc_floor(coeff_x, 0);
3475 y = 8 + k;
3476 k = wlc_lcnphy_calc_floor(coeff_x, 1);
3477 x = 8 - k;
3478 data_rf = (x * 16 + y);
3479 write_radio_reg(pi, RADIO_2064_REG08B, data_rf);
3480 k = wlc_lcnphy_calc_floor(coeff_y, 0);
3481 y = 8 + k;
3482 k = wlc_lcnphy_calc_floor(coeff_y, 1);
3483 x = 8 - k;
3484 data_rf = (x * 16 + y);
3485 write_radio_reg(pi, RADIO_2064_REG08C, data_rf);
3486 break;
3487 }
3488}
3489
3490static struct lcnphy_unsign16_struct
3491wlc_lcnphy_get_cc(struct brcms_phy *pi, int cal_type)
3492{
3493 u16 a, b, didq;
3494 u8 di0, dq0, ei, eq, fi, fq;
3495 struct lcnphy_unsign16_struct cc;
3496 cc.re = 0;
3497 cc.im = 0;
3498 switch (cal_type) {
3499 case 0:
3500 wlc_lcnphy_get_tx_iqcc(pi, &a, &b);
3501 cc.re = a;
3502 cc.im = b;
3503 break;
3504 case 2:
3505 didq = wlc_lcnphy_get_tx_locc(pi);
3506 di0 = (((didq & 0xff00) << 16) >> 24);
3507 dq0 = (((didq & 0x00ff) << 24) >> 24);
3508 cc.re = (u16) di0;
3509 cc.im = (u16) dq0;
3510 break;
3511 case 3:
3512 wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq);
3513 cc.re = (u16) ei;
3514 cc.im = (u16) eq;
3515 break;
3516 case 4:
3517 wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq);
3518 cc.re = (u16) fi;
3519 cc.im = (u16) fq;
3520 break;
3521 }
3522 return cc;
3523}
3524
3525static void
3526wlc_lcnphy_samp_cap(struct brcms_phy *pi, int clip_detect_algo, u16 thresh,
3527 s16 *ptr, int mode)
3528{
3529 u32 curval1, curval2, stpptr, curptr, strptr, val;
3530 u16 sslpnCalibClkEnCtrl, timer;
3531 u16 old_sslpnCalibClkEnCtrl;
3532 s16 imag, real;
3533 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3534
3535 timer = 0;
3536 old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
3537
3538 curval1 = R_REG(&pi->regs->psm_corectlsts);
3539 ptr[130] = 0;
3540 W_REG(&pi->regs->psm_corectlsts, ((1 << 6) | curval1));
3541
3542 W_REG(&pi->regs->smpl_clct_strptr, 0x7E00);
3543 W_REG(&pi->regs->smpl_clct_stpptr, 0x8000);
3544 udelay(20);
3545 curval2 = R_REG(&pi->regs->psm_phy_hdr_param);
3546 W_REG(&pi->regs->psm_phy_hdr_param, curval2 | 0x30);
3547
3548 write_phy_reg(pi, 0x555, 0x0);
3549 write_phy_reg(pi, 0x5a6, 0x5);
3550
3551 write_phy_reg(pi, 0x5a2, (u16) (mode | mode << 6));
3552 write_phy_reg(pi, 0x5cf, 3);
3553 write_phy_reg(pi, 0x5a5, 0x3);
3554 write_phy_reg(pi, 0x583, 0x0);
3555 write_phy_reg(pi, 0x584, 0x0);
3556 write_phy_reg(pi, 0x585, 0x0fff);
3557 write_phy_reg(pi, 0x586, 0x0000);
3558
3559 write_phy_reg(pi, 0x580, 0x4501);
3560
3561 sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
3562 write_phy_reg(pi, 0x6da, (u32) (sslpnCalibClkEnCtrl | 0x2008));
3563 stpptr = R_REG(&pi->regs->smpl_clct_stpptr);
3564 curptr = R_REG(&pi->regs->smpl_clct_curptr);
3565 do {
3566 udelay(10);
3567 curptr = R_REG(&pi->regs->smpl_clct_curptr);
3568 timer++;
3569 } while ((curptr != stpptr) && (timer < 500));
3570
3571 W_REG(&pi->regs->psm_phy_hdr_param, 0x2);
3572 strptr = 0x7E00;
3573 W_REG(&pi->regs->tplatewrptr, strptr);
3574 while (strptr < 0x8000) {
3575 val = R_REG(&pi->regs->tplatewrdata);
3576 imag = ((val >> 16) & 0x3ff);
3577 real = ((val) & 0x3ff);
3578 if (imag > 511)
3579 imag -= 1024;
3580
3581 if (real > 511)
3582 real -= 1024;
3583
3584 if (pi_lcn->lcnphy_iqcal_swp_dis)
3585 ptr[(strptr - 0x7E00) / 4] = real;
3586 else
3587 ptr[(strptr - 0x7E00) / 4] = imag;
3588
3589 if (clip_detect_algo) {
3590 if (imag > thresh || imag < -thresh) {
3591 strptr = 0x8000;
3592 ptr[130] = 1;
3593 }
3594 }
3595
3596 strptr += 4;
3597 }
3598
3599 write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
3600 W_REG(&pi->regs->psm_phy_hdr_param, curval2);
3601 W_REG(&pi->regs->psm_corectlsts, curval1);
3602}
3603
3604static void
3605wlc_lcnphy_a1(struct brcms_phy *pi, int cal_type, int num_levels,
3606 int step_size_lg2)
3607{
3608 const struct lcnphy_spb_tone *phy_c1;
3609 struct lcnphy_spb_tone phy_c2;
3610 struct lcnphy_unsign16_struct phy_c3;
3611 int phy_c4, phy_c5, k, l, j, phy_c6;
3612 u16 phy_c7, phy_c8, phy_c9;
3613 s16 phy_c10, phy_c11, phy_c12, phy_c13, phy_c14, phy_c15, phy_c16;
3614 s16 *ptr, phy_c17;
3615 s32 phy_c18, phy_c19;
3616 u32 phy_c20, phy_c21;
3617 bool phy_c22, phy_c23, phy_c24, phy_c25;
3618 u16 phy_c26, phy_c27;
3619 u16 phy_c28, phy_c29, phy_c30;
3620 u16 phy_c31;
3621 u16 *phy_c32;
3622 phy_c21 = 0;
3623 phy_c10 = phy_c13 = phy_c14 = phy_c8 = 0;
3624 ptr = kmalloc(sizeof(s16) * 131, GFP_ATOMIC);
3625 if (NULL == ptr)
3626 return;
3627
3628 phy_c32 = kmalloc(sizeof(u16) * 20, GFP_ATOMIC);
3629 if (NULL == phy_c32) {
3630 kfree(ptr);
3631 return;
3632 }
3633 phy_c26 = read_phy_reg(pi, 0x6da);
3634 phy_c27 = read_phy_reg(pi, 0x6db);
3635 phy_c31 = read_radio_reg(pi, RADIO_2064_REG026);
3636 write_phy_reg(pi, 0x93d, 0xC0);
3637
3638 wlc_lcnphy_start_tx_tone(pi, 3750, 88, 0);
3639 write_phy_reg(pi, 0x6da, 0xffff);
3640 or_phy_reg(pi, 0x6db, 0x3);
3641
3642 wlc_lcnphy_tx_iqlo_loopback(pi, phy_c32);
3643 udelay(500);
3644 phy_c28 = read_phy_reg(pi, 0x938);
3645 phy_c29 = read_phy_reg(pi, 0x4d7);
3646 phy_c30 = read_phy_reg(pi, 0x4d8);
3647 or_phy_reg(pi, 0x938, 0x1 << 2);
3648 or_phy_reg(pi, 0x4d7, 0x1 << 2);
3649 or_phy_reg(pi, 0x4d7, 0x1 << 3);
3650 mod_phy_reg(pi, 0x4d7, (0x7 << 12), 0x2 << 12);
3651 or_phy_reg(pi, 0x4d8, 1 << 0);
3652 or_phy_reg(pi, 0x4d8, 1 << 1);
3653 mod_phy_reg(pi, 0x4d8, (0x3ff << 2), 0x23A << 2);
3654 mod_phy_reg(pi, 0x4d8, (0x7 << 12), 0x7 << 12);
3655 phy_c1 = &lcnphy_spb_tone_3750[0];
3656 phy_c4 = 32;
3657
3658 if (num_levels == 0) {
3659 if (cal_type != 0)
3660 num_levels = 4;
3661 else
3662 num_levels = 9;
3663 }
3664 if (step_size_lg2 == 0) {
3665 if (cal_type != 0)
3666 step_size_lg2 = 3;
3667 else
3668 step_size_lg2 = 8;
3669 }
3670
3671 phy_c7 = (1 << step_size_lg2);
3672 phy_c3 = wlc_lcnphy_get_cc(pi, cal_type);
3673 phy_c15 = (s16) phy_c3.re;
3674 phy_c16 = (s16) phy_c3.im;
3675 if (cal_type == 2) {
3676 if (phy_c3.re > 127)
3677 phy_c15 = phy_c3.re - 256;
3678 if (phy_c3.im > 127)
3679 phy_c16 = phy_c3.im - 256;
3680 }
3681 wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
3682 udelay(20);
3683 for (phy_c8 = 0; phy_c7 != 0 && phy_c8 < num_levels; phy_c8++) {
3684 phy_c23 = 1;
3685 phy_c22 = 0;
3686 switch (cal_type) {
3687 case 0:
3688 phy_c10 = 511;
3689 break;
3690 case 2:
3691 phy_c10 = 127;
3692 break;
3693 case 3:
3694 phy_c10 = 15;
3695 break;
3696 case 4:
3697 phy_c10 = 15;
3698 break;
3699 }
3700
3701 phy_c9 = read_phy_reg(pi, 0x93d);
3702 phy_c9 = 2 * phy_c9;
3703 phy_c24 = 0;
3704 phy_c5 = 7;
3705 phy_c25 = 1;
3706 while (1) {
3707 write_radio_reg(pi, RADIO_2064_REG026,
3708 (phy_c5 & 0x7) | ((phy_c5 & 0x7) << 4));
3709 udelay(50);
3710 phy_c22 = 0;
3711 ptr[130] = 0;
3712 wlc_lcnphy_samp_cap(pi, 1, phy_c9, &ptr[0], 2);
3713 if (ptr[130] == 1)
3714 phy_c22 = 1;
3715 if (phy_c22)
3716 phy_c5 -= 1;
3717 if ((phy_c22 != phy_c24) && (!phy_c25))
3718 break;
3719 if (!phy_c22)
3720 phy_c5 += 1;
3721 if (phy_c5 <= 0 || phy_c5 >= 7)
3722 break;
3723 phy_c24 = phy_c22;
3724 phy_c25 = 0;
3725 }
3726
3727 if (phy_c5 < 0)
3728 phy_c5 = 0;
3729 else if (phy_c5 > 7)
3730 phy_c5 = 7;
3731
3732 for (k = -phy_c7; k <= phy_c7; k += phy_c7) {
3733 for (l = -phy_c7; l <= phy_c7; l += phy_c7) {
3734 phy_c11 = phy_c15 + k;
3735 phy_c12 = phy_c16 + l;
3736
3737 if (phy_c11 < -phy_c10)
3738 phy_c11 = -phy_c10;
3739 else if (phy_c11 > phy_c10)
3740 phy_c11 = phy_c10;
3741 if (phy_c12 < -phy_c10)
3742 phy_c12 = -phy_c10;
3743 else if (phy_c12 > phy_c10)
3744 phy_c12 = phy_c10;
3745 wlc_lcnphy_set_cc(pi, cal_type, phy_c11,
3746 phy_c12);
3747 udelay(20);
3748 wlc_lcnphy_samp_cap(pi, 0, 0, ptr, 2);
3749
3750 phy_c18 = 0;
3751 phy_c19 = 0;
3752 for (j = 0; j < 128; j++) {
3753 if (cal_type != 0)
3754 phy_c6 = j % phy_c4;
3755 else
3756 phy_c6 = (2 * j) % phy_c4;
3757
3758 phy_c2.re = phy_c1[phy_c6].re;
3759 phy_c2.im = phy_c1[phy_c6].im;
3760 phy_c17 = ptr[j];
3761 phy_c18 = phy_c18 + phy_c17 * phy_c2.re;
3762 phy_c19 = phy_c19 + phy_c17 * phy_c2.im;
3763 }
3764
3765 phy_c18 = phy_c18 >> 10;
3766 phy_c19 = phy_c19 >> 10;
3767 phy_c20 = ((phy_c18 * phy_c18) +
3768 (phy_c19 * phy_c19));
3769
3770 if (phy_c23 || phy_c20 < phy_c21) {
3771 phy_c21 = phy_c20;
3772 phy_c13 = phy_c11;
3773 phy_c14 = phy_c12;
3774 }
3775 phy_c23 = 0;
3776 }
3777 }
3778 phy_c23 = 1;
3779 phy_c15 = phy_c13;
3780 phy_c16 = phy_c14;
3781 phy_c7 = phy_c7 >> 1;
3782 wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
3783 udelay(20);
3784 }
3785 goto cleanup;
3786cleanup:
3787 wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, phy_c32);
3788 wlc_lcnphy_stop_tx_tone(pi);
3789 write_phy_reg(pi, 0x6da, phy_c26);
3790 write_phy_reg(pi, 0x6db, phy_c27);
3791 write_phy_reg(pi, 0x938, phy_c28);
3792 write_phy_reg(pi, 0x4d7, phy_c29);
3793 write_phy_reg(pi, 0x4d8, phy_c30);
3794 write_radio_reg(pi, RADIO_2064_REG026, phy_c31);
3795
3796 kfree(phy_c32);
3797 kfree(ptr);
3798}
3799
3800void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b)
3801{
3802 u16 iqcc[2];
3803 struct phytbl_info tab;
3804
3805 tab.tbl_ptr = iqcc;
3806 tab.tbl_len = 2;
3807 tab.tbl_id = 0;
3808 tab.tbl_offset = 80;
3809 tab.tbl_width = 16;
3810 wlc_lcnphy_read_table(pi, &tab);
3811
3812 *a = iqcc[0];
3813 *b = iqcc[1];
3814}
3815
3816static void wlc_lcnphy_tx_iqlo_soft_cal_full(struct brcms_phy *pi)
3817{
3818 struct lcnphy_unsign16_struct iqcc0, locc2, locc3, locc4;
3819
3820 wlc_lcnphy_set_cc(pi, 0, 0, 0);
3821 wlc_lcnphy_set_cc(pi, 2, 0, 0);
3822 wlc_lcnphy_set_cc(pi, 3, 0, 0);
3823 wlc_lcnphy_set_cc(pi, 4, 0, 0);
3824
3825 wlc_lcnphy_a1(pi, 4, 0, 0);
3826 wlc_lcnphy_a1(pi, 3, 0, 0);
3827 wlc_lcnphy_a1(pi, 2, 3, 2);
3828 wlc_lcnphy_a1(pi, 0, 5, 8);
3829 wlc_lcnphy_a1(pi, 2, 2, 1);
3830 wlc_lcnphy_a1(pi, 0, 4, 3);
3831
3832 iqcc0 = wlc_lcnphy_get_cc(pi, 0);
3833 locc2 = wlc_lcnphy_get_cc(pi, 2);
3834 locc3 = wlc_lcnphy_get_cc(pi, 3);
3835 locc4 = wlc_lcnphy_get_cc(pi, 4);
3836}
3837
3838u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi)
3839{
3840 struct phytbl_info tab;
3841 u16 didq;
3842
3843 tab.tbl_id = 0;
3844 tab.tbl_width = 16;
3845 tab.tbl_ptr = &didq;
3846 tab.tbl_len = 1;
3847 tab.tbl_offset = 85;
3848 wlc_lcnphy_read_table(pi, &tab);
3849
3850 return didq;
3851}
3852
3853static void wlc_lcnphy_txpwrtbl_iqlo_cal(struct brcms_phy *pi)
3854{
3855
3856 struct lcnphy_txgains target_gains, old_gains;
3857 u8 save_bb_mult;
3858 u16 a, b, didq, save_pa_gain = 0;
3859 uint idx, SAVE_txpwrindex = 0xFF;
3860 u32 val;
3861 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
3862 struct phytbl_info tab;
3863 u8 ei0, eq0, fi0, fq0;
3864 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3865
3866 wlc_lcnphy_get_tx_gain(pi, &old_gains);
3867 save_pa_gain = wlc_lcnphy_get_pa_gain(pi);
3868
3869 save_bb_mult = wlc_lcnphy_get_bbmult(pi);
3870
3871 if (SAVE_txpwrctrl == LCNPHY_TX_PWR_CTRL_OFF)
3872 SAVE_txpwrindex = wlc_lcnphy_get_current_tx_pwr_idx(pi);
3873
3874 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
3875
3876 target_gains.gm_gain = 7;
3877 target_gains.pga_gain = 0;
3878 target_gains.pad_gain = 21;
3879 target_gains.dac_gain = 0;
3880 wlc_lcnphy_set_tx_gain(pi, &target_gains);
3881 wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
3882
3883 if (LCNREV_IS(pi->pubpi.phy_rev, 1) || pi_lcn->lcnphy_hw_iqcal_en) {
3884
3885 wlc_lcnphy_set_tx_pwr_by_index(pi, 30);
3886
3887 wlc_lcnphy_tx_iqlo_cal(pi, &target_gains,
3888 (pi_lcn->
3889 lcnphy_recal ? LCNPHY_CAL_RECAL :
3890 LCNPHY_CAL_FULL), false);
3891 } else {
3892 wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
3893 }
3894
3895 wlc_lcnphy_get_radio_loft(pi, &ei0, &eq0, &fi0, &fq0);
3896 if ((abs((s8) fi0) == 15) && (abs((s8) fq0) == 15)) {
3897 if (CHSPEC_IS5G(pi->radio_chanspec)) {
3898 target_gains.gm_gain = 255;
3899 target_gains.pga_gain = 255;
3900 target_gains.pad_gain = 0xf0;
3901 target_gains.dac_gain = 0;
3902 } else {
3903 target_gains.gm_gain = 7;
3904 target_gains.pga_gain = 45;
3905 target_gains.pad_gain = 186;
3906 target_gains.dac_gain = 0;
3907 }
3908
3909 if (LCNREV_IS(pi->pubpi.phy_rev, 1)
3910 || pi_lcn->lcnphy_hw_iqcal_en) {
3911
3912 target_gains.pga_gain = 0;
3913 target_gains.pad_gain = 30;
3914 wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
3915 wlc_lcnphy_tx_iqlo_cal(pi, &target_gains,
3916 LCNPHY_CAL_FULL, false);
3917 } else {
3918 wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
3919 }
3920 }
3921
3922 wlc_lcnphy_get_tx_iqcc(pi, &a, &b);
3923
3924 didq = wlc_lcnphy_get_tx_locc(pi);
3925
3926 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
3927 tab.tbl_width = 32;
3928 tab.tbl_ptr = &val;
3929
3930 tab.tbl_len = 1;
3931 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
3932
3933 for (idx = 0; idx < 128; idx++) {
3934 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + idx;
3935
3936 wlc_lcnphy_read_table(pi, &tab);
3937 val = (val & 0xfff00000) |
3938 ((u32) (a & 0x3FF) << 10) | (b & 0x3ff);
3939 wlc_lcnphy_write_table(pi, &tab);
3940
3941 val = didq;
3942 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + idx;
3943 wlc_lcnphy_write_table(pi, &tab);
3944 }
3945
3946 pi_lcn->lcnphy_cal_results.txiqlocal_a = a;
3947 pi_lcn->lcnphy_cal_results.txiqlocal_b = b;
3948 pi_lcn->lcnphy_cal_results.txiqlocal_didq = didq;
3949 pi_lcn->lcnphy_cal_results.txiqlocal_ei0 = ei0;
3950 pi_lcn->lcnphy_cal_results.txiqlocal_eq0 = eq0;
3951 pi_lcn->lcnphy_cal_results.txiqlocal_fi0 = fi0;
3952 pi_lcn->lcnphy_cal_results.txiqlocal_fq0 = fq0;
3953
3954 wlc_lcnphy_set_bbmult(pi, save_bb_mult);
3955 wlc_lcnphy_set_pa_gain(pi, save_pa_gain);
3956 wlc_lcnphy_set_tx_gain(pi, &old_gains);
3957
3958 if (SAVE_txpwrctrl != LCNPHY_TX_PWR_CTRL_OFF)
3959 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
3960 else
3961 wlc_lcnphy_set_tx_pwr_by_index(pi, SAVE_txpwrindex);
3962}
3963
3964s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode)
3965{
3966 u16 tempsenseval1, tempsenseval2;
3967 s16 avg = 0;
3968 bool suspend = 0;
3969
3970 if (mode == 1) {
3971 suspend =
3972 (0 ==
3973 (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
3974 if (!suspend)
3975 wlapi_suspend_mac_and_wait(pi->sh->physhim);
3976 wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
3977 }
3978 tempsenseval1 = read_phy_reg(pi, 0x476) & 0x1FF;
3979 tempsenseval2 = read_phy_reg(pi, 0x477) & 0x1FF;
3980
3981 if (tempsenseval1 > 255)
3982 avg = (s16) (tempsenseval1 - 512);
3983 else
3984 avg = (s16) tempsenseval1;
3985
3986 if (tempsenseval2 > 255)
3987 avg += (s16) (tempsenseval2 - 512);
3988 else
3989 avg += (s16) tempsenseval2;
3990
3991 avg /= 2;
3992
3993 if (mode == 1) {
3994
3995 mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
3996
3997 udelay(100);
3998 mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
3999
4000 if (!suspend)
4001 wlapi_enable_mac(pi->sh->physhim);
4002 }
4003 return avg;
4004}
4005
4006u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode)
4007{
4008 u16 tempsenseval1, tempsenseval2;
4009 s32 avg = 0;
4010 bool suspend = 0;
4011 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
4012 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4013
4014 if (mode == 1) {
4015 suspend =
4016 (0 ==
4017 (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
4018 if (!suspend)
4019 wlapi_suspend_mac_and_wait(pi->sh->physhim);
4020 wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
4021 }
4022 tempsenseval1 = read_phy_reg(pi, 0x476) & 0x1FF;
4023 tempsenseval2 = read_phy_reg(pi, 0x477) & 0x1FF;
4024
4025 if (tempsenseval1 > 255)
4026 avg = (int)(tempsenseval1 - 512);
4027 else
4028 avg = (int)tempsenseval1;
4029
4030 if (pi_lcn->lcnphy_tempsense_option == 1 || pi->hwpwrctrl_capable) {
4031 if (tempsenseval2 > 255)
4032 avg = (int)(avg - tempsenseval2 + 512);
4033 else
4034 avg = (int)(avg - tempsenseval2);
4035 } else {
4036 if (tempsenseval2 > 255)
4037 avg = (int)(avg + tempsenseval2 - 512);
4038 else
4039 avg = (int)(avg + tempsenseval2);
4040 avg = avg / 2;
4041 }
4042 if (avg < 0)
4043 avg = avg + 512;
4044
4045 if (pi_lcn->lcnphy_tempsense_option == 2)
4046 avg = tempsenseval1;
4047
4048 if (mode)
4049 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
4050
4051 if (mode == 1) {
4052
4053 mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
4054
4055 udelay(100);
4056 mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
4057
4058 if (!suspend)
4059 wlapi_enable_mac(pi->sh->physhim);
4060 }
4061 return (u16) avg;
4062}
4063
4064s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode)
4065{
4066 s32 degree = wlc_lcnphy_tempsense_new(pi, mode);
4067 degree =
4068 ((degree <<
4069 10) + LCN_TEMPSENSE_OFFSET + (LCN_TEMPSENSE_DEN >> 1))
4070 / LCN_TEMPSENSE_DEN;
4071 return (s8) degree;
4072}
4073
4074s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode)
4075{
4076 u16 vbatsenseval;
4077 s32 avg = 0;
4078 bool suspend = 0;
4079
4080 if (mode == 1) {
4081 suspend =
4082 (0 ==
4083 (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
4084 if (!suspend)
4085 wlapi_suspend_mac_and_wait(pi->sh->physhim);
4086 wlc_lcnphy_vbat_temp_sense_setup(pi, VBATSENSE);
4087 }
4088
4089 vbatsenseval = read_phy_reg(pi, 0x475) & 0x1FF;
4090
4091 if (vbatsenseval > 255)
4092 avg = (s32) (vbatsenseval - 512);
4093 else
4094 avg = (s32) vbatsenseval;
4095
4096 avg = (avg * LCN_VBAT_SCALE_NOM +
4097 (LCN_VBAT_SCALE_DEN >> 1)) / LCN_VBAT_SCALE_DEN;
4098
4099 if (mode == 1) {
4100 if (!suspend)
4101 wlapi_enable_mac(pi->sh->physhim);
4102 }
4103 return (s8) avg;
4104}
4105
4106static void wlc_lcnphy_afe_clk_init(struct brcms_phy *pi, u8 mode)
4107{
4108 u8 phybw40;
4109 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
4110
4111 mod_phy_reg(pi, 0x6d1, (0x1 << 7), (1) << 7);
4112
4113 if (((mode == AFE_CLK_INIT_MODE_PAPD) && (phybw40 == 0)) ||
4114 (mode == AFE_CLK_INIT_MODE_TXRX2X))
4115 write_phy_reg(pi, 0x6d0, 0x7);
4116
4117 wlc_lcnphy_toggle_afe_pwdn(pi);
4118}
4119
4120static void wlc_lcnphy_temp_adj(struct brcms_phy *pi)
4121{
4122}
4123
4124static void wlc_lcnphy_glacial_timer_based_cal(struct brcms_phy *pi)
4125{
4126 bool suspend;
4127 s8 index;
4128 u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
4129 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4130 suspend =
4131 (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
4132 if (!suspend)
4133 wlapi_suspend_mac_and_wait(pi->sh->physhim);
4134 wlc_lcnphy_deaf_mode(pi, true);
4135 pi->phy_lastcal = pi->sh->now;
4136 pi->phy_forcecal = false;
4137 index = pi_lcn->lcnphy_current_index;
4138
4139 wlc_lcnphy_txpwrtbl_iqlo_cal(pi);
4140
4141 wlc_lcnphy_set_tx_pwr_by_index(pi, index);
4142 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_pwrctrl);
4143 wlc_lcnphy_deaf_mode(pi, false);
4144 if (!suspend)
4145 wlapi_enable_mac(pi->sh->physhim);
4146
4147}
4148
4149static void wlc_lcnphy_periodic_cal(struct brcms_phy *pi)
4150{
4151 bool suspend, full_cal;
4152 const struct lcnphy_rx_iqcomp *rx_iqcomp;
4153 int rx_iqcomp_sz;
4154 u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
4155 s8 index;
4156 struct phytbl_info tab;
4157 s32 a1, b0, b1;
4158 s32 tssi, pwr, maxtargetpwr, mintargetpwr;
4159 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4160
4161 pi->phy_lastcal = pi->sh->now;
4162 pi->phy_forcecal = false;
4163 full_cal =
4164 (pi_lcn->lcnphy_full_cal_channel !=
4165 CHSPEC_CHANNEL(pi->radio_chanspec));
4166 pi_lcn->lcnphy_full_cal_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
4167 index = pi_lcn->lcnphy_current_index;
4168
4169 suspend =
4170 (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
4171 if (!suspend) {
4172 wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
4173 wlapi_suspend_mac_and_wait(pi->sh->physhim);
4174 }
4175
4176 wlc_lcnphy_deaf_mode(pi, true);
4177
4178 wlc_lcnphy_txpwrtbl_iqlo_cal(pi);
4179
4180 rx_iqcomp = lcnphy_rx_iqcomp_table_rev0;
4181 rx_iqcomp_sz = ARRAY_SIZE(lcnphy_rx_iqcomp_table_rev0);
4182
4183 if (LCNREV_IS(pi->pubpi.phy_rev, 1))
4184 wlc_lcnphy_rx_iq_cal(pi, NULL, 0, true, false, 1, 40);
4185 else
4186 wlc_lcnphy_rx_iq_cal(pi, NULL, 0, true, false, 1, 127);
4187
4188 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) {
4189
4190 wlc_lcnphy_idle_tssi_est((struct brcms_phy_pub *) pi);
4191
4192 b0 = pi->txpa_2g[0];
4193 b1 = pi->txpa_2g[1];
4194 a1 = pi->txpa_2g[2];
4195 maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1);
4196 mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1);
4197
4198 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
4199 tab.tbl_width = 32;
4200 tab.tbl_ptr = &pwr;
4201 tab.tbl_len = 1;
4202 tab.tbl_offset = 0;
4203 for (tssi = 0; tssi < 128; tssi++) {
4204 pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1);
4205 pwr = (pwr < mintargetpwr) ? mintargetpwr : pwr;
4206 wlc_lcnphy_write_table(pi, &tab);
4207 tab.tbl_offset++;
4208 }
4209 }
4210
4211 wlc_lcnphy_set_tx_pwr_by_index(pi, index);
4212 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_pwrctrl);
4213 wlc_lcnphy_deaf_mode(pi, false);
4214 if (!suspend)
4215 wlapi_enable_mac(pi->sh->physhim);
4216}
4217
4218void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode)
4219{
4220 u16 temp_new;
4221 int temp1, temp2, temp_diff;
4222 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4223
4224 switch (mode) {
4225 case PHY_PERICAL_CHAN:
4226 break;
4227 case PHY_FULLCAL:
4228 wlc_lcnphy_periodic_cal(pi);
4229 break;
4230 case PHY_PERICAL_PHYINIT:
4231 wlc_lcnphy_periodic_cal(pi);
4232 break;
4233 case PHY_PERICAL_WATCHDOG:
4234 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
4235 temp_new = wlc_lcnphy_tempsense(pi, 0);
4236 temp1 = LCNPHY_TEMPSENSE(temp_new);
4237 temp2 = LCNPHY_TEMPSENSE(pi_lcn->lcnphy_cal_temper);
4238 temp_diff = temp1 - temp2;
4239 if ((pi_lcn->lcnphy_cal_counter > 90) ||
4240 (temp_diff > 60) || (temp_diff < -60)) {
4241 wlc_lcnphy_glacial_timer_based_cal(pi);
4242 wlc_2064_vco_cal(pi);
4243 pi_lcn->lcnphy_cal_temper = temp_new;
4244 pi_lcn->lcnphy_cal_counter = 0;
4245 } else
4246 pi_lcn->lcnphy_cal_counter++;
4247 }
4248 break;
4249 case LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL:
4250 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
4251 wlc_lcnphy_tx_power_adjustment(
4252 (struct brcms_phy_pub *) pi);
4253 break;
4254 }
4255}
4256
4257void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr, s8 *cck_pwr)
4258{
4259 s8 cck_offset;
4260 u16 status;
4261 status = (read_phy_reg(pi, 0x4ab));
4262 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) &&
4263 (status & (0x1 << 15))) {
4264 *ofdm_pwr = (s8) (((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
4265 >> 0) >> 1);
4266
4267 if (wlc_phy_tpc_isenabled_lcnphy(pi))
4268 cck_offset = pi->tx_power_offset[TXP_FIRST_CCK];
4269 else
4270 cck_offset = 0;
4271
4272 *cck_pwr = *ofdm_pwr + cck_offset;
4273 } else {
4274 *cck_pwr = 0;
4275 *ofdm_pwr = 0;
4276 }
4277}
4278
4279void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi)
4280{
4281 return;
4282
4283}
4284
4285void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi)
4286{
4287 s8 index;
4288 u16 index2;
4289 struct brcms_phy *pi = (struct brcms_phy *) ppi;
4290 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4291 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
4292 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) &&
4293 SAVE_txpwrctrl) {
4294 index = wlc_lcnphy_tempcompensated_txpwrctrl(pi);
4295 index2 = (u16) (index * 2);
4296 mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0);
4297
4298 pi_lcn->lcnphy_current_index =
4299 (s8)((read_phy_reg(pi, 0x4a9) & 0xFF) / 2);
4300 }
4301}
4302
4303static void
4304wlc_lcnphy_load_tx_gain_table(struct brcms_phy *pi,
4305 const struct lcnphy_tx_gain_tbl_entry *gain_table)
4306{
4307 u32 j;
4308 struct phytbl_info tab;
4309 u32 val;
4310 u16 pa_gain;
4311 u16 gm_gain;
4312
4313 if (CHSPEC_IS5G(pi->radio_chanspec))
4314 pa_gain = 0x70;
4315 else
4316 pa_gain = 0x70;
4317
4318 if (pi->sh->boardflags & BFL_FEM)
4319 pa_gain = 0x10;
4320 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
4321 tab.tbl_width = 32;
4322 tab.tbl_len = 1;
4323 tab.tbl_ptr = &val;
4324
4325 for (j = 0; j < 128; j++) {
4326 gm_gain = gain_table[j].gm;
4327 val = (((u32) pa_gain << 24) |
4328 (gain_table[j].pad << 16) |
4329 (gain_table[j].pga << 8) | gm_gain);
4330
4331 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + j;
4332 wlc_lcnphy_write_table(pi, &tab);
4333
4334 val = (gain_table[j].dac << 28) | (gain_table[j].bb_mult << 20);
4335 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + j;
4336 wlc_lcnphy_write_table(pi, &tab);
4337 }
4338}
4339
4340static void wlc_lcnphy_load_rfpower(struct brcms_phy *pi)
4341{
4342 struct phytbl_info tab;
4343 u32 val, bbmult, rfgain;
4344 u8 index;
4345 u8 scale_factor = 1;
4346 s16 temp, temp1, temp2, qQ, qQ1, qQ2, shift;
4347
4348 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
4349 tab.tbl_width = 32;
4350 tab.tbl_len = 1;
4351
4352 for (index = 0; index < 128; index++) {
4353 tab.tbl_ptr = &bbmult;
4354 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + index;
4355 wlc_lcnphy_read_table(pi, &tab);
4356 bbmult = bbmult >> 20;
4357
4358 tab.tbl_ptr = &rfgain;
4359 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + index;
4360 wlc_lcnphy_read_table(pi, &tab);
4361
4362 qm_log10((s32) (bbmult), 0, &temp1, &qQ1);
4363 qm_log10((s32) (1 << 6), 0, &temp2, &qQ2);
4364
4365 if (qQ1 < qQ2) {
4366 temp2 = qm_shr16(temp2, qQ2 - qQ1);
4367 qQ = qQ1;
4368 } else {
4369 temp1 = qm_shr16(temp1, qQ1 - qQ2);
4370 qQ = qQ2;
4371 }
4372 temp = qm_sub16(temp1, temp2);
4373
4374 if (qQ >= 4)
4375 shift = qQ - 4;
4376 else
4377 shift = 4 - qQ;
4378
4379 val = (((index << shift) + (5 * temp) +
4380 (1 << (scale_factor + shift - 3))) >> (scale_factor +
4381 shift - 2));
4382
4383 tab.tbl_ptr = &val;
4384 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index;
4385 wlc_lcnphy_write_table(pi, &tab);
4386 }
4387}
4388
4389static void wlc_lcnphy_bu_tweaks(struct brcms_phy *pi)
4390{
4391 or_phy_reg(pi, 0x805, 0x1);
4392
4393 mod_phy_reg(pi, 0x42f, (0x7 << 0), (0x3) << 0);
4394
4395 mod_phy_reg(pi, 0x030, (0x7 << 0), (0x3) << 0);
4396
4397 write_phy_reg(pi, 0x414, 0x1e10);
4398 write_phy_reg(pi, 0x415, 0x0640);
4399
4400 mod_phy_reg(pi, 0x4df, (0xff << 8), -9 << 8);
4401
4402 or_phy_reg(pi, 0x44a, 0x44);
4403 write_phy_reg(pi, 0x44a, 0x80);
4404 mod_phy_reg(pi, 0x434, (0xff << 0), (0xFD) << 0);
4405
4406 mod_phy_reg(pi, 0x420, (0xff << 0), (16) << 0);
4407
4408 if (!(pi->sh->boardrev < 0x1204))
4409 mod_radio_reg(pi, RADIO_2064_REG09B, 0xF0, 0xF0);
4410
4411 write_phy_reg(pi, 0x7d6, 0x0902);
4412 mod_phy_reg(pi, 0x429, (0xf << 0), (0x9) << 0);
4413
4414 mod_phy_reg(pi, 0x429, (0x3f << 4), (0xe) << 4);
4415
4416 if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
4417 mod_phy_reg(pi, 0x423, (0xff << 0), (0x46) << 0);
4418
4419 mod_phy_reg(pi, 0x411, (0xff << 0), (1) << 0);
4420
4421 mod_phy_reg(pi, 0x434, (0xff << 0), (0xFF) << 0);
4422
4423 mod_phy_reg(pi, 0x656, (0xf << 0), (2) << 0);
4424
4425 mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
4426
4427 mod_radio_reg(pi, RADIO_2064_REG0F7, 0x4, 0x4);
4428 mod_radio_reg(pi, RADIO_2064_REG0F1, 0x3, 0);
4429 mod_radio_reg(pi, RADIO_2064_REG0F2, 0xF8, 0x90);
4430 mod_radio_reg(pi, RADIO_2064_REG0F3, 0x3, 0x2);
4431 mod_radio_reg(pi, RADIO_2064_REG0F3, 0xf0, 0xa0);
4432
4433 mod_radio_reg(pi, RADIO_2064_REG11F, 0x2, 0x2);
4434
4435 wlc_lcnphy_clear_tx_power_offsets(pi);
4436 mod_phy_reg(pi, 0x4d0, (0x1ff << 6), (10) << 6);
4437
4438 }
4439}
4440
4441static void wlc_lcnphy_rcal(struct brcms_phy *pi)
4442{
4443 u8 rcal_value;
4444
4445 and_radio_reg(pi, RADIO_2064_REG05B, 0xfD);
4446
4447 or_radio_reg(pi, RADIO_2064_REG004, 0x40);
4448 or_radio_reg(pi, RADIO_2064_REG120, 0x10);
4449
4450 or_radio_reg(pi, RADIO_2064_REG078, 0x80);
4451 or_radio_reg(pi, RADIO_2064_REG129, 0x02);
4452
4453 or_radio_reg(pi, RADIO_2064_REG057, 0x01);
4454
4455 or_radio_reg(pi, RADIO_2064_REG05B, 0x02);
4456 mdelay(5);
4457 SPINWAIT(!wlc_radio_2064_rcal_done(pi), 10 * 1000 * 1000);
4458
4459 if (wlc_radio_2064_rcal_done(pi)) {
4460 rcal_value = (u8) read_radio_reg(pi, RADIO_2064_REG05C);
4461 rcal_value = rcal_value & 0x1f;
4462 }
4463
4464 and_radio_reg(pi, RADIO_2064_REG05B, 0xfD);
4465
4466 and_radio_reg(pi, RADIO_2064_REG057, 0xFE);
4467}
4468
4469static void wlc_lcnphy_rc_cal(struct brcms_phy *pi)
4470{
4471 u8 dflt_rc_cal_val;
4472 u16 flt_val;
4473
4474 dflt_rc_cal_val = 7;
4475 if (LCNREV_IS(pi->pubpi.phy_rev, 1))
4476 dflt_rc_cal_val = 11;
4477 flt_val =
4478 (dflt_rc_cal_val << 10) | (dflt_rc_cal_val << 5) |
4479 (dflt_rc_cal_val);
4480 write_phy_reg(pi, 0x933, flt_val);
4481 write_phy_reg(pi, 0x934, flt_val);
4482 write_phy_reg(pi, 0x935, flt_val);
4483 write_phy_reg(pi, 0x936, flt_val);
4484 write_phy_reg(pi, 0x937, (flt_val & 0x1FF));
4485
4486 return;
4487}
4488
4489static void wlc_radio_2064_init(struct brcms_phy *pi)
4490{
4491 u32 i;
4492 const struct lcnphy_radio_regs *lcnphyregs = NULL;
4493
4494 lcnphyregs = lcnphy_radio_regs_2064;
4495
4496 for (i = 0; lcnphyregs[i].address != 0xffff; i++)
4497 if (CHSPEC_IS5G(pi->radio_chanspec) && lcnphyregs[i].do_init_a)
4498 write_radio_reg(pi,
4499 ((lcnphyregs[i].address & 0x3fff) |
4500 RADIO_DEFAULT_CORE),
4501 (u16) lcnphyregs[i].init_a);
4502 else if (lcnphyregs[i].do_init_g)
4503 write_radio_reg(pi,
4504 ((lcnphyregs[i].address & 0x3fff) |
4505 RADIO_DEFAULT_CORE),
4506 (u16) lcnphyregs[i].init_g);
4507
4508 write_radio_reg(pi, RADIO_2064_REG032, 0x62);
4509 write_radio_reg(pi, RADIO_2064_REG033, 0x19);
4510
4511 write_radio_reg(pi, RADIO_2064_REG090, 0x10);
4512
4513 write_radio_reg(pi, RADIO_2064_REG010, 0x00);
4514
4515 if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
4516
4517 write_radio_reg(pi, RADIO_2064_REG060, 0x7f);
4518 write_radio_reg(pi, RADIO_2064_REG061, 0x72);
4519 write_radio_reg(pi, RADIO_2064_REG062, 0x7f);
4520 }
4521
4522 write_radio_reg(pi, RADIO_2064_REG01D, 0x02);
4523 write_radio_reg(pi, RADIO_2064_REG01E, 0x06);
4524
4525 mod_phy_reg(pi, 0x4ea, (0x7 << 0), 0 << 0);
4526
4527 mod_phy_reg(pi, 0x4ea, (0x7 << 3), 1 << 3);
4528
4529 mod_phy_reg(pi, 0x4ea, (0x7 << 6), 2 << 6);
4530
4531 mod_phy_reg(pi, 0x4ea, (0x7 << 9), 3 << 9);
4532
4533 mod_phy_reg(pi, 0x4ea, (0x7 << 12), 4 << 12);
4534
4535 write_phy_reg(pi, 0x4ea, 0x4688);
4536
4537 mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
4538
4539 mod_phy_reg(pi, 0x4eb, (0x7 << 6), 0 << 6);
4540
4541 mod_phy_reg(pi, 0x46a, (0xffff << 0), 25 << 0);
4542
4543 wlc_lcnphy_set_tx_locc(pi, 0);
4544
4545 wlc_lcnphy_rcal(pi);
4546
4547 wlc_lcnphy_rc_cal(pi);
4548}
4549
4550static void wlc_lcnphy_radio_init(struct brcms_phy *pi)
4551{
4552 wlc_radio_2064_init(pi);
4553}
4554
4555static void wlc_lcnphy_tbl_init(struct brcms_phy *pi)
4556{
4557 uint idx;
4558 u8 phybw40;
4559 struct phytbl_info tab;
4560 u32 val;
4561
4562 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
4563
4564 for (idx = 0; idx < dot11lcnphytbl_info_sz_rev0; idx++)
4565 wlc_lcnphy_write_table(pi, &dot11lcnphytbl_info_rev0[idx]);
4566
4567 if (pi->sh->boardflags & BFL_FEM_BT) {
4568 tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
4569 tab.tbl_width = 16;
4570 tab.tbl_ptr = &val;
4571 tab.tbl_len = 1;
4572 val = 100;
4573 tab.tbl_offset = 4;
4574 wlc_lcnphy_write_table(pi, &tab);
4575 }
4576
4577 tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
4578 tab.tbl_width = 16;
4579 tab.tbl_ptr = &val;
4580 tab.tbl_len = 1;
4581
4582 val = 114;
4583 tab.tbl_offset = 0;
4584 wlc_lcnphy_write_table(pi, &tab);
4585
4586 val = 130;
4587 tab.tbl_offset = 1;
4588 wlc_lcnphy_write_table(pi, &tab);
4589
4590 val = 6;
4591 tab.tbl_offset = 8;
4592 wlc_lcnphy_write_table(pi, &tab);
4593
4594 if (CHSPEC_IS2G(pi->radio_chanspec)) {
4595 if (pi->sh->boardflags & BFL_FEM)
4596 wlc_lcnphy_load_tx_gain_table(
4597 pi,
4598 dot11lcnphy_2GHz_extPA_gaintable_rev0);
4599 else
4600 wlc_lcnphy_load_tx_gain_table(
4601 pi,
4602 dot11lcnphy_2GHz_gaintable_rev0);
4603 }
4604
4605 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
4606 const struct phytbl_info *tb;
4607 int l;
4608
4609 if (CHSPEC_IS2G(pi->radio_chanspec)) {
4610 l = dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
4611 if (pi->sh->boardflags & BFL_EXTLNA)
4612 tb = dot11lcnphytbl_rx_gain_info_extlna_2G_rev2;
4613 else
4614 tb = dot11lcnphytbl_rx_gain_info_2G_rev2;
4615 } else {
4616 l = dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
4617 if (pi->sh->boardflags & BFL_EXTLNA_5GHz)
4618 tb = dot11lcnphytbl_rx_gain_info_extlna_5G_rev2;
4619 else
4620 tb = dot11lcnphytbl_rx_gain_info_5G_rev2;
4621 }
4622
4623 for (idx = 0; idx < l; idx++)
4624 wlc_lcnphy_write_table(pi, &tb[idx]);
4625 }
4626
4627 if ((pi->sh->boardflags & BFL_FEM)
4628 && !(pi->sh->boardflags & BFL_FEM_BT))
4629 wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313_epa);
4630 else if (pi->sh->boardflags & BFL_FEM_BT) {
4631 if (pi->sh->boardrev < 0x1250)
4632 wlc_lcnphy_write_table(
4633 pi,
4634 &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa);
4635 else
4636 wlc_lcnphy_write_table(
4637 pi,
4638 &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250);
4639 } else
4640 wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313);
4641
4642 wlc_lcnphy_load_rfpower(pi);
4643
4644 wlc_lcnphy_clear_papd_comptable(pi);
4645}
4646
4647static void wlc_lcnphy_rev0_baseband_init(struct brcms_phy *pi)
4648{
4649 u16 afectrl1;
4650 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4651
4652 write_radio_reg(pi, RADIO_2064_REG11C, 0x0);
4653
4654 write_phy_reg(pi, 0x43b, 0x0);
4655 write_phy_reg(pi, 0x43c, 0x0);
4656 write_phy_reg(pi, 0x44c, 0x0);
4657 write_phy_reg(pi, 0x4e6, 0x0);
4658 write_phy_reg(pi, 0x4f9, 0x0);
4659 write_phy_reg(pi, 0x4b0, 0x0);
4660 write_phy_reg(pi, 0x938, 0x0);
4661 write_phy_reg(pi, 0x4b0, 0x0);
4662 write_phy_reg(pi, 0x44e, 0);
4663
4664 or_phy_reg(pi, 0x567, 0x03);
4665
4666 or_phy_reg(pi, 0x44a, 0x44);
4667 write_phy_reg(pi, 0x44a, 0x80);
4668
4669 if (!(pi->sh->boardflags & BFL_FEM))
4670 wlc_lcnphy_set_tx_pwr_by_index(pi, 52);
4671
4672 if (0) {
4673 afectrl1 = 0;
4674 afectrl1 = (u16) ((pi_lcn->lcnphy_rssi_vf) |
4675 (pi_lcn->lcnphy_rssi_vc << 4) |
4676 (pi_lcn->lcnphy_rssi_gs << 10));
4677 write_phy_reg(pi, 0x43e, afectrl1);
4678 }
4679
4680 mod_phy_reg(pi, 0x634, (0xff << 0), 0xC << 0);
4681 if (pi->sh->boardflags & BFL_FEM) {
4682 mod_phy_reg(pi, 0x634, (0xff << 0), 0xA << 0);
4683
4684 write_phy_reg(pi, 0x910, 0x1);
4685 }
4686
4687 mod_phy_reg(pi, 0x448, (0x3 << 8), 1 << 8);
4688 mod_phy_reg(pi, 0x608, (0xff << 0), 0x17 << 0);
4689 mod_phy_reg(pi, 0x604, (0x7ff << 0), 0x3EA << 0);
4690
4691}
4692
4693static void wlc_lcnphy_rev2_baseband_init(struct brcms_phy *pi)
4694{
4695 if (CHSPEC_IS5G(pi->radio_chanspec)) {
4696 mod_phy_reg(pi, 0x416, (0xff << 0), 80 << 0);
4697 mod_phy_reg(pi, 0x416, (0xff << 8), 80 << 8);
4698 }
4699}
4700
4701static void wlc_lcnphy_agc_temp_init(struct brcms_phy *pi)
4702{
4703 s16 temp;
4704 struct phytbl_info tab;
4705 u32 tableBuffer[2];
4706 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4707
4708 temp = (s16) read_phy_reg(pi, 0x4df);
4709 pi_lcn->lcnphy_ofdmgainidxtableoffset = (temp & (0xff << 0)) >> 0;
4710
4711 if (pi_lcn->lcnphy_ofdmgainidxtableoffset > 127)
4712 pi_lcn->lcnphy_ofdmgainidxtableoffset -= 256;
4713
4714 pi_lcn->lcnphy_dsssgainidxtableoffset = (temp & (0xff << 8)) >> 8;
4715
4716 if (pi_lcn->lcnphy_dsssgainidxtableoffset > 127)
4717 pi_lcn->lcnphy_dsssgainidxtableoffset -= 256;
4718
4719 tab.tbl_ptr = tableBuffer;
4720 tab.tbl_len = 2;
4721 tab.tbl_id = 17;
4722 tab.tbl_offset = 59;
4723 tab.tbl_width = 32;
4724 wlc_lcnphy_read_table(pi, &tab);
4725
4726 if (tableBuffer[0] > 63)
4727 tableBuffer[0] -= 128;
4728 pi_lcn->lcnphy_tr_R_gain_val = tableBuffer[0];
4729
4730 if (tableBuffer[1] > 63)
4731 tableBuffer[1] -= 128;
4732 pi_lcn->lcnphy_tr_T_gain_val = tableBuffer[1];
4733
4734 temp = (s16) (read_phy_reg(pi, 0x434) & (0xff << 0));
4735 if (temp > 127)
4736 temp -= 256;
4737 pi_lcn->lcnphy_input_pwr_offset_db = (s8) temp;
4738
4739 pi_lcn->lcnphy_Med_Low_Gain_db =
4740 (read_phy_reg(pi, 0x424) & (0xff << 8)) >> 8;
4741 pi_lcn->lcnphy_Very_Low_Gain_db =
4742 (read_phy_reg(pi, 0x425) & (0xff << 0)) >> 0;
4743
4744 tab.tbl_ptr = tableBuffer;
4745 tab.tbl_len = 2;
4746 tab.tbl_id = LCNPHY_TBL_ID_GAIN_IDX;
4747 tab.tbl_offset = 28;
4748 tab.tbl_width = 32;
4749 wlc_lcnphy_read_table(pi, &tab);
4750
4751 pi_lcn->lcnphy_gain_idx_14_lowword = tableBuffer[0];
4752 pi_lcn->lcnphy_gain_idx_14_hiword = tableBuffer[1];
4753
4754}
4755
4756static void wlc_lcnphy_baseband_init(struct brcms_phy *pi)
4757{
4758
4759 wlc_lcnphy_tbl_init(pi);
4760 wlc_lcnphy_rev0_baseband_init(pi);
4761 if (LCNREV_IS(pi->pubpi.phy_rev, 2))
4762 wlc_lcnphy_rev2_baseband_init(pi);
4763 wlc_lcnphy_bu_tweaks(pi);
4764}
4765
4766void wlc_phy_init_lcnphy(struct brcms_phy *pi)
4767{
4768 u8 phybw40;
4769 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4770 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
4771
4772 pi_lcn->lcnphy_cal_counter = 0;
4773 pi_lcn->lcnphy_cal_temper = pi_lcn->lcnphy_rawtempsense;
4774
4775 or_phy_reg(pi, 0x44a, 0x80);
4776 and_phy_reg(pi, 0x44a, 0x7f);
4777
4778 wlc_lcnphy_afe_clk_init(pi, AFE_CLK_INIT_MODE_TXRX2X);
4779
4780 write_phy_reg(pi, 0x60a, 160);
4781
4782 write_phy_reg(pi, 0x46a, 25);
4783
4784 wlc_lcnphy_baseband_init(pi);
4785
4786 wlc_lcnphy_radio_init(pi);
4787
4788 if (CHSPEC_IS2G(pi->radio_chanspec))
4789 wlc_lcnphy_tx_pwr_ctrl_init((struct brcms_phy_pub *) pi);
4790
4791 wlc_phy_chanspec_set((struct brcms_phy_pub *) pi, pi->radio_chanspec);
4792
4793 si_pmu_regcontrol(pi->sh->sih, 0, 0xf, 0x9);
4794
4795 si_pmu_chipcontrol(pi->sh->sih, 0, 0xffffffff, 0x03CDDDDD);
4796
4797 if ((pi->sh->boardflags & BFL_FEM)
4798 && wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
4799 wlc_lcnphy_set_tx_pwr_by_index(pi, FIXED_TXPWR);
4800
4801 wlc_lcnphy_agc_temp_init(pi);
4802
4803 wlc_lcnphy_temp_adj(pi);
4804
4805 mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
4806
4807 udelay(100);
4808 mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
4809
4810 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_HW);
4811 pi_lcn->lcnphy_noise_samples = LCNPHY_NOISE_SAMPLES_DEFAULT;
4812 wlc_lcnphy_calib_modes(pi, PHY_PERICAL_PHYINIT);
4813}
4814
4815static bool wlc_phy_txpwr_srom_read_lcnphy(struct brcms_phy *pi)
4816{
4817 s8 txpwr = 0;
4818 int i;
4819 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4820 struct phy_shim_info *shim = pi->sh->physhim;
4821
4822 if (CHSPEC_IS2G(pi->radio_chanspec)) {
4823 u16 cckpo = 0;
4824 u32 offset_ofdm, offset_mcs;
4825
4826 pi_lcn->lcnphy_tr_isolation_mid =
4827 (u8)wlapi_getintvar(shim, BRCMS_SROM_TRISO2G);
4828
4829 pi_lcn->lcnphy_rx_power_offset =
4830 (u8)wlapi_getintvar(shim, BRCMS_SROM_RXPO2G);
4831
4832 pi->txpa_2g[0] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B0);
4833 pi->txpa_2g[1] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B1);
4834 pi->txpa_2g[2] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B2);
4835
4836 pi_lcn->lcnphy_rssi_vf =
4837 (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISMF2G);
4838 pi_lcn->lcnphy_rssi_vc =
4839 (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISMC2G);
4840 pi_lcn->lcnphy_rssi_gs =
4841 (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISAV2G);
4842
4843 pi_lcn->lcnphy_rssi_vf_lowtemp = pi_lcn->lcnphy_rssi_vf;
4844 pi_lcn->lcnphy_rssi_vc_lowtemp = pi_lcn->lcnphy_rssi_vc;
4845 pi_lcn->lcnphy_rssi_gs_lowtemp = pi_lcn->lcnphy_rssi_gs;
4846
4847 pi_lcn->lcnphy_rssi_vf_hightemp = pi_lcn->lcnphy_rssi_vf;
4848 pi_lcn->lcnphy_rssi_vc_hightemp = pi_lcn->lcnphy_rssi_vc;
4849 pi_lcn->lcnphy_rssi_gs_hightemp = pi_lcn->lcnphy_rssi_gs;
4850
4851 txpwr = (s8)wlapi_getintvar(shim, BRCMS_SROM_MAXP2GA0);
4852 pi->tx_srom_max_2g = txpwr;
4853
4854 for (i = 0; i < PWRTBL_NUM_COEFF; i++) {
4855 pi->txpa_2g_low_temp[i] = pi->txpa_2g[i];
4856 pi->txpa_2g_high_temp[i] = pi->txpa_2g[i];
4857 }
4858
4859 cckpo = (u16)wlapi_getintvar(shim, BRCMS_SROM_CCK2GPO);
4860 offset_ofdm = (u32)wlapi_getintvar(shim, BRCMS_SROM_OFDM2GPO);
4861 if (cckpo) {
4862 uint max_pwr_chan = txpwr;
4863
4864 for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++) {
4865 pi->tx_srom_max_rate_2g[i] =
4866 max_pwr_chan - ((cckpo & 0xf) * 2);
4867 cckpo >>= 4;
4868 }
4869
4870 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
4871 pi->tx_srom_max_rate_2g[i] =
4872 max_pwr_chan -
4873 ((offset_ofdm & 0xf) * 2);
4874 offset_ofdm >>= 4;
4875 }
4876 } else {
4877 u8 opo = 0;
4878
4879 opo = (u8)wlapi_getintvar(shim, BRCMS_SROM_OPO);
4880
4881 for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++)
4882 pi->tx_srom_max_rate_2g[i] = txpwr;
4883
4884 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
4885 pi->tx_srom_max_rate_2g[i] = txpwr -
4886 ((offset_ofdm & 0xf) * 2);
4887 offset_ofdm >>= 4;
4888 }
4889 offset_mcs =
4890 wlapi_getintvar(shim,
4891 BRCMS_SROM_MCS2GPO1) << 16;
4892 offset_mcs |=
4893 (u16) wlapi_getintvar(shim,
4894 BRCMS_SROM_MCS2GPO0);
4895 pi_lcn->lcnphy_mcs20_po = offset_mcs;
4896 for (i = TXP_FIRST_SISO_MCS_20;
4897 i <= TXP_LAST_SISO_MCS_20; i++) {
4898 pi->tx_srom_max_rate_2g[i] =
4899 txpwr - ((offset_mcs & 0xf) * 2);
4900 offset_mcs >>= 4;
4901 }
4902 }
4903
4904 pi_lcn->lcnphy_rawtempsense =
4905 (u16)wlapi_getintvar(shim, BRCMS_SROM_RAWTEMPSENSE);
4906 pi_lcn->lcnphy_measPower =
4907 (u8)wlapi_getintvar(shim, BRCMS_SROM_MEASPOWER);
4908 pi_lcn->lcnphy_tempsense_slope =
4909 (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPSENSE_SLOPE);
4910 pi_lcn->lcnphy_hw_iqcal_en =
4911 (bool)wlapi_getintvar(shim, BRCMS_SROM_HW_IQCAL_EN);
4912 pi_lcn->lcnphy_iqcal_swp_dis =
4913 (bool)wlapi_getintvar(shim, BRCMS_SROM_IQCAL_SWP_DIS);
4914 pi_lcn->lcnphy_tempcorrx =
4915 (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPCORRX);
4916 pi_lcn->lcnphy_tempsense_option =
4917 (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPSENSE_OPTION);
4918 pi_lcn->lcnphy_freqoffset_corr =
4919 (u8)wlapi_getintvar(shim, BRCMS_SROM_FREQOFFSET_CORR);
4920 if ((u8)wlapi_getintvar(shim, BRCMS_SROM_AA2G) > 1)
4921 wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi,
4922 (u8) wlapi_getintvar(shim, BRCMS_SROM_AA2G));
4923 }
4924 pi_lcn->lcnphy_cck_dig_filt_type = -1;
4925
4926 return true;
4927}
4928
4929void wlc_2064_vco_cal(struct brcms_phy *pi)
4930{
4931 u8 calnrst;
4932
4933 mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 1 << 3);
4934 calnrst = (u8) read_radio_reg(pi, RADIO_2064_REG056) & 0xf8;
4935 write_radio_reg(pi, RADIO_2064_REG056, calnrst);
4936 udelay(1);
4937 write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x03);
4938 udelay(1);
4939 write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x07);
4940 udelay(300);
4941 mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 0);
4942}
4943
4944bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi)
4945{
4946 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
4947 return 0;
4948 else
4949 return (LCNPHY_TX_PWR_CTRL_HW ==
4950 wlc_lcnphy_get_tx_pwr_ctrl((pi)));
4951}
4952
4953void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi)
4954{
4955 u16 pwr_ctrl;
4956 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
4957 wlc_lcnphy_calib_modes(pi, LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL);
4958 } else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) {
4959 pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
4960 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
4961 wlc_lcnphy_txpower_recalc_target(pi);
4962 wlc_lcnphy_set_tx_pwr_ctrl(pi, pwr_ctrl);
4963 }
4964}
4965
4966void wlc_phy_detach_lcnphy(struct brcms_phy *pi)
4967{
4968 kfree(pi->u.pi_lcnphy);
4969}
4970
4971bool wlc_phy_attach_lcnphy(struct brcms_phy *pi)
4972{
4973 struct brcms_phy_lcnphy *pi_lcn;
4974
4975 pi->u.pi_lcnphy = kzalloc(sizeof(struct brcms_phy_lcnphy), GFP_ATOMIC);
4976 if (pi->u.pi_lcnphy == NULL)
4977 return false;
4978
4979 pi_lcn = pi->u.pi_lcnphy;
4980
4981 if (0 == (pi->sh->boardflags & BFL_NOPA)) {
4982 pi->hwpwrctrl = true;
4983 pi->hwpwrctrl_capable = true;
4984 }
4985
4986 pi->xtalfreq = si_pmu_alp_clock(pi->sh->sih);
4987 pi_lcn->lcnphy_papd_rxGnCtrl_init = 0;
4988
4989 pi->pi_fptr.init = wlc_phy_init_lcnphy;
4990 pi->pi_fptr.calinit = wlc_phy_cal_init_lcnphy;
4991 pi->pi_fptr.chanset = wlc_phy_chanspec_set_lcnphy;
4992 pi->pi_fptr.txpwrrecalc = wlc_phy_txpower_recalc_target_lcnphy;
4993 pi->pi_fptr.txiqccget = wlc_lcnphy_get_tx_iqcc;
4994 pi->pi_fptr.txiqccset = wlc_lcnphy_set_tx_iqcc;
4995 pi->pi_fptr.txloccget = wlc_lcnphy_get_tx_locc;
4996 pi->pi_fptr.radioloftget = wlc_lcnphy_get_radio_loft;
4997 pi->pi_fptr.detach = wlc_phy_detach_lcnphy;
4998
4999 if (!wlc_phy_txpwr_srom_read_lcnphy(pi))
5000 return false;
5001
5002 if ((pi->sh->boardflags & BFL_FEM) &&
5003 (LCNREV_IS(pi->pubpi.phy_rev, 1))) {
5004 if (pi_lcn->lcnphy_tempsense_option == 3) {
5005 pi->hwpwrctrl = true;
5006 pi->hwpwrctrl_capable = true;
5007 pi->temppwrctrl_capable = false;
5008 } else {
5009 pi->hwpwrctrl = false;
5010 pi->hwpwrctrl_capable = false;
5011 pi->temppwrctrl_capable = true;
5012 }
5013 }
5014
5015 return true;
5016}
5017
5018static void wlc_lcnphy_set_rx_gain(struct brcms_phy *pi, u32 gain)
5019{
5020 u16 trsw, ext_lna, lna1, lna2, tia, biq0, biq1, gain0_15, gain16_19;
5021
5022 trsw = (gain & ((u32) 1 << 28)) ? 0 : 1;
5023 ext_lna = (u16) (gain >> 29) & 0x01;
5024 lna1 = (u16) (gain >> 0) & 0x0f;
5025 lna2 = (u16) (gain >> 4) & 0x0f;
5026 tia = (u16) (gain >> 8) & 0xf;
5027 biq0 = (u16) (gain >> 12) & 0xf;
5028 biq1 = (u16) (gain >> 16) & 0xf;
5029
5030 gain0_15 = (u16) ((lna1 & 0x3) | ((lna1 & 0x3) << 2) |
5031 ((lna2 & 0x3) << 4) | ((lna2 & 0x3) << 6) |
5032 ((tia & 0xf) << 8) | ((biq0 & 0xf) << 12));
5033 gain16_19 = biq1;
5034
5035 mod_phy_reg(pi, 0x44d, (0x1 << 0), trsw << 0);
5036 mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
5037 mod_phy_reg(pi, 0x4b1, (0x1 << 10), ext_lna << 10);
5038 mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
5039 mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
5040
5041 if (CHSPEC_IS2G(pi->radio_chanspec)) {
5042 mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
5043 mod_phy_reg(pi, 0x4e6, (0x3 << 3), lna1 << 3);
5044 }
5045 wlc_lcnphy_rx_gain_override_enable(pi, true);
5046}
5047
5048static u32 wlc_lcnphy_get_receive_power(struct brcms_phy *pi, s32 *gain_index)
5049{
5050 u32 received_power = 0;
5051 s32 max_index = 0;
5052 u32 gain_code = 0;
5053 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
5054
5055 max_index = 36;
5056 if (*gain_index >= 0)
5057 gain_code = lcnphy_23bitgaincode_table[*gain_index];
5058
5059 if (-1 == *gain_index) {
5060 *gain_index = 0;
5061 while ((*gain_index <= (s32) max_index)
5062 && (received_power < 700)) {
5063 wlc_lcnphy_set_rx_gain(pi,
5064 lcnphy_23bitgaincode_table
5065 [*gain_index]);
5066 received_power =
5067 wlc_lcnphy_measure_digital_power(
5068 pi,
5069 pi_lcn->
5070 lcnphy_noise_samples);
5071 (*gain_index)++;
5072 }
5073 (*gain_index)--;
5074 } else {
5075 wlc_lcnphy_set_rx_gain(pi, gain_code);
5076 received_power =
5077 wlc_lcnphy_measure_digital_power(pi,
5078 pi_lcn->
5079 lcnphy_noise_samples);
5080 }
5081
5082 return received_power;
5083}
5084
5085s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index)
5086{
5087 s32 gain = 0;
5088 s32 nominal_power_db;
5089 s32 log_val, gain_mismatch, desired_gain, input_power_offset_db,
5090 input_power_db;
5091 s32 received_power, temperature;
5092 u32 power;
5093 u32 msb1, msb2, val1, val2, diff1, diff2;
5094 uint freq;
5095 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
5096
5097 received_power = wlc_lcnphy_get_receive_power(pi, &gain_index);
5098
5099 gain = lcnphy_gain_table[gain_index];
5100
5101 nominal_power_db = read_phy_reg(pi, 0x425) >> 8;
5102
5103 power = (received_power * 16);
5104 msb1 = ffs(power) - 1;
5105 msb2 = msb1 + 1;
5106 val1 = 1 << msb1;
5107 val2 = 1 << msb2;
5108 diff1 = (power - val1);
5109 diff2 = (val2 - power);
5110 if (diff1 < diff2)
5111 log_val = msb1;
5112 else
5113 log_val = msb2;
5114
5115 log_val = log_val * 3;
5116
5117 gain_mismatch = (nominal_power_db / 2) - (log_val);
5118
5119 desired_gain = gain + gain_mismatch;
5120
5121 input_power_offset_db = read_phy_reg(pi, 0x434) & 0xFF;
5122
5123 if (input_power_offset_db > 127)
5124 input_power_offset_db -= 256;
5125
5126 input_power_db = input_power_offset_db - desired_gain;
5127
5128 input_power_db =
5129 input_power_db + lcnphy_gain_index_offset_for_rssi[gain_index];
5130
5131 freq = wlc_phy_channel2freq(CHSPEC_CHANNEL(pi->radio_chanspec));
5132 if ((freq > 2427) && (freq <= 2467))
5133 input_power_db = input_power_db - 1;
5134
5135 temperature = pi_lcn->lcnphy_lastsensed_temperature;
5136
5137 if ((temperature - 15) < -30)
5138 input_power_db =
5139 input_power_db +
5140 (((temperature - 10 - 25) * 286) >> 12) -
5141 7;
5142 else if ((temperature - 15) < 4)
5143 input_power_db =
5144 input_power_db +
5145 (((temperature - 10 - 25) * 286) >> 12) -
5146 3;
5147 else
5148 input_power_db = input_power_db +
5149 (((temperature - 10 - 25) * 286) >> 12);
5150
5151 wlc_lcnphy_rx_gain_override_enable(pi, 0);
5152
5153 return input_power_db;
5154}
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.h b/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.h
deleted file mode 100644
index f4a8ab09da4..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_PHY_LCN_H_
18#define _BRCM_PHY_LCN_H_
19
20#include <types.h>
21
22struct brcms_phy_lcnphy {
23 int lcnphy_txrf_sp_9_override;
24 u8 lcnphy_full_cal_channel;
25 u8 lcnphy_cal_counter;
26 u16 lcnphy_cal_temper;
27 bool lcnphy_recal;
28
29 u8 lcnphy_rc_cap;
30 u32 lcnphy_mcs20_po;
31
32 u8 lcnphy_tr_isolation_mid;
33 u8 lcnphy_tr_isolation_low;
34 u8 lcnphy_tr_isolation_hi;
35
36 u8 lcnphy_bx_arch;
37 u8 lcnphy_rx_power_offset;
38 u8 lcnphy_rssi_vf;
39 u8 lcnphy_rssi_vc;
40 u8 lcnphy_rssi_gs;
41 u8 lcnphy_tssi_val;
42 u8 lcnphy_rssi_vf_lowtemp;
43 u8 lcnphy_rssi_vc_lowtemp;
44 u8 lcnphy_rssi_gs_lowtemp;
45
46 u8 lcnphy_rssi_vf_hightemp;
47 u8 lcnphy_rssi_vc_hightemp;
48 u8 lcnphy_rssi_gs_hightemp;
49
50 s16 lcnphy_pa0b0;
51 s16 lcnphy_pa0b1;
52 s16 lcnphy_pa0b2;
53
54 u16 lcnphy_rawtempsense;
55 u8 lcnphy_measPower;
56 u8 lcnphy_tempsense_slope;
57 u8 lcnphy_freqoffset_corr;
58 u8 lcnphy_tempsense_option;
59 u8 lcnphy_tempcorrx;
60 bool lcnphy_iqcal_swp_dis;
61 bool lcnphy_hw_iqcal_en;
62 uint lcnphy_bandedge_corr;
63 bool lcnphy_spurmod;
64 u16 lcnphy_tssi_tx_cnt;
65 u16 lcnphy_tssi_idx;
66 u16 lcnphy_tssi_npt;
67
68 u16 lcnphy_target_tx_freq;
69 s8 lcnphy_tx_power_idx_override;
70 u16 lcnphy_noise_samples;
71
72 u32 lcnphy_papdRxGnIdx;
73 u32 lcnphy_papd_rxGnCtrl_init;
74
75 u32 lcnphy_gain_idx_14_lowword;
76 u32 lcnphy_gain_idx_14_hiword;
77 u32 lcnphy_gain_idx_27_lowword;
78 u32 lcnphy_gain_idx_27_hiword;
79 s16 lcnphy_ofdmgainidxtableoffset;
80 s16 lcnphy_dsssgainidxtableoffset;
81 u32 lcnphy_tr_R_gain_val;
82 u32 lcnphy_tr_T_gain_val;
83 s8 lcnphy_input_pwr_offset_db;
84 u16 lcnphy_Med_Low_Gain_db;
85 u16 lcnphy_Very_Low_Gain_db;
86 s8 lcnphy_lastsensed_temperature;
87 s8 lcnphy_pkteng_rssi_slope;
88 u8 lcnphy_saved_tx_user_target[TXP_NUM_RATES];
89 u8 lcnphy_volt_winner;
90 u8 lcnphy_volt_low;
91 u8 lcnphy_54_48_36_24mbps_backoff;
92 u8 lcnphy_11n_backoff;
93 u8 lcnphy_lowerofdm;
94 u8 lcnphy_cck;
95 u8 lcnphy_psat_2pt3_detected;
96 s32 lcnphy_lowest_Re_div_Im;
97 s8 lcnphy_final_papd_cal_idx;
98 u16 lcnphy_extstxctrl4;
99 u16 lcnphy_extstxctrl0;
100 u16 lcnphy_extstxctrl1;
101 s16 lcnphy_cck_dig_filt_type;
102 s16 lcnphy_ofdm_dig_filt_type;
103 struct lcnphy_cal_results lcnphy_cal_results;
104
105 u8 lcnphy_psat_pwr;
106 u8 lcnphy_psat_indx;
107 s32 lcnphy_min_phase;
108 u8 lcnphy_final_idx;
109 u8 lcnphy_start_idx;
110 u8 lcnphy_current_index;
111 u16 lcnphy_logen_buf_1;
112 u16 lcnphy_local_ovr_2;
113 u16 lcnphy_local_oval_6;
114 u16 lcnphy_local_oval_5;
115 u16 lcnphy_logen_mixer_1;
116
117 u8 lcnphy_aci_stat;
118 uint lcnphy_aci_start_time;
119 s8 lcnphy_tx_power_offset[TXP_NUM_RATES];
120};
121#endif /* _BRCM_PHY_LCN_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_n.c b/drivers/staging/brcm80211/brcmsmac/phy/phy_n.c
deleted file mode 100644
index cd19c2f7a34..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_n.c
+++ /dev/null
@@ -1,28876 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/kernel.h>
18#include <linux/delay.h>
19#include <linux/cordic.h>
20
21#include <brcm_hw_ids.h>
22#include <aiutils.h>
23#include <chipcommon.h>
24#include <pmu.h>
25#include <d11.h>
26#include <phy_shim.h>
27#include "phy_int.h"
28#include "phy_hal.h"
29#include "phy_radio.h"
30#include "phyreg_n.h"
31#include "phytbl_n.h"
32
33#define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \
34 read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
35 ((core == PHY_CORE_0) ? \
36 radio_type##_##jspace##0 : \
37 radio_type##_##jspace##1))
38
39#define WRITE_RADIO_REG2(pi, radio_type, jspace, core, reg_name, value) \
40 write_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
41 ((core == PHY_CORE_0) ? \
42 radio_type##_##jspace##0 : \
43 radio_type##_##jspace##1), value)
44
45#define WRITE_RADIO_SYN(pi, radio_type, reg_name, value) \
46 write_radio_reg(pi, radio_type##_##SYN##_##reg_name, value)
47
48#define READ_RADIO_REG3(pi, radio_type, jspace, core, reg_name) \
49 read_radio_reg(pi, ((core == PHY_CORE_0) ? \
50 radio_type##_##jspace##0##_##reg_name : \
51 radio_type##_##jspace##1##_##reg_name))
52
53#define WRITE_RADIO_REG3(pi, radio_type, jspace, core, reg_name, value) \
54 write_radio_reg(pi, ((core == PHY_CORE_0) ? \
55 radio_type##_##jspace##0##_##reg_name : \
56 radio_type##_##jspace##1##_##reg_name), \
57 value)
58
59#define READ_RADIO_REG4(pi, radio_type, jspace, core, reg_name) \
60 read_radio_reg(pi, ((core == PHY_CORE_0) ? \
61 radio_type##_##reg_name##_##jspace##0 : \
62 radio_type##_##reg_name##_##jspace##1))
63
64#define WRITE_RADIO_REG4(pi, radio_type, jspace, core, reg_name, value) \
65 write_radio_reg(pi, ((core == PHY_CORE_0) ? \
66 radio_type##_##reg_name##_##jspace##0 : \
67 radio_type##_##reg_name##_##jspace##1), \
68 value)
69
70#define NPHY_ACI_MAX_UNDETECT_WINDOW_SZ 40
71#define NPHY_ACI_CHANNEL_DELTA 5
72#define NPHY_ACI_CHANNEL_SKIP 4
73#define NPHY_ACI_40MHZ_CHANNEL_DELTA 6
74#define NPHY_ACI_40MHZ_CHANNEL_SKIP 5
75#define NPHY_ACI_40MHZ_CHANNEL_DELTA_GE_REV3 6
76#define NPHY_ACI_40MHZ_CHANNEL_SKIP_GE_REV3 5
77#define NPHY_ACI_CHANNEL_DELTA_GE_REV3 4
78#define NPHY_ACI_CHANNEL_SKIP_GE_REV3 3
79
80#define NPHY_NOISE_NOASSOC_GLITCH_TH_UP 2
81
82#define NPHY_NOISE_NOASSOC_GLITCH_TH_DN 8
83
84#define NPHY_NOISE_ASSOC_GLITCH_TH_UP 2
85
86#define NPHY_NOISE_ASSOC_GLITCH_TH_DN 8
87
88#define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_UP 2
89
90#define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_DN 8
91
92#define NPHY_NOISE_NOASSOC_ENTER_TH 400
93
94#define NPHY_NOISE_ASSOC_ENTER_TH 400
95
96#define NPHY_NOISE_ASSOC_RX_GLITCH_BADPLCP_ENTER_TH 400
97
98#define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX 44
99#define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX_REV_7 56
100
101#define NPHY_NOISE_NOASSOC_CRSIDX_INCR 16
102
103#define NPHY_NOISE_ASSOC_CRSIDX_INCR 8
104
105#define NPHY_IS_SROM_REINTERPRET NREV_GE(pi->pubpi.phy_rev, 5)
106
107#define NPHY_RSSICAL_MAXREAD 31
108
109#define NPHY_RSSICAL_NPOLL 8
110#define NPHY_RSSICAL_MAXD (1<<20)
111#define NPHY_MIN_RXIQ_PWR 2
112
113#define NPHY_RSSICAL_W1_TARGET 25
114#define NPHY_RSSICAL_W2_TARGET NPHY_RSSICAL_W1_TARGET
115#define NPHY_RSSICAL_NB_TARGET 0
116
117#define NPHY_RSSICAL_W1_TARGET_REV3 29
118#define NPHY_RSSICAL_W2_TARGET_REV3 NPHY_RSSICAL_W1_TARGET_REV3
119
120#define NPHY_CALSANITY_RSSI_NB_MAX_POS 9
121#define NPHY_CALSANITY_RSSI_NB_MAX_NEG -9
122#define NPHY_CALSANITY_RSSI_W1_MAX_POS 12
123#define NPHY_CALSANITY_RSSI_W1_MAX_NEG (NPHY_RSSICAL_W1_TARGET - \
124 NPHY_RSSICAL_MAXREAD)
125#define NPHY_CALSANITY_RSSI_W2_MAX_POS NPHY_CALSANITY_RSSI_W1_MAX_POS
126#define NPHY_CALSANITY_RSSI_W2_MAX_NEG (NPHY_RSSICAL_W2_TARGET - \
127 NPHY_RSSICAL_MAXREAD)
128#define NPHY_RSSI_SXT(x) ((s8) (-((x) & 0x20) + ((x) & 0x1f)))
129#define NPHY_RSSI_NB_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_NB_MAX_POS) || \
130 ((x) < NPHY_CALSANITY_RSSI_NB_MAX_NEG))
131#define NPHY_RSSI_W1_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W1_MAX_POS) || \
132 ((x) < NPHY_CALSANITY_RSSI_W1_MAX_NEG))
133#define NPHY_RSSI_W2_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W2_MAX_POS) || \
134 ((x) < NPHY_CALSANITY_RSSI_W2_MAX_NEG))
135
136#define NPHY_IQCAL_NUMGAINS 9
137#define NPHY_N_GCTL 0x66
138
139#define NPHY_PAPD_EPS_TBL_SIZE 64
140#define NPHY_PAPD_SCL_TBL_SIZE 64
141#define NPHY_NUM_DIG_FILT_COEFFS 15
142
143#define NPHY_PAPD_COMP_OFF 0
144#define NPHY_PAPD_COMP_ON 1
145
146#define NPHY_SROM_TEMPSHIFT 32
147#define NPHY_SROM_MAXTEMPOFFSET 16
148#define NPHY_SROM_MINTEMPOFFSET -16
149
150#define NPHY_CAL_MAXTEMPDELTA 64
151
152#define NPHY_NOISEVAR_TBLLEN40 256
153#define NPHY_NOISEVAR_TBLLEN20 128
154
155#define NPHY_ANARXLPFBW_REDUCTIONFACT 7
156
157#define NPHY_ADJUSTED_MINCRSPOWER 0x1e
158
159/* 5357 Chip specific ChipControl register bits */
160#define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */
161#define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */
162
163#define NPHY_CAL_TSSISAMPS 64
164#define NPHY_TEST_TONE_FREQ_40MHz 4000
165#define NPHY_TEST_TONE_FREQ_20MHz 2500
166
167#define MAX_205x_RCAL_WAITLOOPS 10000
168
169#define NPHY_RXCAL_TONEAMP 181
170#define NPHY_RXCAL_TONEFREQ_40MHz 4000
171#define NPHY_RXCAL_TONEFREQ_20MHz 2000
172
173#define TXFILT_SHAPING_OFDM20 0
174#define TXFILT_SHAPING_OFDM40 1
175#define TXFILT_SHAPING_CCK 2
176#define TXFILT_DEFAULT_OFDM20 3
177#define TXFILT_DEFAULT_OFDM40 4
178
179struct nphy_iqcal_params {
180 u16 txlpf;
181 u16 txgm;
182 u16 pga;
183 u16 pad;
184 u16 ipa;
185 u16 cal_gain;
186 u16 ncorr[5];
187};
188
189struct nphy_txiqcal_ladder {
190 u8 percent;
191 u8 g_env;
192};
193
194struct nphy_ipa_txcalgains {
195 struct nphy_txgains gains;
196 bool useindex;
197 u8 index;
198};
199
200struct nphy_papd_restore_state {
201 u16 fbmix[2];
202 u16 vga_master[2];
203 u16 intpa_master[2];
204 u16 afectrl[2];
205 u16 afeoverride[2];
206 u16 pwrup[2];
207 u16 atten[2];
208 u16 mm;
209};
210
211struct nphy_ipa_txrxgain {
212 u16 hpvga;
213 u16 lpf_biq1;
214 u16 lpf_biq0;
215 u16 lna2;
216 u16 lna1;
217 s8 txpwrindex;
218};
219
220#define NPHY_IPA_RXCAL_MAXGAININDEX (6 - 1)
221
222static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_5GHz[] = {
223 {0, 0, 0, 0, 0, 100},
224 {0, 0, 0, 0, 0, 50},
225 {0, 0, 0, 0, 0, -1},
226 {0, 0, 0, 3, 0, -1},
227 {0, 0, 3, 3, 0, -1},
228 {0, 2, 3, 3, 0, -1}
229};
230
231static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_2GHz[] = {
232 {0, 0, 0, 0, 0, 128},
233 {0, 0, 0, 0, 0, 70},
234 {0, 0, 0, 0, 0, 20},
235 {0, 0, 0, 3, 0, 20},
236 {0, 0, 3, 3, 0, 20},
237 {0, 2, 3, 3, 0, 20}
238};
239
240static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_5GHz_rev7[] = {
241 {0, 0, 0, 0, 0, 100},
242 {0, 0, 0, 0, 0, 50},
243 {0, 0, 0, 0, 0, -1},
244 {0, 0, 0, 3, 0, -1},
245 {0, 0, 3, 3, 0, -1},
246 {0, 0, 5, 3, 0, -1}
247};
248
249static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_2GHz_rev7[] = {
250 {0, 0, 0, 0, 0, 10},
251 {0, 0, 0, 1, 0, 10},
252 {0, 0, 1, 2, 0, 10},
253 {0, 0, 1, 3, 0, 10},
254 {0, 0, 4, 3, 0, 10},
255 {0, 0, 6, 3, 0, 10}
256};
257
258enum {
259 NPHY_RXCAL_GAIN_INIT = 0,
260 NPHY_RXCAL_GAIN_UP,
261 NPHY_RXCAL_GAIN_DOWN
262};
263
264#define wlc_phy_get_papd_nphy(pi) \
265 (read_phy_reg((pi), 0x1e7) & \
266 ((0x1 << 15) | \
267 (0x1 << 14) | \
268 (0x1 << 13)))
269
270static const u16 NPHY_IPA_REV4_txdigi_filtcoeffs[][NPHY_NUM_DIG_FILT_COEFFS] = {
271 {-377, 137, -407, 208, -1527, 956, 93, 186, 93,
272 230, -44, 230, 201, -191, 201},
273 {-77, 20, -98, 49, -93, 60, 56, 111, 56, 26, -5,
274 26, 34, -32, 34},
275 {-360, 164, -376, 164, -1533, 576, 308, -314, 308,
276 121, -73, 121, 91, 124, 91},
277 {-295, 200, -363, 142, -1391, 826, 151, 301, 151,
278 151, 301, 151, 602, -752, 602},
279 {-92, 58, -96, 49, -104, 44, 17, 35, 17,
280 12, 25, 12, 13, 27, 13},
281 {-375, 136, -399, 209, -1479, 949, 130, 260, 130,
282 230, -44, 230, 201, -191, 201},
283 {0xed9, 0xc8, 0xe95, 0x8e, 0xa91, 0x33a, 0x97, 0x12d, 0x97,
284 0x97, 0x12d, 0x97, 0x25a, 0xd10, 0x25a}
285};
286
287struct chan_info_nphy_2055 {
288 u16 chan;
289 u16 freq;
290 uint unknown;
291 u8 RF_pll_ref;
292 u8 RF_rf_pll_mod1;
293 u8 RF_rf_pll_mod0;
294 u8 RF_vco_cap_tail;
295 u8 RF_vco_cal1;
296 u8 RF_vco_cal2;
297 u8 RF_pll_lf_c1;
298 u8 RF_pll_lf_r1;
299 u8 RF_pll_lf_c2;
300 u8 RF_lgbuf_cen_buf;
301 u8 RF_lgen_tune1;
302 u8 RF_lgen_tune2;
303 u8 RF_core1_lgbuf_a_tune;
304 u8 RF_core1_lgbuf_g_tune;
305 u8 RF_core1_rxrf_reg1;
306 u8 RF_core1_tx_pga_pad_tn;
307 u8 RF_core1_tx_mx_bgtrim;
308 u8 RF_core2_lgbuf_a_tune;
309 u8 RF_core2_lgbuf_g_tune;
310 u8 RF_core2_rxrf_reg1;
311 u8 RF_core2_tx_pga_pad_tn;
312 u8 RF_core2_tx_mx_bgtrim;
313 u16 PHY_BW1a;
314 u16 PHY_BW2;
315 u16 PHY_BW3;
316 u16 PHY_BW4;
317 u16 PHY_BW5;
318 u16 PHY_BW6;
319};
320
321struct chan_info_nphy_radio205x {
322 u16 chan;
323 u16 freq;
324 u8 RF_SYN_pll_vcocal1;
325 u8 RF_SYN_pll_vcocal2;
326 u8 RF_SYN_pll_refdiv;
327 u8 RF_SYN_pll_mmd2;
328 u8 RF_SYN_pll_mmd1;
329 u8 RF_SYN_pll_loopfilter1;
330 u8 RF_SYN_pll_loopfilter2;
331 u8 RF_SYN_pll_loopfilter3;
332 u8 RF_SYN_pll_loopfilter4;
333 u8 RF_SYN_pll_loopfilter5;
334 u8 RF_SYN_reserved_addr27;
335 u8 RF_SYN_reserved_addr28;
336 u8 RF_SYN_reserved_addr29;
337 u8 RF_SYN_logen_VCOBUF1;
338 u8 RF_SYN_logen_MIXER2;
339 u8 RF_SYN_logen_BUF3;
340 u8 RF_SYN_logen_BUF4;
341 u8 RF_RX0_lnaa_tune;
342 u8 RF_RX0_lnag_tune;
343 u8 RF_TX0_intpaa_boost_tune;
344 u8 RF_TX0_intpag_boost_tune;
345 u8 RF_TX0_pada_boost_tune;
346 u8 RF_TX0_padg_boost_tune;
347 u8 RF_TX0_pgaa_boost_tune;
348 u8 RF_TX0_pgag_boost_tune;
349 u8 RF_TX0_mixa_boost_tune;
350 u8 RF_TX0_mixg_boost_tune;
351 u8 RF_RX1_lnaa_tune;
352 u8 RF_RX1_lnag_tune;
353 u8 RF_TX1_intpaa_boost_tune;
354 u8 RF_TX1_intpag_boost_tune;
355 u8 RF_TX1_pada_boost_tune;
356 u8 RF_TX1_padg_boost_tune;
357 u8 RF_TX1_pgaa_boost_tune;
358 u8 RF_TX1_pgag_boost_tune;
359 u8 RF_TX1_mixa_boost_tune;
360 u8 RF_TX1_mixg_boost_tune;
361 u16 PHY_BW1a;
362 u16 PHY_BW2;
363 u16 PHY_BW3;
364 u16 PHY_BW4;
365 u16 PHY_BW5;
366 u16 PHY_BW6;
367};
368
369struct chan_info_nphy_radio2057 {
370 u16 chan;
371 u16 freq;
372 u8 RF_vcocal_countval0;
373 u8 RF_vcocal_countval1;
374 u8 RF_rfpll_refmaster_sparextalsize;
375 u8 RF_rfpll_loopfilter_r1;
376 u8 RF_rfpll_loopfilter_c2;
377 u8 RF_rfpll_loopfilter_c1;
378 u8 RF_cp_kpd_idac;
379 u8 RF_rfpll_mmd0;
380 u8 RF_rfpll_mmd1;
381 u8 RF_vcobuf_tune;
382 u8 RF_logen_mx2g_tune;
383 u8 RF_logen_mx5g_tune;
384 u8 RF_logen_indbuf2g_tune;
385 u8 RF_logen_indbuf5g_tune;
386 u8 RF_txmix2g_tune_boost_pu_core0;
387 u8 RF_pad2g_tune_pus_core0;
388 u8 RF_pga_boost_tune_core0;
389 u8 RF_txmix5g_boost_tune_core0;
390 u8 RF_pad5g_tune_misc_pus_core0;
391 u8 RF_lna2g_tune_core0;
392 u8 RF_lna5g_tune_core0;
393 u8 RF_txmix2g_tune_boost_pu_core1;
394 u8 RF_pad2g_tune_pus_core1;
395 u8 RF_pga_boost_tune_core1;
396 u8 RF_txmix5g_boost_tune_core1;
397 u8 RF_pad5g_tune_misc_pus_core1;
398 u8 RF_lna2g_tune_core1;
399 u8 RF_lna5g_tune_core1;
400 u16 PHY_BW1a;
401 u16 PHY_BW2;
402 u16 PHY_BW3;
403 u16 PHY_BW4;
404 u16 PHY_BW5;
405 u16 PHY_BW6;
406};
407
408struct chan_info_nphy_radio2057_rev5 {
409 u16 chan;
410 u16 freq;
411 u8 RF_vcocal_countval0;
412 u8 RF_vcocal_countval1;
413 u8 RF_rfpll_refmaster_sparextalsize;
414 u8 RF_rfpll_loopfilter_r1;
415 u8 RF_rfpll_loopfilter_c2;
416 u8 RF_rfpll_loopfilter_c1;
417 u8 RF_cp_kpd_idac;
418 u8 RF_rfpll_mmd0;
419 u8 RF_rfpll_mmd1;
420 u8 RF_vcobuf_tune;
421 u8 RF_logen_mx2g_tune;
422 u8 RF_logen_indbuf2g_tune;
423 u8 RF_txmix2g_tune_boost_pu_core0;
424 u8 RF_pad2g_tune_pus_core0;
425 u8 RF_lna2g_tune_core0;
426 u8 RF_txmix2g_tune_boost_pu_core1;
427 u8 RF_pad2g_tune_pus_core1;
428 u8 RF_lna2g_tune_core1;
429 u16 PHY_BW1a;
430 u16 PHY_BW2;
431 u16 PHY_BW3;
432 u16 PHY_BW4;
433 u16 PHY_BW5;
434 u16 PHY_BW6;
435};
436
437struct nphy_sfo_cfg {
438 u16 PHY_BW1a;
439 u16 PHY_BW2;
440 u16 PHY_BW3;
441 u16 PHY_BW4;
442 u16 PHY_BW5;
443 u16 PHY_BW6;
444};
445
446static const struct chan_info_nphy_2055 chan_info_nphy_2055[] = {
447 {
448 184, 4920, 3280, 0x71, 0x01, 0xEC, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
449 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
450 0x0F, 0x8F, 0x7B4, 0x7B0, 0x7AC, 0x214, 0x215, 0x216},
451 {
452 186, 4930, 3287, 0x71, 0x01, 0xED, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
453 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
454 0x0F, 0x8F, 0x7B8, 0x7B4, 0x7B0, 0x213, 0x214, 0x215},
455 {
456 188, 4940, 3293, 0x71, 0x01, 0xEE, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
457 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
458 0x0F, 0x8F, 0x7BC, 0x7B8, 0x7B4, 0x212, 0x213, 0x214},
459 {
460 190, 4950, 3300, 0x71, 0x01, 0xEF, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
461 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
462 0x0F, 0x8F, 0x7C0, 0x7BC, 0x7B8, 0x211, 0x212, 0x213},
463 {
464 192, 4960, 3307, 0x71, 0x01, 0xF0, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
465 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
466 0x0F, 0x8F, 0x7C4, 0x7C0, 0x7BC, 0x20F, 0x211, 0x212},
467 {
468 194, 4970, 3313, 0x71, 0x01, 0xF1, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
469 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
470 0x0F, 0x8F, 0x7C8, 0x7C4, 0x7C0, 0x20E, 0x20F, 0x211},
471 {
472 196, 4980, 3320, 0x71, 0x01, 0xF2, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
473 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
474 0x0F, 0x8F, 0x7CC, 0x7C8, 0x7C4, 0x20D, 0x20E, 0x20F},
475 {
476 198, 4990, 3327, 0x71, 0x01, 0xF3, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
477 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
478 0x0F, 0x8F, 0x7D0, 0x7CC, 0x7C8, 0x20C, 0x20D, 0x20E},
479 {
480 200, 5000, 3333, 0x71, 0x01, 0xF4, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
481 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
482 0x0F, 0x8F, 0x7D4, 0x7D0, 0x7CC, 0x20B, 0x20C, 0x20D},
483 {
484 202, 5010, 3340, 0x71, 0x01, 0xF5, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
485 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
486 0x0F, 0x8F, 0x7D8, 0x7D4, 0x7D0, 0x20A, 0x20B, 0x20C},
487 {
488 204, 5020, 3347, 0x71, 0x01, 0xF6, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
489 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
490 0x0F, 0x8F, 0x7DC, 0x7D8, 0x7D4, 0x209, 0x20A, 0x20B},
491 {
492 206, 5030, 3353, 0x71, 0x01, 0xF7, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
493 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
494 0x0F, 0x8F, 0x7E0, 0x7DC, 0x7D8, 0x208, 0x209, 0x20A},
495 {
496 208, 5040, 3360, 0x71, 0x01, 0xF8, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
497 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
498 0x0F, 0x8F, 0x7E4, 0x7E0, 0x7DC, 0x207, 0x208, 0x209},
499 {
500 210, 5050, 3367, 0x71, 0x01, 0xF9, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
501 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
502 0x0F, 0x8F, 0x7E8, 0x7E4, 0x7E0, 0x206, 0x207, 0x208},
503 {
504 212, 5060, 3373, 0x71, 0x01, 0xFA, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
505 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, 0x8E, 0xFF, 0x00, 0x0E,
506 0x0F, 0x8E, 0x7EC, 0x7E8, 0x7E4, 0x205, 0x206, 0x207},
507 {
508 214, 5070, 3380, 0x71, 0x01, 0xFB, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
509 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, 0x8E, 0xFF, 0x00, 0x0E,
510 0x0F, 0x8E, 0x7F0, 0x7EC, 0x7E8, 0x204, 0x205, 0x206},
511 {
512 216, 5080, 3387, 0x71, 0x01, 0xFC, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
513 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, 0x8D, 0xEE, 0x00, 0x0E,
514 0x0F, 0x8D, 0x7F4, 0x7F0, 0x7EC, 0x203, 0x204, 0x205},
515 {
516 218, 5090, 3393, 0x71, 0x01, 0xFD, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
517 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, 0x8D, 0xEE, 0x00, 0x0E,
518 0x0F, 0x8D, 0x7F8, 0x7F4, 0x7F0, 0x202, 0x203, 0x204},
519 {
520 220, 5100, 3400, 0x71, 0x01, 0xFE, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
521 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, 0x8D, 0xEE, 0x00, 0x0D,
522 0x0F, 0x8D, 0x7FC, 0x7F8, 0x7F4, 0x201, 0x202, 0x203},
523 {
524 222, 5110, 3407, 0x71, 0x01, 0xFF, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
525 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, 0x8D, 0xEE, 0x00, 0x0D,
526 0x0F, 0x8D, 0x800, 0x7FC, 0x7F8, 0x200, 0x201, 0x202},
527 {
528 224, 5120, 3413, 0x71, 0x02, 0x00, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
529 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, 0x8C, 0xDD, 0x00, 0x0D,
530 0x0F, 0x8C, 0x804, 0x800, 0x7FC, 0x1FF, 0x200, 0x201},
531 {
532 226, 5130, 3420, 0x71, 0x02, 0x01, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
533 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, 0x8C, 0xDD, 0x00, 0x0D,
534 0x0F, 0x8C, 0x808, 0x804, 0x800, 0x1FE, 0x1FF, 0x200},
535 {
536 228, 5140, 3427, 0x71, 0x02, 0x02, 0x0C, 0xC6, 0x01, 0x04, 0x0A,
537 0x00, 0x8D, 0x99, 0x99, 0xDD, 0x00, 0x0C, 0x0E, 0x8B, 0xDD, 0x00, 0x0C,
538 0x0E, 0x8B, 0x80C, 0x808, 0x804, 0x1FD, 0x1FE, 0x1FF},
539 {
540 32, 5160, 3440, 0x71, 0x02, 0x04, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
541 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, 0x8A, 0xCC, 0x00, 0x0B,
542 0x0D, 0x8A, 0x814, 0x810, 0x80C, 0x1FB, 0x1FC, 0x1FD},
543 {
544 34, 5170, 3447, 0x71, 0x02, 0x05, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
545 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, 0x8A, 0xCC, 0x00, 0x0B,
546 0x0D, 0x8A, 0x818, 0x814, 0x810, 0x1FA, 0x1FB, 0x1FC},
547 {
548 36, 5180, 3453, 0x71, 0x02, 0x06, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
549 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, 0x89, 0xCC, 0x00, 0x0B,
550 0x0C, 0x89, 0x81C, 0x818, 0x814, 0x1F9, 0x1FA, 0x1FB},
551 {
552 38, 5190, 3460, 0x71, 0x02, 0x07, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
553 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, 0x89, 0xCC, 0x00, 0x0B,
554 0x0C, 0x89, 0x820, 0x81C, 0x818, 0x1F8, 0x1F9, 0x1FA},
555 {
556 40, 5200, 3467, 0x71, 0x02, 0x08, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
557 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, 0x89, 0xBB, 0x00, 0x0A,
558 0x0B, 0x89, 0x824, 0x820, 0x81C, 0x1F7, 0x1F8, 0x1F9},
559 {
560 42, 5210, 3473, 0x71, 0x02, 0x09, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
561 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, 0x89, 0xBB, 0x00, 0x0A,
562 0x0B, 0x89, 0x828, 0x824, 0x820, 0x1F6, 0x1F7, 0x1F8},
563 {
564 44, 5220, 3480, 0x71, 0x02, 0x0A, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
565 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A, 0x88, 0xBB, 0x00, 0x09,
566 0x0A, 0x88, 0x82C, 0x828, 0x824, 0x1F5, 0x1F6, 0x1F7},
567 {
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791 {
792 151, 5755, 3837, 0x72, 0x04, 0x7F, 0x02, 0xFE, 0x00, 0x03, 0x14,
793 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
794 0x00, 0x80, 0x902, 0x8FE, 0x8FA, 0x1C7, 0x1C8, 0x1C8},
795 {
796 152, 5760, 3840, 0x71, 0x02, 0x40, 0x02, 0x0A, 0x01, 0x04, 0x0A,
797 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
798 0x00, 0x80, 0x904, 0x900, 0x8FC, 0x1C6, 0x1C7, 0x1C8},
799 {
800 153, 5765, 3843, 0x72, 0x04, 0x81, 0x02, 0xF8, 0x00, 0x03, 0x14,
801 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
802 0x00, 0x80, 0x906, 0x902, 0x8FE, 0x1C6, 0x1C7, 0x1C8},
803 {
804 154, 5770, 3847, 0x71, 0x02, 0x41, 0x02, 0x0A, 0x01, 0x04, 0x0A,
805 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
806 0x00, 0x80, 0x908, 0x904, 0x900, 0x1C6, 0x1C6, 0x1C7},
807 {
808 155, 5775, 3850, 0x72, 0x04, 0x83, 0x02, 0xF8, 0x00, 0x03, 0x14,
809 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
810 0x00, 0x80, 0x90A, 0x906, 0x902, 0x1C5, 0x1C6, 0x1C7},
811 {
812 156, 5780, 3853, 0x71, 0x02, 0x42, 0x02, 0x0A, 0x01, 0x04, 0x0A,
813 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
814 0x00, 0x80, 0x90C, 0x908, 0x904, 0x1C5, 0x1C6, 0x1C6},
815 {
816 157, 5785, 3857, 0x72, 0x04, 0x85, 0x02, 0xF2, 0x00, 0x03, 0x14,
817 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
818 0x00, 0x80, 0x90E, 0x90A, 0x906, 0x1C4, 0x1C5, 0x1C6},
819 {
820 158, 5790, 3860, 0x71, 0x02, 0x43, 0x02, 0x0A, 0x01, 0x04, 0x0A,
821 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
822 0x00, 0x80, 0x910, 0x90C, 0x908, 0x1C4, 0x1C5, 0x1C6},
823 {
824 159, 5795, 3863, 0x72, 0x04, 0x87, 0x02, 0xF2, 0x00, 0x03, 0x14,
825 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
826 0x00, 0x80, 0x912, 0x90E, 0x90A, 0x1C4, 0x1C4, 0x1C5},
827 {
828 160, 5800, 3867, 0x71, 0x02, 0x44, 0x01, 0x0A, 0x01, 0x04, 0x0A,
829 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
830 0x00, 0x80, 0x914, 0x910, 0x90C, 0x1C3, 0x1C4, 0x1C5},
831 {
832 161, 5805, 3870, 0x72, 0x04, 0x89, 0x01, 0xED, 0x00, 0x03, 0x14,
833 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
834 0x00, 0x80, 0x916, 0x912, 0x90E, 0x1C3, 0x1C4, 0x1C4},
835 {
836 162, 5810, 3873, 0x71, 0x02, 0x45, 0x01, 0x0A, 0x01, 0x04, 0x0A,
837 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
838 0x00, 0x80, 0x918, 0x914, 0x910, 0x1C2, 0x1C3, 0x1C4},
839 {
840 163, 5815, 3877, 0x72, 0x04, 0x8B, 0x01, 0xED, 0x00, 0x03, 0x14,
841 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
842 0x00, 0x80, 0x91A, 0x916, 0x912, 0x1C2, 0x1C3, 0x1C4},
843 {
844 164, 5820, 3880, 0x71, 0x02, 0x46, 0x01, 0x0A, 0x01, 0x04, 0x0A,
845 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
846 0x00, 0x80, 0x91C, 0x918, 0x914, 0x1C2, 0x1C2, 0x1C3},
847 {
848 165, 5825, 3883, 0x72, 0x04, 0x8D, 0x01, 0xED, 0x00, 0x03, 0x14,
849 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
850 0x00, 0x80, 0x91E, 0x91A, 0x916, 0x1C1, 0x1C2, 0x1C3},
851 {
852 166, 5830, 3887, 0x71, 0x02, 0x47, 0x01, 0x0A, 0x01, 0x04, 0x0A,
853 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
854 0x00, 0x80, 0x920, 0x91C, 0x918, 0x1C1, 0x1C2, 0x1C2},
855 {
856 168, 5840, 3893, 0x71, 0x02, 0x48, 0x01, 0x0A, 0x01, 0x04, 0x0A,
857 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
858 0x00, 0x80, 0x924, 0x920, 0x91C, 0x1C0, 0x1C1, 0x1C2},
859 {
860 170, 5850, 3900, 0x71, 0x02, 0x49, 0x01, 0xE0, 0x00, 0x04, 0x0A,
861 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
862 0x00, 0x80, 0x928, 0x924, 0x920, 0x1BF, 0x1C0, 0x1C1},
863 {
864 172, 5860, 3907, 0x71, 0x02, 0x4A, 0x01, 0xDE, 0x00, 0x04, 0x0A,
865 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
866 0x00, 0x80, 0x92C, 0x928, 0x924, 0x1BF, 0x1BF, 0x1C0},
867 {
868 174, 5870, 3913, 0x71, 0x02, 0x4B, 0x00, 0xDB, 0x00, 0x04, 0x0A,
869 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
870 0x00, 0x80, 0x930, 0x92C, 0x928, 0x1BE, 0x1BF, 0x1BF},
871 {
872 176, 5880, 3920, 0x71, 0x02, 0x4C, 0x00, 0xD8, 0x00, 0x04, 0x0A,
873 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
874 0x00, 0x80, 0x934, 0x930, 0x92C, 0x1BD, 0x1BE, 0x1BF},
875 {
876 178, 5890, 3927, 0x71, 0x02, 0x4D, 0x00, 0xD6, 0x00, 0x04, 0x0A,
877 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
878 0x00, 0x80, 0x938, 0x934, 0x930, 0x1BC, 0x1BD, 0x1BE},
879 {
880 180, 5900, 3933, 0x71, 0x02, 0x4E, 0x00, 0xD3, 0x00, 0x04, 0x0A,
881 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
882 0x00, 0x80, 0x93C, 0x938, 0x934, 0x1BC, 0x1BC, 0x1BD},
883 {
884 182, 5910, 3940, 0x71, 0x02, 0x4F, 0x00, 0xD6, 0x00, 0x04, 0x0A,
885 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
886 0x00, 0x80, 0x940, 0x93C, 0x938, 0x1BB, 0x1BC, 0x1BC},
887 {
888 1, 2412, 3216, 0x73, 0x09, 0x6C, 0x0F, 0x00, 0x01, 0x07, 0x15,
889 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0D, 0x0C, 0x80, 0xFF, 0x88, 0x0D,
890 0x0C, 0x80, 0x3C9, 0x3C5, 0x3C1, 0x43A, 0x43F, 0x443},
891 {
892 2, 2417, 3223, 0x73, 0x09, 0x71, 0x0F, 0x00, 0x01, 0x07, 0x15,
893 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0B, 0x80, 0xFF, 0x88, 0x0C,
894 0x0B, 0x80, 0x3CB, 0x3C7, 0x3C3, 0x438, 0x43D, 0x441},
895 {
896 3, 2422, 3229, 0x73, 0x09, 0x76, 0x0F, 0x00, 0x01, 0x07, 0x15,
897 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, 0x80, 0xFF, 0x88, 0x0C,
898 0x0A, 0x80, 0x3CD, 0x3C9, 0x3C5, 0x436, 0x43A, 0x43F},
899 {
900 4, 2427, 3236, 0x73, 0x09, 0x7B, 0x0F, 0x00, 0x01, 0x07, 0x15,
901 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, 0x80, 0xFF, 0x88, 0x0C,
902 0x0A, 0x80, 0x3CF, 0x3CB, 0x3C7, 0x434, 0x438, 0x43D},
903 {
904 5, 2432, 3243, 0x73, 0x09, 0x80, 0x0F, 0x00, 0x01, 0x07, 0x15,
905 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x09, 0x80, 0xFF, 0x88, 0x0C,
906 0x09, 0x80, 0x3D1, 0x3CD, 0x3C9, 0x431, 0x436, 0x43A},
907 {
908 6, 2437, 3249, 0x73, 0x09, 0x85, 0x0F, 0x00, 0x01, 0x07, 0x15,
909 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0B, 0x08, 0x80, 0xFF, 0x88, 0x0B,
910 0x08, 0x80, 0x3D3, 0x3CF, 0x3CB, 0x42F, 0x434, 0x438},
911 {
912 7, 2442, 3256, 0x73, 0x09, 0x8A, 0x0F, 0x00, 0x01, 0x07, 0x15,
913 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x07, 0x80, 0xFF, 0x88, 0x0A,
914 0x07, 0x80, 0x3D5, 0x3D1, 0x3CD, 0x42D, 0x431, 0x436},
915 {
916 8, 2447, 3263, 0x73, 0x09, 0x8F, 0x0F, 0x00, 0x01, 0x07, 0x15,
917 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x06, 0x80, 0xFF, 0x88, 0x0A,
918 0x06, 0x80, 0x3D7, 0x3D3, 0x3CF, 0x42B, 0x42F, 0x434},
919 {
920 9, 2452, 3269, 0x73, 0x09, 0x94, 0x0F, 0x00, 0x01, 0x07, 0x15,
921 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x09, 0x06, 0x80, 0xFF, 0x88, 0x09,
922 0x06, 0x80, 0x3D9, 0x3D5, 0x3D1, 0x429, 0x42D, 0x431},
923 {
924 10, 2457, 3276, 0x73, 0x09, 0x99, 0x0F, 0x00, 0x01, 0x07, 0x15,
925 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x05, 0x80, 0xFF, 0x88, 0x08,
926 0x05, 0x80, 0x3DB, 0x3D7, 0x3D3, 0x427, 0x42B, 0x42F},
927 {
928 11, 2462, 3283, 0x73, 0x09, 0x9E, 0x0F, 0x00, 0x01, 0x07, 0x15,
929 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x04, 0x80, 0xFF, 0x88, 0x08,
930 0x04, 0x80, 0x3DD, 0x3D9, 0x3D5, 0x424, 0x429, 0x42D},
931 {
932 12, 2467, 3289, 0x73, 0x09, 0xA3, 0x0F, 0x00, 0x01, 0x07, 0x15,
933 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x03, 0x80, 0xFF, 0x88, 0x08,
934 0x03, 0x80, 0x3DF, 0x3DB, 0x3D7, 0x422, 0x427, 0x42B},
935 {
936 13, 2472, 3296, 0x73, 0x09, 0xA8, 0x0F, 0x00, 0x01, 0x07, 0x15,
937 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x03, 0x80, 0xFF, 0x88, 0x07,
938 0x03, 0x80, 0x3E1, 0x3DD, 0x3D9, 0x420, 0x424, 0x429},
939 {
940 14, 2484, 3312, 0x73, 0x09, 0xB4, 0x0F, 0xFF, 0x01, 0x07, 0x15,
941 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x01, 0x80, 0xFF, 0x88, 0x07,
942 0x01, 0x80, 0x3E6, 0x3E2, 0x3DE, 0x41B, 0x41F, 0x424}
943};
944
945static const struct chan_info_nphy_radio205x chan_info_nphyrev3_2056[] = {
946 {
947 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
948 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
949 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
950 0x00, 0xff, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
951 {
952 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
953 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
954 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
955 0x00, 0xff, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
956 {
957 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
958 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
959 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
960 0x00, 0xff, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
961 {
962 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
963 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
964 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
965 0x00, 0xff, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
966 {
967 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
968 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
969 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
970 0x00, 0xff, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
971 {
972 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
973 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
974 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
975 0x00, 0xff, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
976 {
977 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
978 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
979 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
980 0x00, 0xff, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
981 {
982 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
983 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
984 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
985 0x00, 0xff, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
986 {
987 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
988 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
989 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
990 0x00, 0xff, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
991 {
992 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
993 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
994 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
995 0x00, 0xff, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
996 {
997 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
998 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
999 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1000 0x00, 0xff, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
1001 {
1002 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
1003 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1004 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1005 0x00, 0xff, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
1006 {
1007 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
1008 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1009 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1010 0x00, 0xff, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
1011 {
1012 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
1013 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1014 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1015 0x00, 0xff, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
1016 {
1017 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
1018 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1019 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1020 0x00, 0xff, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
1021 {
1022 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
1023 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1024 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1025 0x00, 0xff, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
1026 {
1027 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
1028 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1029 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1030 0x00, 0xff, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
1031 {
1032 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
1033 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1034 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1035 0x00, 0xff, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
1036 {
1037 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
1038 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1039 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1040 0x00, 0xff, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
1041 {
1042 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
1043 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1044 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1045 0x00, 0xfc, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
1046 {
1047 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
1048 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1049 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1050 0x00, 0xfc, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
1051 {
1052 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
1053 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1054 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1055 0x00, 0xfc, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
1056 {
1057 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
1058 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1059 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1060 0x00, 0xfc, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
1061 {
1062 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
1063 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1064 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1065 0x00, 0xfc, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
1066 {
1067 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
1068 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
1069 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1070 0x00, 0xfc, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
1071 {
1072 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, 0x0c, 0x01,
1073 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xef, 0x00, 0x07, 0x00, 0x7f,
1074 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xef, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1075 0x00, 0xfc, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
1076 {
1077 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, 0x0c, 0x01,
1078 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xef, 0x00, 0x07, 0x00, 0x7f,
1079 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xef, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
1080 0x00, 0xfc, 0x00, 0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa},
1081 {
1082 40, 5200, 0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, 0x0c, 0x01,
1083 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xef, 0x00, 0x06, 0x00, 0x7f,
1084 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xef, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1085 0x00, 0xfc, 0x00, 0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9},
1086 {
1087 42, 5210, 0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, 0x0c, 0x01,
1088 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f,
1089 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1090 0x00, 0xfc, 0x00, 0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8},
1091 {
1092 44, 5220, 0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, 0x0c, 0x01,
1093 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f,
1094 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1095 0x00, 0xfc, 0x00, 0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7},
1096 {
1097 46, 5230, 0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, 0x0c, 0x01,
1098 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f,
1099 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1100 0x00, 0xfc, 0x00, 0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6},
1101 {
1102 48, 5240, 0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, 0x0c, 0x01,
1103 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f,
1104 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1105 0x00, 0xfc, 0x00, 0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5},
1106 {
1107 50, 5250, 0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, 0x0c, 0x01,
1108 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f,
1109 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1110 0x00, 0xfc, 0x00, 0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4},
1111 {
1112 52, 5260, 0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, 0x0c, 0x01,
1113 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f,
1114 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1115 0x00, 0xfc, 0x00, 0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3},
1116 {
1117 54, 5270, 0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, 0x0c, 0x01,
1118 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f,
1119 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1120 0x00, 0xfc, 0x00, 0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2},
1121 {
1122 56, 5280, 0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, 0x0c, 0x01,
1123 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, 0xff, 0xbf, 0x00, 0x06, 0x00, 0x7f,
1124 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1125 0x00, 0xfc, 0x00, 0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1},
1126 {
1127 58, 5290, 0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, 0x0c, 0x01,
1128 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, 0xff, 0xbf, 0x00, 0x06, 0x00, 0x7f,
1129 0x00, 0x0a, 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
1130 0x00, 0xfc, 0x00, 0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0},
1131 {
1132 60, 5300, 0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, 0x0c, 0x01,
1133 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f,
1134 0x00, 0x09, 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1135 0x00, 0xfc, 0x00, 0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0},
1136 {
1137 62, 5310, 0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, 0x0c, 0x01,
1138 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f,
1139 0x00, 0x09, 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1140 0x00, 0xfa, 0x00, 0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef},
1141 {
1142 64, 5320, 0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, 0x0c, 0x01,
1143 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f,
1144 0x00, 0x09, 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1145 0x00, 0xfa, 0x00, 0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee},
1146 {
1147 66, 5330, 0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, 0x0c, 0x01,
1148 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xaf, 0x00, 0x05, 0x00, 0x7f,
1149 0x00, 0x09, 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1150 0x00, 0xfa, 0x00, 0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed},
1151 {
1152 68, 5340, 0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, 0x0c, 0x01,
1153 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xaf, 0x00, 0x05, 0x00, 0x7f,
1154 0x00, 0x09, 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1155 0x00, 0xfa, 0x00, 0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec},
1156 {
1157 70, 5350, 0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, 0x0c, 0x01,
1158 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f,
1159 0x00, 0x09, 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1160 0x00, 0xfa, 0x00, 0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb},
1161 {
1162 72, 5360, 0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, 0x0c, 0x01,
1163 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f,
1164 0x00, 0x09, 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1165 0x00, 0xfa, 0x00, 0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea},
1166 {
1167 74, 5370, 0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, 0x0c, 0x01,
1168 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f,
1169 0x00, 0x09, 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1170 0x00, 0xfa, 0x00, 0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9},
1171 {
1172 76, 5380, 0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, 0x0c, 0x01,
1173 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f,
1174 0x00, 0x09, 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1175 0x00, 0xfa, 0x00, 0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8},
1176 {
1177 78, 5390, 0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, 0x0c, 0x01,
1178 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0x8f, 0x00, 0x05, 0x00, 0x7f,
1179 0x00, 0x09, 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
1180 0x00, 0xfa, 0x00, 0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7},
1181 {
1182 80, 5400, 0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, 0x0c, 0x01,
1183 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, 0xc8, 0x8f, 0x00, 0x04, 0x00, 0x7f,
1184 0x00, 0x08, 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
1185 0x00, 0xfa, 0x00, 0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6},
1186 {
1187 82, 5410, 0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, 0x0c, 0x01,
1188 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, 0xc8, 0x8f, 0x00, 0x04, 0x00, 0x7f,
1189 0x00, 0x08, 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
1190 0x00, 0xfa, 0x00, 0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5},
1191 {
1192 84, 5420, 0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, 0x0c, 0x01,
1193 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, 0xc8, 0x8e, 0x00, 0x04, 0x00, 0x7f,
1194 0x00, 0x08, 0x00, 0xfa, 0x00, 0x8e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
1195 0x00, 0xfa, 0x00, 0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5},
1196 {
1197 86, 5430, 0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, 0x0c, 0x01,
1198 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, 0xc8, 0x8e, 0x00, 0x04, 0x00, 0x7f,
1199 0x00, 0x08, 0x00, 0xfa, 0x00, 0x8e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
1200 0x00, 0xfa, 0x00, 0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4},
1201 {
1202 88, 5440, 0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, 0x0c, 0x01,
1203 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x7e, 0x00, 0x04, 0x00, 0x7f,
1204 0x00, 0x08, 0x00, 0xfa, 0x00, 0x7e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
1205 0x00, 0xfa, 0x00, 0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3},
1206 {
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1208 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x7d, 0x00, 0x04, 0x00, 0x7f,
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1210 0x00, 0xfa, 0x00, 0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2},
1211 {
1212 92, 5460, 0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, 0x0c, 0x01,
1213 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x6d, 0x00, 0x04, 0x00, 0x7f,
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1215 0x00, 0xf8, 0x00, 0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1},
1216 {
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1218 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x6d, 0x00, 0x04, 0x00, 0x7f,
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1220 0x00, 0xf8, 0x00, 0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0},
1221 {
1222 96, 5480, 0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, 0x0c, 0x01,
1223 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x5d, 0x00, 0x04, 0x00, 0x7f,
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1225 0x00, 0xf8, 0x00, 0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df},
1226 {
1227 98, 5490, 0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, 0x0c, 0x01,
1228 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x5c, 0x00, 0x04, 0x00, 0x7f,
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1230 0x00, 0xf8, 0x00, 0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de},
1231 {
1232 100, 5500, 0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, 0x0c, 0x01,
1233 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x5c, 0x00, 0x03, 0x00, 0x7f,
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1235 0x00, 0xf8, 0x00, 0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd},
1236 {
1237 102, 5510, 0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, 0x0c, 0x01,
1238 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x4c, 0x00, 0x03, 0x00, 0x7f,
1239 0x00, 0x07, 0x00, 0xf8, 0x00, 0x4c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1240 0x00, 0xf8, 0x00, 0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd},
1241 {
1242 104, 5520, 0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, 0x0c, 0x01,
1243 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x4c, 0x00, 0x03, 0x00, 0x7f,
1244 0x00, 0x07, 0x00, 0xf8, 0x00, 0x4c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1245 0x00, 0xf8, 0x00, 0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc},
1246 {
1247 106, 5530, 0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, 0x0c, 0x01,
1248 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f,
1249 0x00, 0x07, 0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1250 0x00, 0xf8, 0x00, 0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db},
1251 {
1252 108, 5540, 0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, 0x0c, 0x01,
1253 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f,
1254 0x00, 0x07, 0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1255 0x00, 0xf8, 0x00, 0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da},
1256 {
1257 110, 5550, 0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, 0x0c, 0x01,
1258 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f,
1259 0x00, 0x07, 0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1260 0x00, 0xf8, 0x00, 0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9},
1261 {
1262 112, 5560, 0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, 0x0c, 0x01,
1263 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x2b, 0x00, 0x03, 0x00, 0x7f,
1264 0x00, 0x07, 0x00, 0xf8, 0x00, 0x2b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1265 0x00, 0xf8, 0x00, 0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8},
1266 {
1267 114, 5570, 0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, 0x0c, 0x01,
1268 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x2a, 0x00, 0x03, 0x00, 0x7f,
1269 0x00, 0x07, 0x00, 0xf8, 0x00, 0x2a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1270 0x00, 0xf8, 0x00, 0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7},
1271 {
1272 116, 5580, 0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, 0x0c, 0x01,
1273 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x1a, 0x00, 0x03, 0x00, 0x7f,
1274 0x00, 0x07, 0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1275 0x00, 0xf8, 0x00, 0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7},
1276 {
1277 118, 5590, 0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, 0x0c, 0x01,
1278 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x1a, 0x00, 0x03, 0x00, 0x7f,
1279 0x00, 0x07, 0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1280 0x00, 0xf8, 0x00, 0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6},
1281 {
1282 120, 5600, 0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, 0x0c, 0x01,
1283 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x1a, 0x00, 0x03, 0x00, 0x7f,
1284 0x00, 0x07, 0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1285 0x00, 0xf8, 0x00, 0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5},
1286 {
1287 122, 5610, 0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, 0x0c, 0x01,
1288 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x19, 0x00, 0x03, 0x00, 0x7f,
1289 0x00, 0x07, 0x00, 0xf8, 0x00, 0x19, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1290 0x00, 0xf8, 0x00, 0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4},
1291 {
1292 124, 5620, 0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, 0x0c, 0x01,
1293 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x19, 0x00, 0x03, 0x00, 0x7f,
1294 0x00, 0x07, 0x00, 0xf8, 0x00, 0x19, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1295 0x00, 0xf8, 0x00, 0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3},
1296 {
1297 126, 5630, 0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, 0x0c, 0x01,
1298 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x09, 0x00, 0x03, 0x00, 0x7f,
1299 0x00, 0x07, 0x00, 0xf8, 0x00, 0x09, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1300 0x00, 0xf8, 0x00, 0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2},
1301 {
1302 128, 5640, 0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, 0x0c, 0x01,
1303 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x09, 0x00, 0x03, 0x00, 0x7f,
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1305 0x00, 0xf8, 0x00, 0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2},
1306 {
1307 130, 5650, 0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, 0x0c, 0x01,
1308 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f,
1309 0x00, 0x07, 0x00, 0xf8, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1310 0x00, 0xf8, 0x00, 0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1},
1311 {
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1313 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f,
1314 0x00, 0x07, 0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1315 0x00, 0xf6, 0x00, 0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0},
1316 {
1317 134, 5670, 0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, 0x0c, 0x01,
1318 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f,
1319 0x00, 0x07, 0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1320 0x00, 0xf6, 0x00, 0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf},
1321 {
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1323 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f,
1324 0x00, 0x07, 0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1325 0x00, 0xf6, 0x00, 0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce},
1326 {
1327 138, 5690, 0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, 0x0c, 0x01,
1328 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x07, 0x00, 0x03, 0x00, 0x7f,
1329 0x00, 0x07, 0x00, 0xf6, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
1330 0x00, 0xf6, 0x00, 0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce},
1331 {
1332 140, 5700, 0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, 0x0c, 0x01,
1333 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x07, 0x00, 0x02, 0x00, 0x7f,
1334 0x00, 0x06, 0x00, 0xf6, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1335 0x00, 0xf6, 0x00, 0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd},
1336 {
1337 142, 5710, 0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, 0x0c, 0x01,
1338 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x07, 0x00, 0x02, 0x00, 0x7f,
1339 0x00, 0x06, 0x00, 0xf4, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1340 0x00, 0xf4, 0x00, 0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc},
1341 {
1342 144, 5720, 0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, 0x0c, 0x01,
1343 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x07, 0x00, 0x02, 0x00, 0x7f,
1344 0x00, 0x06, 0x00, 0xf4, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1345 0x00, 0xf4, 0x00, 0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb},
1346 {
1347 145, 5725, 0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, 0x10, 0x01,
1348 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f,
1349 0x00, 0x06, 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1350 0x00, 0xf4, 0x00, 0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb},
1351 {
1352 146, 5730, 0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, 0x0c, 0x01,
1353 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f,
1354 0x00, 0x06, 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1355 0x00, 0xf4, 0x00, 0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca},
1356 {
1357 147, 5735, 0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, 0x10, 0x01,
1358 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f,
1359 0x00, 0x06, 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1360 0x00, 0xf4, 0x00, 0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca},
1361 {
1362 148, 5740, 0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, 0x0c, 0x01,
1363 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f,
1364 0x00, 0x06, 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1365 0x00, 0xf4, 0x00, 0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9},
1366 {
1367 149, 5745, 0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, 0x10, 0x01,
1368 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f,
1369 0x00, 0x06, 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1370 0x00, 0xf4, 0x00, 0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9},
1371 {
1372 150, 5750, 0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, 0x0c, 0x01,
1373 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f,
1374 0x00, 0x06, 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1375 0x00, 0xf4, 0x00, 0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9},
1376 {
1377 151, 5755, 0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, 0x10, 0x01,
1378 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f,
1379 0x00, 0x06, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1380 0x00, 0xf4, 0x00, 0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8},
1381 {
1382 152, 5760, 0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, 0x0c, 0x01,
1383 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f,
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1385 0x00, 0xf4, 0x00, 0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8},
1386 {
1387 153, 5765, 0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, 0x10, 0x01,
1388 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f,
1389 0x00, 0x06, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1390 0x00, 0xf4, 0x00, 0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8},
1391 {
1392 154, 5770, 0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, 0x0c, 0x01,
1393 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f,
1394 0x00, 0x06, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1395 0x00, 0xf4, 0x00, 0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7},
1396 {
1397 155, 5775, 0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, 0x10, 0x01,
1398 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f,
1399 0x00, 0x06, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1400 0x00, 0xf4, 0x00, 0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7},
1401 {
1402 156, 5780, 0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, 0x0c, 0x01,
1403 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f,
1404 0x00, 0x06, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1405 0x00, 0xf4, 0x00, 0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6},
1406 {
1407 157, 5785, 0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, 0x10, 0x01,
1408 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x02, 0x00, 0x7f,
1409 0x00, 0x06, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1410 0x00, 0xf4, 0x00, 0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6},
1411 {
1412 158, 5790, 0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, 0x0c, 0x01,
1413 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x02, 0x00, 0x7f,
1414 0x00, 0x06, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1415 0x00, 0xf4, 0x00, 0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6},
1416 {
1417 159, 5795, 0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, 0x10, 0x01,
1418 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x02, 0x00, 0x7f,
1419 0x00, 0x06, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
1420 0x00, 0xf4, 0x00, 0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5},
1421 {
1422 160, 5800, 0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, 0x0c, 0x01,
1423 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f,
1424 0x00, 0x06, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1425 0x00, 0xf4, 0x00, 0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5},
1426 {
1427 161, 5805, 0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, 0x10, 0x01,
1428 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f,
1429 0x00, 0x06, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1430 0x00, 0xf4, 0x00, 0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4},
1431 {
1432 162, 5810, 0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, 0x0c, 0x01,
1433 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f,
1434 0x00, 0x06, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1435 0x00, 0xf4, 0x00, 0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4},
1436 {
1437 163, 5815, 0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, 0x10, 0x01,
1438 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f,
1439 0x00, 0x06, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1440 0x00, 0xf4, 0x00, 0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4},
1441 {
1442 164, 5820, 0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, 0x0c, 0x01,
1443 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
1444 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1445 0x00, 0xf4, 0x00, 0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3},
1446 {
1447 165, 5825, 0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, 0x10, 0x01,
1448 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
1449 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1450 0x00, 0xf4, 0x00, 0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3},
1451 {
1452 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, 0x0c, 0x01,
1453 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
1454 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1455 0x00, 0xf4, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
1456 {
1457 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, 0x0c, 0x01,
1458 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
1459 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1460 0x00, 0xf4, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
1461 {
1462 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, 0x0c, 0x01,
1463 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
1464 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1465 0x00, 0xf4, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
1466 {
1467 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, 0x0c, 0x01,
1468 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
1469 0x00, 0x06, 0x00, 0xf2, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1470 0x00, 0xf2, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
1471 {
1472 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, 0x0c, 0x01,
1473 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f,
1474 0x00, 0x06, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1475 0x00, 0xf2, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
1476 {
1477 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
1478 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f,
1479 0x00, 0x06, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1480 0x00, 0xf2, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
1481 {
1482 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
1483 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f,
1484 0x00, 0x06, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
1485 0x00, 0xf2, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
1486 {
1487 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
1488 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
1489 0x00, 0x05, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05,
1490 0x00, 0xf2, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
1491 {
1492 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
1493 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f,
1494 0x00, 0x05, 0x00, 0xf2, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05,
1495 0x00, 0xf2, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
1496 {
1497 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
1498 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x05, 0x00,
1499 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
1500 0x0f, 0x00, 0x0f, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
1501 {
1502 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
1503 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x05, 0x00,
1504 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
1505 0x0f, 0x00, 0x0f, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
1506 {
1507 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
1508 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x05, 0x00,
1509 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
1510 0x0f, 0x00, 0x0f, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
1511 {
1512 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
1513 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x05, 0x00,
1514 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xfd, 0x00, 0x05, 0x00, 0x70, 0x00,
1515 0x0f, 0x00, 0x0f, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
1516 {
1517 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
1518 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfb, 0x00, 0x05, 0x00,
1519 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xfb, 0x00, 0x05, 0x00, 0x70, 0x00,
1520 0x0f, 0x00, 0x0f, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
1521 {
1522 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
1523 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x05, 0x00,
1524 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xfa, 0x00, 0x05, 0x00, 0x70, 0x00,
1525 0x0f, 0x00, 0x0f, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
1526 {
1527 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
1528 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x05, 0x00,
1529 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xf8, 0x00, 0x05, 0x00, 0x70, 0x00,
1530 0x0f, 0x00, 0x0f, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
1531 {
1532 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
1533 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf7, 0x00, 0x05, 0x00,
1534 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xf7, 0x00, 0x05, 0x00, 0x70, 0x00,
1535 0x0f, 0x00, 0x0f, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
1536 {
1537 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
1538 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf6, 0x00, 0x05, 0x00,
1539 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xf6, 0x00, 0x05, 0x00, 0x70, 0x00,
1540 0x0f, 0x00, 0x0f, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
1541 {
1542 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
1543 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x05, 0x00,
1544 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf5, 0x00, 0x05, 0x00, 0x70, 0x00,
1545 0x0f, 0x00, 0x0d, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
1546 {
1547 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
1548 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf4, 0x00, 0x05, 0x00,
1549 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x70, 0x00,
1550 0x0f, 0x00, 0x0d, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
1551 {
1552 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
1553 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x05, 0x00,
1554 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf3, 0x00, 0x05, 0x00, 0x70, 0x00,
1555 0x0f, 0x00, 0x0d, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
1556 {
1557 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
1558 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf2, 0x00, 0x05, 0x00,
1559 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x70, 0x00,
1560 0x0f, 0x00, 0x0d, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
1561 {
1562 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
1563 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x05, 0x00,
1564 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf0, 0x00, 0x05, 0x00, 0x70, 0x00,
1565 0x0f, 0x00, 0x0d, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
1566};
1567
1568static const struct chan_info_nphy_radio205x chan_info_nphyrev4_2056_A1[] = {
1569 {
1570 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
1571 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
1572 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
1573 0x00, 0xff, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
1574 {
1575 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
1576 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
1577 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
1578 0x00, 0xff, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
1579 {
1580 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
1581 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
1582 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
1583 0x00, 0xff, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
1584 {
1585 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
1586 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
1587 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
1588 0x00, 0xff, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
1589 {
1590 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
1591 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
1592 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
1593 0x00, 0xff, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
1594 {
1595 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
1596 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
1597 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
1598 0x00, 0xff, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
1599 {
1600 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
1601 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
1602 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
1603 0x00, 0xff, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
1604 {
1605 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
1606 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
1607 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
1608 0x00, 0xff, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
1609 {
1610 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
1611 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1612 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1613 0x00, 0xff, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
1614 {
1615 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
1616 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1617 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1618 0x00, 0xff, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
1619 {
1620 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
1621 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1622 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1623 0x00, 0xff, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
1624 {
1625 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
1626 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1627 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1628 0x00, 0xff, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
1629 {
1630 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
1631 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1632 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1633 0x00, 0xff, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
1634 {
1635 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
1636 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1637 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1638 0x00, 0xff, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
1639 {
1640 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
1641 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1642 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1643 0x00, 0xff, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
1644 {
1645 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
1646 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1647 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1648 0x00, 0xff, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
1649 {
1650 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
1651 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1652 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1653 0x00, 0xff, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
1654 {
1655 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
1656 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
1657 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
1658 0x00, 0xff, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
1659 {
1660 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
1661 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f,
1662 0x00, 0x0f, 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
1663 0x00, 0xfe, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
1664 {
1665 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
1666 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f,
1667 0x00, 0x0f, 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
1668 0x00, 0xfe, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
1669 {
1670 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
1671 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f,
1672 0x00, 0x0f, 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
1673 0x00, 0xfe, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
1674 {
1675 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
1676 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f,
1677 0x00, 0x0f, 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
1678 0x00, 0xfe, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
1679 {
1680 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
1681 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f,
1682 0x00, 0x0f, 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
1683 0x00, 0xfe, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
1684 {
1685 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
1686 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f,
1687 0x00, 0x0f, 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
1688 0x00, 0xfe, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
1689 {
1690 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
1691 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f,
1692 0x00, 0x0f, 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
1693 0x00, 0xfe, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
1694 {
1695 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, 0x0c, 0x01,
1696 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xef, 0x00, 0x0c, 0x00, 0x7f,
1697 0x00, 0x0f, 0x00, 0xfe, 0x00, 0xef, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
1698 0x00, 0xfe, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
1699 {
1700 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, 0x0c, 0x01,
1701 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xef, 0x00, 0x0c, 0x00, 0x7f,
1702 0x00, 0x0f, 0x00, 0xfe, 0x00, 0xef, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
1703 0x00, 0xfe, 0x00, 0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa},
1704 {
1705 40, 5200, 0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, 0x0c, 0x01,
1706 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xef, 0x00, 0x0a, 0x00, 0x7f,
1707 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xef, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1708 0x00, 0xfc, 0x00, 0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9},
1709 {
1710 42, 5210, 0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, 0x0c, 0x01,
1711 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f,
1712 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1713 0x00, 0xfc, 0x00, 0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8},
1714 {
1715 44, 5220, 0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, 0x0c, 0x01,
1716 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f,
1717 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1718 0x00, 0xfc, 0x00, 0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7},
1719 {
1720 46, 5230, 0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, 0x0c, 0x01,
1721 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f,
1722 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1723 0x00, 0xfc, 0x00, 0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6},
1724 {
1725 48, 5240, 0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, 0x0c, 0x01,
1726 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f,
1727 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1728 0x00, 0xfc, 0x00, 0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5},
1729 {
1730 50, 5250, 0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, 0x0c, 0x01,
1731 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f,
1732 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1733 0x00, 0xfc, 0x00, 0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4},
1734 {
1735 52, 5260, 0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, 0x0c, 0x01,
1736 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f,
1737 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1738 0x00, 0xfc, 0x00, 0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3},
1739 {
1740 54, 5270, 0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, 0x0c, 0x01,
1741 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f,
1742 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1743 0x00, 0xfc, 0x00, 0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2},
1744 {
1745 56, 5280, 0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, 0x0c, 0x01,
1746 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, 0xff, 0xbf, 0x00, 0x0a, 0x00, 0x7f,
1747 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1748 0x00, 0xfc, 0x00, 0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1},
1749 {
1750 58, 5290, 0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, 0x0c, 0x01,
1751 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, 0xff, 0xbf, 0x00, 0x0a, 0x00, 0x7f,
1752 0x00, 0x0f, 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
1753 0x00, 0xfc, 0x00, 0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0},
1754 {
1755 60, 5300, 0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, 0x0c, 0x01,
1756 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f,
1757 0x00, 0x0f, 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
1758 0x00, 0xfa, 0x00, 0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0},
1759 {
1760 62, 5310, 0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, 0x0c, 0x01,
1761 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f,
1762 0x00, 0x0f, 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
1763 0x00, 0xfa, 0x00, 0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef},
1764 {
1765 64, 5320, 0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, 0x0c, 0x01,
1766 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f,
1767 0x00, 0x0f, 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
1768 0x00, 0xfa, 0x00, 0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee},
1769 {
1770 66, 5330, 0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, 0x0c, 0x01,
1771 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xaf, 0x00, 0x08, 0x00, 0x7f,
1772 0x00, 0x0f, 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
1773 0x00, 0xfa, 0x00, 0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed},
1774 {
1775 68, 5340, 0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, 0x0c, 0x01,
1776 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, 0xff, 0xaf, 0x00, 0x08, 0x00, 0x7f,
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1779 {
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1784 {
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1789 {
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1794 {
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1799 {
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1804 {
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1809 {
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1813 0x00, 0xf8, 0x00, 0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5},
1814 {
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1816 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, 0xc8, 0x8e, 0x00, 0x07, 0x00, 0x7f,
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1818 0x00, 0xf8, 0x00, 0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5},
1819 {
1820 86, 5430, 0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, 0x0c, 0x01,
1821 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, 0xc8, 0x8e, 0x00, 0x07, 0x00, 0x7f,
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1823 0x00, 0xf8, 0x00, 0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4},
1824 {
1825 88, 5440, 0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, 0x0c, 0x01,
1826 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x7e, 0x00, 0x07, 0x00, 0x7f,
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1828 0x00, 0xf8, 0x00, 0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3},
1829 {
1830 90, 5450, 0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, 0x0c, 0x01,
1831 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x7d, 0x00, 0x07, 0x00, 0x7f,
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1833 0x00, 0xf8, 0x00, 0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2},
1834 {
1835 92, 5460, 0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, 0x0c, 0x01,
1836 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x6d, 0x00, 0x07, 0x00, 0x7f,
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1838 0x00, 0xf8, 0x00, 0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1},
1839 {
1840 94, 5470, 0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, 0x0c, 0x01,
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1843 0x00, 0xf8, 0x00, 0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0},
1844 {
1845 96, 5480, 0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, 0x0c, 0x01,
1846 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x5d, 0x00, 0x07, 0x00, 0x7f,
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1848 0x00, 0xf8, 0x00, 0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df},
1849 {
1850 98, 5490, 0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, 0x0c, 0x01,
1851 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, 0xc8, 0x5c, 0x00, 0x07, 0x00, 0x7f,
1852 0x00, 0x0f, 0x00, 0xf8, 0x00, 0x5c, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
1853 0x00, 0xf8, 0x00, 0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de},
1854 {
1855 100, 5500, 0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, 0x0c, 0x01,
1856 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x5c, 0x00, 0x06, 0x00, 0x7f,
1857 0x00, 0x0d, 0x00, 0xf6, 0x00, 0x5c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
1858 0x00, 0xf6, 0x00, 0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd},
1859 {
1860 102, 5510, 0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, 0x0c, 0x01,
1861 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x4c, 0x00, 0x06, 0x00, 0x7f,
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1863 0x00, 0xf6, 0x00, 0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd},
1864 {
1865 104, 5520, 0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, 0x0c, 0x01,
1866 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x4c, 0x00, 0x06, 0x00, 0x7f,
1867 0x00, 0x0d, 0x00, 0xf6, 0x00, 0x4c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
1868 0x00, 0xf6, 0x00, 0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc},
1869 {
1870 106, 5530, 0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, 0x0c, 0x01,
1871 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f,
1872 0x00, 0x0d, 0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
1873 0x00, 0xf6, 0x00, 0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db},
1874 {
1875 108, 5540, 0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, 0x0c, 0x01,
1876 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f,
1877 0x00, 0x0d, 0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
1878 0x00, 0xf6, 0x00, 0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da},
1879 {
1880 110, 5550, 0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, 0x0c, 0x01,
1881 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f,
1882 0x00, 0x0d, 0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
1883 0x00, 0xf6, 0x00, 0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9},
1884 {
1885 112, 5560, 0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, 0x0c, 0x01,
1886 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x2b, 0x00, 0x06, 0x00, 0x7f,
1887 0x00, 0x0d, 0x00, 0xf6, 0x00, 0x2b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
1888 0x00, 0xf6, 0x00, 0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8},
1889 {
1890 114, 5570, 0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, 0x0c, 0x01,
1891 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x2a, 0x00, 0x06, 0x00, 0x7f,
1892 0x00, 0x0d, 0x00, 0xf6, 0x00, 0x2a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
1893 0x00, 0xf6, 0x00, 0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7},
1894 {
1895 116, 5580, 0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, 0x0c, 0x01,
1896 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x1a, 0x00, 0x06, 0x00, 0x7f,
1897 0x00, 0x0d, 0x00, 0xf6, 0x00, 0x1a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
1898 0x00, 0xf6, 0x00, 0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7},
1899 {
1900 118, 5590, 0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, 0x0c, 0x01,
1901 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, 0x84, 0x1a, 0x00, 0x06, 0x00, 0x7f,
1902 0x00, 0x0d, 0x00, 0xf6, 0x00, 0x1a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
1903 0x00, 0xf6, 0x00, 0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6},
1904 {
1905 120, 5600, 0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, 0x0c, 0x01,
1906 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x1a, 0x00, 0x04, 0x00, 0x7f,
1907 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x1a, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1908 0x00, 0xf4, 0x00, 0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5},
1909 {
1910 122, 5610, 0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, 0x0c, 0x01,
1911 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x19, 0x00, 0x04, 0x00, 0x7f,
1912 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x19, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1913 0x00, 0xf4, 0x00, 0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4},
1914 {
1915 124, 5620, 0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, 0x0c, 0x01,
1916 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x19, 0x00, 0x04, 0x00, 0x7f,
1917 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x19, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1918 0x00, 0xf4, 0x00, 0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3},
1919 {
1920 126, 5630, 0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, 0x0c, 0x01,
1921 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x09, 0x00, 0x04, 0x00, 0x7f,
1922 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x09, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1923 0x00, 0xf4, 0x00, 0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2},
1924 {
1925 128, 5640, 0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, 0x0c, 0x01,
1926 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x09, 0x00, 0x04, 0x00, 0x7f,
1927 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x09, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1928 0x00, 0xf4, 0x00, 0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2},
1929 {
1930 130, 5650, 0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, 0x0c, 0x01,
1931 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f,
1932 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1933 0x00, 0xf4, 0x00, 0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1},
1934 {
1935 132, 5660, 0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, 0x0c, 0x01,
1936 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f,
1937 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1938 0x00, 0xf4, 0x00, 0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0},
1939 {
1940 134, 5670, 0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, 0x0c, 0x01,
1941 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f,
1942 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1943 0x00, 0xf4, 0x00, 0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf},
1944 {
1945 136, 5680, 0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, 0x0c, 0x01,
1946 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f,
1947 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1948 0x00, 0xf4, 0x00, 0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce},
1949 {
1950 138, 5690, 0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, 0x0c, 0x01,
1951 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, 0x70, 0x07, 0x00, 0x04, 0x00, 0x7f,
1952 0x00, 0x0b, 0x00, 0xf4, 0x00, 0x07, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
1953 0x00, 0xf4, 0x00, 0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce},
1954 {
1955 140, 5700, 0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, 0x0c, 0x01,
1956 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x07, 0x00, 0x03, 0x00, 0x7f,
1957 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
1958 0x00, 0xf2, 0x00, 0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd},
1959 {
1960 142, 5710, 0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, 0x0c, 0x01,
1961 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x07, 0x00, 0x03, 0x00, 0x7f,
1962 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
1963 0x00, 0xf2, 0x00, 0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc},
1964 {
1965 144, 5720, 0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, 0x0c, 0x01,
1966 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x07, 0x00, 0x03, 0x00, 0x7f,
1967 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
1968 0x00, 0xf2, 0x00, 0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb},
1969 {
1970 145, 5725, 0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, 0x10, 0x01,
1971 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f,
1972 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
1973 0x00, 0xf2, 0x00, 0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb},
1974 {
1975 146, 5730, 0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, 0x0c, 0x01,
1976 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f,
1977 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
1978 0x00, 0xf2, 0x00, 0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca},
1979 {
1980 147, 5735, 0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, 0x10, 0x01,
1981 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f,
1982 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
1983 0x00, 0xf2, 0x00, 0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca},
1984 {
1985 148, 5740, 0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, 0x0c, 0x01,
1986 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f,
1987 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
1988 0x00, 0xf2, 0x00, 0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9},
1989 {
1990 149, 5745, 0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, 0x10, 0x01,
1991 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f,
1992 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
1993 0x00, 0xf2, 0x00, 0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9},
1994 {
1995 150, 5750, 0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, 0x0c, 0x01,
1996 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f,
1997 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
1998 0x00, 0xf2, 0x00, 0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9},
1999 {
2000 151, 5755, 0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, 0x10, 0x01,
2001 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f,
2002 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
2003 0x00, 0xf2, 0x00, 0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8},
2004 {
2005 152, 5760, 0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, 0x0c, 0x01,
2006 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f,
2007 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
2008 0x00, 0xf2, 0x00, 0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8},
2009 {
2010 153, 5765, 0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, 0x10, 0x01,
2011 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f,
2012 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
2013 0x00, 0xf2, 0x00, 0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8},
2014 {
2015 154, 5770, 0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, 0x0c, 0x01,
2016 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f,
2017 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
2018 0x00, 0xf2, 0x00, 0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7},
2019 {
2020 155, 5775, 0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, 0x10, 0x01,
2021 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f,
2022 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
2023 0x00, 0xf2, 0x00, 0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7},
2024 {
2025 156, 5780, 0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, 0x0c, 0x01,
2026 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f,
2027 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
2028 0x00, 0xf2, 0x00, 0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6},
2029 {
2030 157, 5785, 0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, 0x10, 0x01,
2031 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f,
2032 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
2033 0x00, 0xf2, 0x00, 0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6},
2034 {
2035 158, 5790, 0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, 0x0c, 0x01,
2036 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f,
2037 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
2038 0x00, 0xf2, 0x00, 0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6},
2039 {
2040 159, 5795, 0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, 0x10, 0x01,
2041 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f,
2042 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
2043 0x00, 0xf2, 0x00, 0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5},
2044 {
2045 160, 5800, 0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, 0x0c, 0x01,
2046 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
2047 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2048 0x00, 0xf0, 0x00, 0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5},
2049 {
2050 161, 5805, 0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, 0x10, 0x01,
2051 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
2052 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2053 0x00, 0xf0, 0x00, 0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4},
2054 {
2055 162, 5810, 0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, 0x0c, 0x01,
2056 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
2057 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2058 0x00, 0xf0, 0x00, 0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4},
2059 {
2060 163, 5815, 0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, 0x10, 0x01,
2061 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
2062 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2063 0x00, 0xf0, 0x00, 0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4},
2064 {
2065 164, 5820, 0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, 0x0c, 0x01,
2066 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
2067 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2068 0x00, 0xf0, 0x00, 0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3},
2069 {
2070 165, 5825, 0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, 0x10, 0x01,
2071 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
2072 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2073 0x00, 0xf0, 0x00, 0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3},
2074 {
2075 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, 0x0c, 0x01,
2076 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
2077 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2078 0x00, 0xf0, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
2079 {
2080 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, 0x0c, 0x01,
2081 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
2082 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2083 0x00, 0xf0, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
2084 {
2085 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, 0x0c, 0x01,
2086 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
2087 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2088 0x00, 0xf0, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
2089 {
2090 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, 0x0c, 0x01,
2091 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
2092 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2093 0x00, 0xf0, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
2094 {
2095 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, 0x0c, 0x01,
2096 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f,
2097 0x00, 0x09, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2098 0x00, 0xf0, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
2099 {
2100 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
2101 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f,
2102 0x00, 0x09, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2103 0x00, 0xf0, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
2104 {
2105 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
2106 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f,
2107 0x00, 0x09, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
2108 0x00, 0xf0, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
2109 {
2110 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
2111 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
2112 0x00, 0x07, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07,
2113 0x00, 0xf0, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
2114 {
2115 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
2116 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f,
2117 0x00, 0x07, 0x00, 0xf0, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07,
2118 0x00, 0xf0, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
2119 {
2120 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
2121 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x04, 0x00,
2122 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
2123 0x0f, 0x00, 0x0e, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
2124 {
2125 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
2126 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x04, 0x00,
2127 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
2128 0x0f, 0x00, 0x0e, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
2129 {
2130 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
2131 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x04, 0x00,
2132 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
2133 0x0f, 0x00, 0x0e, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
2134 {
2135 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
2136 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x04, 0x00,
2137 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xfd, 0x00, 0x04, 0x00, 0x70, 0x00,
2138 0x0f, 0x00, 0x0e, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
2139 {
2140 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
2141 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfb, 0x00, 0x04, 0x00,
2142 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xfb, 0x00, 0x04, 0x00, 0x70, 0x00,
2143 0x0f, 0x00, 0x0e, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
2144 {
2145 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
2146 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00,
2147 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xfa, 0x00, 0x04, 0x00, 0x70, 0x00,
2148 0x0f, 0x00, 0x0e, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
2149 {
2150 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
2151 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x04, 0x00,
2152 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf8, 0x00, 0x04, 0x00, 0x70, 0x00,
2153 0x0f, 0x00, 0x0e, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
2154 {
2155 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
2156 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf7, 0x00, 0x04, 0x00,
2157 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf7, 0x00, 0x04, 0x00, 0x70, 0x00,
2158 0x0f, 0x00, 0x0e, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
2159 {
2160 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
2161 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf6, 0x00, 0x04, 0x00,
2162 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf6, 0x00, 0x04, 0x00, 0x70, 0x00,
2163 0x0f, 0x00, 0x0e, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
2164 {
2165 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
2166 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x04, 0x00,
2167 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf5, 0x00, 0x04, 0x00, 0x70, 0x00,
2168 0x0f, 0x00, 0x0e, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
2169 {
2170 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
2171 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf4, 0x00, 0x04, 0x00,
2172 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x70, 0x00,
2173 0x0f, 0x00, 0x0e, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
2174 {
2175 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
2176 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x04, 0x00,
2177 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf3, 0x00, 0x04, 0x00, 0x70, 0x00,
2178 0x0f, 0x00, 0x0e, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
2179 {
2180 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
2181 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf2, 0x00, 0x04, 0x00,
2182 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x70, 0x00,
2183 0x0f, 0x00, 0x0e, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
2184 {
2185 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
2186 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x04, 0x00,
2187 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x70, 0x00,
2188 0x0f, 0x00, 0x0e, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
2189};
2190
2191static const struct chan_info_nphy_radio205x chan_info_nphyrev5_2056v5[] = {
2192 {
2193 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
2194 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
2195 0x00, 0x0f, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f,
2196 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
2197 {
2198 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
2199 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
2200 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
2201 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
2202 {
2203 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
2204 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
2205 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
2206 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
2207 {
2208 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
2209 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
2210 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
2211 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
2212 {
2213 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
2214 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
2215 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e,
2216 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
2217 {
2218 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
2219 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
2220 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
2221 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
2222 {
2223 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
2224 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
2225 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
2226 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
2227 {
2228 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
2229 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
2230 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
2231 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
2232 {
2233 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
2234 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
2235 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
2236 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
2237 {
2238 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
2239 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
2240 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
2241 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
2242 {
2243 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
2244 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x09, 0x00, 0x70,
2245 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d,
2246 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
2247 {
2248 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
2249 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x09, 0x00, 0x70,
2250 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
2251 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
2252 {
2253 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
2254 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70,
2255 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
2256 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
2257 {
2258 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
2259 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70,
2260 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
2261 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
2262 {
2263 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
2264 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x70,
2265 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
2266 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
2267 {
2268 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
2269 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x70,
2270 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
2271 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
2272 {
2273 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
2274 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
2275 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
2276 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
2277 {
2278 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
2279 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
2280 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
2281 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
2282 {
2283 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
2284 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
2285 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
2286 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
2287 {
2288 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
2289 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
2290 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
2291 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
2292 {
2293 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
2294 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
2295 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
2296 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
2297 {
2298 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
2299 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x70,
2300 0x00, 0x0a, 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0a,
2301 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
2302 {
2303 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
2304 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70,
2305 0x00, 0x0a, 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x0a,
2306 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
2307 {
2308 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
2309 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70,
2310 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x09,
2311 0x00, 0x6e, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
2312 {
2313 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
2314 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x06, 0x00, 0x70,
2315 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
2316 0x00, 0x6e, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
2317 {
2318 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, 0x0c, 0x01,
2319 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
2320 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
2321 0x00, 0x6e, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
2322 {
2323 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, 0x0c, 0x01,
2324 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
2325 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
2326 0x00, 0x6e, 0x00, 0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa},
2327 {
2328 40, 5200, 0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, 0x0c, 0x01,
2329 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
2330 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
2331 0x00, 0x6e, 0x00, 0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9},
2332 {
2333 42, 5210, 0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, 0x0c, 0x01,
2334 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
2335 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
2336 0x00, 0x6e, 0x00, 0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8},
2337 {
2338 44, 5220, 0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, 0x0c, 0x01,
2339 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
2340 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
2341 0x00, 0x6e, 0x00, 0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7},
2342 {
2343 46, 5230, 0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, 0x0c, 0x01,
2344 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xea, 0x00, 0x06, 0x00, 0x70,
2345 0x00, 0x08, 0x00, 0x9e, 0x00, 0xea, 0x00, 0x06, 0x00, 0x70, 0x00, 0x08,
2346 0x00, 0x6e, 0x00, 0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6},
2347 {
2348 48, 5240, 0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, 0x0c, 0x01,
2349 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xe9, 0x00, 0x05, 0x00, 0x70,
2350 0x00, 0x08, 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
2351 0x00, 0x6d, 0x00, 0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5},
2352 {
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2542 {
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2732 {
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2736 0x00, 0x71, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
2737 {
2738 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
2739 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2740 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
2741 0x00, 0x71, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
2742 {
2743 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
2744 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x03, 0x00,
2745 0x70, 0x00, 0x0f, 0x00, 0x0b, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00,
2746 0x0f, 0x00, 0x0b, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
2747 {
2748 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
2749 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x03, 0x00,
2750 0x70, 0x00, 0x0f, 0x00, 0x0a, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00,
2751 0x0f, 0x00, 0x0a, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
2752 {
2753 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
2754 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x03, 0x00,
2755 0x70, 0x00, 0x0f, 0x00, 0x0a, 0x00, 0x0e, 0x00, 0x03, 0x00, 0x70, 0x00,
2756 0x0f, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
2757 {
2758 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
2759 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x03, 0x00,
2760 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x03, 0x00, 0x70, 0x00,
2761 0x0e, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
2762 {
2763 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
2764 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x03, 0x00,
2765 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x0c, 0x00, 0x03, 0x00, 0x70, 0x00,
2766 0x0e, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
2767 {
2768 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
2769 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x03, 0x00,
2770 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x0b, 0x00, 0x03, 0x00, 0x70, 0x00,
2771 0x0e, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
2772 {
2773 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
2774 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00,
2775 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x03, 0x00, 0x70, 0x00,
2776 0x0e, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
2777 {
2778 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
2779 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x08, 0x00, 0x02, 0x00,
2780 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x08, 0x00, 0x02, 0x00, 0x70, 0x00,
2781 0x0e, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
2782 {
2783 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
2784 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x07, 0x00, 0x02, 0x00,
2785 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x07, 0x00, 0x02, 0x00, 0x70, 0x00,
2786 0x0e, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
2787 {
2788 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
2789 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x06, 0x00, 0x02, 0x00,
2790 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x06, 0x00, 0x02, 0x00, 0x70, 0x00,
2791 0x0d, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
2792 {
2793 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
2794 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x05, 0x00, 0x02, 0x00,
2795 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x05, 0x00, 0x02, 0x00, 0x70, 0x00,
2796 0x0d, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
2797 {
2798 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
2799 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x04, 0x00, 0x02, 0x00,
2800 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x04, 0x00, 0x02, 0x00, 0x70, 0x00,
2801 0x0d, 0x00, 0x08, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
2802 {
2803 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
2804 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x03, 0x00, 0x02, 0x00,
2805 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0x70, 0x00,
2806 0x0d, 0x00, 0x08, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
2807 {
2808 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
2809 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
2810 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
2811 0x0d, 0x00, 0x08, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
2812};
2813
2814static const struct chan_info_nphy_radio205x chan_info_nphyrev6_2056v6[] = {
2815 {
2816 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
2817 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2818 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2819 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
2820 {
2821 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
2822 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2823 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2824 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
2825 {
2826 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
2827 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2828 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2829 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
2830 {
2831 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
2832 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2833 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2834 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
2835 {
2836 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
2837 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2838 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2839 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
2840 {
2841 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
2842 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2843 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2844 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
2845 {
2846 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
2847 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2848 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2849 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
2850 {
2851 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
2852 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2853 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2854 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
2855 {
2856 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
2857 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2858 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2859 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
2860 {
2861 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
2862 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2863 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2864 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
2865 {
2866 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
2867 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2868 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2869 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
2870 {
2871 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
2872 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2873 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2874 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
2875 {
2876 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
2877 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2878 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2879 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
2880 {
2881 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
2882 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2883 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2884 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
2885 {
2886 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
2887 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
2888 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2889 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
2890 {
2891 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
2892 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
2893 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2894 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
2895 {
2896 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
2897 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
2898 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2899 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
2900 {
2901 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
2902 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
2903 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
2904 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
2905 {
2906 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
2907 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77,
2908 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
2909 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
2910 {
2911 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
2912 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
2913 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
2914 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
2915 {
2916 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
2917 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
2918 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
2919 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
2920 {
2921 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
2922 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
2923 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
2924 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
2925 {
2926 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
2927 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77,
2928 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
2929 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
2930 {
2931 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
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3060 {
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3070 {
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3075 {
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3080 {
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3085 {
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3090 {
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3095 {
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3100 {
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3105 {
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3110 {
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3115 {
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3120 {
3121 108, 5540, 0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, 0x0c, 0x01,
3122 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, 0x71, 0x73, 0x00, 0x00, 0x00, 0x77,
3123 0x00, 0x09, 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
3124 0x00, 0x6f, 0x00, 0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da},
3125 {
3126 110, 5550, 0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, 0x0c, 0x01,
3127 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0x77,
3128 0x00, 0x09, 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
3129 0x00, 0x6f, 0x00, 0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9},
3130 {
3131 112, 5560, 0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, 0x0c, 0x01,
3132 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0x77,
3133 0x00, 0x09, 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
3134 0x00, 0x6f, 0x00, 0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8},
3135 {
3136 114, 5570, 0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, 0x0c, 0x01,
3137 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, 0x61, 0x62, 0x00, 0x00, 0x00, 0x77,
3138 0x00, 0x09, 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
3139 0x00, 0x6f, 0x00, 0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7},
3140 {
3141 116, 5580, 0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, 0x0c, 0x01,
3142 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, 0x60, 0x62, 0x00, 0x00, 0x00, 0x77,
3143 0x00, 0x08, 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
3144 0x00, 0x6f, 0x00, 0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7},
3145 {
3146 118, 5590, 0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, 0x0c, 0x01,
3147 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, 0x50, 0x61, 0x00, 0x00, 0x00, 0x77,
3148 0x00, 0x08, 0x00, 0x6f, 0x00, 0x61, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
3149 0x00, 0x6f, 0x00, 0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6},
3150 {
3151 120, 5600, 0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, 0x0c, 0x01,
3152 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, 0x50, 0x51, 0x00, 0x00, 0x00, 0x77,
3153 0x00, 0x08, 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
3154 0x00, 0x6f, 0x00, 0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5},
3155 {
3156 122, 5610, 0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, 0x0c, 0x01,
3157 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, 0x50, 0x51, 0x00, 0x00, 0x00, 0x77,
3158 0x00, 0x08, 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
3159 0x00, 0x6f, 0x00, 0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4},
3160 {
3161 124, 5620, 0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, 0x0c, 0x01,
3162 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, 0x50, 0x50, 0x00, 0x00, 0x00, 0x77,
3163 0x00, 0x07, 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
3164 0x00, 0x6f, 0x00, 0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3},
3165 {
3166 126, 5630, 0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, 0x0c, 0x01,
3167 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, 0x50, 0x50, 0x00, 0x00, 0x00, 0x77,
3168 0x00, 0x07, 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
3169 0x00, 0x6f, 0x00, 0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2},
3170 {
3171 128, 5640, 0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, 0x0c, 0x01,
3172 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, 0x40, 0x50, 0x00, 0x00, 0x00, 0x77,
3173 0x00, 0x07, 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
3174 0x00, 0x6f, 0x00, 0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2},
3175 {
3176 130, 5650, 0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, 0x0c, 0x01,
3177 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00, 0x77,
3178 0x00, 0x07, 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
3179 0x00, 0x6f, 0x00, 0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1},
3180 {
3181 132, 5660, 0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, 0x0c, 0x01,
3182 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00, 0x77,
3183 0x00, 0x06, 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3184 0x00, 0x6f, 0x00, 0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0},
3185 {
3186 134, 5670, 0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, 0x0c, 0x01,
3187 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, 0x40, 0x30, 0x00, 0x00, 0x00, 0x77,
3188 0x00, 0x06, 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3189 0x00, 0x6f, 0x00, 0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf},
3190 {
3191 136, 5680, 0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, 0x0c, 0x01,
3192 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x77,
3193 0x00, 0x06, 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3194 0x00, 0x6f, 0x00, 0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce},
3195 {
3196 138, 5690, 0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, 0x0c, 0x01,
3197 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x77,
3198 0x00, 0x06, 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3199 0x00, 0x6f, 0x00, 0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce},
3200 {
3201 140, 5700, 0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, 0x0c, 0x01,
3202 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x77,
3203 0x00, 0x06, 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3204 0x00, 0x6e, 0x00, 0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd},
3205 {
3206 142, 5710, 0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, 0x0c, 0x01,
3207 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x77,
3208 0x00, 0x06, 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3209 0x00, 0x6e, 0x00, 0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc},
3210 {
3211 144, 5720, 0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, 0x0c, 0x01,
3212 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x77,
3213 0x00, 0x06, 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3214 0x00, 0x6e, 0x00, 0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb},
3215 {
3216 145, 5725, 0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, 0x10, 0x01,
3217 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x77,
3218 0x00, 0x06, 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3219 0x00, 0x6e, 0x00, 0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb},
3220 {
3221 146, 5730, 0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, 0x0c, 0x01,
3222 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, 0x20, 0x30, 0x00, 0x00, 0x00, 0x77,
3223 0x00, 0x06, 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3224 0x00, 0x6e, 0x00, 0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca},
3225 {
3226 147, 5735, 0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, 0x10, 0x01,
3227 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, 0x20, 0x30, 0x00, 0x00, 0x00, 0x77,
3228 0x00, 0x06, 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3229 0x00, 0x6d, 0x00, 0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca},
3230 {
3231 148, 5740, 0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, 0x0c, 0x01,
3232 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, 0x20, 0x30, 0x00, 0x00, 0x00, 0x77,
3233 0x00, 0x06, 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3234 0x00, 0x6d, 0x00, 0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9},
3235 {
3236 149, 5745, 0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, 0x10, 0x01,
3237 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, 0x20, 0x30, 0x00, 0x00, 0x00, 0x77,
3238 0x00, 0x06, 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
3239 0x00, 0x6d, 0x00, 0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9},
3240 {
3241 150, 5750, 0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, 0x0c, 0x01,
3242 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00, 0x77,
3243 0x00, 0x05, 0x00, 0x6d, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3244 0x00, 0x6d, 0x00, 0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9},
3245 {
3246 151, 5755, 0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, 0x10, 0x01,
3247 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x77,
3248 0x00, 0x05, 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3249 0x00, 0x6c, 0x00, 0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8},
3250 {
3251 152, 5760, 0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, 0x0c, 0x01,
3252 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x77,
3253 0x00, 0x05, 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3254 0x00, 0x6c, 0x00, 0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8},
3255 {
3256 153, 5765, 0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, 0x10, 0x01,
3257 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x77,
3258 0x00, 0x05, 0x00, 0x6c, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3259 0x00, 0x6c, 0x00, 0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8},
3260 {
3261 154, 5770, 0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, 0x0c, 0x01,
3262 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x77,
3263 0x00, 0x05, 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3264 0x00, 0x6b, 0x00, 0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7},
3265 {
3266 155, 5775, 0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, 0x10, 0x01,
3267 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x77,
3268 0x00, 0x05, 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3269 0x00, 0x6b, 0x00, 0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7},
3270 {
3271 156, 5780, 0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, 0x0c, 0x01,
3272 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x77,
3273 0x00, 0x05, 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3274 0x00, 0x6b, 0x00, 0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6},
3275 {
3276 157, 5785, 0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, 0x10, 0x01,
3277 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
3278 0x00, 0x05, 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3279 0x00, 0x6b, 0x00, 0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6},
3280 {
3281 158, 5790, 0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, 0x0c, 0x01,
3282 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
3283 0x00, 0x05, 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3284 0x00, 0x6b, 0x00, 0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6},
3285 {
3286 159, 5795, 0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, 0x10, 0x01,
3287 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3288 0x00, 0x05, 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3289 0x00, 0x6b, 0x00, 0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5},
3290 {
3291 160, 5800, 0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, 0x0c, 0x01,
3292 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3293 0x00, 0x05, 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3294 0x00, 0x6b, 0x00, 0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5},
3295 {
3296 161, 5805, 0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, 0x10, 0x01,
3297 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3298 0x00, 0x05, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3299 0x00, 0x6a, 0x00, 0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4},
3300 {
3301 162, 5810, 0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, 0x0c, 0x01,
3302 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3303 0x00, 0x05, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3304 0x00, 0x6a, 0x00, 0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4},
3305 {
3306 163, 5815, 0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, 0x10, 0x01,
3307 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3308 0x00, 0x05, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3309 0x00, 0x6a, 0x00, 0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4},
3310 {
3311 164, 5820, 0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, 0x0c, 0x01,
3312 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3313 0x00, 0x05, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3314 0x00, 0x6a, 0x00, 0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3},
3315 {
3316 165, 5825, 0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, 0x10, 0x01,
3317 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3318 0x00, 0x05, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3319 0x00, 0x69, 0x00, 0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3},
3320 {
3321 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, 0x0c, 0x01,
3322 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3323 0x00, 0x05, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
3324 0x00, 0x69, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
3325 {
3326 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, 0x0c, 0x01,
3327 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3328 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
3329 0x00, 0x69, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
3330 {
3331 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, 0x0c, 0x01,
3332 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3333 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
3334 0x00, 0x69, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
3335 {
3336 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, 0x0c, 0x01,
3337 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3338 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
3339 0x00, 0x69, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
3340 {
3341 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, 0x0c, 0x01,
3342 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3343 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
3344 0x00, 0x68, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
3345 {
3346 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
3347 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3348 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
3349 0x00, 0x68, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
3350 {
3351 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
3352 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3353 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
3354 0x00, 0x68, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
3355 {
3356 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
3357 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3358 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
3359 0x00, 0x68, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
3360 {
3361 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
3362 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
3363 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
3364 0x00, 0x68, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
3365 {
3366 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
3367 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
3368 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
3369 0x0b, 0x00, 0x0a, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
3370 {
3371 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
3372 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
3373 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
3374 0x0b, 0x00, 0x0a, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
3375 {
3376 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
3377 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x67, 0x00, 0x03, 0x00,
3378 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x67, 0x00, 0x03, 0x00, 0x70, 0x00,
3379 0x0b, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
3380 {
3381 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
3382 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x57, 0x00, 0x03, 0x00,
3383 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x57, 0x00, 0x03, 0x00, 0x70, 0x00,
3384 0x0a, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
3385 {
3386 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
3387 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x56, 0x00, 0x03, 0x00,
3388 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x56, 0x00, 0x03, 0x00, 0x70, 0x00,
3389 0x0a, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
3390 {
3391 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
3392 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x46, 0x00, 0x03, 0x00,
3393 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x46, 0x00, 0x03, 0x00, 0x70, 0x00,
3394 0x0a, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
3395 {
3396 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
3397 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x45, 0x00, 0x02, 0x00,
3398 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
3399 0x0a, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
3400 {
3401 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
3402 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x34, 0x00, 0x02, 0x00,
3403 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
3404 0x0a, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
3405 {
3406 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
3407 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x23, 0x00, 0x02, 0x00,
3408 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00,
3409 0x0a, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
3410 {
3411 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
3412 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x12, 0x00, 0x02, 0x00,
3413 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00,
3414 0x0a, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
3415 {
3416 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
3417 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00,
3418 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00,
3419 0x09, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
3420 {
3421 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
3422 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
3423 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
3424 0x09, 0x00, 0x09, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
3425 {
3426 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
3427 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
3428 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
3429 0x09, 0x00, 0x09, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
3430 {
3431 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
3432 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
3433 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
3434 0x09, 0x00, 0x09, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
3435};
3436
3437static const struct chan_info_nphy_radio205x chan_info_nphyrev5n6_2056v7[] = {
3438 {
3439 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
3440 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
3441 0x00, 0x0f, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f,
3442 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
3443 {
3444 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
3445 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
3446 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
3447 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
3448 {
3449 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
3450 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
3451 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
3452 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
3453 {
3454 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
3455 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
3456 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
3457 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
3458 {
3459 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
3460 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
3461 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e,
3462 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
3463 {
3464 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
3465 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
3466 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
3467 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
3468 {
3469 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
3470 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
3471 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
3472 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
3473 {
3474 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
3475 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
3476 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
3477 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
3478 {
3479 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
3480 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
3481 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
3482 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
3483 {
3484 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
3485 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
3486 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
3487 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
3488 {
3489 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
3490 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x09, 0x00, 0x70,
3491 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d,
3492 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
3493 {
3494 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
3495 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x09, 0x00, 0x70,
3496 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
3497 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
3498 {
3499 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
3500 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70,
3501 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
3502 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
3503 {
3504 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
3505 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70,
3506 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
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3588 {
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3593 {
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3598 {
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3618 {
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3623 {
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3628 {
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3638 {
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3653 {
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3658 {
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3663 {
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3668 {
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3673 {
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3678 {
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3683 {
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3688 {
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3693 {
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3889 155, 5775, 0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, 0x10, 0x01,
3890 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x70,
3891 0x00, 0x00, 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3892 0x00, 0x92, 0x00, 0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7},
3893 {
3894 156, 5780, 0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, 0x0c, 0x01,
3895 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x70,
3896 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3897 0x00, 0x92, 0x00, 0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6},
3898 {
3899 157, 5785, 0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, 0x10, 0x01,
3900 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3901 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3902 0x00, 0x92, 0x00, 0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6},
3903 {
3904 158, 5790, 0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, 0x0c, 0x01,
3905 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3906 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3907 0x00, 0x92, 0x00, 0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6},
3908 {
3909 159, 5795, 0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, 0x10, 0x01,
3910 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3911 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3912 0x00, 0x92, 0x00, 0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5},
3913 {
3914 160, 5800, 0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, 0x0c, 0x01,
3915 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3916 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3917 0x00, 0x92, 0x00, 0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5},
3918 {
3919 161, 5805, 0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, 0x10, 0x01,
3920 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3921 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3922 0x00, 0x92, 0x00, 0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4},
3923 {
3924 162, 5810, 0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, 0x0c, 0x01,
3925 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3926 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3927 0x00, 0x92, 0x00, 0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4},
3928 {
3929 163, 5815, 0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, 0x10, 0x01,
3930 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3931 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3932 0x00, 0x92, 0x00, 0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4},
3933 {
3934 164, 5820, 0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, 0x0c, 0x01,
3935 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3936 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3937 0x00, 0x92, 0x00, 0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3},
3938 {
3939 165, 5825, 0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, 0x10, 0x01,
3940 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3941 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3942 0x00, 0x92, 0x00, 0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3},
3943 {
3944 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, 0x0c, 0x01,
3945 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3946 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3947 0x00, 0x92, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
3948 {
3949 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, 0x0c, 0x01,
3950 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
3951 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3952 0x00, 0x92, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
3953 {
3954 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, 0x0c, 0x01,
3955 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
3956 0x00, 0x00, 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3957 0x00, 0x92, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
3958 {
3959 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, 0x0c, 0x01,
3960 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
3961 0x00, 0x00, 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3962 0x00, 0x92, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
3963 {
3964 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, 0x0c, 0x01,
3965 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
3966 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3967 0x00, 0x91, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
3968 {
3969 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
3970 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
3971 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3972 0x00, 0x91, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
3973 {
3974 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
3975 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
3976 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3977 0x00, 0x91, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
3978 {
3979 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
3980 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
3981 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3982 0x00, 0x91, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
3983 {
3984 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
3985 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
3986 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
3987 0x00, 0x91, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
3988 {
3989 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
3990 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x89, 0x00, 0x03, 0x00,
3991 0x70, 0x00, 0x0f, 0x00, 0x0b, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
3992 0x0f, 0x00, 0x0b, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
3993 {
3994 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
3995 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x89, 0x00, 0x03, 0x00,
3996 0x70, 0x00, 0x0f, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
3997 0x0f, 0x00, 0x0a, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
3998 {
3999 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
4000 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x89, 0x00, 0x03, 0x00,
4001 0x70, 0x00, 0x0f, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
4002 0x0f, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
4003 {
4004 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
4005 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
4006 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
4007 0x0e, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
4008 {
4009 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
4010 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x03, 0x00,
4011 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00,
4012 0x0e, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
4013 {
4014 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
4015 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x76, 0x00, 0x03, 0x00,
4016 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00,
4017 0x0e, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
4018 {
4019 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
4020 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x66, 0x00, 0x03, 0x00,
4021 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x03, 0x00, 0x70, 0x00,
4022 0x0e, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
4023 {
4024 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
4025 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x55, 0x00, 0x02, 0x00,
4026 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00,
4027 0x0e, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
4028 {
4029 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
4030 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x45, 0x00, 0x02, 0x00,
4031 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
4032 0x0e, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
4033 {
4034 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
4035 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x34, 0x00, 0x02, 0x00,
4036 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
4037 0x0d, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
4038 {
4039 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
4040 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
4041 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
4042 0x0d, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
4043 {
4044 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
4045 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x22, 0x00, 0x02, 0x00,
4046 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
4047 0x0d, 0x00, 0x08, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
4048 {
4049 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
4050 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00,
4051 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
4052 0x0d, 0x00, 0x08, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
4053 {
4054 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
4055 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
4056 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
4057 0x0d, 0x00, 0x08, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
4058};
4059
4060static const struct chan_info_nphy_radio205x chan_info_nphyrev6_2056v8[] = {
4061 {
4062 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
4063 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4064 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4065 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
4066 {
4067 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
4068 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4069 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4070 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
4071 {
4072 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
4073 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4074 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4075 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
4076 {
4077 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
4078 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4079 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4080 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
4081 {
4082 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
4083 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4084 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4085 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
4086 {
4087 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
4088 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
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4090 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
4091 {
4092 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
4093 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
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4095 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
4096 {
4097 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
4098 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
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4100 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
4101 {
4102 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
4103 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
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4105 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
4106 {
4107 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
4108 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4109 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4110 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
4111 {
4112 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
4113 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
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4115 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
4116 {
4117 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
4118 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4119 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4120 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
4121 {
4122 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
4123 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4124 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4125 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
4126 {
4127 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
4128 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4129 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4130 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
4131 {
4132 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
4133 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4134 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4135 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
4136 {
4137 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
4138 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
4139 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4140 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
4141 {
4142 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
4143 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
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4145 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
4146 {
4147 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
4148 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
4149 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4150 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
4151 {
4152 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
4153 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77,
4154 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
4155 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
4156 {
4157 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
4158 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
4159 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
4160 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
4161 {
4162 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
4163 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
4164 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
4165 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
4166 {
4167 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
4168 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
4169 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
4170 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
4171 {
4172 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
4173 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77,
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4175 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
4176 {
4177 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
4178 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
4179 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
4180 0x00, 0x6f, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
4181 {
4182 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
4183 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
4184 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
4185 0x00, 0x6f, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
4186 {
4187 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, 0x0c, 0x01,
4188 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
4189 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e,
4190 0x00, 0x6f, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
4191 {
4192 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, 0x0c, 0x01,
4193 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
4194 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d,
4195 0x00, 0x6f, 0x00, 0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa},
4196 {
4197 40, 5200, 0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, 0x0c, 0x01,
4198 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77,
4199 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4200 0x00, 0x6f, 0x00, 0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9},
4201 {
4202 42, 5210, 0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, 0x0c, 0x01,
4203 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77,
4204 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4205 0x00, 0x6f, 0x00, 0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8},
4206 {
4207 44, 5220, 0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, 0x0c, 0x01,
4208 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77,
4209 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4210 0x00, 0x6f, 0x00, 0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7},
4211 {
4212 46, 5230, 0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, 0x0c, 0x01,
4213 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77,
4214 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4215 0x00, 0x6f, 0x00, 0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6},
4216 {
4217 48, 5240, 0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, 0x0c, 0x01,
4218 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xc8, 0x00, 0x05, 0x00, 0x77,
4219 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4220 0x00, 0x6f, 0x00, 0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5},
4221 {
4222 50, 5250, 0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, 0x0c, 0x01,
4223 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xed, 0xc7, 0x00, 0x05, 0x00, 0x77,
4224 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4225 0x00, 0x6f, 0x00, 0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4},
4226 {
4227 52, 5260, 0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, 0x0c, 0x01,
4228 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77,
4229 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d,
4230 0x00, 0x6f, 0x00, 0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3},
4231 {
4232 54, 5270, 0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, 0x0c, 0x01,
4233 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77,
4234 0x00, 0x0c, 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c,
4235 0x00, 0x6f, 0x00, 0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2},
4236 {
4237 56, 5280, 0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, 0x0c, 0x01,
4238 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77,
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4240 0x00, 0x6f, 0x00, 0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1},
4241 {
4242 58, 5290, 0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, 0x0c, 0x01,
4243 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77,
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4245 0x00, 0x6f, 0x00, 0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0},
4246 {
4247 60, 5300, 0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, 0x0c, 0x01,
4248 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77,
4249 0x00, 0x0c, 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
4250 0x00, 0x6f, 0x00, 0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0},
4251 {
4252 62, 5310, 0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, 0x0c, 0x01,
4253 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77,
4254 0x00, 0x0c, 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
4255 0x00, 0x6f, 0x00, 0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef},
4256 {
4257 64, 5320, 0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, 0x0c, 0x01,
4258 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdb, 0xb7, 0x00, 0x03, 0x00, 0x77,
4259 0x00, 0x0c, 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
4260 0x00, 0x6f, 0x00, 0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee},
4261 {
4262 66, 5330, 0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, 0x0c, 0x01,
4263 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, 0xcb, 0xa6, 0x00, 0x03, 0x00, 0x77,
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4265 0x00, 0x6f, 0x00, 0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed},
4266 {
4267 68, 5340, 0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, 0x0c, 0x01,
4268 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77,
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4270 0x00, 0x6f, 0x00, 0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec},
4271 {
4272 70, 5350, 0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, 0x0c, 0x01,
4273 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77,
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4276 {
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4291 {
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4296 {
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4301 {
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4306 {
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4311 {
4312 86, 5430, 0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, 0x0c, 0x01,
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4316 {
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4321 {
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4325 0x00, 0x6f, 0x00, 0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2},
4326 {
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4330 0x00, 0x6f, 0x00, 0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1},
4331 {
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4336 {
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4341 {
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4346 {
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4350 0x00, 0x6f, 0x00, 0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd},
4351 {
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4356 {
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4361 {
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4366 {
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4371 {
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4376 {
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4380 0x00, 0x6f, 0x00, 0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8},
4381 {
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4385 0x00, 0x6f, 0x00, 0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7},
4386 {
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4391 {
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4396 {
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4401 {
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4406 {
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4411 {
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4415 0x00, 0x6f, 0x00, 0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2},
4416 {
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4421 {
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4426 {
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4431 {
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4436 {
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4441 {
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4446 {
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4451 {
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4456 {
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4461 {
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4601 {
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4656 {
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4660 0x0a, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
4661 {
4662 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
4663 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00,
4664 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
4665 0x09, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
4666 {
4667 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
4668 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
4669 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
4670 0x09, 0x00, 0x09, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
4671 {
4672 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
4673 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
4674 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
4675 0x09, 0x00, 0x09, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
4676 {
4677 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
4678 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
4679 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
4680 0x09, 0x00, 0x09, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
4681};
4682
4683static const struct chan_info_nphy_radio205x chan_info_nphyrev6_2056v11[] = {
4684 {
4685 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x02, 0x0c, 0x01,
4686 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4687 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4688 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
4689 {
4690 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x02, 0x0c, 0x01,
4691 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4692 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4693 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
4694 {
4695 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x02, 0x0c, 0x01,
4696 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4697 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4698 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
4699 {
4700 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x02, 0x0c, 0x01,
4701 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4702 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4703 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
4704 {
4705 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x02, 0x0c, 0x01,
4706 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4707 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4708 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
4709 {
4710 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x02, 0x0c, 0x01,
4711 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4712 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4713 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
4714 {
4715 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x02, 0x0c, 0x01,
4716 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4717 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4718 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
4719 {
4720 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x02, 0x0c, 0x01,
4721 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4722 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4723 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
4724 {
4725 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x02, 0x0c, 0x01,
4726 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4727 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4728 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
4729 {
4730 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x02, 0x0c, 0x01,
4731 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4732 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4733 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
4734 {
4735 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x02, 0x0c, 0x01,
4736 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4737 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4738 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
4739 {
4740 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x02, 0x0c, 0x01,
4741 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4742 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4743 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
4744 {
4745 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x02, 0x0c, 0x01,
4746 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4747 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4748 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
4749 {
4750 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x02, 0x0c, 0x01,
4751 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4752 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4753 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
4754 {
4755 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x02, 0x0c, 0x01,
4756 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
4757 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4758 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
4759 {
4760 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x02, 0x0c, 0x01,
4761 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
4762 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4763 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
4764 {
4765 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x02, 0x0c, 0x01,
4766 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
4767 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4768 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
4769 {
4770 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x02, 0x0c, 0x01,
4771 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
4772 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
4773 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
4774 {
4775 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x02, 0x0c, 0x01,
4776 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77,
4777 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
4778 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
4779 {
4780 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x02, 0x0c, 0x01,
4781 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
4782 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
4783 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
4784 {
4785 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x02, 0x0c, 0x01,
4786 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
4787 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
4788 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
4789 {
4790 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x02, 0x0c, 0x01,
4791 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
4792 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
4793 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
4794 {
4795 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x02, 0x0c, 0x01,
4796 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77,
4797 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
4798 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
4799 {
4800 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x02, 0x0c, 0x01,
4801 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
4802 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
4803 0x00, 0x6f, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
4804 {
4805 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x02, 0x0c, 0x01,
4806 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
4807 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
4808 0x00, 0x6f, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
4809 {
4810 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x02, 0x0c, 0x01,
4811 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
4812 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e,
4813 0x00, 0x6f, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
4814 {
4815 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x02, 0x0c, 0x01,
4816 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
4817 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d,
4818 0x00, 0x6f, 0x00, 0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa},
4819 {
4820 40, 5200, 0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x02, 0x0c, 0x01,
4821 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77,
4822 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4823 0x00, 0x6f, 0x00, 0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9},
4824 {
4825 42, 5210, 0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x02, 0x0c, 0x01,
4826 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77,
4827 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4828 0x00, 0x6f, 0x00, 0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8},
4829 {
4830 44, 5220, 0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x02, 0x0c, 0x01,
4831 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77,
4832 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4833 0x00, 0x6f, 0x00, 0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7},
4834 {
4835 46, 5230, 0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x02, 0x0c, 0x01,
4836 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77,
4837 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4838 0x00, 0x6f, 0x00, 0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6},
4839 {
4840 48, 5240, 0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x02, 0x0c, 0x01,
4841 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xc8, 0x00, 0x05, 0x00, 0x77,
4842 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4843 0x00, 0x6f, 0x00, 0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5},
4844 {
4845 50, 5250, 0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x02, 0x0c, 0x01,
4846 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xed, 0xc7, 0x00, 0x05, 0x00, 0x77,
4847 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
4848 0x00, 0x6f, 0x00, 0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4},
4849 {
4850 52, 5260, 0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x02, 0x0c, 0x01,
4851 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77,
4852 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d,
4853 0x00, 0x6f, 0x00, 0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3},
4854 {
4855 54, 5270, 0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x02, 0x0c, 0x01,
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4894 {
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4899 {
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4904 {
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4909 {
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4929 {
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4934 {
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4939 {
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4954 {
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4959 {
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4964 {
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4969 {
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4974 {
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4979 {
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4984 {
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4989 {
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4994 {
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4999 {
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5004 {
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5009 {
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5014 {
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5019 {
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5021 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, 0x50, 0x51, 0x00, 0x00, 0x00, 0x77,
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5024 {
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5028 0x00, 0x6f, 0x00, 0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4},
5029 {
5030 124, 5620, 0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x02, 0x0c, 0x01,
5031 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, 0x50, 0x50, 0x00, 0x00, 0x00, 0x77,
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5034 {
5035 126, 5630, 0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x02, 0x0c, 0x01,
5036 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, 0x50, 0x50, 0x00, 0x00, 0x00, 0x77,
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5039 {
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5044 {
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5079 {
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5084 {
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5089 {
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5094 {
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5099 {
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5104 {
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5109 {
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5114 {
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5119 {
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5124 {
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5129 {
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5134 {
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5139 {
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5144 {
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5149 {
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5154 {
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5159 {
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5164 {
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5169 {
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5174 {
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5179 {
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5184 {
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5189 {
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5194 {
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5199 {
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5204 {
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5209 {
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5213 0x00, 0x68, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
5214 {
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5219 {
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5224 {
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5229 {
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5234 {
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5238 0x0b, 0x00, 0x0a, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
5239 {
5240 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x06, 0x06, 0x04, 0x2b, 0x01,
5241 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
5242 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
5243 0x0b, 0x00, 0x0a, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
5244 {
5245 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x06, 0x06, 0x04, 0x2b, 0x01,
5246 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x67, 0x00, 0x03, 0x00,
5247 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
5248 0x0b, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
5249 {
5250 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x06, 0x06, 0x04, 0x2b, 0x01,
5251 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x57, 0x00, 0x03, 0x00,
5252 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
5253 0x0a, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
5254 {
5255 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x06, 0x06, 0x04, 0x2b, 0x01,
5256 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x56, 0x00, 0x03, 0x00,
5257 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00,
5258 0x0a, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
5259 {
5260 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x06, 0x06, 0x04, 0x2b, 0x01,
5261 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x46, 0x00, 0x03, 0x00,
5262 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00,
5263 0x0a, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
5264 {
5265 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x06, 0x06, 0x04, 0x2b, 0x01,
5266 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x45, 0x00, 0x02, 0x00,
5267 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00, 0x70, 0x00,
5268 0x0a, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
5269 {
5270 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x06, 0x06, 0x04, 0x2b, 0x01,
5271 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x34, 0x00, 0x02, 0x00,
5272 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00,
5273 0x0a, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
5274 {
5275 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x06, 0x06, 0x04, 0x2b, 0x01,
5276 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x23, 0x00, 0x02, 0x00,
5277 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
5278 0x0a, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
5279 {
5280 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x06, 0x06, 0x04, 0x2b, 0x01,
5281 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x12, 0x00, 0x02, 0x00,
5282 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
5283 0x0a, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
5284 {
5285 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x06, 0x06, 0x04, 0x2b, 0x01,
5286 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00,
5287 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
5288 0x09, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
5289 {
5290 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x06, 0x06, 0x04, 0x2b, 0x01,
5291 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
5292 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
5293 0x09, 0x00, 0x09, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
5294 {
5295 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x06, 0x06, 0x04, 0x2b, 0x01,
5296 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
5297 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
5298 0x09, 0x00, 0x09, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
5299 {
5300 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x06, 0x06, 0x04, 0x2b, 0x01,
5301 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
5302 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
5303 0x09, 0x00, 0x09, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
5304};
5305
5306static const struct chan_info_nphy_radio2057 chan_info_nphyrev7_2057_rev4[] = {
5307 {
5308 184, 4920, 0x68, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xec, 0x01, 0x0f,
5309 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5310 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07b4, 0x07b0, 0x07ac, 0x0214,
5311 0x0215,
5312 0x0216,
5313 },
5314 {
5315 186, 4930, 0x6b, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xed, 0x01, 0x0f,
5316 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5317 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07b8, 0x07b4, 0x07b0, 0x0213,
5318 0x0214,
5319 0x0215,
5320 },
5321 {
5322 188, 4940, 0x6e, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xee, 0x01, 0x0f,
5323 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5324 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07bc, 0x07b8, 0x07b4, 0x0212,
5325 0x0213,
5326 0x0214,
5327 },
5328 {
5329 190, 4950, 0x72, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xef, 0x01, 0x0f,
5330 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5331 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07c0, 0x07bc, 0x07b8, 0x0211,
5332 0x0212,
5333 0x0213,
5334 },
5335 {
5336 192, 4960, 0x75, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf0, 0x01, 0x0f,
5337 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5338 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07c4, 0x07c0, 0x07bc, 0x020f,
5339 0x0211,
5340 0x0212,
5341 },
5342 {
5343 194, 4970, 0x78, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf1, 0x01, 0x0f,
5344 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5345 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07c8, 0x07c4, 0x07c0, 0x020e,
5346 0x020f,
5347 0x0211,
5348 },
5349 {
5350 196, 4980, 0x7c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf2, 0x01, 0x0f,
5351 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5352 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07cc, 0x07c8, 0x07c4, 0x020d,
5353 0x020e,
5354 0x020f,
5355 },
5356 {
5357 198, 4990, 0x7f, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf3, 0x01, 0x0f,
5358 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5359 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07d0, 0x07cc, 0x07c8, 0x020c,
5360 0x020d,
5361 0x020e,
5362 },
5363 {
5364 200, 5000, 0x82, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf4, 0x01, 0x0f,
5365 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5366 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07d4, 0x07d0, 0x07cc, 0x020b,
5367 0x020c,
5368 0x020d,
5369 },
5370 {
5371 202, 5010, 0x86, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf5, 0x01, 0x0f,
5372 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5373 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07d8, 0x07d4, 0x07d0, 0x020a,
5374 0x020b,
5375 0x020c,
5376 },
5377 {
5378 204, 5020, 0x89, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf6, 0x01, 0x0e,
5379 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5380 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07dc, 0x07d8, 0x07d4, 0x0209,
5381 0x020a,
5382 0x020b,
5383 },
5384 {
5385 206, 5030, 0x8c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf7, 0x01, 0x0e,
5386 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5387 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07e0, 0x07dc, 0x07d8, 0x0208,
5388 0x0209,
5389 0x020a,
5390 },
5391 {
5392 208, 5040, 0x90, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf8, 0x01, 0x0e,
5393 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5394 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07e4, 0x07e0, 0x07dc, 0x0207,
5395 0x0208,
5396 0x0209,
5397 },
5398 {
5399 210, 5050, 0x93, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf9, 0x01, 0x0e,
5400 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
5401 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07e8, 0x07e4, 0x07e0, 0x0206,
5402 0x0207,
5403 0x0208,
5404 },
5405 {
5406 212, 5060, 0x96, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfa, 0x01, 0x0e,
5407 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xe3, 0x00, 0xef, 0x00,
5408 0x00, 0x0f, 0x0f, 0xe3, 0x00, 0xef, 0x07ec, 0x07e8, 0x07e4, 0x0205,
5409 0x0206,
5410 0x0207,
5411 },
5412 {
5413 214, 5070, 0x9a, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfb, 0x01, 0x0e,
5414 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xef, 0x00,
5415 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xef, 0x07f0, 0x07ec, 0x07e8, 0x0204,
5416 0x0205,
5417 0x0206,
5418 },
5419 {
5420 216, 5080, 0x9d, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfc, 0x01, 0x0e,
5421 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xef, 0x00,
5422 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xef, 0x07f4, 0x07f0, 0x07ec, 0x0203,
5423 0x0204,
5424 0x0205,
5425 },
5426 {
5427 218, 5090, 0xa0, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfd, 0x01, 0x0e,
5428 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x00,
5429 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x07f8, 0x07f4, 0x07f0, 0x0202,
5430 0x0203,
5431 0x0204,
5432 },
5433 {
5434 220, 5100, 0xa4, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfe, 0x01, 0x0d,
5435 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x00,
5436 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x07fc, 0x07f8, 0x07f4, 0x0201,
5437 0x0202,
5438 0x0203,
5439 },
5440 {
5441 222, 5110, 0xa7, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xff, 0x01, 0x0d,
5442 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x00,
5443 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x0800, 0x07fc, 0x07f8, 0x0200,
5444 0x0201,
5445 0x0202,
5446 },
5447 {
5448 224, 5120, 0xaa, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x02, 0x0d,
5449 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x00,
5450 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x0804, 0x0800, 0x07fc, 0x01ff,
5451 0x0200,
5452 0x0201,
5453 },
5454 {
5455 226, 5130, 0xae, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x01, 0x02, 0x0d,
5456 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x00,
5457 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x0808, 0x0804, 0x0800, 0x01fe,
5458 0x01ff,
5459 0x0200,
5460 },
5461 {
5462 228, 5140, 0xb1, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x02, 0x02, 0x0d,
5463 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0e, 0x0e, 0xe3, 0x00, 0xd6, 0x00,
5464 0x00, 0x0e, 0x0e, 0xe3, 0x00, 0xd6, 0x080c, 0x0808, 0x0804, 0x01fd,
5465 0x01fe,
5466 0x01ff,
5467 },
5468 {
5469 32, 5160, 0xb8, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x04, 0x02, 0x0d,
5470 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0d, 0x0e, 0xe3, 0x00, 0xd6, 0x00,
5471 0x00, 0x0d, 0x0e, 0xe3, 0x00, 0xd6, 0x0814, 0x0810, 0x080c, 0x01fb,
5472 0x01fc,
5473 0x01fd,
5474 },
5475 {
5476 34, 5170, 0xbb, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x05, 0x02, 0x0d,
5477 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0d, 0x0e, 0xe3, 0x00, 0xd6, 0x00,
5478 0x00, 0x0d, 0x0e, 0xe3, 0x00, 0xd6, 0x0818, 0x0814, 0x0810, 0x01fa,
5479 0x01fb,
5480 0x01fc,
5481 },
5482 {
5483 36, 5180, 0xbe, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x06, 0x02, 0x0c,
5484 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0d, 0x0e, 0xd3, 0x00, 0xd6, 0x00,
5485 0x00, 0x0d, 0x0e, 0xd3, 0x00, 0xd6, 0x081c, 0x0818, 0x0814, 0x01f9,
5486 0x01fa,
5487 0x01fb,
5488 },
5489 {
5490 38, 5190, 0xc2, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x07, 0x02, 0x0c,
5491 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0d, 0x0e, 0xd3, 0x00, 0xd6, 0x00,
5492 0x00, 0x0d, 0x0e, 0xd3, 0x00, 0xd6, 0x0820, 0x081c, 0x0818, 0x01f8,
5493 0x01f9,
5494 0x01fa,
5495 },
5496 {
5497 40, 5200, 0xc5, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x08, 0x02, 0x0c,
5498 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0d, 0x0e, 0xd3, 0x00, 0xd6, 0x00,
5499 0x00, 0x0d, 0x0e, 0xd3, 0x00, 0xd6, 0x0824, 0x0820, 0x081c, 0x01f7,
5500 0x01f8,
5501 0x01f9,
5502 },
5503 {
5504 42, 5210, 0xc8, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x09, 0x02, 0x0c,
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6120 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0f,
6121 0x07, 0x00, 0x07, 0x00, 0x31, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
6122 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d7, 0x03d3, 0x03cf, 0x042b,
6123 0x042f,
6124 0x0434,
6125 },
6126 {
6127 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0f,
6128 0x07, 0x00, 0x07, 0x00, 0x31, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
6129 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d9, 0x03d5, 0x03d1, 0x0429,
6130 0x042d,
6131 0x0431,
6132 },
6133 {
6134 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0f,
6135 0x06, 0x00, 0x06, 0x00, 0x31, 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
6136 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03db, 0x03d7, 0x03d3, 0x0427,
6137 0x042b,
6138 0x042f,
6139 },
6140 {
6141 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0f,
6142 0x06, 0x00, 0x06, 0x00, 0x31, 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
6143 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03dd, 0x03d9, 0x03d5, 0x0424,
6144 0x0429,
6145 0x042d,
6146 },
6147 {
6148 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0f,
6149 0x05, 0x00, 0x05, 0x00, 0x11, 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x11,
6150 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03df, 0x03db, 0x03d7, 0x0422,
6151 0x0427,
6152 0x042b,
6153 },
6154 {
6155 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0f,
6156 0x05, 0x00, 0x05, 0x00, 0x11, 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x11,
6157 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03e1, 0x03dd, 0x03d9, 0x0420,
6158 0x0424,
6159 0x0429,
6160 },
6161 {
6162 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0f,
6163 0x04, 0x00, 0x04, 0x00, 0x11, 0x43, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x11,
6164 0x43, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x03e6, 0x03e2, 0x03de, 0x041b,
6165 0x041f,
6166 0x0424}
6167};
6168
6169static const struct chan_info_nphy_radio2057_rev5
6170chan_info_nphyrev8_2057_rev5[] = {
6171 {
6172 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0d,
6173 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03c9, 0x03c5, 0x03c1,
6174 0x043a, 0x043f, 0x0443},
6175 {
6176 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0d,
6177 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03cb, 0x03c7, 0x03c3,
6178 0x0438, 0x043d, 0x0441},
6179 {
6180 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0d,
6181 0x08, 0x0e, 0x61, 0x03, 0xef, 0x61, 0x03, 0xef, 0x03cd, 0x03c9, 0x03c5,
6182 0x0436, 0x043a, 0x043f},
6183 {
6184 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0c,
6185 0x08, 0x0e, 0x61, 0x03, 0xdf, 0x61, 0x03, 0xdf, 0x03cf, 0x03cb, 0x03c7,
6186 0x0434, 0x0438, 0x043d},
6187 {
6188 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0c,
6189 0x07, 0x0d, 0x61, 0x03, 0xcf, 0x61, 0x03, 0xcf, 0x03d1, 0x03cd, 0x03c9,
6190 0x0431, 0x0436, 0x043a},
6191 {
6192 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0c,
6193 0x07, 0x0d, 0x61, 0x03, 0xbf, 0x61, 0x03, 0xbf, 0x03d3, 0x03cf, 0x03cb,
6194 0x042f, 0x0434, 0x0438},
6195 {
6196 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0b,
6197 0x07, 0x0d, 0x61, 0x03, 0xaf, 0x61, 0x03, 0xaf, 0x03d5, 0x03d1, 0x03cd,
6198 0x042d, 0x0431, 0x0436},
6199 {
6200 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0b,
6201 0x07, 0x0d, 0x61, 0x03, 0x9f, 0x61, 0x03, 0x9f, 0x03d7, 0x03d3, 0x03cf,
6202 0x042b, 0x042f, 0x0434},
6203 {
6204 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0b,
6205 0x07, 0x0d, 0x61, 0x03, 0x8f, 0x61, 0x03, 0x8f, 0x03d9, 0x03d5, 0x03d1,
6206 0x0429, 0x042d, 0x0431},
6207 {
6208 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0b,
6209 0x07, 0x0c, 0x61, 0x03, 0x7f, 0x61, 0x03, 0x7f, 0x03db, 0x03d7, 0x03d3,
6210 0x0427, 0x042b, 0x042f},
6211 {
6212 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0b,
6213 0x07, 0x0c, 0x61, 0x03, 0x6f, 0x61, 0x03, 0x6f, 0x03dd, 0x03d9, 0x03d5,
6214 0x0424, 0x0429, 0x042d},
6215 {
6216 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0b,
6217 0x06, 0x0c, 0x61, 0x03, 0x5f, 0x61, 0x03, 0x5f, 0x03df, 0x03db, 0x03d7,
6218 0x0422, 0x0427, 0x042b},
6219 {
6220 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0a,
6221 0x06, 0x0b, 0x61, 0x03, 0x4f, 0x61, 0x03, 0x4f, 0x03e1, 0x03dd, 0x03d9,
6222 0x0420, 0x0424, 0x0429},
6223 {
6224 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0a,
6225 0x06, 0x0b, 0x61, 0x03, 0x3f, 0x61, 0x03, 0x3f, 0x03e6, 0x03e2, 0x03de,
6226 0x041b, 0x041f, 0x0424}
6227};
6228
6229static const struct chan_info_nphy_radio2057_rev5
6230chan_info_nphyrev9_2057_rev5v1[] = {
6231 {
6232 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0d,
6233 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03c9, 0x03c5, 0x03c1,
6234 0x043a, 0x043f, 0x0443},
6235 {
6236 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0d,
6237 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03cb, 0x03c7, 0x03c3,
6238 0x0438, 0x043d, 0x0441},
6239 {
6240 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0d,
6241 0x08, 0x0e, 0x61, 0x03, 0xef, 0x61, 0x03, 0xef, 0x03cd, 0x03c9, 0x03c5,
6242 0x0436, 0x043a, 0x043f},
6243 {
6244 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0c,
6245 0x08, 0x0e, 0x61, 0x03, 0xdf, 0x61, 0x03, 0xdf, 0x03cf, 0x03cb, 0x03c7,
6246 0x0434, 0x0438, 0x043d},
6247 {
6248 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0c,
6249 0x07, 0x0d, 0x61, 0x03, 0xcf, 0x61, 0x03, 0xcf, 0x03d1, 0x03cd, 0x03c9,
6250 0x0431, 0x0436, 0x043a},
6251 {
6252 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0c,
6253 0x07, 0x0d, 0x61, 0x03, 0xbf, 0x61, 0x03, 0xbf, 0x03d3, 0x03cf, 0x03cb,
6254 0x042f, 0x0434, 0x0438},
6255 {
6256 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0b,
6257 0x07, 0x0d, 0x61, 0x03, 0xaf, 0x61, 0x03, 0xaf, 0x03d5, 0x03d1, 0x03cd,
6258 0x042d, 0x0431, 0x0436},
6259 {
6260 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0b,
6261 0x07, 0x0d, 0x61, 0x03, 0x9f, 0x61, 0x03, 0x9f, 0x03d7, 0x03d3, 0x03cf,
6262 0x042b, 0x042f, 0x0434},
6263 {
6264 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0b,
6265 0x07, 0x0d, 0x61, 0x03, 0x8f, 0x61, 0x03, 0x8f, 0x03d9, 0x03d5, 0x03d1,
6266 0x0429, 0x042d, 0x0431},
6267 {
6268 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0b,
6269 0x07, 0x0c, 0x61, 0x03, 0x7f, 0x61, 0x03, 0x7f, 0x03db, 0x03d7, 0x03d3,
6270 0x0427, 0x042b, 0x042f},
6271 {
6272 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0b,
6273 0x07, 0x0c, 0x61, 0x03, 0x6f, 0x61, 0x03, 0x6f, 0x03dd, 0x03d9, 0x03d5,
6274 0x0424, 0x0429, 0x042d},
6275 {
6276 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0b,
6277 0x06, 0x0c, 0x61, 0x03, 0x5f, 0x61, 0x03, 0x5f, 0x03df, 0x03db, 0x03d7,
6278 0x0422, 0x0427, 0x042b},
6279 {
6280 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0a,
6281 0x06, 0x0b, 0x61, 0x03, 0x4f, 0x61, 0x03, 0x4f, 0x03e1, 0x03dd, 0x03d9,
6282 0x0420, 0x0424, 0x0429},
6283 {
6284 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0a,
6285 0x06, 0x0b, 0x61, 0x03, 0x3f, 0x61, 0x03, 0x3f, 0x03e6, 0x03e2, 0x03de,
6286 0x041b, 0x041f, 0x0424}
6287};
6288
6289static const struct chan_info_nphy_radio2057 chan_info_nphyrev8_2057_rev7[] = {
6290 {
6291 184, 4920, 0x68, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xec, 0x01, 0x0f,
6292 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
6293 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07b4, 0x07b0, 0x07ac, 0x0214,
6294 0x0215,
6295 0x0216},
6296 {
6297 186, 4930, 0x6b, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xed, 0x01, 0x0f,
6298 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
6299 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07b8, 0x07b4, 0x07b0, 0x0213,
6300 0x0214,
6301 0x0215},
6302 {
6303 188, 4940, 0x6e, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xee, 0x01, 0x0f,
6304 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
6305 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07bc, 0x07b8, 0x07b4, 0x0212,
6306 0x0213,
6307 0x0214},
6308 {
6309 190, 4950, 0x72, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xef, 0x01, 0x0f,
6310 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
6311 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c0, 0x07bc, 0x07b8, 0x0211,
6312 0x0212,
6313 0x0213},
6314 {
6315 192, 4960, 0x75, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf0, 0x01, 0x0f,
6316 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
6317 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c4, 0x07c0, 0x07bc, 0x020f,
6318 0x0211,
6319 0x0212},
6320 {
6321 194, 4970, 0x78, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf1, 0x01, 0x0f,
6322 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
6323 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c8, 0x07c4, 0x07c0, 0x020e,
6324 0x020f,
6325 0x0211},
6326 {
6327 196, 4980, 0x7c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf2, 0x01, 0x0f,
6328 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
6329 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07cc, 0x07c8, 0x07c4, 0x020d,
6330 0x020e,
6331 0x020f},
6332 {
6333 198, 4990, 0x7f, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf3, 0x01, 0x0f,
6334 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
6335 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07d0, 0x07cc, 0x07c8, 0x020c,
6336 0x020d,
6337 0x020e},
6338 {
6339 200, 5000, 0x82, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf4, 0x01, 0x0f,
6340 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
6341 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d4, 0x07d0, 0x07cc, 0x020b,
6342 0x020c,
6343 0x020d},
6344 {
6345 202, 5010, 0x86, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf5, 0x01, 0x0f,
6346 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
6347 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d8, 0x07d4, 0x07d0, 0x020a,
6348 0x020b,
6349 0x020c},
6350 {
6351 204, 5020, 0x89, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf6, 0x01, 0x0e,
6352 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
6353 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07dc, 0x07d8, 0x07d4, 0x0209,
6354 0x020a,
6355 0x020b},
6356 {
6357 206, 5030, 0x8c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf7, 0x01, 0x0e,
6358 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
6359 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e0, 0x07dc, 0x07d8, 0x0208,
6360 0x0209,
6361 0x020a},
6362 {
6363 208, 5040, 0x90, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf8, 0x01, 0x0e,
6364 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
6365 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e4, 0x07e0, 0x07dc, 0x0207,
6366 0x0208,
6367 0x0209},
6368 {
6369 210, 5050, 0x93, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf9, 0x01, 0x0e,
6370 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
6371 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e8, 0x07e4, 0x07e0, 0x0206,
6372 0x0207,
6373 0x0208},
6374 {
6375 212, 5060, 0x96, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfa, 0x01, 0x0e,
6376 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
6377 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07ec, 0x07e8, 0x07e4, 0x0205,
6378 0x0206,
6379 0x0207},
6380 {
6381 214, 5070, 0x9a, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfb, 0x01, 0x0e,
6382 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
6383 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f0, 0x07ec, 0x07e8, 0x0204,
6384 0x0205,
6385 0x0206},
6386 {
6387 216, 5080, 0x9d, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfc, 0x01, 0x0e,
6388 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
6389 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f4, 0x07f0, 0x07ec, 0x0203,
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6398 {
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6600 0x01e2,
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6602 {
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6620 {
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6626 {
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6637 0x01dd},
6638 {
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6644 {
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6648 0x01db,
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6650 {
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6654 0x01da,
6655 0x01db},
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6927 176, 5880, 0xa8, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4c, 0x02, 0x03,
6928 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
6929 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd,
6930 0x01be,
6931 0x01bf},
6932 {
6933 178, 5890, 0xab, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4d, 0x02, 0x03,
6934 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
6935 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc,
6936 0x01bd,
6937 0x01be},
6938 {
6939 180, 5900, 0xae, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4e, 0x02, 0x03,
6940 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
6941 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc,
6942 0x01bc,
6943 0x01bd},
6944 {
6945 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0f,
6946 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
6947 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03c9, 0x03c5, 0x03c1, 0x043a,
6948 0x043f,
6949 0x0443},
6950 {
6951 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0f,
6952 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
6953 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cb, 0x03c7, 0x03c3, 0x0438,
6954 0x043d,
6955 0x0441},
6956 {
6957 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0f,
6958 0x09, 0x00, 0x09, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
6959 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cd, 0x03c9, 0x03c5, 0x0436,
6960 0x043a,
6961 0x043f},
6962 {
6963 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0f,
6964 0x09, 0x00, 0x09, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
6965 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cf, 0x03cb, 0x03c7, 0x0434,
6966 0x0438,
6967 0x043d},
6968 {
6969 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0f,
6970 0x08, 0x00, 0x08, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
6971 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d1, 0x03cd, 0x03c9, 0x0431,
6972 0x0436,
6973 0x043a},
6974 {
6975 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0f,
6976 0x08, 0x00, 0x08, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
6977 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d3, 0x03cf, 0x03cb, 0x042f,
6978 0x0434,
6979 0x0438},
6980 {
6981 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0f,
6982 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
6983 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d5, 0x03d1, 0x03cd, 0x042d,
6984 0x0431,
6985 0x0436},
6986 {
6987 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0f,
6988 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
6989 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d7, 0x03d3, 0x03cf, 0x042b,
6990 0x042f,
6991 0x0434},
6992 {
6993 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0f,
6994 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
6995 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d9, 0x03d5, 0x03d1, 0x0429,
6996 0x042d,
6997 0x0431},
6998 {
6999 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0f,
7000 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
7001 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03db, 0x03d7, 0x03d3, 0x0427,
7002 0x042b,
7003 0x042f},
7004 {
7005 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0f,
7006 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
7007 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03dd, 0x03d9, 0x03d5, 0x0424,
7008 0x0429,
7009 0x042d},
7010 {
7011 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0f,
7012 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
7013 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03df, 0x03db, 0x03d7, 0x0422,
7014 0x0427,
7015 0x042b},
7016 {
7017 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0f,
7018 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
7019 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03e1, 0x03dd, 0x03d9, 0x0420,
7020 0x0424,
7021 0x0429},
7022 {
7023 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0f,
7024 0x04, 0x00, 0x04, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x61,
7025 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x03e6, 0x03e2, 0x03de, 0x041b,
7026 0x041f,
7027 0x0424}
7028};
7029
7030static const struct chan_info_nphy_radio2057 chan_info_nphyrev8_2057_rev8[] = {
7031 {
7032 186, 4930, 0x6b, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xed, 0x01, 0x0f,
7033 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
7034 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07b8, 0x07b4, 0x07b0, 0x0213,
7035 0x0214,
7036 0x0215},
7037 {
7038 188, 4940, 0x6e, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xee, 0x01, 0x0f,
7039 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
7040 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07bc, 0x07b8, 0x07b4, 0x0212,
7041 0x0213,
7042 0x0214},
7043 {
7044 190, 4950, 0x72, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xef, 0x01, 0x0f,
7045 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
7046 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c0, 0x07bc, 0x07b8, 0x0211,
7047 0x0212,
7048 0x0213},
7049 {
7050 192, 4960, 0x75, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf0, 0x01, 0x0f,
7051 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
7052 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c4, 0x07c0, 0x07bc, 0x020f,
7053 0x0211,
7054 0x0212},
7055 {
7056 194, 4970, 0x78, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf1, 0x01, 0x0f,
7057 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
7058 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c8, 0x07c4, 0x07c0, 0x020e,
7059 0x020f,
7060 0x0211},
7061 {
7062 196, 4980, 0x7c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf2, 0x01, 0x0f,
7063 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
7064 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07cc, 0x07c8, 0x07c4, 0x020d,
7065 0x020e,
7066 0x020f},
7067 {
7068 198, 4990, 0x7f, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf3, 0x01, 0x0f,
7069 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
7070 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07d0, 0x07cc, 0x07c8, 0x020c,
7071 0x020d,
7072 0x020e},
7073 {
7074 200, 5000, 0x82, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf4, 0x01, 0x0f,
7075 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7076 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d4, 0x07d0, 0x07cc, 0x020b,
7077 0x020c,
7078 0x020d},
7079 {
7080 202, 5010, 0x86, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf5, 0x01, 0x0f,
7081 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7082 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d8, 0x07d4, 0x07d0, 0x020a,
7083 0x020b,
7084 0x020c},
7085 {
7086 204, 5020, 0x89, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf6, 0x01, 0x0e,
7087 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7088 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07dc, 0x07d8, 0x07d4, 0x0209,
7089 0x020a,
7090 0x020b},
7091 {
7092 206, 5030, 0x8c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf7, 0x01, 0x0e,
7093 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7094 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e0, 0x07dc, 0x07d8, 0x0208,
7095 0x0209,
7096 0x020a},
7097 {
7098 208, 5040, 0x90, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf8, 0x01, 0x0e,
7099 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7100 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e4, 0x07e0, 0x07dc, 0x0207,
7101 0x0208,
7102 0x0209},
7103 {
7104 210, 5050, 0x93, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf9, 0x01, 0x0e,
7105 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7106 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e8, 0x07e4, 0x07e0, 0x0206,
7107 0x0207,
7108 0x0208},
7109 {
7110 212, 5060, 0x96, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfa, 0x01, 0x0e,
7111 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7112 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07ec, 0x07e8, 0x07e4, 0x0205,
7113 0x0206,
7114 0x0207},
7115 {
7116 214, 5070, 0x9a, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfb, 0x01, 0x0e,
7117 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7118 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f0, 0x07ec, 0x07e8, 0x0204,
7119 0x0205,
7120 0x0206},
7121 {
7122 216, 5080, 0x9d, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfc, 0x01, 0x0e,
7123 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7124 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f4, 0x07f0, 0x07ec, 0x0203,
7125 0x0204,
7126 0x0205},
7127 {
7128 218, 5090, 0xa0, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfd, 0x01, 0x0e,
7129 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
7130 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f8, 0x07f4, 0x07f0, 0x0202,
7131 0x0203,
7132 0x0204},
7133 {
7134 220, 5100, 0xa4, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfe, 0x01, 0x0d,
7135 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
7136 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x07fc, 0x07f8, 0x07f4, 0x0201,
7137 0x0202,
7138 0x0203},
7139 {
7140 222, 5110, 0xa7, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xff, 0x01, 0x0d,
7141 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
7142 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0800, 0x07fc, 0x07f8, 0x0200,
7143 0x0201,
7144 0x0202},
7145 {
7146 224, 5120, 0xaa, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x02, 0x0d,
7147 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
7148 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0804, 0x0800, 0x07fc, 0x01ff,
7149 0x0200,
7150 0x0201},
7151 {
7152 226, 5130, 0xae, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x01, 0x02, 0x0d,
7153 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
7154 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0808, 0x0804, 0x0800, 0x01fe,
7155 0x01ff,
7156 0x0200},
7157 {
7158 228, 5140, 0xb1, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x02, 0x02, 0x0d,
7159 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
7160 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x080c, 0x0808, 0x0804, 0x01fd,
7161 0x01fe,
7162 0x01ff},
7163 {
7164 32, 5160, 0xb8, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x04, 0x02, 0x0d,
7165 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
7166 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0814, 0x0810, 0x080c, 0x01fb,
7167 0x01fc,
7168 0x01fd},
7169 {
7170 34, 5170, 0xbb, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x05, 0x02, 0x0d,
7171 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
7172 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0818, 0x0814, 0x0810, 0x01fa,
7173 0x01fb,
7174 0x01fc},
7175 {
7176 36, 5180, 0xbe, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x06, 0x02, 0x0c,
7177 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
7178 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x081c, 0x0818, 0x0814, 0x01f9,
7179 0x01fa,
7180 0x01fb},
7181 {
7182 38, 5190, 0xc2, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x07, 0x02, 0x0c,
7183 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
7184 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0820, 0x081c, 0x0818, 0x01f8,
7185 0x01f9,
7186 0x01fa},
7187 {
7188 40, 5200, 0xc5, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x08, 0x02, 0x0c,
7189 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0f, 0x0f, 0x93, 0x00, 0xf8, 0x00,
7190 0x00, 0x0f, 0x0f, 0x93, 0x00, 0xf8, 0x0824, 0x0820, 0x081c, 0x01f7,
7191 0x01f8,
7192 0x01f9},
7193 {
7194 42, 5210, 0xc8, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x09, 0x02, 0x0c,
7195 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0f, 0x0f, 0x93, 0x00, 0xf8, 0x00,
7196 0x00, 0x0f, 0x0f, 0x93, 0x00, 0xf8, 0x0828, 0x0824, 0x0820, 0x01f6,
7197 0x01f7,
7198 0x01f8},
7199 {
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7740 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0f,
7741 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
7742 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03dd, 0x03d9, 0x03d5, 0x0424,
7743 0x0429,
7744 0x042d},
7745 {
7746 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0f,
7747 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
7748 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03df, 0x03db, 0x03d7, 0x0422,
7749 0x0427,
7750 0x042b},
7751 {
7752 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0f,
7753 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
7754 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03e1, 0x03dd, 0x03d9, 0x0420,
7755 0x0424,
7756 0x0429},
7757 {
7758 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0f,
7759 0x04, 0x00, 0x04, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x61,
7760 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x03e6, 0x03e2, 0x03de, 0x041b,
7761 0x041f,
7762 0x0424}
7763};
7764
7765static struct radio_regs regs_2055[] = {
7766 {0x02, 0x80, 0x80, 0, 0},
7767 {0x03, 0, 0, 0, 0},
7768 {0x04, 0x27, 0x27, 0, 0},
7769 {0x05, 0, 0, 0, 0},
7770 {0x06, 0x27, 0x27, 0, 0},
7771 {0x07, 0x7f, 0x7f, 1, 1},
7772 {0x08, 0x7, 0x7, 1, 1},
7773 {0x09, 0x7f, 0x7f, 1, 1},
7774 {0x0A, 0x7, 0x7, 1, 1},
7775 {0x0B, 0x15, 0x15, 0, 0},
7776 {0x0C, 0x15, 0x15, 0, 0},
7777 {0x0D, 0x4f, 0x4f, 1, 1},
7778 {0x0E, 0x5, 0x5, 1, 1},
7779 {0x0F, 0x4f, 0x4f, 1, 1},
7780 {0x10, 0x5, 0x5, 1, 1},
7781 {0x11, 0xd0, 0xd0, 0, 0},
7782 {0x12, 0x2, 0x2, 0, 0},
7783 {0x13, 0, 0, 0, 0},
7784 {0x14, 0x40, 0x40, 0, 0},
7785 {0x15, 0, 0, 0, 0},
7786 {0x16, 0, 0, 0, 0},
7787 {0x17, 0, 0, 0, 0},
7788 {0x18, 0, 0, 0, 0},
7789 {0x19, 0, 0, 0, 0},
7790 {0x1A, 0, 0, 0, 0},
7791 {0x1B, 0, 0, 0, 0},
7792 {0x1C, 0, 0, 0, 0},
7793 {0x1D, 0xc0, 0xc0, 0, 0},
7794 {0x1E, 0xff, 0xff, 0, 0},
7795 {0x1F, 0xc0, 0xc0, 0, 0},
7796 {0x20, 0xff, 0xff, 0, 0},
7797 {0x21, 0xc0, 0xc0, 0, 0},
7798 {0x22, 0, 0, 0, 0},
7799 {0x23, 0x2c, 0x2c, 0, 0},
7800 {0x24, 0, 0, 0, 0},
7801 {0x25, 0, 0, 0, 0},
7802 {0x26, 0, 0, 0, 0},
7803 {0x27, 0, 0, 0, 0},
7804 {0x28, 0, 0, 0, 0},
7805 {0x29, 0, 0, 0, 0},
7806 {0x2A, 0, 0, 0, 0},
7807 {0x2B, 0, 0, 0, 0},
7808 {0x2C, 0, 0, 0, 0},
7809 {0x2D, 0xa4, 0xa4, 0, 0},
7810 {0x2E, 0x38, 0x38, 0, 0},
7811 {0x2F, 0, 0, 0, 0},
7812 {0x30, 0x4, 0x4, 1, 1},
7813 {0x31, 0, 0, 0, 0},
7814 {0x32, 0xa, 0xa, 0, 0},
7815 {0x33, 0x87, 0x87, 0, 0},
7816 {0x34, 0x9, 0x9, 0, 0},
7817 {0x35, 0x70, 0x70, 0, 0},
7818 {0x36, 0x11, 0x11, 0, 0},
7819 {0x37, 0x18, 0x18, 1, 1},
7820 {0x38, 0x6, 0x6, 0, 0},
7821 {0x39, 0x4, 0x4, 1, 1},
7822 {0x3A, 0x6, 0x6, 0, 0},
7823 {0x3B, 0x9e, 0x9e, 0, 0},
7824 {0x3C, 0x9, 0x9, 0, 0},
7825 {0x3D, 0xc8, 0xc8, 1, 1},
7826 {0x3E, 0x88, 0x88, 0, 0},
7827 {0x3F, 0, 0, 0, 0},
7828 {0x40, 0, 0, 0, 0},
7829 {0x41, 0, 0, 0, 0},
7830 {0x42, 0x1, 0x1, 0, 0},
7831 {0x43, 0x2, 0x2, 0, 0},
7832 {0x44, 0x96, 0x96, 0, 0},
7833 {0x45, 0x3e, 0x3e, 0, 0},
7834 {0x46, 0x3e, 0x3e, 0, 0},
7835 {0x47, 0x13, 0x13, 0, 0},
7836 {0x48, 0x2, 0x2, 0, 0},
7837 {0x49, 0x15, 0x15, 0, 0},
7838 {0x4A, 0x7, 0x7, 0, 0},
7839 {0x4B, 0, 0, 0, 0},
7840 {0x4C, 0, 0, 0, 0},
7841 {0x4D, 0, 0, 0, 0},
7842 {0x4E, 0, 0, 0, 0},
7843 {0x4F, 0, 0, 0, 0},
7844 {0x50, 0x8, 0x8, 0, 0},
7845 {0x51, 0x8, 0x8, 0, 0},
7846 {0x52, 0x6, 0x6, 0, 0},
7847 {0x53, 0x84, 0x84, 1, 1},
7848 {0x54, 0xc3, 0xc3, 0, 0},
7849 {0x55, 0x8f, 0x8f, 0, 0},
7850 {0x56, 0xff, 0xff, 0, 0},
7851 {0x57, 0xff, 0xff, 0, 0},
7852 {0x58, 0x88, 0x88, 0, 0},
7853 {0x59, 0x88, 0x88, 0, 0},
7854 {0x5A, 0, 0, 0, 0},
7855 {0x5B, 0xcc, 0xcc, 0, 0},
7856 {0x5C, 0x6, 0x6, 0, 0},
7857 {0x5D, 0x80, 0x80, 0, 0},
7858 {0x5E, 0x80, 0x80, 0, 0},
7859 {0x5F, 0xf8, 0xf8, 0, 0},
7860 {0x60, 0x88, 0x88, 0, 0},
7861 {0x61, 0x88, 0x88, 0, 0},
7862 {0x62, 0x88, 0x8, 1, 1},
7863 {0x63, 0x88, 0x88, 0, 0},
7864 {0x64, 0, 0, 0, 0},
7865 {0x65, 0x1, 0x1, 1, 1},
7866 {0x66, 0x8a, 0x8a, 0, 0},
7867 {0x67, 0x8, 0x8, 0, 0},
7868 {0x68, 0x83, 0x83, 0, 0},
7869 {0x69, 0x6, 0x6, 0, 0},
7870 {0x6A, 0xa0, 0xa0, 0, 0},
7871 {0x6B, 0xa, 0xa, 0, 0},
7872 {0x6C, 0x87, 0x87, 1, 1},
7873 {0x6D, 0x2a, 0x2a, 0, 0},
7874 {0x6E, 0x2a, 0x2a, 0, 0},
7875 {0x6F, 0x2a, 0x2a, 0, 0},
7876 {0x70, 0x2a, 0x2a, 0, 0},
7877 {0x71, 0x18, 0x18, 0, 0},
7878 {0x72, 0x6a, 0x6a, 1, 1},
7879 {0x73, 0xab, 0xab, 1, 1},
7880 {0x74, 0x13, 0x13, 1, 1},
7881 {0x75, 0xc1, 0xc1, 1, 1},
7882 {0x76, 0xaa, 0xaa, 1, 1},
7883 {0x77, 0x87, 0x87, 1, 1},
7884 {0x78, 0, 0, 0, 0},
7885 {0x79, 0x6, 0x6, 0, 0},
7886 {0x7A, 0x7, 0x7, 0, 0},
7887 {0x7B, 0x7, 0x7, 0, 0},
7888 {0x7C, 0x15, 0x15, 0, 0},
7889 {0x7D, 0x55, 0x55, 0, 0},
7890 {0x7E, 0x97, 0x97, 1, 1},
7891 {0x7F, 0x8, 0x8, 0, 0},
7892 {0x80, 0x14, 0x14, 1, 1},
7893 {0x81, 0x33, 0x33, 0, 0},
7894 {0x82, 0x88, 0x88, 0, 0},
7895 {0x83, 0x6, 0x6, 0, 0},
7896 {0x84, 0x3, 0x3, 1, 1},
7897 {0x85, 0xa, 0xa, 0, 0},
7898 {0x86, 0x3, 0x3, 1, 1},
7899 {0x87, 0x2a, 0x2a, 0, 0},
7900 {0x88, 0xa4, 0xa4, 0, 0},
7901 {0x89, 0x18, 0x18, 0, 0},
7902 {0x8A, 0x28, 0x28, 0, 0},
7903 {0x8B, 0, 0, 0, 0},
7904 {0x8C, 0x4a, 0x4a, 0, 0},
7905 {0x8D, 0, 0, 0, 0},
7906 {0x8E, 0xf8, 0xf8, 0, 0},
7907 {0x8F, 0x88, 0x88, 0, 0},
7908 {0x90, 0x88, 0x88, 0, 0},
7909 {0x91, 0x88, 0x8, 1, 1},
7910 {0x92, 0x88, 0x88, 0, 0},
7911 {0x93, 0, 0, 0, 0},
7912 {0x94, 0x1, 0x1, 1, 1},
7913 {0x95, 0x8a, 0x8a, 0, 0},
7914 {0x96, 0x8, 0x8, 0, 0},
7915 {0x97, 0x83, 0x83, 0, 0},
7916 {0x98, 0x6, 0x6, 0, 0},
7917 {0x99, 0xa0, 0xa0, 0, 0},
7918 {0x9A, 0xa, 0xa, 0, 0},
7919 {0x9B, 0x87, 0x87, 1, 1},
7920 {0x9C, 0x2a, 0x2a, 0, 0},
7921 {0x9D, 0x2a, 0x2a, 0, 0},
7922 {0x9E, 0x2a, 0x2a, 0, 0},
7923 {0x9F, 0x2a, 0x2a, 0, 0},
7924 {0xA0, 0x18, 0x18, 0, 0},
7925 {0xA1, 0x6a, 0x6a, 1, 1},
7926 {0xA2, 0xab, 0xab, 1, 1},
7927 {0xA3, 0x13, 0x13, 1, 1},
7928 {0xA4, 0xc1, 0xc1, 1, 1},
7929 {0xA5, 0xaa, 0xaa, 1, 1},
7930 {0xA6, 0x87, 0x87, 1, 1},
7931 {0xA7, 0, 0, 0, 0},
7932 {0xA8, 0x6, 0x6, 0, 0},
7933 {0xA9, 0x7, 0x7, 0, 0},
7934 {0xAA, 0x7, 0x7, 0, 0},
7935 {0xAB, 0x15, 0x15, 0, 0},
7936 {0xAC, 0x55, 0x55, 0, 0},
7937 {0xAD, 0x97, 0x97, 1, 1},
7938 {0xAE, 0x8, 0x8, 0, 0},
7939 {0xAF, 0x14, 0x14, 1, 1},
7940 {0xB0, 0x33, 0x33, 0, 0},
7941 {0xB1, 0x88, 0x88, 0, 0},
7942 {0xB2, 0x6, 0x6, 0, 0},
7943 {0xB3, 0x3, 0x3, 1, 1},
7944 {0xB4, 0xa, 0xa, 0, 0},
7945 {0xB5, 0x3, 0x3, 1, 1},
7946 {0xB6, 0x2a, 0x2a, 0, 0},
7947 {0xB7, 0xa4, 0xa4, 0, 0},
7948 {0xB8, 0x18, 0x18, 0, 0},
7949 {0xB9, 0x28, 0x28, 0, 0},
7950 {0xBA, 0, 0, 0, 0},
7951 {0xBB, 0x4a, 0x4a, 0, 0},
7952 {0xBC, 0, 0, 0, 0},
7953 {0xBD, 0x71, 0x71, 0, 0},
7954 {0xBE, 0x72, 0x72, 0, 0},
7955 {0xBF, 0x73, 0x73, 0, 0},
7956 {0xC0, 0x74, 0x74, 0, 0},
7957 {0xC1, 0x75, 0x75, 0, 0},
7958 {0xC2, 0x76, 0x76, 0, 0},
7959 {0xC3, 0x77, 0x77, 0, 0},
7960 {0xC4, 0x78, 0x78, 0, 0},
7961 {0xC5, 0x79, 0x79, 0, 0},
7962 {0xC6, 0x7a, 0x7a, 0, 0},
7963 {0xC7, 0, 0, 0, 0},
7964 {0xC8, 0, 0, 0, 0},
7965 {0xC9, 0, 0, 0, 0},
7966 {0xCA, 0, 0, 0, 0},
7967 {0xCB, 0, 0, 0, 0},
7968 {0xCC, 0, 0, 0, 0},
7969 {0xCD, 0, 0, 0, 0},
7970 {0xCE, 0x6, 0x6, 0, 0},
7971 {0xCF, 0, 0, 0, 0},
7972 {0xD0, 0, 0, 0, 0},
7973 {0xD1, 0x18, 0x18, 0, 0},
7974 {0xD2, 0x88, 0x88, 0, 0},
7975 {0xD3, 0, 0, 0, 0},
7976 {0xD4, 0, 0, 0, 0},
7977 {0xD5, 0, 0, 0, 0},
7978 {0xD6, 0, 0, 0, 0},
7979 {0xD7, 0, 0, 0, 0},
7980 {0xD8, 0, 0, 0, 0},
7981 {0xD9, 0, 0, 0, 0},
7982 {0xDA, 0x6, 0x6, 0, 0},
7983 {0xDB, 0, 0, 0, 0},
7984 {0xDC, 0, 0, 0, 0},
7985 {0xDD, 0x18, 0x18, 0, 0},
7986 {0xDE, 0x88, 0x88, 0, 0},
7987 {0xDF, 0, 0, 0, 0},
7988 {0xE0, 0, 0, 0, 0},
7989 {0xE1, 0, 0, 0, 0},
7990 {0xE2, 0, 0, 0, 0},
7991 {0xFFFF, 0, 0, 0, 0},
7992};
7993
7994static struct radio_regs regs_SYN_2056[] = {
7995 {0x02, 0, 0, 0, 0},
7996 {0x03, 0, 0, 0, 0},
7997 {0x04, 0, 0, 0, 0},
7998 {0x05, 0, 0, 0, 0},
7999 {0x06, 0, 0, 0, 0},
8000 {0x07, 0, 0, 0, 0},
8001 {0x08, 0, 0, 0, 0},
8002 {0x09, 0x1, 0x1, 0, 0},
8003 {0x0A, 0, 0, 0, 0},
8004 {0x0B, 0, 0, 0, 0},
8005 {0x0C, 0, 0, 0, 0},
8006 {0x0D, 0, 0, 0, 0},
8007 {0x0E, 0, 0, 0, 0},
8008 {0x0F, 0, 0, 0, 0},
8009 {0x10, 0, 0, 0, 0},
8010 {0x11, 0, 0, 0, 0},
8011 {0x12, 0, 0, 0, 0},
8012 {0x13, 0, 0, 0, 0},
8013 {0x14, 0, 0, 0, 0},
8014 {0x15, 0, 0, 0, 0},
8015 {0x16, 0, 0, 0, 0},
8016 {0x17, 0, 0, 0, 0},
8017 {0x18, 0, 0, 0, 0},
8018 {0x19, 0, 0, 0, 0},
8019 {0x1A, 0, 0, 0, 0},
8020 {0x1B, 0, 0, 0, 0},
8021 {0x1C, 0, 0, 0, 0},
8022 {0x1D, 0, 0, 0, 0},
8023 {0x1E, 0, 0, 0, 0},
8024 {0x1F, 0, 0, 0, 0},
8025 {0x20, 0, 0, 0, 0},
8026 {0x21, 0, 0, 0, 0},
8027 {0x22, 0x60, 0x60, 0, 0},
8028 {0x23, 0x6, 0x6, 0, 0},
8029 {0x24, 0xc, 0xc, 0, 0},
8030 {0x25, 0, 0, 0, 0},
8031 {0x26, 0, 0, 0, 0},
8032 {0x27, 0, 0, 0, 0},
8033 {0x28, 0x1, 0x1, 0, 0},
8034 {0x29, 0, 0, 0, 0},
8035 {0x2A, 0, 0, 0, 0},
8036 {0x2B, 0, 0, 0, 0},
8037 {0x2C, 0, 0, 0, 0},
8038 {0x2D, 0, 0, 0, 0},
8039 {0x2E, 0xd, 0xd, 0, 0},
8040 {0x2F, 0x1f, 0x1f, 0, 0},
8041 {0x30, 0x15, 0x15, 0, 0},
8042 {0x31, 0xf, 0xf, 0, 0},
8043 {0x32, 0, 0, 0, 0},
8044 {0x33, 0, 0, 0, 0},
8045 {0x34, 0, 0, 0, 0},
8046 {0x35, 0, 0, 0, 0},
8047 {0x36, 0, 0, 0, 0},
8048 {0x37, 0, 0, 0, 0},
8049 {0x38, 0, 0, 0, 0},
8050 {0x39, 0, 0, 0, 0},
8051 {0x3A, 0, 0, 0, 0},
8052 {0x3B, 0, 0, 0, 0},
8053 {0x3C, 0x13, 0x13, 0, 0},
8054 {0x3D, 0xf, 0xf, 0, 0},
8055 {0x3E, 0x18, 0x18, 0, 0},
8056 {0x3F, 0, 0, 0, 0},
8057 {0x40, 0, 0, 0, 0},
8058 {0x41, 0x20, 0x20, 0, 0},
8059 {0x42, 0x20, 0x20, 0, 0},
8060 {0x43, 0, 0, 0, 0},
8061 {0x44, 0x77, 0x77, 0, 0},
8062 {0x45, 0x7, 0x7, 0, 0},
8063 {0x46, 0x1, 0x1, 0, 0},
8064 {0x47, 0x4, 0x4, 0, 0},
8065 {0x48, 0xf, 0xf, 0, 0},
8066 {0x49, 0x30, 0x30, 0, 0},
8067 {0x4A, 0x32, 0x32, 0, 0},
8068 {0x4B, 0xd, 0xd, 0, 0},
8069 {0x4C, 0xd, 0xd, 0, 0},
8070 {0x4D, 0x4, 0x4, 0, 0},
8071 {0x4E, 0x6, 0x6, 0, 0},
8072 {0x4F, 0x1, 0x1, 0, 0},
8073 {0x50, 0x1c, 0x1c, 0, 0},
8074 {0x51, 0x2, 0x2, 0, 0},
8075 {0x52, 0x2, 0x2, 0, 0},
8076 {0x53, 0xf7, 0xf7, 1, 1},
8077 {0x54, 0xb4, 0xb4, 0, 0},
8078 {0x55, 0xd2, 0xd2, 0, 0},
8079 {0x56, 0, 0, 0, 0},
8080 {0x57, 0, 0, 0, 0},
8081 {0x58, 0x4, 0x4, 0, 0},
8082 {0x59, 0x96, 0x96, 0, 0},
8083 {0x5A, 0x3e, 0x3e, 0, 0},
8084 {0x5B, 0x3e, 0x3e, 0, 0},
8085 {0x5C, 0x13, 0x13, 0, 0},
8086 {0x5D, 0x2, 0x2, 0, 0},
8087 {0x5E, 0, 0, 0, 0},
8088 {0x5F, 0x7, 0x7, 0, 0},
8089 {0x60, 0x7, 0x7, 1, 1},
8090 {0x61, 0x8, 0x8, 0, 0},
8091 {0x62, 0x3, 0x3, 0, 0},
8092 {0x63, 0, 0, 0, 0},
8093 {0x64, 0, 0, 0, 0},
8094 {0x65, 0, 0, 0, 0},
8095 {0x66, 0, 0, 0, 0},
8096 {0x67, 0, 0, 0, 0},
8097 {0x68, 0x40, 0x40, 0, 0},
8098 {0x69, 0, 0, 0, 0},
8099 {0x6A, 0, 0, 0, 0},
8100 {0x6B, 0, 0, 0, 0},
8101 {0x6C, 0, 0, 0, 0},
8102 {0x6D, 0x1, 0x1, 0, 0},
8103 {0x6E, 0, 0, 0, 0},
8104 {0x6F, 0, 0, 0, 0},
8105 {0x70, 0x60, 0x60, 0, 0},
8106 {0x71, 0x66, 0x66, 0, 0},
8107 {0x72, 0xc, 0xc, 0, 0},
8108 {0x73, 0x66, 0x66, 0, 0},
8109 {0x74, 0x8f, 0x8f, 1, 1},
8110 {0x75, 0, 0, 0, 0},
8111 {0x76, 0xcc, 0xcc, 0, 0},
8112 {0x77, 0x1, 0x1, 0, 0},
8113 {0x78, 0x66, 0x66, 0, 0},
8114 {0x79, 0x66, 0x66, 0, 0},
8115 {0x7A, 0, 0, 0, 0},
8116 {0x7B, 0, 0, 0, 0},
8117 {0x7C, 0, 0, 0, 0},
8118 {0x7D, 0, 0, 0, 0},
8119 {0x7E, 0, 0, 0, 0},
8120 {0x7F, 0, 0, 0, 0},
8121 {0x80, 0, 0, 0, 0},
8122 {0x81, 0, 0, 0, 0},
8123 {0x82, 0, 0, 0, 0},
8124 {0x83, 0, 0, 0, 0},
8125 {0x84, 0, 0, 0, 0},
8126 {0x85, 0xff, 0xff, 0, 0},
8127 {0x86, 0, 0, 0, 0},
8128 {0x87, 0, 0, 0, 0},
8129 {0x88, 0, 0, 0, 0},
8130 {0x89, 0, 0, 0, 0},
8131 {0x8A, 0, 0, 0, 0},
8132 {0x8B, 0, 0, 0, 0},
8133 {0x8C, 0, 0, 0, 0},
8134 {0x8D, 0, 0, 0, 0},
8135 {0x8E, 0, 0, 0, 0},
8136 {0x8F, 0, 0, 0, 0},
8137 {0x90, 0, 0, 0, 0},
8138 {0x91, 0, 0, 0, 0},
8139 {0x92, 0, 0, 0, 0},
8140 {0x93, 0, 0, 0, 0},
8141 {0x94, 0, 0, 0, 0},
8142 {0x95, 0, 0, 0, 0},
8143 {0x96, 0, 0, 0, 0},
8144 {0x97, 0, 0, 0, 0},
8145 {0x98, 0, 0, 0, 0},
8146 {0x99, 0, 0, 0, 0},
8147 {0x9A, 0, 0, 0, 0},
8148 {0x9B, 0, 0, 0, 0},
8149 {0x9C, 0, 0, 0, 0},
8150 {0x9D, 0, 0, 0, 0},
8151 {0x9E, 0, 0, 0, 0},
8152 {0x9F, 0x6, 0x6, 0, 0},
8153 {0xA0, 0x66, 0x66, 0, 0},
8154 {0xA1, 0x66, 0x66, 0, 0},
8155 {0xA2, 0x66, 0x66, 0, 0},
8156 {0xA3, 0x66, 0x66, 0, 0},
8157 {0xA4, 0x66, 0x66, 0, 0},
8158 {0xA5, 0x66, 0x66, 0, 0},
8159 {0xA6, 0x66, 0x66, 0, 0},
8160 {0xA7, 0x66, 0x66, 0, 0},
8161 {0xA8, 0x66, 0x66, 0, 0},
8162 {0xA9, 0x66, 0x66, 0, 0},
8163 {0xAA, 0x66, 0x66, 0, 0},
8164 {0xAB, 0x66, 0x66, 0, 0},
8165 {0xAC, 0x66, 0x66, 0, 0},
8166 {0xAD, 0x66, 0x66, 0, 0},
8167 {0xAE, 0x66, 0x66, 0, 0},
8168 {0xAF, 0x66, 0x66, 0, 0},
8169 {0xB0, 0x66, 0x66, 0, 0},
8170 {0xB1, 0x66, 0x66, 0, 0},
8171 {0xB2, 0x66, 0x66, 0, 0},
8172 {0xB3, 0xa, 0xa, 0, 0},
8173 {0xB4, 0, 0, 0, 0},
8174 {0xB5, 0, 0, 0, 0},
8175 {0xB6, 0, 0, 0, 0},
8176 {0xFFFF, 0, 0, 0, 0}
8177};
8178
8179static struct radio_regs regs_TX_2056[] = {
8180 {0x02, 0, 0, 0, 0},
8181 {0x03, 0, 0, 0, 0},
8182 {0x04, 0, 0, 0, 0},
8183 {0x05, 0, 0, 0, 0},
8184 {0x06, 0, 0, 0, 0},
8185 {0x07, 0, 0, 0, 0},
8186 {0x08, 0, 0, 0, 0},
8187 {0x09, 0, 0, 0, 0},
8188 {0x0A, 0, 0, 0, 0},
8189 {0x0B, 0, 0, 0, 0},
8190 {0x0C, 0, 0, 0, 0},
8191 {0x0D, 0, 0, 0, 0},
8192 {0x0E, 0, 0, 0, 0},
8193 {0x0F, 0, 0, 0, 0},
8194 {0x10, 0, 0, 0, 0},
8195 {0x11, 0, 0, 0, 0},
8196 {0x12, 0, 0, 0, 0},
8197 {0x13, 0, 0, 0, 0},
8198 {0x14, 0, 0, 0, 0},
8199 {0x15, 0, 0, 0, 0},
8200 {0x16, 0, 0, 0, 0},
8201 {0x17, 0, 0, 0, 0},
8202 {0x18, 0, 0, 0, 0},
8203 {0x19, 0, 0, 0, 0},
8204 {0x1A, 0, 0, 0, 0},
8205 {0x1B, 0, 0, 0, 0},
8206 {0x1C, 0, 0, 0, 0},
8207 {0x1D, 0, 0, 0, 0},
8208 {0x1E, 0, 0, 0, 0},
8209 {0x1F, 0, 0, 0, 0},
8210 {0x20, 0, 0, 0, 0},
8211 {0x21, 0x88, 0x88, 0, 0},
8212 {0x22, 0x88, 0x88, 0, 0},
8213 {0x23, 0x88, 0x88, 0, 0},
8214 {0x24, 0x88, 0x88, 0, 0},
8215 {0x25, 0xc, 0xc, 0, 0},
8216 {0x26, 0, 0, 0, 0},
8217 {0x27, 0x3, 0x3, 0, 0},
8218 {0x28, 0, 0, 0, 0},
8219 {0x29, 0x3, 0x3, 0, 0},
8220 {0x2A, 0x37, 0x37, 0, 0},
8221 {0x2B, 0x3, 0x3, 0, 0},
8222 {0x2C, 0, 0, 0, 0},
8223 {0x2D, 0, 0, 0, 0},
8224 {0x2E, 0x1, 0x1, 0, 0},
8225 {0x2F, 0x1, 0x1, 0, 0},
8226 {0x30, 0, 0, 0, 0},
8227 {0x31, 0, 0, 0, 0},
8228 {0x32, 0, 0, 0, 0},
8229 {0x33, 0x11, 0x11, 0, 0},
8230 {0x34, 0x11, 0x11, 0, 0},
8231 {0x35, 0, 0, 0, 0},
8232 {0x36, 0, 0, 0, 0},
8233 {0x37, 0x3, 0x3, 0, 0},
8234 {0x38, 0xf, 0xf, 0, 0},
8235 {0x39, 0, 0, 0, 0},
8236 {0x3A, 0x2d, 0x2d, 0, 0},
8237 {0x3B, 0, 0, 0, 0},
8238 {0x3C, 0x6e, 0x6e, 0, 0},
8239 {0x3D, 0xf0, 0xf0, 1, 1},
8240 {0x3E, 0, 0, 0, 0},
8241 {0x3F, 0, 0, 0, 0},
8242 {0x40, 0, 0, 0, 0},
8243 {0x41, 0x3, 0x3, 0, 0},
8244 {0x42, 0x3, 0x3, 0, 0},
8245 {0x43, 0, 0, 0, 0},
8246 {0x44, 0x1e, 0x1e, 0, 0},
8247 {0x45, 0, 0, 0, 0},
8248 {0x46, 0x6e, 0x6e, 0, 0},
8249 {0x47, 0xf0, 0xf0, 1, 1},
8250 {0x48, 0, 0, 0, 0},
8251 {0x49, 0x2, 0x2, 0, 0},
8252 {0x4A, 0xff, 0xff, 1, 1},
8253 {0x4B, 0xc, 0xc, 0, 0},
8254 {0x4C, 0, 0, 0, 0},
8255 {0x4D, 0x38, 0x38, 0, 0},
8256 {0x4E, 0x70, 0x70, 1, 1},
8257 {0x4F, 0x2, 0x2, 0, 0},
8258 {0x50, 0x88, 0x88, 0, 0},
8259 {0x51, 0xc, 0xc, 0, 0},
8260 {0x52, 0, 0, 0, 0},
8261 {0x53, 0x8, 0x8, 0, 0},
8262 {0x54, 0x70, 0x70, 1, 1},
8263 {0x55, 0x2, 0x2, 0, 0},
8264 {0x56, 0xff, 0xff, 1, 1},
8265 {0x57, 0, 0, 0, 0},
8266 {0x58, 0x83, 0x83, 0, 0},
8267 {0x59, 0x77, 0x77, 1, 1},
8268 {0x5A, 0, 0, 0, 0},
8269 {0x5B, 0x2, 0x2, 0, 0},
8270 {0x5C, 0x88, 0x88, 0, 0},
8271 {0x5D, 0, 0, 0, 0},
8272 {0x5E, 0x8, 0x8, 0, 0},
8273 {0x5F, 0x77, 0x77, 1, 1},
8274 {0x60, 0x1, 0x1, 0, 0},
8275 {0x61, 0, 0, 0, 0},
8276 {0x62, 0x7, 0x7, 0, 0},
8277 {0x63, 0, 0, 0, 0},
8278 {0x64, 0x7, 0x7, 0, 0},
8279 {0x65, 0, 0, 0, 0},
8280 {0x66, 0, 0, 0, 0},
8281 {0x67, 0x74, 0x74, 1, 1},
8282 {0x68, 0, 0, 0, 0},
8283 {0x69, 0xa, 0xa, 0, 0},
8284 {0x6A, 0, 0, 0, 0},
8285 {0x6B, 0, 0, 0, 0},
8286 {0x6C, 0, 0, 0, 0},
8287 {0x6D, 0, 0, 0, 0},
8288 {0x6E, 0, 0, 0, 0},
8289 {0x6F, 0, 0, 0, 0},
8290 {0x70, 0, 0, 0, 0},
8291 {0x71, 0x2, 0x2, 0, 0},
8292 {0x72, 0, 0, 0, 0},
8293 {0x73, 0, 0, 0, 0},
8294 {0x74, 0xe, 0xe, 0, 0},
8295 {0x75, 0xe, 0xe, 0, 0},
8296 {0x76, 0xe, 0xe, 0, 0},
8297 {0x77, 0x13, 0x13, 0, 0},
8298 {0x78, 0x13, 0x13, 0, 0},
8299 {0x79, 0x1b, 0x1b, 0, 0},
8300 {0x7A, 0x1b, 0x1b, 0, 0},
8301 {0x7B, 0x55, 0x55, 0, 0},
8302 {0x7C, 0x5b, 0x5b, 0, 0},
8303 {0x7D, 0, 0, 0, 0},
8304 {0x7E, 0, 0, 0, 0},
8305 {0x7F, 0, 0, 0, 0},
8306 {0x80, 0, 0, 0, 0},
8307 {0x81, 0, 0, 0, 0},
8308 {0x82, 0, 0, 0, 0},
8309 {0x83, 0, 0, 0, 0},
8310 {0x84, 0, 0, 0, 0},
8311 {0x85, 0, 0, 0, 0},
8312 {0x86, 0, 0, 0, 0},
8313 {0x87, 0, 0, 0, 0},
8314 {0x88, 0, 0, 0, 0},
8315 {0x89, 0, 0, 0, 0},
8316 {0x8A, 0, 0, 0, 0},
8317 {0x8B, 0, 0, 0, 0},
8318 {0x8C, 0, 0, 0, 0},
8319 {0x8D, 0, 0, 0, 0},
8320 {0x8E, 0, 0, 0, 0},
8321 {0x8F, 0, 0, 0, 0},
8322 {0x90, 0, 0, 0, 0},
8323 {0x91, 0, 0, 0, 0},
8324 {0x92, 0, 0, 0, 0},
8325 {0xFFFF, 0, 0, 0, 0}
8326};
8327
8328static struct radio_regs regs_RX_2056[] = {
8329 {0x02, 0, 0, 0, 0},
8330 {0x03, 0, 0, 0, 0},
8331 {0x04, 0, 0, 0, 0},
8332 {0x05, 0, 0, 0, 0},
8333 {0x06, 0, 0, 0, 0},
8334 {0x07, 0, 0, 0, 0},
8335 {0x08, 0, 0, 0, 0},
8336 {0x09, 0, 0, 0, 0},
8337 {0x0A, 0, 0, 0, 0},
8338 {0x0B, 0, 0, 0, 0},
8339 {0x0C, 0, 0, 0, 0},
8340 {0x0D, 0, 0, 0, 0},
8341 {0x0E, 0, 0, 0, 0},
8342 {0x0F, 0, 0, 0, 0},
8343 {0x10, 0, 0, 0, 0},
8344 {0x11, 0, 0, 0, 0},
8345 {0x12, 0, 0, 0, 0},
8346 {0x13, 0, 0, 0, 0},
8347 {0x14, 0, 0, 0, 0},
8348 {0x15, 0, 0, 0, 0},
8349 {0x16, 0, 0, 0, 0},
8350 {0x17, 0, 0, 0, 0},
8351 {0x18, 0, 0, 0, 0},
8352 {0x19, 0, 0, 0, 0},
8353 {0x1A, 0, 0, 0, 0},
8354 {0x1B, 0, 0, 0, 0},
8355 {0x1C, 0, 0, 0, 0},
8356 {0x1D, 0, 0, 0, 0},
8357 {0x1E, 0, 0, 0, 0},
8358 {0x1F, 0, 0, 0, 0},
8359 {0x20, 0x3, 0x3, 0, 0},
8360 {0x21, 0, 0, 0, 0},
8361 {0x22, 0, 0, 0, 0},
8362 {0x23, 0x90, 0x90, 0, 0},
8363 {0x24, 0x55, 0x55, 0, 0},
8364 {0x25, 0x15, 0x15, 0, 0},
8365 {0x26, 0x5, 0x5, 0, 0},
8366 {0x27, 0x15, 0x15, 0, 0},
8367 {0x28, 0x5, 0x5, 0, 0},
8368 {0x29, 0x20, 0x20, 0, 0},
8369 {0x2A, 0x11, 0x11, 0, 0},
8370 {0x2B, 0x90, 0x90, 0, 0},
8371 {0x2C, 0, 0, 0, 0},
8372 {0x2D, 0x88, 0x88, 0, 0},
8373 {0x2E, 0x32, 0x32, 0, 0},
8374 {0x2F, 0x77, 0x77, 0, 0},
8375 {0x30, 0x17, 0x17, 1, 1},
8376 {0x31, 0xff, 0xff, 1, 1},
8377 {0x32, 0x20, 0x20, 0, 0},
8378 {0x33, 0, 0, 0, 0},
8379 {0x34, 0x88, 0x88, 0, 0},
8380 {0x35, 0x32, 0x32, 0, 0},
8381 {0x36, 0x77, 0x77, 0, 0},
8382 {0x37, 0x17, 0x17, 1, 1},
8383 {0x38, 0xf0, 0xf0, 1, 1},
8384 {0x39, 0x20, 0x20, 0, 0},
8385 {0x3A, 0x8, 0x8, 0, 0},
8386 {0x3B, 0x99, 0x99, 0, 0},
8387 {0x3C, 0, 0, 0, 0},
8388 {0x3D, 0x44, 0x44, 1, 1},
8389 {0x3E, 0, 0, 0, 0},
8390 {0x3F, 0x44, 0x44, 0, 0},
8391 {0x40, 0xf, 0xf, 1, 1},
8392 {0x41, 0x6, 0x6, 0, 0},
8393 {0x42, 0x4, 0x4, 0, 0},
8394 {0x43, 0x50, 0x50, 1, 1},
8395 {0x44, 0x8, 0x8, 0, 0},
8396 {0x45, 0x99, 0x99, 0, 0},
8397 {0x46, 0, 0, 0, 0},
8398 {0x47, 0x11, 0x11, 0, 0},
8399 {0x48, 0, 0, 0, 0},
8400 {0x49, 0x44, 0x44, 0, 0},
8401 {0x4A, 0x7, 0x7, 0, 0},
8402 {0x4B, 0x6, 0x6, 0, 0},
8403 {0x4C, 0x4, 0x4, 0, 0},
8404 {0x4D, 0, 0, 0, 0},
8405 {0x4E, 0, 0, 0, 0},
8406 {0x4F, 0x66, 0x66, 0, 0},
8407 {0x50, 0x66, 0x66, 0, 0},
8408 {0x51, 0x57, 0x57, 0, 0},
8409 {0x52, 0x57, 0x57, 0, 0},
8410 {0x53, 0x44, 0x44, 0, 0},
8411 {0x54, 0, 0, 0, 0},
8412 {0x55, 0, 0, 0, 0},
8413 {0x56, 0x8, 0x8, 0, 0},
8414 {0x57, 0x8, 0x8, 0, 0},
8415 {0x58, 0x7, 0x7, 0, 0},
8416 {0x59, 0x22, 0x22, 0, 0},
8417 {0x5A, 0x22, 0x22, 0, 0},
8418 {0x5B, 0x2, 0x2, 0, 0},
8419 {0x5C, 0x23, 0x23, 0, 0},
8420 {0x5D, 0x7, 0x7, 0, 0},
8421 {0x5E, 0x55, 0x55, 0, 0},
8422 {0x5F, 0x23, 0x23, 0, 0},
8423 {0x60, 0x41, 0x41, 0, 0},
8424 {0x61, 0x1, 0x1, 0, 0},
8425 {0x62, 0xa, 0xa, 0, 0},
8426 {0x63, 0, 0, 0, 0},
8427 {0x64, 0, 0, 0, 0},
8428 {0x65, 0, 0, 0, 0},
8429 {0x66, 0, 0, 0, 0},
8430 {0x67, 0, 0, 0, 0},
8431 {0x68, 0, 0, 0, 0},
8432 {0x69, 0, 0, 0, 0},
8433 {0x6A, 0, 0, 0, 0},
8434 {0x6B, 0xc, 0xc, 0, 0},
8435 {0x6C, 0, 0, 0, 0},
8436 {0x6D, 0, 0, 0, 0},
8437 {0x6E, 0, 0, 0, 0},
8438 {0x6F, 0, 0, 0, 0},
8439 {0x70, 0, 0, 0, 0},
8440 {0x71, 0, 0, 0, 0},
8441 {0x72, 0x22, 0x22, 0, 0},
8442 {0x73, 0x22, 0x22, 0, 0},
8443 {0x74, 0x2, 0x2, 0, 0},
8444 {0x75, 0xa, 0xa, 0, 0},
8445 {0x76, 0x1, 0x1, 0, 0},
8446 {0x77, 0x22, 0x22, 0, 0},
8447 {0x78, 0x30, 0x30, 0, 0},
8448 {0x79, 0, 0, 0, 0},
8449 {0x7A, 0, 0, 0, 0},
8450 {0x7B, 0, 0, 0, 0},
8451 {0x7C, 0, 0, 0, 0},
8452 {0x7D, 0, 0, 0, 0},
8453 {0x7E, 0, 0, 0, 0},
8454 {0x7F, 0, 0, 0, 0},
8455 {0x80, 0, 0, 0, 0},
8456 {0x81, 0, 0, 0, 0},
8457 {0x82, 0, 0, 0, 0},
8458 {0x83, 0, 0, 0, 0},
8459 {0x84, 0, 0, 0, 0},
8460 {0x85, 0, 0, 0, 0},
8461 {0x86, 0, 0, 0, 0},
8462 {0x87, 0, 0, 0, 0},
8463 {0x88, 0, 0, 0, 0},
8464 {0x89, 0, 0, 0, 0},
8465 {0x8A, 0, 0, 0, 0},
8466 {0x8B, 0, 0, 0, 0},
8467 {0x8C, 0, 0, 0, 0},
8468 {0x8D, 0, 0, 0, 0},
8469 {0x8E, 0, 0, 0, 0},
8470 {0x8F, 0, 0, 0, 0},
8471 {0x90, 0, 0, 0, 0},
8472 {0x91, 0, 0, 0, 0},
8473 {0x92, 0, 0, 0, 0},
8474 {0x93, 0, 0, 0, 0},
8475 {0x94, 0, 0, 0, 0},
8476 {0xFFFF, 0, 0, 0, 0}
8477};
8478
8479static struct radio_regs regs_SYN_2056_A1[] = {
8480 {0x02, 0, 0, 0, 0},
8481 {0x03, 0, 0, 0, 0},
8482 {0x04, 0, 0, 0, 0},
8483 {0x05, 0, 0, 0, 0},
8484 {0x06, 0, 0, 0, 0},
8485 {0x07, 0, 0, 0, 0},
8486 {0x08, 0, 0, 0, 0},
8487 {0x09, 0x1, 0x1, 0, 0},
8488 {0x0A, 0, 0, 0, 0},
8489 {0x0B, 0, 0, 0, 0},
8490 {0x0C, 0, 0, 0, 0},
8491 {0x0D, 0, 0, 0, 0},
8492 {0x0E, 0, 0, 0, 0},
8493 {0x0F, 0, 0, 0, 0},
8494 {0x10, 0, 0, 0, 0},
8495 {0x11, 0, 0, 0, 0},
8496 {0x12, 0, 0, 0, 0},
8497 {0x13, 0, 0, 0, 0},
8498 {0x14, 0, 0, 0, 0},
8499 {0x15, 0, 0, 0, 0},
8500 {0x16, 0, 0, 0, 0},
8501 {0x17, 0, 0, 0, 0},
8502 {0x18, 0, 0, 0, 0},
8503 {0x19, 0, 0, 0, 0},
8504 {0x1A, 0, 0, 0, 0},
8505 {0x1B, 0, 0, 0, 0},
8506 {0x1C, 0, 0, 0, 0},
8507 {0x1D, 0, 0, 0, 0},
8508 {0x1E, 0, 0, 0, 0},
8509 {0x1F, 0, 0, 0, 0},
8510 {0x20, 0, 0, 0, 0},
8511 {0x21, 0, 0, 0, 0},
8512 {0x22, 0x60, 0x60, 0, 0},
8513 {0x23, 0x6, 0x6, 0, 0},
8514 {0x24, 0xc, 0xc, 0, 0},
8515 {0x25, 0, 0, 0, 0},
8516 {0x26, 0, 0, 0, 0},
8517 {0x27, 0, 0, 0, 0},
8518 {0x28, 0x1, 0x1, 0, 0},
8519 {0x29, 0, 0, 0, 0},
8520 {0x2A, 0, 0, 0, 0},
8521 {0x2B, 0, 0, 0, 0},
8522 {0x2C, 0, 0, 0, 0},
8523 {0x2D, 0, 0, 0, 0},
8524 {0x2E, 0xd, 0xd, 0, 0},
8525 {0x2F, 0x1f, 0x1f, 0, 0},
8526 {0x30, 0x15, 0x15, 0, 0},
8527 {0x31, 0xf, 0xf, 0, 0},
8528 {0x32, 0, 0, 0, 0},
8529 {0x33, 0, 0, 0, 0},
8530 {0x34, 0, 0, 0, 0},
8531 {0x35, 0, 0, 0, 0},
8532 {0x36, 0, 0, 0, 0},
8533 {0x37, 0, 0, 0, 0},
8534 {0x38, 0, 0, 0, 0},
8535 {0x39, 0, 0, 0, 0},
8536 {0x3A, 0, 0, 0, 0},
8537 {0x3B, 0, 0, 0, 0},
8538 {0x3C, 0x13, 0x13, 0, 0},
8539 {0x3D, 0xf, 0xf, 0, 0},
8540 {0x3E, 0x18, 0x18, 0, 0},
8541 {0x3F, 0, 0, 0, 0},
8542 {0x40, 0, 0, 0, 0},
8543 {0x41, 0x20, 0x20, 0, 0},
8544 {0x42, 0x20, 0x20, 0, 0},
8545 {0x43, 0, 0, 0, 0},
8546 {0x44, 0x77, 0x77, 0, 0},
8547 {0x45, 0x7, 0x7, 0, 0},
8548 {0x46, 0x1, 0x1, 0, 0},
8549 {0x47, 0x4, 0x4, 0, 0},
8550 {0x48, 0xf, 0xf, 0, 0},
8551 {0x49, 0x30, 0x30, 0, 0},
8552 {0x4A, 0x32, 0x32, 0, 0},
8553 {0x4B, 0xd, 0xd, 0, 0},
8554 {0x4C, 0xd, 0xd, 0, 0},
8555 {0x4D, 0x4, 0x4, 0, 0},
8556 {0x4E, 0x6, 0x6, 0, 0},
8557 {0x4F, 0x1, 0x1, 0, 0},
8558 {0x50, 0x1c, 0x1c, 0, 0},
8559 {0x51, 0x2, 0x2, 0, 0},
8560 {0x52, 0x2, 0x2, 0, 0},
8561 {0x53, 0xf7, 0xf7, 1, 1},
8562 {0x54, 0xb4, 0xb4, 0, 0},
8563 {0x55, 0xd2, 0xd2, 0, 0},
8564 {0x56, 0, 0, 0, 0},
8565 {0x57, 0, 0, 0, 0},
8566 {0x58, 0x4, 0x4, 0, 0},
8567 {0x59, 0x96, 0x96, 0, 0},
8568 {0x5A, 0x3e, 0x3e, 0, 0},
8569 {0x5B, 0x3e, 0x3e, 0, 0},
8570 {0x5C, 0x13, 0x13, 0, 0},
8571 {0x5D, 0x2, 0x2, 0, 0},
8572 {0x5E, 0, 0, 0, 0},
8573 {0x5F, 0x7, 0x7, 0, 0},
8574 {0x60, 0x7, 0x7, 1, 1},
8575 {0x61, 0x8, 0x8, 0, 0},
8576 {0x62, 0x3, 0x3, 0, 0},
8577 {0x63, 0, 0, 0, 0},
8578 {0x64, 0, 0, 0, 0},
8579 {0x65, 0, 0, 0, 0},
8580 {0x66, 0, 0, 0, 0},
8581 {0x67, 0, 0, 0, 0},
8582 {0x68, 0x40, 0x40, 0, 0},
8583 {0x69, 0, 0, 0, 0},
8584 {0x6A, 0, 0, 0, 0},
8585 {0x6B, 0, 0, 0, 0},
8586 {0x6C, 0, 0, 0, 0},
8587 {0x6D, 0x1, 0x1, 0, 0},
8588 {0x6E, 0, 0, 0, 0},
8589 {0x6F, 0, 0, 0, 0},
8590 {0x70, 0x60, 0x60, 0, 0},
8591 {0x71, 0x66, 0x66, 0, 0},
8592 {0x72, 0xc, 0xc, 0, 0},
8593 {0x73, 0x66, 0x66, 0, 0},
8594 {0x74, 0x8f, 0x8f, 1, 1},
8595 {0x75, 0, 0, 0, 0},
8596 {0x76, 0xcc, 0xcc, 0, 0},
8597 {0x77, 0x1, 0x1, 0, 0},
8598 {0x78, 0x66, 0x66, 0, 0},
8599 {0x79, 0x66, 0x66, 0, 0},
8600 {0x7A, 0, 0, 0, 0},
8601 {0x7B, 0, 0, 0, 0},
8602 {0x7C, 0, 0, 0, 0},
8603 {0x7D, 0, 0, 0, 0},
8604 {0x7E, 0, 0, 0, 0},
8605 {0x7F, 0, 0, 0, 0},
8606 {0x80, 0, 0, 0, 0},
8607 {0x81, 0, 0, 0, 0},
8608 {0x82, 0, 0, 0, 0},
8609 {0x83, 0, 0, 0, 0},
8610 {0x84, 0, 0, 0, 0},
8611 {0x85, 0xff, 0xff, 0, 0},
8612 {0x86, 0, 0, 0, 0},
8613 {0x87, 0, 0, 0, 0},
8614 {0x88, 0, 0, 0, 0},
8615 {0x89, 0, 0, 0, 0},
8616 {0x8A, 0, 0, 0, 0},
8617 {0x8B, 0, 0, 0, 0},
8618 {0x8C, 0, 0, 0, 0},
8619 {0x8D, 0, 0, 0, 0},
8620 {0x8E, 0, 0, 0, 0},
8621 {0x8F, 0, 0, 0, 0},
8622 {0x90, 0, 0, 0, 0},
8623 {0x91, 0, 0, 0, 0},
8624 {0x92, 0, 0, 0, 0},
8625 {0x93, 0, 0, 0, 0},
8626 {0x94, 0, 0, 0, 0},
8627 {0x95, 0, 0, 0, 0},
8628 {0x96, 0, 0, 0, 0},
8629 {0x97, 0, 0, 0, 0},
8630 {0x98, 0, 0, 0, 0},
8631 {0x99, 0, 0, 0, 0},
8632 {0x9A, 0, 0, 0, 0},
8633 {0x9B, 0, 0, 0, 0},
8634 {0x9C, 0, 0, 0, 0},
8635 {0x9D, 0, 0, 0, 0},
8636 {0x9E, 0, 0, 0, 0},
8637 {0x9F, 0x6, 0x6, 0, 0},
8638 {0xA0, 0x66, 0x66, 0, 0},
8639 {0xA1, 0x66, 0x66, 0, 0},
8640 {0xA2, 0x66, 0x66, 0, 0},
8641 {0xA3, 0x66, 0x66, 0, 0},
8642 {0xA4, 0x66, 0x66, 0, 0},
8643 {0xA5, 0x66, 0x66, 0, 0},
8644 {0xA6, 0x66, 0x66, 0, 0},
8645 {0xA7, 0x66, 0x66, 0, 0},
8646 {0xA8, 0x66, 0x66, 0, 0},
8647 {0xA9, 0x66, 0x66, 0, 0},
8648 {0xAA, 0x66, 0x66, 0, 0},
8649 {0xAB, 0x66, 0x66, 0, 0},
8650 {0xAC, 0x66, 0x66, 0, 0},
8651 {0xAD, 0x66, 0x66, 0, 0},
8652 {0xAE, 0x66, 0x66, 0, 0},
8653 {0xAF, 0x66, 0x66, 0, 0},
8654 {0xB0, 0x66, 0x66, 0, 0},
8655 {0xB1, 0x66, 0x66, 0, 0},
8656 {0xB2, 0x66, 0x66, 0, 0},
8657 {0xB3, 0xa, 0xa, 0, 0},
8658 {0xB4, 0, 0, 0, 0},
8659 {0xB5, 0, 0, 0, 0},
8660 {0xB6, 0, 0, 0, 0},
8661 {0xFFFF, 0, 0, 0, 0}
8662};
8663
8664static struct radio_regs regs_TX_2056_A1[] = {
8665 {0x02, 0, 0, 0, 0},
8666 {0x03, 0, 0, 0, 0},
8667 {0x04, 0, 0, 0, 0},
8668 {0x05, 0, 0, 0, 0},
8669 {0x06, 0, 0, 0, 0},
8670 {0x07, 0, 0, 0, 0},
8671 {0x08, 0, 0, 0, 0},
8672 {0x09, 0, 0, 0, 0},
8673 {0x0A, 0, 0, 0, 0},
8674 {0x0B, 0, 0, 0, 0},
8675 {0x0C, 0, 0, 0, 0},
8676 {0x0D, 0, 0, 0, 0},
8677 {0x0E, 0, 0, 0, 0},
8678 {0x0F, 0, 0, 0, 0},
8679 {0x10, 0, 0, 0, 0},
8680 {0x11, 0, 0, 0, 0},
8681 {0x12, 0, 0, 0, 0},
8682 {0x13, 0, 0, 0, 0},
8683 {0x14, 0, 0, 0, 0},
8684 {0x15, 0, 0, 0, 0},
8685 {0x16, 0, 0, 0, 0},
8686 {0x17, 0, 0, 0, 0},
8687 {0x18, 0, 0, 0, 0},
8688 {0x19, 0, 0, 0, 0},
8689 {0x1A, 0, 0, 0, 0},
8690 {0x1B, 0, 0, 0, 0},
8691 {0x1C, 0, 0, 0, 0},
8692 {0x1D, 0, 0, 0, 0},
8693 {0x1E, 0, 0, 0, 0},
8694 {0x1F, 0, 0, 0, 0},
8695 {0x20, 0, 0, 0, 0},
8696 {0x21, 0x88, 0x88, 0, 0},
8697 {0x22, 0x88, 0x88, 0, 0},
8698 {0x23, 0x88, 0x88, 0, 0},
8699 {0x24, 0x88, 0x88, 0, 0},
8700 {0x25, 0xc, 0xc, 0, 0},
8701 {0x26, 0, 0, 0, 0},
8702 {0x27, 0x3, 0x3, 0, 0},
8703 {0x28, 0, 0, 0, 0},
8704 {0x29, 0x3, 0x3, 0, 0},
8705 {0x2A, 0x37, 0x37, 0, 0},
8706 {0x2B, 0x3, 0x3, 0, 0},
8707 {0x2C, 0, 0, 0, 0},
8708 {0x2D, 0, 0, 0, 0},
8709 {0x2E, 0x1, 0x1, 0, 0},
8710 {0x2F, 0x1, 0x1, 0, 0},
8711 {0x30, 0, 0, 0, 0},
8712 {0x31, 0, 0, 0, 0},
8713 {0x32, 0, 0, 0, 0},
8714 {0x33, 0x11, 0x11, 0, 0},
8715 {0x34, 0x11, 0x11, 0, 0},
8716 {0x35, 0, 0, 0, 0},
8717 {0x36, 0, 0, 0, 0},
8718 {0x37, 0x3, 0x3, 0, 0},
8719 {0x38, 0xf, 0xf, 0, 0},
8720 {0x39, 0, 0, 0, 0},
8721 {0x3A, 0x2d, 0x2d, 0, 0},
8722 {0x3B, 0, 0, 0, 0},
8723 {0x3C, 0x6e, 0x6e, 0, 0},
8724 {0x3D, 0xf0, 0xf0, 1, 1},
8725 {0x3E, 0, 0, 0, 0},
8726 {0x3F, 0, 0, 0, 0},
8727 {0x40, 0, 0, 0, 0},
8728 {0x41, 0x3, 0x3, 0, 0},
8729 {0x42, 0x3, 0x3, 0, 0},
8730 {0x43, 0, 0, 0, 0},
8731 {0x44, 0x1e, 0x1e, 0, 0},
8732 {0x45, 0, 0, 0, 0},
8733 {0x46, 0x6e, 0x6e, 0, 0},
8734 {0x47, 0xf0, 0xf0, 1, 1},
8735 {0x48, 0, 0, 0, 0},
8736 {0x49, 0x2, 0x2, 0, 0},
8737 {0x4A, 0xff, 0xff, 1, 1},
8738 {0x4B, 0xc, 0xc, 0, 0},
8739 {0x4C, 0, 0, 0, 0},
8740 {0x4D, 0x38, 0x38, 0, 0},
8741 {0x4E, 0x70, 0x70, 1, 1},
8742 {0x4F, 0x2, 0x2, 0, 0},
8743 {0x50, 0x88, 0x88, 0, 0},
8744 {0x51, 0xc, 0xc, 0, 0},
8745 {0x52, 0, 0, 0, 0},
8746 {0x53, 0x8, 0x8, 0, 0},
8747 {0x54, 0x70, 0x70, 1, 1},
8748 {0x55, 0x2, 0x2, 0, 0},
8749 {0x56, 0xff, 0xff, 1, 1},
8750 {0x57, 0, 0, 0, 0},
8751 {0x58, 0x83, 0x83, 0, 0},
8752 {0x59, 0x77, 0x77, 1, 1},
8753 {0x5A, 0, 0, 0, 0},
8754 {0x5B, 0x2, 0x2, 0, 0},
8755 {0x5C, 0x88, 0x88, 0, 0},
8756 {0x5D, 0, 0, 0, 0},
8757 {0x5E, 0x8, 0x8, 0, 0},
8758 {0x5F, 0x77, 0x77, 1, 1},
8759 {0x60, 0x1, 0x1, 0, 0},
8760 {0x61, 0, 0, 0, 0},
8761 {0x62, 0x7, 0x7, 0, 0},
8762 {0x63, 0, 0, 0, 0},
8763 {0x64, 0x7, 0x7, 0, 0},
8764 {0x65, 0, 0, 0, 0},
8765 {0x66, 0, 0, 0, 0},
8766 {0x67, 0x72, 0x72, 1, 1},
8767 {0x68, 0, 0, 0, 0},
8768 {0x69, 0xa, 0xa, 0, 0},
8769 {0x6A, 0, 0, 0, 0},
8770 {0x6B, 0, 0, 0, 0},
8771 {0x6C, 0, 0, 0, 0},
8772 {0x6D, 0, 0, 0, 0},
8773 {0x6E, 0, 0, 0, 0},
8774 {0x6F, 0, 0, 0, 0},
8775 {0x70, 0, 0, 0, 0},
8776 {0x71, 0x2, 0x2, 0, 0},
8777 {0x72, 0, 0, 0, 0},
8778 {0x73, 0, 0, 0, 0},
8779 {0x74, 0xe, 0xe, 0, 0},
8780 {0x75, 0xe, 0xe, 0, 0},
8781 {0x76, 0xe, 0xe, 0, 0},
8782 {0x77, 0x13, 0x13, 0, 0},
8783 {0x78, 0x13, 0x13, 0, 0},
8784 {0x79, 0x1b, 0x1b, 0, 0},
8785 {0x7A, 0x1b, 0x1b, 0, 0},
8786 {0x7B, 0x55, 0x55, 0, 0},
8787 {0x7C, 0x5b, 0x5b, 0, 0},
8788 {0x7D, 0, 0, 0, 0},
8789 {0x7E, 0, 0, 0, 0},
8790 {0x7F, 0, 0, 0, 0},
8791 {0x80, 0, 0, 0, 0},
8792 {0x81, 0, 0, 0, 0},
8793 {0x82, 0, 0, 0, 0},
8794 {0x83, 0, 0, 0, 0},
8795 {0x84, 0, 0, 0, 0},
8796 {0x85, 0, 0, 0, 0},
8797 {0x86, 0, 0, 0, 0},
8798 {0x87, 0, 0, 0, 0},
8799 {0x88, 0, 0, 0, 0},
8800 {0x89, 0, 0, 0, 0},
8801 {0x8A, 0, 0, 0, 0},
8802 {0x8B, 0, 0, 0, 0},
8803 {0x8C, 0, 0, 0, 0},
8804 {0x8D, 0, 0, 0, 0},
8805 {0x8E, 0, 0, 0, 0},
8806 {0x8F, 0, 0, 0, 0},
8807 {0x90, 0, 0, 0, 0},
8808 {0x91, 0, 0, 0, 0},
8809 {0x92, 0, 0, 0, 0},
8810 {0xFFFF, 0, 0, 0, 0}
8811};
8812
8813static struct radio_regs regs_RX_2056_A1[] = {
8814 {0x02, 0, 0, 0, 0},
8815 {0x03, 0, 0, 0, 0},
8816 {0x04, 0, 0, 0, 0},
8817 {0x05, 0, 0, 0, 0},
8818 {0x06, 0, 0, 0, 0},
8819 {0x07, 0, 0, 0, 0},
8820 {0x08, 0, 0, 0, 0},
8821 {0x09, 0, 0, 0, 0},
8822 {0x0A, 0, 0, 0, 0},
8823 {0x0B, 0, 0, 0, 0},
8824 {0x0C, 0, 0, 0, 0},
8825 {0x0D, 0, 0, 0, 0},
8826 {0x0E, 0, 0, 0, 0},
8827 {0x0F, 0, 0, 0, 0},
8828 {0x10, 0, 0, 0, 0},
8829 {0x11, 0, 0, 0, 0},
8830 {0x12, 0, 0, 0, 0},
8831 {0x13, 0, 0, 0, 0},
8832 {0x14, 0, 0, 0, 0},
8833 {0x15, 0, 0, 0, 0},
8834 {0x16, 0, 0, 0, 0},
8835 {0x17, 0, 0, 0, 0},
8836 {0x18, 0, 0, 0, 0},
8837 {0x19, 0, 0, 0, 0},
8838 {0x1A, 0, 0, 0, 0},
8839 {0x1B, 0, 0, 0, 0},
8840 {0x1C, 0, 0, 0, 0},
8841 {0x1D, 0, 0, 0, 0},
8842 {0x1E, 0, 0, 0, 0},
8843 {0x1F, 0, 0, 0, 0},
8844 {0x20, 0x3, 0x3, 0, 0},
8845 {0x21, 0, 0, 0, 0},
8846 {0x22, 0, 0, 0, 0},
8847 {0x23, 0x90, 0x90, 0, 0},
8848 {0x24, 0x55, 0x55, 0, 0},
8849 {0x25, 0x15, 0x15, 0, 0},
8850 {0x26, 0x5, 0x5, 0, 0},
8851 {0x27, 0x15, 0x15, 0, 0},
8852 {0x28, 0x5, 0x5, 0, 0},
8853 {0x29, 0x20, 0x20, 0, 0},
8854 {0x2A, 0x11, 0x11, 0, 0},
8855 {0x2B, 0x90, 0x90, 0, 0},
8856 {0x2C, 0, 0, 0, 0},
8857 {0x2D, 0x88, 0x88, 0, 0},
8858 {0x2E, 0x32, 0x32, 0, 0},
8859 {0x2F, 0x77, 0x77, 0, 0},
8860 {0x30, 0x17, 0x17, 1, 1},
8861 {0x31, 0xff, 0xff, 1, 1},
8862 {0x32, 0x20, 0x20, 0, 0},
8863 {0x33, 0, 0, 0, 0},
8864 {0x34, 0x88, 0x88, 0, 0},
8865 {0x35, 0x32, 0x32, 0, 0},
8866 {0x36, 0x77, 0x77, 0, 0},
8867 {0x37, 0x17, 0x17, 1, 1},
8868 {0x38, 0xf0, 0xf0, 1, 1},
8869 {0x39, 0x20, 0x20, 0, 0},
8870 {0x3A, 0x8, 0x8, 0, 0},
8871 {0x3B, 0x55, 0x55, 1, 1},
8872 {0x3C, 0, 0, 0, 0},
8873 {0x3D, 0x44, 0x44, 1, 1},
8874 {0x3E, 0, 0, 0, 0},
8875 {0x3F, 0x44, 0x44, 0, 0},
8876 {0x40, 0xf, 0xf, 1, 1},
8877 {0x41, 0x6, 0x6, 0, 0},
8878 {0x42, 0x4, 0x4, 0, 0},
8879 {0x43, 0x50, 0x50, 1, 1},
8880 {0x44, 0x8, 0x8, 0, 0},
8881 {0x45, 0x55, 0x55, 1, 1},
8882 {0x46, 0, 0, 0, 0},
8883 {0x47, 0x11, 0x11, 0, 0},
8884 {0x48, 0, 0, 0, 0},
8885 {0x49, 0x44, 0x44, 0, 0},
8886 {0x4A, 0x7, 0x7, 0, 0},
8887 {0x4B, 0x6, 0x6, 0, 0},
8888 {0x4C, 0x4, 0x4, 0, 0},
8889 {0x4D, 0, 0, 0, 0},
8890 {0x4E, 0, 0, 0, 0},
8891 {0x4F, 0x26, 0x26, 1, 1},
8892 {0x50, 0x26, 0x26, 1, 1},
8893 {0x51, 0xf, 0xf, 1, 1},
8894 {0x52, 0xf, 0xf, 1, 1},
8895 {0x53, 0x44, 0x44, 0, 0},
8896 {0x54, 0, 0, 0, 0},
8897 {0x55, 0, 0, 0, 0},
8898 {0x56, 0x8, 0x8, 0, 0},
8899 {0x57, 0x8, 0x8, 0, 0},
8900 {0x58, 0x7, 0x7, 0, 0},
8901 {0x59, 0x22, 0x22, 0, 0},
8902 {0x5A, 0x22, 0x22, 0, 0},
8903 {0x5B, 0x2, 0x2, 0, 0},
8904 {0x5C, 0x2f, 0x2f, 1, 1},
8905 {0x5D, 0x7, 0x7, 0, 0},
8906 {0x5E, 0x55, 0x55, 0, 0},
8907 {0x5F, 0x23, 0x23, 0, 0},
8908 {0x60, 0x41, 0x41, 0, 0},
8909 {0x61, 0x1, 0x1, 0, 0},
8910 {0x62, 0xa, 0xa, 0, 0},
8911 {0x63, 0, 0, 0, 0},
8912 {0x64, 0, 0, 0, 0},
8913 {0x65, 0, 0, 0, 0},
8914 {0x66, 0, 0, 0, 0},
8915 {0x67, 0, 0, 0, 0},
8916 {0x68, 0, 0, 0, 0},
8917 {0x69, 0, 0, 0, 0},
8918 {0x6A, 0, 0, 0, 0},
8919 {0x6B, 0xc, 0xc, 0, 0},
8920 {0x6C, 0, 0, 0, 0},
8921 {0x6D, 0, 0, 0, 0},
8922 {0x6E, 0, 0, 0, 0},
8923 {0x6F, 0, 0, 0, 0},
8924 {0x70, 0, 0, 0, 0},
8925 {0x71, 0, 0, 0, 0},
8926 {0x72, 0x22, 0x22, 0, 0},
8927 {0x73, 0x22, 0x22, 0, 0},
8928 {0x74, 0, 0, 1, 1},
8929 {0x75, 0xa, 0xa, 0, 0},
8930 {0x76, 0x1, 0x1, 0, 0},
8931 {0x77, 0x22, 0x22, 0, 0},
8932 {0x78, 0x30, 0x30, 0, 0},
8933 {0x79, 0, 0, 0, 0},
8934 {0x7A, 0, 0, 0, 0},
8935 {0x7B, 0, 0, 0, 0},
8936 {0x7C, 0, 0, 0, 0},
8937 {0x7D, 0, 0, 0, 0},
8938 {0x7E, 0, 0, 0, 0},
8939 {0x7F, 0, 0, 0, 0},
8940 {0x80, 0, 0, 0, 0},
8941 {0x81, 0, 0, 0, 0},
8942 {0x82, 0, 0, 0, 0},
8943 {0x83, 0, 0, 0, 0},
8944 {0x84, 0, 0, 0, 0},
8945 {0x85, 0, 0, 0, 0},
8946 {0x86, 0, 0, 0, 0},
8947 {0x87, 0, 0, 0, 0},
8948 {0x88, 0, 0, 0, 0},
8949 {0x89, 0, 0, 0, 0},
8950 {0x8A, 0, 0, 0, 0},
8951 {0x8B, 0, 0, 0, 0},
8952 {0x8C, 0, 0, 0, 0},
8953 {0x8D, 0, 0, 0, 0},
8954 {0x8E, 0, 0, 0, 0},
8955 {0x8F, 0, 0, 0, 0},
8956 {0x90, 0, 0, 0, 0},
8957 {0x91, 0, 0, 0, 0},
8958 {0x92, 0, 0, 0, 0},
8959 {0x93, 0, 0, 0, 0},
8960 {0x94, 0, 0, 0, 0},
8961 {0xFFFF, 0, 0, 0, 0}
8962};
8963
8964static struct radio_regs regs_SYN_2056_rev5[] = {
8965 {0x02, 0, 0, 0, 0},
8966 {0x03, 0, 0, 0, 0},
8967 {0x04, 0, 0, 0, 0},
8968 {0x05, 0, 0, 0, 0},
8969 {0x06, 0, 0, 0, 0},
8970 {0x07, 0, 0, 0, 0},
8971 {0x08, 0, 0, 0, 0},
8972 {0x09, 0x1, 0x1, 0, 0},
8973 {0x0A, 0, 0, 0, 0},
8974 {0x0B, 0, 0, 0, 0},
8975 {0x0C, 0, 0, 0, 0},
8976 {0x0D, 0, 0, 0, 0},
8977 {0x0E, 0, 0, 0, 0},
8978 {0x0F, 0, 0, 0, 0},
8979 {0x10, 0, 0, 0, 0},
8980 {0x11, 0, 0, 0, 0},
8981 {0x12, 0, 0, 0, 0},
8982 {0x13, 0, 0, 0, 0},
8983 {0x14, 0, 0, 0, 0},
8984 {0x15, 0, 0, 0, 0},
8985 {0x16, 0, 0, 0, 0},
8986 {0x17, 0, 0, 0, 0},
8987 {0x18, 0, 0, 0, 0},
8988 {0x19, 0, 0, 0, 0},
8989 {0x1A, 0, 0, 0, 0},
8990 {0x1B, 0, 0, 0, 0},
8991 {0x1C, 0, 0, 0, 0},
8992 {0x1D, 0, 0, 0, 0},
8993 {0x1E, 0, 0, 0, 0},
8994 {0x1F, 0, 0, 0, 0},
8995 {0x20, 0, 0, 0, 0},
8996 {0x21, 0, 0, 0, 0},
8997 {0x22, 0x60, 0x60, 0, 0},
8998 {0x23, 0x6, 0x6, 0, 0},
8999 {0x24, 0xc, 0xc, 0, 0},
9000 {0x25, 0, 0, 0, 0},
9001 {0x26, 0, 0, 0, 0},
9002 {0x27, 0, 0, 0, 0},
9003 {0x28, 0x1, 0x1, 0, 0},
9004 {0x29, 0, 0, 0, 0},
9005 {0x2A, 0, 0, 0, 0},
9006 {0x2B, 0, 0, 0, 0},
9007 {0x2C, 0, 0, 0, 0},
9008 {0x2D, 0, 0, 0, 0},
9009 {0x2E, 0, 0, 0, 0},
9010 {0x2F, 0x1f, 0x1f, 0, 0},
9011 {0x30, 0x15, 0x15, 0, 0},
9012 {0x31, 0xf, 0xf, 0, 0},
9013 {0x32, 0, 0, 0, 0},
9014 {0x33, 0, 0, 0, 0},
9015 {0x34, 0, 0, 0, 0},
9016 {0x35, 0, 0, 0, 0},
9017 {0x36, 0, 0, 0, 0},
9018 {0x37, 0, 0, 0, 0},
9019 {0x38, 0, 0, 0, 0},
9020 {0x39, 0, 0, 0, 0},
9021 {0x3A, 0, 0, 0, 0},
9022 {0x3B, 0, 0, 0, 0},
9023 {0x3C, 0x13, 0x13, 0, 0},
9024 {0x3D, 0xf, 0xf, 0, 0},
9025 {0x3E, 0x18, 0x18, 0, 0},
9026 {0x3F, 0, 0, 0, 0},
9027 {0x40, 0, 0, 0, 0},
9028 {0x41, 0x20, 0x20, 0, 0},
9029 {0x42, 0x20, 0x20, 0, 0},
9030 {0x43, 0, 0, 0, 0},
9031 {0x44, 0x77, 0x77, 0, 0},
9032 {0x45, 0x7, 0x7, 0, 0},
9033 {0x46, 0x1, 0x1, 0, 0},
9034 {0x47, 0x4, 0x4, 0, 0},
9035 {0x48, 0xf, 0xf, 0, 0},
9036 {0x49, 0x30, 0x30, 0, 0},
9037 {0x4A, 0x32, 0x32, 0, 0},
9038 {0x4B, 0xd, 0xd, 0, 0},
9039 {0x4C, 0xd, 0xd, 0, 0},
9040 {0x4D, 0x4, 0x4, 0, 0},
9041 {0x4E, 0x6, 0x6, 0, 0},
9042 {0x4F, 0x1, 0x1, 0, 0},
9043 {0x50, 0x1c, 0x1c, 0, 0},
9044 {0x51, 0x2, 0x2, 0, 0},
9045 {0x52, 0x2, 0x2, 0, 0},
9046 {0x53, 0xf7, 0xf7, 1, 1},
9047 {0x54, 0xb4, 0xb4, 0, 0},
9048 {0x55, 0xd2, 0xd2, 0, 0},
9049 {0x56, 0, 0, 0, 0},
9050 {0x57, 0, 0, 0, 0},
9051 {0x58, 0x4, 0x4, 0, 0},
9052 {0x59, 0x96, 0x96, 0, 0},
9053 {0x5A, 0x3e, 0x3e, 0, 0},
9054 {0x5B, 0x3e, 0x3e, 0, 0},
9055 {0x5C, 0x13, 0x13, 0, 0},
9056 {0x5D, 0x2, 0x2, 0, 0},
9057 {0x5E, 0, 0, 0, 0},
9058 {0x5F, 0x7, 0x7, 0, 0},
9059 {0x60, 0x7, 0x7, 1, 1},
9060 {0x61, 0x8, 0x8, 0, 0},
9061 {0x62, 0x3, 0x3, 0, 0},
9062 {0x63, 0, 0, 0, 0},
9063 {0x64, 0, 0, 0, 0},
9064 {0x65, 0, 0, 0, 0},
9065 {0x66, 0, 0, 0, 0},
9066 {0x67, 0, 0, 0, 0},
9067 {0x68, 0x40, 0x40, 0, 0},
9068 {0x69, 0, 0, 0, 0},
9069 {0x6A, 0, 0, 0, 0},
9070 {0x6B, 0, 0, 0, 0},
9071 {0x6C, 0, 0, 0, 0},
9072 {0x6D, 0x1, 0x1, 0, 0},
9073 {0x6E, 0, 0, 0, 0},
9074 {0x6F, 0, 0, 0, 0},
9075 {0x70, 0x60, 0x60, 0, 0},
9076 {0x71, 0x66, 0x66, 0, 0},
9077 {0x72, 0xc, 0xc, 0, 0},
9078 {0x73, 0x66, 0x66, 0, 0},
9079 {0x74, 0x8f, 0x8f, 1, 1},
9080 {0x75, 0, 0, 0, 0},
9081 {0x76, 0xcc, 0xcc, 0, 0},
9082 {0x77, 0x1, 0x1, 0, 0},
9083 {0x78, 0x66, 0x66, 0, 0},
9084 {0x79, 0x66, 0x66, 0, 0},
9085 {0x7A, 0, 0, 0, 0},
9086 {0x7B, 0, 0, 0, 0},
9087 {0x7C, 0, 0, 0, 0},
9088 {0x7D, 0, 0, 0, 0},
9089 {0x7E, 0, 0, 0, 0},
9090 {0x7F, 0, 0, 0, 0},
9091 {0x80, 0, 0, 0, 0},
9092 {0x81, 0, 0, 0, 0},
9093 {0x82, 0, 0, 0, 0},
9094 {0x83, 0, 0, 0, 0},
9095 {0x84, 0, 0, 0, 0},
9096 {0x85, 0xff, 0xff, 0, 0},
9097 {0x86, 0, 0, 0, 0},
9098 {0x87, 0, 0, 0, 0},
9099 {0x88, 0, 0, 0, 0},
9100 {0x89, 0, 0, 0, 0},
9101 {0x8A, 0, 0, 0, 0},
9102 {0x8B, 0, 0, 0, 0},
9103 {0x8C, 0, 0, 0, 0},
9104 {0x8D, 0, 0, 0, 0},
9105 {0x8E, 0, 0, 0, 0},
9106 {0x8F, 0, 0, 0, 0},
9107 {0x90, 0, 0, 0, 0},
9108 {0x91, 0, 0, 0, 0},
9109 {0x92, 0, 0, 0, 0},
9110 {0x93, 0, 0, 0, 0},
9111 {0x94, 0, 0, 0, 0},
9112 {0x95, 0, 0, 0, 0},
9113 {0x96, 0, 0, 0, 0},
9114 {0x97, 0, 0, 0, 0},
9115 {0x98, 0, 0, 0, 0},
9116 {0x99, 0, 0, 0, 0},
9117 {0x9A, 0, 0, 0, 0},
9118 {0x9B, 0, 0, 0, 0},
9119 {0x9C, 0, 0, 0, 0},
9120 {0x9D, 0, 0, 0, 0},
9121 {0x9E, 0, 0, 0, 0},
9122 {0x9F, 0x6, 0x6, 0, 0},
9123 {0xA0, 0x66, 0x66, 0, 0},
9124 {0xA1, 0x66, 0x66, 0, 0},
9125 {0xA2, 0x66, 0x66, 0, 0},
9126 {0xA3, 0x66, 0x66, 0, 0},
9127 {0xA4, 0x66, 0x66, 0, 0},
9128 {0xA5, 0x66, 0x66, 0, 0},
9129 {0xA6, 0x66, 0x66, 0, 0},
9130 {0xA7, 0x66, 0x66, 0, 0},
9131 {0xA8, 0x66, 0x66, 0, 0},
9132 {0xA9, 0x66, 0x66, 0, 0},
9133 {0xAA, 0x66, 0x66, 0, 0},
9134 {0xAB, 0x66, 0x66, 0, 0},
9135 {0xAC, 0x66, 0x66, 0, 0},
9136 {0xAD, 0x66, 0x66, 0, 0},
9137 {0xAE, 0x66, 0x66, 0, 0},
9138 {0xAF, 0x66, 0x66, 0, 0},
9139 {0xB0, 0x66, 0x66, 0, 0},
9140 {0xB1, 0x66, 0x66, 0, 0},
9141 {0xB2, 0x66, 0x66, 0, 0},
9142 {0xB3, 0xa, 0xa, 0, 0},
9143 {0xB4, 0, 0, 0, 0},
9144 {0xB5, 0, 0, 0, 0},
9145 {0xB6, 0, 0, 0, 0},
9146 {0xFFFF, 0, 0, 0, 0}
9147};
9148
9149static struct radio_regs regs_TX_2056_rev5[] = {
9150 {0x02, 0, 0, 0, 0},
9151 {0x03, 0, 0, 0, 0},
9152 {0x04, 0, 0, 0, 0},
9153 {0x05, 0, 0, 0, 0},
9154 {0x06, 0, 0, 0, 0},
9155 {0x07, 0, 0, 0, 0},
9156 {0x08, 0, 0, 0, 0},
9157 {0x09, 0, 0, 0, 0},
9158 {0x0A, 0, 0, 0, 0},
9159 {0x0B, 0, 0, 0, 0},
9160 {0x0C, 0, 0, 0, 0},
9161 {0x0D, 0, 0, 0, 0},
9162 {0x0E, 0, 0, 0, 0},
9163 {0x0F, 0, 0, 0, 0},
9164 {0x10, 0, 0, 0, 0},
9165 {0x11, 0, 0, 0, 0},
9166 {0x12, 0, 0, 0, 0},
9167 {0x13, 0, 0, 0, 0},
9168 {0x14, 0, 0, 0, 0},
9169 {0x15, 0, 0, 0, 0},
9170 {0x16, 0, 0, 0, 0},
9171 {0x17, 0, 0, 0, 0},
9172 {0x18, 0, 0, 0, 0},
9173 {0x19, 0, 0, 0, 0},
9174 {0x1A, 0, 0, 0, 0},
9175 {0x1B, 0, 0, 0, 0},
9176 {0x1C, 0, 0, 0, 0},
9177 {0x1D, 0, 0, 0, 0},
9178 {0x1E, 0, 0, 0, 0},
9179 {0x1F, 0, 0, 0, 0},
9180 {0x20, 0, 0, 0, 0},
9181 {0x21, 0x88, 0x88, 0, 0},
9182 {0x22, 0x88, 0x88, 0, 0},
9183 {0x23, 0x88, 0x88, 0, 0},
9184 {0x24, 0x88, 0x88, 0, 0},
9185 {0x25, 0xc, 0xc, 0, 0},
9186 {0x26, 0, 0, 0, 0},
9187 {0x27, 0x3, 0x3, 0, 0},
9188 {0x28, 0, 0, 0, 0},
9189 {0x29, 0x3, 0x3, 0, 0},
9190 {0x2A, 0x37, 0x37, 0, 0},
9191 {0x2B, 0x3, 0x3, 0, 0},
9192 {0x2C, 0, 0, 0, 0},
9193 {0x2D, 0, 0, 0, 0},
9194 {0x2E, 0x1, 0x1, 0, 0},
9195 {0x2F, 0x1, 0x1, 0, 0},
9196 {0x30, 0, 0, 0, 0},
9197 {0x31, 0, 0, 0, 0},
9198 {0x32, 0, 0, 0, 0},
9199 {0x33, 0x11, 0x11, 0, 0},
9200 {0x34, 0x11, 0x11, 0, 0},
9201 {0x35, 0, 0, 0, 0},
9202 {0x36, 0, 0, 0, 0},
9203 {0x37, 0x3, 0x3, 0, 0},
9204 {0x38, 0xf, 0xf, 0, 0},
9205 {0x39, 0, 0, 0, 0},
9206 {0x3A, 0x2d, 0x2d, 0, 0},
9207 {0x3B, 0, 0, 0, 0},
9208 {0x3C, 0x6e, 0x6e, 0, 0},
9209 {0x3D, 0xf0, 0xf0, 1, 1},
9210 {0x3E, 0, 0, 0, 0},
9211 {0x3F, 0, 0, 0, 0},
9212 {0x40, 0, 0, 0, 0},
9213 {0x41, 0x3, 0x3, 0, 0},
9214 {0x42, 0x3, 0x3, 0, 0},
9215 {0x43, 0, 0, 0, 0},
9216 {0x44, 0x1e, 0x1e, 0, 0},
9217 {0x45, 0, 0, 0, 0},
9218 {0x46, 0x6e, 0x6e, 0, 0},
9219 {0x47, 0xf0, 0xf0, 1, 1},
9220 {0x48, 0, 0, 0, 0},
9221 {0x49, 0x2, 0x2, 0, 0},
9222 {0x4A, 0xff, 0xff, 1, 1},
9223 {0x4B, 0xc, 0xc, 0, 0},
9224 {0x4C, 0, 0, 0, 0},
9225 {0x4D, 0x38, 0x38, 0, 0},
9226 {0x4E, 0x70, 0x70, 1, 1},
9227 {0x4F, 0x2, 0x2, 0, 0},
9228 {0x50, 0x88, 0x88, 0, 0},
9229 {0x51, 0xc, 0xc, 0, 0},
9230 {0x52, 0, 0, 0, 0},
9231 {0x53, 0x8, 0x8, 0, 0},
9232 {0x54, 0x70, 0x70, 1, 1},
9233 {0x55, 0x2, 0x2, 0, 0},
9234 {0x56, 0xff, 0xff, 1, 1},
9235 {0x57, 0, 0, 0, 0},
9236 {0x58, 0x83, 0x83, 0, 0},
9237 {0x59, 0x77, 0x77, 1, 1},
9238 {0x5A, 0, 0, 0, 0},
9239 {0x5B, 0x2, 0x2, 0, 0},
9240 {0x5C, 0x88, 0x88, 0, 0},
9241 {0x5D, 0, 0, 0, 0},
9242 {0x5E, 0x8, 0x8, 0, 0},
9243 {0x5F, 0x77, 0x77, 1, 1},
9244 {0x60, 0x1, 0x1, 0, 0},
9245 {0x61, 0, 0, 0, 0},
9246 {0x62, 0x7, 0x7, 0, 0},
9247 {0x63, 0, 0, 0, 0},
9248 {0x64, 0x7, 0x7, 0, 0},
9249 {0x65, 0, 0, 0, 0},
9250 {0x66, 0, 0, 0, 0},
9251 {0x67, 0, 0, 1, 1},
9252 {0x68, 0, 0, 0, 0},
9253 {0x69, 0xa, 0xa, 0, 0},
9254 {0x6A, 0, 0, 0, 0},
9255 {0x6B, 0, 0, 0, 0},
9256 {0x6C, 0, 0, 0, 0},
9257 {0x6D, 0, 0, 0, 0},
9258 {0x6E, 0, 0, 0, 0},
9259 {0x6F, 0, 0, 0, 0},
9260 {0x70, 0, 0, 0, 0},
9261 {0x71, 0x2, 0x2, 0, 0},
9262 {0x72, 0, 0, 0, 0},
9263 {0x73, 0, 0, 0, 0},
9264 {0x74, 0xe, 0xe, 0, 0},
9265 {0x75, 0xe, 0xe, 0, 0},
9266 {0x76, 0xe, 0xe, 0, 0},
9267 {0x77, 0x13, 0x13, 0, 0},
9268 {0x78, 0x13, 0x13, 0, 0},
9269 {0x79, 0x1b, 0x1b, 0, 0},
9270 {0x7A, 0x1b, 0x1b, 0, 0},
9271 {0x7B, 0x55, 0x55, 0, 0},
9272 {0x7C, 0x5b, 0x5b, 0, 0},
9273 {0x7D, 0, 0, 0, 0},
9274 {0x7E, 0, 0, 0, 0},
9275 {0x7F, 0, 0, 0, 0},
9276 {0x80, 0, 0, 0, 0},
9277 {0x81, 0, 0, 0, 0},
9278 {0x82, 0, 0, 0, 0},
9279 {0x83, 0, 0, 0, 0},
9280 {0x84, 0, 0, 0, 0},
9281 {0x85, 0, 0, 0, 0},
9282 {0x86, 0, 0, 0, 0},
9283 {0x87, 0, 0, 0, 0},
9284 {0x88, 0, 0, 0, 0},
9285 {0x89, 0, 0, 0, 0},
9286 {0x8A, 0, 0, 0, 0},
9287 {0x8B, 0, 0, 0, 0},
9288 {0x8C, 0, 0, 0, 0},
9289 {0x8D, 0, 0, 0, 0},
9290 {0x8E, 0, 0, 0, 0},
9291 {0x8F, 0, 0, 0, 0},
9292 {0x90, 0, 0, 0, 0},
9293 {0x91, 0, 0, 0, 0},
9294 {0x92, 0, 0, 0, 0},
9295 {0x93, 0x70, 0x70, 0, 0},
9296 {0x94, 0x70, 0x70, 0, 0},
9297 {0x95, 0x71, 0x71, 1, 1},
9298 {0x96, 0x71, 0x71, 1, 1},
9299 {0x97, 0x72, 0x72, 1, 1},
9300 {0x98, 0x73, 0x73, 1, 1},
9301 {0x99, 0x74, 0x74, 1, 1},
9302 {0x9A, 0x75, 0x75, 1, 1},
9303 {0xFFFF, 0, 0, 0, 0}
9304};
9305
9306static struct radio_regs regs_RX_2056_rev5[] = {
9307 {0x02, 0, 0, 0, 0},
9308 {0x03, 0, 0, 0, 0},
9309 {0x04, 0, 0, 0, 0},
9310 {0x05, 0, 0, 0, 0},
9311 {0x06, 0, 0, 0, 0},
9312 {0x07, 0, 0, 0, 0},
9313 {0x08, 0, 0, 0, 0},
9314 {0x09, 0, 0, 0, 0},
9315 {0x0A, 0, 0, 0, 0},
9316 {0x0B, 0, 0, 0, 0},
9317 {0x0C, 0, 0, 0, 0},
9318 {0x0D, 0, 0, 0, 0},
9319 {0x0E, 0, 0, 0, 0},
9320 {0x0F, 0, 0, 0, 0},
9321 {0x10, 0, 0, 0, 0},
9322 {0x11, 0, 0, 0, 0},
9323 {0x12, 0, 0, 0, 0},
9324 {0x13, 0, 0, 0, 0},
9325 {0x14, 0, 0, 0, 0},
9326 {0x15, 0, 0, 0, 0},
9327 {0x16, 0, 0, 0, 0},
9328 {0x17, 0, 0, 0, 0},
9329 {0x18, 0, 0, 0, 0},
9330 {0x19, 0, 0, 0, 0},
9331 {0x1A, 0, 0, 0, 0},
9332 {0x1B, 0, 0, 0, 0},
9333 {0x1C, 0, 0, 0, 0},
9334 {0x1D, 0, 0, 0, 0},
9335 {0x1E, 0, 0, 0, 0},
9336 {0x1F, 0, 0, 0, 0},
9337 {0x20, 0x3, 0x3, 0, 0},
9338 {0x21, 0, 0, 0, 0},
9339 {0x22, 0, 0, 0, 0},
9340 {0x23, 0x90, 0x90, 0, 0},
9341 {0x24, 0x55, 0x55, 0, 0},
9342 {0x25, 0x15, 0x15, 0, 0},
9343 {0x26, 0x5, 0x5, 0, 0},
9344 {0x27, 0x15, 0x15, 0, 0},
9345 {0x28, 0x5, 0x5, 0, 0},
9346 {0x29, 0x20, 0x20, 0, 0},
9347 {0x2A, 0x11, 0x11, 0, 0},
9348 {0x2B, 0x90, 0x90, 0, 0},
9349 {0x2C, 0, 0, 0, 0},
9350 {0x2D, 0x88, 0x88, 0, 0},
9351 {0x2E, 0x32, 0x32, 0, 0},
9352 {0x2F, 0x77, 0x77, 0, 0},
9353 {0x30, 0x17, 0x17, 1, 1},
9354 {0x31, 0xff, 0xff, 1, 1},
9355 {0x32, 0x20, 0x20, 0, 0},
9356 {0x33, 0, 0, 0, 0},
9357 {0x34, 0x88, 0x88, 0, 0},
9358 {0x35, 0x32, 0x32, 0, 0},
9359 {0x36, 0x77, 0x77, 0, 0},
9360 {0x37, 0x17, 0x17, 1, 1},
9361 {0x38, 0xf0, 0xf0, 1, 1},
9362 {0x39, 0x20, 0x20, 0, 0},
9363 {0x3A, 0x8, 0x8, 0, 0},
9364 {0x3B, 0x55, 0x55, 1, 1},
9365 {0x3C, 0, 0, 0, 0},
9366 {0x3D, 0x88, 0x88, 1, 1},
9367 {0x3E, 0, 0, 0, 0},
9368 {0x3F, 0, 0, 1, 1},
9369 {0x40, 0x7, 0x7, 1, 1},
9370 {0x41, 0x6, 0x6, 0, 0},
9371 {0x42, 0x4, 0x4, 0, 0},
9372 {0x43, 0, 0, 0, 0},
9373 {0x44, 0x8, 0x8, 0, 0},
9374 {0x45, 0x55, 0x55, 1, 1},
9375 {0x46, 0, 0, 0, 0},
9376 {0x47, 0x11, 0x11, 0, 0},
9377 {0x48, 0, 0, 0, 0},
9378 {0x49, 0, 0, 1, 1},
9379 {0x4A, 0x7, 0x7, 0, 0},
9380 {0x4B, 0x6, 0x6, 0, 0},
9381 {0x4C, 0x4, 0x4, 0, 0},
9382 {0x4D, 0, 0, 0, 0},
9383 {0x4E, 0, 0, 0, 0},
9384 {0x4F, 0x26, 0x26, 1, 1},
9385 {0x50, 0x26, 0x26, 1, 1},
9386 {0x51, 0xf, 0xf, 1, 1},
9387 {0x52, 0xf, 0xf, 1, 1},
9388 {0x53, 0x44, 0x44, 0, 0},
9389 {0x54, 0, 0, 0, 0},
9390 {0x55, 0, 0, 0, 0},
9391 {0x56, 0x8, 0x8, 0, 0},
9392 {0x57, 0x8, 0x8, 0, 0},
9393 {0x58, 0x7, 0x7, 0, 0},
9394 {0x59, 0x22, 0x22, 0, 0},
9395 {0x5A, 0x22, 0x22, 0, 0},
9396 {0x5B, 0x2, 0x2, 0, 0},
9397 {0x5C, 0x4, 0x4, 1, 1},
9398 {0x5D, 0x7, 0x7, 0, 0},
9399 {0x5E, 0x55, 0x55, 0, 0},
9400 {0x5F, 0x23, 0x23, 0, 0},
9401 {0x60, 0x41, 0x41, 0, 0},
9402 {0x61, 0x1, 0x1, 0, 0},
9403 {0x62, 0xa, 0xa, 0, 0},
9404 {0x63, 0, 0, 0, 0},
9405 {0x64, 0, 0, 0, 0},
9406 {0x65, 0, 0, 0, 0},
9407 {0x66, 0, 0, 0, 0},
9408 {0x67, 0, 0, 0, 0},
9409 {0x68, 0, 0, 0, 0},
9410 {0x69, 0, 0, 0, 0},
9411 {0x6A, 0, 0, 0, 0},
9412 {0x6B, 0xc, 0xc, 0, 0},
9413 {0x6C, 0, 0, 0, 0},
9414 {0x6D, 0, 0, 0, 0},
9415 {0x6E, 0, 0, 0, 0},
9416 {0x6F, 0, 0, 0, 0},
9417 {0x70, 0, 0, 0, 0},
9418 {0x71, 0, 0, 0, 0},
9419 {0x72, 0x22, 0x22, 0, 0},
9420 {0x73, 0x22, 0x22, 0, 0},
9421 {0x74, 0, 0, 1, 1},
9422 {0x75, 0xa, 0xa, 0, 0},
9423 {0x76, 0x1, 0x1, 0, 0},
9424 {0x77, 0x22, 0x22, 0, 0},
9425 {0x78, 0x30, 0x30, 0, 0},
9426 {0x79, 0, 0, 0, 0},
9427 {0x7A, 0, 0, 0, 0},
9428 {0x7B, 0, 0, 0, 0},
9429 {0x7C, 0, 0, 0, 0},
9430 {0x7D, 0, 0, 0, 0},
9431 {0x7E, 0, 0, 0, 0},
9432 {0x7F, 0, 0, 0, 0},
9433 {0x80, 0, 0, 0, 0},
9434 {0x81, 0, 0, 0, 0},
9435 {0x82, 0, 0, 0, 0},
9436 {0x83, 0, 0, 0, 0},
9437 {0x84, 0, 0, 0, 0},
9438 {0x85, 0, 0, 0, 0},
9439 {0x86, 0, 0, 0, 0},
9440 {0x87, 0, 0, 0, 0},
9441 {0x88, 0, 0, 0, 0},
9442 {0x89, 0, 0, 0, 0},
9443 {0x8A, 0, 0, 0, 0},
9444 {0x8B, 0, 0, 0, 0},
9445 {0x8C, 0, 0, 0, 0},
9446 {0x8D, 0, 0, 0, 0},
9447 {0x8E, 0, 0, 0, 0},
9448 {0x8F, 0, 0, 0, 0},
9449 {0x90, 0, 0, 0, 0},
9450 {0x91, 0, 0, 0, 0},
9451 {0x92, 0, 0, 0, 0},
9452 {0x93, 0, 0, 0, 0},
9453 {0x94, 0, 0, 0, 0},
9454 {0xFFFF, 0, 0, 0, 0}
9455};
9456
9457static struct radio_regs regs_SYN_2056_rev6[] = {
9458 {0x02, 0, 0, 0, 0},
9459 {0x03, 0, 0, 0, 0},
9460 {0x04, 0, 0, 0, 0},
9461 {0x05, 0, 0, 0, 0},
9462 {0x06, 0, 0, 0, 0},
9463 {0x07, 0, 0, 0, 0},
9464 {0x08, 0, 0, 0, 0},
9465 {0x09, 0x1, 0x1, 0, 0},
9466 {0x0A, 0, 0, 0, 0},
9467 {0x0B, 0, 0, 0, 0},
9468 {0x0C, 0, 0, 0, 0},
9469 {0x0D, 0, 0, 0, 0},
9470 {0x0E, 0, 0, 0, 0},
9471 {0x0F, 0, 0, 0, 0},
9472 {0x10, 0, 0, 0, 0},
9473 {0x11, 0, 0, 0, 0},
9474 {0x12, 0, 0, 0, 0},
9475 {0x13, 0, 0, 0, 0},
9476 {0x14, 0, 0, 0, 0},
9477 {0x15, 0, 0, 0, 0},
9478 {0x16, 0, 0, 0, 0},
9479 {0x17, 0, 0, 0, 0},
9480 {0x18, 0, 0, 0, 0},
9481 {0x19, 0, 0, 0, 0},
9482 {0x1A, 0, 0, 0, 0},
9483 {0x1B, 0, 0, 0, 0},
9484 {0x1C, 0, 0, 0, 0},
9485 {0x1D, 0, 0, 0, 0},
9486 {0x1E, 0, 0, 0, 0},
9487 {0x1F, 0, 0, 0, 0},
9488 {0x20, 0, 0, 0, 0},
9489 {0x21, 0, 0, 0, 0},
9490 {0x22, 0x60, 0x60, 0, 0},
9491 {0x23, 0x6, 0x6, 0, 0},
9492 {0x24, 0xc, 0xc, 0, 0},
9493 {0x25, 0, 0, 0, 0},
9494 {0x26, 0, 0, 0, 0},
9495 {0x27, 0, 0, 0, 0},
9496 {0x28, 0x1, 0x1, 0, 0},
9497 {0x29, 0, 0, 0, 0},
9498 {0x2A, 0, 0, 0, 0},
9499 {0x2B, 0, 0, 0, 0},
9500 {0x2C, 0, 0, 0, 0},
9501 {0x2D, 0, 0, 0, 0},
9502 {0x2E, 0, 0, 0, 0},
9503 {0x2F, 0x1f, 0x1f, 0, 0},
9504 {0x30, 0x15, 0x15, 0, 0},
9505 {0x31, 0xf, 0xf, 0, 0},
9506 {0x32, 0, 0, 0, 0},
9507 {0x33, 0, 0, 0, 0},
9508 {0x34, 0, 0, 0, 0},
9509 {0x35, 0, 0, 0, 0},
9510 {0x36, 0, 0, 0, 0},
9511 {0x37, 0, 0, 0, 0},
9512 {0x38, 0, 0, 0, 0},
9513 {0x39, 0, 0, 0, 0},
9514 {0x3A, 0, 0, 0, 0},
9515 {0x3B, 0, 0, 0, 0},
9516 {0x3C, 0x13, 0x13, 0, 0},
9517 {0x3D, 0xf, 0xf, 0, 0},
9518 {0x3E, 0x18, 0x18, 0, 0},
9519 {0x3F, 0, 0, 0, 0},
9520 {0x40, 0, 0, 0, 0},
9521 {0x41, 0x20, 0x20, 0, 0},
9522 {0x42, 0x20, 0x20, 0, 0},
9523 {0x43, 0, 0, 0, 0},
9524 {0x44, 0x77, 0x77, 0, 0},
9525 {0x45, 0x7, 0x7, 0, 0},
9526 {0x46, 0x1, 0x1, 0, 0},
9527 {0x47, 0x4, 0x4, 0, 0},
9528 {0x48, 0xf, 0xf, 0, 0},
9529 {0x49, 0x30, 0x30, 0, 0},
9530 {0x4A, 0x32, 0x32, 0, 0},
9531 {0x4B, 0xd, 0xd, 0, 0},
9532 {0x4C, 0xd, 0xd, 0, 0},
9533 {0x4D, 0x4, 0x4, 0, 0},
9534 {0x4E, 0x6, 0x6, 0, 0},
9535 {0x4F, 0x1, 0x1, 0, 0},
9536 {0x50, 0x1c, 0x1c, 0, 0},
9537 {0x51, 0x2, 0x2, 0, 0},
9538 {0x52, 0x2, 0x2, 0, 0},
9539 {0x53, 0xf7, 0xf7, 1, 1},
9540 {0x54, 0xb4, 0xb4, 0, 0},
9541 {0x55, 0xd2, 0xd2, 0, 0},
9542 {0x56, 0, 0, 0, 0},
9543 {0x57, 0, 0, 0, 0},
9544 {0x58, 0x4, 0x4, 0, 0},
9545 {0x59, 0x96, 0x96, 0, 0},
9546 {0x5A, 0x3e, 0x3e, 0, 0},
9547 {0x5B, 0x3e, 0x3e, 0, 0},
9548 {0x5C, 0x13, 0x13, 0, 0},
9549 {0x5D, 0x2, 0x2, 0, 0},
9550 {0x5E, 0, 0, 0, 0},
9551 {0x5F, 0x7, 0x7, 0, 0},
9552 {0x60, 0x7, 0x7, 1, 1},
9553 {0x61, 0x8, 0x8, 0, 0},
9554 {0x62, 0x3, 0x3, 0, 0},
9555 {0x63, 0, 0, 0, 0},
9556 {0x64, 0, 0, 0, 0},
9557 {0x65, 0, 0, 0, 0},
9558 {0x66, 0, 0, 0, 0},
9559 {0x67, 0, 0, 0, 0},
9560 {0x68, 0x40, 0x40, 0, 0},
9561 {0x69, 0, 0, 0, 0},
9562 {0x6A, 0, 0, 0, 0},
9563 {0x6B, 0, 0, 0, 0},
9564 {0x6C, 0, 0, 0, 0},
9565 {0x6D, 0x1, 0x1, 0, 0},
9566 {0x6E, 0, 0, 0, 0},
9567 {0x6F, 0, 0, 0, 0},
9568 {0x70, 0x60, 0x60, 0, 0},
9569 {0x71, 0x66, 0x66, 0, 0},
9570 {0x72, 0xc, 0xc, 0, 0},
9571 {0x73, 0x66, 0x66, 0, 0},
9572 {0x74, 0x8f, 0x8f, 1, 1},
9573 {0x75, 0, 0, 0, 0},
9574 {0x76, 0xcc, 0xcc, 0, 0},
9575 {0x77, 0x1, 0x1, 0, 0},
9576 {0x78, 0x66, 0x66, 0, 0},
9577 {0x79, 0x66, 0x66, 0, 0},
9578 {0x7A, 0, 0, 0, 0},
9579 {0x7B, 0, 0, 0, 0},
9580 {0x7C, 0, 0, 0, 0},
9581 {0x7D, 0, 0, 0, 0},
9582 {0x7E, 0, 0, 0, 0},
9583 {0x7F, 0, 0, 0, 0},
9584 {0x80, 0, 0, 0, 0},
9585 {0x81, 0, 0, 0, 0},
9586 {0x82, 0, 0, 0, 0},
9587 {0x83, 0, 0, 0, 0},
9588 {0x84, 0, 0, 0, 0},
9589 {0x85, 0xff, 0xff, 0, 0},
9590 {0x86, 0, 0, 0, 0},
9591 {0x87, 0, 0, 0, 0},
9592 {0x88, 0, 0, 0, 0},
9593 {0x89, 0, 0, 0, 0},
9594 {0x8A, 0, 0, 0, 0},
9595 {0x8B, 0, 0, 0, 0},
9596 {0x8C, 0, 0, 0, 0},
9597 {0x8D, 0, 0, 0, 0},
9598 {0x8E, 0, 0, 0, 0},
9599 {0x8F, 0, 0, 0, 0},
9600 {0x90, 0, 0, 0, 0},
9601 {0x91, 0, 0, 0, 0},
9602 {0x92, 0, 0, 0, 0},
9603 {0x93, 0, 0, 0, 0},
9604 {0x94, 0, 0, 0, 0},
9605 {0x95, 0, 0, 0, 0},
9606 {0x96, 0, 0, 0, 0},
9607 {0x97, 0, 0, 0, 0},
9608 {0x98, 0, 0, 0, 0},
9609 {0x99, 0, 0, 0, 0},
9610 {0x9A, 0, 0, 0, 0},
9611 {0x9B, 0, 0, 0, 0},
9612 {0x9C, 0, 0, 0, 0},
9613 {0x9D, 0, 0, 0, 0},
9614 {0x9E, 0, 0, 0, 0},
9615 {0x9F, 0x6, 0x6, 0, 0},
9616 {0xA0, 0x66, 0x66, 0, 0},
9617 {0xA1, 0x66, 0x66, 0, 0},
9618 {0xA2, 0x66, 0x66, 0, 0},
9619 {0xA3, 0x66, 0x66, 0, 0},
9620 {0xA4, 0x66, 0x66, 0, 0},
9621 {0xA5, 0x66, 0x66, 0, 0},
9622 {0xA6, 0x66, 0x66, 0, 0},
9623 {0xA7, 0x66, 0x66, 0, 0},
9624 {0xA8, 0x66, 0x66, 0, 0},
9625 {0xA9, 0x66, 0x66, 0, 0},
9626 {0xAA, 0x66, 0x66, 0, 0},
9627 {0xAB, 0x66, 0x66, 0, 0},
9628 {0xAC, 0x66, 0x66, 0, 0},
9629 {0xAD, 0x66, 0x66, 0, 0},
9630 {0xAE, 0x66, 0x66, 0, 0},
9631 {0xAF, 0x66, 0x66, 0, 0},
9632 {0xB0, 0x66, 0x66, 0, 0},
9633 {0xB1, 0x66, 0x66, 0, 0},
9634 {0xB2, 0x66, 0x66, 0, 0},
9635 {0xB3, 0xa, 0xa, 0, 0},
9636 {0xB4, 0, 0, 0, 0},
9637 {0xB5, 0, 0, 0, 0},
9638 {0xB6, 0, 0, 0, 0},
9639 {0xFFFF, 0, 0, 0, 0}
9640};
9641
9642static struct radio_regs regs_TX_2056_rev6[] = {
9643 {0x02, 0, 0, 0, 0},
9644 {0x03, 0, 0, 0, 0},
9645 {0x04, 0, 0, 0, 0},
9646 {0x05, 0, 0, 0, 0},
9647 {0x06, 0, 0, 0, 0},
9648 {0x07, 0, 0, 0, 0},
9649 {0x08, 0, 0, 0, 0},
9650 {0x09, 0, 0, 0, 0},
9651 {0x0A, 0, 0, 0, 0},
9652 {0x0B, 0, 0, 0, 0},
9653 {0x0C, 0, 0, 0, 0},
9654 {0x0D, 0, 0, 0, 0},
9655 {0x0E, 0, 0, 0, 0},
9656 {0x0F, 0, 0, 0, 0},
9657 {0x10, 0, 0, 0, 0},
9658 {0x11, 0, 0, 0, 0},
9659 {0x12, 0, 0, 0, 0},
9660 {0x13, 0, 0, 0, 0},
9661 {0x14, 0, 0, 0, 0},
9662 {0x15, 0, 0, 0, 0},
9663 {0x16, 0, 0, 0, 0},
9664 {0x17, 0, 0, 0, 0},
9665 {0x18, 0, 0, 0, 0},
9666 {0x19, 0, 0, 0, 0},
9667 {0x1A, 0, 0, 0, 0},
9668 {0x1B, 0, 0, 0, 0},
9669 {0x1C, 0, 0, 0, 0},
9670 {0x1D, 0, 0, 0, 0},
9671 {0x1E, 0, 0, 0, 0},
9672 {0x1F, 0, 0, 0, 0},
9673 {0x20, 0, 0, 0, 0},
9674 {0x21, 0x88, 0x88, 0, 0},
9675 {0x22, 0x88, 0x88, 0, 0},
9676 {0x23, 0x88, 0x88, 0, 0},
9677 {0x24, 0x88, 0x88, 0, 0},
9678 {0x25, 0xc, 0xc, 0, 0},
9679 {0x26, 0, 0, 0, 0},
9680 {0x27, 0x3, 0x3, 0, 0},
9681 {0x28, 0, 0, 0, 0},
9682 {0x29, 0x3, 0x3, 0, 0},
9683 {0x2A, 0x37, 0x37, 0, 0},
9684 {0x2B, 0x3, 0x3, 0, 0},
9685 {0x2C, 0, 0, 0, 0},
9686 {0x2D, 0, 0, 0, 0},
9687 {0x2E, 0x1, 0x1, 0, 0},
9688 {0x2F, 0x1, 0x1, 0, 0},
9689 {0x30, 0, 0, 0, 0},
9690 {0x31, 0, 0, 0, 0},
9691 {0x32, 0, 0, 0, 0},
9692 {0x33, 0x11, 0x11, 0, 0},
9693 {0x34, 0xee, 0xee, 1, 1},
9694 {0x35, 0, 0, 0, 0},
9695 {0x36, 0, 0, 0, 0},
9696 {0x37, 0x3, 0x3, 0, 0},
9697 {0x38, 0x50, 0x50, 1, 1},
9698 {0x39, 0, 0, 0, 0},
9699 {0x3A, 0x50, 0x50, 1, 1},
9700 {0x3B, 0, 0, 0, 0},
9701 {0x3C, 0x6e, 0x6e, 0, 0},
9702 {0x3D, 0xf0, 0xf0, 1, 1},
9703 {0x3E, 0, 0, 0, 0},
9704 {0x3F, 0, 0, 0, 0},
9705 {0x40, 0, 0, 0, 0},
9706 {0x41, 0x3, 0x3, 0, 0},
9707 {0x42, 0x3, 0x3, 0, 0},
9708 {0x43, 0, 0, 0, 0},
9709 {0x44, 0x1e, 0x1e, 0, 0},
9710 {0x45, 0, 0, 0, 0},
9711 {0x46, 0x6e, 0x6e, 0, 0},
9712 {0x47, 0xf0, 0xf0, 1, 1},
9713 {0x48, 0, 0, 0, 0},
9714 {0x49, 0x2, 0x2, 0, 0},
9715 {0x4A, 0xff, 0xff, 1, 1},
9716 {0x4B, 0xc, 0xc, 0, 0},
9717 {0x4C, 0, 0, 0, 0},
9718 {0x4D, 0x38, 0x38, 0, 0},
9719 {0x4E, 0x70, 0x70, 1, 1},
9720 {0x4F, 0x2, 0x2, 0, 0},
9721 {0x50, 0x88, 0x88, 0, 0},
9722 {0x51, 0xc, 0xc, 0, 0},
9723 {0x52, 0, 0, 0, 0},
9724 {0x53, 0x8, 0x8, 0, 0},
9725 {0x54, 0x70, 0x70, 1, 1},
9726 {0x55, 0x2, 0x2, 0, 0},
9727 {0x56, 0xff, 0xff, 1, 1},
9728 {0x57, 0, 0, 0, 0},
9729 {0x58, 0x83, 0x83, 0, 0},
9730 {0x59, 0x77, 0x77, 1, 1},
9731 {0x5A, 0, 0, 0, 0},
9732 {0x5B, 0x2, 0x2, 0, 0},
9733 {0x5C, 0x88, 0x88, 0, 0},
9734 {0x5D, 0, 0, 0, 0},
9735 {0x5E, 0x8, 0x8, 0, 0},
9736 {0x5F, 0x77, 0x77, 1, 1},
9737 {0x60, 0x1, 0x1, 0, 0},
9738 {0x61, 0, 0, 0, 0},
9739 {0x62, 0x7, 0x7, 0, 0},
9740 {0x63, 0, 0, 0, 0},
9741 {0x64, 0x7, 0x7, 0, 0},
9742 {0x65, 0, 0, 0, 0},
9743 {0x66, 0, 0, 0, 0},
9744 {0x67, 0, 0, 1, 1},
9745 {0x68, 0, 0, 0, 0},
9746 {0x69, 0xa, 0xa, 0, 0},
9747 {0x6A, 0, 0, 0, 0},
9748 {0x6B, 0, 0, 0, 0},
9749 {0x6C, 0, 0, 0, 0},
9750 {0x6D, 0, 0, 0, 0},
9751 {0x6E, 0, 0, 0, 0},
9752 {0x6F, 0, 0, 0, 0},
9753 {0x70, 0, 0, 0, 0},
9754 {0x71, 0x2, 0x2, 0, 0},
9755 {0x72, 0, 0, 0, 0},
9756 {0x73, 0, 0, 0, 0},
9757 {0x74, 0xe, 0xe, 0, 0},
9758 {0x75, 0xe, 0xe, 0, 0},
9759 {0x76, 0xe, 0xe, 0, 0},
9760 {0x77, 0x13, 0x13, 0, 0},
9761 {0x78, 0x13, 0x13, 0, 0},
9762 {0x79, 0x1b, 0x1b, 0, 0},
9763 {0x7A, 0x1b, 0x1b, 0, 0},
9764 {0x7B, 0x55, 0x55, 0, 0},
9765 {0x7C, 0x5b, 0x5b, 0, 0},
9766 {0x7D, 0x30, 0x30, 1, 1},
9767 {0x7E, 0, 0, 0, 0},
9768 {0x7F, 0, 0, 0, 0},
9769 {0x80, 0, 0, 0, 0},
9770 {0x81, 0, 0, 0, 0},
9771 {0x82, 0, 0, 0, 0},
9772 {0x83, 0, 0, 0, 0},
9773 {0x84, 0, 0, 0, 0},
9774 {0x85, 0, 0, 0, 0},
9775 {0x86, 0, 0, 0, 0},
9776 {0x87, 0, 0, 0, 0},
9777 {0x88, 0, 0, 0, 0},
9778 {0x89, 0, 0, 0, 0},
9779 {0x8A, 0, 0, 0, 0},
9780 {0x8B, 0, 0, 0, 0},
9781 {0x8C, 0, 0, 0, 0},
9782 {0x8D, 0, 0, 0, 0},
9783 {0x8E, 0, 0, 0, 0},
9784 {0x8F, 0, 0, 0, 0},
9785 {0x90, 0, 0, 0, 0},
9786 {0x91, 0, 0, 0, 0},
9787 {0x92, 0, 0, 0, 0},
9788 {0x93, 0x70, 0x70, 0, 0},
9789 {0x94, 0x70, 0x70, 0, 0},
9790 {0x95, 0x70, 0x70, 0, 0},
9791 {0x96, 0x70, 0x70, 0, 0},
9792 {0x97, 0x70, 0x70, 0, 0},
9793 {0x98, 0x70, 0x70, 0, 0},
9794 {0x99, 0x70, 0x70, 0, 0},
9795 {0x9A, 0x70, 0x70, 0, 0},
9796 {0xFFFF, 0, 0, 0, 0}
9797};
9798
9799static struct radio_regs regs_RX_2056_rev6[] = {
9800 {0x02, 0, 0, 0, 0},
9801 {0x03, 0, 0, 0, 0},
9802 {0x04, 0, 0, 0, 0},
9803 {0x05, 0, 0, 0, 0},
9804 {0x06, 0, 0, 0, 0},
9805 {0x07, 0, 0, 0, 0},
9806 {0x08, 0, 0, 0, 0},
9807 {0x09, 0, 0, 0, 0},
9808 {0x0A, 0, 0, 0, 0},
9809 {0x0B, 0, 0, 0, 0},
9810 {0x0C, 0, 0, 0, 0},
9811 {0x0D, 0, 0, 0, 0},
9812 {0x0E, 0, 0, 0, 0},
9813 {0x0F, 0, 0, 0, 0},
9814 {0x10, 0, 0, 0, 0},
9815 {0x11, 0, 0, 0, 0},
9816 {0x12, 0, 0, 0, 0},
9817 {0x13, 0, 0, 0, 0},
9818 {0x14, 0, 0, 0, 0},
9819 {0x15, 0, 0, 0, 0},
9820 {0x16, 0, 0, 0, 0},
9821 {0x17, 0, 0, 0, 0},
9822 {0x18, 0, 0, 0, 0},
9823 {0x19, 0, 0, 0, 0},
9824 {0x1A, 0, 0, 0, 0},
9825 {0x1B, 0, 0, 0, 0},
9826 {0x1C, 0, 0, 0, 0},
9827 {0x1D, 0, 0, 0, 0},
9828 {0x1E, 0, 0, 0, 0},
9829 {0x1F, 0, 0, 0, 0},
9830 {0x20, 0x3, 0x3, 0, 0},
9831 {0x21, 0, 0, 0, 0},
9832 {0x22, 0, 0, 0, 0},
9833 {0x23, 0x90, 0x90, 0, 0},
9834 {0x24, 0x55, 0x55, 0, 0},
9835 {0x25, 0x15, 0x15, 0, 0},
9836 {0x26, 0x5, 0x5, 0, 0},
9837 {0x27, 0x15, 0x15, 0, 0},
9838 {0x28, 0x5, 0x5, 0, 0},
9839 {0x29, 0x20, 0x20, 0, 0},
9840 {0x2A, 0x11, 0x11, 0, 0},
9841 {0x2B, 0x90, 0x90, 0, 0},
9842 {0x2C, 0, 0, 0, 0},
9843 {0x2D, 0x88, 0x88, 0, 0},
9844 {0x2E, 0x32, 0x32, 0, 0},
9845 {0x2F, 0x77, 0x77, 0, 0},
9846 {0x30, 0x17, 0x17, 1, 1},
9847 {0x31, 0xff, 0xff, 1, 1},
9848 {0x32, 0x20, 0x20, 0, 0},
9849 {0x33, 0, 0, 0, 0},
9850 {0x34, 0x88, 0x88, 0, 0},
9851 {0x35, 0x32, 0x32, 0, 0},
9852 {0x36, 0x77, 0x77, 0, 0},
9853 {0x37, 0x17, 0x17, 1, 1},
9854 {0x38, 0xf0, 0xf0, 1, 1},
9855 {0x39, 0x20, 0x20, 0, 0},
9856 {0x3A, 0x8, 0x8, 0, 0},
9857 {0x3B, 0x55, 0x55, 1, 1},
9858 {0x3C, 0, 0, 0, 0},
9859 {0x3D, 0x88, 0x88, 1, 1},
9860 {0x3E, 0, 0, 0, 0},
9861 {0x3F, 0x44, 0x44, 0, 0},
9862 {0x40, 0x7, 0x7, 1, 1},
9863 {0x41, 0x6, 0x6, 0, 0},
9864 {0x42, 0x4, 0x4, 0, 0},
9865 {0x43, 0, 0, 0, 0},
9866 {0x44, 0x8, 0x8, 0, 0},
9867 {0x45, 0x55, 0x55, 1, 1},
9868 {0x46, 0, 0, 0, 0},
9869 {0x47, 0x11, 0x11, 0, 0},
9870 {0x48, 0, 0, 0, 0},
9871 {0x49, 0x44, 0x44, 0, 0},
9872 {0x4A, 0x7, 0x7, 0, 0},
9873 {0x4B, 0x6, 0x6, 0, 0},
9874 {0x4C, 0x4, 0x4, 0, 0},
9875 {0x4D, 0, 0, 0, 0},
9876 {0x4E, 0, 0, 0, 0},
9877 {0x4F, 0x26, 0x26, 1, 1},
9878 {0x50, 0x26, 0x26, 1, 1},
9879 {0x51, 0xf, 0xf, 1, 1},
9880 {0x52, 0xf, 0xf, 1, 1},
9881 {0x53, 0x44, 0x44, 0, 0},
9882 {0x54, 0, 0, 0, 0},
9883 {0x55, 0, 0, 0, 0},
9884 {0x56, 0x8, 0x8, 0, 0},
9885 {0x57, 0x8, 0x8, 0, 0},
9886 {0x58, 0x7, 0x7, 0, 0},
9887 {0x59, 0x22, 0x22, 0, 0},
9888 {0x5A, 0x22, 0x22, 0, 0},
9889 {0x5B, 0x2, 0x2, 0, 0},
9890 {0x5C, 0x4, 0x4, 1, 1},
9891 {0x5D, 0x7, 0x7, 0, 0},
9892 {0x5E, 0x55, 0x55, 0, 0},
9893 {0x5F, 0x23, 0x23, 0, 0},
9894 {0x60, 0x41, 0x41, 0, 0},
9895 {0x61, 0x1, 0x1, 0, 0},
9896 {0x62, 0xa, 0xa, 0, 0},
9897 {0x63, 0, 0, 0, 0},
9898 {0x64, 0, 0, 0, 0},
9899 {0x65, 0, 0, 0, 0},
9900 {0x66, 0, 0, 0, 0},
9901 {0x67, 0, 0, 0, 0},
9902 {0x68, 0, 0, 0, 0},
9903 {0x69, 0, 0, 0, 0},
9904 {0x6A, 0, 0, 0, 0},
9905 {0x6B, 0xc, 0xc, 0, 0},
9906 {0x6C, 0, 0, 0, 0},
9907 {0x6D, 0, 0, 0, 0},
9908 {0x6E, 0, 0, 0, 0},
9909 {0x6F, 0, 0, 0, 0},
9910 {0x70, 0, 0, 0, 0},
9911 {0x71, 0, 0, 0, 0},
9912 {0x72, 0x22, 0x22, 0, 0},
9913 {0x73, 0x22, 0x22, 0, 0},
9914 {0x74, 0, 0, 1, 1},
9915 {0x75, 0xa, 0xa, 0, 0},
9916 {0x76, 0x1, 0x1, 0, 0},
9917 {0x77, 0x22, 0x22, 0, 0},
9918 {0x78, 0x30, 0x30, 0, 0},
9919 {0x79, 0, 0, 0, 0},
9920 {0x7A, 0, 0, 0, 0},
9921 {0x7B, 0, 0, 0, 0},
9922 {0x7C, 0, 0, 0, 0},
9923 {0x7D, 0x5, 0x5, 1, 1},
9924 {0x7E, 0, 0, 0, 0},
9925 {0x7F, 0, 0, 0, 0},
9926 {0x80, 0, 0, 0, 0},
9927 {0x81, 0, 0, 0, 0},
9928 {0x82, 0, 0, 0, 0},
9929 {0x83, 0, 0, 0, 0},
9930 {0x84, 0, 0, 0, 0},
9931 {0x85, 0, 0, 0, 0},
9932 {0x86, 0, 0, 0, 0},
9933 {0x87, 0, 0, 0, 0},
9934 {0x88, 0, 0, 0, 0},
9935 {0x89, 0, 0, 0, 0},
9936 {0x8A, 0, 0, 0, 0},
9937 {0x8B, 0, 0, 0, 0},
9938 {0x8C, 0, 0, 0, 0},
9939 {0x8D, 0, 0, 0, 0},
9940 {0x8E, 0, 0, 0, 0},
9941 {0x8F, 0, 0, 0, 0},
9942 {0x90, 0, 0, 0, 0},
9943 {0x91, 0, 0, 0, 0},
9944 {0x92, 0, 0, 0, 0},
9945 {0x93, 0, 0, 0, 0},
9946 {0x94, 0, 0, 0, 0},
9947 {0xFFFF, 0, 0, 0, 0}
9948};
9949
9950static struct radio_regs regs_SYN_2056_rev7[] = {
9951 {0x02, 0, 0, 0, 0},
9952 {0x03, 0, 0, 0, 0},
9953 {0x04, 0, 0, 0, 0},
9954 {0x05, 0, 0, 0, 0},
9955 {0x06, 0, 0, 0, 0},
9956 {0x07, 0, 0, 0, 0},
9957 {0x08, 0, 0, 0, 0},
9958 {0x09, 0x1, 0x1, 0, 0},
9959 {0x0A, 0, 0, 0, 0},
9960 {0x0B, 0, 0, 0, 0},
9961 {0x0C, 0, 0, 0, 0},
9962 {0x0D, 0, 0, 0, 0},
9963 {0x0E, 0, 0, 0, 0},
9964 {0x0F, 0, 0, 0, 0},
9965 {0x10, 0, 0, 0, 0},
9966 {0x11, 0, 0, 0, 0},
9967 {0x12, 0, 0, 0, 0},
9968 {0x13, 0, 0, 0, 0},
9969 {0x14, 0, 0, 0, 0},
9970 {0x15, 0, 0, 0, 0},
9971 {0x16, 0, 0, 0, 0},
9972 {0x17, 0, 0, 0, 0},
9973 {0x18, 0, 0, 0, 0},
9974 {0x19, 0, 0, 0, 0},
9975 {0x1A, 0, 0, 0, 0},
9976 {0x1B, 0, 0, 0, 0},
9977 {0x1C, 0, 0, 0, 0},
9978 {0x1D, 0, 0, 0, 0},
9979 {0x1E, 0, 0, 0, 0},
9980 {0x1F, 0, 0, 0, 0},
9981 {0x20, 0, 0, 0, 0},
9982 {0x21, 0, 0, 0, 0},
9983 {0x22, 0x60, 0x60, 0, 0},
9984 {0x23, 0x6, 0x6, 0, 0},
9985 {0x24, 0xc, 0xc, 0, 0},
9986 {0x25, 0, 0, 0, 0},
9987 {0x26, 0, 0, 0, 0},
9988 {0x27, 0, 0, 0, 0},
9989 {0x28, 0x1, 0x1, 0, 0},
9990 {0x29, 0, 0, 0, 0},
9991 {0x2A, 0, 0, 0, 0},
9992 {0x2B, 0, 0, 0, 0},
9993 {0x2C, 0, 0, 0, 0},
9994 {0x2D, 0, 0, 0, 0},
9995 {0x2E, 0, 0, 0, 0},
9996 {0x2F, 0x1f, 0x1f, 0, 0},
9997 {0x30, 0x15, 0x15, 0, 0},
9998 {0x31, 0xf, 0xf, 0, 0},
9999 {0x32, 0, 0, 0, 0},
10000 {0x33, 0, 0, 0, 0},
10001 {0x34, 0, 0, 0, 0},
10002 {0x35, 0, 0, 0, 0},
10003 {0x36, 0, 0, 0, 0},
10004 {0x37, 0, 0, 0, 0},
10005 {0x38, 0, 0, 0, 0},
10006 {0x39, 0, 0, 0, 0},
10007 {0x3A, 0, 0, 0, 0},
10008 {0x3B, 0, 0, 0, 0},
10009 {0x3C, 0x13, 0x13, 0, 0},
10010 {0x3D, 0xf, 0xf, 0, 0},
10011 {0x3E, 0x18, 0x18, 0, 0},
10012 {0x3F, 0, 0, 0, 0},
10013 {0x40, 0, 0, 0, 0},
10014 {0x41, 0x20, 0x20, 0, 0},
10015 {0x42, 0x20, 0x20, 0, 0},
10016 {0x43, 0, 0, 0, 0},
10017 {0x44, 0x77, 0x77, 0, 0},
10018 {0x45, 0x7, 0x7, 0, 0},
10019 {0x46, 0x1, 0x1, 0, 0},
10020 {0x47, 0x4, 0x4, 0, 0},
10021 {0x48, 0xf, 0xf, 0, 0},
10022 {0x49, 0x30, 0x30, 0, 0},
10023 {0x4A, 0x32, 0x32, 0, 0},
10024 {0x4B, 0xd, 0xd, 0, 0},
10025 {0x4C, 0xd, 0xd, 0, 0},
10026 {0x4D, 0x4, 0x4, 0, 0},
10027 {0x4E, 0x6, 0x6, 0, 0},
10028 {0x4F, 0x1, 0x1, 0, 0},
10029 {0x50, 0x1c, 0x1c, 0, 0},
10030 {0x51, 0x2, 0x2, 0, 0},
10031 {0x52, 0x2, 0x2, 0, 0},
10032 {0x53, 0xf7, 0xf7, 1, 1},
10033 {0x54, 0xb4, 0xb4, 0, 0},
10034 {0x55, 0xd2, 0xd2, 0, 0},
10035 {0x56, 0, 0, 0, 0},
10036 {0x57, 0, 0, 0, 0},
10037 {0x58, 0x4, 0x4, 0, 0},
10038 {0x59, 0x96, 0x96, 0, 0},
10039 {0x5A, 0x3e, 0x3e, 0, 0},
10040 {0x5B, 0x3e, 0x3e, 0, 0},
10041 {0x5C, 0x13, 0x13, 0, 0},
10042 {0x5D, 0x2, 0x2, 0, 0},
10043 {0x5E, 0, 0, 0, 0},
10044 {0x5F, 0x7, 0x7, 0, 0},
10045 {0x60, 0x7, 0x7, 1, 1},
10046 {0x61, 0x8, 0x8, 0, 0},
10047 {0x62, 0x3, 0x3, 0, 0},
10048 {0x63, 0, 0, 0, 0},
10049 {0x64, 0, 0, 0, 0},
10050 {0x65, 0, 0, 0, 0},
10051 {0x66, 0, 0, 0, 0},
10052 {0x67, 0, 0, 0, 0},
10053 {0x68, 0x40, 0x40, 0, 0},
10054 {0x69, 0, 0, 0, 0},
10055 {0x6A, 0, 0, 0, 0},
10056 {0x6B, 0, 0, 0, 0},
10057 {0x6C, 0, 0, 0, 0},
10058 {0x6D, 0x1, 0x1, 0, 0},
10059 {0x6E, 0, 0, 0, 0},
10060 {0x6F, 0, 0, 0, 0},
10061 {0x70, 0x60, 0x60, 0, 0},
10062 {0x71, 0x66, 0x66, 0, 0},
10063 {0x72, 0xc, 0xc, 0, 0},
10064 {0x73, 0x66, 0x66, 0, 0},
10065 {0x74, 0x8f, 0x8f, 1, 1},
10066 {0x75, 0, 0, 0, 0},
10067 {0x76, 0xcc, 0xcc, 0, 0},
10068 {0x77, 0x1, 0x1, 0, 0},
10069 {0x78, 0x66, 0x66, 0, 0},
10070 {0x79, 0x66, 0x66, 0, 0},
10071 {0x7A, 0, 0, 0, 0},
10072 {0x7B, 0, 0, 0, 0},
10073 {0x7C, 0, 0, 0, 0},
10074 {0x7D, 0, 0, 0, 0},
10075 {0x7E, 0, 0, 0, 0},
10076 {0x7F, 0, 0, 0, 0},
10077 {0x80, 0, 0, 0, 0},
10078 {0x81, 0, 0, 0, 0},
10079 {0x82, 0, 0, 0, 0},
10080 {0x83, 0, 0, 0, 0},
10081 {0x84, 0, 0, 0, 0},
10082 {0x85, 0xff, 0xff, 0, 0},
10083 {0x86, 0, 0, 0, 0},
10084 {0x87, 0, 0, 0, 0},
10085 {0x88, 0, 0, 0, 0},
10086 {0x89, 0, 0, 0, 0},
10087 {0x8A, 0, 0, 0, 0},
10088 {0x8B, 0, 0, 0, 0},
10089 {0x8C, 0, 0, 0, 0},
10090 {0x8D, 0, 0, 0, 0},
10091 {0x8E, 0, 0, 0, 0},
10092 {0x8F, 0, 0, 0, 0},
10093 {0x90, 0, 0, 0, 0},
10094 {0x91, 0, 0, 0, 0},
10095 {0x92, 0, 0, 0, 0},
10096 {0x93, 0, 0, 0, 0},
10097 {0x94, 0, 0, 0, 0},
10098 {0x95, 0, 0, 0, 0},
10099 {0x96, 0, 0, 0, 0},
10100 {0x97, 0, 0, 0, 0},
10101 {0x98, 0, 0, 0, 0},
10102 {0x99, 0, 0, 0, 0},
10103 {0x9A, 0, 0, 0, 0},
10104 {0x9B, 0, 0, 0, 0},
10105 {0x9C, 0, 0, 0, 0},
10106 {0x9D, 0, 0, 0, 0},
10107 {0x9E, 0, 0, 0, 0},
10108 {0x9F, 0x6, 0x6, 0, 0},
10109 {0xA0, 0x66, 0x66, 0, 0},
10110 {0xA1, 0x66, 0x66, 0, 0},
10111 {0xA2, 0x66, 0x66, 0, 0},
10112 {0xA3, 0x66, 0x66, 0, 0},
10113 {0xA4, 0x66, 0x66, 0, 0},
10114 {0xA5, 0x66, 0x66, 0, 0},
10115 {0xA6, 0x66, 0x66, 0, 0},
10116 {0xA7, 0x66, 0x66, 0, 0},
10117 {0xA8, 0x66, 0x66, 0, 0},
10118 {0xA9, 0x66, 0x66, 0, 0},
10119 {0xAA, 0x66, 0x66, 0, 0},
10120 {0xAB, 0x66, 0x66, 0, 0},
10121 {0xAC, 0x66, 0x66, 0, 0},
10122 {0xAD, 0x66, 0x66, 0, 0},
10123 {0xAE, 0x66, 0x66, 0, 0},
10124 {0xAF, 0x66, 0x66, 0, 0},
10125 {0xB0, 0x66, 0x66, 0, 0},
10126 {0xB1, 0x66, 0x66, 0, 0},
10127 {0xB2, 0x66, 0x66, 0, 0},
10128 {0xB3, 0xa, 0xa, 0, 0},
10129 {0xB4, 0, 0, 0, 0},
10130 {0xB5, 0, 0, 0, 0},
10131 {0xB6, 0, 0, 0, 0},
10132 {0xFFFF, 0, 0, 0, 0},
10133};
10134
10135static struct radio_regs regs_TX_2056_rev7[] = {
10136 {0x02, 0, 0, 0, 0},
10137 {0x03, 0, 0, 0, 0},
10138 {0x04, 0, 0, 0, 0},
10139 {0x05, 0, 0, 0, 0},
10140 {0x06, 0, 0, 0, 0},
10141 {0x07, 0, 0, 0, 0},
10142 {0x08, 0, 0, 0, 0},
10143 {0x09, 0, 0, 0, 0},
10144 {0x0A, 0, 0, 0, 0},
10145 {0x0B, 0, 0, 0, 0},
10146 {0x0C, 0, 0, 0, 0},
10147 {0x0D, 0, 0, 0, 0},
10148 {0x0E, 0, 0, 0, 0},
10149 {0x0F, 0, 0, 0, 0},
10150 {0x10, 0, 0, 0, 0},
10151 {0x11, 0, 0, 0, 0},
10152 {0x12, 0, 0, 0, 0},
10153 {0x13, 0, 0, 0, 0},
10154 {0x14, 0, 0, 0, 0},
10155 {0x15, 0, 0, 0, 0},
10156 {0x16, 0, 0, 0, 0},
10157 {0x17, 0, 0, 0, 0},
10158 {0x18, 0, 0, 0, 0},
10159 {0x19, 0, 0, 0, 0},
10160 {0x1A, 0, 0, 0, 0},
10161 {0x1B, 0, 0, 0, 0},
10162 {0x1C, 0, 0, 0, 0},
10163 {0x1D, 0, 0, 0, 0},
10164 {0x1E, 0, 0, 0, 0},
10165 {0x1F, 0, 0, 0, 0},
10166 {0x20, 0, 0, 0, 0},
10167 {0x21, 0x88, 0x88, 0, 0},
10168 {0x22, 0x88, 0x88, 0, 0},
10169 {0x23, 0x88, 0x88, 0, 0},
10170 {0x24, 0x88, 0x88, 0, 0},
10171 {0x25, 0xc, 0xc, 0, 0},
10172 {0x26, 0, 0, 0, 0},
10173 {0x27, 0x3, 0x3, 0, 0},
10174 {0x28, 0, 0, 0, 0},
10175 {0x29, 0x3, 0x3, 0, 0},
10176 {0x2A, 0x37, 0x37, 0, 0},
10177 {0x2B, 0x3, 0x3, 0, 0},
10178 {0x2C, 0, 0, 0, 0},
10179 {0x2D, 0, 0, 0, 0},
10180 {0x2E, 0x1, 0x1, 0, 0},
10181 {0x2F, 0x1, 0x1, 0, 0},
10182 {0x30, 0, 0, 0, 0},
10183 {0x31, 0, 0, 0, 0},
10184 {0x32, 0, 0, 0, 0},
10185 {0x33, 0x11, 0x11, 0, 0},
10186 {0x34, 0xee, 0xee, 1, 1},
10187 {0x35, 0, 0, 0, 0},
10188 {0x36, 0, 0, 0, 0},
10189 {0x37, 0x3, 0x3, 0, 0},
10190 {0x38, 0x50, 0x50, 1, 1},
10191 {0x39, 0, 0, 0, 0},
10192 {0x3A, 0x50, 0x50, 1, 1},
10193 {0x3B, 0, 0, 0, 0},
10194 {0x3C, 0x6e, 0x6e, 0, 0},
10195 {0x3D, 0xf0, 0xf0, 1, 1},
10196 {0x3E, 0, 0, 0, 0},
10197 {0x3F, 0, 0, 0, 0},
10198 {0x40, 0, 0, 0, 0},
10199 {0x41, 0x3, 0x3, 0, 0},
10200 {0x42, 0x3, 0x3, 0, 0},
10201 {0x43, 0, 0, 0, 0},
10202 {0x44, 0x1e, 0x1e, 0, 0},
10203 {0x45, 0, 0, 0, 0},
10204 {0x46, 0x6e, 0x6e, 0, 0},
10205 {0x47, 0xf0, 0xf0, 1, 1},
10206 {0x48, 0, 0, 0, 0},
10207 {0x49, 0x2, 0x2, 0, 0},
10208 {0x4A, 0xff, 0xff, 1, 1},
10209 {0x4B, 0xc, 0xc, 0, 0},
10210 {0x4C, 0, 0, 0, 0},
10211 {0x4D, 0x38, 0x38, 0, 0},
10212 {0x4E, 0x70, 0x70, 1, 1},
10213 {0x4F, 0x2, 0x2, 0, 0},
10214 {0x50, 0x88, 0x88, 0, 0},
10215 {0x51, 0xc, 0xc, 0, 0},
10216 {0x52, 0, 0, 0, 0},
10217 {0x53, 0x8, 0x8, 0, 0},
10218 {0x54, 0x70, 0x70, 1, 1},
10219 {0x55, 0x2, 0x2, 0, 0},
10220 {0x56, 0xff, 0xff, 1, 1},
10221 {0x57, 0, 0, 0, 0},
10222 {0x58, 0x83, 0x83, 0, 0},
10223 {0x59, 0x77, 0x77, 1, 1},
10224 {0x5A, 0, 0, 0, 0},
10225 {0x5B, 0x2, 0x2, 0, 0},
10226 {0x5C, 0x88, 0x88, 0, 0},
10227 {0x5D, 0, 0, 0, 0},
10228 {0x5E, 0x8, 0x8, 0, 0},
10229 {0x5F, 0x77, 0x77, 1, 1},
10230 {0x60, 0x1, 0x1, 0, 0},
10231 {0x61, 0, 0, 0, 0},
10232 {0x62, 0x7, 0x7, 0, 0},
10233 {0x63, 0, 0, 0, 0},
10234 {0x64, 0x7, 0x7, 0, 0},
10235 {0x65, 0, 0, 0, 0},
10236 {0x66, 0, 0, 0, 0},
10237 {0x67, 0, 0, 1, 1},
10238 {0x68, 0, 0, 0, 0},
10239 {0x69, 0xa, 0xa, 0, 0},
10240 {0x6A, 0, 0, 0, 0},
10241 {0x6B, 0, 0, 0, 0},
10242 {0x6C, 0, 0, 0, 0},
10243 {0x6D, 0, 0, 0, 0},
10244 {0x6E, 0, 0, 0, 0},
10245 {0x6F, 0, 0, 0, 0},
10246 {0x70, 0, 0, 0, 0},
10247 {0x71, 0x2, 0x2, 0, 0},
10248 {0x72, 0, 0, 0, 0},
10249 {0x73, 0, 0, 0, 0},
10250 {0x74, 0xe, 0xe, 0, 0},
10251 {0x75, 0xe, 0xe, 0, 0},
10252 {0x76, 0xe, 0xe, 0, 0},
10253 {0x77, 0x13, 0x13, 0, 0},
10254 {0x78, 0x13, 0x13, 0, 0},
10255 {0x79, 0x1b, 0x1b, 0, 0},
10256 {0x7A, 0x1b, 0x1b, 0, 0},
10257 {0x7B, 0x55, 0x55, 0, 0},
10258 {0x7C, 0x5b, 0x5b, 0, 0},
10259 {0x7D, 0x30, 0x30, 1, 1},
10260 {0x7E, 0, 0, 0, 0},
10261 {0x7F, 0, 0, 0, 0},
10262 {0x80, 0, 0, 0, 0},
10263 {0x81, 0, 0, 0, 0},
10264 {0x82, 0, 0, 0, 0},
10265 {0x83, 0, 0, 0, 0},
10266 {0x84, 0, 0, 0, 0},
10267 {0x85, 0, 0, 0, 0},
10268 {0x86, 0, 0, 0, 0},
10269 {0x87, 0, 0, 0, 0},
10270 {0x88, 0, 0, 0, 0},
10271 {0x89, 0, 0, 0, 0},
10272 {0x8A, 0, 0, 0, 0},
10273 {0x8B, 0, 0, 0, 0},
10274 {0x8C, 0, 0, 0, 0},
10275 {0x8D, 0, 0, 0, 0},
10276 {0x8E, 0, 0, 0, 0},
10277 {0x8F, 0, 0, 0, 0},
10278 {0x90, 0, 0, 0, 0},
10279 {0x91, 0, 0, 0, 0},
10280 {0x92, 0, 0, 0, 0},
10281 {0x93, 0x70, 0x70, 0, 0},
10282 {0x94, 0x70, 0x70, 0, 0},
10283 {0x95, 0x71, 0x71, 1, 1},
10284 {0x96, 0x71, 0x71, 1, 1},
10285 {0x97, 0x72, 0x72, 1, 1},
10286 {0x98, 0x73, 0x73, 1, 1},
10287 {0x99, 0x74, 0x74, 1, 1},
10288 {0x9A, 0x75, 0x75, 1, 1},
10289 {0xFFFF, 0, 0, 0, 0},
10290};
10291
10292static struct radio_regs regs_RX_2056_rev7[] = {
10293 {0x02, 0, 0, 0, 0},
10294 {0x03, 0, 0, 0, 0},
10295 {0x04, 0, 0, 0, 0},
10296 {0x05, 0, 0, 0, 0},
10297 {0x06, 0, 0, 0, 0},
10298 {0x07, 0, 0, 0, 0},
10299 {0x08, 0, 0, 0, 0},
10300 {0x09, 0, 0, 0, 0},
10301 {0x0A, 0, 0, 0, 0},
10302 {0x0B, 0, 0, 0, 0},
10303 {0x0C, 0, 0, 0, 0},
10304 {0x0D, 0, 0, 0, 0},
10305 {0x0E, 0, 0, 0, 0},
10306 {0x0F, 0, 0, 0, 0},
10307 {0x10, 0, 0, 0, 0},
10308 {0x11, 0, 0, 0, 0},
10309 {0x12, 0, 0, 0, 0},
10310 {0x13, 0, 0, 0, 0},
10311 {0x14, 0, 0, 0, 0},
10312 {0x15, 0, 0, 0, 0},
10313 {0x16, 0, 0, 0, 0},
10314 {0x17, 0, 0, 0, 0},
10315 {0x18, 0, 0, 0, 0},
10316 {0x19, 0, 0, 0, 0},
10317 {0x1A, 0, 0, 0, 0},
10318 {0x1B, 0, 0, 0, 0},
10319 {0x1C, 0, 0, 0, 0},
10320 {0x1D, 0, 0, 0, 0},
10321 {0x1E, 0, 0, 0, 0},
10322 {0x1F, 0, 0, 0, 0},
10323 {0x20, 0x3, 0x3, 0, 0},
10324 {0x21, 0, 0, 0, 0},
10325 {0x22, 0, 0, 0, 0},
10326 {0x23, 0x90, 0x90, 0, 0},
10327 {0x24, 0x55, 0x55, 0, 0},
10328 {0x25, 0x15, 0x15, 0, 0},
10329 {0x26, 0x5, 0x5, 0, 0},
10330 {0x27, 0x15, 0x15, 0, 0},
10331 {0x28, 0x5, 0x5, 0, 0},
10332 {0x29, 0x20, 0x20, 0, 0},
10333 {0x2A, 0x11, 0x11, 0, 0},
10334 {0x2B, 0x90, 0x90, 0, 0},
10335 {0x2C, 0, 0, 0, 0},
10336 {0x2D, 0x88, 0x88, 0, 0},
10337 {0x2E, 0x32, 0x32, 0, 0},
10338 {0x2F, 0x77, 0x77, 0, 0},
10339 {0x30, 0x17, 0x17, 1, 1},
10340 {0x31, 0xff, 0xff, 1, 1},
10341 {0x32, 0x20, 0x20, 0, 0},
10342 {0x33, 0, 0, 0, 0},
10343 {0x34, 0x88, 0x88, 0, 0},
10344 {0x35, 0x32, 0x32, 0, 0},
10345 {0x36, 0x77, 0x77, 0, 0},
10346 {0x37, 0x17, 0x17, 1, 1},
10347 {0x38, 0xf0, 0xf0, 1, 1},
10348 {0x39, 0x20, 0x20, 0, 0},
10349 {0x3A, 0x8, 0x8, 0, 0},
10350 {0x3B, 0x55, 0x55, 1, 1},
10351 {0x3C, 0, 0, 0, 0},
10352 {0x3D, 0x88, 0x88, 1, 1},
10353 {0x3E, 0, 0, 0, 0},
10354 {0x3F, 0, 0, 1, 1},
10355 {0x40, 0x7, 0x7, 1, 1},
10356 {0x41, 0x6, 0x6, 0, 0},
10357 {0x42, 0x4, 0x4, 0, 0},
10358 {0x43, 0, 0, 0, 0},
10359 {0x44, 0x8, 0x8, 0, 0},
10360 {0x45, 0x55, 0x55, 1, 1},
10361 {0x46, 0, 0, 0, 0},
10362 {0x47, 0x11, 0x11, 0, 0},
10363 {0x48, 0, 0, 0, 0},
10364 {0x49, 0, 0, 1, 1},
10365 {0x4A, 0x7, 0x7, 0, 0},
10366 {0x4B, 0x6, 0x6, 0, 0},
10367 {0x4C, 0x4, 0x4, 0, 0},
10368 {0x4D, 0, 0, 0, 0},
10369 {0x4E, 0, 0, 0, 0},
10370 {0x4F, 0x26, 0x26, 1, 1},
10371 {0x50, 0x26, 0x26, 1, 1},
10372 {0x51, 0xf, 0xf, 1, 1},
10373 {0x52, 0xf, 0xf, 1, 1},
10374 {0x53, 0x44, 0x44, 0, 0},
10375 {0x54, 0, 0, 0, 0},
10376 {0x55, 0, 0, 0, 0},
10377 {0x56, 0x8, 0x8, 0, 0},
10378 {0x57, 0x8, 0x8, 0, 0},
10379 {0x58, 0x7, 0x7, 0, 0},
10380 {0x59, 0x22, 0x22, 0, 0},
10381 {0x5A, 0x22, 0x22, 0, 0},
10382 {0x5B, 0x2, 0x2, 0, 0},
10383 {0x5C, 0x4, 0x4, 1, 1},
10384 {0x5D, 0x7, 0x7, 0, 0},
10385 {0x5E, 0x55, 0x55, 0, 0},
10386 {0x5F, 0x23, 0x23, 0, 0},
10387 {0x60, 0x41, 0x41, 0, 0},
10388 {0x61, 0x1, 0x1, 0, 0},
10389 {0x62, 0xa, 0xa, 0, 0},
10390 {0x63, 0, 0, 0, 0},
10391 {0x64, 0, 0, 0, 0},
10392 {0x65, 0, 0, 0, 0},
10393 {0x66, 0, 0, 0, 0},
10394 {0x67, 0, 0, 0, 0},
10395 {0x68, 0, 0, 0, 0},
10396 {0x69, 0, 0, 0, 0},
10397 {0x6A, 0, 0, 0, 0},
10398 {0x6B, 0xc, 0xc, 0, 0},
10399 {0x6C, 0, 0, 0, 0},
10400 {0x6D, 0, 0, 0, 0},
10401 {0x6E, 0, 0, 0, 0},
10402 {0x6F, 0, 0, 0, 0},
10403 {0x70, 0, 0, 0, 0},
10404 {0x71, 0, 0, 0, 0},
10405 {0x72, 0x22, 0x22, 0, 0},
10406 {0x73, 0x22, 0x22, 0, 0},
10407 {0x74, 0, 0, 1, 1},
10408 {0x75, 0xa, 0xa, 0, 0},
10409 {0x76, 0x1, 0x1, 0, 0},
10410 {0x77, 0x22, 0x22, 0, 0},
10411 {0x78, 0x30, 0x30, 0, 0},
10412 {0x79, 0, 0, 0, 0},
10413 {0x7A, 0, 0, 0, 0},
10414 {0x7B, 0, 0, 0, 0},
10415 {0x7C, 0, 0, 0, 0},
10416 {0x7D, 0, 0, 0, 0},
10417 {0x7E, 0, 0, 0, 0},
10418 {0x7F, 0, 0, 0, 0},
10419 {0x80, 0, 0, 0, 0},
10420 {0x81, 0, 0, 0, 0},
10421 {0x82, 0, 0, 0, 0},
10422 {0x83, 0, 0, 0, 0},
10423 {0x84, 0, 0, 0, 0},
10424 {0x85, 0, 0, 0, 0},
10425 {0x86, 0, 0, 0, 0},
10426 {0x87, 0, 0, 0, 0},
10427 {0x88, 0, 0, 0, 0},
10428 {0x89, 0, 0, 0, 0},
10429 {0x8A, 0, 0, 0, 0},
10430 {0x8B, 0, 0, 0, 0},
10431 {0x8C, 0, 0, 0, 0},
10432 {0x8D, 0, 0, 0, 0},
10433 {0x8E, 0, 0, 0, 0},
10434 {0x8F, 0, 0, 0, 0},
10435 {0x90, 0, 0, 0, 0},
10436 {0x91, 0, 0, 0, 0},
10437 {0x92, 0, 0, 0, 0},
10438 {0x93, 0, 0, 0, 0},
10439 {0x94, 0, 0, 0, 0},
10440 {0xFFFF, 0, 0, 0, 0},
10441};
10442
10443static struct radio_regs regs_SYN_2056_rev8[] = {
10444 {0x02, 0, 0, 0, 0},
10445 {0x03, 0, 0, 0, 0},
10446 {0x04, 0, 0, 0, 0},
10447 {0x05, 0, 0, 0, 0},
10448 {0x06, 0, 0, 0, 0},
10449 {0x07, 0, 0, 0, 0},
10450 {0x08, 0, 0, 0, 0},
10451 {0x09, 0x1, 0x1, 0, 0},
10452 {0x0A, 0, 0, 0, 0},
10453 {0x0B, 0, 0, 0, 0},
10454 {0x0C, 0, 0, 0, 0},
10455 {0x0D, 0, 0, 0, 0},
10456 {0x0E, 0, 0, 0, 0},
10457 {0x0F, 0, 0, 0, 0},
10458 {0x10, 0, 0, 0, 0},
10459 {0x11, 0, 0, 0, 0},
10460 {0x12, 0, 0, 0, 0},
10461 {0x13, 0, 0, 0, 0},
10462 {0x14, 0, 0, 0, 0},
10463 {0x15, 0, 0, 0, 0},
10464 {0x16, 0, 0, 0, 0},
10465 {0x17, 0, 0, 0, 0},
10466 {0x18, 0, 0, 0, 0},
10467 {0x19, 0, 0, 0, 0},
10468 {0x1A, 0, 0, 0, 0},
10469 {0x1B, 0, 0, 0, 0},
10470 {0x1C, 0, 0, 0, 0},
10471 {0x1D, 0, 0, 0, 0},
10472 {0x1E, 0, 0, 0, 0},
10473 {0x1F, 0, 0, 0, 0},
10474 {0x20, 0, 0, 0, 0},
10475 {0x21, 0, 0, 0, 0},
10476 {0x22, 0x60, 0x60, 0, 0},
10477 {0x23, 0x6, 0x6, 0, 0},
10478 {0x24, 0xc, 0xc, 0, 0},
10479 {0x25, 0, 0, 0, 0},
10480 {0x26, 0, 0, 0, 0},
10481 {0x27, 0, 0, 0, 0},
10482 {0x28, 0x1, 0x1, 0, 0},
10483 {0x29, 0, 0, 0, 0},
10484 {0x2A, 0, 0, 0, 0},
10485 {0x2B, 0, 0, 0, 0},
10486 {0x2C, 0, 0, 0, 0},
10487 {0x2D, 0, 0, 0, 0},
10488 {0x2E, 0, 0, 0, 0},
10489 {0x2F, 0x1f, 0x1f, 0, 0},
10490 {0x30, 0x15, 0x15, 0, 0},
10491 {0x31, 0xf, 0xf, 0, 0},
10492 {0x32, 0, 0, 0, 0},
10493 {0x33, 0, 0, 0, 0},
10494 {0x34, 0, 0, 0, 0},
10495 {0x35, 0, 0, 0, 0},
10496 {0x36, 0, 0, 0, 0},
10497 {0x37, 0, 0, 0, 0},
10498 {0x38, 0, 0, 0, 0},
10499 {0x39, 0, 0, 0, 0},
10500 {0x3A, 0, 0, 0, 0},
10501 {0x3B, 0, 0, 0, 0},
10502 {0x3C, 0x13, 0x13, 0, 0},
10503 {0x3D, 0xf, 0xf, 0, 0},
10504 {0x3E, 0x18, 0x18, 0, 0},
10505 {0x3F, 0, 0, 0, 0},
10506 {0x40, 0, 0, 0, 0},
10507 {0x41, 0x20, 0x20, 0, 0},
10508 {0x42, 0x20, 0x20, 0, 0},
10509 {0x43, 0, 0, 0, 0},
10510 {0x44, 0x77, 0x77, 0, 0},
10511 {0x45, 0x7, 0x7, 0, 0},
10512 {0x46, 0x1, 0x1, 0, 0},
10513 {0x47, 0x4, 0x4, 0, 0},
10514 {0x48, 0xf, 0xf, 0, 0},
10515 {0x49, 0x30, 0x30, 0, 0},
10516 {0x4A, 0x32, 0x32, 0, 0},
10517 {0x4B, 0xd, 0xd, 0, 0},
10518 {0x4C, 0xd, 0xd, 0, 0},
10519 {0x4D, 0x4, 0x4, 0, 0},
10520 {0x4E, 0x6, 0x6, 0, 0},
10521 {0x4F, 0x1, 0x1, 0, 0},
10522 {0x50, 0x1c, 0x1c, 0, 0},
10523 {0x51, 0x2, 0x2, 0, 0},
10524 {0x52, 0x2, 0x2, 0, 0},
10525 {0x53, 0xf7, 0xf7, 1, 1},
10526 {0x54, 0xb4, 0xb4, 0, 0},
10527 {0x55, 0xd2, 0xd2, 0, 0},
10528 {0x56, 0, 0, 0, 0},
10529 {0x57, 0, 0, 0, 0},
10530 {0x58, 0x4, 0x4, 0, 0},
10531 {0x59, 0x96, 0x96, 0, 0},
10532 {0x5A, 0x3e, 0x3e, 0, 0},
10533 {0x5B, 0x3e, 0x3e, 0, 0},
10534 {0x5C, 0x13, 0x13, 0, 0},
10535 {0x5D, 0x2, 0x2, 0, 0},
10536 {0x5E, 0, 0, 0, 0},
10537 {0x5F, 0x7, 0x7, 0, 0},
10538 {0x60, 0x7, 0x7, 1, 1},
10539 {0x61, 0x8, 0x8, 0, 0},
10540 {0x62, 0x3, 0x3, 0, 0},
10541 {0x63, 0, 0, 0, 0},
10542 {0x64, 0, 0, 0, 0},
10543 {0x65, 0, 0, 0, 0},
10544 {0x66, 0, 0, 0, 0},
10545 {0x67, 0, 0, 0, 0},
10546 {0x68, 0x40, 0x40, 0, 0},
10547 {0x69, 0, 0, 0, 0},
10548 {0x6A, 0, 0, 0, 0},
10549 {0x6B, 0, 0, 0, 0},
10550 {0x6C, 0, 0, 0, 0},
10551 {0x6D, 0x1, 0x1, 0, 0},
10552 {0x6E, 0, 0, 0, 0},
10553 {0x6F, 0, 0, 0, 0},
10554 {0x70, 0x60, 0x60, 0, 0},
10555 {0x71, 0x66, 0x66, 0, 0},
10556 {0x72, 0xc, 0xc, 0, 0},
10557 {0x73, 0x66, 0x66, 0, 0},
10558 {0x74, 0x8f, 0x8f, 1, 1},
10559 {0x75, 0, 0, 0, 0},
10560 {0x76, 0xcc, 0xcc, 0, 0},
10561 {0x77, 0x1, 0x1, 0, 0},
10562 {0x78, 0x66, 0x66, 0, 0},
10563 {0x79, 0x66, 0x66, 0, 0},
10564 {0x7A, 0, 0, 0, 0},
10565 {0x7B, 0, 0, 0, 0},
10566 {0x7C, 0, 0, 0, 0},
10567 {0x7D, 0, 0, 0, 0},
10568 {0x7E, 0, 0, 0, 0},
10569 {0x7F, 0, 0, 0, 0},
10570 {0x80, 0, 0, 0, 0},
10571 {0x81, 0, 0, 0, 0},
10572 {0x82, 0, 0, 0, 0},
10573 {0x83, 0, 0, 0, 0},
10574 {0x84, 0, 0, 0, 0},
10575 {0x85, 0xff, 0xff, 0, 0},
10576 {0x86, 0, 0, 0, 0},
10577 {0x87, 0, 0, 0, 0},
10578 {0x88, 0, 0, 0, 0},
10579 {0x89, 0, 0, 0, 0},
10580 {0x8A, 0, 0, 0, 0},
10581 {0x8B, 0, 0, 0, 0},
10582 {0x8C, 0, 0, 0, 0},
10583 {0x8D, 0, 0, 0, 0},
10584 {0x8E, 0, 0, 0, 0},
10585 {0x8F, 0, 0, 0, 0},
10586 {0x90, 0, 0, 0, 0},
10587 {0x91, 0, 0, 0, 0},
10588 {0x92, 0, 0, 0, 0},
10589 {0x93, 0, 0, 0, 0},
10590 {0x94, 0, 0, 0, 0},
10591 {0x95, 0, 0, 0, 0},
10592 {0x96, 0, 0, 0, 0},
10593 {0x97, 0, 0, 0, 0},
10594 {0x98, 0, 0, 0, 0},
10595 {0x99, 0, 0, 0, 0},
10596 {0x9A, 0, 0, 0, 0},
10597 {0x9B, 0, 0, 0, 0},
10598 {0x9C, 0, 0, 0, 0},
10599 {0x9D, 0, 0, 0, 0},
10600 {0x9E, 0, 0, 0, 0},
10601 {0x9F, 0x6, 0x6, 0, 0},
10602 {0xA0, 0x66, 0x66, 0, 0},
10603 {0xA1, 0x66, 0x66, 0, 0},
10604 {0xA2, 0x66, 0x66, 0, 0},
10605 {0xA3, 0x66, 0x66, 0, 0},
10606 {0xA4, 0x66, 0x66, 0, 0},
10607 {0xA5, 0x66, 0x66, 0, 0},
10608 {0xA6, 0x66, 0x66, 0, 0},
10609 {0xA7, 0x66, 0x66, 0, 0},
10610 {0xA8, 0x66, 0x66, 0, 0},
10611 {0xA9, 0x66, 0x66, 0, 0},
10612 {0xAA, 0x66, 0x66, 0, 0},
10613 {0xAB, 0x66, 0x66, 0, 0},
10614 {0xAC, 0x66, 0x66, 0, 0},
10615 {0xAD, 0x66, 0x66, 0, 0},
10616 {0xAE, 0x66, 0x66, 0, 0},
10617 {0xAF, 0x66, 0x66, 0, 0},
10618 {0xB0, 0x66, 0x66, 0, 0},
10619 {0xB1, 0x66, 0x66, 0, 0},
10620 {0xB2, 0x66, 0x66, 0, 0},
10621 {0xB3, 0xa, 0xa, 0, 0},
10622 {0xB4, 0, 0, 0, 0},
10623 {0xB5, 0, 0, 0, 0},
10624 {0xB6, 0, 0, 0, 0},
10625 {0xFFFF, 0, 0, 0, 0},
10626};
10627
10628static struct radio_regs regs_TX_2056_rev8[] = {
10629 {0x02, 0, 0, 0, 0},
10630 {0x03, 0, 0, 0, 0},
10631 {0x04, 0, 0, 0, 0},
10632 {0x05, 0, 0, 0, 0},
10633 {0x06, 0, 0, 0, 0},
10634 {0x07, 0, 0, 0, 0},
10635 {0x08, 0, 0, 0, 0},
10636 {0x09, 0, 0, 0, 0},
10637 {0x0A, 0, 0, 0, 0},
10638 {0x0B, 0, 0, 0, 0},
10639 {0x0C, 0, 0, 0, 0},
10640 {0x0D, 0, 0, 0, 0},
10641 {0x0E, 0, 0, 0, 0},
10642 {0x0F, 0, 0, 0, 0},
10643 {0x10, 0, 0, 0, 0},
10644 {0x11, 0, 0, 0, 0},
10645 {0x12, 0, 0, 0, 0},
10646 {0x13, 0, 0, 0, 0},
10647 {0x14, 0, 0, 0, 0},
10648 {0x15, 0, 0, 0, 0},
10649 {0x16, 0, 0, 0, 0},
10650 {0x17, 0, 0, 0, 0},
10651 {0x18, 0, 0, 0, 0},
10652 {0x19, 0, 0, 0, 0},
10653 {0x1A, 0, 0, 0, 0},
10654 {0x1B, 0, 0, 0, 0},
10655 {0x1C, 0, 0, 0, 0},
10656 {0x1D, 0, 0, 0, 0},
10657 {0x1E, 0, 0, 0, 0},
10658 {0x1F, 0, 0, 0, 0},
10659 {0x20, 0, 0, 0, 0},
10660 {0x21, 0x88, 0x88, 0, 0},
10661 {0x22, 0x88, 0x88, 0, 0},
10662 {0x23, 0x88, 0x88, 0, 0},
10663 {0x24, 0x88, 0x88, 0, 0},
10664 {0x25, 0xc, 0xc, 0, 0},
10665 {0x26, 0, 0, 0, 0},
10666 {0x27, 0x3, 0x3, 0, 0},
10667 {0x28, 0, 0, 0, 0},
10668 {0x29, 0x3, 0x3, 0, 0},
10669 {0x2A, 0x37, 0x37, 0, 0},
10670 {0x2B, 0x3, 0x3, 0, 0},
10671 {0x2C, 0, 0, 0, 0},
10672 {0x2D, 0, 0, 0, 0},
10673 {0x2E, 0x1, 0x1, 0, 0},
10674 {0x2F, 0x1, 0x1, 0, 0},
10675 {0x30, 0, 0, 0, 0},
10676 {0x31, 0, 0, 0, 0},
10677 {0x32, 0, 0, 0, 0},
10678 {0x33, 0x11, 0x11, 0, 0},
10679 {0x34, 0xee, 0xee, 1, 1},
10680 {0x35, 0, 0, 0, 0},
10681 {0x36, 0, 0, 0, 0},
10682 {0x37, 0x3, 0x3, 0, 0},
10683 {0x38, 0x50, 0x50, 1, 1},
10684 {0x39, 0, 0, 0, 0},
10685 {0x3A, 0x50, 0x50, 1, 1},
10686 {0x3B, 0, 0, 0, 0},
10687 {0x3C, 0x6e, 0x6e, 0, 0},
10688 {0x3D, 0xf0, 0xf0, 1, 1},
10689 {0x3E, 0, 0, 0, 0},
10690 {0x3F, 0, 0, 0, 0},
10691 {0x40, 0, 0, 0, 0},
10692 {0x41, 0x3, 0x3, 0, 0},
10693 {0x42, 0x3, 0x3, 0, 0},
10694 {0x43, 0, 0, 0, 0},
10695 {0x44, 0x1e, 0x1e, 0, 0},
10696 {0x45, 0, 0, 0, 0},
10697 {0x46, 0x6e, 0x6e, 0, 0},
10698 {0x47, 0xf0, 0xf0, 1, 1},
10699 {0x48, 0, 0, 0, 0},
10700 {0x49, 0x2, 0x2, 0, 0},
10701 {0x4A, 0xff, 0xff, 1, 1},
10702 {0x4B, 0xc, 0xc, 0, 0},
10703 {0x4C, 0, 0, 0, 0},
10704 {0x4D, 0x38, 0x38, 0, 0},
10705 {0x4E, 0x70, 0x70, 1, 1},
10706 {0x4F, 0x2, 0x2, 0, 0},
10707 {0x50, 0x88, 0x88, 0, 0},
10708 {0x51, 0xc, 0xc, 0, 0},
10709 {0x52, 0, 0, 0, 0},
10710 {0x53, 0x8, 0x8, 0, 0},
10711 {0x54, 0x70, 0x70, 1, 1},
10712 {0x55, 0x2, 0x2, 0, 0},
10713 {0x56, 0xff, 0xff, 1, 1},
10714 {0x57, 0, 0, 0, 0},
10715 {0x58, 0x83, 0x83, 0, 0},
10716 {0x59, 0x77, 0x77, 1, 1},
10717 {0x5A, 0, 0, 0, 0},
10718 {0x5B, 0x2, 0x2, 0, 0},
10719 {0x5C, 0x88, 0x88, 0, 0},
10720 {0x5D, 0, 0, 0, 0},
10721 {0x5E, 0x8, 0x8, 0, 0},
10722 {0x5F, 0x77, 0x77, 1, 1},
10723 {0x60, 0x1, 0x1, 0, 0},
10724 {0x61, 0, 0, 0, 0},
10725 {0x62, 0x7, 0x7, 0, 0},
10726 {0x63, 0, 0, 0, 0},
10727 {0x64, 0x7, 0x7, 0, 0},
10728 {0x65, 0, 0, 0, 0},
10729 {0x66, 0, 0, 0, 0},
10730 {0x67, 0, 0, 1, 1},
10731 {0x68, 0, 0, 0, 0},
10732 {0x69, 0xa, 0xa, 0, 0},
10733 {0x6A, 0, 0, 0, 0},
10734 {0x6B, 0, 0, 0, 0},
10735 {0x6C, 0, 0, 0, 0},
10736 {0x6D, 0, 0, 0, 0},
10737 {0x6E, 0, 0, 0, 0},
10738 {0x6F, 0, 0, 0, 0},
10739 {0x70, 0, 0, 0, 0},
10740 {0x71, 0x2, 0x2, 0, 0},
10741 {0x72, 0, 0, 0, 0},
10742 {0x73, 0, 0, 0, 0},
10743 {0x74, 0xe, 0xe, 0, 0},
10744 {0x75, 0xe, 0xe, 0, 0},
10745 {0x76, 0xe, 0xe, 0, 0},
10746 {0x77, 0x13, 0x13, 0, 0},
10747 {0x78, 0x13, 0x13, 0, 0},
10748 {0x79, 0x1b, 0x1b, 0, 0},
10749 {0x7A, 0x1b, 0x1b, 0, 0},
10750 {0x7B, 0x55, 0x55, 0, 0},
10751 {0x7C, 0x5b, 0x5b, 0, 0},
10752 {0x7D, 0x30, 0x30, 1, 1},
10753 {0x7E, 0, 0, 0, 0},
10754 {0x7F, 0, 0, 0, 0},
10755 {0x80, 0, 0, 0, 0},
10756 {0x81, 0, 0, 0, 0},
10757 {0x82, 0, 0, 0, 0},
10758 {0x83, 0, 0, 0, 0},
10759 {0x84, 0, 0, 0, 0},
10760 {0x85, 0, 0, 0, 0},
10761 {0x86, 0, 0, 0, 0},
10762 {0x87, 0, 0, 0, 0},
10763 {0x88, 0, 0, 0, 0},
10764 {0x89, 0, 0, 0, 0},
10765 {0x8A, 0, 0, 0, 0},
10766 {0x8B, 0, 0, 0, 0},
10767 {0x8C, 0, 0, 0, 0},
10768 {0x8D, 0, 0, 0, 0},
10769 {0x8E, 0, 0, 0, 0},
10770 {0x8F, 0, 0, 0, 0},
10771 {0x90, 0, 0, 0, 0},
10772 {0x91, 0, 0, 0, 0},
10773 {0x92, 0, 0, 0, 0},
10774 {0x93, 0x70, 0x70, 0, 0},
10775 {0x94, 0x70, 0x70, 0, 0},
10776 {0x95, 0x70, 0x70, 0, 0},
10777 {0x96, 0x70, 0x70, 0, 0},
10778 {0x97, 0x70, 0x70, 0, 0},
10779 {0x98, 0x70, 0x70, 0, 0},
10780 {0x99, 0x70, 0x70, 0, 0},
10781 {0x9A, 0x70, 0x70, 0, 0},
10782 {0xFFFF, 0, 0, 0, 0},
10783};
10784
10785static struct radio_regs regs_RX_2056_rev8[] = {
10786 {0x02, 0, 0, 0, 0},
10787 {0x03, 0, 0, 0, 0},
10788 {0x04, 0, 0, 0, 0},
10789 {0x05, 0, 0, 0, 0},
10790 {0x06, 0, 0, 0, 0},
10791 {0x07, 0, 0, 0, 0},
10792 {0x08, 0, 0, 0, 0},
10793 {0x09, 0, 0, 0, 0},
10794 {0x0A, 0, 0, 0, 0},
10795 {0x0B, 0, 0, 0, 0},
10796 {0x0C, 0, 0, 0, 0},
10797 {0x0D, 0, 0, 0, 0},
10798 {0x0E, 0, 0, 0, 0},
10799 {0x0F, 0, 0, 0, 0},
10800 {0x10, 0, 0, 0, 0},
10801 {0x11, 0, 0, 0, 0},
10802 {0x12, 0, 0, 0, 0},
10803 {0x13, 0, 0, 0, 0},
10804 {0x14, 0, 0, 0, 0},
10805 {0x15, 0, 0, 0, 0},
10806 {0x16, 0, 0, 0, 0},
10807 {0x17, 0, 0, 0, 0},
10808 {0x18, 0, 0, 0, 0},
10809 {0x19, 0, 0, 0, 0},
10810 {0x1A, 0, 0, 0, 0},
10811 {0x1B, 0, 0, 0, 0},
10812 {0x1C, 0, 0, 0, 0},
10813 {0x1D, 0, 0, 0, 0},
10814 {0x1E, 0, 0, 0, 0},
10815 {0x1F, 0, 0, 0, 0},
10816 {0x20, 0x3, 0x3, 0, 0},
10817 {0x21, 0, 0, 0, 0},
10818 {0x22, 0, 0, 0, 0},
10819 {0x23, 0x90, 0x90, 0, 0},
10820 {0x24, 0x55, 0x55, 0, 0},
10821 {0x25, 0x15, 0x15, 0, 0},
10822 {0x26, 0x5, 0x5, 0, 0},
10823 {0x27, 0x15, 0x15, 0, 0},
10824 {0x28, 0x5, 0x5, 0, 0},
10825 {0x29, 0x20, 0x20, 0, 0},
10826 {0x2A, 0x11, 0x11, 0, 0},
10827 {0x2B, 0x90, 0x90, 0, 0},
10828 {0x2C, 0, 0, 0, 0},
10829 {0x2D, 0x88, 0x88, 0, 0},
10830 {0x2E, 0x32, 0x32, 0, 0},
10831 {0x2F, 0x77, 0x77, 0, 0},
10832 {0x30, 0x17, 0x17, 1, 1},
10833 {0x31, 0xff, 0xff, 1, 1},
10834 {0x32, 0x20, 0x20, 0, 0},
10835 {0x33, 0, 0, 0, 0},
10836 {0x34, 0x88, 0x88, 0, 0},
10837 {0x35, 0x32, 0x32, 0, 0},
10838 {0x36, 0x77, 0x77, 0, 0},
10839 {0x37, 0x17, 0x17, 1, 1},
10840 {0x38, 0xf0, 0xf0, 1, 1},
10841 {0x39, 0x20, 0x20, 0, 0},
10842 {0x3A, 0x8, 0x8, 0, 0},
10843 {0x3B, 0x55, 0x55, 1, 1},
10844 {0x3C, 0, 0, 0, 0},
10845 {0x3D, 0x88, 0x88, 1, 1},
10846 {0x3E, 0, 0, 0, 0},
10847 {0x3F, 0x44, 0x44, 0, 0},
10848 {0x40, 0x7, 0x7, 1, 1},
10849 {0x41, 0x6, 0x6, 0, 0},
10850 {0x42, 0x4, 0x4, 0, 0},
10851 {0x43, 0, 0, 0, 0},
10852 {0x44, 0x8, 0x8, 0, 0},
10853 {0x45, 0x55, 0x55, 1, 1},
10854 {0x46, 0, 0, 0, 0},
10855 {0x47, 0x11, 0x11, 0, 0},
10856 {0x48, 0, 0, 0, 0},
10857 {0x49, 0x44, 0x44, 0, 0},
10858 {0x4A, 0x7, 0x7, 0, 0},
10859 {0x4B, 0x6, 0x6, 0, 0},
10860 {0x4C, 0x4, 0x4, 0, 0},
10861 {0x4D, 0, 0, 0, 0},
10862 {0x4E, 0, 0, 0, 0},
10863 {0x4F, 0x26, 0x26, 1, 1},
10864 {0x50, 0x26, 0x26, 1, 1},
10865 {0x51, 0xf, 0xf, 1, 1},
10866 {0x52, 0xf, 0xf, 1, 1},
10867 {0x53, 0x44, 0x44, 0, 0},
10868 {0x54, 0, 0, 0, 0},
10869 {0x55, 0, 0, 0, 0},
10870 {0x56, 0x8, 0x8, 0, 0},
10871 {0x57, 0x8, 0x8, 0, 0},
10872 {0x58, 0x7, 0x7, 0, 0},
10873 {0x59, 0x22, 0x22, 0, 0},
10874 {0x5A, 0x22, 0x22, 0, 0},
10875 {0x5B, 0x2, 0x2, 0, 0},
10876 {0x5C, 0x4, 0x4, 1, 1},
10877 {0x5D, 0x7, 0x7, 0, 0},
10878 {0x5E, 0x55, 0x55, 0, 0},
10879 {0x5F, 0x23, 0x23, 0, 0},
10880 {0x60, 0x41, 0x41, 0, 0},
10881 {0x61, 0x1, 0x1, 0, 0},
10882 {0x62, 0xa, 0xa, 0, 0},
10883 {0x63, 0, 0, 0, 0},
10884 {0x64, 0, 0, 0, 0},
10885 {0x65, 0, 0, 0, 0},
10886 {0x66, 0, 0, 0, 0},
10887 {0x67, 0, 0, 0, 0},
10888 {0x68, 0, 0, 0, 0},
10889 {0x69, 0, 0, 0, 0},
10890 {0x6A, 0, 0, 0, 0},
10891 {0x6B, 0xc, 0xc, 0, 0},
10892 {0x6C, 0, 0, 0, 0},
10893 {0x6D, 0, 0, 0, 0},
10894 {0x6E, 0, 0, 0, 0},
10895 {0x6F, 0, 0, 0, 0},
10896 {0x70, 0, 0, 0, 0},
10897 {0x71, 0, 0, 0, 0},
10898 {0x72, 0x22, 0x22, 0, 0},
10899 {0x73, 0x22, 0x22, 0, 0},
10900 {0x74, 0, 0, 1, 1},
10901 {0x75, 0xa, 0xa, 0, 0},
10902 {0x76, 0x1, 0x1, 0, 0},
10903 {0x77, 0x22, 0x22, 0, 0},
10904 {0x78, 0x30, 0x30, 0, 0},
10905 {0x79, 0, 0, 0, 0},
10906 {0x7A, 0, 0, 0, 0},
10907 {0x7B, 0, 0, 0, 0},
10908 {0x7C, 0, 0, 0, 0},
10909 {0x7D, 0x5, 0x5, 1, 1},
10910 {0x7E, 0, 0, 0, 0},
10911 {0x7F, 0, 0, 0, 0},
10912 {0x80, 0, 0, 0, 0},
10913 {0x81, 0, 0, 0, 0},
10914 {0x82, 0, 0, 0, 0},
10915 {0x83, 0, 0, 0, 0},
10916 {0x84, 0, 0, 0, 0},
10917 {0x85, 0, 0, 0, 0},
10918 {0x86, 0, 0, 0, 0},
10919 {0x87, 0, 0, 0, 0},
10920 {0x88, 0, 0, 0, 0},
10921 {0x89, 0, 0, 0, 0},
10922 {0x8A, 0, 0, 0, 0},
10923 {0x8B, 0, 0, 0, 0},
10924 {0x8C, 0, 0, 0, 0},
10925 {0x8D, 0, 0, 0, 0},
10926 {0x8E, 0, 0, 0, 0},
10927 {0x8F, 0, 0, 0, 0},
10928 {0x90, 0, 0, 0, 0},
10929 {0x91, 0, 0, 0, 0},
10930 {0x92, 0, 0, 0, 0},
10931 {0x93, 0, 0, 0, 0},
10932 {0x94, 0, 0, 0, 0},
10933 {0xFFFF, 0, 0, 0, 0},
10934};
10935
10936static const struct radio_regs regs_SYN_2056_rev11[] = {
10937 {0x02, 0, 0, 0, 0},
10938 {0x03, 0, 0, 0, 0},
10939 {0x04, 0, 0, 0, 0},
10940 {0x05, 0, 0, 0, 0},
10941 {0x06, 0, 0, 0, 0},
10942 {0x07, 0, 0, 0, 0},
10943 {0x08, 0, 0, 0, 0},
10944 {0x09, 0x1, 0x1, 0, 0},
10945 {0x0A, 0, 0, 0, 0},
10946 {0x0B, 0, 0, 0, 0},
10947 {0x0C, 0, 0, 0, 0},
10948 {0x0D, 0, 0, 0, 0},
10949 {0x0E, 0, 0, 0, 0},
10950 {0x0F, 0, 0, 0, 0},
10951 {0x10, 0, 0, 0, 0},
10952 {0x11, 0, 0, 0, 0},
10953 {0x12, 0, 0, 0, 0},
10954 {0x13, 0, 0, 0, 0},
10955 {0x14, 0, 0, 0, 0},
10956 {0x15, 0, 0, 0, 0},
10957 {0x16, 0, 0, 0, 0},
10958 {0x17, 0, 0, 0, 0},
10959 {0x18, 0, 0, 0, 0},
10960 {0x19, 0, 0, 0, 0},
10961 {0x1A, 0, 0, 0, 0},
10962 {0x1B, 0, 0, 0, 0},
10963 {0x1C, 0, 0, 0, 0},
10964 {0x1D, 0, 0, 0, 0},
10965 {0x1E, 0, 0, 0, 0},
10966 {0x1F, 0, 0, 0, 0},
10967 {0x20, 0, 0, 0, 0},
10968 {0x21, 0, 0, 0, 0},
10969 {0x22, 0x60, 0x60, 0, 0},
10970 {0x23, 0x6, 0x6, 0, 0},
10971 {0x24, 0xc, 0xc, 0, 0},
10972 {0x25, 0, 0, 0, 0},
10973 {0x26, 0, 0, 0, 0},
10974 {0x27, 0, 0, 0, 0},
10975 {0x28, 0x1, 0x1, 0, 0},
10976 {0x29, 0, 0, 0, 0},
10977 {0x2A, 0, 0, 0, 0},
10978 {0x2B, 0, 0, 0, 0},
10979 {0x2C, 0, 0, 0, 0},
10980 {0x2D, 0, 0, 0, 0},
10981 {0x2E, 0, 0, 0, 0},
10982 {0x2F, 0x1f, 0x1f, 0, 0},
10983 {0x30, 0x15, 0x15, 0, 0},
10984 {0x31, 0xf, 0xf, 0, 0},
10985 {0x32, 0, 0, 0, 0},
10986 {0x33, 0, 0, 0, 0},
10987 {0x34, 0, 0, 0, 0},
10988 {0x35, 0, 0, 0, 0},
10989 {0x36, 0, 0, 0, 0},
10990 {0x37, 0, 0, 0, 0},
10991 {0x38, 0, 0, 0, 0},
10992 {0x39, 0, 0, 0, 0},
10993 {0x3A, 0, 0, 0, 0},
10994 {0x3B, 0, 0, 0, 0},
10995 {0x3C, 0x13, 0x13, 0, 0},
10996 {0x3D, 0xf, 0xf, 0, 0},
10997 {0x3E, 0x18, 0x18, 0, 0},
10998 {0x3F, 0, 0, 0, 0},
10999 {0x40, 0, 0, 0, 0},
11000 {0x41, 0x20, 0x20, 0, 0},
11001 {0x42, 0x20, 0x20, 0, 0},
11002 {0x43, 0, 0, 0, 0},
11003 {0x44, 0x77, 0x77, 0, 0},
11004 {0x45, 0x7, 0x7, 0, 0},
11005 {0x46, 0x1, 0x1, 0, 0},
11006 {0x47, 0x6, 0x6, 1, 1},
11007 {0x48, 0xf, 0xf, 0, 0},
11008 {0x49, 0x3f, 0x3f, 1, 1},
11009 {0x4A, 0x32, 0x32, 0, 0},
11010 {0x4B, 0x6, 0x6, 1, 1},
11011 {0x4C, 0x6, 0x6, 1, 1},
11012 {0x4D, 0x4, 0x4, 0, 0},
11013 {0x4E, 0x2b, 0x2b, 1, 1},
11014 {0x4F, 0x1, 0x1, 0, 0},
11015 {0x50, 0x1c, 0x1c, 0, 0},
11016 {0x51, 0x2, 0x2, 0, 0},
11017 {0x52, 0x2, 0x2, 0, 0},
11018 {0x53, 0xf7, 0xf7, 1, 1},
11019 {0x54, 0xb4, 0xb4, 0, 0},
11020 {0x55, 0xd2, 0xd2, 0, 0},
11021 {0x56, 0, 0, 0, 0},
11022 {0x57, 0, 0, 0, 0},
11023 {0x58, 0x4, 0x4, 0, 0},
11024 {0x59, 0x96, 0x96, 0, 0},
11025 {0x5A, 0x3e, 0x3e, 0, 0},
11026 {0x5B, 0x3e, 0x3e, 0, 0},
11027 {0x5C, 0x13, 0x13, 0, 0},
11028 {0x5D, 0x2, 0x2, 0, 0},
11029 {0x5E, 0, 0, 0, 0},
11030 {0x5F, 0x7, 0x7, 0, 0},
11031 {0x60, 0x7, 0x7, 1, 1},
11032 {0x61, 0x8, 0x8, 0, 0},
11033 {0x62, 0x3, 0x3, 0, 0},
11034 {0x63, 0, 0, 0, 0},
11035 {0x64, 0, 0, 0, 0},
11036 {0x65, 0, 0, 0, 0},
11037 {0x66, 0, 0, 0, 0},
11038 {0x67, 0, 0, 0, 0},
11039 {0x68, 0x40, 0x40, 0, 0},
11040 {0x69, 0, 0, 0, 0},
11041 {0x6A, 0, 0, 0, 0},
11042 {0x6B, 0, 0, 0, 0},
11043 {0x6C, 0, 0, 0, 0},
11044 {0x6D, 0x1, 0x1, 0, 0},
11045 {0x6E, 0, 0, 0, 0},
11046 {0x6F, 0, 0, 0, 0},
11047 {0x70, 0x60, 0x60, 0, 0},
11048 {0x71, 0x66, 0x66, 0, 0},
11049 {0x72, 0xc, 0xc, 0, 0},
11050 {0x73, 0x66, 0x66, 0, 0},
11051 {0x74, 0x8f, 0x8f, 1, 1},
11052 {0x75, 0, 0, 0, 0},
11053 {0x76, 0xcc, 0xcc, 0, 0},
11054 {0x77, 0x1, 0x1, 0, 0},
11055 {0x78, 0x66, 0x66, 0, 0},
11056 {0x79, 0x66, 0x66, 0, 0},
11057 {0x7A, 0, 0, 0, 0},
11058 {0x7B, 0, 0, 0, 0},
11059 {0x7C, 0, 0, 0, 0},
11060 {0x7D, 0, 0, 0, 0},
11061 {0x7E, 0, 0, 0, 0},
11062 {0x7F, 0, 0, 0, 0},
11063 {0x80, 0, 0, 0, 0},
11064 {0x81, 0, 0, 0, 0},
11065 {0x82, 0, 0, 0, 0},
11066 {0x83, 0, 0, 0, 0},
11067 {0x84, 0, 0, 0, 0},
11068 {0x85, 0xff, 0xff, 0, 0},
11069 {0x86, 0, 0, 0, 0},
11070 {0x87, 0, 0, 0, 0},
11071 {0x88, 0, 0, 0, 0},
11072 {0x89, 0, 0, 0, 0},
11073 {0x8A, 0, 0, 0, 0},
11074 {0x8B, 0, 0, 0, 0},
11075 {0x8C, 0, 0, 0, 0},
11076 {0x8D, 0, 0, 0, 0},
11077 {0x8E, 0, 0, 0, 0},
11078 {0x8F, 0, 0, 0, 0},
11079 {0x90, 0, 0, 0, 0},
11080 {0x91, 0, 0, 0, 0},
11081 {0x92, 0, 0, 0, 0},
11082 {0x93, 0, 0, 0, 0},
11083 {0x94, 0, 0, 0, 0},
11084 {0x95, 0, 0, 0, 0},
11085 {0x96, 0, 0, 0, 0},
11086 {0x97, 0, 0, 0, 0},
11087 {0x98, 0, 0, 0, 0},
11088 {0x99, 0, 0, 0, 0},
11089 {0x9A, 0, 0, 0, 0},
11090 {0x9B, 0, 0, 0, 0},
11091 {0x9C, 0, 0, 0, 0},
11092 {0x9D, 0, 0, 0, 0},
11093 {0x9E, 0, 0, 0, 0},
11094 {0x9F, 0x6, 0x6, 0, 0},
11095 {0xA0, 0x66, 0x66, 0, 0},
11096 {0xA1, 0x66, 0x66, 0, 0},
11097 {0xA2, 0x66, 0x66, 0, 0},
11098 {0xA3, 0x66, 0x66, 0, 0},
11099 {0xA4, 0x66, 0x66, 0, 0},
11100 {0xA5, 0x66, 0x66, 0, 0},
11101 {0xA6, 0x66, 0x66, 0, 0},
11102 {0xA7, 0x66, 0x66, 0, 0},
11103 {0xA8, 0x66, 0x66, 0, 0},
11104 {0xA9, 0x66, 0x66, 0, 0},
11105 {0xAA, 0x66, 0x66, 0, 0},
11106 {0xAB, 0x66, 0x66, 0, 0},
11107 {0xAC, 0x66, 0x66, 0, 0},
11108 {0xAD, 0x66, 0x66, 0, 0},
11109 {0xAE, 0x66, 0x66, 0, 0},
11110 {0xAF, 0x66, 0x66, 0, 0},
11111 {0xB0, 0x66, 0x66, 0, 0},
11112 {0xB1, 0x66, 0x66, 0, 0},
11113 {0xB2, 0x66, 0x66, 0, 0},
11114 {0xB3, 0xa, 0xa, 0, 0},
11115 {0xB4, 0, 0, 0, 0},
11116 {0xB5, 0, 0, 0, 0},
11117 {0xB6, 0, 0, 0, 0},
11118 {0xFFFF, 0, 0, 0, 0},
11119};
11120
11121static const struct radio_regs regs_TX_2056_rev11[] = {
11122 {0x02, 0, 0, 0, 0},
11123 {0x03, 0, 0, 0, 0},
11124 {0x04, 0, 0, 0, 0},
11125 {0x05, 0, 0, 0, 0},
11126 {0x06, 0, 0, 0, 0},
11127 {0x07, 0, 0, 0, 0},
11128 {0x08, 0, 0, 0, 0},
11129 {0x09, 0, 0, 0, 0},
11130 {0x0A, 0, 0, 0, 0},
11131 {0x0B, 0, 0, 0, 0},
11132 {0x0C, 0, 0, 0, 0},
11133 {0x0D, 0, 0, 0, 0},
11134 {0x0E, 0, 0, 0, 0},
11135 {0x0F, 0, 0, 0, 0},
11136 {0x10, 0, 0, 0, 0},
11137 {0x11, 0, 0, 0, 0},
11138 {0x12, 0, 0, 0, 0},
11139 {0x13, 0, 0, 0, 0},
11140 {0x14, 0, 0, 0, 0},
11141 {0x15, 0, 0, 0, 0},
11142 {0x16, 0, 0, 0, 0},
11143 {0x17, 0, 0, 0, 0},
11144 {0x18, 0, 0, 0, 0},
11145 {0x19, 0, 0, 0, 0},
11146 {0x1A, 0, 0, 0, 0},
11147 {0x1B, 0, 0, 0, 0},
11148 {0x1C, 0, 0, 0, 0},
11149 {0x1D, 0, 0, 0, 0},
11150 {0x1E, 0, 0, 0, 0},
11151 {0x1F, 0, 0, 0, 0},
11152 {0x20, 0, 0, 0, 0},
11153 {0x21, 0x88, 0x88, 0, 0},
11154 {0x22, 0x88, 0x88, 0, 0},
11155 {0x23, 0x88, 0x88, 0, 0},
11156 {0x24, 0x88, 0x88, 0, 0},
11157 {0x25, 0xc, 0xc, 0, 0},
11158 {0x26, 0, 0, 0, 0},
11159 {0x27, 0x3, 0x3, 0, 0},
11160 {0x28, 0, 0, 0, 0},
11161 {0x29, 0x3, 0x3, 0, 0},
11162 {0x2A, 0x37, 0x37, 0, 0},
11163 {0x2B, 0x3, 0x3, 0, 0},
11164 {0x2C, 0, 0, 0, 0},
11165 {0x2D, 0, 0, 0, 0},
11166 {0x2E, 0x1, 0x1, 0, 0},
11167 {0x2F, 0x1, 0x1, 0, 0},
11168 {0x30, 0, 0, 0, 0},
11169 {0x31, 0, 0, 0, 0},
11170 {0x32, 0, 0, 0, 0},
11171 {0x33, 0x11, 0x11, 0, 0},
11172 {0x34, 0xee, 0xee, 1, 1},
11173 {0x35, 0, 0, 0, 0},
11174 {0x36, 0, 0, 0, 0},
11175 {0x37, 0x3, 0x3, 0, 0},
11176 {0x38, 0x50, 0x50, 1, 1},
11177 {0x39, 0, 0, 0, 0},
11178 {0x3A, 0x50, 0x50, 1, 1},
11179 {0x3B, 0, 0, 0, 0},
11180 {0x3C, 0x6e, 0x6e, 0, 0},
11181 {0x3D, 0xf0, 0xf0, 1, 1},
11182 {0x3E, 0, 0, 0, 0},
11183 {0x3F, 0, 0, 0, 0},
11184 {0x40, 0, 0, 0, 0},
11185 {0x41, 0x3, 0x3, 0, 0},
11186 {0x42, 0x3, 0x3, 0, 0},
11187 {0x43, 0, 0, 0, 0},
11188 {0x44, 0x1e, 0x1e, 0, 0},
11189 {0x45, 0, 0, 0, 0},
11190 {0x46, 0x6e, 0x6e, 0, 0},
11191 {0x47, 0xf0, 0xf0, 1, 1},
11192 {0x48, 0, 0, 0, 0},
11193 {0x49, 0x2, 0x2, 0, 0},
11194 {0x4A, 0xff, 0xff, 1, 1},
11195 {0x4B, 0xc, 0xc, 0, 0},
11196 {0x4C, 0, 0, 0, 0},
11197 {0x4D, 0x38, 0x38, 0, 0},
11198 {0x4E, 0x70, 0x70, 1, 1},
11199 {0x4F, 0x2, 0x2, 0, 0},
11200 {0x50, 0x88, 0x88, 0, 0},
11201 {0x51, 0xc, 0xc, 0, 0},
11202 {0x52, 0, 0, 0, 0},
11203 {0x53, 0x8, 0x8, 0, 0},
11204 {0x54, 0x70, 0x70, 1, 1},
11205 {0x55, 0x2, 0x2, 0, 0},
11206 {0x56, 0xff, 0xff, 1, 1},
11207 {0x57, 0, 0, 0, 0},
11208 {0x58, 0x83, 0x83, 0, 0},
11209 {0x59, 0x77, 0x77, 1, 1},
11210 {0x5A, 0, 0, 0, 0},
11211 {0x5B, 0x2, 0x2, 0, 0},
11212 {0x5C, 0x88, 0x88, 0, 0},
11213 {0x5D, 0, 0, 0, 0},
11214 {0x5E, 0x8, 0x8, 0, 0},
11215 {0x5F, 0x77, 0x77, 1, 1},
11216 {0x60, 0x1, 0x1, 0, 0},
11217 {0x61, 0, 0, 0, 0},
11218 {0x62, 0x7, 0x7, 0, 0},
11219 {0x63, 0, 0, 0, 0},
11220 {0x64, 0x7, 0x7, 0, 0},
11221 {0x65, 0, 0, 0, 0},
11222 {0x66, 0, 0, 0, 0},
11223 {0x67, 0, 0, 1, 1},
11224 {0x68, 0, 0, 0, 0},
11225 {0x69, 0xa, 0xa, 0, 0},
11226 {0x6A, 0, 0, 0, 0},
11227 {0x6B, 0, 0, 0, 0},
11228 {0x6C, 0, 0, 0, 0},
11229 {0x6D, 0, 0, 0, 0},
11230 {0x6E, 0, 0, 0, 0},
11231 {0x6F, 0, 0, 0, 0},
11232 {0x70, 0, 0, 0, 0},
11233 {0x71, 0x2, 0x2, 0, 0},
11234 {0x72, 0, 0, 0, 0},
11235 {0x73, 0, 0, 0, 0},
11236 {0x74, 0xe, 0xe, 0, 0},
11237 {0x75, 0xe, 0xe, 0, 0},
11238 {0x76, 0xe, 0xe, 0, 0},
11239 {0x77, 0x13, 0x13, 0, 0},
11240 {0x78, 0x13, 0x13, 0, 0},
11241 {0x79, 0x1b, 0x1b, 0, 0},
11242 {0x7A, 0x1b, 0x1b, 0, 0},
11243 {0x7B, 0x55, 0x55, 0, 0},
11244 {0x7C, 0x5b, 0x5b, 0, 0},
11245 {0x7D, 0x30, 0x30, 1, 1},
11246 {0x7E, 0, 0, 0, 0},
11247 {0x7F, 0, 0, 0, 0},
11248 {0x80, 0, 0, 0, 0},
11249 {0x81, 0, 0, 0, 0},
11250 {0x82, 0, 0, 0, 0},
11251 {0x83, 0, 0, 0, 0},
11252 {0x84, 0, 0, 0, 0},
11253 {0x85, 0, 0, 0, 0},
11254 {0x86, 0, 0, 0, 0},
11255 {0x87, 0, 0, 0, 0},
11256 {0x88, 0, 0, 0, 0},
11257 {0x89, 0, 0, 0, 0},
11258 {0x8A, 0, 0, 0, 0},
11259 {0x8B, 0, 0, 0, 0},
11260 {0x8C, 0, 0, 0, 0},
11261 {0x8D, 0, 0, 0, 0},
11262 {0x8E, 0, 0, 0, 0},
11263 {0x8F, 0, 0, 0, 0},
11264 {0x90, 0, 0, 0, 0},
11265 {0x91, 0, 0, 0, 0},
11266 {0x92, 0, 0, 0, 0},
11267 {0x93, 0x70, 0x70, 0, 0},
11268 {0x94, 0x70, 0x70, 0, 0},
11269 {0x95, 0x70, 0x70, 0, 0},
11270 {0x96, 0x70, 0x70, 0, 0},
11271 {0x97, 0x70, 0x70, 0, 0},
11272 {0x98, 0x70, 0x70, 0, 0},
11273 {0x99, 0x70, 0x70, 0, 0},
11274 {0x9A, 0x70, 0x70, 0, 0},
11275 {0xFFFF, 0, 0, 0, 0},
11276};
11277
11278static const struct radio_regs regs_RX_2056_rev11[] = {
11279 {0x02, 0, 0, 0, 0},
11280 {0x03, 0, 0, 0, 0},
11281 {0x04, 0, 0, 0, 0},
11282 {0x05, 0, 0, 0, 0},
11283 {0x06, 0, 0, 0, 0},
11284 {0x07, 0, 0, 0, 0},
11285 {0x08, 0, 0, 0, 0},
11286 {0x09, 0, 0, 0, 0},
11287 {0x0A, 0, 0, 0, 0},
11288 {0x0B, 0, 0, 0, 0},
11289 {0x0C, 0, 0, 0, 0},
11290 {0x0D, 0, 0, 0, 0},
11291 {0x0E, 0, 0, 0, 0},
11292 {0x0F, 0, 0, 0, 0},
11293 {0x10, 0, 0, 0, 0},
11294 {0x11, 0, 0, 0, 0},
11295 {0x12, 0, 0, 0, 0},
11296 {0x13, 0, 0, 0, 0},
11297 {0x14, 0, 0, 0, 0},
11298 {0x15, 0, 0, 0, 0},
11299 {0x16, 0, 0, 0, 0},
11300 {0x17, 0, 0, 0, 0},
11301 {0x18, 0, 0, 0, 0},
11302 {0x19, 0, 0, 0, 0},
11303 {0x1A, 0, 0, 0, 0},
11304 {0x1B, 0, 0, 0, 0},
11305 {0x1C, 0, 0, 0, 0},
11306 {0x1D, 0, 0, 0, 0},
11307 {0x1E, 0, 0, 0, 0},
11308 {0x1F, 0, 0, 0, 0},
11309 {0x20, 0x3, 0x3, 0, 0},
11310 {0x21, 0, 0, 0, 0},
11311 {0x22, 0, 0, 0, 0},
11312 {0x23, 0x90, 0x90, 0, 0},
11313 {0x24, 0x55, 0x55, 0, 0},
11314 {0x25, 0x15, 0x15, 0, 0},
11315 {0x26, 0x5, 0x5, 0, 0},
11316 {0x27, 0x15, 0x15, 0, 0},
11317 {0x28, 0x5, 0x5, 0, 0},
11318 {0x29, 0x20, 0x20, 0, 0},
11319 {0x2A, 0x11, 0x11, 0, 0},
11320 {0x2B, 0x90, 0x90, 0, 0},
11321 {0x2C, 0, 0, 0, 0},
11322 {0x2D, 0x88, 0x88, 0, 0},
11323 {0x2E, 0x32, 0x32, 0, 0},
11324 {0x2F, 0x77, 0x77, 0, 0},
11325 {0x30, 0x17, 0x17, 1, 1},
11326 {0x31, 0xff, 0xff, 1, 1},
11327 {0x32, 0x20, 0x20, 0, 0},
11328 {0x33, 0, 0, 0, 0},
11329 {0x34, 0x88, 0x88, 0, 0},
11330 {0x35, 0x32, 0x32, 0, 0},
11331 {0x36, 0x77, 0x77, 0, 0},
11332 {0x37, 0x17, 0x17, 1, 1},
11333 {0x38, 0xf0, 0xf0, 1, 1},
11334 {0x39, 0x20, 0x20, 0, 0},
11335 {0x3A, 0x8, 0x8, 0, 0},
11336 {0x3B, 0x55, 0x55, 1, 1},
11337 {0x3C, 0, 0, 0, 0},
11338 {0x3D, 0x88, 0x88, 1, 1},
11339 {0x3E, 0, 0, 0, 0},
11340 {0x3F, 0x44, 0x44, 0, 0},
11341 {0x40, 0x7, 0x7, 1, 1},
11342 {0x41, 0x6, 0x6, 0, 0},
11343 {0x42, 0x4, 0x4, 0, 0},
11344 {0x43, 0, 0, 0, 0},
11345 {0x44, 0x8, 0x8, 0, 0},
11346 {0x45, 0x55, 0x55, 1, 1},
11347 {0x46, 0, 0, 0, 0},
11348 {0x47, 0x11, 0x11, 0, 0},
11349 {0x48, 0, 0, 0, 0},
11350 {0x49, 0x44, 0x44, 0, 0},
11351 {0x4A, 0x7, 0x7, 0, 0},
11352 {0x4B, 0x6, 0x6, 0, 0},
11353 {0x4C, 0x4, 0x4, 0, 0},
11354 {0x4D, 0, 0, 0, 0},
11355 {0x4E, 0, 0, 0, 0},
11356 {0x4F, 0x26, 0x26, 1, 1},
11357 {0x50, 0x26, 0x26, 1, 1},
11358 {0x51, 0xf, 0xf, 1, 1},
11359 {0x52, 0xf, 0xf, 1, 1},
11360 {0x53, 0x44, 0x44, 0, 0},
11361 {0x54, 0, 0, 0, 0},
11362 {0x55, 0, 0, 0, 0},
11363 {0x56, 0x8, 0x8, 0, 0},
11364 {0x57, 0x8, 0x8, 0, 0},
11365 {0x58, 0x7, 0x7, 0, 0},
11366 {0x59, 0x22, 0x22, 0, 0},
11367 {0x5A, 0x22, 0x22, 0, 0},
11368 {0x5B, 0x2, 0x2, 0, 0},
11369 {0x5C, 0x4, 0x4, 1, 1},
11370 {0x5D, 0x7, 0x7, 0, 0},
11371 {0x5E, 0x55, 0x55, 0, 0},
11372 {0x5F, 0x23, 0x23, 0, 0},
11373 {0x60, 0x41, 0x41, 0, 0},
11374 {0x61, 0x1, 0x1, 0, 0},
11375 {0x62, 0xa, 0xa, 0, 0},
11376 {0x63, 0, 0, 0, 0},
11377 {0x64, 0, 0, 0, 0},
11378 {0x65, 0, 0, 0, 0},
11379 {0x66, 0, 0, 0, 0},
11380 {0x67, 0, 0, 0, 0},
11381 {0x68, 0, 0, 0, 0},
11382 {0x69, 0, 0, 0, 0},
11383 {0x6A, 0, 0, 0, 0},
11384 {0x6B, 0xc, 0xc, 0, 0},
11385 {0x6C, 0, 0, 0, 0},
11386 {0x6D, 0, 0, 0, 0},
11387 {0x6E, 0, 0, 0, 0},
11388 {0x6F, 0, 0, 0, 0},
11389 {0x70, 0, 0, 0, 0},
11390 {0x71, 0, 0, 0, 0},
11391 {0x72, 0x22, 0x22, 0, 0},
11392 {0x73, 0x22, 0x22, 0, 0},
11393 {0x74, 0, 0, 1, 1},
11394 {0x75, 0xa, 0xa, 0, 0},
11395 {0x76, 0x1, 0x1, 0, 0},
11396 {0x77, 0x22, 0x22, 0, 0},
11397 {0x78, 0x30, 0x30, 0, 0},
11398 {0x79, 0, 0, 0, 0},
11399 {0x7A, 0, 0, 0, 0},
11400 {0x7B, 0, 0, 0, 0},
11401 {0x7C, 0, 0, 0, 0},
11402 {0x7D, 0x5, 0x5, 1, 1},
11403 {0x7E, 0, 0, 0, 0},
11404 {0x7F, 0, 0, 0, 0},
11405 {0x80, 0, 0, 0, 0},
11406 {0x81, 0, 0, 0, 0},
11407 {0x82, 0, 0, 0, 0},
11408 {0x83, 0, 0, 0, 0},
11409 {0x84, 0, 0, 0, 0},
11410 {0x85, 0, 0, 0, 0},
11411 {0x86, 0, 0, 0, 0},
11412 {0x87, 0, 0, 0, 0},
11413 {0x88, 0, 0, 0, 0},
11414 {0x89, 0, 0, 0, 0},
11415 {0x8A, 0, 0, 0, 0},
11416 {0x8B, 0, 0, 0, 0},
11417 {0x8C, 0, 0, 0, 0},
11418 {0x8D, 0, 0, 0, 0},
11419 {0x8E, 0, 0, 0, 0},
11420 {0x8F, 0, 0, 0, 0},
11421 {0x90, 0, 0, 0, 0},
11422 {0x91, 0, 0, 0, 0},
11423 {0x92, 0, 0, 0, 0},
11424 {0x93, 0, 0, 0, 0},
11425 {0x94, 0, 0, 0, 0},
11426 {0xFFFF, 0, 0, 0, 0},
11427};
11428
11429static struct radio_20xx_regs regs_2057_rev4[] = {
11430 {0x00, 0x84, 0},
11431 {0x01, 0, 0},
11432 {0x02, 0x60, 0},
11433 {0x03, 0x1f, 0},
11434 {0x04, 0x4, 0},
11435 {0x05, 0x2, 0},
11436 {0x06, 0x1, 0},
11437 {0x07, 0x1, 0},
11438 {0x08, 0x1, 0},
11439 {0x09, 0x69, 0},
11440 {0x0A, 0x66, 0},
11441 {0x0B, 0x6, 0},
11442 {0x0C, 0x18, 0},
11443 {0x0D, 0x3, 0},
11444 {0x0E, 0x20, 1},
11445 {0x0F, 0x20, 0},
11446 {0x10, 0, 0},
11447 {0x11, 0x7c, 0},
11448 {0x12, 0x42, 0},
11449 {0x13, 0xbd, 0},
11450 {0x14, 0x7, 0},
11451 {0x15, 0xf7, 0},
11452 {0x16, 0x8, 0},
11453 {0x17, 0x17, 0},
11454 {0x18, 0x7, 0},
11455 {0x19, 0, 0},
11456 {0x1A, 0x2, 0},
11457 {0x1B, 0x13, 0},
11458 {0x1C, 0x3e, 0},
11459 {0x1D, 0x3e, 0},
11460 {0x1E, 0x96, 0},
11461 {0x1F, 0x4, 0},
11462 {0x20, 0, 0},
11463 {0x21, 0, 0},
11464 {0x22, 0x17, 0},
11465 {0x23, 0x4, 0},
11466 {0x24, 0x1, 0},
11467 {0x25, 0x6, 0},
11468 {0x26, 0x4, 0},
11469 {0x27, 0xd, 0},
11470 {0x28, 0xd, 0},
11471 {0x29, 0x30, 0},
11472 {0x2A, 0x32, 0},
11473 {0x2B, 0x8, 0},
11474 {0x2C, 0x1c, 0},
11475 {0x2D, 0x2, 0},
11476 {0x2E, 0x4, 0},
11477 {0x2F, 0x7f, 0},
11478 {0x30, 0x27, 0},
11479 {0x31, 0, 1},
11480 {0x32, 0, 1},
11481 {0x33, 0, 1},
11482 {0x34, 0, 0},
11483 {0x35, 0x26, 1},
11484 {0x36, 0x18, 0},
11485 {0x37, 0x7, 0},
11486 {0x38, 0x66, 0},
11487 {0x39, 0x66, 0},
11488 {0x3A, 0x66, 0},
11489 {0x3B, 0x66, 0},
11490 {0x3C, 0xff, 1},
11491 {0x3D, 0xff, 1},
11492 {0x3E, 0xff, 1},
11493 {0x3F, 0xff, 1},
11494 {0x40, 0x16, 0},
11495 {0x41, 0x7, 0},
11496 {0x42, 0x19, 0},
11497 {0x43, 0x7, 0},
11498 {0x44, 0x6, 0},
11499 {0x45, 0x3, 0},
11500 {0x46, 0x1, 0},
11501 {0x47, 0x7, 0},
11502 {0x48, 0x33, 0},
11503 {0x49, 0x5, 0},
11504 {0x4A, 0x77, 0},
11505 {0x4B, 0x66, 0},
11506 {0x4C, 0x66, 0},
11507 {0x4D, 0, 0},
11508 {0x4E, 0x4, 0},
11509 {0x4F, 0xc, 0},
11510 {0x50, 0, 0},
11511 {0x51, 0x75, 0},
11512 {0x56, 0x7, 0},
11513 {0x57, 0, 0},
11514 {0x58, 0, 0},
11515 {0x59, 0xa8, 0},
11516 {0x5A, 0, 0},
11517 {0x5B, 0x1f, 0},
11518 {0x5C, 0x30, 0},
11519 {0x5D, 0x1, 0},
11520 {0x5E, 0x30, 0},
11521 {0x5F, 0x70, 0},
11522 {0x60, 0, 0},
11523 {0x61, 0, 0},
11524 {0x62, 0x33, 1},
11525 {0x63, 0x19, 0},
11526 {0x64, 0x62, 0},
11527 {0x65, 0, 0},
11528 {0x66, 0x11, 0},
11529 {0x69, 0, 0},
11530 {0x6A, 0x7e, 0},
11531 {0x6B, 0x3f, 0},
11532 {0x6C, 0x7f, 0},
11533 {0x6D, 0x78, 0},
11534 {0x6E, 0xc8, 0},
11535 {0x6F, 0x88, 0},
11536 {0x70, 0x8, 0},
11537 {0x71, 0xf, 0},
11538 {0x72, 0xbc, 0},
11539 {0x73, 0x8, 0},
11540 {0x74, 0x60, 0},
11541 {0x75, 0x1e, 0},
11542 {0x76, 0x70, 0},
11543 {0x77, 0, 0},
11544 {0x78, 0, 0},
11545 {0x79, 0, 0},
11546 {0x7A, 0x33, 0},
11547 {0x7B, 0x1e, 0},
11548 {0x7C, 0x62, 0},
11549 {0x7D, 0x11, 0},
11550 {0x80, 0x3c, 0},
11551 {0x81, 0x9c, 0},
11552 {0x82, 0xa, 0},
11553 {0x83, 0x9d, 0},
11554 {0x84, 0xa, 0},
11555 {0x85, 0, 0},
11556 {0x86, 0x40, 0},
11557 {0x87, 0x40, 0},
11558 {0x88, 0x88, 0},
11559 {0x89, 0x10, 0},
11560 {0x8A, 0xf0, 1},
11561 {0x8B, 0x10, 1},
11562 {0x8C, 0xf0, 1},
11563 {0x8D, 0, 0},
11564 {0x8E, 0, 0},
11565 {0x8F, 0x10, 0},
11566 {0x90, 0x55, 0},
11567 {0x91, 0x3f, 1},
11568 {0x92, 0x36, 1},
11569 {0x93, 0, 0},
11570 {0x94, 0, 0},
11571 {0x95, 0, 0},
11572 {0x96, 0x87, 0},
11573 {0x97, 0x11, 0},
11574 {0x98, 0, 0},
11575 {0x99, 0x33, 0},
11576 {0x9A, 0x88, 0},
11577 {0x9B, 0, 0},
11578 {0x9C, 0x87, 0},
11579 {0x9D, 0x11, 0},
11580 {0x9E, 0, 0},
11581 {0x9F, 0x33, 0},
11582 {0xA0, 0x88, 0},
11583 {0xA1, 0xe1, 0},
11584 {0xA2, 0x3f, 0},
11585 {0xA3, 0x44, 0},
11586 {0xA4, 0x8c, 1},
11587 {0xA5, 0x6d, 0},
11588 {0xA6, 0x22, 0},
11589 {0xA7, 0xbe, 0},
11590 {0xA8, 0x55, 1},
11591 {0xA9, 0xc, 0},
11592 {0xAA, 0xc, 0},
11593 {0xAB, 0xaa, 0},
11594 {0xAC, 0x2, 0},
11595 {0xAD, 0, 0},
11596 {0xAE, 0x10, 0},
11597 {0xAF, 0x1, 1},
11598 {0xB0, 0, 0},
11599 {0xB1, 0, 0},
11600 {0xB2, 0x80, 0},
11601 {0xB3, 0x60, 0},
11602 {0xB4, 0x44, 0},
11603 {0xB5, 0x55, 0},
11604 {0xB6, 0x1, 0},
11605 {0xB7, 0x55, 0},
11606 {0xB8, 0x1, 0},
11607 {0xB9, 0x5, 0},
11608 {0xBA, 0x55, 0},
11609 {0xBB, 0x55, 0},
11610 {0xC1, 0, 0},
11611 {0xC2, 0, 0},
11612 {0xC3, 0, 0},
11613 {0xC4, 0, 0},
11614 {0xC5, 0, 0},
11615 {0xC6, 0, 0},
11616 {0xC7, 0, 0},
11617 {0xC8, 0, 0},
11618 {0xC9, 0, 0},
11619 {0xCA, 0, 0},
11620 {0xCB, 0, 0},
11621 {0xCC, 0, 0},
11622 {0xCD, 0, 0},
11623 {0xCE, 0x5e, 0},
11624 {0xCF, 0xc, 0},
11625 {0xD0, 0xc, 0},
11626 {0xD1, 0xc, 0},
11627 {0xD2, 0, 0},
11628 {0xD3, 0x2b, 0},
11629 {0xD4, 0xc, 0},
11630 {0xD5, 0, 0},
11631 {0xD6, 0x75, 0},
11632 {0xDB, 0x7, 0},
11633 {0xDC, 0, 0},
11634 {0xDD, 0, 0},
11635 {0xDE, 0xa8, 0},
11636 {0xDF, 0, 0},
11637 {0xE0, 0x1f, 0},
11638 {0xE1, 0x30, 0},
11639 {0xE2, 0x1, 0},
11640 {0xE3, 0x30, 0},
11641 {0xE4, 0x70, 0},
11642 {0xE5, 0, 0},
11643 {0xE6, 0, 0},
11644 {0xE7, 0x33, 0},
11645 {0xE8, 0x19, 0},
11646 {0xE9, 0x62, 0},
11647 {0xEA, 0, 0},
11648 {0xEB, 0x11, 0},
11649 {0xEE, 0, 0},
11650 {0xEF, 0x7e, 0},
11651 {0xF0, 0x3f, 0},
11652 {0xF1, 0x7f, 0},
11653 {0xF2, 0x78, 0},
11654 {0xF3, 0xc8, 0},
11655 {0xF4, 0x88, 0},
11656 {0xF5, 0x8, 0},
11657 {0xF6, 0xf, 0},
11658 {0xF7, 0xbc, 0},
11659 {0xF8, 0x8, 0},
11660 {0xF9, 0x60, 0},
11661 {0xFA, 0x1e, 0},
11662 {0xFB, 0x70, 0},
11663 {0xFC, 0, 0},
11664 {0xFD, 0, 0},
11665 {0xFE, 0, 0},
11666 {0xFF, 0x33, 0},
11667 {0x100, 0x1e, 0},
11668 {0x101, 0x62, 0},
11669 {0x102, 0x11, 0},
11670 {0x105, 0x3c, 0},
11671 {0x106, 0x9c, 0},
11672 {0x107, 0xa, 0},
11673 {0x108, 0x9d, 0},
11674 {0x109, 0xa, 0},
11675 {0x10A, 0, 0},
11676 {0x10B, 0x40, 0},
11677 {0x10C, 0x40, 0},
11678 {0x10D, 0x88, 0},
11679 {0x10E, 0x10, 0},
11680 {0x10F, 0xf0, 1},
11681 {0x110, 0x10, 1},
11682 {0x111, 0xf0, 1},
11683 {0x112, 0, 0},
11684 {0x113, 0, 0},
11685 {0x114, 0x10, 0},
11686 {0x115, 0x55, 0},
11687 {0x116, 0x3f, 1},
11688 {0x117, 0x36, 1},
11689 {0x118, 0, 0},
11690 {0x119, 0, 0},
11691 {0x11A, 0, 0},
11692 {0x11B, 0x87, 0},
11693 {0x11C, 0x11, 0},
11694 {0x11D, 0, 0},
11695 {0x11E, 0x33, 0},
11696 {0x11F, 0x88, 0},
11697 {0x120, 0, 0},
11698 {0x121, 0x87, 0},
11699 {0x122, 0x11, 0},
11700 {0x123, 0, 0},
11701 {0x124, 0x33, 0},
11702 {0x125, 0x88, 0},
11703 {0x126, 0xe1, 0},
11704 {0x127, 0x3f, 0},
11705 {0x128, 0x44, 0},
11706 {0x129, 0x8c, 1},
11707 {0x12A, 0x6d, 0},
11708 {0x12B, 0x22, 0},
11709 {0x12C, 0xbe, 0},
11710 {0x12D, 0x55, 1},
11711 {0x12E, 0xc, 0},
11712 {0x12F, 0xc, 0},
11713 {0x130, 0xaa, 0},
11714 {0x131, 0x2, 0},
11715 {0x132, 0, 0},
11716 {0x133, 0x10, 0},
11717 {0x134, 0x1, 1},
11718 {0x135, 0, 0},
11719 {0x136, 0, 0},
11720 {0x137, 0x80, 0},
11721 {0x138, 0x60, 0},
11722 {0x139, 0x44, 0},
11723 {0x13A, 0x55, 0},
11724 {0x13B, 0x1, 0},
11725 {0x13C, 0x55, 0},
11726 {0x13D, 0x1, 0},
11727 {0x13E, 0x5, 0},
11728 {0x13F, 0x55, 0},
11729 {0x140, 0x55, 0},
11730 {0x146, 0, 0},
11731 {0x147, 0, 0},
11732 {0x148, 0, 0},
11733 {0x149, 0, 0},
11734 {0x14A, 0, 0},
11735 {0x14B, 0, 0},
11736 {0x14C, 0, 0},
11737 {0x14D, 0, 0},
11738 {0x14E, 0, 0},
11739 {0x14F, 0, 0},
11740 {0x150, 0, 0},
11741 {0x151, 0, 0},
11742 {0x152, 0, 0},
11743 {0x153, 0, 0},
11744 {0x154, 0xc, 0},
11745 {0x155, 0xc, 0},
11746 {0x156, 0xc, 0},
11747 {0x157, 0, 0},
11748 {0x158, 0x2b, 0},
11749 {0x159, 0x84, 0},
11750 {0x15A, 0x15, 0},
11751 {0x15B, 0xf, 0},
11752 {0x15C, 0, 0},
11753 {0x15D, 0, 0},
11754 {0x15E, 0, 1},
11755 {0x15F, 0, 1},
11756 {0x160, 0, 1},
11757 {0x161, 0, 1},
11758 {0x162, 0, 1},
11759 {0x163, 0, 1},
11760 {0x164, 0, 0},
11761 {0x165, 0, 0},
11762 {0x166, 0, 0},
11763 {0x167, 0, 0},
11764 {0x168, 0, 0},
11765 {0x169, 0x2, 1},
11766 {0x16A, 0, 1},
11767 {0x16B, 0, 1},
11768 {0x16C, 0, 1},
11769 {0x16D, 0, 0},
11770 {0x170, 0, 0},
11771 {0x171, 0x77, 0},
11772 {0x172, 0x77, 0},
11773 {0x173, 0x77, 0},
11774 {0x174, 0x77, 0},
11775 {0x175, 0, 0},
11776 {0x176, 0x3, 0},
11777 {0x177, 0x37, 0},
11778 {0x178, 0x3, 0},
11779 {0x179, 0, 0},
11780 {0x17A, 0x21, 0},
11781 {0x17B, 0x21, 0},
11782 {0x17C, 0, 0},
11783 {0x17D, 0xaa, 0},
11784 {0x17E, 0, 0},
11785 {0x17F, 0xaa, 0},
11786 {0x180, 0, 0},
11787 {0x190, 0, 0},
11788 {0x191, 0x77, 0},
11789 {0x192, 0x77, 0},
11790 {0x193, 0x77, 0},
11791 {0x194, 0x77, 0},
11792 {0x195, 0, 0},
11793 {0x196, 0x3, 0},
11794 {0x197, 0x37, 0},
11795 {0x198, 0x3, 0},
11796 {0x199, 0, 0},
11797 {0x19A, 0x21, 0},
11798 {0x19B, 0x21, 0},
11799 {0x19C, 0, 0},
11800 {0x19D, 0xaa, 0},
11801 {0x19E, 0, 0},
11802 {0x19F, 0xaa, 0},
11803 {0x1A0, 0, 0},
11804 {0x1A1, 0x2, 0},
11805 {0x1A2, 0xf, 0},
11806 {0x1A3, 0xf, 0},
11807 {0x1A4, 0, 1},
11808 {0x1A5, 0, 1},
11809 {0x1A6, 0, 1},
11810 {0x1A7, 0x2, 0},
11811 {0x1A8, 0xf, 0},
11812 {0x1A9, 0xf, 0},
11813 {0x1AA, 0, 1},
11814 {0x1AB, 0, 1},
11815 {0x1AC, 0, 1},
11816 {0xFFFF, 0, 0},
11817};
11818
11819static struct radio_20xx_regs regs_2057_rev5[] = {
11820 {0x00, 0, 1},
11821 {0x01, 0x57, 1},
11822 {0x02, 0x20, 1},
11823 {0x03, 0x1f, 0},
11824 {0x04, 0x4, 0},
11825 {0x05, 0x2, 0},
11826 {0x06, 0x1, 0},
11827 {0x07, 0x1, 0},
11828 {0x08, 0x1, 0},
11829 {0x09, 0x69, 0},
11830 {0x0A, 0x66, 0},
11831 {0x0B, 0x6, 0},
11832 {0x0C, 0x18, 0},
11833 {0x0D, 0x3, 0},
11834 {0x0E, 0x20, 0},
11835 {0x0F, 0x20, 0},
11836 {0x10, 0, 0},
11837 {0x11, 0x7c, 0},
11838 {0x12, 0x42, 0},
11839 {0x13, 0xbd, 0},
11840 {0x14, 0x7, 0},
11841 {0x15, 0x87, 0},
11842 {0x16, 0x8, 0},
11843 {0x17, 0x17, 0},
11844 {0x18, 0x7, 0},
11845 {0x19, 0, 0},
11846 {0x1A, 0x2, 0},
11847 {0x1B, 0x13, 0},
11848 {0x1C, 0x3e, 0},
11849 {0x1D, 0x3e, 0},
11850 {0x1E, 0x96, 0},
11851 {0x1F, 0x4, 0},
11852 {0x20, 0, 0},
11853 {0x21, 0, 0},
11854 {0x22, 0x17, 0},
11855 {0x23, 0x6, 1},
11856 {0x24, 0x1, 0},
11857 {0x25, 0x6, 0},
11858 {0x26, 0x4, 0},
11859 {0x27, 0xd, 0},
11860 {0x28, 0xd, 0},
11861 {0x29, 0x30, 0},
11862 {0x2A, 0x32, 0},
11863 {0x2B, 0x8, 0},
11864 {0x2C, 0x1c, 0},
11865 {0x2D, 0x2, 0},
11866 {0x2E, 0x4, 0},
11867 {0x2F, 0x7f, 0},
11868 {0x30, 0x27, 0},
11869 {0x31, 0, 1},
11870 {0x32, 0, 1},
11871 {0x33, 0, 1},
11872 {0x34, 0, 0},
11873 {0x35, 0x20, 0},
11874 {0x36, 0x18, 0},
11875 {0x37, 0x7, 0},
11876 {0x38, 0x66, 0},
11877 {0x39, 0x66, 0},
11878 {0x3C, 0xff, 0},
11879 {0x3D, 0xff, 0},
11880 {0x40, 0x16, 0},
11881 {0x41, 0x7, 0},
11882 {0x45, 0x3, 0},
11883 {0x46, 0x1, 0},
11884 {0x47, 0x7, 0},
11885 {0x4B, 0x66, 0},
11886 {0x4C, 0x66, 0},
11887 {0x4D, 0, 0},
11888 {0x4E, 0x4, 0},
11889 {0x4F, 0xc, 0},
11890 {0x50, 0, 0},
11891 {0x51, 0x70, 1},
11892 {0x56, 0x7, 0},
11893 {0x57, 0, 0},
11894 {0x58, 0, 0},
11895 {0x59, 0x88, 1},
11896 {0x5A, 0, 0},
11897 {0x5B, 0x1f, 0},
11898 {0x5C, 0x20, 1},
11899 {0x5D, 0x1, 0},
11900 {0x5E, 0x30, 0},
11901 {0x5F, 0x70, 0},
11902 {0x60, 0, 0},
11903 {0x61, 0, 0},
11904 {0x62, 0x33, 1},
11905 {0x63, 0xf, 1},
11906 {0x64, 0xf, 1},
11907 {0x65, 0, 0},
11908 {0x66, 0x11, 0},
11909 {0x80, 0x3c, 0},
11910 {0x81, 0x1, 1},
11911 {0x82, 0xa, 0},
11912 {0x85, 0, 0},
11913 {0x86, 0x40, 0},
11914 {0x87, 0x40, 0},
11915 {0x88, 0x88, 0},
11916 {0x89, 0x10, 0},
11917 {0x8A, 0xf0, 0},
11918 {0x8B, 0x10, 0},
11919 {0x8C, 0xf0, 0},
11920 {0x8F, 0x10, 0},
11921 {0x90, 0x55, 0},
11922 {0x91, 0x3f, 1},
11923 {0x92, 0x36, 1},
11924 {0x93, 0, 0},
11925 {0x94, 0, 0},
11926 {0x95, 0, 0},
11927 {0x96, 0x87, 0},
11928 {0x97, 0x11, 0},
11929 {0x98, 0, 0},
11930 {0x99, 0x33, 0},
11931 {0x9A, 0x88, 0},
11932 {0xA1, 0x20, 1},
11933 {0xA2, 0x3f, 0},
11934 {0xA3, 0x44, 0},
11935 {0xA4, 0x8c, 0},
11936 {0xA5, 0x6c, 0},
11937 {0xA6, 0x22, 0},
11938 {0xA7, 0xbe, 0},
11939 {0xA8, 0x55, 0},
11940 {0xAA, 0xc, 0},
11941 {0xAB, 0xaa, 0},
11942 {0xAC, 0x2, 0},
11943 {0xAD, 0, 0},
11944 {0xAE, 0x10, 0},
11945 {0xAF, 0x1, 0},
11946 {0xB0, 0, 0},
11947 {0xB1, 0, 0},
11948 {0xB2, 0x80, 0},
11949 {0xB3, 0x60, 0},
11950 {0xB4, 0x44, 0},
11951 {0xB5, 0x55, 0},
11952 {0xB6, 0x1, 0},
11953 {0xB7, 0x55, 0},
11954 {0xB8, 0x1, 0},
11955 {0xB9, 0x5, 0},
11956 {0xBA, 0x55, 0},
11957 {0xBB, 0x55, 0},
11958 {0xC3, 0, 0},
11959 {0xC4, 0, 0},
11960 {0xC5, 0, 0},
11961 {0xC6, 0, 0},
11962 {0xC7, 0, 0},
11963 {0xC8, 0, 0},
11964 {0xC9, 0, 0},
11965 {0xCA, 0, 0},
11966 {0xCB, 0, 0},
11967 {0xCD, 0, 0},
11968 {0xCE, 0x5e, 0},
11969 {0xCF, 0xc, 0},
11970 {0xD0, 0xc, 0},
11971 {0xD1, 0xc, 0},
11972 {0xD2, 0, 0},
11973 {0xD3, 0x2b, 0},
11974 {0xD4, 0xc, 0},
11975 {0xD5, 0, 0},
11976 {0xD6, 0x70, 1},
11977 {0xDB, 0x7, 0},
11978 {0xDC, 0, 0},
11979 {0xDD, 0, 0},
11980 {0xDE, 0x88, 1},
11981 {0xDF, 0, 0},
11982 {0xE0, 0x1f, 0},
11983 {0xE1, 0x20, 1},
11984 {0xE2, 0x1, 0},
11985 {0xE3, 0x30, 0},
11986 {0xE4, 0x70, 0},
11987 {0xE5, 0, 0},
11988 {0xE6, 0, 0},
11989 {0xE7, 0x33, 0},
11990 {0xE8, 0xf, 1},
11991 {0xE9, 0xf, 1},
11992 {0xEA, 0, 0},
11993 {0xEB, 0x11, 0},
11994 {0x105, 0x3c, 0},
11995 {0x106, 0x1, 1},
11996 {0x107, 0xa, 0},
11997 {0x10A, 0, 0},
11998 {0x10B, 0x40, 0},
11999 {0x10C, 0x40, 0},
12000 {0x10D, 0x88, 0},
12001 {0x10E, 0x10, 0},
12002 {0x10F, 0xf0, 0},
12003 {0x110, 0x10, 0},
12004 {0x111, 0xf0, 0},
12005 {0x114, 0x10, 0},
12006 {0x115, 0x55, 0},
12007 {0x116, 0x3f, 1},
12008 {0x117, 0x36, 1},
12009 {0x118, 0, 0},
12010 {0x119, 0, 0},
12011 {0x11A, 0, 0},
12012 {0x11B, 0x87, 0},
12013 {0x11C, 0x11, 0},
12014 {0x11D, 0, 0},
12015 {0x11E, 0x33, 0},
12016 {0x11F, 0x88, 0},
12017 {0x126, 0x20, 1},
12018 {0x127, 0x3f, 0},
12019 {0x128, 0x44, 0},
12020 {0x129, 0x8c, 0},
12021 {0x12A, 0x6c, 0},
12022 {0x12B, 0x22, 0},
12023 {0x12C, 0xbe, 0},
12024 {0x12D, 0x55, 0},
12025 {0x12F, 0xc, 0},
12026 {0x130, 0xaa, 0},
12027 {0x131, 0x2, 0},
12028 {0x132, 0, 0},
12029 {0x133, 0x10, 0},
12030 {0x134, 0x1, 0},
12031 {0x135, 0, 0},
12032 {0x136, 0, 0},
12033 {0x137, 0x80, 0},
12034 {0x138, 0x60, 0},
12035 {0x139, 0x44, 0},
12036 {0x13A, 0x55, 0},
12037 {0x13B, 0x1, 0},
12038 {0x13C, 0x55, 0},
12039 {0x13D, 0x1, 0},
12040 {0x13E, 0x5, 0},
12041 {0x13F, 0x55, 0},
12042 {0x140, 0x55, 0},
12043 {0x148, 0, 0},
12044 {0x149, 0, 0},
12045 {0x14A, 0, 0},
12046 {0x14B, 0, 0},
12047 {0x14C, 0, 0},
12048 {0x14D, 0, 0},
12049 {0x14E, 0, 0},
12050 {0x14F, 0, 0},
12051 {0x150, 0, 0},
12052 {0x154, 0xc, 0},
12053 {0x155, 0xc, 0},
12054 {0x156, 0xc, 0},
12055 {0x157, 0, 0},
12056 {0x158, 0x2b, 0},
12057 {0x159, 0x84, 0},
12058 {0x15A, 0x15, 0},
12059 {0x15B, 0xf, 0},
12060 {0x15C, 0, 0},
12061 {0x15D, 0, 0},
12062 {0x15E, 0, 1},
12063 {0x15F, 0, 1},
12064 {0x160, 0, 1},
12065 {0x161, 0, 1},
12066 {0x162, 0, 1},
12067 {0x163, 0, 1},
12068 {0x164, 0, 0},
12069 {0x165, 0, 0},
12070 {0x166, 0, 0},
12071 {0x167, 0, 0},
12072 {0x168, 0, 0},
12073 {0x169, 0, 0},
12074 {0x16A, 0, 1},
12075 {0x16B, 0, 1},
12076 {0x16C, 0, 1},
12077 {0x16D, 0, 0},
12078 {0x170, 0, 0},
12079 {0x171, 0x77, 0},
12080 {0x172, 0x77, 0},
12081 {0x173, 0x77, 0},
12082 {0x174, 0x77, 0},
12083 {0x175, 0, 0},
12084 {0x176, 0x3, 0},
12085 {0x177, 0x37, 0},
12086 {0x178, 0x3, 0},
12087 {0x179, 0, 0},
12088 {0x17B, 0x21, 0},
12089 {0x17C, 0, 0},
12090 {0x17D, 0xaa, 0},
12091 {0x17E, 0, 0},
12092 {0x190, 0, 0},
12093 {0x191, 0x77, 0},
12094 {0x192, 0x77, 0},
12095 {0x193, 0x77, 0},
12096 {0x194, 0x77, 0},
12097 {0x195, 0, 0},
12098 {0x196, 0x3, 0},
12099 {0x197, 0x37, 0},
12100 {0x198, 0x3, 0},
12101 {0x199, 0, 0},
12102 {0x19B, 0x21, 0},
12103 {0x19C, 0, 0},
12104 {0x19D, 0xaa, 0},
12105 {0x19E, 0, 0},
12106 {0x1A1, 0x2, 0},
12107 {0x1A2, 0xf, 0},
12108 {0x1A3, 0xf, 0},
12109 {0x1A4, 0, 1},
12110 {0x1A5, 0, 1},
12111 {0x1A6, 0, 1},
12112 {0x1A7, 0x2, 0},
12113 {0x1A8, 0xf, 0},
12114 {0x1A9, 0xf, 0},
12115 {0x1AA, 0, 1},
12116 {0x1AB, 0, 1},
12117 {0x1AC, 0, 1},
12118 {0x1AD, 0x84, 0},
12119 {0x1AE, 0x60, 0},
12120 {0x1AF, 0x47, 0},
12121 {0x1B0, 0x47, 0},
12122 {0x1B1, 0, 0},
12123 {0x1B2, 0, 0},
12124 {0x1B3, 0, 0},
12125 {0x1B4, 0, 0},
12126 {0x1B5, 0, 0},
12127 {0x1B6, 0, 0},
12128 {0x1B7, 0xc, 1},
12129 {0x1B8, 0, 0},
12130 {0x1B9, 0, 0},
12131 {0x1BA, 0, 0},
12132 {0x1BB, 0, 0},
12133 {0x1BC, 0, 0},
12134 {0x1BD, 0, 0},
12135 {0x1BE, 0, 0},
12136 {0x1BF, 0, 0},
12137 {0x1C0, 0, 0},
12138 {0x1C1, 0x1, 1},
12139 {0x1C2, 0x80, 1},
12140 {0x1C3, 0, 0},
12141 {0x1C4, 0, 0},
12142 {0x1C5, 0, 0},
12143 {0x1C6, 0, 0},
12144 {0x1C7, 0, 0},
12145 {0x1C8, 0, 0},
12146 {0x1C9, 0, 0},
12147 {0x1CA, 0, 0},
12148 {0xFFFF, 0, 0}
12149};
12150
12151static struct radio_20xx_regs regs_2057_rev5v1[] = {
12152 {0x00, 0x15, 1},
12153 {0x01, 0x57, 1},
12154 {0x02, 0x20, 1},
12155 {0x03, 0x1f, 0},
12156 {0x04, 0x4, 0},
12157 {0x05, 0x2, 0},
12158 {0x06, 0x1, 0},
12159 {0x07, 0x1, 0},
12160 {0x08, 0x1, 0},
12161 {0x09, 0x69, 0},
12162 {0x0A, 0x66, 0},
12163 {0x0B, 0x6, 0},
12164 {0x0C, 0x18, 0},
12165 {0x0D, 0x3, 0},
12166 {0x0E, 0x20, 0},
12167 {0x0F, 0x20, 0},
12168 {0x10, 0, 0},
12169 {0x11, 0x7c, 0},
12170 {0x12, 0x42, 0},
12171 {0x13, 0xbd, 0},
12172 {0x14, 0x7, 0},
12173 {0x15, 0x87, 0},
12174 {0x16, 0x8, 0},
12175 {0x17, 0x17, 0},
12176 {0x18, 0x7, 0},
12177 {0x19, 0, 0},
12178 {0x1A, 0x2, 0},
12179 {0x1B, 0x13, 0},
12180 {0x1C, 0x3e, 0},
12181 {0x1D, 0x3e, 0},
12182 {0x1E, 0x96, 0},
12183 {0x1F, 0x4, 0},
12184 {0x20, 0, 0},
12185 {0x21, 0, 0},
12186 {0x22, 0x17, 0},
12187 {0x23, 0x6, 1},
12188 {0x24, 0x1, 0},
12189 {0x25, 0x6, 0},
12190 {0x26, 0x4, 0},
12191 {0x27, 0xd, 0},
12192 {0x28, 0xd, 0},
12193 {0x29, 0x30, 0},
12194 {0x2A, 0x32, 0},
12195 {0x2B, 0x8, 0},
12196 {0x2C, 0x1c, 0},
12197 {0x2D, 0x2, 0},
12198 {0x2E, 0x4, 0},
12199 {0x2F, 0x7f, 0},
12200 {0x30, 0x27, 0},
12201 {0x31, 0, 1},
12202 {0x32, 0, 1},
12203 {0x33, 0, 1},
12204 {0x34, 0, 0},
12205 {0x35, 0x20, 0},
12206 {0x36, 0x18, 0},
12207 {0x37, 0x7, 0},
12208 {0x38, 0x66, 0},
12209 {0x39, 0x66, 0},
12210 {0x3C, 0xff, 0},
12211 {0x3D, 0xff, 0},
12212 {0x40, 0x16, 0},
12213 {0x41, 0x7, 0},
12214 {0x45, 0x3, 0},
12215 {0x46, 0x1, 0},
12216 {0x47, 0x7, 0},
12217 {0x4B, 0x66, 0},
12218 {0x4C, 0x66, 0},
12219 {0x4D, 0, 0},
12220 {0x4E, 0x4, 0},
12221 {0x4F, 0xc, 0},
12222 {0x50, 0, 0},
12223 {0x51, 0x70, 1},
12224 {0x56, 0x7, 0},
12225 {0x57, 0, 0},
12226 {0x58, 0, 0},
12227 {0x59, 0x88, 1},
12228 {0x5A, 0, 0},
12229 {0x5B, 0x1f, 0},
12230 {0x5C, 0x20, 1},
12231 {0x5D, 0x1, 0},
12232 {0x5E, 0x30, 0},
12233 {0x5F, 0x70, 0},
12234 {0x60, 0, 0},
12235 {0x61, 0, 0},
12236 {0x62, 0x33, 1},
12237 {0x63, 0xf, 1},
12238 {0x64, 0xf, 1},
12239 {0x65, 0, 0},
12240 {0x66, 0x11, 0},
12241 {0x80, 0x3c, 0},
12242 {0x81, 0x1, 1},
12243 {0x82, 0xa, 0},
12244 {0x85, 0, 0},
12245 {0x86, 0x40, 0},
12246 {0x87, 0x40, 0},
12247 {0x88, 0x88, 0},
12248 {0x89, 0x10, 0},
12249 {0x8A, 0xf0, 0},
12250 {0x8B, 0x10, 0},
12251 {0x8C, 0xf0, 0},
12252 {0x8F, 0x10, 0},
12253 {0x90, 0x55, 0},
12254 {0x91, 0x3f, 1},
12255 {0x92, 0x36, 1},
12256 {0x93, 0, 0},
12257 {0x94, 0, 0},
12258 {0x95, 0, 0},
12259 {0x96, 0x87, 0},
12260 {0x97, 0x11, 0},
12261 {0x98, 0, 0},
12262 {0x99, 0x33, 0},
12263 {0x9A, 0x88, 0},
12264 {0xA1, 0x20, 1},
12265 {0xA2, 0x3f, 0},
12266 {0xA3, 0x44, 0},
12267 {0xA4, 0x8c, 0},
12268 {0xA5, 0x6c, 0},
12269 {0xA6, 0x22, 0},
12270 {0xA7, 0xbe, 0},
12271 {0xA8, 0x55, 0},
12272 {0xAA, 0xc, 0},
12273 {0xAB, 0xaa, 0},
12274 {0xAC, 0x2, 0},
12275 {0xAD, 0, 0},
12276 {0xAE, 0x10, 0},
12277 {0xAF, 0x1, 0},
12278 {0xB0, 0, 0},
12279 {0xB1, 0, 0},
12280 {0xB2, 0x80, 0},
12281 {0xB3, 0x60, 0},
12282 {0xB4, 0x44, 0},
12283 {0xB5, 0x55, 0},
12284 {0xB6, 0x1, 0},
12285 {0xB7, 0x55, 0},
12286 {0xB8, 0x1, 0},
12287 {0xB9, 0x5, 0},
12288 {0xBA, 0x55, 0},
12289 {0xBB, 0x55, 0},
12290 {0xC3, 0, 0},
12291 {0xC4, 0, 0},
12292 {0xC5, 0, 0},
12293 {0xC6, 0, 0},
12294 {0xC7, 0, 0},
12295 {0xC8, 0, 0},
12296 {0xC9, 0x1, 1},
12297 {0xCA, 0, 0},
12298 {0xCB, 0, 0},
12299 {0xCD, 0, 0},
12300 {0xCE, 0x5e, 0},
12301 {0xCF, 0xc, 0},
12302 {0xD0, 0xc, 0},
12303 {0xD1, 0xc, 0},
12304 {0xD2, 0, 0},
12305 {0xD3, 0x2b, 0},
12306 {0xD4, 0xc, 0},
12307 {0xD5, 0, 0},
12308 {0xD6, 0x70, 1},
12309 {0xDB, 0x7, 0},
12310 {0xDC, 0, 0},
12311 {0xDD, 0, 0},
12312 {0xDE, 0x88, 1},
12313 {0xDF, 0, 0},
12314 {0xE0, 0x1f, 0},
12315 {0xE1, 0x20, 1},
12316 {0xE2, 0x1, 0},
12317 {0xE3, 0x30, 0},
12318 {0xE4, 0x70, 0},
12319 {0xE5, 0, 0},
12320 {0xE6, 0, 0},
12321 {0xE7, 0x33, 0},
12322 {0xE8, 0xf, 1},
12323 {0xE9, 0xf, 1},
12324 {0xEA, 0, 0},
12325 {0xEB, 0x11, 0},
12326 {0x105, 0x3c, 0},
12327 {0x106, 0x1, 1},
12328 {0x107, 0xa, 0},
12329 {0x10A, 0, 0},
12330 {0x10B, 0x40, 0},
12331 {0x10C, 0x40, 0},
12332 {0x10D, 0x88, 0},
12333 {0x10E, 0x10, 0},
12334 {0x10F, 0xf0, 0},
12335 {0x110, 0x10, 0},
12336 {0x111, 0xf0, 0},
12337 {0x114, 0x10, 0},
12338 {0x115, 0x55, 0},
12339 {0x116, 0x3f, 1},
12340 {0x117, 0x36, 1},
12341 {0x118, 0, 0},
12342 {0x119, 0, 0},
12343 {0x11A, 0, 0},
12344 {0x11B, 0x87, 0},
12345 {0x11C, 0x11, 0},
12346 {0x11D, 0, 0},
12347 {0x11E, 0x33, 0},
12348 {0x11F, 0x88, 0},
12349 {0x126, 0x20, 1},
12350 {0x127, 0x3f, 0},
12351 {0x128, 0x44, 0},
12352 {0x129, 0x8c, 0},
12353 {0x12A, 0x6c, 0},
12354 {0x12B, 0x22, 0},
12355 {0x12C, 0xbe, 0},
12356 {0x12D, 0x55, 0},
12357 {0x12F, 0xc, 0},
12358 {0x130, 0xaa, 0},
12359 {0x131, 0x2, 0},
12360 {0x132, 0, 0},
12361 {0x133, 0x10, 0},
12362 {0x134, 0x1, 0},
12363 {0x135, 0, 0},
12364 {0x136, 0, 0},
12365 {0x137, 0x80, 0},
12366 {0x138, 0x60, 0},
12367 {0x139, 0x44, 0},
12368 {0x13A, 0x55, 0},
12369 {0x13B, 0x1, 0},
12370 {0x13C, 0x55, 0},
12371 {0x13D, 0x1, 0},
12372 {0x13E, 0x5, 0},
12373 {0x13F, 0x55, 0},
12374 {0x140, 0x55, 0},
12375 {0x148, 0, 0},
12376 {0x149, 0, 0},
12377 {0x14A, 0, 0},
12378 {0x14B, 0, 0},
12379 {0x14C, 0, 0},
12380 {0x14D, 0, 0},
12381 {0x14E, 0x1, 1},
12382 {0x14F, 0, 0},
12383 {0x150, 0, 0},
12384 {0x154, 0xc, 0},
12385 {0x155, 0xc, 0},
12386 {0x156, 0xc, 0},
12387 {0x157, 0, 0},
12388 {0x158, 0x2b, 0},
12389 {0x159, 0x84, 0},
12390 {0x15A, 0x15, 0},
12391 {0x15B, 0xf, 0},
12392 {0x15C, 0, 0},
12393 {0x15D, 0, 0},
12394 {0x15E, 0, 1},
12395 {0x15F, 0, 1},
12396 {0x160, 0, 1},
12397 {0x161, 0, 1},
12398 {0x162, 0, 1},
12399 {0x163, 0, 1},
12400 {0x164, 0, 0},
12401 {0x165, 0, 0},
12402 {0x166, 0, 0},
12403 {0x167, 0, 0},
12404 {0x168, 0, 0},
12405 {0x169, 0, 0},
12406 {0x16A, 0, 1},
12407 {0x16B, 0, 1},
12408 {0x16C, 0, 1},
12409 {0x16D, 0, 0},
12410 {0x170, 0, 0},
12411 {0x171, 0x77, 0},
12412 {0x172, 0x77, 0},
12413 {0x173, 0x77, 0},
12414 {0x174, 0x77, 0},
12415 {0x175, 0, 0},
12416 {0x176, 0x3, 0},
12417 {0x177, 0x37, 0},
12418 {0x178, 0x3, 0},
12419 {0x179, 0, 0},
12420 {0x17B, 0x21, 0},
12421 {0x17C, 0, 0},
12422 {0x17D, 0xaa, 0},
12423 {0x17E, 0, 0},
12424 {0x190, 0, 0},
12425 {0x191, 0x77, 0},
12426 {0x192, 0x77, 0},
12427 {0x193, 0x77, 0},
12428 {0x194, 0x77, 0},
12429 {0x195, 0, 0},
12430 {0x196, 0x3, 0},
12431 {0x197, 0x37, 0},
12432 {0x198, 0x3, 0},
12433 {0x199, 0, 0},
12434 {0x19B, 0x21, 0},
12435 {0x19C, 0, 0},
12436 {0x19D, 0xaa, 0},
12437 {0x19E, 0, 0},
12438 {0x1A1, 0x2, 0},
12439 {0x1A2, 0xf, 0},
12440 {0x1A3, 0xf, 0},
12441 {0x1A4, 0, 1},
12442 {0x1A5, 0, 1},
12443 {0x1A6, 0, 1},
12444 {0x1A7, 0x2, 0},
12445 {0x1A8, 0xf, 0},
12446 {0x1A9, 0xf, 0},
12447 {0x1AA, 0, 1},
12448 {0x1AB, 0, 1},
12449 {0x1AC, 0, 1},
12450 {0x1AD, 0x84, 0},
12451 {0x1AE, 0x60, 0},
12452 {0x1AF, 0x47, 0},
12453 {0x1B0, 0x47, 0},
12454 {0x1B1, 0, 0},
12455 {0x1B2, 0, 0},
12456 {0x1B3, 0, 0},
12457 {0x1B4, 0, 0},
12458 {0x1B5, 0, 0},
12459 {0x1B6, 0, 0},
12460 {0x1B7, 0xc, 1},
12461 {0x1B8, 0, 0},
12462 {0x1B9, 0, 0},
12463 {0x1BA, 0, 0},
12464 {0x1BB, 0, 0},
12465 {0x1BC, 0, 0},
12466 {0x1BD, 0, 0},
12467 {0x1BE, 0, 0},
12468 {0x1BF, 0, 0},
12469 {0x1C0, 0, 0},
12470 {0x1C1, 0x1, 1},
12471 {0x1C2, 0x80, 1},
12472 {0x1C3, 0, 0},
12473 {0x1C4, 0, 0},
12474 {0x1C5, 0, 0},
12475 {0x1C6, 0, 0},
12476 {0x1C7, 0, 0},
12477 {0x1C8, 0, 0},
12478 {0x1C9, 0, 0},
12479 {0x1CA, 0, 0},
12480 {0xFFFF, 0, 0}
12481};
12482
12483static struct radio_20xx_regs regs_2057_rev7[] = {
12484 {0x00, 0, 1},
12485 {0x01, 0x57, 1},
12486 {0x02, 0x20, 1},
12487 {0x03, 0x1f, 0},
12488 {0x04, 0x4, 0},
12489 {0x05, 0x2, 0},
12490 {0x06, 0x1, 0},
12491 {0x07, 0x1, 0},
12492 {0x08, 0x1, 0},
12493 {0x09, 0x69, 0},
12494 {0x0A, 0x66, 0},
12495 {0x0B, 0x6, 0},
12496 {0x0C, 0x18, 0},
12497 {0x0D, 0x3, 0},
12498 {0x0E, 0x20, 0},
12499 {0x0F, 0x20, 0},
12500 {0x10, 0, 0},
12501 {0x11, 0x7c, 0},
12502 {0x12, 0x42, 0},
12503 {0x13, 0xbd, 0},
12504 {0x14, 0x7, 0},
12505 {0x15, 0x87, 0},
12506 {0x16, 0x8, 0},
12507 {0x17, 0x17, 0},
12508 {0x18, 0x7, 0},
12509 {0x19, 0, 0},
12510 {0x1A, 0x2, 0},
12511 {0x1B, 0x13, 0},
12512 {0x1C, 0x3e, 0},
12513 {0x1D, 0x3e, 0},
12514 {0x1E, 0x96, 0},
12515 {0x1F, 0x4, 0},
12516 {0x20, 0, 0},
12517 {0x21, 0, 0},
12518 {0x22, 0x17, 0},
12519 {0x23, 0x6, 0},
12520 {0x24, 0x1, 0},
12521 {0x25, 0x6, 0},
12522 {0x26, 0x4, 0},
12523 {0x27, 0xd, 0},
12524 {0x28, 0xd, 0},
12525 {0x29, 0x30, 0},
12526 {0x2A, 0x32, 0},
12527 {0x2B, 0x8, 0},
12528 {0x2C, 0x1c, 0},
12529 {0x2D, 0x2, 0},
12530 {0x2E, 0x4, 0},
12531 {0x2F, 0x7f, 0},
12532 {0x30, 0x27, 0},
12533 {0x31, 0, 1},
12534 {0x32, 0, 1},
12535 {0x33, 0, 1},
12536 {0x34, 0, 0},
12537 {0x35, 0x20, 0},
12538 {0x36, 0x18, 0},
12539 {0x37, 0x7, 0},
12540 {0x38, 0x66, 0},
12541 {0x39, 0x66, 0},
12542 {0x3A, 0x66, 0},
12543 {0x3B, 0x66, 0},
12544 {0x3C, 0xff, 0},
12545 {0x3D, 0xff, 0},
12546 {0x3E, 0xff, 0},
12547 {0x3F, 0xff, 0},
12548 {0x40, 0x16, 0},
12549 {0x41, 0x7, 0},
12550 {0x42, 0x19, 0},
12551 {0x43, 0x7, 0},
12552 {0x44, 0x6, 0},
12553 {0x45, 0x3, 0},
12554 {0x46, 0x1, 0},
12555 {0x47, 0x7, 0},
12556 {0x48, 0x33, 0},
12557 {0x49, 0x5, 0},
12558 {0x4A, 0x77, 0},
12559 {0x4B, 0x66, 0},
12560 {0x4C, 0x66, 0},
12561 {0x4D, 0, 0},
12562 {0x4E, 0x4, 0},
12563 {0x4F, 0xc, 0},
12564 {0x50, 0, 0},
12565 {0x51, 0x70, 1},
12566 {0x56, 0x7, 0},
12567 {0x57, 0, 0},
12568 {0x58, 0, 0},
12569 {0x59, 0x88, 1},
12570 {0x5A, 0, 0},
12571 {0x5B, 0x1f, 0},
12572 {0x5C, 0x20, 1},
12573 {0x5D, 0x1, 0},
12574 {0x5E, 0x30, 0},
12575 {0x5F, 0x70, 0},
12576 {0x60, 0, 0},
12577 {0x61, 0, 0},
12578 {0x62, 0x33, 1},
12579 {0x63, 0xf, 1},
12580 {0x64, 0x13, 1},
12581 {0x65, 0, 0},
12582 {0x66, 0xee, 1},
12583 {0x69, 0, 0},
12584 {0x6A, 0x7e, 0},
12585 {0x6B, 0x3f, 0},
12586 {0x6C, 0x7f, 0},
12587 {0x6D, 0x78, 0},
12588 {0x6E, 0x58, 1},
12589 {0x6F, 0x88, 0},
12590 {0x70, 0x8, 0},
12591 {0x71, 0xf, 0},
12592 {0x72, 0xbc, 0},
12593 {0x73, 0x8, 0},
12594 {0x74, 0x60, 0},
12595 {0x75, 0x13, 1},
12596 {0x76, 0x70, 0},
12597 {0x77, 0, 0},
12598 {0x78, 0, 0},
12599 {0x79, 0, 0},
12600 {0x7A, 0x33, 0},
12601 {0x7B, 0x13, 1},
12602 {0x7C, 0x14, 1},
12603 {0x7D, 0xee, 1},
12604 {0x80, 0x3c, 0},
12605 {0x81, 0x1, 1},
12606 {0x82, 0xa, 0},
12607 {0x83, 0x9d, 0},
12608 {0x84, 0xa, 0},
12609 {0x85, 0, 0},
12610 {0x86, 0x40, 0},
12611 {0x87, 0x40, 0},
12612 {0x88, 0x88, 0},
12613 {0x89, 0x10, 0},
12614 {0x8A, 0xf0, 0},
12615 {0x8B, 0x10, 0},
12616 {0x8C, 0xf0, 0},
12617 {0x8D, 0, 0},
12618 {0x8E, 0, 0},
12619 {0x8F, 0x10, 0},
12620 {0x90, 0x55, 0},
12621 {0x91, 0x3f, 1},
12622 {0x92, 0x36, 1},
12623 {0x93, 0, 0},
12624 {0x94, 0, 0},
12625 {0x95, 0, 0},
12626 {0x96, 0x87, 0},
12627 {0x97, 0x11, 0},
12628 {0x98, 0, 0},
12629 {0x99, 0x33, 0},
12630 {0x9A, 0x88, 0},
12631 {0x9B, 0, 0},
12632 {0x9C, 0x87, 0},
12633 {0x9D, 0x11, 0},
12634 {0x9E, 0, 0},
12635 {0x9F, 0x33, 0},
12636 {0xA0, 0x88, 0},
12637 {0xA1, 0x20, 1},
12638 {0xA2, 0x3f, 0},
12639 {0xA3, 0x44, 0},
12640 {0xA4, 0x8c, 0},
12641 {0xA5, 0x6c, 0},
12642 {0xA6, 0x22, 0},
12643 {0xA7, 0xbe, 0},
12644 {0xA8, 0x55, 0},
12645 {0xAA, 0xc, 0},
12646 {0xAB, 0xaa, 0},
12647 {0xAC, 0x2, 0},
12648 {0xAD, 0, 0},
12649 {0xAE, 0x10, 0},
12650 {0xAF, 0x1, 0},
12651 {0xB0, 0, 0},
12652 {0xB1, 0, 0},
12653 {0xB2, 0x80, 0},
12654 {0xB3, 0x60, 0},
12655 {0xB4, 0x44, 0},
12656 {0xB5, 0x55, 0},
12657 {0xB6, 0x1, 0},
12658 {0xB7, 0x55, 0},
12659 {0xB8, 0x1, 0},
12660 {0xB9, 0x5, 0},
12661 {0xBA, 0x55, 0},
12662 {0xBB, 0x55, 0},
12663 {0xC1, 0, 0},
12664 {0xC2, 0, 0},
12665 {0xC3, 0, 0},
12666 {0xC4, 0, 0},
12667 {0xC5, 0, 0},
12668 {0xC6, 0, 0},
12669 {0xC7, 0, 0},
12670 {0xC8, 0, 0},
12671 {0xC9, 0, 0},
12672 {0xCA, 0, 0},
12673 {0xCB, 0, 0},
12674 {0xCC, 0, 0},
12675 {0xCD, 0, 0},
12676 {0xCE, 0x5e, 0},
12677 {0xCF, 0xc, 0},
12678 {0xD0, 0xc, 0},
12679 {0xD1, 0xc, 0},
12680 {0xD2, 0, 0},
12681 {0xD3, 0x2b, 0},
12682 {0xD4, 0xc, 0},
12683 {0xD5, 0, 0},
12684 {0xD6, 0x70, 1},
12685 {0xDB, 0x7, 0},
12686 {0xDC, 0, 0},
12687 {0xDD, 0, 0},
12688 {0xDE, 0x88, 1},
12689 {0xDF, 0, 0},
12690 {0xE0, 0x1f, 0},
12691 {0xE1, 0x20, 1},
12692 {0xE2, 0x1, 0},
12693 {0xE3, 0x30, 0},
12694 {0xE4, 0x70, 0},
12695 {0xE5, 0, 0},
12696 {0xE6, 0, 0},
12697 {0xE7, 0x33, 0},
12698 {0xE8, 0xf, 1},
12699 {0xE9, 0x13, 1},
12700 {0xEA, 0, 0},
12701 {0xEB, 0xee, 1},
12702 {0xEE, 0, 0},
12703 {0xEF, 0x7e, 0},
12704 {0xF0, 0x3f, 0},
12705 {0xF1, 0x7f, 0},
12706 {0xF2, 0x78, 0},
12707 {0xF3, 0x58, 1},
12708 {0xF4, 0x88, 0},
12709 {0xF5, 0x8, 0},
12710 {0xF6, 0xf, 0},
12711 {0xF7, 0xbc, 0},
12712 {0xF8, 0x8, 0},
12713 {0xF9, 0x60, 0},
12714 {0xFA, 0x13, 1},
12715 {0xFB, 0x70, 0},
12716 {0xFC, 0, 0},
12717 {0xFD, 0, 0},
12718 {0xFE, 0, 0},
12719 {0xFF, 0x33, 0},
12720 {0x100, 0x13, 1},
12721 {0x101, 0x14, 1},
12722 {0x102, 0xee, 1},
12723 {0x105, 0x3c, 0},
12724 {0x106, 0x1, 1},
12725 {0x107, 0xa, 0},
12726 {0x108, 0x9d, 0},
12727 {0x109, 0xa, 0},
12728 {0x10A, 0, 0},
12729 {0x10B, 0x40, 0},
12730 {0x10C, 0x40, 0},
12731 {0x10D, 0x88, 0},
12732 {0x10E, 0x10, 0},
12733 {0x10F, 0xf0, 0},
12734 {0x110, 0x10, 0},
12735 {0x111, 0xf0, 0},
12736 {0x112, 0, 0},
12737 {0x113, 0, 0},
12738 {0x114, 0x10, 0},
12739 {0x115, 0x55, 0},
12740 {0x116, 0x3f, 1},
12741 {0x117, 0x36, 1},
12742 {0x118, 0, 0},
12743 {0x119, 0, 0},
12744 {0x11A, 0, 0},
12745 {0x11B, 0x87, 0},
12746 {0x11C, 0x11, 0},
12747 {0x11D, 0, 0},
12748 {0x11E, 0x33, 0},
12749 {0x11F, 0x88, 0},
12750 {0x120, 0, 0},
12751 {0x121, 0x87, 0},
12752 {0x122, 0x11, 0},
12753 {0x123, 0, 0},
12754 {0x124, 0x33, 0},
12755 {0x125, 0x88, 0},
12756 {0x126, 0x20, 1},
12757 {0x127, 0x3f, 0},
12758 {0x128, 0x44, 0},
12759 {0x129, 0x8c, 0},
12760 {0x12A, 0x6c, 0},
12761 {0x12B, 0x22, 0},
12762 {0x12C, 0xbe, 0},
12763 {0x12D, 0x55, 0},
12764 {0x12F, 0xc, 0},
12765 {0x130, 0xaa, 0},
12766 {0x131, 0x2, 0},
12767 {0x132, 0, 0},
12768 {0x133, 0x10, 0},
12769 {0x134, 0x1, 0},
12770 {0x135, 0, 0},
12771 {0x136, 0, 0},
12772 {0x137, 0x80, 0},
12773 {0x138, 0x60, 0},
12774 {0x139, 0x44, 0},
12775 {0x13A, 0x55, 0},
12776 {0x13B, 0x1, 0},
12777 {0x13C, 0x55, 0},
12778 {0x13D, 0x1, 0},
12779 {0x13E, 0x5, 0},
12780 {0x13F, 0x55, 0},
12781 {0x140, 0x55, 0},
12782 {0x146, 0, 0},
12783 {0x147, 0, 0},
12784 {0x148, 0, 0},
12785 {0x149, 0, 0},
12786 {0x14A, 0, 0},
12787 {0x14B, 0, 0},
12788 {0x14C, 0, 0},
12789 {0x14D, 0, 0},
12790 {0x14E, 0, 0},
12791 {0x14F, 0, 0},
12792 {0x150, 0, 0},
12793 {0x151, 0, 0},
12794 {0x154, 0xc, 0},
12795 {0x155, 0xc, 0},
12796 {0x156, 0xc, 0},
12797 {0x157, 0, 0},
12798 {0x158, 0x2b, 0},
12799 {0x159, 0x84, 0},
12800 {0x15A, 0x15, 0},
12801 {0x15B, 0xf, 0},
12802 {0x15C, 0, 0},
12803 {0x15D, 0, 0},
12804 {0x15E, 0, 1},
12805 {0x15F, 0, 1},
12806 {0x160, 0, 1},
12807 {0x161, 0, 1},
12808 {0x162, 0, 1},
12809 {0x163, 0, 1},
12810 {0x164, 0, 0},
12811 {0x165, 0, 0},
12812 {0x166, 0, 0},
12813 {0x167, 0, 0},
12814 {0x168, 0, 0},
12815 {0x169, 0, 0},
12816 {0x16A, 0, 1},
12817 {0x16B, 0, 1},
12818 {0x16C, 0, 1},
12819 {0x16D, 0, 0},
12820 {0x170, 0, 0},
12821 {0x171, 0x77, 0},
12822 {0x172, 0x77, 0},
12823 {0x173, 0x77, 0},
12824 {0x174, 0x77, 0},
12825 {0x175, 0, 0},
12826 {0x176, 0x3, 0},
12827 {0x177, 0x37, 0},
12828 {0x178, 0x3, 0},
12829 {0x179, 0, 0},
12830 {0x17A, 0x21, 0},
12831 {0x17B, 0x21, 0},
12832 {0x17C, 0, 0},
12833 {0x17D, 0xaa, 0},
12834 {0x17E, 0, 0},
12835 {0x17F, 0xaa, 0},
12836 {0x180, 0, 0},
12837 {0x190, 0, 0},
12838 {0x191, 0x77, 0},
12839 {0x192, 0x77, 0},
12840 {0x193, 0x77, 0},
12841 {0x194, 0x77, 0},
12842 {0x195, 0, 0},
12843 {0x196, 0x3, 0},
12844 {0x197, 0x37, 0},
12845 {0x198, 0x3, 0},
12846 {0x199, 0, 0},
12847 {0x19A, 0x21, 0},
12848 {0x19B, 0x21, 0},
12849 {0x19C, 0, 0},
12850 {0x19D, 0xaa, 0},
12851 {0x19E, 0, 0},
12852 {0x19F, 0xaa, 0},
12853 {0x1A0, 0, 0},
12854 {0x1A1, 0x2, 0},
12855 {0x1A2, 0xf, 0},
12856 {0x1A3, 0xf, 0},
12857 {0x1A4, 0, 1},
12858 {0x1A5, 0, 1},
12859 {0x1A6, 0, 1},
12860 {0x1A7, 0x2, 0},
12861 {0x1A8, 0xf, 0},
12862 {0x1A9, 0xf, 0},
12863 {0x1AA, 0, 1},
12864 {0x1AB, 0, 1},
12865 {0x1AC, 0, 1},
12866 {0x1AD, 0x84, 0},
12867 {0x1AE, 0x60, 0},
12868 {0x1AF, 0x47, 0},
12869 {0x1B0, 0x47, 0},
12870 {0x1B1, 0, 0},
12871 {0x1B2, 0, 0},
12872 {0x1B3, 0, 0},
12873 {0x1B4, 0, 0},
12874 {0x1B5, 0, 0},
12875 {0x1B6, 0, 0},
12876 {0x1B7, 0x5, 1},
12877 {0x1B8, 0, 0},
12878 {0x1B9, 0, 0},
12879 {0x1BA, 0, 0},
12880 {0x1BB, 0, 0},
12881 {0x1BC, 0, 0},
12882 {0x1BD, 0, 0},
12883 {0x1BE, 0, 0},
12884 {0x1BF, 0, 0},
12885 {0x1C0, 0, 0},
12886 {0x1C1, 0, 0},
12887 {0x1C2, 0xa0, 1},
12888 {0x1C3, 0, 0},
12889 {0x1C4, 0, 0},
12890 {0x1C5, 0, 0},
12891 {0x1C6, 0, 0},
12892 {0x1C7, 0, 0},
12893 {0x1C8, 0, 0},
12894 {0x1C9, 0, 0},
12895 {0x1CA, 0, 0},
12896 {0xFFFF, 0, 0}
12897};
12898
12899static struct radio_20xx_regs regs_2057_rev8[] = {
12900 {0x00, 0x8, 1},
12901 {0x01, 0x57, 1},
12902 {0x02, 0x20, 1},
12903 {0x03, 0x1f, 0},
12904 {0x04, 0x4, 0},
12905 {0x05, 0x2, 0},
12906 {0x06, 0x1, 0},
12907 {0x07, 0x1, 0},
12908 {0x08, 0x1, 0},
12909 {0x09, 0x69, 0},
12910 {0x0A, 0x66, 0},
12911 {0x0B, 0x6, 0},
12912 {0x0C, 0x18, 0},
12913 {0x0D, 0x3, 0},
12914 {0x0E, 0x20, 0},
12915 {0x0F, 0x20, 0},
12916 {0x10, 0, 0},
12917 {0x11, 0x7c, 0},
12918 {0x12, 0x42, 0},
12919 {0x13, 0xbd, 0},
12920 {0x14, 0x7, 0},
12921 {0x15, 0x87, 0},
12922 {0x16, 0x8, 0},
12923 {0x17, 0x17, 0},
12924 {0x18, 0x7, 0},
12925 {0x19, 0, 0},
12926 {0x1A, 0x2, 0},
12927 {0x1B, 0x13, 0},
12928 {0x1C, 0x3e, 0},
12929 {0x1D, 0x3e, 0},
12930 {0x1E, 0x96, 0},
12931 {0x1F, 0x4, 0},
12932 {0x20, 0, 0},
12933 {0x21, 0, 0},
12934 {0x22, 0x17, 0},
12935 {0x23, 0x6, 0},
12936 {0x24, 0x1, 0},
12937 {0x25, 0x6, 0},
12938 {0x26, 0x4, 0},
12939 {0x27, 0xd, 0},
12940 {0x28, 0xd, 0},
12941 {0x29, 0x30, 0},
12942 {0x2A, 0x32, 0},
12943 {0x2B, 0x8, 0},
12944 {0x2C, 0x1c, 0},
12945 {0x2D, 0x2, 0},
12946 {0x2E, 0x4, 0},
12947 {0x2F, 0x7f, 0},
12948 {0x30, 0x27, 0},
12949 {0x31, 0, 1},
12950 {0x32, 0, 1},
12951 {0x33, 0, 1},
12952 {0x34, 0, 0},
12953 {0x35, 0x20, 0},
12954 {0x36, 0x18, 0},
12955 {0x37, 0x7, 0},
12956 {0x38, 0x66, 0},
12957 {0x39, 0x66, 0},
12958 {0x3A, 0x66, 0},
12959 {0x3B, 0x66, 0},
12960 {0x3C, 0xff, 0},
12961 {0x3D, 0xff, 0},
12962 {0x3E, 0xff, 0},
12963 {0x3F, 0xff, 0},
12964 {0x40, 0x16, 0},
12965 {0x41, 0x7, 0},
12966 {0x42, 0x19, 0},
12967 {0x43, 0x7, 0},
12968 {0x44, 0x6, 0},
12969 {0x45, 0x3, 0},
12970 {0x46, 0x1, 0},
12971 {0x47, 0x7, 0},
12972 {0x48, 0x33, 0},
12973 {0x49, 0x5, 0},
12974 {0x4A, 0x77, 0},
12975 {0x4B, 0x66, 0},
12976 {0x4C, 0x66, 0},
12977 {0x4D, 0, 0},
12978 {0x4E, 0x4, 0},
12979 {0x4F, 0xc, 0},
12980 {0x50, 0, 0},
12981 {0x51, 0x70, 1},
12982 {0x56, 0x7, 0},
12983 {0x57, 0, 0},
12984 {0x58, 0, 0},
12985 {0x59, 0x88, 1},
12986 {0x5A, 0, 0},
12987 {0x5B, 0x1f, 0},
12988 {0x5C, 0x20, 1},
12989 {0x5D, 0x1, 0},
12990 {0x5E, 0x30, 0},
12991 {0x5F, 0x70, 0},
12992 {0x60, 0, 0},
12993 {0x61, 0, 0},
12994 {0x62, 0x33, 1},
12995 {0x63, 0xf, 1},
12996 {0x64, 0xf, 1},
12997 {0x65, 0, 0},
12998 {0x66, 0x11, 0},
12999 {0x69, 0, 0},
13000 {0x6A, 0x7e, 0},
13001 {0x6B, 0x3f, 0},
13002 {0x6C, 0x7f, 0},
13003 {0x6D, 0x78, 0},
13004 {0x6E, 0x58, 1},
13005 {0x6F, 0x88, 0},
13006 {0x70, 0x8, 0},
13007 {0x71, 0xf, 0},
13008 {0x72, 0xbc, 0},
13009 {0x73, 0x8, 0},
13010 {0x74, 0x60, 0},
13011 {0x75, 0x13, 1},
13012 {0x76, 0x70, 0},
13013 {0x77, 0, 0},
13014 {0x78, 0, 0},
13015 {0x79, 0, 0},
13016 {0x7A, 0x33, 0},
13017 {0x7B, 0x13, 1},
13018 {0x7C, 0xf, 1},
13019 {0x7D, 0xee, 1},
13020 {0x80, 0x3c, 0},
13021 {0x81, 0x1, 1},
13022 {0x82, 0xa, 0},
13023 {0x83, 0x9d, 0},
13024 {0x84, 0xa, 0},
13025 {0x85, 0, 0},
13026 {0x86, 0x40, 0},
13027 {0x87, 0x40, 0},
13028 {0x88, 0x88, 0},
13029 {0x89, 0x10, 0},
13030 {0x8A, 0xf0, 0},
13031 {0x8B, 0x10, 0},
13032 {0x8C, 0xf0, 0},
13033 {0x8D, 0, 0},
13034 {0x8E, 0, 0},
13035 {0x8F, 0x10, 0},
13036 {0x90, 0x55, 0},
13037 {0x91, 0x3f, 1},
13038 {0x92, 0x36, 1},
13039 {0x93, 0, 0},
13040 {0x94, 0, 0},
13041 {0x95, 0, 0},
13042 {0x96, 0x87, 0},
13043 {0x97, 0x11, 0},
13044 {0x98, 0, 0},
13045 {0x99, 0x33, 0},
13046 {0x9A, 0x88, 0},
13047 {0x9B, 0, 0},
13048 {0x9C, 0x87, 0},
13049 {0x9D, 0x11, 0},
13050 {0x9E, 0, 0},
13051 {0x9F, 0x33, 0},
13052 {0xA0, 0x88, 0},
13053 {0xA1, 0x20, 1},
13054 {0xA2, 0x3f, 0},
13055 {0xA3, 0x44, 0},
13056 {0xA4, 0x8c, 0},
13057 {0xA5, 0x6c, 0},
13058 {0xA6, 0x22, 0},
13059 {0xA7, 0xbe, 0},
13060 {0xA8, 0x55, 0},
13061 {0xAA, 0xc, 0},
13062 {0xAB, 0xaa, 0},
13063 {0xAC, 0x2, 0},
13064 {0xAD, 0, 0},
13065 {0xAE, 0x10, 0},
13066 {0xAF, 0x1, 0},
13067 {0xB0, 0, 0},
13068 {0xB1, 0, 0},
13069 {0xB2, 0x80, 0},
13070 {0xB3, 0x60, 0},
13071 {0xB4, 0x44, 0},
13072 {0xB5, 0x55, 0},
13073 {0xB6, 0x1, 0},
13074 {0xB7, 0x55, 0},
13075 {0xB8, 0x1, 0},
13076 {0xB9, 0x5, 0},
13077 {0xBA, 0x55, 0},
13078 {0xBB, 0x55, 0},
13079 {0xC1, 0, 0},
13080 {0xC2, 0, 0},
13081 {0xC3, 0, 0},
13082 {0xC4, 0, 0},
13083 {0xC5, 0, 0},
13084 {0xC6, 0, 0},
13085 {0xC7, 0, 0},
13086 {0xC8, 0, 0},
13087 {0xC9, 0x1, 1},
13088 {0xCA, 0, 0},
13089 {0xCB, 0, 0},
13090 {0xCC, 0, 0},
13091 {0xCD, 0, 0},
13092 {0xCE, 0x5e, 0},
13093 {0xCF, 0xc, 0},
13094 {0xD0, 0xc, 0},
13095 {0xD1, 0xc, 0},
13096 {0xD2, 0, 0},
13097 {0xD3, 0x2b, 0},
13098 {0xD4, 0xc, 0},
13099 {0xD5, 0, 0},
13100 {0xD6, 0x70, 1},
13101 {0xDB, 0x7, 0},
13102 {0xDC, 0, 0},
13103 {0xDD, 0, 0},
13104 {0xDE, 0x88, 1},
13105 {0xDF, 0, 0},
13106 {0xE0, 0x1f, 0},
13107 {0xE1, 0x20, 1},
13108 {0xE2, 0x1, 0},
13109 {0xE3, 0x30, 0},
13110 {0xE4, 0x70, 0},
13111 {0xE5, 0, 0},
13112 {0xE6, 0, 0},
13113 {0xE7, 0x33, 0},
13114 {0xE8, 0xf, 1},
13115 {0xE9, 0xf, 1},
13116 {0xEA, 0, 0},
13117 {0xEB, 0x11, 0},
13118 {0xEE, 0, 0},
13119 {0xEF, 0x7e, 0},
13120 {0xF0, 0x3f, 0},
13121 {0xF1, 0x7f, 0},
13122 {0xF2, 0x78, 0},
13123 {0xF3, 0x58, 1},
13124 {0xF4, 0x88, 0},
13125 {0xF5, 0x8, 0},
13126 {0xF6, 0xf, 0},
13127 {0xF7, 0xbc, 0},
13128 {0xF8, 0x8, 0},
13129 {0xF9, 0x60, 0},
13130 {0xFA, 0x13, 1},
13131 {0xFB, 0x70, 0},
13132 {0xFC, 0, 0},
13133 {0xFD, 0, 0},
13134 {0xFE, 0, 0},
13135 {0xFF, 0x33, 0},
13136 {0x100, 0x13, 1},
13137 {0x101, 0xf, 1},
13138 {0x102, 0xee, 1},
13139 {0x105, 0x3c, 0},
13140 {0x106, 0x1, 1},
13141 {0x107, 0xa, 0},
13142 {0x108, 0x9d, 0},
13143 {0x109, 0xa, 0},
13144 {0x10A, 0, 0},
13145 {0x10B, 0x40, 0},
13146 {0x10C, 0x40, 0},
13147 {0x10D, 0x88, 0},
13148 {0x10E, 0x10, 0},
13149 {0x10F, 0xf0, 0},
13150 {0x110, 0x10, 0},
13151 {0x111, 0xf0, 0},
13152 {0x112, 0, 0},
13153 {0x113, 0, 0},
13154 {0x114, 0x10, 0},
13155 {0x115, 0x55, 0},
13156 {0x116, 0x3f, 1},
13157 {0x117, 0x36, 1},
13158 {0x118, 0, 0},
13159 {0x119, 0, 0},
13160 {0x11A, 0, 0},
13161 {0x11B, 0x87, 0},
13162 {0x11C, 0x11, 0},
13163 {0x11D, 0, 0},
13164 {0x11E, 0x33, 0},
13165 {0x11F, 0x88, 0},
13166 {0x120, 0, 0},
13167 {0x121, 0x87, 0},
13168 {0x122, 0x11, 0},
13169 {0x123, 0, 0},
13170 {0x124, 0x33, 0},
13171 {0x125, 0x88, 0},
13172 {0x126, 0x20, 1},
13173 {0x127, 0x3f, 0},
13174 {0x128, 0x44, 0},
13175 {0x129, 0x8c, 0},
13176 {0x12A, 0x6c, 0},
13177 {0x12B, 0x22, 0},
13178 {0x12C, 0xbe, 0},
13179 {0x12D, 0x55, 0},
13180 {0x12F, 0xc, 0},
13181 {0x130, 0xaa, 0},
13182 {0x131, 0x2, 0},
13183 {0x132, 0, 0},
13184 {0x133, 0x10, 0},
13185 {0x134, 0x1, 0},
13186 {0x135, 0, 0},
13187 {0x136, 0, 0},
13188 {0x137, 0x80, 0},
13189 {0x138, 0x60, 0},
13190 {0x139, 0x44, 0},
13191 {0x13A, 0x55, 0},
13192 {0x13B, 0x1, 0},
13193 {0x13C, 0x55, 0},
13194 {0x13D, 0x1, 0},
13195 {0x13E, 0x5, 0},
13196 {0x13F, 0x55, 0},
13197 {0x140, 0x55, 0},
13198 {0x146, 0, 0},
13199 {0x147, 0, 0},
13200 {0x148, 0, 0},
13201 {0x149, 0, 0},
13202 {0x14A, 0, 0},
13203 {0x14B, 0, 0},
13204 {0x14C, 0, 0},
13205 {0x14D, 0, 0},
13206 {0x14E, 0x1, 1},
13207 {0x14F, 0, 0},
13208 {0x150, 0, 0},
13209 {0x151, 0, 0},
13210 {0x154, 0xc, 0},
13211 {0x155, 0xc, 0},
13212 {0x156, 0xc, 0},
13213 {0x157, 0, 0},
13214 {0x158, 0x2b, 0},
13215 {0x159, 0x84, 0},
13216 {0x15A, 0x15, 0},
13217 {0x15B, 0xf, 0},
13218 {0x15C, 0, 0},
13219 {0x15D, 0, 0},
13220 {0x15E, 0, 1},
13221 {0x15F, 0, 1},
13222 {0x160, 0, 1},
13223 {0x161, 0, 1},
13224 {0x162, 0, 1},
13225 {0x163, 0, 1},
13226 {0x164, 0, 0},
13227 {0x165, 0, 0},
13228 {0x166, 0, 0},
13229 {0x167, 0, 0},
13230 {0x168, 0, 0},
13231 {0x169, 0, 0},
13232 {0x16A, 0, 1},
13233 {0x16B, 0, 1},
13234 {0x16C, 0, 1},
13235 {0x16D, 0, 0},
13236 {0x170, 0, 0},
13237 {0x171, 0x77, 0},
13238 {0x172, 0x77, 0},
13239 {0x173, 0x77, 0},
13240 {0x174, 0x77, 0},
13241 {0x175, 0, 0},
13242 {0x176, 0x3, 0},
13243 {0x177, 0x37, 0},
13244 {0x178, 0x3, 0},
13245 {0x179, 0, 0},
13246 {0x17A, 0x21, 0},
13247 {0x17B, 0x21, 0},
13248 {0x17C, 0, 0},
13249 {0x17D, 0xaa, 0},
13250 {0x17E, 0, 0},
13251 {0x17F, 0xaa, 0},
13252 {0x180, 0, 0},
13253 {0x190, 0, 0},
13254 {0x191, 0x77, 0},
13255 {0x192, 0x77, 0},
13256 {0x193, 0x77, 0},
13257 {0x194, 0x77, 0},
13258 {0x195, 0, 0},
13259 {0x196, 0x3, 0},
13260 {0x197, 0x37, 0},
13261 {0x198, 0x3, 0},
13262 {0x199, 0, 0},
13263 {0x19A, 0x21, 0},
13264 {0x19B, 0x21, 0},
13265 {0x19C, 0, 0},
13266 {0x19D, 0xaa, 0},
13267 {0x19E, 0, 0},
13268 {0x19F, 0xaa, 0},
13269 {0x1A0, 0, 0},
13270 {0x1A1, 0x2, 0},
13271 {0x1A2, 0xf, 0},
13272 {0x1A3, 0xf, 0},
13273 {0x1A4, 0, 1},
13274 {0x1A5, 0, 1},
13275 {0x1A6, 0, 1},
13276 {0x1A7, 0x2, 0},
13277 {0x1A8, 0xf, 0},
13278 {0x1A9, 0xf, 0},
13279 {0x1AA, 0, 1},
13280 {0x1AB, 0, 1},
13281 {0x1AC, 0, 1},
13282 {0x1AD, 0x84, 0},
13283 {0x1AE, 0x60, 0},
13284 {0x1AF, 0x47, 0},
13285 {0x1B0, 0x47, 0},
13286 {0x1B1, 0, 0},
13287 {0x1B2, 0, 0},
13288 {0x1B3, 0, 0},
13289 {0x1B4, 0, 0},
13290 {0x1B5, 0, 0},
13291 {0x1B6, 0, 0},
13292 {0x1B7, 0x5, 1},
13293 {0x1B8, 0, 0},
13294 {0x1B9, 0, 0},
13295 {0x1BA, 0, 0},
13296 {0x1BB, 0, 0},
13297 {0x1BC, 0, 0},
13298 {0x1BD, 0, 0},
13299 {0x1BE, 0, 0},
13300 {0x1BF, 0, 0},
13301 {0x1C0, 0, 0},
13302 {0x1C1, 0, 0},
13303 {0x1C2, 0xa0, 1},
13304 {0x1C3, 0, 0},
13305 {0x1C4, 0, 0},
13306 {0x1C5, 0, 0},
13307 {0x1C6, 0, 0},
13308 {0x1C7, 0, 0},
13309 {0x1C8, 0, 0},
13310 {0x1C9, 0, 0},
13311 {0x1CA, 0, 0},
13312 {0xFFFF, 0, 0}
13313};
13314
13315static s16 nphy_def_lnagains[] = { -2, 10, 19, 25 };
13316
13317static s32 nphy_lnagain_est0[] = { -315, 40370 };
13318static s32 nphy_lnagain_est1[] = { -224, 23242 };
13319
13320static const u16 tbl_iqcal_gainparams_nphy[2][NPHY_IQCAL_NUMGAINS][8] = {
13321 {
13322 {0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69},
13323 {0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69},
13324 {0x710, 7, 1, 0, 0x68, 0x68, 0x68, 0x68},
13325 {0x720, 7, 2, 0, 0x67, 0x67, 0x67, 0x67},
13326 {0x730, 7, 3, 0, 0x66, 0x66, 0x66, 0x66},
13327 {0x740, 7, 4, 0, 0x65, 0x65, 0x65, 0x65},
13328 {0x741, 7, 4, 1, 0x65, 0x65, 0x65, 0x65},
13329 {0x742, 7, 4, 2, 0x65, 0x65, 0x65, 0x65},
13330 {0x743, 7, 4, 3, 0x65, 0x65, 0x65, 0x65}
13331 },
13332 {
13333 {0x000, 7, 0, 0, 0x79, 0x79, 0x79, 0x79},
13334 {0x700, 7, 0, 0, 0x79, 0x79, 0x79, 0x79},
13335 {0x710, 7, 1, 0, 0x79, 0x79, 0x79, 0x79},
13336 {0x720, 7, 2, 0, 0x78, 0x78, 0x78, 0x78},
13337 {0x730, 7, 3, 0, 0x78, 0x78, 0x78, 0x78},
13338 {0x740, 7, 4, 0, 0x78, 0x78, 0x78, 0x78},
13339 {0x741, 7, 4, 1, 0x78, 0x78, 0x78, 0x78},
13340 {0x742, 7, 4, 2, 0x78, 0x78, 0x78, 0x78},
13341 {0x743, 7, 4, 3, 0x78, 0x78, 0x78, 0x78}
13342 }
13343};
13344
13345static const u32 nphy_tpc_txgain[] = {
13346 0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42,
13347 0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44,
13348 0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844,
13349 0x03c82842, 0x03c42b44, 0x03c42b42, 0x03c42a44,
13350 0x03c42a42, 0x03c42944, 0x03c42942, 0x03c42844,
13351 0x03c42842, 0x03c42744, 0x03c42742, 0x03c42644,
13352 0x03c42642, 0x03c42544, 0x03c42542, 0x03c42444,
13353 0x03c42442, 0x03c02b44, 0x03c02b42, 0x03c02a44,
13354 0x03c02a42, 0x03c02944, 0x03c02942, 0x03c02844,
13355 0x03c02842, 0x03c02744, 0x03c02742, 0x03b02b44,
13356 0x03b02b42, 0x03b02a44, 0x03b02a42, 0x03b02944,
13357 0x03b02942, 0x03b02844, 0x03b02842, 0x03b02744,
13358 0x03b02742, 0x03b02644, 0x03b02642, 0x03b02544,
13359 0x03b02542, 0x03a02b44, 0x03a02b42, 0x03a02a44,
13360 0x03a02a42, 0x03a02944, 0x03a02942, 0x03a02844,
13361 0x03a02842, 0x03a02744, 0x03a02742, 0x03902b44,
13362 0x03902b42, 0x03902a44, 0x03902a42, 0x03902944,
13363 0x03902942, 0x03902844, 0x03902842, 0x03902744,
13364 0x03902742, 0x03902644, 0x03902642, 0x03902544,
13365 0x03902542, 0x03802b44, 0x03802b42, 0x03802a44,
13366 0x03802a42, 0x03802944, 0x03802942, 0x03802844,
13367 0x03802842, 0x03802744, 0x03802742, 0x03802644,
13368 0x03802642, 0x03802544, 0x03802542, 0x03802444,
13369 0x03802442, 0x03802344, 0x03802342, 0x03802244,
13370 0x03802242, 0x03802144, 0x03802142, 0x03802044,
13371 0x03802042, 0x03801f44, 0x03801f42, 0x03801e44,
13372 0x03801e42, 0x03801d44, 0x03801d42, 0x03801c44,
13373 0x03801c42, 0x03801b44, 0x03801b42, 0x03801a44,
13374 0x03801a42, 0x03801944, 0x03801942, 0x03801844,
13375 0x03801842, 0x03801744, 0x03801742, 0x03801644,
13376 0x03801642, 0x03801544, 0x03801542, 0x03801444,
13377 0x03801442, 0x03801344, 0x03801342, 0x00002b00
13378};
13379
13380static const u16 nphy_tpc_loscale[] = {
13381 256, 256, 271, 271, 287, 256, 256, 271,
13382 271, 287, 287, 304, 304, 256, 256, 271,
13383 271, 287, 287, 304, 304, 322, 322, 341,
13384 341, 362, 362, 383, 383, 256, 256, 271,
13385 271, 287, 287, 304, 304, 322, 322, 256,
13386 256, 271, 271, 287, 287, 304, 304, 322,
13387 322, 341, 341, 362, 362, 256, 256, 271,
13388 271, 287, 287, 304, 304, 322, 322, 256,
13389 256, 271, 271, 287, 287, 304, 304, 322,
13390 322, 341, 341, 362, 362, 256, 256, 271,
13391 271, 287, 287, 304, 304, 322, 322, 341,
13392 341, 362, 362, 383, 383, 406, 406, 430,
13393 430, 455, 455, 482, 482, 511, 511, 541,
13394 541, 573, 573, 607, 607, 643, 643, 681,
13395 681, 722, 722, 764, 764, 810, 810, 858,
13396 858, 908, 908, 962, 962, 1019, 1019, 256
13397};
13398
13399static u32 nphy_tpc_txgain_ipa[] = {
13400 0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029,
13401 0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025,
13402 0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029,
13403 0x5ef70028, 0x5ef70027, 0x5ef70026, 0x5ef70025,
13404 0x5df7002d, 0x5df7002b, 0x5df7002a, 0x5df70029,
13405 0x5df70028, 0x5df70027, 0x5df70026, 0x5df70025,
13406 0x5cf7002d, 0x5cf7002b, 0x5cf7002a, 0x5cf70029,
13407 0x5cf70028, 0x5cf70027, 0x5cf70026, 0x5cf70025,
13408 0x5bf7002d, 0x5bf7002b, 0x5bf7002a, 0x5bf70029,
13409 0x5bf70028, 0x5bf70027, 0x5bf70026, 0x5bf70025,
13410 0x5af7002d, 0x5af7002b, 0x5af7002a, 0x5af70029,
13411 0x5af70028, 0x5af70027, 0x5af70026, 0x5af70025,
13412 0x59f7002d, 0x59f7002b, 0x59f7002a, 0x59f70029,
13413 0x59f70028, 0x59f70027, 0x59f70026, 0x59f70025,
13414 0x58f7002d, 0x58f7002b, 0x58f7002a, 0x58f70029,
13415 0x58f70028, 0x58f70027, 0x58f70026, 0x58f70025,
13416 0x57f7002d, 0x57f7002b, 0x57f7002a, 0x57f70029,
13417 0x57f70028, 0x57f70027, 0x57f70026, 0x57f70025,
13418 0x56f7002d, 0x56f7002b, 0x56f7002a, 0x56f70029,
13419 0x56f70028, 0x56f70027, 0x56f70026, 0x56f70025,
13420 0x55f7002d, 0x55f7002b, 0x55f7002a, 0x55f70029,
13421 0x55f70028, 0x55f70027, 0x55f70026, 0x55f70025,
13422 0x54f7002d, 0x54f7002b, 0x54f7002a, 0x54f70029,
13423 0x54f70028, 0x54f70027, 0x54f70026, 0x54f70025,
13424 0x53f7002d, 0x53f7002b, 0x53f7002a, 0x53f70029,
13425 0x53f70028, 0x53f70027, 0x53f70026, 0x53f70025,
13426 0x52f7002d, 0x52f7002b, 0x52f7002a, 0x52f70029,
13427 0x52f70028, 0x52f70027, 0x52f70026, 0x52f70025,
13428 0x51f7002d, 0x51f7002b, 0x51f7002a, 0x51f70029,
13429 0x51f70028, 0x51f70027, 0x51f70026, 0x51f70025,
13430 0x50f7002d, 0x50f7002b, 0x50f7002a, 0x50f70029,
13431 0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025
13432};
13433
13434static u32 nphy_tpc_txgain_ipa_rev5[] = {
13435 0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029,
13436 0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025,
13437 0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029,
13438 0x1ef70028, 0x1ef70027, 0x1ef70026, 0x1ef70025,
13439 0x1df7002d, 0x1df7002b, 0x1df7002a, 0x1df70029,
13440 0x1df70028, 0x1df70027, 0x1df70026, 0x1df70025,
13441 0x1cf7002d, 0x1cf7002b, 0x1cf7002a, 0x1cf70029,
13442 0x1cf70028, 0x1cf70027, 0x1cf70026, 0x1cf70025,
13443 0x1bf7002d, 0x1bf7002b, 0x1bf7002a, 0x1bf70029,
13444 0x1bf70028, 0x1bf70027, 0x1bf70026, 0x1bf70025,
13445 0x1af7002d, 0x1af7002b, 0x1af7002a, 0x1af70029,
13446 0x1af70028, 0x1af70027, 0x1af70026, 0x1af70025,
13447 0x19f7002d, 0x19f7002b, 0x19f7002a, 0x19f70029,
13448 0x19f70028, 0x19f70027, 0x19f70026, 0x19f70025,
13449 0x18f7002d, 0x18f7002b, 0x18f7002a, 0x18f70029,
13450 0x18f70028, 0x18f70027, 0x18f70026, 0x18f70025,
13451 0x17f7002d, 0x17f7002b, 0x17f7002a, 0x17f70029,
13452 0x17f70028, 0x17f70027, 0x17f70026, 0x17f70025,
13453 0x16f7002d, 0x16f7002b, 0x16f7002a, 0x16f70029,
13454 0x16f70028, 0x16f70027, 0x16f70026, 0x16f70025,
13455 0x15f7002d, 0x15f7002b, 0x15f7002a, 0x15f70029,
13456 0x15f70028, 0x15f70027, 0x15f70026, 0x15f70025,
13457 0x14f7002d, 0x14f7002b, 0x14f7002a, 0x14f70029,
13458 0x14f70028, 0x14f70027, 0x14f70026, 0x14f70025,
13459 0x13f7002d, 0x13f7002b, 0x13f7002a, 0x13f70029,
13460 0x13f70028, 0x13f70027, 0x13f70026, 0x13f70025,
13461 0x12f7002d, 0x12f7002b, 0x12f7002a, 0x12f70029,
13462 0x12f70028, 0x12f70027, 0x12f70026, 0x12f70025,
13463 0x11f7002d, 0x11f7002b, 0x11f7002a, 0x11f70029,
13464 0x11f70028, 0x11f70027, 0x11f70026, 0x11f70025,
13465 0x10f7002d, 0x10f7002b, 0x10f7002a, 0x10f70029,
13466 0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025
13467};
13468
13469static u32 nphy_tpc_txgain_ipa_rev6[] = {
13470 0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029,
13471 0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025,
13472 0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029,
13473 0x0ef70028, 0x0ef70027, 0x0ef70026, 0x0ef70025,
13474 0x0df7002d, 0x0df7002b, 0x0df7002a, 0x0df70029,
13475 0x0df70028, 0x0df70027, 0x0df70026, 0x0df70025,
13476 0x0cf7002d, 0x0cf7002b, 0x0cf7002a, 0x0cf70029,
13477 0x0cf70028, 0x0cf70027, 0x0cf70026, 0x0cf70025,
13478 0x0bf7002d, 0x0bf7002b, 0x0bf7002a, 0x0bf70029,
13479 0x0bf70028, 0x0bf70027, 0x0bf70026, 0x0bf70025,
13480 0x0af7002d, 0x0af7002b, 0x0af7002a, 0x0af70029,
13481 0x0af70028, 0x0af70027, 0x0af70026, 0x0af70025,
13482 0x09f7002d, 0x09f7002b, 0x09f7002a, 0x09f70029,
13483 0x09f70028, 0x09f70027, 0x09f70026, 0x09f70025,
13484 0x08f7002d, 0x08f7002b, 0x08f7002a, 0x08f70029,
13485 0x08f70028, 0x08f70027, 0x08f70026, 0x08f70025,
13486 0x07f7002d, 0x07f7002b, 0x07f7002a, 0x07f70029,
13487 0x07f70028, 0x07f70027, 0x07f70026, 0x07f70025,
13488 0x06f7002d, 0x06f7002b, 0x06f7002a, 0x06f70029,
13489 0x06f70028, 0x06f70027, 0x06f70026, 0x06f70025,
13490 0x05f7002d, 0x05f7002b, 0x05f7002a, 0x05f70029,
13491 0x05f70028, 0x05f70027, 0x05f70026, 0x05f70025,
13492 0x04f7002d, 0x04f7002b, 0x04f7002a, 0x04f70029,
13493 0x04f70028, 0x04f70027, 0x04f70026, 0x04f70025,
13494 0x03f7002d, 0x03f7002b, 0x03f7002a, 0x03f70029,
13495 0x03f70028, 0x03f70027, 0x03f70026, 0x03f70025,
13496 0x02f7002d, 0x02f7002b, 0x02f7002a, 0x02f70029,
13497 0x02f70028, 0x02f70027, 0x02f70026, 0x02f70025,
13498 0x01f7002d, 0x01f7002b, 0x01f7002a, 0x01f70029,
13499 0x01f70028, 0x01f70027, 0x01f70026, 0x01f70025,
13500 0x00f7002d, 0x00f7002b, 0x00f7002a, 0x00f70029,
13501 0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025
13502};
13503
13504static u32 nphy_tpc_txgain_ipa_2g_2057rev3[] = {
13505 0x70ff0040, 0x70f7003e, 0x70ef003b, 0x70e70039,
13506 0x70df0037, 0x70d70036, 0x70cf0033, 0x70c70032,
13507 0x70bf0031, 0x70b7002f, 0x70af002e, 0x70a7002d,
13508 0x709f002d, 0x7097002c, 0x708f002c, 0x7087002c,
13509 0x707f002b, 0x7077002c, 0x706f002c, 0x7067002d,
13510 0x705f002e, 0x705f002b, 0x705f0029, 0x7057002a,
13511 0x70570028, 0x704f002a, 0x7047002c, 0x7047002a,
13512 0x70470028, 0x70470026, 0x70470024, 0x70470022,
13513 0x7047001f, 0x70370027, 0x70370024, 0x70370022,
13514 0x70370020, 0x7037001f, 0x7037001d, 0x7037001b,
13515 0x7037001a, 0x70370018, 0x70370017, 0x7027001e,
13516 0x7027001d, 0x7027001a, 0x701f0024, 0x701f0022,
13517 0x701f0020, 0x701f001f, 0x701f001d, 0x701f001b,
13518 0x701f001a, 0x701f0018, 0x701f0017, 0x701f0015,
13519 0x701f0014, 0x701f0013, 0x701f0012, 0x701f0011,
13520 0x70170019, 0x70170018, 0x70170016, 0x70170015,
13521 0x70170014, 0x70170013, 0x70170012, 0x70170010,
13522 0x70170010, 0x7017000f, 0x700f001d, 0x700f001b,
13523 0x700f001a, 0x700f0018, 0x700f0017, 0x700f0015,
13524 0x700f0015, 0x700f0013, 0x700f0013, 0x700f0011,
13525 0x700f0010, 0x700f0010, 0x700f000f, 0x700f000e,
13526 0x700f000d, 0x700f000c, 0x700f000b, 0x700f000b,
13527 0x700f000b, 0x700f000a, 0x700f0009, 0x700f0009,
13528 0x700f0009, 0x700f0008, 0x700f0007, 0x700f0007,
13529 0x700f0006, 0x700f0006, 0x700f0006, 0x700f0006,
13530 0x700f0005, 0x700f0005, 0x700f0005, 0x700f0004,
13531 0x700f0004, 0x700f0004, 0x700f0004, 0x700f0004,
13532 0x700f0004, 0x700f0003, 0x700f0003, 0x700f0003,
13533 0x700f0003, 0x700f0002, 0x700f0002, 0x700f0002,
13534 0x700f0002, 0x700f0002, 0x700f0002, 0x700f0001,
13535 0x700f0001, 0x700f0001, 0x700f0001, 0x700f0001,
13536 0x700f0001, 0x700f0001, 0x700f0001, 0x700f0001
13537};
13538
13539static u32 nphy_tpc_txgain_ipa_2g_2057rev4n6[] = {
13540 0xf0ff0040, 0xf0f7003e, 0xf0ef003b, 0xf0e70039,
13541 0xf0df0037, 0xf0d70036, 0xf0cf0033, 0xf0c70032,
13542 0xf0bf0031, 0xf0b7002f, 0xf0af002e, 0xf0a7002d,
13543 0xf09f002d, 0xf097002c, 0xf08f002c, 0xf087002c,
13544 0xf07f002b, 0xf077002c, 0xf06f002c, 0xf067002d,
13545 0xf05f002e, 0xf05f002b, 0xf05f0029, 0xf057002a,
13546 0xf0570028, 0xf04f002a, 0xf047002c, 0xf047002a,
13547 0xf0470028, 0xf0470026, 0xf0470024, 0xf0470022,
13548 0xf047001f, 0xf0370027, 0xf0370024, 0xf0370022,
13549 0xf0370020, 0xf037001f, 0xf037001d, 0xf037001b,
13550 0xf037001a, 0xf0370018, 0xf0370017, 0xf027001e,
13551 0xf027001d, 0xf027001a, 0xf01f0024, 0xf01f0022,
13552 0xf01f0020, 0xf01f001f, 0xf01f001d, 0xf01f001b,
13553 0xf01f001a, 0xf01f0018, 0xf01f0017, 0xf01f0015,
13554 0xf01f0014, 0xf01f0013, 0xf01f0012, 0xf01f0011,
13555 0xf0170019, 0xf0170018, 0xf0170016, 0xf0170015,
13556 0xf0170014, 0xf0170013, 0xf0170012, 0xf0170010,
13557 0xf0170010, 0xf017000f, 0xf00f001d, 0xf00f001b,
13558 0xf00f001a, 0xf00f0018, 0xf00f0017, 0xf00f0015,
13559 0xf00f0015, 0xf00f0013, 0xf00f0013, 0xf00f0011,
13560 0xf00f0010, 0xf00f0010, 0xf00f000f, 0xf00f000e,
13561 0xf00f000d, 0xf00f000c, 0xf00f000b, 0xf00f000b,
13562 0xf00f000b, 0xf00f000a, 0xf00f0009, 0xf00f0009,
13563 0xf00f0009, 0xf00f0008, 0xf00f0007, 0xf00f0007,
13564 0xf00f0006, 0xf00f0006, 0xf00f0006, 0xf00f0006,
13565 0xf00f0005, 0xf00f0005, 0xf00f0005, 0xf00f0004,
13566 0xf00f0004, 0xf00f0004, 0xf00f0004, 0xf00f0004,
13567 0xf00f0004, 0xf00f0003, 0xf00f0003, 0xf00f0003,
13568 0xf00f0003, 0xf00f0002, 0xf00f0002, 0xf00f0002,
13569 0xf00f0002, 0xf00f0002, 0xf00f0002, 0xf00f0001,
13570 0xf00f0001, 0xf00f0001, 0xf00f0001, 0xf00f0001,
13571 0xf00f0001, 0xf00f0001, 0xf00f0001, 0xf00f0001
13572};
13573
13574static u32 nphy_tpc_txgain_ipa_2g_2057rev5[] = {
13575 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
13576 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
13577 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
13578 0x3067002e, 0x305f002f, 0x30570030, 0x3057002d,
13579 0x304f002e, 0x30470031, 0x3047002e, 0x3047002c,
13580 0x30470029, 0x303f002c, 0x303f0029, 0x3037002d,
13581 0x3037002a, 0x30370028, 0x302f002c, 0x302f002a,
13582 0x302f0028, 0x302f0026, 0x3027002c, 0x30270029,
13583 0x30270027, 0x30270025, 0x30270023, 0x301f002c,
13584 0x301f002a, 0x301f0028, 0x301f0025, 0x301f0024,
13585 0x301f0022, 0x301f001f, 0x3017002d, 0x3017002b,
13586 0x30170028, 0x30170026, 0x30170024, 0x30170022,
13587 0x30170020, 0x3017001e, 0x3017001d, 0x3017001b,
13588 0x3017001a, 0x30170018, 0x30170017, 0x30170015,
13589 0x300f002c, 0x300f0029, 0x300f0027, 0x300f0024,
13590 0x300f0022, 0x300f0021, 0x300f001f, 0x300f001d,
13591 0x300f001b, 0x300f001a, 0x300f0018, 0x300f0017,
13592 0x300f0016, 0x300f0015, 0x300f0115, 0x300f0215,
13593 0x300f0315, 0x300f0415, 0x300f0515, 0x300f0615,
13594 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13595 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13596 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13597 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13598 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13599 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13600 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13601 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13602 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13603 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13604 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13605 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13606 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
13607};
13608
13609static u32 nphy_tpc_txgain_ipa_2g_2057rev7[] = {
13610 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
13611 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
13612 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
13613 0x3067002e, 0x305f002f, 0x30570030, 0x3057002d,
13614 0x304f002e, 0x30470031, 0x3047002e, 0x3047002c,
13615 0x30470029, 0x303f002c, 0x303f0029, 0x3037002d,
13616 0x3037002a, 0x30370028, 0x302f002c, 0x302f002a,
13617 0x302f0028, 0x302f0026, 0x3027002c, 0x30270029,
13618 0x30270027, 0x30270025, 0x30270023, 0x301f002c,
13619 0x301f002a, 0x301f0028, 0x301f0025, 0x301f0024,
13620 0x301f0022, 0x301f001f, 0x3017002d, 0x3017002b,
13621 0x30170028, 0x30170026, 0x30170024, 0x30170022,
13622 0x30170020, 0x3017001e, 0x3017001d, 0x3017001b,
13623 0x3017001a, 0x30170018, 0x30170017, 0x30170015,
13624 0x300f002c, 0x300f0029, 0x300f0027, 0x300f0024,
13625 0x300f0022, 0x300f0021, 0x300f001f, 0x300f001d,
13626 0x300f001b, 0x300f001a, 0x300f0018, 0x300f0017,
13627 0x300f0016, 0x300f0015, 0x300f0115, 0x300f0215,
13628 0x300f0315, 0x300f0415, 0x300f0515, 0x300f0615,
13629 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13630 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13631 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13632 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13633 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13634 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13635 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13636 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13637 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13638 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13639 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13640 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
13641 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
13642};
13643
13644static u32 nphy_tpc_txgain_ipa_5g[] = {
13645 0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031,
13646 0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b,
13647 0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027,
13648 0x7ff70026, 0x7ff70024, 0x7ff70023, 0x7ff70022,
13649 0x7ef70028, 0x7ef70027, 0x7ef70026, 0x7ef70025,
13650 0x7ef70024, 0x7ef70023, 0x7df70028, 0x7df70027,
13651 0x7df70026, 0x7df70025, 0x7df70024, 0x7df70023,
13652 0x7df70022, 0x7cf70029, 0x7cf70028, 0x7cf70027,
13653 0x7cf70026, 0x7cf70025, 0x7cf70023, 0x7cf70022,
13654 0x7bf70029, 0x7bf70028, 0x7bf70026, 0x7bf70025,
13655 0x7bf70024, 0x7bf70023, 0x7bf70022, 0x7bf70021,
13656 0x7af70029, 0x7af70028, 0x7af70027, 0x7af70026,
13657 0x7af70025, 0x7af70024, 0x7af70023, 0x7af70022,
13658 0x79f70029, 0x79f70028, 0x79f70027, 0x79f70026,
13659 0x79f70025, 0x79f70024, 0x79f70023, 0x79f70022,
13660 0x78f70029, 0x78f70028, 0x78f70027, 0x78f70026,
13661 0x78f70025, 0x78f70024, 0x78f70023, 0x78f70022,
13662 0x77f70029, 0x77f70028, 0x77f70027, 0x77f70026,
13663 0x77f70025, 0x77f70024, 0x77f70023, 0x77f70022,
13664 0x76f70029, 0x76f70028, 0x76f70027, 0x76f70026,
13665 0x76f70024, 0x76f70023, 0x76f70022, 0x76f70021,
13666 0x75f70029, 0x75f70028, 0x75f70027, 0x75f70026,
13667 0x75f70025, 0x75f70024, 0x75f70023, 0x74f70029,
13668 0x74f70028, 0x74f70026, 0x74f70025, 0x74f70024,
13669 0x74f70023, 0x74f70022, 0x73f70029, 0x73f70027,
13670 0x73f70026, 0x73f70025, 0x73f70024, 0x73f70023,
13671 0x73f70022, 0x72f70028, 0x72f70027, 0x72f70026,
13672 0x72f70025, 0x72f70024, 0x72f70023, 0x72f70022,
13673 0x71f70028, 0x71f70027, 0x71f70026, 0x71f70025,
13674 0x71f70024, 0x71f70023, 0x70f70028, 0x70f70027,
13675 0x70f70026, 0x70f70024, 0x70f70023, 0x70f70022,
13676 0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f
13677};
13678
13679static u32 nphy_tpc_txgain_ipa_5g_2057[] = {
13680 0x7f7f0044, 0x7f7f0040, 0x7f7f003c, 0x7f7f0039,
13681 0x7f7f0036, 0x7e7f003c, 0x7e7f0038, 0x7e7f0035,
13682 0x7d7f003c, 0x7d7f0039, 0x7d7f0036, 0x7d7f0033,
13683 0x7c7f003b, 0x7c7f0037, 0x7c7f0034, 0x7b7f003a,
13684 0x7b7f0036, 0x7b7f0033, 0x7a7f003c, 0x7a7f0039,
13685 0x7a7f0036, 0x7a7f0033, 0x797f003b, 0x797f0038,
13686 0x797f0035, 0x797f0032, 0x787f003b, 0x787f0038,
13687 0x787f0035, 0x787f0032, 0x777f003a, 0x777f0037,
13688 0x777f0034, 0x777f0031, 0x767f003a, 0x767f0036,
13689 0x767f0033, 0x767f0031, 0x757f003a, 0x757f0037,
13690 0x757f0034, 0x747f003c, 0x747f0039, 0x747f0036,
13691 0x747f0033, 0x737f003b, 0x737f0038, 0x737f0035,
13692 0x737f0032, 0x727f0039, 0x727f0036, 0x727f0033,
13693 0x727f0030, 0x717f003a, 0x717f0037, 0x717f0034,
13694 0x707f003b, 0x707f0038, 0x707f0035, 0x707f0032,
13695 0x707f002f, 0x707f002d, 0x707f002a, 0x707f0028,
13696 0x707f0025, 0x707f0023, 0x707f0021, 0x707f0020,
13697 0x707f001e, 0x707f001c, 0x707f001b, 0x707f0019,
13698 0x707f0018, 0x707f0016, 0x707f0015, 0x707f0014,
13699 0x707f0013, 0x707f0012, 0x707f0011, 0x707f0010,
13700 0x707f000f, 0x707f000e, 0x707f000d, 0x707f000d,
13701 0x707f000c, 0x707f000b, 0x707f000b, 0x707f000a,
13702 0x707f0009, 0x707f0009, 0x707f0008, 0x707f0008,
13703 0x707f0007, 0x707f0007, 0x707f0007, 0x707f0006,
13704 0x707f0006, 0x707f0006, 0x707f0005, 0x707f0005,
13705 0x707f0005, 0x707f0004, 0x707f0004, 0x707f0004,
13706 0x707f0004, 0x707f0004, 0x707f0003, 0x707f0003,
13707 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003,
13708 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002,
13709 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002,
13710 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001,
13711 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001
13712};
13713
13714static u32 nphy_tpc_txgain_ipa_5g_2057rev7[] = {
13715 0x6f7f0031, 0x6f7f002e, 0x6f7f002c, 0x6f7f002a,
13716 0x6f7f0027, 0x6e7f002e, 0x6e7f002c, 0x6e7f002a,
13717 0x6d7f0030, 0x6d7f002d, 0x6d7f002a, 0x6d7f0028,
13718 0x6c7f0030, 0x6c7f002d, 0x6c7f002b, 0x6b7f002e,
13719 0x6b7f002c, 0x6b7f002a, 0x6b7f0027, 0x6a7f002e,
13720 0x6a7f002c, 0x6a7f002a, 0x697f0030, 0x697f002e,
13721 0x697f002b, 0x697f0029, 0x687f002f, 0x687f002d,
13722 0x687f002a, 0x687f0027, 0x677f002f, 0x677f002d,
13723 0x677f002a, 0x667f0031, 0x667f002e, 0x667f002c,
13724 0x667f002a, 0x657f0030, 0x657f002e, 0x657f002b,
13725 0x657f0029, 0x647f0030, 0x647f002d, 0x647f002b,
13726 0x647f0029, 0x637f002f, 0x637f002d, 0x637f002a,
13727 0x627f0030, 0x627f002d, 0x627f002b, 0x627f0029,
13728 0x617f0030, 0x617f002e, 0x617f002b, 0x617f0029,
13729 0x607f002f, 0x607f002d, 0x607f002a, 0x607f0027,
13730 0x607f0026, 0x607f0023, 0x607f0021, 0x607f0020,
13731 0x607f001e, 0x607f001c, 0x607f001a, 0x607f0019,
13732 0x607f0018, 0x607f0016, 0x607f0015, 0x607f0014,
13733 0x607f0012, 0x607f0012, 0x607f0011, 0x607f000f,
13734 0x607f000f, 0x607f000e, 0x607f000d, 0x607f000c,
13735 0x607f000c, 0x607f000b, 0x607f000b, 0x607f000a,
13736 0x607f0009, 0x607f0009, 0x607f0008, 0x607f0008,
13737 0x607f0008, 0x607f0007, 0x607f0007, 0x607f0006,
13738 0x607f0006, 0x607f0005, 0x607f0005, 0x607f0005,
13739 0x607f0005, 0x607f0005, 0x607f0004, 0x607f0004,
13740 0x607f0004, 0x607f0004, 0x607f0003, 0x607f0003,
13741 0x607f0003, 0x607f0003, 0x607f0002, 0x607f0002,
13742 0x607f0002, 0x607f0002, 0x607f0002, 0x607f0002,
13743 0x607f0002, 0x607f0002, 0x607f0002, 0x607f0002,
13744 0x607f0002, 0x607f0002, 0x607f0002, 0x607f0002,
13745 0x607f0002, 0x607f0001, 0x607f0001, 0x607f0001,
13746 0x607f0001, 0x607f0001, 0x607f0001, 0x607f0001
13747};
13748
13749static s8 nphy_papd_pga_gain_delta_ipa_2g[] = {
13750 -114, -108, -98, -91, -84, -78, -70, -62,
13751 -54, -46, -39, -31, -23, -15, -8, 0
13752};
13753
13754static s8 nphy_papd_pga_gain_delta_ipa_5g[] = {
13755 -100, -95, -89, -83, -77, -70, -63, -56,
13756 -48, -41, -33, -25, -19, -12, -6, 0
13757};
13758
13759static s16 nphy_papd_padgain_dlt_2g_2057rev3n4[] = {
13760 -159, -113, -86, -72, -62, -54, -48, -43,
13761 -39, -35, -31, -28, -25, -23, -20, -18,
13762 -17, -15, -13, -11, -10, -8, -7, -6,
13763 -5, -4, -3, -3, -2, -1, -1, 0
13764};
13765
13766static s16 nphy_papd_padgain_dlt_2g_2057rev5[] = {
13767 -109, -109, -82, -68, -58, -50, -44, -39,
13768 -35, -31, -28, -26, -23, -21, -19, -17,
13769 -16, -14, -13, -11, -10, -9, -8, -7,
13770 -5, -5, -4, -3, -2, -1, -1, 0
13771};
13772
13773static s16 nphy_papd_padgain_dlt_2g_2057rev7[] = {
13774 -122, -122, -95, -80, -69, -61, -54, -49,
13775 -43, -39, -35, -32, -28, -26, -23, -21,
13776 -18, -16, -15, -13, -11, -10, -8, -7,
13777 -6, -5, -4, -3, -2, -1, -1, 0
13778};
13779
13780static s8 nphy_papd_pgagain_dlt_5g_2057[] = {
13781 -107, -101, -92, -85, -78, -71, -62, -55,
13782 -47, -39, -32, -24, -19, -12, -6, 0
13783};
13784
13785static s8 nphy_papd_pgagain_dlt_5g_2057rev7[] = {
13786 -110, -104, -95, -88, -81, -74, -66, -58,
13787 -50, -44, -36, -28, -23, -15, -8, 0
13788};
13789
13790static u8 pad_gain_codes_used_2057rev5[] = {
13791 20, 19, 18, 17, 16, 15, 14, 13, 12, 11,
13792 10, 9, 8, 7, 6, 5, 4, 3, 2, 1
13793};
13794
13795static u8 pad_gain_codes_used_2057rev7[] = {
13796 15, 14, 13, 12, 11, 10, 9, 8, 7, 6,
13797 5, 4, 3, 2, 1
13798};
13799
13800static u8 pad_all_gain_codes_2057[] = {
13801 31, 30, 29, 28, 27, 26, 25, 24, 23, 22,
13802 21, 20, 19, 18, 17, 16, 15, 14, 13, 12,
13803 11, 10, 9, 8, 7, 6, 5, 4, 3, 2,
13804 1, 0
13805};
13806
13807static u8 pga_all_gain_codes_2057[] = {
13808 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
13809};
13810
13811static u32 nphy_papd_scaltbl[] = {
13812 0x0ae2002f, 0x0a3b0032, 0x09a70035, 0x09220038,
13813 0x0887003c, 0x081f003f, 0x07a20043, 0x07340047,
13814 0x06d2004b, 0x067a004f, 0x06170054, 0x05bf0059,
13815 0x0571005e, 0x051e0064, 0x04d3006a, 0x04910070,
13816 0x044c0077, 0x040f007e, 0x03d90085, 0x03a1008d,
13817 0x036f0095, 0x033d009e, 0x030b00a8, 0x02e000b2,
13818 0x02b900bc, 0x029200c7, 0x026d00d3, 0x024900e0,
13819 0x022900ed, 0x020a00fb, 0x01ec010a, 0x01d0011a,
13820 0x01b7012a, 0x019e013c, 0x0187014f, 0x01720162,
13821 0x015d0177, 0x0149018e, 0x013701a5, 0x012601be,
13822 0x011501d9, 0x010501f5, 0x00f70212, 0x00e90232,
13823 0x00dc0253, 0x00d00276, 0x00c4029c, 0x00b902c3,
13824 0x00af02ed, 0x00a5031a, 0x009c0349, 0x0093037a,
13825 0x008b03af, 0x008303e7, 0x007c0422, 0x00750461,
13826 0x006e04a3, 0x006804ea, 0x00620534, 0x005d0583,
13827 0x005805d7, 0x0053062f, 0x004e068d, 0x004a06f1
13828};
13829
13830static u32 nphy_tpc_txgain_rev3[] = {
13831 0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e,
13832 0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037,
13833 0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e,
13834 0x1e41003c, 0x1e41003b, 0x1e410039, 0x1e410037,
13835 0x1d410044, 0x1d410042, 0x1d410040, 0x1d41003e,
13836 0x1d41003c, 0x1d41003b, 0x1d410039, 0x1d410037,
13837 0x1c410044, 0x1c410042, 0x1c410040, 0x1c41003e,
13838 0x1c41003c, 0x1c41003b, 0x1c410039, 0x1c410037,
13839 0x1b410044, 0x1b410042, 0x1b410040, 0x1b41003e,
13840 0x1b41003c, 0x1b41003b, 0x1b410039, 0x1b410037,
13841 0x1a410044, 0x1a410042, 0x1a410040, 0x1a41003e,
13842 0x1a41003c, 0x1a41003b, 0x1a410039, 0x1a410037,
13843 0x19410044, 0x19410042, 0x19410040, 0x1941003e,
13844 0x1941003c, 0x1941003b, 0x19410039, 0x19410037,
13845 0x18410044, 0x18410042, 0x18410040, 0x1841003e,
13846 0x1841003c, 0x1841003b, 0x18410039, 0x18410037,
13847 0x17410044, 0x17410042, 0x17410040, 0x1741003e,
13848 0x1741003c, 0x1741003b, 0x17410039, 0x17410037,
13849 0x16410044, 0x16410042, 0x16410040, 0x1641003e,
13850 0x1641003c, 0x1641003b, 0x16410039, 0x16410037,
13851 0x15410044, 0x15410042, 0x15410040, 0x1541003e,
13852 0x1541003c, 0x1541003b, 0x15410039, 0x15410037,
13853 0x14410044, 0x14410042, 0x14410040, 0x1441003e,
13854 0x1441003c, 0x1441003b, 0x14410039, 0x14410037,
13855 0x13410044, 0x13410042, 0x13410040, 0x1341003e,
13856 0x1341003c, 0x1341003b, 0x13410039, 0x13410037,
13857 0x12410044, 0x12410042, 0x12410040, 0x1241003e,
13858 0x1241003c, 0x1241003b, 0x12410039, 0x12410037,
13859 0x11410044, 0x11410042, 0x11410040, 0x1141003e,
13860 0x1141003c, 0x1141003b, 0x11410039, 0x11410037,
13861 0x10410044, 0x10410042, 0x10410040, 0x1041003e,
13862 0x1041003c, 0x1041003b, 0x10410039, 0x10410037
13863};
13864
13865static u32 nphy_tpc_txgain_HiPwrEPA[] = {
13866 0x0f410044, 0x0f410042, 0x0f410040, 0x0f41003e,
13867 0x0f41003c, 0x0f41003b, 0x0f410039, 0x0f410037,
13868 0x0e410044, 0x0e410042, 0x0e410040, 0x0e41003e,
13869 0x0e41003c, 0x0e41003b, 0x0e410039, 0x0e410037,
13870 0x0d410044, 0x0d410042, 0x0d410040, 0x0d41003e,
13871 0x0d41003c, 0x0d41003b, 0x0d410039, 0x0d410037,
13872 0x0c410044, 0x0c410042, 0x0c410040, 0x0c41003e,
13873 0x0c41003c, 0x0c41003b, 0x0c410039, 0x0c410037,
13874 0x0b410044, 0x0b410042, 0x0b410040, 0x0b41003e,
13875 0x0b41003c, 0x0b41003b, 0x0b410039, 0x0b410037,
13876 0x0a410044, 0x0a410042, 0x0a410040, 0x0a41003e,
13877 0x0a41003c, 0x0a41003b, 0x0a410039, 0x0a410037,
13878 0x09410044, 0x09410042, 0x09410040, 0x0941003e,
13879 0x0941003c, 0x0941003b, 0x09410039, 0x09410037,
13880 0x08410044, 0x08410042, 0x08410040, 0x0841003e,
13881 0x0841003c, 0x0841003b, 0x08410039, 0x08410037,
13882 0x07410044, 0x07410042, 0x07410040, 0x0741003e,
13883 0x0741003c, 0x0741003b, 0x07410039, 0x07410037,
13884 0x06410044, 0x06410042, 0x06410040, 0x0641003e,
13885 0x0641003c, 0x0641003b, 0x06410039, 0x06410037,
13886 0x05410044, 0x05410042, 0x05410040, 0x0541003e,
13887 0x0541003c, 0x0541003b, 0x05410039, 0x05410037,
13888 0x04410044, 0x04410042, 0x04410040, 0x0441003e,
13889 0x0441003c, 0x0441003b, 0x04410039, 0x04410037,
13890 0x03410044, 0x03410042, 0x03410040, 0x0341003e,
13891 0x0341003c, 0x0341003b, 0x03410039, 0x03410037,
13892 0x02410044, 0x02410042, 0x02410040, 0x0241003e,
13893 0x0241003c, 0x0241003b, 0x02410039, 0x02410037,
13894 0x01410044, 0x01410042, 0x01410040, 0x0141003e,
13895 0x0141003c, 0x0141003b, 0x01410039, 0x01410037,
13896 0x00410044, 0x00410042, 0x00410040, 0x0041003e,
13897 0x0041003c, 0x0041003b, 0x00410039, 0x00410037
13898};
13899
13900static u32 nphy_tpc_txgain_epa_2057rev3[] = {
13901 0x80f90040, 0x80e10040, 0x80e1003c, 0x80c9003d,
13902 0x80b9003c, 0x80a9003d, 0x80a1003c, 0x8099003b,
13903 0x8091003b, 0x8089003a, 0x8081003a, 0x80790039,
13904 0x80710039, 0x8069003a, 0x8061003b, 0x8059003d,
13905 0x8051003f, 0x80490042, 0x8049003e, 0x8049003b,
13906 0x8041003e, 0x8041003b, 0x8039003e, 0x8039003b,
13907 0x80390038, 0x80390035, 0x8031003a, 0x80310036,
13908 0x80310033, 0x8029003a, 0x80290037, 0x80290034,
13909 0x80290031, 0x80210039, 0x80210036, 0x80210033,
13910 0x80210030, 0x8019003c, 0x80190039, 0x80190036,
13911 0x80190033, 0x80190030, 0x8019002d, 0x8019002b,
13912 0x80190028, 0x8011003a, 0x80110036, 0x80110033,
13913 0x80110030, 0x8011002e, 0x8011002b, 0x80110029,
13914 0x80110027, 0x80110024, 0x80110022, 0x80110020,
13915 0x8011001f, 0x8011001d, 0x8009003a, 0x80090037,
13916 0x80090034, 0x80090031, 0x8009002e, 0x8009002c,
13917 0x80090029, 0x80090027, 0x80090025, 0x80090023,
13918 0x80090021, 0x8009001f, 0x8009001d, 0x8009011d,
13919 0x8009021d, 0x8009031d, 0x8009041d, 0x8009051d,
13920 0x8009061d, 0x8009071d, 0x8009071d, 0x8009071d,
13921 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13922 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13923 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13924 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13925 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13926 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13927 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13928 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13929 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13930 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13931 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
13932 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d
13933};
13934
13935static u32 nphy_tpc_txgain_epa_2057rev5[] = {
13936 0x10f90040, 0x10e10040, 0x10e1003c, 0x10c9003d,
13937 0x10b9003c, 0x10a9003d, 0x10a1003c, 0x1099003b,
13938 0x1091003b, 0x1089003a, 0x1081003a, 0x10790039,
13939 0x10710039, 0x1069003a, 0x1061003b, 0x1059003d,
13940 0x1051003f, 0x10490042, 0x1049003e, 0x1049003b,
13941 0x1041003e, 0x1041003b, 0x1039003e, 0x1039003b,
13942 0x10390038, 0x10390035, 0x1031003a, 0x10310036,
13943 0x10310033, 0x1029003a, 0x10290037, 0x10290034,
13944 0x10290031, 0x10210039, 0x10210036, 0x10210033,
13945 0x10210030, 0x1019003c, 0x10190039, 0x10190036,
13946 0x10190033, 0x10190030, 0x1019002d, 0x1019002b,
13947 0x10190028, 0x1011003a, 0x10110036, 0x10110033,
13948 0x10110030, 0x1011002e, 0x1011002b, 0x10110029,
13949 0x10110027, 0x10110024, 0x10110022, 0x10110020,
13950 0x1011001f, 0x1011001d, 0x1009003a, 0x10090037,
13951 0x10090034, 0x10090031, 0x1009002e, 0x1009002c,
13952 0x10090029, 0x10090027, 0x10090025, 0x10090023,
13953 0x10090021, 0x1009001f, 0x1009001d, 0x1009001b,
13954 0x1009001a, 0x10090018, 0x10090017, 0x10090016,
13955 0x10090015, 0x10090013, 0x10090012, 0x10090011,
13956 0x10090010, 0x1009000f, 0x1009000f, 0x1009000e,
13957 0x1009000d, 0x1009000c, 0x1009000c, 0x1009000b,
13958 0x1009000a, 0x1009000a, 0x10090009, 0x10090009,
13959 0x10090008, 0x10090008, 0x10090007, 0x10090007,
13960 0x10090007, 0x10090006, 0x10090006, 0x10090005,
13961 0x10090005, 0x10090005, 0x10090005, 0x10090004,
13962 0x10090004, 0x10090004, 0x10090004, 0x10090003,
13963 0x10090003, 0x10090003, 0x10090003, 0x10090003,
13964 0x10090003, 0x10090002, 0x10090002, 0x10090002,
13965 0x10090002, 0x10090002, 0x10090002, 0x10090002,
13966 0x10090002, 0x10090002, 0x10090001, 0x10090001,
13967 0x10090001, 0x10090001, 0x10090001, 0x10090001
13968};
13969
13970static u32 nphy_tpc_5GHz_txgain_rev3[] = {
13971 0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e,
13972 0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037,
13973 0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e,
13974 0xcef7003c, 0xcef7003b, 0xcef70039, 0xcef70037,
13975 0xcdf70044, 0xcdf70042, 0xcdf70040, 0xcdf7003e,
13976 0xcdf7003c, 0xcdf7003b, 0xcdf70039, 0xcdf70037,
13977 0xccf70044, 0xccf70042, 0xccf70040, 0xccf7003e,
13978 0xccf7003c, 0xccf7003b, 0xccf70039, 0xccf70037,
13979 0xcbf70044, 0xcbf70042, 0xcbf70040, 0xcbf7003e,
13980 0xcbf7003c, 0xcbf7003b, 0xcbf70039, 0xcbf70037,
13981 0xcaf70044, 0xcaf70042, 0xcaf70040, 0xcaf7003e,
13982 0xcaf7003c, 0xcaf7003b, 0xcaf70039, 0xcaf70037,
13983 0xc9f70044, 0xc9f70042, 0xc9f70040, 0xc9f7003e,
13984 0xc9f7003c, 0xc9f7003b, 0xc9f70039, 0xc9f70037,
13985 0xc8f70044, 0xc8f70042, 0xc8f70040, 0xc8f7003e,
13986 0xc8f7003c, 0xc8f7003b, 0xc8f70039, 0xc8f70037,
13987 0xc7f70044, 0xc7f70042, 0xc7f70040, 0xc7f7003e,
13988 0xc7f7003c, 0xc7f7003b, 0xc7f70039, 0xc7f70037,
13989 0xc6f70044, 0xc6f70042, 0xc6f70040, 0xc6f7003e,
13990 0xc6f7003c, 0xc6f7003b, 0xc6f70039, 0xc6f70037,
13991 0xc5f70044, 0xc5f70042, 0xc5f70040, 0xc5f7003e,
13992 0xc5f7003c, 0xc5f7003b, 0xc5f70039, 0xc5f70037,
13993 0xc4f70044, 0xc4f70042, 0xc4f70040, 0xc4f7003e,
13994 0xc4f7003c, 0xc4f7003b, 0xc4f70039, 0xc4f70037,
13995 0xc3f70044, 0xc3f70042, 0xc3f70040, 0xc3f7003e,
13996 0xc3f7003c, 0xc3f7003b, 0xc3f70039, 0xc3f70037,
13997 0xc2f70044, 0xc2f70042, 0xc2f70040, 0xc2f7003e,
13998 0xc2f7003c, 0xc2f7003b, 0xc2f70039, 0xc2f70037,
13999 0xc1f70044, 0xc1f70042, 0xc1f70040, 0xc1f7003e,
14000 0xc1f7003c, 0xc1f7003b, 0xc1f70039, 0xc1f70037,
14001 0xc0f70044, 0xc0f70042, 0xc0f70040, 0xc0f7003e,
14002 0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037
14003};
14004
14005static u32 nphy_tpc_5GHz_txgain_rev4[] = {
14006 0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e,
14007 0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037,
14008 0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e,
14009 0x2ef2003c, 0x2ef2003b, 0x2ef20039, 0x2ef20037,
14010 0x2df20044, 0x2df20042, 0x2df20040, 0x2df2003e,
14011 0x2df2003c, 0x2df2003b, 0x2df20039, 0x2df20037,
14012 0x2cf20044, 0x2cf20042, 0x2cf20040, 0x2cf2003e,
14013 0x2cf2003c, 0x2cf2003b, 0x2cf20039, 0x2cf20037,
14014 0x2bf20044, 0x2bf20042, 0x2bf20040, 0x2bf2003e,
14015 0x2bf2003c, 0x2bf2003b, 0x2bf20039, 0x2bf20037,
14016 0x2af20044, 0x2af20042, 0x2af20040, 0x2af2003e,
14017 0x2af2003c, 0x2af2003b, 0x2af20039, 0x2af20037,
14018 0x29f20044, 0x29f20042, 0x29f20040, 0x29f2003e,
14019 0x29f2003c, 0x29f2003b, 0x29f20039, 0x29f20037,
14020 0x28f20044, 0x28f20042, 0x28f20040, 0x28f2003e,
14021 0x28f2003c, 0x28f2003b, 0x28f20039, 0x28f20037,
14022 0x27f20044, 0x27f20042, 0x27f20040, 0x27f2003e,
14023 0x27f2003c, 0x27f2003b, 0x27f20039, 0x27f20037,
14024 0x26f20044, 0x26f20042, 0x26f20040, 0x26f2003e,
14025 0x26f2003c, 0x26f2003b, 0x26f20039, 0x26f20037,
14026 0x25f20044, 0x25f20042, 0x25f20040, 0x25f2003e,
14027 0x25f2003c, 0x25f2003b, 0x25f20039, 0x25f20037,
14028 0x24f20044, 0x24f20042, 0x24f20040, 0x24f2003e,
14029 0x24f2003c, 0x24f2003b, 0x24f20039, 0x24f20038,
14030 0x23f20041, 0x23f20040, 0x23f2003f, 0x23f2003e,
14031 0x23f2003c, 0x23f2003b, 0x23f20039, 0x23f20037,
14032 0x22f20044, 0x22f20042, 0x22f20040, 0x22f2003e,
14033 0x22f2003c, 0x22f2003b, 0x22f20039, 0x22f20037,
14034 0x21f20044, 0x21f20042, 0x21f20040, 0x21f2003e,
14035 0x21f2003c, 0x21f2003b, 0x21f20039, 0x21f20037,
14036 0x20d20043, 0x20d20041, 0x20d2003e, 0x20d2003c,
14037 0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034
14038};
14039
14040static u32 nphy_tpc_5GHz_txgain_rev5[] = {
14041 0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044,
14042 0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c,
14043 0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e,
14044 0x0e62003c, 0x0e62003d, 0x0e62003b, 0x0e62003a,
14045 0x0d620043, 0x0d620041, 0x0d620040, 0x0d62003e,
14046 0x0d62003d, 0x0d62003c, 0x0d62003b, 0x0d62003a,
14047 0x0c620041, 0x0c620040, 0x0c62003f, 0x0c62003e,
14048 0x0c62003c, 0x0c62003b, 0x0c620039, 0x0c620037,
14049 0x0b620046, 0x0b620044, 0x0b620042, 0x0b620040,
14050 0x0b62003e, 0x0b62003c, 0x0b62003b, 0x0b62003a,
14051 0x0a620041, 0x0a620040, 0x0a62003e, 0x0a62003c,
14052 0x0a62003b, 0x0a62003a, 0x0a620039, 0x0a620038,
14053 0x0962003e, 0x0962003d, 0x0962003c, 0x0962003b,
14054 0x09620039, 0x09620037, 0x09620035, 0x09620033,
14055 0x08620044, 0x08620042, 0x08620040, 0x0862003e,
14056 0x0862003c, 0x0862003b, 0x0862003a, 0x08620039,
14057 0x07620043, 0x07620042, 0x07620040, 0x0762003f,
14058 0x0762003d, 0x0762003b, 0x0762003a, 0x07620039,
14059 0x0662003e, 0x0662003d, 0x0662003c, 0x0662003b,
14060 0x06620039, 0x06620037, 0x06620035, 0x06620033,
14061 0x05620046, 0x05620044, 0x05620042, 0x05620040,
14062 0x0562003e, 0x0562003c, 0x0562003b, 0x05620039,
14063 0x04620044, 0x04620042, 0x04620040, 0x0462003e,
14064 0x0462003c, 0x0462003b, 0x04620039, 0x04620038,
14065 0x0362003c, 0x0362003b, 0x0362003a, 0x03620039,
14066 0x03620038, 0x03620037, 0x03620035, 0x03620033,
14067 0x0262004c, 0x0262004a, 0x02620048, 0x02620047,
14068 0x02620046, 0x02620044, 0x02620043, 0x02620042,
14069 0x0162004a, 0x01620048, 0x01620046, 0x01620044,
14070 0x01620043, 0x01620042, 0x01620041, 0x01620040,
14071 0x00620042, 0x00620040, 0x0062003e, 0x0062003c,
14072 0x0062003b, 0x00620039, 0x00620037, 0x00620035
14073};
14074
14075static u32 nphy_tpc_5GHz_txgain_HiPwrEPA[] = {
14076 0x2ff10044, 0x2ff10042, 0x2ff10040, 0x2ff1003e,
14077 0x2ff1003c, 0x2ff1003b, 0x2ff10039, 0x2ff10037,
14078 0x2ef10044, 0x2ef10042, 0x2ef10040, 0x2ef1003e,
14079 0x2ef1003c, 0x2ef1003b, 0x2ef10039, 0x2ef10037,
14080 0x2df10044, 0x2df10042, 0x2df10040, 0x2df1003e,
14081 0x2df1003c, 0x2df1003b, 0x2df10039, 0x2df10037,
14082 0x2cf10044, 0x2cf10042, 0x2cf10040, 0x2cf1003e,
14083 0x2cf1003c, 0x2cf1003b, 0x2cf10039, 0x2cf10037,
14084 0x2bf10044, 0x2bf10042, 0x2bf10040, 0x2bf1003e,
14085 0x2bf1003c, 0x2bf1003b, 0x2bf10039, 0x2bf10037,
14086 0x2af10044, 0x2af10042, 0x2af10040, 0x2af1003e,
14087 0x2af1003c, 0x2af1003b, 0x2af10039, 0x2af10037,
14088 0x29f10044, 0x29f10042, 0x29f10040, 0x29f1003e,
14089 0x29f1003c, 0x29f1003b, 0x29f10039, 0x29f10037,
14090 0x28f10044, 0x28f10042, 0x28f10040, 0x28f1003e,
14091 0x28f1003c, 0x28f1003b, 0x28f10039, 0x28f10037,
14092 0x27f10044, 0x27f10042, 0x27f10040, 0x27f1003e,
14093 0x27f1003c, 0x27f1003b, 0x27f10039, 0x27f10037,
14094 0x26f10044, 0x26f10042, 0x26f10040, 0x26f1003e,
14095 0x26f1003c, 0x26f1003b, 0x26f10039, 0x26f10037,
14096 0x25f10044, 0x25f10042, 0x25f10040, 0x25f1003e,
14097 0x25f1003c, 0x25f1003b, 0x25f10039, 0x25f10037,
14098 0x24f10044, 0x24f10042, 0x24f10040, 0x24f1003e,
14099 0x24f1003c, 0x24f1003b, 0x24f10039, 0x24f10038,
14100 0x23f10041, 0x23f10040, 0x23f1003f, 0x23f1003e,
14101 0x23f1003c, 0x23f1003b, 0x23f10039, 0x23f10037,
14102 0x22f10044, 0x22f10042, 0x22f10040, 0x22f1003e,
14103 0x22f1003c, 0x22f1003b, 0x22f10039, 0x22f10037,
14104 0x21f10044, 0x21f10042, 0x21f10040, 0x21f1003e,
14105 0x21f1003c, 0x21f1003b, 0x21f10039, 0x21f10037,
14106 0x20d10043, 0x20d10041, 0x20d1003e, 0x20d1003c,
14107 0x20d1003a, 0x20d10038, 0x20d10036, 0x20d10034
14108};
14109
14110static u8 ant_sw_ctrl_tbl_rev8_2o3[] = { 0x14, 0x18 };
14111static u8 ant_sw_ctrl_tbl_rev8[] = { 0x4, 0x8, 0x4, 0x8, 0x11, 0x12 };
14112static u8 ant_sw_ctrl_tbl_rev8_2057v7_core0[] = {
14113 0x09, 0x0a, 0x15, 0x16, 0x09, 0x0a
14114};
14115static u8 ant_sw_ctrl_tbl_rev8_2057v7_core1[] = {
14116 0x09, 0x0a, 0x09, 0x0a, 0x15, 0x16
14117};
14118
14119bool wlc_phy_bist_check_phy(struct brcms_phy_pub *pih)
14120{
14121 struct brcms_phy *pi = (struct brcms_phy *) pih;
14122 u32 phybist0, phybist1, phybist2, phybist3, phybist4;
14123
14124 if (NREV_GE(pi->pubpi.phy_rev, 16))
14125 return true;
14126
14127 phybist0 = read_phy_reg(pi, 0x0e);
14128 phybist1 = read_phy_reg(pi, 0x0f);
14129 phybist2 = read_phy_reg(pi, 0xea);
14130 phybist3 = read_phy_reg(pi, 0xeb);
14131 phybist4 = read_phy_reg(pi, 0x156);
14132
14133 if ((phybist0 == 0) && (phybist1 == 0x4000) && (phybist2 == 0x1fe0) &&
14134 (phybist3 == 0) && (phybist4 == 0))
14135 return true;
14136
14137 return false;
14138}
14139
14140static void wlc_phy_bphy_init_nphy(struct brcms_phy *pi)
14141{
14142 u16 addr, val;
14143
14144 val = 0x1e1f;
14145 for (addr = (NPHY_TO_BPHY_OFF + BPHY_RSSI_LUT);
14146 addr <= (NPHY_TO_BPHY_OFF + BPHY_RSSI_LUT_END); addr++) {
14147 write_phy_reg(pi, addr, val);
14148 if (addr == (NPHY_TO_BPHY_OFF + 0x97))
14149 val = 0x3e3f;
14150 else
14151 val -= 0x0202;
14152 }
14153
14154 write_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_STEP, 0x668);
14155}
14156
14157void
14158wlc_phy_table_write_nphy(struct brcms_phy *pi, u32 id, u32 len, u32 offset,
14159 u32 width, const void *data)
14160{
14161 struct phytbl_info tbl;
14162
14163 tbl.tbl_id = id;
14164 tbl.tbl_len = len;
14165 tbl.tbl_offset = offset;
14166 tbl.tbl_width = width;
14167 tbl.tbl_ptr = data;
14168 wlc_phy_write_table_nphy(pi, &tbl);
14169}
14170
14171void
14172wlc_phy_table_read_nphy(struct brcms_phy *pi, u32 id, u32 len, u32 offset,
14173 u32 width, void *data)
14174{
14175 struct phytbl_info tbl;
14176
14177 tbl.tbl_id = id;
14178 tbl.tbl_len = len;
14179 tbl.tbl_offset = offset;
14180 tbl.tbl_width = width;
14181 tbl.tbl_ptr = data;
14182 wlc_phy_read_table_nphy(pi, &tbl);
14183}
14184
14185static void
14186wlc_phy_static_table_download_nphy(struct brcms_phy *pi)
14187{
14188 uint idx;
14189
14190 if (NREV_GE(pi->pubpi.phy_rev, 16)) {
14191 for (idx = 0; idx < mimophytbl_info_sz_rev16; idx++)
14192 wlc_phy_write_table_nphy(pi,
14193 &mimophytbl_info_rev16[idx]);
14194 } else if (NREV_GE(pi->pubpi.phy_rev, 7)) {
14195 for (idx = 0; idx < mimophytbl_info_sz_rev7; idx++)
14196 wlc_phy_write_table_nphy(pi,
14197 &mimophytbl_info_rev7[idx]);
14198 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
14199 for (idx = 0; idx < mimophytbl_info_sz_rev3; idx++)
14200 wlc_phy_write_table_nphy(pi,
14201 &mimophytbl_info_rev3[idx]);
14202 } else {
14203 for (idx = 0; idx < mimophytbl_info_sz_rev0; idx++)
14204 wlc_phy_write_table_nphy(pi,
14205 &mimophytbl_info_rev0[idx]);
14206 }
14207}
14208
14209static void wlc_phy_tbl_init_nphy(struct brcms_phy *pi)
14210{
14211 uint idx = 0;
14212 u8 antswctrllut;
14213
14214 if (pi->phy_init_por)
14215 wlc_phy_static_table_download_nphy(pi);
14216
14217 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
14218
14219 antswctrllut = CHSPEC_IS2G(pi->radio_chanspec) ?
14220 pi->srom_fem2g.antswctrllut : pi->srom_fem5g.
14221 antswctrllut;
14222
14223 switch (antswctrllut) {
14224 case 0:
14225
14226 break;
14227
14228 case 1:
14229
14230 if (pi->aa2g == 7)
14231 wlc_phy_table_write_nphy(
14232 pi,
14233 NPHY_TBL_ID_ANTSWCTRLLUT,
14234 2, 0x21, 8,
14235 &ant_sw_ctrl_tbl_rev8_2o3[0]);
14236 else
14237 wlc_phy_table_write_nphy(
14238 pi,
14239 NPHY_TBL_ID_ANTSWCTRLLUT,
14240 2, 0x21, 8,
14241 &ant_sw_ctrl_tbl_rev8
14242 [0]);
14243
14244 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14245 2, 0x25, 8,
14246 &ant_sw_ctrl_tbl_rev8[2]);
14247 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14248 2, 0x29, 8,
14249 &ant_sw_ctrl_tbl_rev8[4]);
14250 break;
14251
14252 case 2:
14253
14254 wlc_phy_table_write_nphy(
14255 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14256 2, 0x1, 8,
14257 &ant_sw_ctrl_tbl_rev8_2057v7_core0[0]);
14258 wlc_phy_table_write_nphy(
14259 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14260 2, 0x5, 8,
14261 &ant_sw_ctrl_tbl_rev8_2057v7_core0[2]);
14262 wlc_phy_table_write_nphy(
14263 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14264 2, 0x9, 8,
14265 &ant_sw_ctrl_tbl_rev8_2057v7_core0[4]);
14266
14267 wlc_phy_table_write_nphy(
14268 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14269 2, 0x21, 8,
14270 &ant_sw_ctrl_tbl_rev8_2057v7_core1[0]);
14271 wlc_phy_table_write_nphy(
14272 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14273 2, 0x25, 8,
14274 &ant_sw_ctrl_tbl_rev8_2057v7_core1[2]);
14275 wlc_phy_table_write_nphy(
14276 pi, NPHY_TBL_ID_ANTSWCTRLLUT,
14277 2, 0x29, 8,
14278 &ant_sw_ctrl_tbl_rev8_2057v7_core1[4]);
14279 break;
14280
14281 default:
14282 break;
14283 }
14284
14285 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
14286 for (idx = 0; idx < mimophytbl_info_sz_rev3_volatile; idx++) {
14287
14288 if (idx == ANT_SWCTRL_TBL_REV3_IDX) {
14289 antswctrllut =
14290 CHSPEC_IS2G(pi->radio_chanspec) ?
14291 pi->srom_fem2g.antswctrllut :
14292 pi->srom_fem5g.antswctrllut;
14293 switch (antswctrllut) {
14294 case 0:
14295 wlc_phy_write_table_nphy(
14296 pi,
14297 &mimophytbl_info_rev3_volatile
14298 [idx]);
14299 break;
14300 case 1:
14301 wlc_phy_write_table_nphy(
14302 pi,
14303 &mimophytbl_info_rev3_volatile1
14304 [idx]);
14305 break;
14306 case 2:
14307 wlc_phy_write_table_nphy(
14308 pi,
14309 &mimophytbl_info_rev3_volatile2
14310 [idx]);
14311 break;
14312 case 3:
14313 wlc_phy_write_table_nphy(
14314 pi,
14315 &mimophytbl_info_rev3_volatile3
14316 [idx]);
14317 break;
14318 default:
14319 break;
14320 }
14321 } else {
14322 wlc_phy_write_table_nphy(
14323 pi,
14324 &mimophytbl_info_rev3_volatile[idx]);
14325 }
14326 }
14327 } else {
14328 for (idx = 0; idx < mimophytbl_info_sz_rev0_volatile; idx++)
14329 wlc_phy_write_table_nphy(pi,
14330 &mimophytbl_info_rev0_volatile
14331 [idx]);
14332 }
14333}
14334
14335static void
14336wlc_phy_write_txmacreg_nphy(struct brcms_phy *pi, u16 holdoff, u16 delay)
14337{
14338 write_phy_reg(pi, 0x77, holdoff);
14339 write_phy_reg(pi, 0xb4, delay);
14340}
14341
14342void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs)
14343{
14344 u16 holdoff, delay;
14345
14346 if (rifs) {
14347
14348 holdoff = 0x10;
14349 delay = 0x258;
14350 } else {
14351
14352 holdoff = 0x15;
14353 delay = 0x320;
14354 }
14355
14356 wlc_phy_write_txmacreg_nphy(pi, holdoff, delay);
14357
14358 if (pi && pi->sh && (pi->sh->_rifs_phy != rifs))
14359 pi->sh->_rifs_phy = rifs;
14360}
14361
14362static void wlc_phy_txpwrctrl_config_nphy(struct brcms_phy *pi)
14363{
14364
14365 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
14366 pi->nphy_txpwrctrl = PHY_TPC_HW_ON;
14367 pi->phy_5g_pwrgain = true;
14368 return;
14369 }
14370
14371 pi->nphy_txpwrctrl = PHY_TPC_HW_OFF;
14372 pi->phy_5g_pwrgain = false;
14373
14374 if ((pi->sh->boardflags2 & BFL2_TXPWRCTRL_EN) &&
14375 NREV_GE(pi->pubpi.phy_rev, 2) && (pi->sh->sromrev >= 4))
14376 pi->nphy_txpwrctrl = PHY_TPC_HW_ON;
14377 else if ((pi->sh->sromrev >= 4)
14378 && (pi->sh->boardflags2 & BFL2_5G_PWRGAIN))
14379 pi->phy_5g_pwrgain = true;
14380}
14381
14382static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi)
14383{
14384 u16 bw40po, cddpo, stbcpo, bwduppo;
14385 uint band_num;
14386 struct phy_shim_info *shim = pi->sh->physhim;
14387
14388 if (pi->sh->sromrev >= 9)
14389 return;
14390
14391 bw40po = (u16) wlapi_getintvar(shim, BRCMS_SROM_BW40PO);
14392 pi->bw402gpo = bw40po & 0xf;
14393 pi->bw405gpo = (bw40po & 0xf0) >> 4;
14394 pi->bw405glpo = (bw40po & 0xf00) >> 8;
14395 pi->bw405ghpo = (bw40po & 0xf000) >> 12;
14396
14397 cddpo = (u16) wlapi_getintvar(shim, BRCMS_SROM_CDDPO);
14398 pi->cdd2gpo = cddpo & 0xf;
14399 pi->cdd5gpo = (cddpo & 0xf0) >> 4;
14400 pi->cdd5glpo = (cddpo & 0xf00) >> 8;
14401 pi->cdd5ghpo = (cddpo & 0xf000) >> 12;
14402
14403 stbcpo = (u16) wlapi_getintvar(shim, BRCMS_SROM_STBCPO);
14404 pi->stbc2gpo = stbcpo & 0xf;
14405 pi->stbc5gpo = (stbcpo & 0xf0) >> 4;
14406 pi->stbc5glpo = (stbcpo & 0xf00) >> 8;
14407 pi->stbc5ghpo = (stbcpo & 0xf000) >> 12;
14408
14409 bwduppo = (u16) wlapi_getintvar(shim, BRCMS_SROM_BWDUPPO);
14410 pi->bwdup2gpo = bwduppo & 0xf;
14411 pi->bwdup5gpo = (bwduppo & 0xf0) >> 4;
14412 pi->bwdup5glpo = (bwduppo & 0xf00) >> 8;
14413 pi->bwdup5ghpo = (bwduppo & 0xf000) >> 12;
14414
14415 for (band_num = 0; band_num < (CH_2G_GROUP + CH_5G_GROUP);
14416 band_num++) {
14417 switch (band_num) {
14418 case 0:
14419
14420 pi->nphy_txpid2g[PHY_CORE_0] =
14421 (u8) wlapi_getintvar(shim,
14422 BRCMS_SROM_TXPID2GA0);
14423 pi->nphy_txpid2g[PHY_CORE_1] =
14424 (u8) wlapi_getintvar(shim,
14425 BRCMS_SROM_TXPID2GA1);
14426 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g =
14427 (s8) wlapi_getintvar(shim,
14428 BRCMS_SROM_MAXP2GA0);
14429 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_2g =
14430 (s8) wlapi_getintvar(shim,
14431 BRCMS_SROM_MAXP2GA1);
14432 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_a1 =
14433 (s16) wlapi_getintvar(shim,
14434 BRCMS_SROM_PA2GW0A0);
14435 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_a1 =
14436 (s16) wlapi_getintvar(shim,
14437 BRCMS_SROM_PA2GW0A1);
14438 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b0 =
14439 (s16) wlapi_getintvar(shim,
14440 BRCMS_SROM_PA2GW1A0);
14441 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b0 =
14442 (s16) wlapi_getintvar(shim,
14443 BRCMS_SROM_PA2GW1A1);
14444 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b1 =
14445 (s16) wlapi_getintvar(shim,
14446 BRCMS_SROM_PA2GW2A0);
14447 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b1 =
14448 (s16) wlapi_getintvar(shim,
14449 BRCMS_SROM_PA2GW2A1);
14450 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_2g =
14451 (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT2GA0);
14452 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g =
14453 (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT2GA1);
14454
14455 pi->cck2gpo = (u16) wlapi_getintvar(shim,
14456 BRCMS_SROM_CCK2GPO);
14457
14458 pi->ofdm2gpo =
14459 (u32) wlapi_getintvar(shim,
14460 BRCMS_SROM_OFDM2GPO);
14461
14462 pi->mcs2gpo[0] =
14463 (u16) wlapi_getintvar(shim,
14464 BRCMS_SROM_MCS2GPO0);
14465 pi->mcs2gpo[1] =
14466 (u16) wlapi_getintvar(shim,
14467 BRCMS_SROM_MCS2GPO1);
14468 pi->mcs2gpo[2] =
14469 (u16) wlapi_getintvar(shim,
14470 BRCMS_SROM_MCS2GPO2);
14471 pi->mcs2gpo[3] =
14472 (u16) wlapi_getintvar(shim,
14473 BRCMS_SROM_MCS2GPO3);
14474 pi->mcs2gpo[4] =
14475 (u16) wlapi_getintvar(shim,
14476 BRCMS_SROM_MCS2GPO4);
14477 pi->mcs2gpo[5] =
14478 (u16) wlapi_getintvar(shim,
14479 BRCMS_SROM_MCS2GPO5);
14480 pi->mcs2gpo[6] =
14481 (u16) wlapi_getintvar(shim,
14482 BRCMS_SROM_MCS2GPO6);
14483 pi->mcs2gpo[7] =
14484 (u16) wlapi_getintvar(shim,
14485 BRCMS_SROM_MCS2GPO7);
14486 break;
14487 case 1:
14488
14489 pi->nphy_txpid5g[PHY_CORE_0] =
14490 (u8) wlapi_getintvar(shim,
14491 BRCMS_SROM_TXPID5GA0);
14492 pi->nphy_txpid5g[PHY_CORE_1] =
14493 (u8) wlapi_getintvar(shim,
14494 BRCMS_SROM_TXPID5GA1);
14495 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm =
14496 (s8) wlapi_getintvar(shim, BRCMS_SROM_MAXP5GA0);
14497 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm =
14498 (s8) wlapi_getintvar(shim,
14499 BRCMS_SROM_MAXP5GA1);
14500 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_a1 =
14501 (s16) wlapi_getintvar(shim,
14502 BRCMS_SROM_PA5GW0A0);
14503 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_a1 =
14504 (s16) wlapi_getintvar(shim,
14505 BRCMS_SROM_PA5GW0A1);
14506 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b0 =
14507 (s16) wlapi_getintvar(shim,
14508 BRCMS_SROM_PA5GW1A0);
14509 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b0 =
14510 (s16) wlapi_getintvar(shim,
14511 BRCMS_SROM_PA5GW1A1);
14512 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b1 =
14513 (s16) wlapi_getintvar(shim,
14514 BRCMS_SROM_PA5GW2A0);
14515 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b1 =
14516 (s16) wlapi_getintvar(shim,
14517 BRCMS_SROM_PA5GW2A1);
14518 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_5gm =
14519 (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT5GA0);
14520 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm =
14521 (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT5GA1);
14522
14523 pi->ofdm5gpo =
14524 (u32) wlapi_getintvar(shim,
14525 BRCMS_SROM_OFDM5GPO);
14526
14527 pi->mcs5gpo[0] =
14528 (u16) wlapi_getintvar(shim,
14529 BRCMS_SROM_MCS5GPO0);
14530 pi->mcs5gpo[1] =
14531 (u16) wlapi_getintvar(shim,
14532 BRCMS_SROM_MCS5GPO1);
14533 pi->mcs5gpo[2] =
14534 (u16) wlapi_getintvar(shim,
14535 BRCMS_SROM_MCS5GPO2);
14536 pi->mcs5gpo[3] =
14537 (u16) wlapi_getintvar(shim,
14538 BRCMS_SROM_MCS5GPO3);
14539 pi->mcs5gpo[4] =
14540 (u16) wlapi_getintvar(shim,
14541 BRCMS_SROM_MCS5GPO4);
14542 pi->mcs5gpo[5] =
14543 (u16) wlapi_getintvar(shim,
14544 BRCMS_SROM_MCS5GPO5);
14545 pi->mcs5gpo[6] =
14546 (u16) wlapi_getintvar(shim,
14547 BRCMS_SROM_MCS5GPO6);
14548 pi->mcs5gpo[7] =
14549 (u16) wlapi_getintvar(shim,
14550 BRCMS_SROM_MCS5GPO7);
14551 break;
14552 case 2:
14553
14554 pi->nphy_txpid5gl[0] =
14555 (u8) wlapi_getintvar(shim,
14556 BRCMS_SROM_TXPID5GLA0);
14557 pi->nphy_txpid5gl[1] =
14558 (u8) wlapi_getintvar(shim,
14559 BRCMS_SROM_TXPID5GLA1);
14560 pi->nphy_pwrctrl_info[0].max_pwr_5gl =
14561 (s8) wlapi_getintvar(shim,
14562 BRCMS_SROM_MAXP5GLA0);
14563 pi->nphy_pwrctrl_info[1].max_pwr_5gl =
14564 (s8) wlapi_getintvar(shim,
14565 BRCMS_SROM_MAXP5GLA1);
14566 pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1 =
14567 (s16) wlapi_getintvar(shim,
14568 BRCMS_SROM_PA5GLW0A0);
14569 pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1 =
14570 (s16) wlapi_getintvar(shim,
14571 BRCMS_SROM_PA5GLW0A1);
14572 pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0 =
14573 (s16) wlapi_getintvar(shim,
14574 BRCMS_SROM_PA5GLW1A0);
14575 pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0 =
14576 (s16) wlapi_getintvar(shim,
14577 BRCMS_SROM_PA5GLW1A1);
14578 pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1 =
14579 (s16) wlapi_getintvar(shim,
14580 BRCMS_SROM_PA5GLW2A0);
14581 pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1 =
14582 (s16) wlapi_getintvar(shim,
14583 BRCMS_SROM_PA5GLW2A1);
14584 pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0;
14585 pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0;
14586
14587 pi->ofdm5glpo =
14588 (u32) wlapi_getintvar(shim,
14589 BRCMS_SROM_OFDM5GLPO);
14590
14591 pi->mcs5glpo[0] =
14592 (u16) wlapi_getintvar(shim,
14593 BRCMS_SROM_MCS5GLPO0);
14594 pi->mcs5glpo[1] =
14595 (u16) wlapi_getintvar(shim,
14596 BRCMS_SROM_MCS5GLPO1);
14597 pi->mcs5glpo[2] =
14598 (u16) wlapi_getintvar(shim,
14599 BRCMS_SROM_MCS5GLPO2);
14600 pi->mcs5glpo[3] =
14601 (u16) wlapi_getintvar(shim,
14602 BRCMS_SROM_MCS5GLPO3);
14603 pi->mcs5glpo[4] =
14604 (u16) wlapi_getintvar(shim,
14605 BRCMS_SROM_MCS5GLPO4);
14606 pi->mcs5glpo[5] =
14607 (u16) wlapi_getintvar(shim,
14608 BRCMS_SROM_MCS5GLPO5);
14609 pi->mcs5glpo[6] =
14610 (u16) wlapi_getintvar(shim,
14611 BRCMS_SROM_MCS5GLPO6);
14612 pi->mcs5glpo[7] =
14613 (u16) wlapi_getintvar(shim,
14614 BRCMS_SROM_MCS5GLPO7);
14615 break;
14616 case 3:
14617
14618 pi->nphy_txpid5gh[0] =
14619 (u8) wlapi_getintvar(shim,
14620 BRCMS_SROM_TXPID5GHA0);
14621 pi->nphy_txpid5gh[1] =
14622 (u8) wlapi_getintvar(shim,
14623 BRCMS_SROM_TXPID5GHA1);
14624 pi->nphy_pwrctrl_info[0].max_pwr_5gh =
14625 (s8) wlapi_getintvar(shim,
14626 BRCMS_SROM_MAXP5GHA0);
14627 pi->nphy_pwrctrl_info[1].max_pwr_5gh =
14628 (s8) wlapi_getintvar(shim,
14629 BRCMS_SROM_MAXP5GHA1);
14630 pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1 =
14631 (s16) wlapi_getintvar(shim,
14632 BRCMS_SROM_PA5GHW0A0);
14633 pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1 =
14634 (s16) wlapi_getintvar(shim,
14635 BRCMS_SROM_PA5GHW0A1);
14636 pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0 =
14637 (s16) wlapi_getintvar(shim,
14638 BRCMS_SROM_PA5GHW1A0);
14639 pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0 =
14640 (s16) wlapi_getintvar(shim,
14641 BRCMS_SROM_PA5GHW1A1);
14642 pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1 =
14643 (s16) wlapi_getintvar(shim,
14644 BRCMS_SROM_PA5GHW2A0);
14645 pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1 =
14646 (s16) wlapi_getintvar(shim,
14647 BRCMS_SROM_PA5GHW2A1);
14648 pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0;
14649 pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0;
14650
14651 pi->ofdm5ghpo =
14652 (u32) wlapi_getintvar(shim,
14653 BRCMS_SROM_OFDM5GHPO);
14654
14655 pi->mcs5ghpo[0] =
14656 (u16) wlapi_getintvar(shim,
14657 BRCMS_SROM_MCS5GHPO0);
14658 pi->mcs5ghpo[1] =
14659 (u16) wlapi_getintvar(shim,
14660 BRCMS_SROM_MCS5GHPO1);
14661 pi->mcs5ghpo[2] =
14662 (u16) wlapi_getintvar(shim,
14663 BRCMS_SROM_MCS5GHPO2);
14664 pi->mcs5ghpo[3] =
14665 (u16) wlapi_getintvar(shim,
14666 BRCMS_SROM_MCS5GHPO3);
14667 pi->mcs5ghpo[4] =
14668 (u16) wlapi_getintvar(shim,
14669 BRCMS_SROM_MCS5GHPO4);
14670 pi->mcs5ghpo[5] =
14671 (u16) wlapi_getintvar(shim,
14672 BRCMS_SROM_MCS5GHPO5);
14673 pi->mcs5ghpo[6] =
14674 (u16) wlapi_getintvar(shim,
14675 BRCMS_SROM_MCS5GHPO6);
14676 pi->mcs5ghpo[7] =
14677 (u16) wlapi_getintvar(shim,
14678 BRCMS_SROM_MCS5GHPO7);
14679 break;
14680 }
14681 }
14682
14683 wlc_phy_txpwr_apply_nphy(pi);
14684}
14685
14686static bool wlc_phy_txpwr_srom_read_nphy(struct brcms_phy *pi)
14687{
14688 struct phy_shim_info *shim = pi->sh->physhim;
14689
14690 pi->antswitch = (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWITCH);
14691 pi->aa2g = (u8) wlapi_getintvar(shim, BRCMS_SROM_AA2G);
14692 pi->aa5g = (u8) wlapi_getintvar(shim, BRCMS_SROM_AA5G);
14693
14694 pi->srom_fem2g.tssipos = (u8) wlapi_getintvar(shim,
14695 BRCMS_SROM_TSSIPOS2G);
14696 pi->srom_fem2g.extpagain = (u8) wlapi_getintvar(shim,
14697 BRCMS_SROM_EXTPAGAIN2G);
14698 pi->srom_fem2g.pdetrange = (u8) wlapi_getintvar(shim,
14699 BRCMS_SROM_PDETRANGE2G);
14700 pi->srom_fem2g.triso = (u8) wlapi_getintvar(shim, BRCMS_SROM_TRISO2G);
14701 pi->srom_fem2g.antswctrllut =
14702 (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL2G);
14703
14704 pi->srom_fem5g.tssipos = (u8) wlapi_getintvar(shim,
14705 BRCMS_SROM_TSSIPOS5G);
14706 pi->srom_fem5g.extpagain = (u8) wlapi_getintvar(shim,
14707 BRCMS_SROM_EXTPAGAIN5G);
14708 pi->srom_fem5g.pdetrange = (u8) wlapi_getintvar(shim,
14709 BRCMS_SROM_PDETRANGE5G);
14710 pi->srom_fem5g.triso = (u8) wlapi_getintvar(shim, BRCMS_SROM_TRISO5G);
14711 if (wlapi_getvar(shim, BRCMS_SROM_ANTSWCTL5G))
14712 pi->srom_fem5g.antswctrllut =
14713 (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL5G);
14714 else
14715 pi->srom_fem5g.antswctrllut =
14716 (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL2G);
14717
14718 wlc_phy_txpower_ipa_upd(pi);
14719
14720 pi->phy_txcore_disable_temp =
14721 (s16) wlapi_getintvar(shim, BRCMS_SROM_TEMPTHRESH);
14722 if (pi->phy_txcore_disable_temp == 0)
14723 pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
14724
14725 pi->phy_tempsense_offset = (s8) wlapi_getintvar(shim,
14726 BRCMS_SROM_TEMPOFFSET);
14727 if (pi->phy_tempsense_offset != 0) {
14728 if (pi->phy_tempsense_offset >
14729 (NPHY_SROM_TEMPSHIFT + NPHY_SROM_MAXTEMPOFFSET))
14730 pi->phy_tempsense_offset = NPHY_SROM_MAXTEMPOFFSET;
14731 else if (pi->phy_tempsense_offset < (NPHY_SROM_TEMPSHIFT +
14732 NPHY_SROM_MINTEMPOFFSET))
14733 pi->phy_tempsense_offset = NPHY_SROM_MINTEMPOFFSET;
14734 else
14735 pi->phy_tempsense_offset -= NPHY_SROM_TEMPSHIFT;
14736 }
14737
14738 pi->phy_txcore_enable_temp =
14739 pi->phy_txcore_disable_temp - PHY_HYSTERESIS_DELTATEMP;
14740
14741 pi->phycal_tempdelta =
14742 (u8) wlapi_getintvar(shim, BRCMS_SROM_PHYCAL_TEMPDELTA);
14743 if (pi->phycal_tempdelta > NPHY_CAL_MAXTEMPDELTA)
14744 pi->phycal_tempdelta = 0;
14745
14746 wlc_phy_txpwr_srom_read_ppr_nphy(pi);
14747
14748 return true;
14749}
14750
14751bool wlc_phy_attach_nphy(struct brcms_phy *pi)
14752{
14753 uint i;
14754
14755 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 6))
14756 pi->phyhang_avoid = true;
14757
14758 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
14759 pi->nphy_gband_spurwar_en = true;
14760 if (pi->sh->boardflags2 & BFL2_SPUR_WAR)
14761 pi->nphy_aband_spurwar_en = true;
14762 }
14763 if (NREV_GE(pi->pubpi.phy_rev, 6) && NREV_LT(pi->pubpi.phy_rev, 7)) {
14764 if (pi->sh->boardflags2 & BFL2_2G_SPUR_WAR)
14765 pi->nphy_gband_spurwar2_en = true;
14766 }
14767
14768 pi->n_preamble_override = AUTO;
14769 if (NREV_IS(pi->pubpi.phy_rev, 3) || NREV_IS(pi->pubpi.phy_rev, 4))
14770 pi->n_preamble_override = BRCMS_N_PREAMBLE_MIXEDMODE;
14771
14772 pi->nphy_txrx_chain = AUTO;
14773 pi->phy_scraminit = AUTO;
14774
14775 pi->nphy_rxcalparams = 0x010100B5;
14776
14777 pi->nphy_perical = PHY_PERICAL_MPHASE;
14778 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
14779 pi->mphase_txcal_numcmds = MPHASE_TXCAL_NUMCMDS;
14780
14781 pi->nphy_gain_boost = true;
14782 pi->nphy_elna_gain_config = false;
14783 pi->radio_is_on = false;
14784
14785 for (i = 0; i < pi->pubpi.phy_corenum; i++)
14786 pi->nphy_txpwrindex[i].index = AUTO;
14787
14788 wlc_phy_txpwrctrl_config_nphy(pi);
14789 if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
14790 pi->hwpwrctrl_capable = true;
14791
14792 pi->pi_fptr.init = wlc_phy_init_nphy;
14793 pi->pi_fptr.calinit = wlc_phy_cal_init_nphy;
14794 pi->pi_fptr.chanset = wlc_phy_chanspec_set_nphy;
14795 pi->pi_fptr.txpwrrecalc = wlc_phy_txpower_recalc_target_nphy;
14796
14797 if (!wlc_phy_txpwr_srom_read_nphy(pi))
14798 return false;
14799
14800 return true;
14801}
14802
14803static s32 get_rf_pwr_offset(struct brcms_phy *pi, s16 pga_gn, s16 pad_gn)
14804{
14805 s32 rfpwr_offset = 0;
14806
14807 if (CHSPEC_IS2G(pi->radio_chanspec)) {
14808 if ((pi->pubpi.radiorev == 3) ||
14809 (pi->pubpi.radiorev == 4) ||
14810 (pi->pubpi.radiorev == 6))
14811 rfpwr_offset = (s16)
14812 nphy_papd_padgain_dlt_2g_2057rev3n4
14813 [pad_gn];
14814 else if (pi->pubpi.radiorev == 5)
14815 rfpwr_offset = (s16)
14816 nphy_papd_padgain_dlt_2g_2057rev5
14817 [pad_gn];
14818 else if ((pi->pubpi.radiorev == 7)
14819 || (pi->pubpi.radiorev ==
14820 8))
14821 rfpwr_offset = (s16)
14822 nphy_papd_padgain_dlt_2g_2057rev7
14823 [pad_gn];
14824 } else {
14825 if ((pi->pubpi.radiorev == 3) ||
14826 (pi->pubpi.radiorev == 4) ||
14827 (pi->pubpi.radiorev == 6))
14828 rfpwr_offset = (s16)
14829 nphy_papd_pgagain_dlt_5g_2057
14830 [pga_gn];
14831 else if ((pi->pubpi.radiorev == 7)
14832 || (pi->pubpi.radiorev ==
14833 8))
14834 rfpwr_offset = (s16)
14835 nphy_papd_pgagain_dlt_5g_2057rev7
14836 [pga_gn];
14837 }
14838 return rfpwr_offset;
14839}
14840
14841static void wlc_phy_update_mimoconfig_nphy(struct brcms_phy *pi, s32 preamble)
14842{
14843 bool gf_preamble = false;
14844 u16 val;
14845
14846 if (preamble == BRCMS_N_PREAMBLE_GF)
14847 gf_preamble = true;
14848
14849 val = read_phy_reg(pi, 0xed);
14850
14851 val |= RX_GF_MM_AUTO;
14852 val &= ~RX_GF_OR_MM;
14853 if (gf_preamble)
14854 val |= RX_GF_OR_MM;
14855
14856 write_phy_reg(pi, 0xed, val);
14857}
14858
14859static void wlc_phy_ipa_set_tx_digi_filts_nphy(struct brcms_phy *pi)
14860{
14861 int j, type;
14862 u16 addr_offset[] = { 0x186, 0x195, 0x2c5};
14863
14864 for (type = 0; type < 3; type++) {
14865 for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++)
14866 write_phy_reg(pi, addr_offset[type] + j,
14867 NPHY_IPA_REV4_txdigi_filtcoeffs[type][j]);
14868 }
14869
14870 if (pi->bw == WL_CHANSPEC_BW_40) {
14871 for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++)
14872 write_phy_reg(pi, 0x186 + j,
14873 NPHY_IPA_REV4_txdigi_filtcoeffs[3][j]);
14874 } else {
14875 if (CHSPEC_IS5G(pi->radio_chanspec)) {
14876 for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++)
14877 write_phy_reg(pi, 0x186 + j,
14878 NPHY_IPA_REV4_txdigi_filtcoeffs[5][j]);
14879 }
14880
14881 if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
14882 for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++)
14883 write_phy_reg(pi, 0x2c5 + j,
14884 NPHY_IPA_REV4_txdigi_filtcoeffs[6][j]);
14885 }
14886 }
14887}
14888
14889static void wlc_phy_ipa_restore_tx_digi_filts_nphy(struct brcms_phy *pi)
14890{
14891 int j;
14892
14893 if (pi->bw == WL_CHANSPEC_BW_40) {
14894 for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++)
14895 write_phy_reg(pi, 0x195 + j,
14896 NPHY_IPA_REV4_txdigi_filtcoeffs[4][j]);
14897 } else {
14898 for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++)
14899 write_phy_reg(pi, 0x186 + j,
14900 NPHY_IPA_REV4_txdigi_filtcoeffs[3][j]);
14901 }
14902}
14903
14904static void
14905wlc_phy_set_rfseq_nphy(struct brcms_phy *pi, u8 cmd, u8 *events, u8 *dlys,
14906 u8 len)
14907{
14908 u32 t1_offset, t2_offset;
14909 u8 ctr;
14910 u8 end_event =
14911 NREV_GE(pi->pubpi.phy_rev,
14912 3) ? NPHY_REV3_RFSEQ_CMD_END : NPHY_RFSEQ_CMD_END;
14913 u8 end_dly = 1;
14914
14915 if (pi->phyhang_avoid)
14916 wlc_phy_stay_in_carriersearch_nphy(pi, true);
14917
14918 t1_offset = cmd << 4;
14919 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, len, t1_offset, 8,
14920 events);
14921 t2_offset = t1_offset + 0x080;
14922 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, len, t2_offset, 8,
14923 dlys);
14924
14925 for (ctr = len; ctr < 16; ctr++) {
14926 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
14927 t1_offset + ctr, 8, &end_event);
14928 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
14929 t2_offset + ctr, 8, &end_dly);
14930 }
14931
14932 if (pi->phyhang_avoid)
14933 wlc_phy_stay_in_carriersearch_nphy(pi, false);
14934}
14935
14936static u16 wlc_phy_read_lpf_bw_ctl_nphy(struct brcms_phy *pi, u16 offset)
14937{
14938 u16 lpf_bw_ctl_val = 0;
14939 u16 rx2tx_lpf_rc_lut_offset = 0;
14940
14941 if (offset == 0) {
14942 if (CHSPEC_IS40(pi->radio_chanspec))
14943 rx2tx_lpf_rc_lut_offset = 0x159;
14944 else
14945 rx2tx_lpf_rc_lut_offset = 0x154;
14946 } else {
14947 rx2tx_lpf_rc_lut_offset = offset;
14948 }
14949 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
14950 (u32) rx2tx_lpf_rc_lut_offset, 16,
14951 &lpf_bw_ctl_val);
14952
14953 lpf_bw_ctl_val = lpf_bw_ctl_val & 0x7;
14954
14955 return lpf_bw_ctl_val;
14956}
14957
14958static void
14959wlc_phy_rfctrl_override_nphy_rev7(struct brcms_phy *pi, u16 field, u16 value,
14960 u8 core_mask, u8 off, u8 override_id)
14961{
14962 u8 core_num;
14963 u16 addr = 0, en_addr = 0, val_addr = 0, en_mask = 0, val_mask = 0;
14964 u8 val_shift = 0;
14965
14966 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
14967 en_mask = field;
14968 for (core_num = 0; core_num < 2; core_num++) {
14969 if (override_id == NPHY_REV7_RFCTRLOVERRIDE_ID0) {
14970
14971 switch (field) {
14972 case (0x1 << 2):
14973 en_addr = (core_num == 0) ? 0xe7 : 0xec;
14974 val_addr = (core_num == 0) ? 0x7a :
14975 0x7d;
14976 val_mask = (0x1 << 1);
14977 val_shift = 1;
14978 break;
14979 case (0x1 << 3):
14980 en_addr = (core_num == 0) ? 0xe7 : 0xec;
14981 val_addr = (core_num == 0) ? 0x7a :
14982 0x7d;
14983 val_mask = (0x1 << 2);
14984 val_shift = 2;
14985 break;
14986 case (0x1 << 4):
14987 en_addr = (core_num == 0) ? 0xe7 : 0xec;
14988 val_addr = (core_num == 0) ? 0x7a :
14989 0x7d;
14990 val_mask = (0x1 << 4);
14991 val_shift = 4;
14992 break;
14993 case (0x1 << 5):
14994 en_addr = (core_num == 0) ? 0xe7 : 0xec;
14995 val_addr = (core_num == 0) ? 0x7a :
14996 0x7d;
14997 val_mask = (0x1 << 5);
14998 val_shift = 5;
14999 break;
15000 case (0x1 << 6):
15001 en_addr = (core_num == 0) ? 0xe7 : 0xec;
15002 val_addr = (core_num == 0) ? 0x7a :
15003 0x7d;
15004 val_mask = (0x1 << 6);
15005 val_shift = 6;
15006 break;
15007 case (0x1 << 7):
15008 en_addr = (core_num == 0) ? 0xe7 : 0xec;
15009 val_addr = (core_num == 0) ? 0x7a :
15010 0x7d;
15011 val_mask = (0x1 << 7);
15012 val_shift = 7;
15013 break;
15014 case (0x1 << 10):
15015 en_addr = (core_num == 0) ? 0xe7 : 0xec;
15016 val_addr = (core_num == 0) ? 0xf8 :
15017 0xfa;
15018 val_mask = (0x7 << 4);
15019 val_shift = 4;
15020 break;
15021 case (0x1 << 11):
15022 en_addr = (core_num == 0) ? 0xe7 : 0xec;
15023 val_addr = (core_num == 0) ? 0x7b :
15024 0x7e;
15025 val_mask = (0xffff << 0);
15026 val_shift = 0;
15027 break;
15028 case (0x1 << 12):
15029 en_addr = (core_num == 0) ? 0xe7 : 0xec;
15030 val_addr = (core_num == 0) ? 0x7c :
15031 0x7f;
15032 val_mask = (0xffff << 0);
15033 val_shift = 0;
15034 break;
15035 case (0x3 << 13):
15036 en_addr = (core_num == 0) ? 0xe7 : 0xec;
15037 val_addr = (core_num == 0) ? 0x348 :
15038 0x349;
15039 val_mask = (0xff << 0);
15040 val_shift = 0;
15041 break;
15042 case (0x1 << 13):
15043 en_addr = (core_num == 0) ? 0xe7 : 0xec;
15044 val_addr = (core_num == 0) ? 0x348 :
15045 0x349;
15046 val_mask = (0xf << 0);
15047 val_shift = 0;
15048 break;
15049 default:
15050 addr = 0xffff;
15051 break;
15052 }
15053 } else if (override_id ==
15054 NPHY_REV7_RFCTRLOVERRIDE_ID1) {
15055
15056 switch (field) {
15057 case (0x1 << 1):
15058 en_addr = (core_num == 0) ? 0x342 :
15059 0x343;
15060 val_addr = (core_num == 0) ? 0x340 :
15061 0x341;
15062 val_mask = (0x1 << 1);
15063 val_shift = 1;
15064 break;
15065 case (0x1 << 3):
15066 en_addr = (core_num == 0) ? 0x342 :
15067 0x343;
15068 val_addr = (core_num == 0) ? 0x340 :
15069 0x341;
15070 val_mask = (0x1 << 3);
15071 val_shift = 3;
15072 break;
15073 case (0x1 << 5):
15074 en_addr = (core_num == 0) ? 0x342 :
15075 0x343;
15076 val_addr = (core_num == 0) ? 0x340 :
15077 0x341;
15078 val_mask = (0x1 << 5);
15079 val_shift = 5;
15080 break;
15081 case (0x1 << 4):
15082 en_addr = (core_num == 0) ? 0x342 :
15083 0x343;
15084 val_addr = (core_num == 0) ? 0x340 :
15085 0x341;
15086 val_mask = (0x1 << 4);
15087 val_shift = 4;
15088 break;
15089 case (0x1 << 2):
15090
15091 en_addr = (core_num == 0) ? 0x342 :
15092 0x343;
15093 val_addr = (core_num == 0) ? 0x340 :
15094 0x341;
15095 val_mask = (0x1 << 2);
15096 val_shift = 2;
15097 break;
15098 case (0x1 << 7):
15099
15100 en_addr = (core_num == 0) ? 0x342 :
15101 0x343;
15102 val_addr = (core_num == 0) ? 0x340 :
15103 0x341;
15104 val_mask = (0x7 << 8);
15105 val_shift = 8;
15106 break;
15107 case (0x1 << 11):
15108 en_addr = (core_num == 0) ? 0x342 :
15109 0x343;
15110 val_addr = (core_num == 0) ? 0x340 :
15111 0x341;
15112 val_mask = (0x1 << 14);
15113 val_shift = 14;
15114 break;
15115 case (0x1 << 10):
15116 en_addr = (core_num == 0) ? 0x342 :
15117 0x343;
15118 val_addr = (core_num == 0) ? 0x340 :
15119 0x341;
15120 val_mask = (0x1 << 13);
15121 val_shift = 13;
15122 break;
15123 case (0x1 << 9):
15124 en_addr = (core_num == 0) ? 0x342 :
15125 0x343;
15126 val_addr = (core_num == 0) ? 0x340 :
15127 0x341;
15128 val_mask = (0x1 << 12);
15129 val_shift = 12;
15130 break;
15131 case (0x1 << 8):
15132 en_addr = (core_num == 0) ? 0x342 :
15133 0x343;
15134 val_addr = (core_num == 0) ? 0x340 :
15135 0x341;
15136 val_mask = (0x1 << 11);
15137 val_shift = 11;
15138 break;
15139 case (0x1 << 6):
15140 en_addr = (core_num == 0) ? 0x342 :
15141 0x343;
15142 val_addr = (core_num == 0) ? 0x340 :
15143 0x341;
15144 val_mask = (0x1 << 6);
15145 val_shift = 6;
15146 break;
15147 case (0x1 << 0):
15148 en_addr = (core_num == 0) ? 0x342 :
15149 0x343;
15150 val_addr = (core_num == 0) ? 0x340 :
15151 0x341;
15152 val_mask = (0x1 << 0);
15153 val_shift = 0;
15154 break;
15155 default:
15156 addr = 0xffff;
15157 break;
15158 }
15159 } else if (override_id ==
15160 NPHY_REV7_RFCTRLOVERRIDE_ID2) {
15161
15162 switch (field) {
15163 case (0x1 << 3):
15164 en_addr = (core_num == 0) ? 0x346 :
15165 0x347;
15166 val_addr = (core_num == 0) ? 0x344 :
15167 0x345;
15168 val_mask = (0x1 << 3);
15169 val_shift = 3;
15170 break;
15171 case (0x1 << 1):
15172 en_addr = (core_num == 0) ? 0x346 :
15173 0x347;
15174 val_addr = (core_num == 0) ? 0x344 :
15175 0x345;
15176 val_mask = (0x1 << 1);
15177 val_shift = 1;
15178 break;
15179 case (0x1 << 0):
15180 en_addr = (core_num == 0) ? 0x346 :
15181 0x347;
15182 val_addr = (core_num == 0) ? 0x344 :
15183 0x345;
15184 val_mask = (0x1 << 0);
15185 val_shift = 0;
15186 break;
15187 case (0x1 << 2):
15188 en_addr = (core_num == 0) ? 0x346 :
15189 0x347;
15190 val_addr = (core_num == 0) ? 0x344 :
15191 0x345;
15192 val_mask = (0x1 << 2);
15193 val_shift = 2;
15194 break;
15195 case (0x1 << 4):
15196 en_addr = (core_num == 0) ? 0x346 :
15197 0x347;
15198 val_addr = (core_num == 0) ? 0x344 :
15199 0x345;
15200 val_mask = (0x1 << 4);
15201 val_shift = 4;
15202 break;
15203 default:
15204 addr = 0xffff;
15205 break;
15206 }
15207 }
15208
15209 if (off) {
15210 and_phy_reg(pi, en_addr, ~en_mask);
15211 and_phy_reg(pi, val_addr, ~val_mask);
15212 } else {
15213
15214 if ((core_mask == 0)
15215 || (core_mask & (1 << core_num))) {
15216 or_phy_reg(pi, en_addr, en_mask);
15217
15218 if (addr != 0xffff)
15219 mod_phy_reg(pi, val_addr,
15220 val_mask,
15221 (value <<
15222 val_shift));
15223 }
15224 }
15225 }
15226 }
15227}
15228
15229static void wlc_phy_adjust_lnagaintbl_nphy(struct brcms_phy *pi)
15230{
15231 uint core;
15232 int ctr;
15233 s16 gain_delta[2];
15234 u8 curr_channel;
15235 u16 minmax_gain[2];
15236 u16 regval[4];
15237
15238 if (pi->phyhang_avoid)
15239 wlc_phy_stay_in_carriersearch_nphy(pi, true);
15240
15241 if (pi->nphy_gain_boost) {
15242 if ((CHSPEC_IS2G(pi->radio_chanspec))) {
15243
15244 gain_delta[0] = 6;
15245 gain_delta[1] = 6;
15246 } else {
15247
15248 curr_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
15249 gain_delta[0] =
15250 (s16)
15251 PHY_HW_ROUND(((nphy_lnagain_est0[0] *
15252 curr_channel) +
15253 nphy_lnagain_est0[1]), 13);
15254 gain_delta[1] =
15255 (s16)
15256 PHY_HW_ROUND(((nphy_lnagain_est1[0] *
15257 curr_channel) +
15258 nphy_lnagain_est1[1]), 13);
15259 }
15260 } else {
15261
15262 gain_delta[0] = 0;
15263 gain_delta[1] = 0;
15264 }
15265
15266 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
15267 if (pi->nphy_elna_gain_config) {
15268
15269 regval[0] = nphy_def_lnagains[2] + gain_delta[core];
15270 regval[1] = nphy_def_lnagains[3] + gain_delta[core];
15271 regval[2] = nphy_def_lnagains[3] + gain_delta[core];
15272 regval[3] = nphy_def_lnagains[3] + gain_delta[core];
15273 } else {
15274 for (ctr = 0; ctr < 4; ctr++)
15275 regval[ctr] =
15276 nphy_def_lnagains[ctr] +
15277 gain_delta[core];
15278 }
15279 wlc_phy_table_write_nphy(pi, core, 4, 8, 16, regval);
15280
15281 minmax_gain[core] =
15282 (u16) (nphy_def_lnagains[2] + gain_delta[core] + 4);
15283 }
15284
15285 mod_phy_reg(pi, 0x1e, (0xff << 0), (minmax_gain[0] << 0));
15286 mod_phy_reg(pi, 0x34, (0xff << 0), (minmax_gain[1] << 0));
15287
15288 if (pi->phyhang_avoid)
15289 wlc_phy_stay_in_carriersearch_nphy(pi, false);
15290}
15291
15292static void
15293wlc_phy_war_force_trsw_to_R_cliplo_nphy(struct brcms_phy *pi, u8 core)
15294{
15295 if (core == PHY_CORE_0) {
15296 write_phy_reg(pi, 0x38, 0x4);
15297 if (CHSPEC_IS2G(pi->radio_chanspec))
15298 write_phy_reg(pi, 0x37, 0x0060);
15299 else
15300 write_phy_reg(pi, 0x37, 0x1080);
15301 } else if (core == PHY_CORE_1) {
15302 write_phy_reg(pi, 0x2ae, 0x4);
15303 if (CHSPEC_IS2G(pi->radio_chanspec))
15304 write_phy_reg(pi, 0x2ad, 0x0060);
15305 else
15306 write_phy_reg(pi, 0x2ad, 0x1080);
15307 }
15308}
15309
15310static void wlc_phy_war_txchain_upd_nphy(struct brcms_phy *pi, u8 txchain)
15311{
15312 u8 txchain0, txchain1;
15313
15314 txchain0 = txchain & 0x1;
15315 txchain1 = (txchain & 0x2) >> 1;
15316 if (!txchain0)
15317 wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_0);
15318
15319 if (!txchain1)
15320 wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_1);
15321}
15322
15323static void wlc_phy_workarounds_nphy_gainctrl_2057_rev5(struct brcms_phy *pi)
15324{
15325 s8 lna1_gain_db[] = { 8, 13, 17, 22 };
15326 s8 lna2_gain_db[] = { -2, 7, 11, 15 };
15327 s8 tia_gain_db[] = { -4, -1, 2, 5, 5, 5, 5, 5, 5, 5 };
15328 s8 tia_gainbits[] = {
15329 0x0, 0x01, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
15330
15331 mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
15332 mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
15333
15334 mod_phy_reg(pi, 0x289, (0xff << 0), (0x46 << 0));
15335
15336 mod_phy_reg(pi, 0x283, (0xff << 0), (0x3c << 0));
15337 mod_phy_reg(pi, 0x280, (0xff << 0), (0x3c << 0));
15338
15339 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x8, 8,
15340 lna1_gain_db);
15341 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x8, 8,
15342 lna1_gain_db);
15343
15344 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10, 8,
15345 lna2_gain_db);
15346 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10, 8,
15347 lna2_gain_db);
15348
15349 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20, 8,
15350 tia_gain_db);
15351 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20, 8,
15352 tia_gain_db);
15353
15354 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20, 8,
15355 tia_gainbits);
15356 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20, 8,
15357 tia_gainbits);
15358
15359 write_phy_reg(pi, 0x37, 0x74);
15360 write_phy_reg(pi, 0x2ad, 0x74);
15361 write_phy_reg(pi, 0x38, 0x18);
15362 write_phy_reg(pi, 0x2ae, 0x18);
15363
15364 write_phy_reg(pi, 0x2b, 0xe8);
15365 write_phy_reg(pi, 0x41, 0xe8);
15366
15367 if (CHSPEC_IS20(pi->radio_chanspec)) {
15368
15369 mod_phy_reg(pi, 0x300, (0x3f << 0), (0x12 << 0));
15370 mod_phy_reg(pi, 0x301, (0x3f << 0), (0x12 << 0));
15371 } else {
15372
15373 mod_phy_reg(pi, 0x300, (0x3f << 0), (0x10 << 0));
15374 mod_phy_reg(pi, 0x301, (0x3f << 0), (0x10 << 0));
15375 }
15376}
15377
15378static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(struct brcms_phy *pi)
15379{
15380 u16 currband;
15381 s8 lna1G_gain_db_rev7[] = { 9, 14, 19, 24 };
15382 s8 *lna1_gain_db = NULL;
15383 s8 *lna1_gain_db_2 = NULL;
15384 s8 *lna2_gain_db = NULL;
15385 s8 tiaA_gain_db_rev7[] = { -9, -6, -3, 0, 3, 3, 3, 3, 3, 3 };
15386 s8 *tia_gain_db;
15387 s8 tiaA_gainbits_rev7[] = { 0, 1, 2, 3, 4, 4, 4, 4, 4, 4 };
15388 s8 *tia_gainbits;
15389 u16 rfseqA_init_gain_rev7[] = { 0x624f, 0x624f };
15390 u16 *rfseq_init_gain;
15391 u16 init_gaincode;
15392 u16 clip1hi_gaincode;
15393 u16 clip1md_gaincode = 0;
15394 u16 clip1md_gaincode_B;
15395 u16 clip1lo_gaincode;
15396 u16 clip1lo_gaincode_B;
15397 u8 crsminl_th = 0;
15398 u8 crsminu_th;
15399 u16 nbclip_th = 0;
15400 u8 w1clip_th;
15401 u16 freq;
15402 s8 nvar_baseline_offset0 = 0, nvar_baseline_offset1 = 0;
15403 u8 chg_nbclip_th = 0;
15404
15405 mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
15406 mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
15407
15408 currband = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
15409 if (currband == 0) {
15410
15411 lna1_gain_db = lna1G_gain_db_rev7;
15412
15413 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8, 8,
15414 lna1_gain_db);
15415 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8, 8,
15416 lna1_gain_db);
15417
15418 mod_phy_reg(pi, 0x283, (0xff << 0), (0x40 << 0));
15419
15420 if (CHSPEC_IS40(pi->radio_chanspec)) {
15421 mod_phy_reg(pi, 0x280, (0xff << 0), (0x3e << 0));
15422 mod_phy_reg(pi, 0x283, (0xff << 0), (0x3e << 0));
15423 }
15424
15425 mod_phy_reg(pi, 0x289, (0xff << 0), (0x46 << 0));
15426
15427 if (CHSPEC_IS20(pi->radio_chanspec)) {
15428 mod_phy_reg(pi, 0x300, (0x3f << 0), (13 << 0));
15429 mod_phy_reg(pi, 0x301, (0x3f << 0), (13 << 0));
15430 }
15431 } else {
15432
15433 init_gaincode = 0x9e;
15434 clip1hi_gaincode = 0x9e;
15435 clip1md_gaincode_B = 0x24;
15436 clip1lo_gaincode = 0x8a;
15437 clip1lo_gaincode_B = 8;
15438 rfseq_init_gain = rfseqA_init_gain_rev7;
15439
15440 tia_gain_db = tiaA_gain_db_rev7;
15441 tia_gainbits = tiaA_gainbits_rev7;
15442
15443 freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec));
15444 if (CHSPEC_IS20(pi->radio_chanspec)) {
15445
15446 w1clip_th = 25;
15447 clip1md_gaincode = 0x82;
15448
15449 if ((freq <= 5080) || (freq == 5825)) {
15450
15451 s8 lna1A_gain_db_rev7[] = { 11, 16, 20, 24 };
15452 s8 lna1A_gain_db_2_rev7[] = {
15453 11, 17, 22, 25};
15454 s8 lna2A_gain_db_rev7[] = { -1, 6, 10, 14 };
15455
15456 crsminu_th = 0x3e;
15457 lna1_gain_db = lna1A_gain_db_rev7;
15458 lna1_gain_db_2 = lna1A_gain_db_2_rev7;
15459 lna2_gain_db = lna2A_gain_db_rev7;
15460 } else if ((freq >= 5500) && (freq <= 5700)) {
15461
15462 s8 lna1A_gain_db_rev7[] = { 11, 17, 21, 25 };
15463 s8 lna1A_gain_db_2_rev7[] = {
15464 12, 18, 22, 26};
15465 s8 lna2A_gain_db_rev7[] = { 1, 8, 12, 16 };
15466
15467 crsminu_th = 0x45;
15468 clip1md_gaincode_B = 0x14;
15469 nbclip_th = 0xff;
15470 chg_nbclip_th = 1;
15471 lna1_gain_db = lna1A_gain_db_rev7;
15472 lna1_gain_db_2 = lna1A_gain_db_2_rev7;
15473 lna2_gain_db = lna2A_gain_db_rev7;
15474 } else {
15475
15476 s8 lna1A_gain_db_rev7[] = { 12, 18, 22, 26 };
15477 s8 lna1A_gain_db_2_rev7[] = {
15478 12, 18, 22, 26};
15479 s8 lna2A_gain_db_rev7[] = { -1, 6, 10, 14 };
15480
15481 crsminu_th = 0x41;
15482 lna1_gain_db = lna1A_gain_db_rev7;
15483 lna1_gain_db_2 = lna1A_gain_db_2_rev7;
15484 lna2_gain_db = lna2A_gain_db_rev7;
15485 }
15486
15487 if (freq <= 4920) {
15488 nvar_baseline_offset0 = 5;
15489 nvar_baseline_offset1 = 5;
15490 } else if ((freq > 4920) && (freq <= 5320)) {
15491 nvar_baseline_offset0 = 3;
15492 nvar_baseline_offset1 = 5;
15493 } else if ((freq > 5320) && (freq <= 5700)) {
15494 nvar_baseline_offset0 = 3;
15495 nvar_baseline_offset1 = 2;
15496 } else {
15497 nvar_baseline_offset0 = 4;
15498 nvar_baseline_offset1 = 0;
15499 }
15500 } else {
15501
15502 crsminu_th = 0x3a;
15503 crsminl_th = 0x3a;
15504 w1clip_th = 20;
15505
15506 if ((freq >= 4920) && (freq <= 5320)) {
15507 nvar_baseline_offset0 = 4;
15508 nvar_baseline_offset1 = 5;
15509 } else if ((freq > 5320) && (freq <= 5550)) {
15510 nvar_baseline_offset0 = 4;
15511 nvar_baseline_offset1 = 2;
15512 } else {
15513 nvar_baseline_offset0 = 5;
15514 nvar_baseline_offset1 = 3;
15515 }
15516 }
15517
15518 write_phy_reg(pi, 0x20, init_gaincode);
15519 write_phy_reg(pi, 0x2a7, init_gaincode);
15520
15521 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
15522 pi->pubpi.phy_corenum, 0x106, 16,
15523 rfseq_init_gain);
15524
15525 write_phy_reg(pi, 0x22, clip1hi_gaincode);
15526 write_phy_reg(pi, 0x2a9, clip1hi_gaincode);
15527
15528 write_phy_reg(pi, 0x36, clip1md_gaincode_B);
15529 write_phy_reg(pi, 0x2ac, clip1md_gaincode_B);
15530
15531 write_phy_reg(pi, 0x37, clip1lo_gaincode);
15532 write_phy_reg(pi, 0x2ad, clip1lo_gaincode);
15533 write_phy_reg(pi, 0x38, clip1lo_gaincode_B);
15534 write_phy_reg(pi, 0x2ae, clip1lo_gaincode_B);
15535
15536 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20, 8,
15537 tia_gain_db);
15538 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20, 8,
15539 tia_gain_db);
15540
15541 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20, 8,
15542 tia_gainbits);
15543 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20, 8,
15544 tia_gainbits);
15545
15546 mod_phy_reg(pi, 0x283, (0xff << 0), (crsminu_th << 0));
15547
15548 if (chg_nbclip_th == 1) {
15549 write_phy_reg(pi, 0x2b, nbclip_th);
15550 write_phy_reg(pi, 0x41, nbclip_th);
15551 }
15552
15553 mod_phy_reg(pi, 0x300, (0x3f << 0), (w1clip_th << 0));
15554 mod_phy_reg(pi, 0x301, (0x3f << 0), (w1clip_th << 0));
15555
15556 mod_phy_reg(pi, 0x2e4,
15557 (0x3f << 0), (nvar_baseline_offset0 << 0));
15558
15559 mod_phy_reg(pi, 0x2e4,
15560 (0x3f << 6), (nvar_baseline_offset1 << 6));
15561
15562 if (CHSPEC_IS20(pi->radio_chanspec)) {
15563
15564 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8, 8,
15565 lna1_gain_db);
15566 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8, 8,
15567 lna1_gain_db_2);
15568
15569 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10,
15570 8, lna2_gain_db);
15571 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10,
15572 8, lna2_gain_db);
15573
15574 write_phy_reg(pi, 0x24, clip1md_gaincode);
15575 write_phy_reg(pi, 0x2ab, clip1md_gaincode);
15576 } else {
15577 mod_phy_reg(pi, 0x280, (0xff << 0), (crsminl_th << 0));
15578 }
15579 }
15580}
15581
15582static void wlc_phy_workarounds_nphy_gainctrl(struct brcms_phy *pi)
15583{
15584 u16 w1th, hpf_code, currband;
15585 int ctr;
15586 u8 rfseq_updategainu_events[] = {
15587 NPHY_RFSEQ_CMD_RX_GAIN,
15588 NPHY_RFSEQ_CMD_CLR_HIQ_DIS,
15589 NPHY_RFSEQ_CMD_SET_HPF_BW
15590 };
15591 u8 rfseq_updategainu_dlys[] = { 10, 30, 1 };
15592 s8 lna1G_gain_db[] = { 7, 11, 16, 23 };
15593 s8 lna1G_gain_db_rev4[] = { 8, 12, 17, 25 };
15594 s8 lna1G_gain_db_rev5[] = { 9, 13, 18, 26 };
15595 s8 lna1G_gain_db_rev6[] = { 8, 13, 18, 25 };
15596 s8 lna1G_gain_db_rev6_224B0[] = { 10, 14, 19, 27 };
15597 s8 lna1A_gain_db[] = { 7, 11, 17, 23 };
15598 s8 lna1A_gain_db_rev4[] = { 8, 12, 18, 23 };
15599 s8 lna1A_gain_db_rev5[] = { 6, 10, 16, 21 };
15600 s8 lna1A_gain_db_rev6[] = { 6, 10, 16, 21 };
15601 s8 *lna1_gain_db = NULL;
15602 s8 lna2G_gain_db[] = { -5, 6, 10, 14 };
15603 s8 lna2G_gain_db_rev5[] = { -3, 7, 11, 16 };
15604 s8 lna2G_gain_db_rev6[] = { -5, 6, 10, 14 };
15605 s8 lna2G_gain_db_rev6_224B0[] = { -5, 6, 10, 15 };
15606 s8 lna2A_gain_db[] = { -6, 2, 6, 10 };
15607 s8 lna2A_gain_db_rev4[] = { -5, 2, 6, 10 };
15608 s8 lna2A_gain_db_rev5[] = { -7, 0, 4, 8 };
15609 s8 lna2A_gain_db_rev6[] = { -7, 0, 4, 8 };
15610 s8 *lna2_gain_db = NULL;
15611 s8 tiaG_gain_db[] = {
15612 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A };
15613 s8 tiaA_gain_db[] = {
15614 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 };
15615 s8 tiaA_gain_db_rev4[] = {
15616 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
15617 s8 tiaA_gain_db_rev5[] = {
15618 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
15619 s8 tiaA_gain_db_rev6[] = {
15620 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
15621 s8 *tia_gain_db;
15622 s8 tiaG_gainbits[] = {
15623 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
15624 s8 tiaA_gainbits[] = {
15625 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 };
15626 s8 tiaA_gainbits_rev4[] = {
15627 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
15628 s8 tiaA_gainbits_rev5[] = {
15629 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
15630 s8 tiaA_gainbits_rev6[] = {
15631 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
15632 s8 *tia_gainbits;
15633 s8 lpf_gain_db[] = { 0x00, 0x06, 0x0c, 0x12, 0x12, 0x12 };
15634 s8 lpf_gainbits[] = { 0x00, 0x01, 0x02, 0x03, 0x03, 0x03 };
15635 u16 rfseqG_init_gain[] = { 0x613f, 0x613f, 0x613f, 0x613f };
15636 u16 rfseqG_init_gain_rev4[] = { 0x513f, 0x513f, 0x513f, 0x513f };
15637 u16 rfseqG_init_gain_rev5[] = { 0x413f, 0x413f, 0x413f, 0x413f };
15638 u16 rfseqG_init_gain_rev5_elna[] = {
15639 0x013f, 0x013f, 0x013f, 0x013f };
15640 u16 rfseqG_init_gain_rev6[] = { 0x513f, 0x513f };
15641 u16 rfseqG_init_gain_rev6_224B0[] = { 0x413f, 0x413f };
15642 u16 rfseqG_init_gain_rev6_elna[] = { 0x113f, 0x113f };
15643 u16 rfseqA_init_gain[] = { 0x516f, 0x516f, 0x516f, 0x516f };
15644 u16 rfseqA_init_gain_rev4[] = { 0x614f, 0x614f, 0x614f, 0x614f };
15645 u16 rfseqA_init_gain_rev4_elna[] = {
15646 0x314f, 0x314f, 0x314f, 0x314f };
15647 u16 rfseqA_init_gain_rev5[] = { 0x714f, 0x714f, 0x714f, 0x714f };
15648 u16 rfseqA_init_gain_rev6[] = { 0x714f, 0x714f };
15649 u16 *rfseq_init_gain;
15650 u16 initG_gaincode = 0x627e;
15651 u16 initG_gaincode_rev4 = 0x527e;
15652 u16 initG_gaincode_rev5 = 0x427e;
15653 u16 initG_gaincode_rev5_elna = 0x027e;
15654 u16 initG_gaincode_rev6 = 0x527e;
15655 u16 initG_gaincode_rev6_224B0 = 0x427e;
15656 u16 initG_gaincode_rev6_elna = 0x127e;
15657 u16 initA_gaincode = 0x52de;
15658 u16 initA_gaincode_rev4 = 0x629e;
15659 u16 initA_gaincode_rev4_elna = 0x329e;
15660 u16 initA_gaincode_rev5 = 0x729e;
15661 u16 initA_gaincode_rev6 = 0x729e;
15662 u16 init_gaincode;
15663 u16 clip1hiG_gaincode = 0x107e;
15664 u16 clip1hiG_gaincode_rev4 = 0x007e;
15665 u16 clip1hiG_gaincode_rev5 = 0x1076;
15666 u16 clip1hiG_gaincode_rev6 = 0x007e;
15667 u16 clip1hiA_gaincode = 0x00de;
15668 u16 clip1hiA_gaincode_rev4 = 0x029e;
15669 u16 clip1hiA_gaincode_rev5 = 0x029e;
15670 u16 clip1hiA_gaincode_rev6 = 0x029e;
15671 u16 clip1hi_gaincode;
15672 u16 clip1mdG_gaincode = 0x0066;
15673 u16 clip1mdA_gaincode = 0x00ca;
15674 u16 clip1mdA_gaincode_rev4 = 0x1084;
15675 u16 clip1mdA_gaincode_rev5 = 0x2084;
15676 u16 clip1mdA_gaincode_rev6 = 0x2084;
15677 u16 clip1md_gaincode = 0;
15678 u16 clip1loG_gaincode = 0x0074;
15679 u16 clip1loG_gaincode_rev5[] = {
15680 0x0062, 0x0064, 0x006a, 0x106a, 0x106c, 0x1074, 0x107c, 0x207c
15681 };
15682 u16 clip1loG_gaincode_rev6[] = {
15683 0x106a, 0x106c, 0x1074, 0x107c, 0x007e, 0x107e, 0x207e, 0x307e
15684 };
15685 u16 clip1loG_gaincode_rev6_224B0 = 0x1074;
15686 u16 clip1loA_gaincode = 0x00cc;
15687 u16 clip1loA_gaincode_rev4 = 0x0086;
15688 u16 clip1loA_gaincode_rev5 = 0x2086;
15689 u16 clip1loA_gaincode_rev6 = 0x2086;
15690 u16 clip1lo_gaincode;
15691 u8 crsminG_th = 0x18;
15692 u8 crsminG_th_rev5 = 0x18;
15693 u8 crsminG_th_rev6 = 0x18;
15694 u8 crsminA_th = 0x1e;
15695 u8 crsminA_th_rev4 = 0x24;
15696 u8 crsminA_th_rev5 = 0x24;
15697 u8 crsminA_th_rev6 = 0x24;
15698 u8 crsmin_th;
15699 u8 crsminlG_th = 0x18;
15700 u8 crsminlG_th_rev5 = 0x18;
15701 u8 crsminlG_th_rev6 = 0x18;
15702 u8 crsminlA_th = 0x1e;
15703 u8 crsminlA_th_rev4 = 0x24;
15704 u8 crsminlA_th_rev5 = 0x24;
15705 u8 crsminlA_th_rev6 = 0x24;
15706 u8 crsminl_th = 0;
15707 u8 crsminuG_th = 0x18;
15708 u8 crsminuG_th_rev5 = 0x18;
15709 u8 crsminuG_th_rev6 = 0x18;
15710 u8 crsminuA_th = 0x1e;
15711 u8 crsminuA_th_rev4 = 0x24;
15712 u8 crsminuA_th_rev5 = 0x24;
15713 u8 crsminuA_th_rev6 = 0x24;
15714 u8 crsminuA_th_rev6_224B0 = 0x2d;
15715 u8 crsminu_th;
15716 u16 nbclipG_th = 0x20d;
15717 u16 nbclipG_th_rev4 = 0x1a1;
15718 u16 nbclipG_th_rev5 = 0x1d0;
15719 u16 nbclipG_th_rev6 = 0x1d0;
15720 u16 nbclipA_th = 0x1a1;
15721 u16 nbclipA_th_rev4 = 0x107;
15722 u16 nbclipA_th_rev5 = 0x0a9;
15723 u16 nbclipA_th_rev6 = 0x0f0;
15724 u16 nbclip_th = 0;
15725 u8 w1clipG_th = 5;
15726 u8 w1clipG_th_rev5 = 9;
15727 u8 w1clipG_th_rev6 = 5;
15728 u8 w1clipA_th = 25, w1clip_th;
15729 u8 rssi_gain_default = 0x50;
15730 u8 rssiG_gain_rev6_224B0 = 0x50;
15731 u8 rssiA_gain_rev5 = 0x90;
15732 u8 rssiA_gain_rev6 = 0x90;
15733 u8 rssi_gain;
15734 u16 regval[21];
15735 u8 triso;
15736
15737 triso = (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.triso :
15738 pi->srom_fem2g.triso;
15739
15740 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
15741 if (pi->pubpi.radiorev == 5) {
15742 wlc_phy_workarounds_nphy_gainctrl_2057_rev5(pi);
15743 } else if (pi->pubpi.radiorev == 7) {
15744 wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
15745
15746 mod_phy_reg(pi, 0x283, (0xff << 0), (0x44 << 0));
15747 mod_phy_reg(pi, 0x280, (0xff << 0), (0x44 << 0));
15748
15749 } else if ((pi->pubpi.radiorev == 3)
15750 || (pi->pubpi.radiorev == 8)) {
15751 wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
15752
15753 if (pi->pubpi.radiorev == 8) {
15754 mod_phy_reg(pi, 0x283,
15755 (0xff << 0), (0x44 << 0));
15756 mod_phy_reg(pi, 0x280,
15757 (0xff << 0), (0x44 << 0));
15758 }
15759 } else {
15760 wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
15761 }
15762 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
15763
15764 mod_phy_reg(pi, 0xa0, (0x1 << 6), (1 << 6));
15765
15766 mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
15767 mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
15768
15769 currband =
15770 read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
15771 if (currband == 0) {
15772 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
15773 if (pi->pubpi.radiorev == 11) {
15774 lna1_gain_db = lna1G_gain_db_rev6_224B0;
15775 lna2_gain_db = lna2G_gain_db_rev6_224B0;
15776 rfseq_init_gain =
15777 rfseqG_init_gain_rev6_224B0;
15778 init_gaincode =
15779 initG_gaincode_rev6_224B0;
15780 clip1hi_gaincode =
15781 clip1hiG_gaincode_rev6;
15782 clip1lo_gaincode =
15783 clip1loG_gaincode_rev6_224B0;
15784 nbclip_th = nbclipG_th_rev6;
15785 w1clip_th = w1clipG_th_rev6;
15786 crsmin_th = crsminG_th_rev6;
15787 crsminl_th = crsminlG_th_rev6;
15788 crsminu_th = crsminuG_th_rev6;
15789 rssi_gain = rssiG_gain_rev6_224B0;
15790 } else {
15791 lna1_gain_db = lna1G_gain_db_rev6;
15792 lna2_gain_db = lna2G_gain_db_rev6;
15793 if (pi->sh->boardflags & BFL_EXTLNA) {
15794
15795 rfseq_init_gain =
15796 rfseqG_init_gain_rev6_elna;
15797 init_gaincode =
15798 initG_gaincode_rev6_elna;
15799 } else {
15800 rfseq_init_gain =
15801 rfseqG_init_gain_rev6;
15802 init_gaincode =
15803 initG_gaincode_rev6;
15804 }
15805 clip1hi_gaincode =
15806 clip1hiG_gaincode_rev6;
15807 switch (triso) {
15808 case 0:
15809 clip1lo_gaincode =
15810 clip1loG_gaincode_rev6
15811 [0];
15812 break;
15813 case 1:
15814 clip1lo_gaincode =
15815 clip1loG_gaincode_rev6
15816 [1];
15817 break;
15818 case 2:
15819 clip1lo_gaincode =
15820 clip1loG_gaincode_rev6
15821 [2];
15822 break;
15823 case 3:
15824 default:
15825
15826 clip1lo_gaincode =
15827 clip1loG_gaincode_rev6
15828 [3];
15829 break;
15830 case 4:
15831 clip1lo_gaincode =
15832 clip1loG_gaincode_rev6
15833 [4];
15834 break;
15835 case 5:
15836 clip1lo_gaincode =
15837 clip1loG_gaincode_rev6
15838 [5];
15839 break;
15840 case 6:
15841 clip1lo_gaincode =
15842 clip1loG_gaincode_rev6
15843 [6];
15844 break;
15845 case 7:
15846 clip1lo_gaincode =
15847 clip1loG_gaincode_rev6
15848 [7];
15849 break;
15850 }
15851 nbclip_th = nbclipG_th_rev6;
15852 w1clip_th = w1clipG_th_rev6;
15853 crsmin_th = crsminG_th_rev6;
15854 crsminl_th = crsminlG_th_rev6;
15855 crsminu_th = crsminuG_th_rev6;
15856 rssi_gain = rssi_gain_default;
15857 }
15858 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
15859 lna1_gain_db = lna1G_gain_db_rev5;
15860 lna2_gain_db = lna2G_gain_db_rev5;
15861 if (pi->sh->boardflags & BFL_EXTLNA) {
15862
15863 rfseq_init_gain =
15864 rfseqG_init_gain_rev5_elna;
15865 init_gaincode =
15866 initG_gaincode_rev5_elna;
15867 } else {
15868 rfseq_init_gain = rfseqG_init_gain_rev5;
15869 init_gaincode = initG_gaincode_rev5;
15870 }
15871 clip1hi_gaincode = clip1hiG_gaincode_rev5;
15872 switch (triso) {
15873 case 0:
15874 clip1lo_gaincode =
15875 clip1loG_gaincode_rev5[0];
15876 break;
15877 case 1:
15878 clip1lo_gaincode =
15879 clip1loG_gaincode_rev5[1];
15880 break;
15881 case 2:
15882 clip1lo_gaincode =
15883 clip1loG_gaincode_rev5[2];
15884 break;
15885 case 3:
15886
15887 clip1lo_gaincode =
15888 clip1loG_gaincode_rev5[3];
15889 break;
15890 case 4:
15891 clip1lo_gaincode =
15892 clip1loG_gaincode_rev5[4];
15893 break;
15894 case 5:
15895 clip1lo_gaincode =
15896 clip1loG_gaincode_rev5[5];
15897 break;
15898 case 6:
15899 clip1lo_gaincode =
15900 clip1loG_gaincode_rev5[6];
15901 break;
15902 case 7:
15903 clip1lo_gaincode =
15904 clip1loG_gaincode_rev5[7];
15905 break;
15906 default:
15907 clip1lo_gaincode =
15908 clip1loG_gaincode_rev5[3];
15909 break;
15910 }
15911 nbclip_th = nbclipG_th_rev5;
15912 w1clip_th = w1clipG_th_rev5;
15913 crsmin_th = crsminG_th_rev5;
15914 crsminl_th = crsminlG_th_rev5;
15915 crsminu_th = crsminuG_th_rev5;
15916 rssi_gain = rssi_gain_default;
15917 } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
15918 lna1_gain_db = lna1G_gain_db_rev4;
15919 lna2_gain_db = lna2G_gain_db;
15920 rfseq_init_gain = rfseqG_init_gain_rev4;
15921 init_gaincode = initG_gaincode_rev4;
15922 clip1hi_gaincode = clip1hiG_gaincode_rev4;
15923 clip1lo_gaincode = clip1loG_gaincode;
15924 nbclip_th = nbclipG_th_rev4;
15925 w1clip_th = w1clipG_th;
15926 crsmin_th = crsminG_th;
15927 crsminl_th = crsminlG_th;
15928 crsminu_th = crsminuG_th;
15929 rssi_gain = rssi_gain_default;
15930 } else {
15931 lna1_gain_db = lna1G_gain_db;
15932 lna2_gain_db = lna2G_gain_db;
15933 rfseq_init_gain = rfseqG_init_gain;
15934 init_gaincode = initG_gaincode;
15935 clip1hi_gaincode = clip1hiG_gaincode;
15936 clip1lo_gaincode = clip1loG_gaincode;
15937 nbclip_th = nbclipG_th;
15938 w1clip_th = w1clipG_th;
15939 crsmin_th = crsminG_th;
15940 crsminl_th = crsminlG_th;
15941 crsminu_th = crsminuG_th;
15942 rssi_gain = rssi_gain_default;
15943 }
15944 tia_gain_db = tiaG_gain_db;
15945 tia_gainbits = tiaG_gainbits;
15946 clip1md_gaincode = clip1mdG_gaincode;
15947 } else {
15948 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
15949 lna1_gain_db = lna1A_gain_db_rev6;
15950 lna2_gain_db = lna2A_gain_db_rev6;
15951 tia_gain_db = tiaA_gain_db_rev6;
15952 tia_gainbits = tiaA_gainbits_rev6;
15953 rfseq_init_gain = rfseqA_init_gain_rev6;
15954 init_gaincode = initA_gaincode_rev6;
15955 clip1hi_gaincode = clip1hiA_gaincode_rev6;
15956 clip1md_gaincode = clip1mdA_gaincode_rev6;
15957 clip1lo_gaincode = clip1loA_gaincode_rev6;
15958 crsmin_th = crsminA_th_rev6;
15959 crsminl_th = crsminlA_th_rev6;
15960 if ((pi->pubpi.radiorev == 11) &&
15961 (CHSPEC_IS40(pi->radio_chanspec) == 0))
15962 crsminu_th = crsminuA_th_rev6_224B0;
15963 else
15964 crsminu_th = crsminuA_th_rev6;
15965
15966 nbclip_th = nbclipA_th_rev6;
15967 rssi_gain = rssiA_gain_rev6;
15968 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
15969 lna1_gain_db = lna1A_gain_db_rev5;
15970 lna2_gain_db = lna2A_gain_db_rev5;
15971 tia_gain_db = tiaA_gain_db_rev5;
15972 tia_gainbits = tiaA_gainbits_rev5;
15973 rfseq_init_gain = rfseqA_init_gain_rev5;
15974 init_gaincode = initA_gaincode_rev5;
15975 clip1hi_gaincode = clip1hiA_gaincode_rev5;
15976 clip1md_gaincode = clip1mdA_gaincode_rev5;
15977 clip1lo_gaincode = clip1loA_gaincode_rev5;
15978 crsmin_th = crsminA_th_rev5;
15979 crsminl_th = crsminlA_th_rev5;
15980 crsminu_th = crsminuA_th_rev5;
15981 nbclip_th = nbclipA_th_rev5;
15982 rssi_gain = rssiA_gain_rev5;
15983 } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
15984 lna1_gain_db = lna1A_gain_db_rev4;
15985 lna2_gain_db = lna2A_gain_db_rev4;
15986 tia_gain_db = tiaA_gain_db_rev4;
15987 tia_gainbits = tiaA_gainbits_rev4;
15988 if (pi->sh->boardflags & BFL_EXTLNA_5GHz) {
15989
15990 rfseq_init_gain =
15991 rfseqA_init_gain_rev4_elna;
15992 init_gaincode =
15993 initA_gaincode_rev4_elna;
15994 } else {
15995 rfseq_init_gain = rfseqA_init_gain_rev4;
15996 init_gaincode = initA_gaincode_rev4;
15997 }
15998 clip1hi_gaincode = clip1hiA_gaincode_rev4;
15999 clip1md_gaincode = clip1mdA_gaincode_rev4;
16000 clip1lo_gaincode = clip1loA_gaincode_rev4;
16001 crsmin_th = crsminA_th_rev4;
16002 crsminl_th = crsminlA_th_rev4;
16003 crsminu_th = crsminuA_th_rev4;
16004 nbclip_th = nbclipA_th_rev4;
16005 rssi_gain = rssi_gain_default;
16006 } else {
16007 lna1_gain_db = lna1A_gain_db;
16008 lna2_gain_db = lna2A_gain_db;
16009 tia_gain_db = tiaA_gain_db;
16010 tia_gainbits = tiaA_gainbits;
16011 rfseq_init_gain = rfseqA_init_gain;
16012 init_gaincode = initA_gaincode;
16013 clip1hi_gaincode = clip1hiA_gaincode;
16014 clip1md_gaincode = clip1mdA_gaincode;
16015 clip1lo_gaincode = clip1loA_gaincode;
16016 crsmin_th = crsminA_th;
16017 crsminl_th = crsminlA_th;
16018 crsminu_th = crsminuA_th;
16019 nbclip_th = nbclipA_th;
16020 rssi_gain = rssi_gain_default;
16021 }
16022 w1clip_th = w1clipA_th;
16023 }
16024
16025 write_radio_reg(pi,
16026 (RADIO_2056_RX_BIASPOLE_LNAG1_IDAC |
16027 RADIO_2056_RX0), 0x17);
16028 write_radio_reg(pi,
16029 (RADIO_2056_RX_BIASPOLE_LNAG1_IDAC |
16030 RADIO_2056_RX1), 0x17);
16031
16032 write_radio_reg(pi, (RADIO_2056_RX_LNAG2_IDAC | RADIO_2056_RX0),
16033 0xf0);
16034 write_radio_reg(pi, (RADIO_2056_RX_LNAG2_IDAC | RADIO_2056_RX1),
16035 0xf0);
16036
16037 write_radio_reg(pi, (RADIO_2056_RX_RSSI_POLE | RADIO_2056_RX0),
16038 0x0);
16039 write_radio_reg(pi, (RADIO_2056_RX_RSSI_POLE | RADIO_2056_RX1),
16040 0x0);
16041
16042 write_radio_reg(pi, (RADIO_2056_RX_RSSI_GAIN | RADIO_2056_RX0),
16043 rssi_gain);
16044 write_radio_reg(pi, (RADIO_2056_RX_RSSI_GAIN | RADIO_2056_RX1),
16045 rssi_gain);
16046
16047 write_radio_reg(pi,
16048 (RADIO_2056_RX_BIASPOLE_LNAA1_IDAC |
16049 RADIO_2056_RX0), 0x17);
16050 write_radio_reg(pi,
16051 (RADIO_2056_RX_BIASPOLE_LNAA1_IDAC |
16052 RADIO_2056_RX1), 0x17);
16053
16054 write_radio_reg(pi, (RADIO_2056_RX_LNAA2_IDAC | RADIO_2056_RX0),
16055 0xFF);
16056 write_radio_reg(pi, (RADIO_2056_RX_LNAA2_IDAC | RADIO_2056_RX1),
16057 0xFF);
16058
16059 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8,
16060 8, lna1_gain_db);
16061 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8,
16062 8, lna1_gain_db);
16063
16064 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10,
16065 8, lna2_gain_db);
16066 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10,
16067 8, lna2_gain_db);
16068
16069 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20,
16070 8, tia_gain_db);
16071 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20,
16072 8, tia_gain_db);
16073
16074 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20,
16075 8, tia_gainbits);
16076 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20,
16077 8, tia_gainbits);
16078
16079 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 6, 0x40,
16080 8, &lpf_gain_db);
16081 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 6, 0x40,
16082 8, &lpf_gain_db);
16083 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 6, 0x40,
16084 8, &lpf_gainbits);
16085 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 6, 0x40,
16086 8, &lpf_gainbits);
16087
16088 write_phy_reg(pi, 0x20, init_gaincode);
16089 write_phy_reg(pi, 0x2a7, init_gaincode);
16090
16091 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
16092 pi->pubpi.phy_corenum, 0x106, 16,
16093 rfseq_init_gain);
16094
16095 write_phy_reg(pi, 0x22, clip1hi_gaincode);
16096 write_phy_reg(pi, 0x2a9, clip1hi_gaincode);
16097
16098 write_phy_reg(pi, 0x24, clip1md_gaincode);
16099 write_phy_reg(pi, 0x2ab, clip1md_gaincode);
16100
16101 write_phy_reg(pi, 0x37, clip1lo_gaincode);
16102 write_phy_reg(pi, 0x2ad, clip1lo_gaincode);
16103
16104 mod_phy_reg(pi, 0x27d, (0xff << 0), (crsmin_th << 0));
16105 mod_phy_reg(pi, 0x280, (0xff << 0), (crsminl_th << 0));
16106 mod_phy_reg(pi, 0x283, (0xff << 0), (crsminu_th << 0));
16107
16108 write_phy_reg(pi, 0x2b, nbclip_th);
16109 write_phy_reg(pi, 0x41, nbclip_th);
16110
16111 mod_phy_reg(pi, 0x27, (0x3f << 0), (w1clip_th << 0));
16112 mod_phy_reg(pi, 0x3d, (0x3f << 0), (w1clip_th << 0));
16113
16114 write_phy_reg(pi, 0x150, 0x809c);
16115
16116 } else {
16117
16118 mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
16119 mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
16120
16121 write_phy_reg(pi, 0x2b, 0x84);
16122 write_phy_reg(pi, 0x41, 0x84);
16123
16124 if (CHSPEC_IS20(pi->radio_chanspec)) {
16125 write_phy_reg(pi, 0x6b, 0x2b);
16126 write_phy_reg(pi, 0x6c, 0x2b);
16127 write_phy_reg(pi, 0x6d, 0x9);
16128 write_phy_reg(pi, 0x6e, 0x9);
16129 }
16130
16131 w1th = NPHY_RSSICAL_W1_TARGET - 4;
16132 mod_phy_reg(pi, 0x27, (0x3f << 0), (w1th << 0));
16133 mod_phy_reg(pi, 0x3d, (0x3f << 0), (w1th << 0));
16134
16135 if (CHSPEC_IS20(pi->radio_chanspec)) {
16136 mod_phy_reg(pi, 0x1c, (0x1f << 0), (0x1 << 0));
16137 mod_phy_reg(pi, 0x32, (0x1f << 0), (0x1 << 0));
16138
16139 mod_phy_reg(pi, 0x1d, (0x1f << 0), (0x1 << 0));
16140 mod_phy_reg(pi, 0x33, (0x1f << 0), (0x1 << 0));
16141 }
16142
16143 write_phy_reg(pi, 0x150, 0x809c);
16144
16145 if (pi->nphy_gain_boost)
16146 if ((CHSPEC_IS2G(pi->radio_chanspec)) &&
16147 (CHSPEC_IS40(pi->radio_chanspec)))
16148 hpf_code = 4;
16149 else
16150 hpf_code = 5;
16151 else if (CHSPEC_IS40(pi->radio_chanspec))
16152 hpf_code = 6;
16153 else
16154 hpf_code = 7;
16155
16156 mod_phy_reg(pi, 0x20, (0x1f << 7), (hpf_code << 7));
16157 mod_phy_reg(pi, 0x36, (0x1f << 7), (hpf_code << 7));
16158
16159 for (ctr = 0; ctr < 4; ctr++)
16160 regval[ctr] = (hpf_code << 8) | 0x7c;
16161 wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);
16162
16163 wlc_phy_adjust_lnagaintbl_nphy(pi);
16164
16165 if (pi->nphy_elna_gain_config) {
16166 regval[0] = 0;
16167 regval[1] = 1;
16168 regval[2] = 1;
16169 regval[3] = 1;
16170 wlc_phy_table_write_nphy(pi, 2, 4, 8, 16, regval);
16171 wlc_phy_table_write_nphy(pi, 3, 4, 8, 16, regval);
16172
16173 for (ctr = 0; ctr < 4; ctr++)
16174 regval[ctr] = (hpf_code << 8) | 0x74;
16175 wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);
16176 }
16177
16178 if (NREV_IS(pi->pubpi.phy_rev, 2)) {
16179 for (ctr = 0; ctr < 21; ctr++)
16180 regval[ctr] = 3 * ctr;
16181 wlc_phy_table_write_nphy(pi, 0, 21, 32, 16, regval);
16182 wlc_phy_table_write_nphy(pi, 1, 21, 32, 16, regval);
16183
16184 for (ctr = 0; ctr < 21; ctr++)
16185 regval[ctr] = (u16) ctr;
16186 wlc_phy_table_write_nphy(pi, 2, 21, 32, 16, regval);
16187 wlc_phy_table_write_nphy(pi, 3, 21, 32, 16, regval);
16188 }
16189
16190 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_UPDATEGAINU,
16191 rfseq_updategainu_events,
16192 rfseq_updategainu_dlys,
16193 sizeof(rfseq_updategainu_events) /
16194 sizeof(rfseq_updategainu_events[0]));
16195
16196 mod_phy_reg(pi, 0x153, (0xff << 8), (90 << 8));
16197
16198 if (CHSPEC_IS2G(pi->radio_chanspec))
16199 mod_phy_reg(pi,
16200 (NPHY_TO_BPHY_OFF + BPHY_OPTIONAL_MODES),
16201 0x7f, 0x4);
16202 }
16203}
16204
16205static void wlc_phy_workarounds_nphy(struct brcms_phy *pi)
16206{
16207 u8 rfseq_rx2tx_events[] = {
16208 NPHY_RFSEQ_CMD_NOP,
16209 NPHY_RFSEQ_CMD_RXG_FBW,
16210 NPHY_RFSEQ_CMD_TR_SWITCH,
16211 NPHY_RFSEQ_CMD_CLR_HIQ_DIS,
16212 NPHY_RFSEQ_CMD_RXPD_TXPD,
16213 NPHY_RFSEQ_CMD_TX_GAIN,
16214 NPHY_RFSEQ_CMD_EXT_PA
16215 };
16216 u8 rfseq_rx2tx_dlys[] = { 8, 6, 6, 2, 4, 60, 1 };
16217 u8 rfseq_tx2rx_events[] = {
16218 NPHY_RFSEQ_CMD_NOP,
16219 NPHY_RFSEQ_CMD_EXT_PA,
16220 NPHY_RFSEQ_CMD_TX_GAIN,
16221 NPHY_RFSEQ_CMD_RXPD_TXPD,
16222 NPHY_RFSEQ_CMD_TR_SWITCH,
16223 NPHY_RFSEQ_CMD_RXG_FBW,
16224 NPHY_RFSEQ_CMD_CLR_HIQ_DIS
16225 };
16226 u8 rfseq_tx2rx_dlys[] = { 8, 6, 2, 4, 4, 6, 1 };
16227 u8 rfseq_tx2rx_events_rev3[] = {
16228 NPHY_REV3_RFSEQ_CMD_EXT_PA,
16229 NPHY_REV3_RFSEQ_CMD_INT_PA_PU,
16230 NPHY_REV3_RFSEQ_CMD_TX_GAIN,
16231 NPHY_REV3_RFSEQ_CMD_RXPD_TXPD,
16232 NPHY_REV3_RFSEQ_CMD_TR_SWITCH,
16233 NPHY_REV3_RFSEQ_CMD_RXG_FBW,
16234 NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS,
16235 NPHY_REV3_RFSEQ_CMD_END
16236 };
16237 u8 rfseq_tx2rx_dlys_rev3[] = { 8, 4, 2, 2, 4, 4, 6, 1 };
16238 u8 rfseq_rx2tx_events_rev3[] = {
16239 NPHY_REV3_RFSEQ_CMD_NOP,
16240 NPHY_REV3_RFSEQ_CMD_RXG_FBW,
16241 NPHY_REV3_RFSEQ_CMD_TR_SWITCH,
16242 NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS,
16243 NPHY_REV3_RFSEQ_CMD_RXPD_TXPD,
16244 NPHY_REV3_RFSEQ_CMD_TX_GAIN,
16245 NPHY_REV3_RFSEQ_CMD_INT_PA_PU,
16246 NPHY_REV3_RFSEQ_CMD_EXT_PA,
16247 NPHY_REV3_RFSEQ_CMD_END
16248 };
16249 u8 rfseq_rx2tx_dlys_rev3[] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
16250
16251 u8 rfseq_rx2tx_events_rev3_ipa[] = {
16252 NPHY_REV3_RFSEQ_CMD_NOP,
16253 NPHY_REV3_RFSEQ_CMD_RXG_FBW,
16254 NPHY_REV3_RFSEQ_CMD_TR_SWITCH,
16255 NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS,
16256 NPHY_REV3_RFSEQ_CMD_RXPD_TXPD,
16257 NPHY_REV3_RFSEQ_CMD_TX_GAIN,
16258 NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS,
16259 NPHY_REV3_RFSEQ_CMD_INT_PA_PU,
16260 NPHY_REV3_RFSEQ_CMD_END
16261 };
16262 u8 rfseq_rx2tx_dlys_rev3_ipa[] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
16263 u16 rfseq_rx2tx_dacbufpu_rev7[] = { 0x10f, 0x10f };
16264
16265 s16 alpha0, alpha1, alpha2;
16266 s16 beta0, beta1, beta2;
16267 u32 leg_data_weights, ht_data_weights, nss1_data_weights,
16268 stbc_data_weights;
16269 u8 chan_freq_range = 0;
16270 u16 dac_control = 0x0002;
16271 u16 aux_adc_vmid_rev7_core0[] = { 0x8e, 0x96, 0x96, 0x96 };
16272 u16 aux_adc_vmid_rev7_core1[] = { 0x8f, 0x9f, 0x9f, 0x96 };
16273 u16 aux_adc_vmid_rev4[] = { 0xa2, 0xb4, 0xb4, 0x89 };
16274 u16 aux_adc_vmid_rev3[] = { 0xa2, 0xb4, 0xb4, 0x89 };
16275 u16 *aux_adc_vmid;
16276 u16 aux_adc_gain_rev7[] = { 0x02, 0x02, 0x02, 0x02 };
16277 u16 aux_adc_gain_rev4[] = { 0x02, 0x02, 0x02, 0x00 };
16278 u16 aux_adc_gain_rev3[] = { 0x02, 0x02, 0x02, 0x00 };
16279 u16 *aux_adc_gain;
16280 u16 sk_adc_vmid[] = { 0xb4, 0xb4, 0xb4, 0x24 };
16281 u16 sk_adc_gain[] = { 0x02, 0x02, 0x02, 0x02 };
16282 s32 min_nvar_val = 0x18d;
16283 s32 min_nvar_offset_6mbps = 20;
16284 u8 pdetrange;
16285 u8 triso;
16286 u16 regval;
16287 u16 afectrl_adc_ctrl1_rev7 = 0x20;
16288 u16 afectrl_adc_ctrl2_rev7 = 0x0;
16289 u16 rfseq_rx2tx_lpf_h_hpc_rev7 = 0x77;
16290 u16 rfseq_tx2rx_lpf_h_hpc_rev7 = 0x77;
16291 u16 rfseq_pktgn_lpf_h_hpc_rev7 = 0x77;
16292 u16 rfseq_htpktgn_lpf_hpc_rev7[] = { 0x77, 0x11, 0x11 };
16293 u16 rfseq_pktgn_lpf_hpc_rev7[] = { 0x11, 0x11 };
16294 u16 rfseq_cckpktgn_lpf_hpc_rev7[] = { 0x11, 0x11 };
16295 u16 ipalvlshift_3p3_war_en = 0;
16296 u16 rccal_bcap_val, rccal_scap_val;
16297 u16 rccal_tx20_11b_bcap = 0;
16298 u16 rccal_tx20_11b_scap = 0;
16299 u16 rccal_tx20_11n_bcap = 0;
16300 u16 rccal_tx20_11n_scap = 0;
16301 u16 rccal_tx40_11n_bcap = 0;
16302 u16 rccal_tx40_11n_scap = 0;
16303 u16 rx2tx_lpf_rc_lut_tx20_11b = 0;
16304 u16 rx2tx_lpf_rc_lut_tx20_11n = 0;
16305 u16 rx2tx_lpf_rc_lut_tx40_11n = 0;
16306 u16 tx_lpf_bw_ofdm_20mhz = 0;
16307 u16 tx_lpf_bw_ofdm_40mhz = 0;
16308 u16 tx_lpf_bw_11b = 0;
16309 u16 ipa2g_mainbias, ipa2g_casconv, ipa2g_biasfilt;
16310 u16 txgm_idac_bleed = 0;
16311 bool rccal_ovrd = false;
16312 u16 freq;
16313 int coreNum;
16314
16315 if (CHSPEC_IS5G(pi->radio_chanspec))
16316 wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_cck_en, 0);
16317 else
16318 wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_cck_en, 1);
16319
16320 if (pi->phyhang_avoid)
16321 wlc_phy_stay_in_carriersearch_nphy(pi, true);
16322
16323 or_phy_reg(pi, 0xb1, NPHY_IQFlip_ADC1 | NPHY_IQFlip_ADC2);
16324
16325 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
16326
16327 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
16328 mod_phy_reg(pi, 0x221, (0x1 << 4), (1 << 4));
16329
16330 mod_phy_reg(pi, 0x160, (0x7f << 0), (32 << 0));
16331 mod_phy_reg(pi, 0x160, (0x7f << 8), (39 << 8));
16332 mod_phy_reg(pi, 0x161, (0x7f << 0), (46 << 0));
16333 mod_phy_reg(pi, 0x161, (0x7f << 8), (51 << 8));
16334 mod_phy_reg(pi, 0x162, (0x7f << 0), (55 << 0));
16335 mod_phy_reg(pi, 0x162, (0x7f << 8), (58 << 8));
16336 mod_phy_reg(pi, 0x163, (0x7f << 0), (60 << 0));
16337 mod_phy_reg(pi, 0x163, (0x7f << 8), (62 << 8));
16338 mod_phy_reg(pi, 0x164, (0x7f << 0), (62 << 0));
16339 mod_phy_reg(pi, 0x164, (0x7f << 8), (63 << 8));
16340 mod_phy_reg(pi, 0x165, (0x7f << 0), (63 << 0));
16341 mod_phy_reg(pi, 0x165, (0x7f << 8), (64 << 8));
16342 mod_phy_reg(pi, 0x166, (0x7f << 0), (64 << 0));
16343 mod_phy_reg(pi, 0x166, (0x7f << 8), (64 << 8));
16344 mod_phy_reg(pi, 0x167, (0x7f << 0), (64 << 0));
16345 mod_phy_reg(pi, 0x167, (0x7f << 8), (64 << 8));
16346 }
16347
16348 if (NREV_LE(pi->pubpi.phy_rev, 8)) {
16349 write_phy_reg(pi, 0x23f, 0x1b0);
16350 write_phy_reg(pi, 0x240, 0x1b0);
16351 }
16352
16353 if (NREV_GE(pi->pubpi.phy_rev, 8))
16354 mod_phy_reg(pi, 0xbd, (0xff << 0), (114 << 0));
16355
16356 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x00, 16,
16357 &dac_control);
16358 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x10, 16,
16359 &dac_control);
16360
16361 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16362 1, 0, 32, &leg_data_weights);
16363 leg_data_weights = leg_data_weights & 0xffffff;
16364 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16365 1, 0, 32, &leg_data_weights);
16366
16367 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
16368 2, 0x15e, 16,
16369 rfseq_rx2tx_dacbufpu_rev7);
16370 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x16e, 16,
16371 rfseq_rx2tx_dacbufpu_rev7);
16372
16373 if (PHY_IPA(pi))
16374 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
16375 rfseq_rx2tx_events_rev3_ipa,
16376 rfseq_rx2tx_dlys_rev3_ipa,
16377 sizeof
16378 (rfseq_rx2tx_events_rev3_ipa) /
16379 sizeof
16380 (rfseq_rx2tx_events_rev3_ipa
16381 [0]));
16382
16383 mod_phy_reg(pi, 0x299, (0x3 << 14), (0x1 << 14));
16384 mod_phy_reg(pi, 0x29d, (0x3 << 14), (0x1 << 14));
16385
16386 tx_lpf_bw_ofdm_20mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x154);
16387 tx_lpf_bw_ofdm_40mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x159);
16388 tx_lpf_bw_11b = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x152);
16389
16390 if (PHY_IPA(pi)) {
16391
16392 if (((pi->pubpi.radiorev == 5)
16393 && (CHSPEC_IS40(pi->radio_chanspec) == 1))
16394 || (pi->pubpi.radiorev == 7)
16395 || (pi->pubpi.radiorev == 8)) {
16396
16397 rccal_bcap_val =
16398 read_radio_reg(
16399 pi,
16400 RADIO_2057_RCCAL_BCAP_VAL);
16401 rccal_scap_val =
16402 read_radio_reg(
16403 pi,
16404 RADIO_2057_RCCAL_SCAP_VAL);
16405
16406 rccal_tx20_11b_bcap = rccal_bcap_val;
16407 rccal_tx20_11b_scap = rccal_scap_val;
16408
16409 if ((pi->pubpi.radiorev == 5) &&
16410 (CHSPEC_IS40(pi->radio_chanspec) == 1)) {
16411
16412 rccal_tx20_11n_bcap = rccal_bcap_val;
16413 rccal_tx20_11n_scap = rccal_scap_val;
16414 rccal_tx40_11n_bcap = 0xc;
16415 rccal_tx40_11n_scap = 0xc;
16416
16417 rccal_ovrd = true;
16418
16419 } else if ((pi->pubpi.radiorev == 7)
16420 || (pi->pubpi.radiorev == 8)) {
16421
16422 tx_lpf_bw_ofdm_20mhz = 4;
16423 tx_lpf_bw_11b = 1;
16424
16425 if (CHSPEC_IS2G(pi->radio_chanspec)) {
16426 rccal_tx20_11n_bcap = 0xc;
16427 rccal_tx20_11n_scap = 0xc;
16428 rccal_tx40_11n_bcap = 0xa;
16429 rccal_tx40_11n_scap = 0xa;
16430 } else {
16431 rccal_tx20_11n_bcap = 0x14;
16432 rccal_tx20_11n_scap = 0x14;
16433 rccal_tx40_11n_bcap = 0xf;
16434 rccal_tx40_11n_scap = 0xf;
16435 }
16436
16437 rccal_ovrd = true;
16438 }
16439 }
16440
16441 } else {
16442
16443 if (pi->pubpi.radiorev == 5) {
16444
16445 tx_lpf_bw_ofdm_20mhz = 1;
16446 tx_lpf_bw_ofdm_40mhz = 3;
16447
16448 rccal_bcap_val =
16449 read_radio_reg(
16450 pi,
16451 RADIO_2057_RCCAL_BCAP_VAL);
16452 rccal_scap_val =
16453 read_radio_reg(
16454 pi,
16455 RADIO_2057_RCCAL_SCAP_VAL);
16456
16457 rccal_tx20_11b_bcap = rccal_bcap_val;
16458 rccal_tx20_11b_scap = rccal_scap_val;
16459
16460 rccal_tx20_11n_bcap = 0x13;
16461 rccal_tx20_11n_scap = 0x11;
16462 rccal_tx40_11n_bcap = 0x13;
16463 rccal_tx40_11n_scap = 0x11;
16464
16465 rccal_ovrd = true;
16466 }
16467 }
16468
16469 if (rccal_ovrd) {
16470
16471 rx2tx_lpf_rc_lut_tx20_11b =
16472 (rccal_tx20_11b_bcap << 8) |
16473 (rccal_tx20_11b_scap << 3) |
16474 tx_lpf_bw_11b;
16475 rx2tx_lpf_rc_lut_tx20_11n =
16476 (rccal_tx20_11n_bcap << 8) |
16477 (rccal_tx20_11n_scap << 3) |
16478 tx_lpf_bw_ofdm_20mhz;
16479 rx2tx_lpf_rc_lut_tx40_11n =
16480 (rccal_tx40_11n_bcap << 8) |
16481 (rccal_tx40_11n_scap << 3) |
16482 tx_lpf_bw_ofdm_40mhz;
16483
16484 for (coreNum = 0; coreNum <= 1; coreNum++) {
16485 wlc_phy_table_write_nphy(
16486 pi, NPHY_TBL_ID_RFSEQ,
16487 1,
16488 0x152 + coreNum * 0x10,
16489 16,
16490 &rx2tx_lpf_rc_lut_tx20_11b);
16491 wlc_phy_table_write_nphy(
16492 pi, NPHY_TBL_ID_RFSEQ,
16493 1,
16494 0x153 + coreNum * 0x10,
16495 16,
16496 &rx2tx_lpf_rc_lut_tx20_11n);
16497 wlc_phy_table_write_nphy(
16498 pi, NPHY_TBL_ID_RFSEQ,
16499 1,
16500 0x154 + coreNum * 0x10,
16501 16,
16502 &rx2tx_lpf_rc_lut_tx20_11n);
16503 wlc_phy_table_write_nphy(
16504 pi, NPHY_TBL_ID_RFSEQ,
16505 1,
16506 0x155 + coreNum * 0x10,
16507 16,
16508 &rx2tx_lpf_rc_lut_tx40_11n);
16509 wlc_phy_table_write_nphy(
16510 pi, NPHY_TBL_ID_RFSEQ,
16511 1,
16512 0x156 + coreNum * 0x10,
16513 16,
16514 &rx2tx_lpf_rc_lut_tx40_11n);
16515 wlc_phy_table_write_nphy(
16516 pi, NPHY_TBL_ID_RFSEQ,
16517 1,
16518 0x157 + coreNum * 0x10,
16519 16,
16520 &rx2tx_lpf_rc_lut_tx40_11n);
16521 wlc_phy_table_write_nphy(
16522 pi, NPHY_TBL_ID_RFSEQ,
16523 1,
16524 0x158 + coreNum * 0x10,
16525 16,
16526 &rx2tx_lpf_rc_lut_tx40_11n);
16527 wlc_phy_table_write_nphy(
16528 pi, NPHY_TBL_ID_RFSEQ,
16529 1,
16530 0x159 + coreNum * 0x10,
16531 16,
16532 &rx2tx_lpf_rc_lut_tx40_11n);
16533 }
16534
16535 wlc_phy_rfctrl_override_nphy_rev7(
16536 pi, (0x1 << 4),
16537 1, 0x3, 0,
16538 NPHY_REV7_RFCTRLOVERRIDE_ID2);
16539 }
16540
16541 write_phy_reg(pi, 0x32f, 0x3);
16542
16543 if ((pi->pubpi.radiorev == 4) || (pi->pubpi.radiorev == 6))
16544 wlc_phy_rfctrl_override_nphy_rev7(
16545 pi, (0x1 << 2),
16546 1, 0x3, 0,
16547 NPHY_REV7_RFCTRLOVERRIDE_ID0);
16548
16549 if ((pi->pubpi.radiorev == 3) || (pi->pubpi.radiorev == 4) ||
16550 (pi->pubpi.radiorev == 6)) {
16551 if ((pi->sh->sromrev >= 8)
16552 && (pi->sh->boardflags2 & BFL2_IPALVLSHIFT_3P3))
16553 ipalvlshift_3p3_war_en = 1;
16554
16555 if (ipalvlshift_3p3_war_en) {
16556 write_radio_reg(pi, RADIO_2057_GPAIO_CONFIG,
16557 0x5);
16558 write_radio_reg(pi, RADIO_2057_GPAIO_SEL1,
16559 0x30);
16560 write_radio_reg(pi, RADIO_2057_GPAIO_SEL0, 0x0);
16561 or_radio_reg(pi,
16562 RADIO_2057_RXTXBIAS_CONFIG_CORE0,
16563 0x1);
16564 or_radio_reg(pi,
16565 RADIO_2057_RXTXBIAS_CONFIG_CORE1,
16566 0x1);
16567
16568 ipa2g_mainbias = 0x1f;
16569
16570 ipa2g_casconv = 0x6f;
16571
16572 ipa2g_biasfilt = 0xaa;
16573 } else {
16574
16575 ipa2g_mainbias = 0x2b;
16576
16577 ipa2g_casconv = 0x7f;
16578
16579 ipa2g_biasfilt = 0xee;
16580 }
16581
16582 if (CHSPEC_IS2G(pi->radio_chanspec)) {
16583 for (coreNum = 0; coreNum <= 1; coreNum++) {
16584 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16585 coreNum, IPA2G_IMAIN,
16586 ipa2g_mainbias);
16587 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16588 coreNum, IPA2G_CASCONV,
16589 ipa2g_casconv);
16590 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16591 coreNum,
16592 IPA2G_BIAS_FILTER,
16593 ipa2g_biasfilt);
16594 }
16595 }
16596 }
16597
16598 if (PHY_IPA(pi)) {
16599 if (CHSPEC_IS2G(pi->radio_chanspec)) {
16600 if ((pi->pubpi.radiorev == 3)
16601 || (pi->pubpi.radiorev == 4)
16602 || (pi->pubpi.radiorev == 6))
16603 txgm_idac_bleed = 0x7f;
16604
16605 for (coreNum = 0; coreNum <= 1; coreNum++) {
16606 if (txgm_idac_bleed != 0)
16607 WRITE_RADIO_REG4(
16608 pi, RADIO_2057,
16609 CORE, coreNum,
16610 TXGM_IDAC_BLEED,
16611 txgm_idac_bleed);
16612 }
16613
16614 if (pi->pubpi.radiorev == 5) {
16615
16616 for (coreNum = 0; coreNum <= 1;
16617 coreNum++) {
16618 WRITE_RADIO_REG4(pi, RADIO_2057,
16619 CORE, coreNum,
16620 IPA2G_CASCONV,
16621 0x13);
16622 WRITE_RADIO_REG4(pi, RADIO_2057,
16623 CORE, coreNum,
16624 IPA2G_IMAIN,
16625 0x1f);
16626 WRITE_RADIO_REG4(
16627 pi, RADIO_2057,
16628 CORE, coreNum,
16629 IPA2G_BIAS_FILTER,
16630 0xee);
16631 WRITE_RADIO_REG4(pi, RADIO_2057,
16632 CORE, coreNum,
16633 PAD2G_IDACS,
16634 0x8a);
16635 WRITE_RADIO_REG4(
16636 pi, RADIO_2057,
16637 CORE, coreNum,
16638 PAD_BIAS_FILTER_BWS,
16639 0x3e);
16640 }
16641
16642 } else if ((pi->pubpi.radiorev == 7)
16643 || (pi->pubpi.radiorev == 8)) {
16644
16645 if (CHSPEC_IS40(pi->radio_chanspec) ==
16646 0) {
16647 WRITE_RADIO_REG4(pi, RADIO_2057,
16648 CORE, 0,
16649 IPA2G_IMAIN,
16650 0x14);
16651 WRITE_RADIO_REG4(pi, RADIO_2057,
16652 CORE, 1,
16653 IPA2G_IMAIN,
16654 0x12);
16655 } else {
16656 WRITE_RADIO_REG4(pi, RADIO_2057,
16657 CORE, 0,
16658 IPA2G_IMAIN,
16659 0x16);
16660 WRITE_RADIO_REG4(pi, RADIO_2057,
16661 CORE, 1,
16662 IPA2G_IMAIN,
16663 0x16);
16664 }
16665 }
16666
16667 } else {
16668 freq = CHAN5G_FREQ(CHSPEC_CHANNEL(
16669 pi->radio_chanspec));
16670 if (((freq >= 5180) && (freq <= 5230))
16671 || ((freq >= 5745) && (freq <= 5805))) {
16672 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16673 0, IPA5G_BIAS_FILTER,
16674 0xff);
16675 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16676 1, IPA5G_BIAS_FILTER,
16677 0xff);
16678 }
16679 }
16680 } else {
16681
16682 if (pi->pubpi.radiorev != 5) {
16683 for (coreNum = 0; coreNum <= 1; coreNum++) {
16684 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16685 coreNum,
16686 TXMIX2G_TUNE_BOOST_PU,
16687 0x61);
16688 WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
16689 coreNum,
16690 TXGM_IDAC_BLEED, 0x70);
16691 }
16692 }
16693 }
16694
16695 if (pi->pubpi.radiorev == 4) {
16696 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
16697 0x05, 16,
16698 &afectrl_adc_ctrl1_rev7);
16699 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
16700 0x15, 16,
16701 &afectrl_adc_ctrl1_rev7);
16702
16703 for (coreNum = 0; coreNum <= 1; coreNum++) {
16704 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
16705 AFE_VCM_CAL_MASTER, 0x0);
16706 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
16707 AFE_SET_VCM_I, 0x3f);
16708 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
16709 AFE_SET_VCM_Q, 0x3f);
16710 }
16711 } else {
16712 mod_phy_reg(pi, 0xa6, (0x1 << 2), (0x1 << 2));
16713 mod_phy_reg(pi, 0x8f, (0x1 << 2), (0x1 << 2));
16714 mod_phy_reg(pi, 0xa7, (0x1 << 2), (0x1 << 2));
16715 mod_phy_reg(pi, 0xa5, (0x1 << 2), (0x1 << 2));
16716
16717 mod_phy_reg(pi, 0xa6, (0x1 << 0), 0);
16718 mod_phy_reg(pi, 0x8f, (0x1 << 0), (0x1 << 0));
16719 mod_phy_reg(pi, 0xa7, (0x1 << 0), 0);
16720 mod_phy_reg(pi, 0xa5, (0x1 << 0), (0x1 << 0));
16721
16722 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
16723 0x05, 16,
16724 &afectrl_adc_ctrl2_rev7);
16725 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
16726 0x15, 16,
16727 &afectrl_adc_ctrl2_rev7);
16728
16729 mod_phy_reg(pi, 0xa6, (0x1 << 2), 0);
16730 mod_phy_reg(pi, 0x8f, (0x1 << 2), 0);
16731 mod_phy_reg(pi, 0xa7, (0x1 << 2), 0);
16732 mod_phy_reg(pi, 0xa5, (0x1 << 2), 0);
16733 }
16734
16735 write_phy_reg(pi, 0x6a, 0x2);
16736
16737 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 256, 32,
16738 &min_nvar_offset_6mbps);
16739
16740 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x138, 16,
16741 &rfseq_pktgn_lpf_hpc_rev7);
16742
16743 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x141, 16,
16744 &rfseq_pktgn_lpf_h_hpc_rev7);
16745
16746 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 3, 0x133, 16,
16747 &rfseq_htpktgn_lpf_hpc_rev7);
16748
16749 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x146, 16,
16750 &rfseq_cckpktgn_lpf_hpc_rev7);
16751
16752 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x123, 16,
16753 &rfseq_tx2rx_lpf_h_hpc_rev7);
16754
16755 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x12A, 16,
16756 &rfseq_rx2tx_lpf_h_hpc_rev7);
16757
16758 if (CHSPEC_IS40(pi->radio_chanspec) == 0) {
16759 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
16760 32, &min_nvar_val);
16761 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
16762 127, 32, &min_nvar_val);
16763 } else {
16764 min_nvar_val = noise_var_tbl_rev7[3];
16765 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
16766 32, &min_nvar_val);
16767
16768 min_nvar_val = noise_var_tbl_rev7[127];
16769 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
16770 127, 32, &min_nvar_val);
16771 }
16772
16773 wlc_phy_workarounds_nphy_gainctrl(pi);
16774
16775 pdetrange =
16776 (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.
16777 pdetrange : pi->srom_fem2g.pdetrange;
16778
16779 if (pdetrange == 0) {
16780 chan_freq_range =
16781 wlc_phy_get_chan_freq_range_nphy(pi, 0);
16782 if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
16783 aux_adc_vmid_rev7_core0[3] = 0x70;
16784 aux_adc_vmid_rev7_core1[3] = 0x70;
16785 aux_adc_gain_rev7[3] = 2;
16786 } else {
16787 aux_adc_vmid_rev7_core0[3] = 0x80;
16788 aux_adc_vmid_rev7_core1[3] = 0x80;
16789 aux_adc_gain_rev7[3] = 3;
16790 }
16791 } else if (pdetrange == 1) {
16792 if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
16793 aux_adc_vmid_rev7_core0[3] = 0x7c;
16794 aux_adc_vmid_rev7_core1[3] = 0x7c;
16795 aux_adc_gain_rev7[3] = 2;
16796 } else {
16797 aux_adc_vmid_rev7_core0[3] = 0x8c;
16798 aux_adc_vmid_rev7_core1[3] = 0x8c;
16799 aux_adc_gain_rev7[3] = 1;
16800 }
16801 } else if (pdetrange == 2) {
16802 if (pi->pubpi.radioid == BCM2057_ID) {
16803 if ((pi->pubpi.radiorev == 5)
16804 || (pi->pubpi.radiorev == 7)
16805 || (pi->pubpi.radiorev == 8)) {
16806 if (chan_freq_range ==
16807 WL_CHAN_FREQ_RANGE_2G) {
16808 aux_adc_vmid_rev7_core0[3] =
16809 0x8c;
16810 aux_adc_vmid_rev7_core1[3] =
16811 0x8c;
16812 aux_adc_gain_rev7[3] = 0;
16813 } else {
16814 aux_adc_vmid_rev7_core0[3] =
16815 0x96;
16816 aux_adc_vmid_rev7_core1[3] =
16817 0x96;
16818 aux_adc_gain_rev7[3] = 0;
16819 }
16820 }
16821 }
16822
16823 } else if (pdetrange == 3) {
16824 if (chan_freq_range == WL_CHAN_FREQ_RANGE_2G) {
16825 aux_adc_vmid_rev7_core0[3] = 0x89;
16826 aux_adc_vmid_rev7_core1[3] = 0x89;
16827 aux_adc_gain_rev7[3] = 0;
16828 }
16829
16830 } else if (pdetrange == 5) {
16831
16832 if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
16833 aux_adc_vmid_rev7_core0[3] = 0x80;
16834 aux_adc_vmid_rev7_core1[3] = 0x80;
16835 aux_adc_gain_rev7[3] = 3;
16836 } else {
16837 aux_adc_vmid_rev7_core0[3] = 0x70;
16838 aux_adc_vmid_rev7_core1[3] = 0x70;
16839 aux_adc_gain_rev7[3] = 2;
16840 }
16841 }
16842
16843 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x08, 16,
16844 &aux_adc_vmid_rev7_core0);
16845 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x18, 16,
16846 &aux_adc_vmid_rev7_core1);
16847 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x0c, 16,
16848 &aux_adc_gain_rev7);
16849 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x1c, 16,
16850 &aux_adc_gain_rev7);
16851
16852 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
16853
16854 write_phy_reg(pi, 0x23f, 0x1f8);
16855 write_phy_reg(pi, 0x240, 0x1f8);
16856
16857 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16858 1, 0, 32, &leg_data_weights);
16859 leg_data_weights = leg_data_weights & 0xffffff;
16860 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
16861 1, 0, 32, &leg_data_weights);
16862
16863 alpha0 = 293;
16864 alpha1 = 435;
16865 alpha2 = 261;
16866 beta0 = 366;
16867 beta1 = 205;
16868 beta2 = 32;
16869 write_phy_reg(pi, 0x145, alpha0);
16870 write_phy_reg(pi, 0x146, alpha1);
16871 write_phy_reg(pi, 0x147, alpha2);
16872 write_phy_reg(pi, 0x148, beta0);
16873 write_phy_reg(pi, 0x149, beta1);
16874 write_phy_reg(pi, 0x14a, beta2);
16875
16876 write_phy_reg(pi, 0x38, 0xC);
16877 write_phy_reg(pi, 0x2ae, 0xC);
16878
16879 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_TX2RX,
16880 rfseq_tx2rx_events_rev3,
16881 rfseq_tx2rx_dlys_rev3,
16882 sizeof(rfseq_tx2rx_events_rev3) /
16883 sizeof(rfseq_tx2rx_events_rev3[0]));
16884
16885 if (PHY_IPA(pi))
16886 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
16887 rfseq_rx2tx_events_rev3_ipa,
16888 rfseq_rx2tx_dlys_rev3_ipa,
16889 sizeof
16890 (rfseq_rx2tx_events_rev3_ipa) /
16891 sizeof
16892 (rfseq_rx2tx_events_rev3_ipa
16893 [0]));
16894
16895 if ((pi->sh->hw_phyrxchain != 0x3) &&
16896 (pi->sh->hw_phyrxchain != pi->sh->hw_phytxchain)) {
16897
16898 if (PHY_IPA(pi)) {
16899 rfseq_rx2tx_dlys_rev3[5] = 59;
16900 rfseq_rx2tx_dlys_rev3[6] = 1;
16901 rfseq_rx2tx_events_rev3[7] =
16902 NPHY_REV3_RFSEQ_CMD_END;
16903 }
16904
16905 wlc_phy_set_rfseq_nphy(
16906 pi, NPHY_RFSEQ_RX2TX,
16907 rfseq_rx2tx_events_rev3,
16908 rfseq_rx2tx_dlys_rev3,
16909 sizeof(rfseq_rx2tx_events_rev3) /
16910 sizeof(rfseq_rx2tx_events_rev3[0]));
16911 }
16912
16913 if (CHSPEC_IS2G(pi->radio_chanspec))
16914 write_phy_reg(pi, 0x6a, 0x2);
16915 else
16916 write_phy_reg(pi, 0x6a, 0x9c40);
16917
16918 mod_phy_reg(pi, 0x294, (0xf << 8), (7 << 8));
16919
16920 if (CHSPEC_IS40(pi->radio_chanspec) == 0) {
16921 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
16922 32, &min_nvar_val);
16923 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
16924 127, 32, &min_nvar_val);
16925 } else {
16926 min_nvar_val = noise_var_tbl_rev3[3];
16927 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
16928 32, &min_nvar_val);
16929
16930 min_nvar_val = noise_var_tbl_rev3[127];
16931 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
16932 127, 32, &min_nvar_val);
16933 }
16934
16935 wlc_phy_workarounds_nphy_gainctrl(pi);
16936
16937 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x00, 16,
16938 &dac_control);
16939 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x10, 16,
16940 &dac_control);
16941
16942 pdetrange =
16943 (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.
16944 pdetrange : pi->srom_fem2g.pdetrange;
16945
16946 if (pdetrange == 0) {
16947 if (NREV_GE(pi->pubpi.phy_rev, 4)) {
16948 aux_adc_vmid = aux_adc_vmid_rev4;
16949 aux_adc_gain = aux_adc_gain_rev4;
16950 } else {
16951 aux_adc_vmid = aux_adc_vmid_rev3;
16952 aux_adc_gain = aux_adc_gain_rev3;
16953 }
16954 chan_freq_range =
16955 wlc_phy_get_chan_freq_range_nphy(pi, 0);
16956 if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
16957 switch (chan_freq_range) {
16958 case WL_CHAN_FREQ_RANGE_5GL:
16959 aux_adc_vmid[3] = 0x89;
16960 aux_adc_gain[3] = 0;
16961 break;
16962 case WL_CHAN_FREQ_RANGE_5GM:
16963 aux_adc_vmid[3] = 0x89;
16964 aux_adc_gain[3] = 0;
16965 break;
16966 case WL_CHAN_FREQ_RANGE_5GH:
16967 aux_adc_vmid[3] = 0x89;
16968 aux_adc_gain[3] = 0;
16969 break;
16970 default:
16971 break;
16972 }
16973 }
16974 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16975 0x08, 16, aux_adc_vmid);
16976 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16977 0x18, 16, aux_adc_vmid);
16978 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16979 0x0c, 16, aux_adc_gain);
16980 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16981 0x1c, 16, aux_adc_gain);
16982 } else if (pdetrange == 1) {
16983 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16984 0x08, 16, sk_adc_vmid);
16985 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16986 0x18, 16, sk_adc_vmid);
16987 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16988 0x0c, 16, sk_adc_gain);
16989 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
16990 0x1c, 16, sk_adc_gain);
16991 } else if (pdetrange == 2) {
16992
16993 u16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x74 };
16994 u16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x04 };
16995
16996 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
16997 chan_freq_range =
16998 wlc_phy_get_chan_freq_range_nphy(pi, 0);
16999 if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
17000 bcm_adc_vmid[3] = 0x8e;
17001 bcm_adc_gain[3] = 0x03;
17002 } else {
17003 bcm_adc_vmid[3] = 0x94;
17004 bcm_adc_gain[3] = 0x03;
17005 }
17006 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
17007 bcm_adc_vmid[3] = 0x84;
17008 bcm_adc_gain[3] = 0x02;
17009 }
17010
17011 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
17012 0x08, 16, bcm_adc_vmid);
17013 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
17014 0x18, 16, bcm_adc_vmid);
17015 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
17016 0x0c, 16, bcm_adc_gain);
17017 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
17018 0x1c, 16, bcm_adc_gain);
17019 } else if (pdetrange == 3) {
17020 chan_freq_range =
17021 wlc_phy_get_chan_freq_range_nphy(pi, 0);
17022 if ((NREV_GE(pi->pubpi.phy_rev, 4))
17023 && (chan_freq_range == WL_CHAN_FREQ_RANGE_2G)) {
17024
17025 u16 auxadc_vmid[] = {
17026 0xa2, 0xb4, 0xb4, 0x270
17027 };
17028 u16 auxadc_gain[] = {
17029 0x02, 0x02, 0x02, 0x00
17030 };
17031
17032 wlc_phy_table_write_nphy(pi,
17033 NPHY_TBL_ID_AFECTRL, 4,
17034 0x08, 16, auxadc_vmid);
17035 wlc_phy_table_write_nphy(pi,
17036 NPHY_TBL_ID_AFECTRL, 4,
17037 0x18, 16, auxadc_vmid);
17038 wlc_phy_table_write_nphy(pi,
17039 NPHY_TBL_ID_AFECTRL, 4,
17040 0x0c, 16, auxadc_gain);
17041 wlc_phy_table_write_nphy(pi,
17042 NPHY_TBL_ID_AFECTRL, 4,
17043 0x1c, 16, auxadc_gain);
17044 }
17045 } else if ((pdetrange == 4) || (pdetrange == 5)) {
17046 u16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x0 };
17047 u16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x0 };
17048 u16 Vmid[2], Av[2];
17049
17050 chan_freq_range =
17051 wlc_phy_get_chan_freq_range_nphy(pi, 0);
17052 if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
17053 Vmid[0] = (pdetrange == 4) ? 0x8e : 0x89;
17054 Vmid[1] = (pdetrange == 4) ? 0x96 : 0x89;
17055 Av[0] = (pdetrange == 4) ? 2 : 0;
17056 Av[1] = (pdetrange == 4) ? 2 : 0;
17057 } else {
17058 Vmid[0] = (pdetrange == 4) ? 0x89 : 0x74;
17059 Vmid[1] = (pdetrange == 4) ? 0x8b : 0x70;
17060 Av[0] = (pdetrange == 4) ? 2 : 0;
17061 Av[1] = (pdetrange == 4) ? 2 : 0;
17062 }
17063
17064 bcm_adc_vmid[3] = Vmid[0];
17065 bcm_adc_gain[3] = Av[0];
17066 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
17067 0x08, 16, bcm_adc_vmid);
17068 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
17069 0x0c, 16, bcm_adc_gain);
17070
17071 bcm_adc_vmid[3] = Vmid[1];
17072 bcm_adc_gain[3] = Av[1];
17073 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
17074 0x18, 16, bcm_adc_vmid);
17075 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
17076 0x1c, 16, bcm_adc_gain);
17077 }
17078
17079 write_radio_reg(pi,
17080 (RADIO_2056_RX_MIXA_MAST_BIAS | RADIO_2056_RX0),
17081 0x0);
17082 write_radio_reg(pi,
17083 (RADIO_2056_RX_MIXA_MAST_BIAS | RADIO_2056_RX1),
17084 0x0);
17085
17086 write_radio_reg(pi,
17087 (RADIO_2056_RX_MIXA_BIAS_MAIN | RADIO_2056_RX0),
17088 0x6);
17089 write_radio_reg(pi,
17090 (RADIO_2056_RX_MIXA_BIAS_MAIN | RADIO_2056_RX1),
17091 0x6);
17092
17093 write_radio_reg(pi,
17094 (RADIO_2056_RX_MIXA_BIAS_AUX | RADIO_2056_RX0),
17095 0x7);
17096 write_radio_reg(pi,
17097 (RADIO_2056_RX_MIXA_BIAS_AUX | RADIO_2056_RX1),
17098 0x7);
17099
17100 write_radio_reg(pi,
17101 (RADIO_2056_RX_MIXA_LOB_BIAS | RADIO_2056_RX0),
17102 0x88);
17103 write_radio_reg(pi,
17104 (RADIO_2056_RX_MIXA_LOB_BIAS | RADIO_2056_RX1),
17105 0x88);
17106
17107 write_radio_reg(pi,
17108 (RADIO_2056_RX_MIXA_CMFB_IDAC | RADIO_2056_RX0),
17109 0x0);
17110 write_radio_reg(pi,
17111 (RADIO_2056_RX_MIXA_CMFB_IDAC | RADIO_2056_RX1),
17112 0x0);
17113
17114 write_radio_reg(pi,
17115 (RADIO_2056_RX_MIXG_CMFB_IDAC | RADIO_2056_RX0),
17116 0x0);
17117 write_radio_reg(pi,
17118 (RADIO_2056_RX_MIXG_CMFB_IDAC | RADIO_2056_RX1),
17119 0x0);
17120
17121 triso =
17122 (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.
17123 triso : pi->srom_fem2g.triso;
17124 if (triso == 7) {
17125 wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_0);
17126 wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_1);
17127 }
17128
17129 wlc_phy_war_txchain_upd_nphy(pi, pi->sh->hw_phytxchain);
17130
17131 if (((pi->sh->boardflags2 & BFL2_APLL_WAR) &&
17132 (CHSPEC_IS5G(pi->radio_chanspec))) ||
17133 (((pi->sh->boardflags2 & BFL2_GPLL_WAR) ||
17134 (pi->sh->boardflags2 & BFL2_GPLL_WAR2)) &&
17135 (CHSPEC_IS2G(pi->radio_chanspec)))) {
17136 nss1_data_weights = 0x00088888;
17137 ht_data_weights = 0x00088888;
17138 stbc_data_weights = 0x00088888;
17139 } else {
17140 nss1_data_weights = 0x88888888;
17141 ht_data_weights = 0x88888888;
17142 stbc_data_weights = 0x88888888;
17143 }
17144 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
17145 1, 1, 32, &nss1_data_weights);
17146 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
17147 1, 2, 32, &ht_data_weights);
17148 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
17149 1, 3, 32, &stbc_data_weights);
17150
17151 if (NREV_IS(pi->pubpi.phy_rev, 4)) {
17152 if (CHSPEC_IS5G(pi->radio_chanspec)) {
17153 write_radio_reg(pi,
17154 RADIO_2056_TX_GMBB_IDAC |
17155 RADIO_2056_TX0, 0x70);
17156 write_radio_reg(pi,
17157 RADIO_2056_TX_GMBB_IDAC |
17158 RADIO_2056_TX1, 0x70);
17159 }
17160 }
17161
17162 if (!pi->edcrs_threshold_lock) {
17163 write_phy_reg(pi, 0x224, 0x3eb);
17164 write_phy_reg(pi, 0x225, 0x3eb);
17165 write_phy_reg(pi, 0x226, 0x341);
17166 write_phy_reg(pi, 0x227, 0x341);
17167 write_phy_reg(pi, 0x228, 0x42b);
17168 write_phy_reg(pi, 0x229, 0x42b);
17169 write_phy_reg(pi, 0x22a, 0x381);
17170 write_phy_reg(pi, 0x22b, 0x381);
17171 write_phy_reg(pi, 0x22c, 0x42b);
17172 write_phy_reg(pi, 0x22d, 0x42b);
17173 write_phy_reg(pi, 0x22e, 0x381);
17174 write_phy_reg(pi, 0x22f, 0x381);
17175 }
17176
17177 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
17178
17179 if (pi->sh->boardflags2 & BFL2_SINGLEANT_CCK)
17180 wlapi_bmac_mhf(pi->sh->physhim, MHF4,
17181 MHF4_BPHY_TXCORE0,
17182 MHF4_BPHY_TXCORE0, BRCM_BAND_ALL);
17183 }
17184 } else {
17185
17186 if (pi->sh->boardflags2 & BFL2_SKWRKFEM_BRD ||
17187 (pi->sh->boardtype == 0x8b)) {
17188 uint i;
17189 u8 war_dlys[] = { 1, 6, 6, 2, 4, 20, 1 };
17190 for (i = 0; i < ARRAY_SIZE(rfseq_rx2tx_dlys); i++)
17191 rfseq_rx2tx_dlys[i] = war_dlys[i];
17192 }
17193
17194 if (CHSPEC_IS5G(pi->radio_chanspec) && pi->phy_5g_pwrgain) {
17195 and_radio_reg(pi, RADIO_2055_CORE1_TX_RF_SPARE, 0xf7);
17196 and_radio_reg(pi, RADIO_2055_CORE2_TX_RF_SPARE, 0xf7);
17197 } else {
17198 or_radio_reg(pi, RADIO_2055_CORE1_TX_RF_SPARE, 0x8);
17199 or_radio_reg(pi, RADIO_2055_CORE2_TX_RF_SPARE, 0x8);
17200 }
17201
17202 regval = 0x000a;
17203 wlc_phy_table_write_nphy(pi, 8, 1, 0, 16, &regval);
17204 wlc_phy_table_write_nphy(pi, 8, 1, 0x10, 16, &regval);
17205
17206 if (NREV_LT(pi->pubpi.phy_rev, 3)) {
17207 regval = 0xcdaa;
17208 wlc_phy_table_write_nphy(pi, 8, 1, 0x02, 16, &regval);
17209 wlc_phy_table_write_nphy(pi, 8, 1, 0x12, 16, &regval);
17210 }
17211
17212 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
17213 regval = 0x0000;
17214 wlc_phy_table_write_nphy(pi, 8, 1, 0x08, 16, &regval);
17215 wlc_phy_table_write_nphy(pi, 8, 1, 0x18, 16, &regval);
17216
17217 regval = 0x7aab;
17218 wlc_phy_table_write_nphy(pi, 8, 1, 0x07, 16, &regval);
17219 wlc_phy_table_write_nphy(pi, 8, 1, 0x17, 16, &regval);
17220
17221 regval = 0x0800;
17222 wlc_phy_table_write_nphy(pi, 8, 1, 0x06, 16, &regval);
17223 wlc_phy_table_write_nphy(pi, 8, 1, 0x16, 16, &regval);
17224 }
17225
17226 write_phy_reg(pi, 0xf8, 0x02d8);
17227 write_phy_reg(pi, 0xf9, 0x0301);
17228 write_phy_reg(pi, 0xfa, 0x02d8);
17229 write_phy_reg(pi, 0xfb, 0x0301);
17230
17231 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX, rfseq_rx2tx_events,
17232 rfseq_rx2tx_dlys,
17233 sizeof(rfseq_rx2tx_events) /
17234 sizeof(rfseq_rx2tx_events[0]));
17235
17236 wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_TX2RX, rfseq_tx2rx_events,
17237 rfseq_tx2rx_dlys,
17238 sizeof(rfseq_tx2rx_events) /
17239 sizeof(rfseq_tx2rx_events[0]));
17240
17241 wlc_phy_workarounds_nphy_gainctrl(pi);
17242
17243 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
17244
17245 if (read_phy_reg(pi, 0xa0) & NPHY_MLenable)
17246 wlapi_bmac_mhf(pi->sh->physhim, MHF3,
17247 MHF3_NPHY_MLADV_WAR,
17248 MHF3_NPHY_MLADV_WAR,
17249 BRCM_BAND_ALL);
17250
17251 } else if (NREV_IS(pi->pubpi.phy_rev, 2)) {
17252 write_phy_reg(pi, 0x1e3, 0x0);
17253 write_phy_reg(pi, 0x1e4, 0x0);
17254 }
17255
17256 if (NREV_LT(pi->pubpi.phy_rev, 2))
17257 mod_phy_reg(pi, 0x90, (0x1 << 7), 0);
17258
17259 alpha0 = 293;
17260 alpha1 = 435;
17261 alpha2 = 261;
17262 beta0 = 366;
17263 beta1 = 205;
17264 beta2 = 32;
17265 write_phy_reg(pi, 0x145, alpha0);
17266 write_phy_reg(pi, 0x146, alpha1);
17267 write_phy_reg(pi, 0x147, alpha2);
17268 write_phy_reg(pi, 0x148, beta0);
17269 write_phy_reg(pi, 0x149, beta1);
17270 write_phy_reg(pi, 0x14a, beta2);
17271
17272 if (NREV_LT(pi->pubpi.phy_rev, 3)) {
17273 mod_phy_reg(pi, 0x142, (0xf << 12), 0);
17274
17275 write_phy_reg(pi, 0x192, 0xb5);
17276 write_phy_reg(pi, 0x193, 0xa4);
17277 write_phy_reg(pi, 0x194, 0x0);
17278 }
17279
17280 if (NREV_IS(pi->pubpi.phy_rev, 2))
17281 mod_phy_reg(pi, 0x221,
17282 NPHY_FORCESIG_DECODEGATEDCLKS,
17283 NPHY_FORCESIG_DECODEGATEDCLKS);
17284 }
17285
17286 if (pi->phyhang_avoid)
17287 wlc_phy_stay_in_carriersearch_nphy(pi, false);
17288}
17289
17290static void wlc_phy_extpa_set_tx_digi_filts_nphy(struct brcms_phy *pi)
17291{
17292 int j, type = 2;
17293 u16 addr_offset = 0x2c5;
17294
17295 for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++)
17296 write_phy_reg(pi, addr_offset + j,
17297 NPHY_IPA_REV4_txdigi_filtcoeffs[type][j]);
17298}
17299
17300static void wlc_phy_clip_det_nphy(struct brcms_phy *pi, u8 write, u16 *vals)
17301{
17302
17303 if (write == 0) {
17304 vals[0] = read_phy_reg(pi, 0x2c);
17305 vals[1] = read_phy_reg(pi, 0x42);
17306 } else {
17307 write_phy_reg(pi, 0x2c, vals[0]);
17308 write_phy_reg(pi, 0x42, vals[1]);
17309 }
17310}
17311
17312static void wlc_phy_ipa_internal_tssi_setup_nphy(struct brcms_phy *pi)
17313{
17314 u8 core;
17315
17316 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
17317 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
17318 if (CHSPEC_IS2G(pi->radio_chanspec)) {
17319 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17320 TX_SSI_MASTER, 0x5);
17321 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17322 TX_SSI_MUX, 0xe);
17323
17324 if (pi->pubpi.radiorev != 5)
17325 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
17326 core, TSSIA, 0);
17327
17328 if (!NREV_IS(pi->pubpi.phy_rev, 7))
17329 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
17330 core, TSSIG, 0x1);
17331 else
17332 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
17333 core, TSSIG, 0x31);
17334 } else {
17335 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17336 TX_SSI_MASTER, 0x9);
17337 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17338 TX_SSI_MUX, 0xc);
17339 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
17340 TSSIG, 0);
17341
17342 if (pi->pubpi.radiorev != 5) {
17343 if (!NREV_IS(pi->pubpi.phy_rev, 7))
17344 WRITE_RADIO_REG3(pi, RADIO_2057,
17345 TX, core,
17346 TSSIA, 0x1);
17347 else
17348 WRITE_RADIO_REG3(pi, RADIO_2057,
17349 TX, core,
17350 TSSIA, 0x31);
17351 }
17352 }
17353 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_VCM_HG,
17354 0);
17355 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_IDAC,
17356 0);
17357 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM,
17358 0x3);
17359 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_MISC1,
17360 0x0);
17361 }
17362 } else {
17363 WRITE_RADIO_SYN(pi, RADIO_2056, RESERVED_ADDR31,
17364 (CHSPEC_IS2G(pi->radio_chanspec)) ? 0x128 :
17365 0x80);
17366 WRITE_RADIO_SYN(pi, RADIO_2056, RESERVED_ADDR30, 0x0);
17367 WRITE_RADIO_SYN(pi, RADIO_2056, GPIO_MASTER1, 0x29);
17368
17369 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
17370 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, IQCAL_VCM_HG,
17371 0x0);
17372 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, IQCAL_IDAC,
17373 0x0);
17374 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_VCM,
17375 0x3);
17376 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TX_AMP_DET,
17377 0x0);
17378 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC1,
17379 0x8);
17380 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC2,
17381 0x0);
17382 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC3,
17383 0x0);
17384
17385 if (CHSPEC_IS2G(pi->radio_chanspec)) {
17386 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17387 TX_SSI_MASTER, 0x5);
17388
17389 if (pi->pubpi.radiorev != 5)
17390 WRITE_RADIO_REG2(pi, RADIO_2056, TX,
17391 core, TSSIA, 0x0);
17392 if (NREV_GE(pi->pubpi.phy_rev, 5))
17393 WRITE_RADIO_REG2(pi, RADIO_2056, TX,
17394 core, TSSIG, 0x31);
17395 else
17396 WRITE_RADIO_REG2(pi, RADIO_2056, TX,
17397 core, TSSIG, 0x11);
17398 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17399 TX_SSI_MUX, 0xe);
17400 } else {
17401 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17402 TX_SSI_MASTER, 0x9);
17403 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17404 TSSIA, 0x31);
17405 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17406 TSSIG, 0x0);
17407 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
17408 TX_SSI_MUX, 0xc);
17409 }
17410 }
17411 }
17412}
17413
17414static void
17415wlc_phy_rfctrl_override_nphy(struct brcms_phy *pi, u16 field, u16 value,
17416 u8 core_mask, u8 off)
17417{
17418 u8 core_num;
17419 u16 addr = 0, mask = 0, en_addr = 0, val_addr = 0, en_mask =
17420 0, val_mask = 0;
17421 u8 shift = 0, val_shift = 0;
17422
17423 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
17424
17425 en_mask = field;
17426 for (core_num = 0; core_num < 2; core_num++) {
17427
17428 switch (field) {
17429 case (0x1 << 1):
17430 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17431 val_addr = (core_num == 0) ? 0x7a : 0x7d;
17432 val_mask = (0x1 << 0);
17433 val_shift = 0;
17434 break;
17435 case (0x1 << 2):
17436 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17437 val_addr = (core_num == 0) ? 0x7a : 0x7d;
17438 val_mask = (0x1 << 1);
17439 val_shift = 1;
17440 break;
17441 case (0x1 << 3):
17442 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17443 val_addr = (core_num == 0) ? 0x7a : 0x7d;
17444 val_mask = (0x1 << 2);
17445 val_shift = 2;
17446 break;
17447 case (0x1 << 4):
17448 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17449 val_addr = (core_num == 0) ? 0x7a : 0x7d;
17450 val_mask = (0x1 << 4);
17451 val_shift = 4;
17452 break;
17453 case (0x1 << 5):
17454 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17455 val_addr = (core_num == 0) ? 0x7a : 0x7d;
17456 val_mask = (0x1 << 5);
17457 val_shift = 5;
17458 break;
17459 case (0x1 << 6):
17460 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17461 val_addr = (core_num == 0) ? 0x7a : 0x7d;
17462 val_mask = (0x1 << 6);
17463 val_shift = 6;
17464 break;
17465 case (0x1 << 7):
17466 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17467 val_addr = (core_num == 0) ? 0x7a : 0x7d;
17468 val_mask = (0x1 << 7);
17469 val_shift = 7;
17470 break;
17471 case (0x1 << 8):
17472 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17473 val_addr = (core_num == 0) ? 0x7a : 0x7d;
17474 val_mask = (0x7 << 8);
17475 val_shift = 8;
17476 break;
17477 case (0x1 << 11):
17478 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17479 val_addr = (core_num == 0) ? 0x7a : 0x7d;
17480 val_mask = (0x7 << 13);
17481 val_shift = 13;
17482 break;
17483
17484 case (0x1 << 9):
17485 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17486 val_addr = (core_num == 0) ? 0xf8 : 0xfa;
17487 val_mask = (0x7 << 0);
17488 val_shift = 0;
17489 break;
17490
17491 case (0x1 << 10):
17492 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17493 val_addr = (core_num == 0) ? 0xf8 : 0xfa;
17494 val_mask = (0x7 << 4);
17495 val_shift = 4;
17496 break;
17497
17498 case (0x1 << 12):
17499 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17500 val_addr = (core_num == 0) ? 0x7b : 0x7e;
17501 val_mask = (0xffff << 0);
17502 val_shift = 0;
17503 break;
17504 case (0x1 << 13):
17505 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17506 val_addr = (core_num == 0) ? 0x7c : 0x7f;
17507 val_mask = (0xffff << 0);
17508 val_shift = 0;
17509 break;
17510 case (0x1 << 14):
17511 en_addr = (core_num == 0) ? 0xe7 : 0xec;
17512 val_addr = (core_num == 0) ? 0xf9 : 0xfb;
17513 val_mask = (0x3 << 6);
17514 val_shift = 6;
17515 break;
17516 case (0x1 << 0):
17517 en_addr = (core_num == 0) ? 0xe5 : 0xe6;
17518 val_addr = (core_num == 0) ? 0xf9 : 0xfb;
17519 val_mask = (0x1 << 15);
17520 val_shift = 15;
17521 break;
17522 default:
17523 addr = 0xffff;
17524 break;
17525 }
17526
17527 if (off) {
17528 and_phy_reg(pi, en_addr, ~en_mask);
17529 and_phy_reg(pi, val_addr, ~val_mask);
17530 } else {
17531
17532 if ((core_mask == 0)
17533 || (core_mask & (1 << core_num))) {
17534 or_phy_reg(pi, en_addr, en_mask);
17535
17536 if (addr != 0xffff)
17537 mod_phy_reg(pi, val_addr,
17538 val_mask,
17539 (value <<
17540 val_shift));
17541 }
17542 }
17543 }
17544 } else {
17545
17546 if (off) {
17547 and_phy_reg(pi, 0xec, ~field);
17548 value = 0x0;
17549 } else {
17550 or_phy_reg(pi, 0xec, field);
17551 }
17552
17553 for (core_num = 0; core_num < 2; core_num++) {
17554
17555 switch (field) {
17556 case (0x1 << 1):
17557 case (0x1 << 9):
17558 case (0x1 << 12):
17559 case (0x1 << 13):
17560 case (0x1 << 14):
17561 addr = 0x78;
17562
17563 core_mask = 0x1;
17564 break;
17565 case (0x1 << 2):
17566 case (0x1 << 3):
17567 case (0x1 << 4):
17568 case (0x1 << 5):
17569 case (0x1 << 6):
17570 case (0x1 << 7):
17571 case (0x1 << 8):
17572 addr = (core_num == 0) ? 0x7a : 0x7d;
17573 break;
17574 case (0x1 << 10):
17575 addr = (core_num == 0) ? 0x7b : 0x7e;
17576 break;
17577 case (0x1 << 11):
17578 addr = (core_num == 0) ? 0x7c : 0x7f;
17579 break;
17580 default:
17581 addr = 0xffff;
17582 }
17583
17584 switch (field) {
17585 case (0x1 << 1):
17586 mask = (0x7 << 3);
17587 shift = 3;
17588 break;
17589 case (0x1 << 9):
17590 mask = (0x1 << 2);
17591 shift = 2;
17592 break;
17593 case (0x1 << 12):
17594 mask = (0x1 << 8);
17595 shift = 8;
17596 break;
17597 case (0x1 << 13):
17598 mask = (0x1 << 9);
17599 shift = 9;
17600 break;
17601 case (0x1 << 14):
17602 mask = (0xf << 12);
17603 shift = 12;
17604 break;
17605 case (0x1 << 2):
17606 mask = (0x1 << 0);
17607 shift = 0;
17608 break;
17609 case (0x1 << 3):
17610 mask = (0x1 << 1);
17611 shift = 1;
17612 break;
17613 case (0x1 << 4):
17614 mask = (0x1 << 2);
17615 shift = 2;
17616 break;
17617 case (0x1 << 5):
17618 mask = (0x3 << 4);
17619 shift = 4;
17620 break;
17621 case (0x1 << 6):
17622 mask = (0x3 << 6);
17623 shift = 6;
17624 break;
17625 case (0x1 << 7):
17626 mask = (0x1 << 8);
17627 shift = 8;
17628 break;
17629 case (0x1 << 8):
17630 mask = (0x1 << 9);
17631 shift = 9;
17632 break;
17633 case (0x1 << 10):
17634 mask = 0x1fff;
17635 shift = 0x0;
17636 break;
17637 case (0x1 << 11):
17638 mask = 0x1fff;
17639 shift = 0x0;
17640 break;
17641 default:
17642 mask = 0x0;
17643 shift = 0x0;
17644 break;
17645 }
17646
17647 if ((addr != 0xffff) && (core_mask & (1 << core_num)))
17648 mod_phy_reg(pi, addr, mask, (value << shift));
17649 }
17650
17651 or_phy_reg(pi, 0xec, (0x1 << 0));
17652 or_phy_reg(pi, 0x78, (0x1 << 0));
17653 udelay(1);
17654 and_phy_reg(pi, 0xec, ~(0x1 << 0));
17655 }
17656}
17657
17658static void wlc_phy_txpwrctrl_idle_tssi_nphy(struct brcms_phy *pi)
17659{
17660 s32 rssi_buf[4];
17661 s32 int_val;
17662
17663 if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi) || PHY_MUTED(pi))
17664
17665 return;
17666
17667 if (PHY_IPA(pi))
17668 wlc_phy_ipa_internal_tssi_setup_nphy(pi);
17669
17670 if (NREV_GE(pi->pubpi.phy_rev, 7))
17671 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
17672 0, 0x3, 0,
17673 NPHY_REV7_RFCTRLOVERRIDE_ID0);
17674 else if (NREV_GE(pi->pubpi.phy_rev, 3))
17675 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 3, 0);
17676
17677 wlc_phy_stopplayback_nphy(pi);
17678
17679 wlc_phy_tx_tone_nphy(pi, 4000, 0, 0, 0, false);
17680
17681 udelay(20);
17682 int_val =
17683 wlc_phy_poll_rssi_nphy(pi, (u8) NPHY_RSSI_SEL_TSSI_2G, rssi_buf,
17684 1);
17685 wlc_phy_stopplayback_nphy(pi);
17686 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_OFF, 0);
17687
17688 if (NREV_GE(pi->pubpi.phy_rev, 7))
17689 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
17690 0, 0x3, 1,
17691 NPHY_REV7_RFCTRLOVERRIDE_ID0);
17692 else if (NREV_GE(pi->pubpi.phy_rev, 3))
17693 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 3, 1);
17694
17695 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
17696
17697 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_2g =
17698 (u8) ((int_val >> 24) & 0xff);
17699 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_5g =
17700 (u8) ((int_val >> 24) & 0xff);
17701
17702 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_2g =
17703 (u8) ((int_val >> 8) & 0xff);
17704 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_5g =
17705 (u8) ((int_val >> 8) & 0xff);
17706 } else {
17707 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_2g =
17708 (u8) ((int_val >> 24) & 0xff);
17709
17710 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_2g =
17711 (u8) ((int_val >> 8) & 0xff);
17712
17713 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_5g =
17714 (u8) ((int_val >> 16) & 0xff);
17715 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_5g =
17716 (u8) ((int_val) & 0xff);
17717 }
17718
17719}
17720
17721static void wlc_phy_txpwr_limit_to_tbl_nphy(struct brcms_phy *pi)
17722{
17723 u8 idx, idx2, i, delta_ind;
17724
17725 for (idx = TXP_FIRST_CCK; idx <= TXP_LAST_CCK; idx++)
17726 pi->adj_pwr_tbl_nphy[idx] = pi->tx_power_offset[idx];
17727
17728 for (i = 0; i < 4; i++) {
17729 idx2 = 0;
17730
17731 delta_ind = 0;
17732
17733 switch (i) {
17734 case 0:
17735
17736 if (CHSPEC_IS40(pi->radio_chanspec)
17737 && NPHY_IS_SROM_REINTERPRET) {
17738 idx = TXP_FIRST_MCS_40_SISO;
17739 } else {
17740 idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
17741 TXP_FIRST_OFDM_40_SISO : TXP_FIRST_OFDM;
17742 delta_ind = 1;
17743 }
17744 break;
17745
17746 case 1:
17747
17748 idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
17749 TXP_FIRST_MCS_40_CDD : TXP_FIRST_MCS_20_CDD;
17750 break;
17751
17752 case 2:
17753
17754 idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
17755 TXP_FIRST_MCS_40_STBC : TXP_FIRST_MCS_20_STBC;
17756 break;
17757
17758 case 3:
17759
17760 idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
17761 TXP_FIRST_MCS_40_SDM : TXP_FIRST_MCS_20_SDM;
17762 break;
17763 }
17764
17765 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17766 pi->tx_power_offset[idx];
17767 idx = idx + delta_ind;
17768 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17769 pi->tx_power_offset[idx];
17770 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17771 pi->tx_power_offset[idx];
17772 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17773 pi->tx_power_offset[idx++];
17774
17775 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17776 pi->tx_power_offset[idx++];
17777 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17778 pi->tx_power_offset[idx];
17779 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17780 pi->tx_power_offset[idx];
17781 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17782 pi->tx_power_offset[idx++];
17783
17784 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17785 pi->tx_power_offset[idx++];
17786 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17787 pi->tx_power_offset[idx];
17788 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17789 pi->tx_power_offset[idx];
17790 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17791 pi->tx_power_offset[idx++];
17792
17793 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17794 pi->tx_power_offset[idx];
17795 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17796 pi->tx_power_offset[idx++];
17797 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17798 pi->tx_power_offset[idx];
17799 idx = idx + 1 - delta_ind;
17800 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17801 pi->tx_power_offset[idx];
17802
17803 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17804 pi->tx_power_offset[idx];
17805 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17806 pi->tx_power_offset[idx];
17807 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17808 pi->tx_power_offset[idx];
17809 pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
17810 pi->tx_power_offset[idx];
17811 }
17812}
17813
17814static void wlc_phy_txpwrctrl_pwr_setup_nphy(struct brcms_phy *pi)
17815{
17816 u32 idx;
17817 s16 a1[2], b0[2], b1[2];
17818 s8 target_pwr_qtrdbm[2];
17819 s32 num, den, pwr_est;
17820 u8 chan_freq_range;
17821 u8 idle_tssi[2];
17822 u32 tbl_id, tbl_len, tbl_offset;
17823 u32 regval[64];
17824 u8 core;
17825
17826 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
17827 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
17828 (void)R_REG(&pi->regs->maccontrol);
17829 udelay(1);
17830 }
17831
17832 if (pi->phyhang_avoid)
17833 wlc_phy_stay_in_carriersearch_nphy(pi, true);
17834
17835 or_phy_reg(pi, 0x122, (0x1 << 0));
17836
17837 if (NREV_GE(pi->pubpi.phy_rev, 3))
17838 and_phy_reg(pi, 0x1e7, (u16) (~(0x1 << 15)));
17839 else
17840 or_phy_reg(pi, 0x1e7, (0x1 << 15));
17841
17842 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
17843 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
17844
17845 if (pi->sh->sromrev < 4) {
17846 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
17847 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
17848 target_pwr_qtrdbm[0] = 13 * 4;
17849 target_pwr_qtrdbm[1] = 13 * 4;
17850 a1[0] = -424;
17851 a1[1] = -424;
17852 b0[0] = 5612;
17853 b0[1] = 5612;
17854 b1[1] = -1393;
17855 b1[0] = -1393;
17856 } else {
17857
17858 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
17859 switch (chan_freq_range) {
17860 case WL_CHAN_FREQ_RANGE_2G:
17861 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
17862 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
17863 target_pwr_qtrdbm[0] =
17864 pi->nphy_pwrctrl_info[0].max_pwr_2g;
17865 target_pwr_qtrdbm[1] =
17866 pi->nphy_pwrctrl_info[1].max_pwr_2g;
17867 a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_a1;
17868 a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_a1;
17869 b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b0;
17870 b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b0;
17871 b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b1;
17872 b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b1;
17873 break;
17874 case WL_CHAN_FREQ_RANGE_5GL:
17875 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
17876 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
17877 target_pwr_qtrdbm[0] =
17878 pi->nphy_pwrctrl_info[0].max_pwr_5gl;
17879 target_pwr_qtrdbm[1] =
17880 pi->nphy_pwrctrl_info[1].max_pwr_5gl;
17881 a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1;
17882 a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1;
17883 b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0;
17884 b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0;
17885 b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1;
17886 b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1;
17887 break;
17888 case WL_CHAN_FREQ_RANGE_5GM:
17889 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
17890 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
17891 target_pwr_qtrdbm[0] =
17892 pi->nphy_pwrctrl_info[0].max_pwr_5gm;
17893 target_pwr_qtrdbm[1] =
17894 pi->nphy_pwrctrl_info[1].max_pwr_5gm;
17895 a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_a1;
17896 a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_a1;
17897 b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b0;
17898 b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b0;
17899 b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b1;
17900 b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b1;
17901 break;
17902 case WL_CHAN_FREQ_RANGE_5GH:
17903 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
17904 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
17905 target_pwr_qtrdbm[0] =
17906 pi->nphy_pwrctrl_info[0].max_pwr_5gh;
17907 target_pwr_qtrdbm[1] =
17908 pi->nphy_pwrctrl_info[1].max_pwr_5gh;
17909 a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1;
17910 a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1;
17911 b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0;
17912 b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0;
17913 b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1;
17914 b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1;
17915 break;
17916 default:
17917 idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
17918 idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
17919 target_pwr_qtrdbm[0] = 13 * 4;
17920 target_pwr_qtrdbm[1] = 13 * 4;
17921 a1[0] = -424;
17922 a1[1] = -424;
17923 b0[0] = 5612;
17924 b0[1] = 5612;
17925 b1[1] = -1393;
17926 b1[0] = -1393;
17927 break;
17928 }
17929 }
17930
17931 target_pwr_qtrdbm[0] = (s8) pi->tx_power_max;
17932 target_pwr_qtrdbm[1] = (s8) pi->tx_power_max;
17933
17934 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
17935 if (pi->srom_fem2g.tssipos)
17936 or_phy_reg(pi, 0x1e9, (0x1 << 14));
17937
17938 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
17939 for (core = 0; core <= 1; core++) {
17940 if (PHY_IPA(pi)) {
17941 if (CHSPEC_IS2G(pi->radio_chanspec))
17942 WRITE_RADIO_REG3(pi, RADIO_2057,
17943 TX, core,
17944 TX_SSI_MUX,
17945 0xe);
17946 else
17947 WRITE_RADIO_REG3(pi, RADIO_2057,
17948 TX, core,
17949 TX_SSI_MUX,
17950 0xc);
17951 }
17952 }
17953 } else {
17954 if (PHY_IPA(pi)) {
17955
17956 write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
17957 RADIO_2056_TX0,
17958 (CHSPEC_IS5G
17959 (pi->radio_chanspec)) ?
17960 0xc : 0xe);
17961 write_radio_reg(pi,
17962 RADIO_2056_TX_TX_SSI_MUX |
17963 RADIO_2056_TX1,
17964 (CHSPEC_IS5G
17965 (pi->radio_chanspec)) ?
17966 0xc : 0xe);
17967 } else {
17968
17969 write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
17970 RADIO_2056_TX0, 0x11);
17971 write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
17972 RADIO_2056_TX1, 0x11);
17973 }
17974 }
17975 }
17976
17977 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
17978 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
17979 (void)R_REG(&pi->regs->maccontrol);
17980 udelay(1);
17981 }
17982
17983 if (NREV_GE(pi->pubpi.phy_rev, 7))
17984 mod_phy_reg(pi, 0x1e7, (0x7f << 0),
17985 (NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 << 0));
17986 else
17987 mod_phy_reg(pi, 0x1e7, (0x7f << 0),
17988 (NPHY_TxPwrCtrlCmd_pwrIndex_init << 0));
17989
17990 if (NREV_GE(pi->pubpi.phy_rev, 7))
17991 mod_phy_reg(pi, 0x222, (0xff << 0),
17992 (NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 << 0));
17993 else if (NREV_GT(pi->pubpi.phy_rev, 1))
17994 mod_phy_reg(pi, 0x222, (0xff << 0),
17995 (NPHY_TxPwrCtrlCmd_pwrIndex_init << 0));
17996
17997 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
17998 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
17999
18000 write_phy_reg(pi, 0x1e8, (0x3 << 8) | (240 << 0));
18001
18002 write_phy_reg(pi, 0x1e9,
18003 (1 << 15) | (idle_tssi[0] << 0) | (idle_tssi[1] << 8));
18004
18005 write_phy_reg(pi, 0x1ea,
18006 (target_pwr_qtrdbm[0] << 0) |
18007 (target_pwr_qtrdbm[1] << 8));
18008
18009 tbl_len = 64;
18010 tbl_offset = 0;
18011 for (tbl_id = NPHY_TBL_ID_CORE1TXPWRCTL;
18012 tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
18013
18014 for (idx = 0; idx < tbl_len; idx++) {
18015 num = 8 *
18016 (16 * b0[tbl_id - 26] + b1[tbl_id - 26] * idx);
18017 den = 32768 + a1[tbl_id - 26] * idx;
18018 pwr_est = max(((4 * num + den / 2) / den), -8);
18019 if (NREV_LT(pi->pubpi.phy_rev, 3)) {
18020 if (idx <=
18021 (uint) (31 - idle_tssi[tbl_id - 26] + 1))
18022 pwr_est =
18023 max(pwr_est,
18024 target_pwr_qtrdbm
18025 [tbl_id - 26] + 1);
18026 }
18027 regval[idx] = (u32) pwr_est;
18028 }
18029 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
18030 regval);
18031 }
18032
18033 wlc_phy_txpwr_limit_to_tbl_nphy(pi);
18034 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 84, 64, 8,
18035 pi->adj_pwr_tbl_nphy);
18036 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 84, 64, 8,
18037 pi->adj_pwr_tbl_nphy);
18038
18039 if (pi->phyhang_avoid)
18040 wlc_phy_stay_in_carriersearch_nphy(pi, false);
18041}
18042
18043static u32 *wlc_phy_get_ipa_gaintbl_nphy(struct brcms_phy *pi)
18044{
18045 u32 *tx_pwrctrl_tbl = NULL;
18046
18047 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18048 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18049 if ((pi->pubpi.radiorev == 4)
18050 || (pi->pubpi.radiorev == 6))
18051 tx_pwrctrl_tbl =
18052 nphy_tpc_txgain_ipa_2g_2057rev4n6;
18053 else if (pi->pubpi.radiorev == 3)
18054 tx_pwrctrl_tbl =
18055 nphy_tpc_txgain_ipa_2g_2057rev3;
18056 else if (pi->pubpi.radiorev == 5)
18057 tx_pwrctrl_tbl =
18058 nphy_tpc_txgain_ipa_2g_2057rev5;
18059 else if ((pi->pubpi.radiorev == 7)
18060 || (pi->pubpi.radiorev == 8))
18061 tx_pwrctrl_tbl =
18062 nphy_tpc_txgain_ipa_2g_2057rev7;
18063 } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
18064 tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev6;
18065 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
18066 tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
18067 } else {
18068 tx_pwrctrl_tbl = nphy_tpc_txgain_ipa;
18069 }
18070 } else {
18071
18072 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18073 if ((pi->pubpi.radiorev == 3) ||
18074 (pi->pubpi.radiorev == 4) ||
18075 (pi->pubpi.radiorev == 6))
18076 tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_5g_2057;
18077 else if ((pi->pubpi.radiorev == 7)
18078 || (pi->pubpi.radiorev == 8))
18079 tx_pwrctrl_tbl =
18080 nphy_tpc_txgain_ipa_5g_2057rev7;
18081 } else {
18082 tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_5g;
18083 }
18084 }
18085
18086 return tx_pwrctrl_tbl;
18087}
18088
18089static void wlc_phy_restore_rssical_nphy(struct brcms_phy *pi)
18090{
18091 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18092 if (pi->nphy_rssical_chanspec_2G == 0)
18093 return;
18094
18095 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18096 mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0,
18097 RADIO_2057_VCM_MASK,
18098 pi->rssical_cache.
18099 rssical_radio_regs_2G[0]);
18100 mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1,
18101 RADIO_2057_VCM_MASK,
18102 pi->rssical_cache.
18103 rssical_radio_regs_2G[1]);
18104 } else {
18105 mod_radio_reg(pi,
18106 RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX0,
18107 RADIO_2056_VCM_MASK,
18108 pi->rssical_cache.
18109 rssical_radio_regs_2G[0]);
18110 mod_radio_reg(pi,
18111 RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX1,
18112 RADIO_2056_VCM_MASK,
18113 pi->rssical_cache.
18114 rssical_radio_regs_2G[1]);
18115 }
18116
18117 write_phy_reg(pi, 0x1a6,
18118 pi->rssical_cache.rssical_phyregs_2G[0]);
18119 write_phy_reg(pi, 0x1ac,
18120 pi->rssical_cache.rssical_phyregs_2G[1]);
18121 write_phy_reg(pi, 0x1b2,
18122 pi->rssical_cache.rssical_phyregs_2G[2]);
18123 write_phy_reg(pi, 0x1b8,
18124 pi->rssical_cache.rssical_phyregs_2G[3]);
18125 write_phy_reg(pi, 0x1a4,
18126 pi->rssical_cache.rssical_phyregs_2G[4]);
18127 write_phy_reg(pi, 0x1aa,
18128 pi->rssical_cache.rssical_phyregs_2G[5]);
18129 write_phy_reg(pi, 0x1b0,
18130 pi->rssical_cache.rssical_phyregs_2G[6]);
18131 write_phy_reg(pi, 0x1b6,
18132 pi->rssical_cache.rssical_phyregs_2G[7]);
18133 write_phy_reg(pi, 0x1a5,
18134 pi->rssical_cache.rssical_phyregs_2G[8]);
18135 write_phy_reg(pi, 0x1ab,
18136 pi->rssical_cache.rssical_phyregs_2G[9]);
18137 write_phy_reg(pi, 0x1b1,
18138 pi->rssical_cache.rssical_phyregs_2G[10]);
18139 write_phy_reg(pi, 0x1b7,
18140 pi->rssical_cache.rssical_phyregs_2G[11]);
18141
18142 } else {
18143 if (pi->nphy_rssical_chanspec_5G == 0)
18144 return;
18145
18146 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18147 mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0,
18148 RADIO_2057_VCM_MASK,
18149 pi->rssical_cache.
18150 rssical_radio_regs_5G[0]);
18151 mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1,
18152 RADIO_2057_VCM_MASK,
18153 pi->rssical_cache.
18154 rssical_radio_regs_5G[1]);
18155 } else {
18156 mod_radio_reg(pi,
18157 RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX0,
18158 RADIO_2056_VCM_MASK,
18159 pi->rssical_cache.
18160 rssical_radio_regs_5G[0]);
18161 mod_radio_reg(pi,
18162 RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX1,
18163 RADIO_2056_VCM_MASK,
18164 pi->rssical_cache.
18165 rssical_radio_regs_5G[1]);
18166 }
18167
18168 write_phy_reg(pi, 0x1a6,
18169 pi->rssical_cache.rssical_phyregs_5G[0]);
18170 write_phy_reg(pi, 0x1ac,
18171 pi->rssical_cache.rssical_phyregs_5G[1]);
18172 write_phy_reg(pi, 0x1b2,
18173 pi->rssical_cache.rssical_phyregs_5G[2]);
18174 write_phy_reg(pi, 0x1b8,
18175 pi->rssical_cache.rssical_phyregs_5G[3]);
18176 write_phy_reg(pi, 0x1a4,
18177 pi->rssical_cache.rssical_phyregs_5G[4]);
18178 write_phy_reg(pi, 0x1aa,
18179 pi->rssical_cache.rssical_phyregs_5G[5]);
18180 write_phy_reg(pi, 0x1b0,
18181 pi->rssical_cache.rssical_phyregs_5G[6]);
18182 write_phy_reg(pi, 0x1b6,
18183 pi->rssical_cache.rssical_phyregs_5G[7]);
18184 write_phy_reg(pi, 0x1a5,
18185 pi->rssical_cache.rssical_phyregs_5G[8]);
18186 write_phy_reg(pi, 0x1ab,
18187 pi->rssical_cache.rssical_phyregs_5G[9]);
18188 write_phy_reg(pi, 0x1b1,
18189 pi->rssical_cache.rssical_phyregs_5G[10]);
18190 write_phy_reg(pi, 0x1b7,
18191 pi->rssical_cache.rssical_phyregs_5G[11]);
18192 }
18193}
18194
18195static void wlc_phy_internal_cal_txgain_nphy(struct brcms_phy *pi)
18196{
18197 u16 txcal_gain[2];
18198
18199 pi->nphy_txcal_pwr_idx[0] = pi->nphy_cal_orig_pwr_idx[0];
18200 pi->nphy_txcal_pwr_idx[1] = pi->nphy_cal_orig_pwr_idx[0];
18201 wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_cal_orig_pwr_idx[0], true);
18202 wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_cal_orig_pwr_idx[1], true);
18203
18204 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
18205 txcal_gain);
18206
18207 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18208 txcal_gain[0] = (txcal_gain[0] & 0xF000) | 0x0F40;
18209 txcal_gain[1] = (txcal_gain[1] & 0xF000) | 0x0F40;
18210 } else {
18211 txcal_gain[0] = (txcal_gain[0] & 0xF000) | 0x0F60;
18212 txcal_gain[1] = (txcal_gain[1] & 0xF000) | 0x0F60;
18213 }
18214
18215 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
18216 txcal_gain);
18217}
18218
18219static void wlc_phy_precal_txgain_nphy(struct brcms_phy *pi)
18220{
18221 bool save_bbmult = false;
18222 u8 txcal_index_2057_rev5n7 = 0;
18223 u8 txcal_index_2057_rev3n4n6 = 10;
18224
18225 if (pi->use_int_tx_iqlo_cal_nphy) {
18226 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18227 if ((pi->pubpi.radiorev == 3) ||
18228 (pi->pubpi.radiorev == 4) ||
18229 (pi->pubpi.radiorev == 6)) {
18230
18231 pi->nphy_txcal_pwr_idx[0] =
18232 txcal_index_2057_rev3n4n6;
18233 pi->nphy_txcal_pwr_idx[1] =
18234 txcal_index_2057_rev3n4n6;
18235 wlc_phy_txpwr_index_nphy(
18236 pi, 3,
18237 txcal_index_2057_rev3n4n6,
18238 false);
18239 } else {
18240
18241 pi->nphy_txcal_pwr_idx[0] =
18242 txcal_index_2057_rev5n7;
18243 pi->nphy_txcal_pwr_idx[1] =
18244 txcal_index_2057_rev5n7;
18245 wlc_phy_txpwr_index_nphy(
18246 pi, 3,
18247 txcal_index_2057_rev5n7,
18248 false);
18249 }
18250 save_bbmult = true;
18251
18252 } else if (NREV_LT(pi->pubpi.phy_rev, 5)) {
18253 wlc_phy_cal_txgainctrl_nphy(pi, 11, false);
18254 if (pi->sh->hw_phytxchain != 3) {
18255 pi->nphy_txcal_pwr_idx[1] =
18256 pi->nphy_txcal_pwr_idx[0];
18257 wlc_phy_txpwr_index_nphy(pi, 3,
18258 pi->
18259 nphy_txcal_pwr_idx[0],
18260 true);
18261 save_bbmult = true;
18262 }
18263
18264 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
18265 if (PHY_IPA(pi)) {
18266 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18267 wlc_phy_cal_txgainctrl_nphy(pi, 12,
18268 false);
18269 } else {
18270 pi->nphy_txcal_pwr_idx[0] = 80;
18271 pi->nphy_txcal_pwr_idx[1] = 80;
18272 wlc_phy_txpwr_index_nphy(pi, 3, 80,
18273 false);
18274 save_bbmult = true;
18275 }
18276 } else {
18277 wlc_phy_internal_cal_txgain_nphy(pi);
18278 save_bbmult = true;
18279 }
18280
18281 } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
18282 if (PHY_IPA(pi)) {
18283 if (CHSPEC_IS2G(pi->radio_chanspec))
18284 wlc_phy_cal_txgainctrl_nphy(pi, 12,
18285 false);
18286 else
18287 wlc_phy_cal_txgainctrl_nphy(pi, 14,
18288 false);
18289 } else {
18290 wlc_phy_internal_cal_txgain_nphy(pi);
18291 save_bbmult = true;
18292 }
18293 }
18294
18295 } else {
18296 wlc_phy_cal_txgainctrl_nphy(pi, 10, false);
18297 }
18298
18299 if (save_bbmult)
18300 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16,
18301 &pi->nphy_txcal_bbmult);
18302}
18303
18304static void
18305wlc_phy_rfctrlintc_override_nphy(struct brcms_phy *pi, u8 field, u16 value,
18306 u8 core_code)
18307{
18308 u16 mask;
18309 u16 val;
18310 u8 core;
18311
18312 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18313 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
18314 if (core_code == RADIO_MIMO_CORESEL_CORE1
18315 && core == PHY_CORE_1)
18316 continue;
18317 else if (core_code == RADIO_MIMO_CORESEL_CORE2
18318 && core == PHY_CORE_0)
18319 continue;
18320
18321 if (NREV_LT(pi->pubpi.phy_rev, 7)) {
18322
18323 mask = (0x1 << 10);
18324 val = 1 << 10;
18325 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x91 :
18326 0x92, mask, val);
18327 }
18328
18329 if (field == NPHY_RfctrlIntc_override_OFF) {
18330
18331 write_phy_reg(pi, (core == PHY_CORE_0) ? 0x91 :
18332 0x92, 0);
18333
18334 wlc_phy_force_rfseq_nphy(pi,
18335 NPHY_RFSEQ_RESET2RX);
18336 } else if (field == NPHY_RfctrlIntc_override_TRSW) {
18337
18338 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18339
18340 mask = (0x1 << 6) | (0x1 << 7);
18341
18342 val = value << 6;
18343 mod_phy_reg(pi,
18344 (core ==
18345 PHY_CORE_0) ? 0x91 : 0x92,
18346 mask, val);
18347
18348 or_phy_reg(pi,
18349 (core ==
18350 PHY_CORE_0) ? 0x91 : 0x92,
18351 (0x1 << 10));
18352
18353 and_phy_reg(pi, 0x2ff, (u16)
18354 ~(0x3 << 14));
18355 or_phy_reg(pi, 0x2ff, (0x1 << 13));
18356 or_phy_reg(pi, 0x2ff, (0x1 << 0));
18357 } else {
18358
18359 mask = (0x1 << 6) |
18360 (0x1 << 7) |
18361 (0x1 << 8) | (0x1 << 9);
18362 val = value << 6;
18363 mod_phy_reg(pi,
18364 (core ==
18365 PHY_CORE_0) ? 0x91 : 0x92,
18366 mask, val);
18367
18368 mask = (0x1 << 0);
18369 val = 1 << 0;
18370 mod_phy_reg(pi,
18371 (core ==
18372 PHY_CORE_0) ? 0xe7 : 0xec,
18373 mask, val);
18374
18375 mask = (core == PHY_CORE_0) ?
18376 (0x1 << 0) : (0x1 << 1);
18377 val = 1 << ((core == PHY_CORE_0) ?
18378 0 : 1);
18379 mod_phy_reg(pi, 0x78, mask, val);
18380
18381 SPINWAIT(((read_phy_reg(pi, 0x78) & val)
18382 != 0), 10000);
18383 if (WARN(read_phy_reg(pi, 0x78) & val,
18384 "HW error: override failed"))
18385 return;
18386
18387 mask = (0x1 << 0);
18388 val = 0 << 0;
18389 mod_phy_reg(pi,
18390 (core ==
18391 PHY_CORE_0) ? 0xe7 : 0xec,
18392 mask, val);
18393 }
18394 } else if (field == NPHY_RfctrlIntc_override_PA) {
18395 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18396
18397 mask = (0x1 << 4) | (0x1 << 5);
18398
18399 if (CHSPEC_IS5G(pi->radio_chanspec))
18400 val = value << 5;
18401 else
18402 val = value << 4;
18403
18404 mod_phy_reg(pi,
18405 (core ==
18406 PHY_CORE_0) ? 0x91 : 0x92,
18407 mask, val);
18408
18409 or_phy_reg(pi,
18410 (core ==
18411 PHY_CORE_0) ? 0x91 : 0x92,
18412 (0x1 << 12));
18413 } else {
18414
18415 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18416 mask = (0x1 << 5);
18417 val = value << 5;
18418 } else {
18419 mask = (0x1 << 4);
18420 val = value << 4;
18421 }
18422 mod_phy_reg(pi,
18423 (core ==
18424 PHY_CORE_0) ? 0x91 : 0x92,
18425 mask, val);
18426 }
18427 } else if (field ==
18428 NPHY_RfctrlIntc_override_EXT_LNA_PU) {
18429 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18430 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18431
18432 mask = (0x1 << 0);
18433 val = value << 0;
18434 mod_phy_reg(pi,
18435 (core ==
18436 PHY_CORE_0) ? 0x91
18437 : 0x92, mask, val);
18438
18439 mask = (0x1 << 2);
18440 mod_phy_reg(pi,
18441 (core ==
18442 PHY_CORE_0) ? 0x91
18443 : 0x92, mask, 0);
18444 } else {
18445
18446 mask = (0x1 << 2);
18447 val = value << 2;
18448 mod_phy_reg(pi,
18449 (core ==
18450 PHY_CORE_0) ? 0x91
18451 : 0x92, mask, val);
18452
18453 mask = (0x1 << 0);
18454 mod_phy_reg(pi,
18455 (core ==
18456 PHY_CORE_0) ? 0x91
18457 : 0x92, mask, 0);
18458 }
18459
18460 mask = (0x1 << 11);
18461 val = 1 << 11;
18462 mod_phy_reg(pi,
18463 (core ==
18464 PHY_CORE_0) ? 0x91 : 0x92,
18465 mask, val);
18466 } else {
18467
18468 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18469 mask = (0x1 << 0);
18470 val = value << 0;
18471 } else {
18472 mask = (0x1 << 2);
18473 val = value << 2;
18474 }
18475 mod_phy_reg(pi,
18476 (core ==
18477 PHY_CORE_0) ? 0x91 : 0x92,
18478 mask, val);
18479 }
18480 } else if (field ==
18481 NPHY_RfctrlIntc_override_EXT_LNA_GAIN) {
18482 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18483 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18484
18485 mask = (0x1 << 1);
18486 val = value << 1;
18487 mod_phy_reg(pi,
18488 (core ==
18489 PHY_CORE_0) ? 0x91
18490 : 0x92, mask, val);
18491
18492 mask = (0x1 << 3);
18493 mod_phy_reg(pi,
18494 (core ==
18495 PHY_CORE_0) ? 0x91
18496 : 0x92, mask, 0);
18497 } else {
18498
18499 mask = (0x1 << 3);
18500 val = value << 3;
18501 mod_phy_reg(pi,
18502 (core ==
18503 PHY_CORE_0) ? 0x91
18504 : 0x92, mask, val);
18505
18506 mask = (0x1 << 1);
18507 mod_phy_reg(pi,
18508 (core ==
18509 PHY_CORE_0) ? 0x91
18510 : 0x92, mask, 0);
18511 }
18512
18513 mask = (0x1 << 11);
18514 val = 1 << 11;
18515 mod_phy_reg(pi,
18516 (core ==
18517 PHY_CORE_0) ? 0x91 : 0x92,
18518 mask, val);
18519 } else {
18520
18521 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18522 mask = (0x1 << 1);
18523 val = value << 1;
18524 } else {
18525 mask = (0x1 << 3);
18526 val = value << 3;
18527 }
18528 mod_phy_reg(pi,
18529 (core ==
18530 PHY_CORE_0) ? 0x91 : 0x92,
18531 mask, val);
18532 }
18533 }
18534 }
18535 }
18536}
18537
18538void
18539wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi, s32 dBm_targetpower,
18540 bool debug)
18541{
18542 int gainctrl_loopidx;
18543 uint core;
18544 u16 m0m1, curr_m0m1;
18545 s32 delta_power;
18546 s32 txpwrindex;
18547 s32 qdBm_power[2];
18548 u16 orig_BBConfig;
18549 u16 phy_saveregs[4];
18550 u32 freq_test;
18551 u16 ampl_test = 250;
18552 uint stepsize;
18553 bool phyhang_avoid_state = false;
18554
18555 if (NREV_GE(pi->pubpi.phy_rev, 7))
18556 stepsize = 2;
18557 else
18558 stepsize = 1;
18559
18560 if (CHSPEC_IS40(pi->radio_chanspec))
18561 freq_test = 5000;
18562 else
18563 freq_test = 2500;
18564
18565 wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_cal_orig_pwr_idx[0], true);
18566 wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_cal_orig_pwr_idx[1], true);
18567
18568 if (pi->phyhang_avoid)
18569 wlc_phy_stay_in_carriersearch_nphy(pi, true);
18570
18571 phyhang_avoid_state = pi->phyhang_avoid;
18572 pi->phyhang_avoid = false;
18573
18574 phy_saveregs[0] = read_phy_reg(pi, 0x91);
18575 phy_saveregs[1] = read_phy_reg(pi, 0x92);
18576 phy_saveregs[2] = read_phy_reg(pi, 0xe7);
18577 phy_saveregs[3] = read_phy_reg(pi, 0xec);
18578 wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_PA, 1,
18579 RADIO_MIMO_CORESEL_CORE1 |
18580 RADIO_MIMO_CORESEL_CORE2);
18581
18582 if (!debug) {
18583 wlc_phy_rfctrlintc_override_nphy(pi,
18584 NPHY_RfctrlIntc_override_TRSW,
18585 0x2, RADIO_MIMO_CORESEL_CORE1);
18586 wlc_phy_rfctrlintc_override_nphy(pi,
18587 NPHY_RfctrlIntc_override_TRSW,
18588 0x8, RADIO_MIMO_CORESEL_CORE2);
18589 } else {
18590 wlc_phy_rfctrlintc_override_nphy(pi,
18591 NPHY_RfctrlIntc_override_TRSW,
18592 0x1, RADIO_MIMO_CORESEL_CORE1);
18593 wlc_phy_rfctrlintc_override_nphy(pi,
18594 NPHY_RfctrlIntc_override_TRSW,
18595 0x7, RADIO_MIMO_CORESEL_CORE2);
18596 }
18597
18598 orig_BBConfig = read_phy_reg(pi, 0x01);
18599 mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
18600
18601 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1);
18602
18603 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
18604 txpwrindex = (s32) pi->nphy_cal_orig_pwr_idx[core];
18605
18606 for (gainctrl_loopidx = 0; gainctrl_loopidx < 2;
18607 gainctrl_loopidx++) {
18608 wlc_phy_tx_tone_nphy(pi, freq_test, ampl_test, 0, 0,
18609 false);
18610
18611 if (core == PHY_CORE_0)
18612 curr_m0m1 = m0m1 & 0xff00;
18613 else
18614 curr_m0m1 = m0m1 & 0x00ff;
18615
18616 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &curr_m0m1);
18617 wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &curr_m0m1);
18618
18619 udelay(50);
18620
18621 wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
18622 NPHY_CAL_TSSISAMPS);
18623
18624 pi->nphy_bb_mult_save = 0;
18625 wlc_phy_stopplayback_nphy(pi);
18626
18627 delta_power = (dBm_targetpower * 4) - qdBm_power[core];
18628
18629 txpwrindex -= stepsize * delta_power;
18630 if (txpwrindex < 0)
18631 txpwrindex = 0;
18632 else if (txpwrindex > 127)
18633 txpwrindex = 127;
18634
18635 if (CHSPEC_IS5G(pi->radio_chanspec)) {
18636 if (NREV_IS(pi->pubpi.phy_rev, 4) &&
18637 (pi->srom_fem5g.extpagain == 3)) {
18638 if (txpwrindex < 30)
18639 txpwrindex = 30;
18640 }
18641 } else {
18642 if (NREV_GE(pi->pubpi.phy_rev, 5) &&
18643 (pi->srom_fem2g.extpagain == 3)) {
18644 if (txpwrindex < 50)
18645 txpwrindex = 50;
18646 }
18647 }
18648
18649 wlc_phy_txpwr_index_nphy(pi, (1 << core),
18650 (u8) txpwrindex, true);
18651 }
18652
18653 pi->nphy_txcal_pwr_idx[core] = (u8) txpwrindex;
18654
18655 if (debug) {
18656 u16 radio_gain;
18657 u16 dbg_m0m1;
18658
18659 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &dbg_m0m1);
18660
18661 wlc_phy_tx_tone_nphy(pi, freq_test, ampl_test, 0, 0,
18662 false);
18663
18664 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &dbg_m0m1);
18665 wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &dbg_m0m1);
18666
18667 udelay(100);
18668
18669 wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
18670 NPHY_CAL_TSSISAMPS);
18671
18672 wlc_phy_table_read_nphy(pi, 7, 1, (0x110 + core), 16,
18673 &radio_gain);
18674
18675 mdelay(4000);
18676 pi->nphy_bb_mult_save = 0;
18677 wlc_phy_stopplayback_nphy(pi);
18678 }
18679 }
18680
18681 wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_txcal_pwr_idx[0], true);
18682 wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_txcal_pwr_idx[1], true);
18683
18684 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &pi->nphy_txcal_bbmult);
18685
18686 write_phy_reg(pi, 0x01, orig_BBConfig);
18687
18688 write_phy_reg(pi, 0x91, phy_saveregs[0]);
18689 write_phy_reg(pi, 0x92, phy_saveregs[1]);
18690 write_phy_reg(pi, 0xe7, phy_saveregs[2]);
18691 write_phy_reg(pi, 0xec, phy_saveregs[3]);
18692
18693 pi->phyhang_avoid = phyhang_avoid_state;
18694
18695 if (pi->phyhang_avoid)
18696 wlc_phy_stay_in_carriersearch_nphy(pi, false);
18697}
18698
18699static void wlc_phy_savecal_nphy(struct brcms_phy *pi)
18700{
18701 void *tbl_ptr;
18702 int coreNum;
18703 u16 *txcal_radio_regs = NULL;
18704
18705 if (pi->phyhang_avoid)
18706 wlc_phy_stay_in_carriersearch_nphy(pi, true);
18707
18708 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18709
18710 wlc_phy_rx_iq_coeffs_nphy(pi, 0,
18711 &pi->calibration_cache.
18712 rxcal_coeffs_2G);
18713
18714 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18715 txcal_radio_regs =
18716 pi->calibration_cache.txcal_radio_regs_2G;
18717 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18718
18719 pi->calibration_cache.txcal_radio_regs_2G[0] =
18720 read_radio_reg(pi,
18721 RADIO_2056_TX_LOFT_FINE_I |
18722 RADIO_2056_TX0);
18723 pi->calibration_cache.txcal_radio_regs_2G[1] =
18724 read_radio_reg(pi,
18725 RADIO_2056_TX_LOFT_FINE_Q |
18726 RADIO_2056_TX0);
18727 pi->calibration_cache.txcal_radio_regs_2G[2] =
18728 read_radio_reg(pi,
18729 RADIO_2056_TX_LOFT_FINE_I |
18730 RADIO_2056_TX1);
18731 pi->calibration_cache.txcal_radio_regs_2G[3] =
18732 read_radio_reg(pi,
18733 RADIO_2056_TX_LOFT_FINE_Q |
18734 RADIO_2056_TX1);
18735
18736 pi->calibration_cache.txcal_radio_regs_2G[4] =
18737 read_radio_reg(pi,
18738 RADIO_2056_TX_LOFT_COARSE_I |
18739 RADIO_2056_TX0);
18740 pi->calibration_cache.txcal_radio_regs_2G[5] =
18741 read_radio_reg(pi,
18742 RADIO_2056_TX_LOFT_COARSE_Q |
18743 RADIO_2056_TX0);
18744 pi->calibration_cache.txcal_radio_regs_2G[6] =
18745 read_radio_reg(pi,
18746 RADIO_2056_TX_LOFT_COARSE_I |
18747 RADIO_2056_TX1);
18748 pi->calibration_cache.txcal_radio_regs_2G[7] =
18749 read_radio_reg(pi,
18750 RADIO_2056_TX_LOFT_COARSE_Q |
18751 RADIO_2056_TX1);
18752 } else {
18753 pi->calibration_cache.txcal_radio_regs_2G[0] =
18754 read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
18755 pi->calibration_cache.txcal_radio_regs_2G[1] =
18756 read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
18757 pi->calibration_cache.txcal_radio_regs_2G[2] =
18758 read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
18759 pi->calibration_cache.txcal_radio_regs_2G[3] =
18760 read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
18761 }
18762
18763 pi->nphy_iqcal_chanspec_2G = pi->radio_chanspec;
18764 tbl_ptr = pi->calibration_cache.txcal_coeffs_2G;
18765 } else {
18766
18767 wlc_phy_rx_iq_coeffs_nphy(pi, 0,
18768 &pi->calibration_cache.
18769 rxcal_coeffs_5G);
18770
18771 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18772 txcal_radio_regs =
18773 pi->calibration_cache.txcal_radio_regs_5G;
18774 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18775
18776 pi->calibration_cache.txcal_radio_regs_5G[0] =
18777 read_radio_reg(pi,
18778 RADIO_2056_TX_LOFT_FINE_I |
18779 RADIO_2056_TX0);
18780 pi->calibration_cache.txcal_radio_regs_5G[1] =
18781 read_radio_reg(pi,
18782 RADIO_2056_TX_LOFT_FINE_Q |
18783 RADIO_2056_TX0);
18784 pi->calibration_cache.txcal_radio_regs_5G[2] =
18785 read_radio_reg(pi,
18786 RADIO_2056_TX_LOFT_FINE_I |
18787 RADIO_2056_TX1);
18788 pi->calibration_cache.txcal_radio_regs_5G[3] =
18789 read_radio_reg(pi,
18790 RADIO_2056_TX_LOFT_FINE_Q |
18791 RADIO_2056_TX1);
18792
18793 pi->calibration_cache.txcal_radio_regs_5G[4] =
18794 read_radio_reg(pi,
18795 RADIO_2056_TX_LOFT_COARSE_I |
18796 RADIO_2056_TX0);
18797 pi->calibration_cache.txcal_radio_regs_5G[5] =
18798 read_radio_reg(pi,
18799 RADIO_2056_TX_LOFT_COARSE_Q |
18800 RADIO_2056_TX0);
18801 pi->calibration_cache.txcal_radio_regs_5G[6] =
18802 read_radio_reg(pi,
18803 RADIO_2056_TX_LOFT_COARSE_I |
18804 RADIO_2056_TX1);
18805 pi->calibration_cache.txcal_radio_regs_5G[7] =
18806 read_radio_reg(pi,
18807 RADIO_2056_TX_LOFT_COARSE_Q |
18808 RADIO_2056_TX1);
18809 } else {
18810 pi->calibration_cache.txcal_radio_regs_5G[0] =
18811 read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
18812 pi->calibration_cache.txcal_radio_regs_5G[1] =
18813 read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
18814 pi->calibration_cache.txcal_radio_regs_5G[2] =
18815 read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
18816 pi->calibration_cache.txcal_radio_regs_5G[3] =
18817 read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
18818 }
18819
18820 pi->nphy_iqcal_chanspec_5G = pi->radio_chanspec;
18821 tbl_ptr = pi->calibration_cache.txcal_coeffs_5G;
18822 }
18823 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18824 for (coreNum = 0; coreNum <= 1; coreNum++) {
18825
18826 txcal_radio_regs[2 * coreNum] =
18827 READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18828 LOFT_FINE_I);
18829 txcal_radio_regs[2 * coreNum + 1] =
18830 READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18831 LOFT_FINE_Q);
18832
18833 txcal_radio_regs[2 * coreNum + 4] =
18834 READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18835 LOFT_COARSE_I);
18836 txcal_radio_regs[2 * coreNum + 5] =
18837 READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
18838 LOFT_COARSE_Q);
18839 }
18840 }
18841
18842 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 8, 80, 16, tbl_ptr);
18843
18844 if (pi->phyhang_avoid)
18845 wlc_phy_stay_in_carriersearch_nphy(pi, false);
18846}
18847
18848static void wlc_phy_tx_iq_war_nphy(struct brcms_phy *pi)
18849{
18850 struct nphy_iq_comp tx_comp;
18851
18852 wlc_phy_table_read_nphy(pi, 15, 4, 0x50, 16, &tx_comp);
18853
18854 wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ, tx_comp.a0);
18855 wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 2, tx_comp.b0);
18856 wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 4, tx_comp.a1);
18857 wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 6, tx_comp.b1);
18858}
18859
18860static void wlc_phy_restorecal_nphy(struct brcms_phy *pi)
18861{
18862 u16 *loft_comp;
18863 u16 txcal_coeffs_bphy[4];
18864 u16 *tbl_ptr;
18865 int coreNum;
18866 u16 *txcal_radio_regs = NULL;
18867
18868 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18869 if (pi->nphy_iqcal_chanspec_2G == 0)
18870 return;
18871
18872 tbl_ptr = pi->calibration_cache.txcal_coeffs_2G;
18873 loft_comp = &pi->calibration_cache.txcal_coeffs_2G[5];
18874 } else {
18875 if (pi->nphy_iqcal_chanspec_5G == 0)
18876 return;
18877
18878 tbl_ptr = pi->calibration_cache.txcal_coeffs_5G;
18879 loft_comp = &pi->calibration_cache.txcal_coeffs_5G[5];
18880 }
18881
18882 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80, 16, tbl_ptr);
18883
18884 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18885 txcal_coeffs_bphy[0] = tbl_ptr[0];
18886 txcal_coeffs_bphy[1] = tbl_ptr[1];
18887 txcal_coeffs_bphy[2] = tbl_ptr[2];
18888 txcal_coeffs_bphy[3] = tbl_ptr[3];
18889 } else {
18890 txcal_coeffs_bphy[0] = 0;
18891 txcal_coeffs_bphy[1] = 0;
18892 txcal_coeffs_bphy[2] = 0;
18893 txcal_coeffs_bphy[3] = 0;
18894 }
18895
18896 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88, 16,
18897 txcal_coeffs_bphy);
18898
18899 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85, 16, loft_comp);
18900
18901 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93, 16, loft_comp);
18902
18903 if (NREV_LT(pi->pubpi.phy_rev, 2))
18904 wlc_phy_tx_iq_war_nphy(pi);
18905
18906 if (CHSPEC_IS2G(pi->radio_chanspec)) {
18907 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18908 txcal_radio_regs =
18909 pi->calibration_cache.txcal_radio_regs_2G;
18910 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18911
18912 write_radio_reg(pi,
18913 RADIO_2056_TX_LOFT_FINE_I |
18914 RADIO_2056_TX0,
18915 pi->calibration_cache.
18916 txcal_radio_regs_2G[0]);
18917 write_radio_reg(pi,
18918 RADIO_2056_TX_LOFT_FINE_Q |
18919 RADIO_2056_TX0,
18920 pi->calibration_cache.
18921 txcal_radio_regs_2G[1]);
18922 write_radio_reg(pi,
18923 RADIO_2056_TX_LOFT_FINE_I |
18924 RADIO_2056_TX1,
18925 pi->calibration_cache.
18926 txcal_radio_regs_2G[2]);
18927 write_radio_reg(pi,
18928 RADIO_2056_TX_LOFT_FINE_Q |
18929 RADIO_2056_TX1,
18930 pi->calibration_cache.
18931 txcal_radio_regs_2G[3]);
18932
18933 write_radio_reg(pi,
18934 RADIO_2056_TX_LOFT_COARSE_I |
18935 RADIO_2056_TX0,
18936 pi->calibration_cache.
18937 txcal_radio_regs_2G[4]);
18938 write_radio_reg(pi,
18939 RADIO_2056_TX_LOFT_COARSE_Q |
18940 RADIO_2056_TX0,
18941 pi->calibration_cache.
18942 txcal_radio_regs_2G[5]);
18943 write_radio_reg(pi,
18944 RADIO_2056_TX_LOFT_COARSE_I |
18945 RADIO_2056_TX1,
18946 pi->calibration_cache.
18947 txcal_radio_regs_2G[6]);
18948 write_radio_reg(pi,
18949 RADIO_2056_TX_LOFT_COARSE_Q |
18950 RADIO_2056_TX1,
18951 pi->calibration_cache.
18952 txcal_radio_regs_2G[7]);
18953 } else {
18954 write_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL,
18955 pi->calibration_cache.
18956 txcal_radio_regs_2G[0]);
18957 write_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL,
18958 pi->calibration_cache.
18959 txcal_radio_regs_2G[1]);
18960 write_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM,
18961 pi->calibration_cache.
18962 txcal_radio_regs_2G[2]);
18963 write_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM,
18964 pi->calibration_cache.
18965 txcal_radio_regs_2G[3]);
18966 }
18967
18968 wlc_phy_rx_iq_coeffs_nphy(pi, 1,
18969 &pi->calibration_cache.
18970 rxcal_coeffs_2G);
18971 } else {
18972 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
18973 txcal_radio_regs =
18974 pi->calibration_cache.txcal_radio_regs_5G;
18975 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18976
18977 write_radio_reg(pi,
18978 RADIO_2056_TX_LOFT_FINE_I |
18979 RADIO_2056_TX0,
18980 pi->calibration_cache.
18981 txcal_radio_regs_5G[0]);
18982 write_radio_reg(pi,
18983 RADIO_2056_TX_LOFT_FINE_Q |
18984 RADIO_2056_TX0,
18985 pi->calibration_cache.
18986 txcal_radio_regs_5G[1]);
18987 write_radio_reg(pi,
18988 RADIO_2056_TX_LOFT_FINE_I |
18989 RADIO_2056_TX1,
18990 pi->calibration_cache.
18991 txcal_radio_regs_5G[2]);
18992 write_radio_reg(pi,
18993 RADIO_2056_TX_LOFT_FINE_Q |
18994 RADIO_2056_TX1,
18995 pi->calibration_cache.
18996 txcal_radio_regs_5G[3]);
18997
18998 write_radio_reg(pi,
18999 RADIO_2056_TX_LOFT_COARSE_I |
19000 RADIO_2056_TX0,
19001 pi->calibration_cache.
19002 txcal_radio_regs_5G[4]);
19003 write_radio_reg(pi,
19004 RADIO_2056_TX_LOFT_COARSE_Q |
19005 RADIO_2056_TX0,
19006 pi->calibration_cache.
19007 txcal_radio_regs_5G[5]);
19008 write_radio_reg(pi,
19009 RADIO_2056_TX_LOFT_COARSE_I |
19010 RADIO_2056_TX1,
19011 pi->calibration_cache.
19012 txcal_radio_regs_5G[6]);
19013 write_radio_reg(pi,
19014 RADIO_2056_TX_LOFT_COARSE_Q |
19015 RADIO_2056_TX1,
19016 pi->calibration_cache.
19017 txcal_radio_regs_5G[7]);
19018 } else {
19019 write_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL,
19020 pi->calibration_cache.
19021 txcal_radio_regs_5G[0]);
19022 write_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL,
19023 pi->calibration_cache.
19024 txcal_radio_regs_5G[1]);
19025 write_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM,
19026 pi->calibration_cache.
19027 txcal_radio_regs_5G[2]);
19028 write_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM,
19029 pi->calibration_cache.
19030 txcal_radio_regs_5G[3]);
19031 }
19032
19033 wlc_phy_rx_iq_coeffs_nphy(pi, 1,
19034 &pi->calibration_cache.
19035 rxcal_coeffs_5G);
19036 }
19037
19038 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
19039 for (coreNum = 0; coreNum <= 1; coreNum++) {
19040
19041 WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
19042 LOFT_FINE_I,
19043 txcal_radio_regs[2 * coreNum]);
19044 WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
19045 LOFT_FINE_Q,
19046 txcal_radio_regs[2 * coreNum + 1]);
19047
19048 WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
19049 LOFT_COARSE_I,
19050 txcal_radio_regs[2 * coreNum + 4]);
19051 WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
19052 LOFT_COARSE_Q,
19053 txcal_radio_regs[2 * coreNum + 5]);
19054 }
19055 }
19056}
19057
19058static void wlc_phy_txpwrctrl_coeff_setup_nphy(struct brcms_phy *pi)
19059{
19060 u32 idx;
19061 u16 iqloCalbuf[7];
19062 u32 iqcomp, locomp, curr_locomp;
19063 s8 locomp_i, locomp_q;
19064 s8 curr_locomp_i, curr_locomp_q;
19065 u32 tbl_id, tbl_len, tbl_offset;
19066 u32 regval[128];
19067
19068 if (pi->phyhang_avoid)
19069 wlc_phy_stay_in_carriersearch_nphy(pi, true);
19070
19071 wlc_phy_table_read_nphy(pi, 15, 7, 80, 16, iqloCalbuf);
19072
19073 tbl_len = 128;
19074 tbl_offset = 320;
19075 for (tbl_id = NPHY_TBL_ID_CORE1TXPWRCTL;
19076 tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
19077 iqcomp =
19078 (tbl_id ==
19079 26) ? (((u32) (iqloCalbuf[0] & 0x3ff)) << 10) |
19080 (iqloCalbuf[1] & 0x3ff)
19081 : (((u32) (iqloCalbuf[2] & 0x3ff)) << 10) |
19082 (iqloCalbuf[3] & 0x3ff);
19083
19084 for (idx = 0; idx < tbl_len; idx++)
19085 regval[idx] = iqcomp;
19086 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
19087 regval);
19088 }
19089
19090 tbl_offset = 448;
19091 for (tbl_id = NPHY_TBL_ID_CORE1TXPWRCTL;
19092 tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
19093
19094 locomp =
19095 (u32) ((tbl_id == 26) ? iqloCalbuf[5] : iqloCalbuf[6]);
19096 locomp_i = (s8) ((locomp >> 8) & 0xff);
19097 locomp_q = (s8) ((locomp) & 0xff);
19098 for (idx = 0; idx < tbl_len; idx++) {
19099 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19100 curr_locomp_i = locomp_i;
19101 curr_locomp_q = locomp_q;
19102 } else {
19103 curr_locomp_i = (s8) ((locomp_i *
19104 nphy_tpc_loscale[idx] +
19105 128) >> 8);
19106 curr_locomp_q =
19107 (s8) ((locomp_q *
19108 nphy_tpc_loscale[idx] +
19109 128) >> 8);
19110 }
19111 curr_locomp = (u32) ((curr_locomp_i & 0xff) << 8);
19112 curr_locomp |= (u32) (curr_locomp_q & 0xff);
19113 regval[idx] = curr_locomp;
19114 }
19115 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
19116 regval);
19117 }
19118
19119 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
19120
19121 wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX1, 0xFFFF);
19122 wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX2, 0xFFFF);
19123 }
19124
19125 if (pi->phyhang_avoid)
19126 wlc_phy_stay_in_carriersearch_nphy(pi, false);
19127}
19128
19129static void wlc_phy_txlpfbw_nphy(struct brcms_phy *pi)
19130{
19131 u8 tx_lpf_bw = 0;
19132
19133 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
19134 if (CHSPEC_IS40(pi->radio_chanspec))
19135 tx_lpf_bw = 3;
19136 else
19137 tx_lpf_bw = 1;
19138
19139 if (PHY_IPA(pi)) {
19140 if (CHSPEC_IS40(pi->radio_chanspec))
19141 tx_lpf_bw = 5;
19142 else
19143 tx_lpf_bw = 4;
19144 }
19145
19146 write_phy_reg(pi, 0xe8,
19147 (tx_lpf_bw << 0) |
19148 (tx_lpf_bw << 3) |
19149 (tx_lpf_bw << 6) | (tx_lpf_bw << 9));
19150
19151 if (PHY_IPA(pi)) {
19152
19153 if (CHSPEC_IS40(pi->radio_chanspec))
19154 tx_lpf_bw = 4;
19155 else
19156 tx_lpf_bw = 1;
19157
19158 write_phy_reg(pi, 0xe9,
19159 (tx_lpf_bw << 0) |
19160 (tx_lpf_bw << 3) |
19161 (tx_lpf_bw << 6) | (tx_lpf_bw << 9));
19162 }
19163 }
19164}
19165
19166static void
19167wlc_phy_adjust_rx_analpfbw_nphy(struct brcms_phy *pi, u16 reduction_factr)
19168{
19169 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
19170 if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) &&
19171 CHSPEC_IS40(pi->radio_chanspec)) {
19172 if (!pi->nphy_anarxlpf_adjusted) {
19173 write_radio_reg(pi,
19174 (RADIO_2056_RX_RXLPF_RCCAL_LPC |
19175 RADIO_2056_RX0),
19176 ((pi->nphy_rccal_value +
19177 reduction_factr) | 0x80));
19178
19179 pi->nphy_anarxlpf_adjusted = true;
19180 }
19181 } else {
19182 if (pi->nphy_anarxlpf_adjusted) {
19183 write_radio_reg(pi,
19184 (RADIO_2056_RX_RXLPF_RCCAL_LPC |
19185 RADIO_2056_RX0),
19186 (pi->nphy_rccal_value | 0x80));
19187
19188 pi->nphy_anarxlpf_adjusted = false;
19189 }
19190 }
19191 }
19192}
19193
19194static void
19195wlc_phy_adjust_min_noisevar_nphy(struct brcms_phy *pi, int ntones,
19196 int *tone_id_buf, u32 *noise_var_buf)
19197{
19198 int i;
19199 u32 offset;
19200 int tone_id;
19201 int tbllen =
19202 CHSPEC_IS40(pi->radio_chanspec) ?
19203 NPHY_NOISEVAR_TBLLEN40 : NPHY_NOISEVAR_TBLLEN20;
19204
19205 if (pi->nphy_noisevars_adjusted) {
19206 for (i = 0; i < pi->nphy_saved_noisevars.bufcount; i++) {
19207 tone_id = pi->nphy_saved_noisevars.tone_id[i];
19208 offset = (tone_id >= 0) ?
19209 ((tone_id *
19210 2) + 1) : (tbllen + (tone_id * 2) + 1);
19211 wlc_phy_table_write_nphy(
19212 pi, NPHY_TBL_ID_NOISEVAR, 1,
19213 offset, 32,
19214 &pi->nphy_saved_noisevars.min_noise_vars[i]);
19215 }
19216
19217 pi->nphy_saved_noisevars.bufcount = 0;
19218 pi->nphy_noisevars_adjusted = false;
19219 }
19220
19221 if ((noise_var_buf != NULL) && (tone_id_buf != NULL)) {
19222 pi->nphy_saved_noisevars.bufcount = 0;
19223
19224 for (i = 0; i < ntones; i++) {
19225 tone_id = tone_id_buf[i];
19226 offset = (tone_id >= 0) ?
19227 ((tone_id * 2) + 1) :
19228 (tbllen + (tone_id * 2) + 1);
19229 pi->nphy_saved_noisevars.tone_id[i] = tone_id;
19230 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
19231 offset, 32,
19232 &pi->nphy_saved_noisevars.
19233 min_noise_vars[i]);
19234 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
19235 offset, 32, &noise_var_buf[i]);
19236 pi->nphy_saved_noisevars.bufcount++;
19237 }
19238
19239 pi->nphy_noisevars_adjusted = true;
19240 }
19241}
19242
19243static void wlc_phy_adjust_crsminpwr_nphy(struct brcms_phy *pi, u8 minpwr)
19244{
19245 u16 regval;
19246
19247 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19248 if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) &&
19249 CHSPEC_IS40(pi->radio_chanspec)) {
19250 if (!pi->nphy_crsminpwr_adjusted) {
19251 regval = read_phy_reg(pi, 0x27d);
19252 pi->nphy_crsminpwr[0] = regval & 0xff;
19253 regval &= 0xff00;
19254 regval |= (u16) minpwr;
19255 write_phy_reg(pi, 0x27d, regval);
19256
19257 regval = read_phy_reg(pi, 0x280);
19258 pi->nphy_crsminpwr[1] = regval & 0xff;
19259 regval &= 0xff00;
19260 regval |= (u16) minpwr;
19261 write_phy_reg(pi, 0x280, regval);
19262
19263 regval = read_phy_reg(pi, 0x283);
19264 pi->nphy_crsminpwr[2] = regval & 0xff;
19265 regval &= 0xff00;
19266 regval |= (u16) minpwr;
19267 write_phy_reg(pi, 0x283, regval);
19268
19269 pi->nphy_crsminpwr_adjusted = true;
19270 }
19271 } else {
19272 if (pi->nphy_crsminpwr_adjusted) {
19273 regval = read_phy_reg(pi, 0x27d);
19274 regval &= 0xff00;
19275 regval |= pi->nphy_crsminpwr[0];
19276 write_phy_reg(pi, 0x27d, regval);
19277
19278 regval = read_phy_reg(pi, 0x280);
19279 regval &= 0xff00;
19280 regval |= pi->nphy_crsminpwr[1];
19281 write_phy_reg(pi, 0x280, regval);
19282
19283 regval = read_phy_reg(pi, 0x283);
19284 regval &= 0xff00;
19285 regval |= pi->nphy_crsminpwr[2];
19286 write_phy_reg(pi, 0x283, regval);
19287
19288 pi->nphy_crsminpwr_adjusted = false;
19289 }
19290 }
19291 }
19292}
19293
19294static void wlc_phy_spurwar_nphy(struct brcms_phy *pi)
19295{
19296 u16 cur_channel = 0;
19297 int nphy_adj_tone_id_buf[] = { 57, 58 };
19298 u32 nphy_adj_noise_var_buf[] = { 0x3ff, 0x3ff };
19299 bool isAdjustNoiseVar = false;
19300 uint numTonesAdjust = 0;
19301 u32 tempval = 0;
19302
19303 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19304 if (pi->phyhang_avoid)
19305 wlc_phy_stay_in_carriersearch_nphy(pi, true);
19306
19307 cur_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
19308
19309 if (pi->nphy_gband_spurwar_en) {
19310
19311 wlc_phy_adjust_rx_analpfbw_nphy(
19312 pi,
19313 NPHY_ANARXLPFBW_REDUCTIONFACT);
19314
19315 if (CHSPEC_IS2G(pi->radio_chanspec)) {
19316 if ((cur_channel == 11)
19317 && CHSPEC_IS40(pi->radio_chanspec))
19318 wlc_phy_adjust_min_noisevar_nphy(
19319 pi, 2,
19320 nphy_adj_tone_id_buf,
19321 nphy_adj_noise_var_buf);
19322 else
19323 wlc_phy_adjust_min_noisevar_nphy(pi, 0,
19324 NULL,
19325 NULL);
19326 }
19327
19328 wlc_phy_adjust_crsminpwr_nphy(pi,
19329 NPHY_ADJUSTED_MINCRSPOWER);
19330 }
19331
19332 if ((pi->nphy_gband_spurwar2_en)
19333 && CHSPEC_IS2G(pi->radio_chanspec)) {
19334
19335 if (CHSPEC_IS40(pi->radio_chanspec)) {
19336 switch (cur_channel) {
19337 case 3:
19338 nphy_adj_tone_id_buf[0] = 57;
19339 nphy_adj_tone_id_buf[1] = 58;
19340 nphy_adj_noise_var_buf[0] = 0x22f;
19341 nphy_adj_noise_var_buf[1] = 0x25f;
19342 isAdjustNoiseVar = true;
19343 break;
19344 case 4:
19345 nphy_adj_tone_id_buf[0] = 41;
19346 nphy_adj_tone_id_buf[1] = 42;
19347 nphy_adj_noise_var_buf[0] = 0x22f;
19348 nphy_adj_noise_var_buf[1] = 0x25f;
19349 isAdjustNoiseVar = true;
19350 break;
19351 case 5:
19352 nphy_adj_tone_id_buf[0] = 25;
19353 nphy_adj_tone_id_buf[1] = 26;
19354 nphy_adj_noise_var_buf[0] = 0x24f;
19355 nphy_adj_noise_var_buf[1] = 0x25f;
19356 isAdjustNoiseVar = true;
19357 break;
19358 case 6:
19359 nphy_adj_tone_id_buf[0] = 9;
19360 nphy_adj_tone_id_buf[1] = 10;
19361 nphy_adj_noise_var_buf[0] = 0x22f;
19362 nphy_adj_noise_var_buf[1] = 0x24f;
19363 isAdjustNoiseVar = true;
19364 break;
19365 case 7:
19366 nphy_adj_tone_id_buf[0] = 121;
19367 nphy_adj_tone_id_buf[1] = 122;
19368 nphy_adj_noise_var_buf[0] = 0x18f;
19369 nphy_adj_noise_var_buf[1] = 0x24f;
19370 isAdjustNoiseVar = true;
19371 break;
19372 case 8:
19373 nphy_adj_tone_id_buf[0] = 105;
19374 nphy_adj_tone_id_buf[1] = 106;
19375 nphy_adj_noise_var_buf[0] = 0x22f;
19376 nphy_adj_noise_var_buf[1] = 0x25f;
19377 isAdjustNoiseVar = true;
19378 break;
19379 case 9:
19380 nphy_adj_tone_id_buf[0] = 89;
19381 nphy_adj_tone_id_buf[1] = 90;
19382 nphy_adj_noise_var_buf[0] = 0x22f;
19383 nphy_adj_noise_var_buf[1] = 0x24f;
19384 isAdjustNoiseVar = true;
19385 break;
19386 case 10:
19387 nphy_adj_tone_id_buf[0] = 73;
19388 nphy_adj_tone_id_buf[1] = 74;
19389 nphy_adj_noise_var_buf[0] = 0x22f;
19390 nphy_adj_noise_var_buf[1] = 0x24f;
19391 isAdjustNoiseVar = true;
19392 break;
19393 default:
19394 isAdjustNoiseVar = false;
19395 break;
19396 }
19397 }
19398
19399 if (isAdjustNoiseVar) {
19400 numTonesAdjust = sizeof(nphy_adj_tone_id_buf) /
19401 sizeof(nphy_adj_tone_id_buf[0]);
19402
19403 wlc_phy_adjust_min_noisevar_nphy(
19404 pi,
19405 numTonesAdjust,
19406 nphy_adj_tone_id_buf,
19407 nphy_adj_noise_var_buf);
19408
19409 tempval = 0;
19410
19411 } else {
19412 wlc_phy_adjust_min_noisevar_nphy(pi, 0, NULL,
19413 NULL);
19414 }
19415 }
19416
19417 if ((pi->nphy_aband_spurwar_en) &&
19418 (CHSPEC_IS5G(pi->radio_chanspec))) {
19419 switch (cur_channel) {
19420 case 54:
19421 nphy_adj_tone_id_buf[0] = 32;
19422 nphy_adj_noise_var_buf[0] = 0x25f;
19423 break;
19424 case 38:
19425 case 102:
19426 case 118:
19427 nphy_adj_tone_id_buf[0] = 0;
19428 nphy_adj_noise_var_buf[0] = 0x0;
19429 break;
19430 case 134:
19431 nphy_adj_tone_id_buf[0] = 32;
19432 nphy_adj_noise_var_buf[0] = 0x21f;
19433 break;
19434 case 151:
19435 nphy_adj_tone_id_buf[0] = 16;
19436 nphy_adj_noise_var_buf[0] = 0x23f;
19437 break;
19438 case 153:
19439 case 161:
19440 nphy_adj_tone_id_buf[0] = 48;
19441 nphy_adj_noise_var_buf[0] = 0x23f;
19442 break;
19443 default:
19444 nphy_adj_tone_id_buf[0] = 0;
19445 nphy_adj_noise_var_buf[0] = 0x0;
19446 break;
19447 }
19448
19449 if (nphy_adj_tone_id_buf[0]
19450 && nphy_adj_noise_var_buf[0])
19451 wlc_phy_adjust_min_noisevar_nphy(
19452 pi, 1,
19453 nphy_adj_tone_id_buf,
19454 nphy_adj_noise_var_buf);
19455 else
19456 wlc_phy_adjust_min_noisevar_nphy(pi, 0, NULL,
19457 NULL);
19458 }
19459
19460 if (pi->phyhang_avoid)
19461 wlc_phy_stay_in_carriersearch_nphy(pi, false);
19462 }
19463}
19464
19465void wlc_phy_init_nphy(struct brcms_phy *pi)
19466{
19467 u16 val;
19468 u16 clip1_ths[2];
19469 struct nphy_txgains target_gain;
19470 u8 tx_pwr_ctrl_state;
19471 bool do_nphy_cal = false;
19472 uint core;
19473 uint origidx, intr_val;
19474 struct d11regs __iomem *regs;
19475 u32 d11_clk_ctl_st;
19476 bool do_rssi_cal = false;
19477
19478 core = 0;
19479
19480 if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN))
19481 pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
19482
19483 if ((ISNPHY(pi)) && (NREV_GE(pi->pubpi.phy_rev, 5)) &&
19484 ((pi->sh->chippkg == BCM4717_PKG_ID) ||
19485 (pi->sh->chippkg == BCM4718_PKG_ID))) {
19486 if ((pi->sh->boardflags & BFL_EXTLNA) &&
19487 (CHSPEC_IS2G(pi->radio_chanspec)))
19488 ai_corereg(pi->sh->sih, SI_CC_IDX,
19489 offsetof(struct chipcregs, chipcontrol),
19490 0x40, 0x40);
19491 }
19492
19493 if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
19494 CHSPEC_IS40(pi->radio_chanspec)) {
19495
19496 regs = (struct d11regs __iomem *)
19497 ai_switch_core(pi->sh->sih,
19498 D11_CORE_ID, &origidx,
19499 &intr_val);
19500 d11_clk_ctl_st = R_REG(&regs->clk_ctl_st);
19501 AND_REG(&regs->clk_ctl_st,
19502 ~(CCS_FORCEHT | CCS_HTAREQ));
19503
19504 W_REG(&regs->clk_ctl_st, d11_clk_ctl_st);
19505
19506 ai_restore_core(pi->sh->sih, origidx, intr_val);
19507 }
19508
19509 pi->use_int_tx_iqlo_cal_nphy =
19510 (PHY_IPA(pi) ||
19511 (NREV_GE(pi->pubpi.phy_rev, 7) ||
19512 (NREV_GE(pi->pubpi.phy_rev, 5)
19513 && pi->sh->boardflags2 & BFL2_INTERNDET_TXIQCAL)));
19514
19515 pi->internal_tx_iqlo_cal_tapoff_intpa_nphy = false;
19516
19517 pi->nphy_deaf_count = 0;
19518
19519 wlc_phy_tbl_init_nphy(pi);
19520
19521 pi->nphy_crsminpwr_adjusted = false;
19522 pi->nphy_noisevars_adjusted = false;
19523
19524 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19525 write_phy_reg(pi, 0xe7, 0);
19526 write_phy_reg(pi, 0xec, 0);
19527 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
19528 write_phy_reg(pi, 0x342, 0);
19529 write_phy_reg(pi, 0x343, 0);
19530 write_phy_reg(pi, 0x346, 0);
19531 write_phy_reg(pi, 0x347, 0);
19532 }
19533 write_phy_reg(pi, 0xe5, 0);
19534 write_phy_reg(pi, 0xe6, 0);
19535 } else {
19536 write_phy_reg(pi, 0xec, 0);
19537 }
19538
19539 write_phy_reg(pi, 0x91, 0);
19540 write_phy_reg(pi, 0x92, 0);
19541 if (NREV_LT(pi->pubpi.phy_rev, 6)) {
19542 write_phy_reg(pi, 0x93, 0);
19543 write_phy_reg(pi, 0x94, 0);
19544 }
19545
19546 and_phy_reg(pi, 0xa1, ~3);
19547
19548 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19549 write_phy_reg(pi, 0x8f, 0);
19550 write_phy_reg(pi, 0xa5, 0);
19551 } else {
19552 write_phy_reg(pi, 0xa5, 0);
19553 }
19554
19555 if (NREV_IS(pi->pubpi.phy_rev, 2))
19556 mod_phy_reg(pi, 0xdc, 0x00ff, 0x3b);
19557 else if (NREV_LT(pi->pubpi.phy_rev, 2))
19558 mod_phy_reg(pi, 0xdc, 0x00ff, 0x40);
19559
19560 write_phy_reg(pi, 0x203, 32);
19561 write_phy_reg(pi, 0x201, 32);
19562
19563 if (pi->sh->boardflags2 & BFL2_SKWRKFEM_BRD)
19564 write_phy_reg(pi, 0x20d, 160);
19565 else
19566 write_phy_reg(pi, 0x20d, 184);
19567
19568 write_phy_reg(pi, 0x13a, 200);
19569
19570 write_phy_reg(pi, 0x70, 80);
19571
19572 write_phy_reg(pi, 0x1ff, 48);
19573
19574 if (NREV_LT(pi->pubpi.phy_rev, 8))
19575 wlc_phy_update_mimoconfig_nphy(pi, pi->n_preamble_override);
19576
19577 wlc_phy_stf_chain_upd_nphy(pi);
19578
19579 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
19580 write_phy_reg(pi, 0x180, 0xaa8);
19581 write_phy_reg(pi, 0x181, 0x9a4);
19582 }
19583
19584 if (PHY_IPA(pi)) {
19585 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
19586
19587 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
19588 0x29b, (0x1 << 0), (1) << 0);
19589
19590 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x298 :
19591 0x29c, (0x1ff << 7),
19592 (pi->nphy_papd_epsilon_offset[core]) << 7);
19593
19594 }
19595
19596 wlc_phy_ipa_set_tx_digi_filts_nphy(pi);
19597 } else if (NREV_GE(pi->pubpi.phy_rev, 5)) {
19598 wlc_phy_extpa_set_tx_digi_filts_nphy(pi);
19599 }
19600
19601 wlc_phy_workarounds_nphy(pi);
19602
19603 wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
19604
19605 val = read_phy_reg(pi, 0x01);
19606 write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA);
19607 write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA));
19608 wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
19609
19610 wlapi_bmac_macphyclk_set(pi->sh->physhim, ON);
19611
19612 wlc_phy_pa_override_nphy(pi, OFF);
19613 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX);
19614 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
19615 wlc_phy_pa_override_nphy(pi, ON);
19616
19617 wlc_phy_classifier_nphy(pi, 0, 0);
19618 wlc_phy_clip_det_nphy(pi, 0, clip1_ths);
19619
19620 if (CHSPEC_IS2G(pi->radio_chanspec))
19621 wlc_phy_bphy_init_nphy(pi);
19622
19623 tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
19624 wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
19625
19626 wlc_phy_txpwr_fixpower_nphy(pi);
19627
19628 wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
19629
19630 wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
19631
19632 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19633 u32 *tx_pwrctrl_tbl = NULL;
19634 u16 idx;
19635 s16 pga_gn = 0;
19636 s16 pad_gn = 0;
19637 s32 rfpwr_offset;
19638
19639 if (PHY_IPA(pi)) {
19640 tx_pwrctrl_tbl = wlc_phy_get_ipa_gaintbl_nphy(pi);
19641 } else {
19642 if (CHSPEC_IS5G(pi->radio_chanspec)) {
19643 if (NREV_IS(pi->pubpi.phy_rev, 3))
19644 tx_pwrctrl_tbl =
19645 nphy_tpc_5GHz_txgain_rev3;
19646 else if (NREV_IS(pi->pubpi.phy_rev, 4))
19647 tx_pwrctrl_tbl =
19648 (pi->srom_fem5g.extpagain ==
19649 3) ?
19650 nphy_tpc_5GHz_txgain_HiPwrEPA :
19651 nphy_tpc_5GHz_txgain_rev4;
19652 else
19653 tx_pwrctrl_tbl =
19654 nphy_tpc_5GHz_txgain_rev5;
19655 } else {
19656 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
19657 if (pi->pubpi.radiorev == 5)
19658 tx_pwrctrl_tbl =
19659 nphy_tpc_txgain_epa_2057rev5;
19660 else if (pi->pubpi.radiorev == 3)
19661 tx_pwrctrl_tbl =
19662 nphy_tpc_txgain_epa_2057rev3;
19663 } else {
19664 if (NREV_GE(pi->pubpi.phy_rev, 5) &&
19665 (pi->srom_fem2g.extpagain == 3))
19666 tx_pwrctrl_tbl =
19667 nphy_tpc_txgain_HiPwrEPA;
19668 else
19669 tx_pwrctrl_tbl =
19670 nphy_tpc_txgain_rev3;
19671 }
19672 }
19673 }
19674
19675 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 128,
19676 192, 32, tx_pwrctrl_tbl);
19677 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128,
19678 192, 32, tx_pwrctrl_tbl);
19679
19680 pi->nphy_gmval = (u16) ((*tx_pwrctrl_tbl >> 16) & 0x7000);
19681
19682 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
19683
19684 for (idx = 0; idx < 128; idx++) {
19685 pga_gn = (tx_pwrctrl_tbl[idx] >> 24) & 0xf;
19686 pad_gn = (tx_pwrctrl_tbl[idx] >> 19) & 0x1f;
19687 rfpwr_offset = get_rf_pwr_offset(pi, pga_gn,
19688 pad_gn);
19689 wlc_phy_table_write_nphy(
19690 pi,
19691 NPHY_TBL_ID_CORE1TXPWRCTL,
19692 1, 576 + idx, 32,
19693 &rfpwr_offset);
19694 wlc_phy_table_write_nphy(
19695 pi,
19696 NPHY_TBL_ID_CORE2TXPWRCTL,
19697 1, 576 + idx, 32,
19698 &rfpwr_offset);
19699 }
19700 } else {
19701
19702 for (idx = 0; idx < 128; idx++) {
19703 pga_gn = (tx_pwrctrl_tbl[idx] >> 24) & 0xf;
19704 if (CHSPEC_IS2G(pi->radio_chanspec))
19705 rfpwr_offset = (s16)
19706 nphy_papd_pga_gain_delta_ipa_2g
19707 [pga_gn];
19708 else
19709 rfpwr_offset = (s16)
19710 nphy_papd_pga_gain_delta_ipa_5g
19711 [pga_gn];
19712
19713 wlc_phy_table_write_nphy(
19714 pi,
19715 NPHY_TBL_ID_CORE1TXPWRCTL,
19716 1, 576 + idx, 32,
19717 &rfpwr_offset);
19718 wlc_phy_table_write_nphy(
19719 pi,
19720 NPHY_TBL_ID_CORE2TXPWRCTL,
19721 1, 576 + idx, 32,
19722 &rfpwr_offset);
19723 }
19724
19725 }
19726 } else {
19727
19728 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 128,
19729 192, 32, nphy_tpc_txgain);
19730 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128,
19731 192, 32, nphy_tpc_txgain);
19732 }
19733
19734 if (pi->sh->phyrxchain != 0x3)
19735 wlc_phy_rxcore_setstate_nphy((struct brcms_phy_pub *) pi,
19736 pi->sh->phyrxchain);
19737
19738 if (PHY_PERICAL_MPHASE_PENDING(pi))
19739 wlc_phy_cal_perical_mphase_restart(pi);
19740
19741 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19742 do_rssi_cal = (CHSPEC_IS2G(pi->radio_chanspec)) ?
19743 (pi->nphy_rssical_chanspec_2G == 0) :
19744 (pi->nphy_rssical_chanspec_5G == 0);
19745
19746 if (do_rssi_cal)
19747 wlc_phy_rssi_cal_nphy(pi);
19748 else
19749 wlc_phy_restore_rssical_nphy(pi);
19750 } else {
19751 wlc_phy_rssi_cal_nphy(pi);
19752 }
19753
19754 if (!SCAN_RM_IN_PROGRESS(pi))
19755 do_nphy_cal = (CHSPEC_IS2G(pi->radio_chanspec)) ?
19756 (pi->nphy_iqcal_chanspec_2G == 0) :
19757 (pi->nphy_iqcal_chanspec_5G == 0);
19758
19759 if (!pi->do_initcal)
19760 do_nphy_cal = false;
19761
19762 if (do_nphy_cal) {
19763
19764 target_gain = wlc_phy_get_tx_gain_nphy(pi);
19765
19766 if (pi->antsel_type == ANTSEL_2x3)
19767 wlc_phy_antsel_init((struct brcms_phy_pub *) pi,
19768 true);
19769
19770 if (pi->nphy_perical != PHY_PERICAL_MPHASE) {
19771 wlc_phy_rssi_cal_nphy(pi);
19772
19773 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19774 pi->nphy_cal_orig_pwr_idx[0] =
19775 pi->nphy_txpwrindex[PHY_CORE_0]
19776 .
19777 index_internal;
19778 pi->nphy_cal_orig_pwr_idx[1] =
19779 pi->nphy_txpwrindex[PHY_CORE_1]
19780 .
19781 index_internal;
19782
19783 wlc_phy_precal_txgain_nphy(pi);
19784 target_gain =
19785 wlc_phy_get_tx_gain_nphy(pi);
19786 }
19787
19788 if (wlc_phy_cal_txiqlo_nphy
19789 (pi, target_gain, true,
19790 false) == 0) {
19791 if (wlc_phy_cal_rxiq_nphy
19792 (pi, target_gain, 2,
19793 false) == 0)
19794 wlc_phy_savecal_nphy(pi);
19795
19796 }
19797 } else if (pi->mphase_cal_phase_id ==
19798 MPHASE_CAL_STATE_IDLE) {
19799 wlc_phy_cal_perical((struct brcms_phy_pub *) pi,
19800 PHY_PERICAL_PHYINIT);
19801 }
19802 } else {
19803 wlc_phy_restorecal_nphy(pi);
19804 }
19805
19806 wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
19807
19808 wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
19809
19810 wlc_phy_nphy_tkip_rifs_war(pi, pi->sh->_rifs_phy);
19811
19812 if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LE(pi->pubpi.phy_rev, 6))
19813
19814 write_phy_reg(pi, 0x70, 50);
19815
19816 wlc_phy_txlpfbw_nphy(pi);
19817
19818 wlc_phy_spurwar_nphy(pi);
19819
19820}
19821
19822static void wlc_phy_resetcca_nphy(struct brcms_phy *pi)
19823{
19824 u16 val;
19825
19826 wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
19827
19828 val = read_phy_reg(pi, 0x01);
19829 write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA);
19830 udelay(1);
19831 write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA));
19832
19833 wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
19834
19835 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
19836}
19837
19838void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en)
19839{
19840 u16 rfctrlintc_override_val;
19841
19842 if (!en) {
19843
19844 pi->rfctrlIntc1_save = read_phy_reg(pi, 0x91);
19845 pi->rfctrlIntc2_save = read_phy_reg(pi, 0x92);
19846
19847 if (NREV_GE(pi->pubpi.phy_rev, 7))
19848 rfctrlintc_override_val = 0x1480;
19849 else if (NREV_GE(pi->pubpi.phy_rev, 3))
19850 rfctrlintc_override_val =
19851 CHSPEC_IS5G(pi->radio_chanspec) ? 0x600 : 0x480;
19852 else
19853 rfctrlintc_override_val =
19854 CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 : 0x120;
19855
19856 write_phy_reg(pi, 0x91, rfctrlintc_override_val);
19857 write_phy_reg(pi, 0x92, rfctrlintc_override_val);
19858 } else {
19859 write_phy_reg(pi, 0x91, pi->rfctrlIntc1_save);
19860 write_phy_reg(pi, 0x92, pi->rfctrlIntc2_save);
19861 }
19862
19863}
19864
19865void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi)
19866{
19867
19868 u16 txrx_chain =
19869 (NPHY_RfseqCoreActv_TxRxChain0 | NPHY_RfseqCoreActv_TxRxChain1);
19870 bool CoreActv_override = false;
19871
19872 if (pi->nphy_txrx_chain == BRCMS_N_TXRX_CHAIN0) {
19873 txrx_chain = NPHY_RfseqCoreActv_TxRxChain0;
19874 CoreActv_override = true;
19875
19876 if (NREV_LE(pi->pubpi.phy_rev, 2))
19877 and_phy_reg(pi, 0xa0, ~0x20);
19878 } else if (pi->nphy_txrx_chain == BRCMS_N_TXRX_CHAIN1) {
19879 txrx_chain = NPHY_RfseqCoreActv_TxRxChain1;
19880 CoreActv_override = true;
19881
19882 if (NREV_LE(pi->pubpi.phy_rev, 2))
19883 or_phy_reg(pi, 0xa0, 0x20);
19884 }
19885
19886 mod_phy_reg(pi, 0xa2, ((0xf << 0) | (0xf << 4)), txrx_chain);
19887
19888 if (CoreActv_override) {
19889 pi->nphy_perical = PHY_PERICAL_DISABLE;
19890 or_phy_reg(pi, 0xa1, NPHY_RfseqMode_CoreActv_override);
19891 } else {
19892 pi->nphy_perical = PHY_PERICAL_MPHASE;
19893 and_phy_reg(pi, 0xa1, ~NPHY_RfseqMode_CoreActv_override);
19894 }
19895}
19896
19897void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih, u8 rxcore_bitmask)
19898{
19899 u16 regval;
19900 u16 tbl_buf[16];
19901 uint i;
19902 struct brcms_phy *pi = (struct brcms_phy *) pih;
19903 u16 tbl_opcode;
19904 bool suspend;
19905
19906 pi->sh->phyrxchain = rxcore_bitmask;
19907
19908 if (!pi->sh->clk)
19909 return;
19910
19911 suspend = (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
19912 if (!suspend)
19913 wlapi_suspend_mac_and_wait(pi->sh->physhim);
19914
19915 if (pi->phyhang_avoid)
19916 wlc_phy_stay_in_carriersearch_nphy(pi, true);
19917
19918 regval = read_phy_reg(pi, 0xa2);
19919 regval &= ~(0xf << 4);
19920 regval |= ((u16) (rxcore_bitmask & 0x3)) << 4;
19921 write_phy_reg(pi, 0xa2, regval);
19922
19923 if ((rxcore_bitmask & 0x3) != 0x3) {
19924
19925 write_phy_reg(pi, 0x20e, 1);
19926
19927 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19928 if (pi->rx2tx_biasentry == -1) {
19929 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ,
19930 ARRAY_SIZE(tbl_buf), 80,
19931 16, tbl_buf);
19932
19933 for (i = 0; i < ARRAY_SIZE(tbl_buf); i++) {
19934 if (tbl_buf[i] ==
19935 NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS) {
19936 pi->rx2tx_biasentry = (u8) i;
19937 tbl_opcode =
19938 NPHY_REV3_RFSEQ_CMD_NOP;
19939 wlc_phy_table_write_nphy(
19940 pi,
19941 NPHY_TBL_ID_RFSEQ,
19942 1, i,
19943 16,
19944 &tbl_opcode);
19945 break;
19946 } else if (tbl_buf[i] ==
19947 NPHY_REV3_RFSEQ_CMD_END)
19948 break;
19949 }
19950 }
19951 }
19952 } else {
19953
19954 write_phy_reg(pi, 0x20e, 30);
19955
19956 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
19957 if (pi->rx2tx_biasentry != -1) {
19958 tbl_opcode = NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS;
19959 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
19960 1, pi->rx2tx_biasentry,
19961 16, &tbl_opcode);
19962 pi->rx2tx_biasentry = -1;
19963 }
19964 }
19965 }
19966
19967 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
19968
19969 if (pi->phyhang_avoid)
19970 wlc_phy_stay_in_carriersearch_nphy(pi, false);
19971
19972 if (!suspend)
19973 wlapi_enable_mac(pi->sh->physhim);
19974}
19975
19976u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih)
19977{
19978 u16 regval, rxen_bits;
19979 struct brcms_phy *pi = (struct brcms_phy *) pih;
19980
19981 regval = read_phy_reg(pi, 0xa2);
19982 rxen_bits = (regval >> 4) & 0xf;
19983
19984 return (u8) rxen_bits;
19985}
19986
19987bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pi)
19988{
19989 return PHY_IPA(pi);
19990}
19991
19992void wlc_phy_cal_init_nphy(struct brcms_phy *pi)
19993{
19994}
19995
19996static void wlc_phy_radio_preinit_205x(struct brcms_phy *pi)
19997{
19998
19999 and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
20000 and_phy_reg(pi, 0x78, RFCC_OE_POR_FORCE);
20001
20002 or_phy_reg(pi, 0x78, ~RFCC_OE_POR_FORCE);
20003 or_phy_reg(pi, 0x78, RFCC_CHIP0_PU);
20004
20005}
20006
20007static void wlc_phy_radio_init_2057(struct brcms_phy *pi)
20008{
20009 struct radio_20xx_regs *regs_2057_ptr = NULL;
20010
20011 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
20012 regs_2057_ptr = regs_2057_rev4;
20013 } else if (NREV_IS(pi->pubpi.phy_rev, 8)
20014 || NREV_IS(pi->pubpi.phy_rev, 9)) {
20015 switch (pi->pubpi.radiorev) {
20016 case 5:
20017
20018 if (pi->pubpi.radiover == 0x0)
20019 regs_2057_ptr = regs_2057_rev5;
20020 else if (pi->pubpi.radiover == 0x1)
20021 regs_2057_ptr = regs_2057_rev5v1;
20022 else
20023 break;
20024
20025 case 7:
20026
20027 regs_2057_ptr = regs_2057_rev7;
20028 break;
20029
20030 case 8:
20031
20032 regs_2057_ptr = regs_2057_rev8;
20033 break;
20034
20035 default:
20036 break;
20037 }
20038 }
20039
20040 wlc_phy_init_radio_regs_allbands(pi, regs_2057_ptr);
20041}
20042
20043static u16 wlc_phy_radio205x_rcal(struct brcms_phy *pi)
20044{
20045 u16 rcal_reg = 0;
20046 int i;
20047
20048 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
20049
20050 if (pi->pubpi.radiorev == 5) {
20051
20052 and_phy_reg(pi, 0x342, ~(0x1 << 1));
20053
20054 udelay(10);
20055
20056 mod_radio_reg(pi, RADIO_2057_IQTEST_SEL_PU, 0x1, 0x1);
20057 mod_radio_reg(pi, RADIO_2057v7_IQTEST_SEL_PU2, 0x2,
20058 0x1);
20059 }
20060 mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x1, 0x1);
20061
20062 udelay(10);
20063
20064 mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x3, 0x3);
20065
20066 for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
20067 rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS);
20068 if (rcal_reg & 0x1)
20069 break;
20070
20071 udelay(100);
20072 }
20073
20074 if (WARN(i == MAX_205x_RCAL_WAITLOOPS,
20075 "HW error: radio calib2"))
20076 return 0;
20077
20078 mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x2, 0x0);
20079
20080 rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS) & 0x3e;
20081
20082 mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x1, 0x0);
20083 if (pi->pubpi.radiorev == 5) {
20084
20085 mod_radio_reg(pi, RADIO_2057_IQTEST_SEL_PU, 0x1, 0x0);
20086 mod_radio_reg(pi, RADIO_2057v7_IQTEST_SEL_PU2, 0x2,
20087 0x0);
20088 }
20089
20090 if ((pi->pubpi.radiorev <= 4) || (pi->pubpi.radiorev == 6)) {
20091
20092 mod_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG, 0x3c,
20093 rcal_reg);
20094 mod_radio_reg(pi, RADIO_2057_BANDGAP_RCAL_TRIM, 0xf0,
20095 rcal_reg << 2);
20096 }
20097
20098 } else if (NREV_IS(pi->pubpi.phy_rev, 3)) {
20099 u16 savereg;
20100
20101 savereg =
20102 read_radio_reg(
20103 pi,
20104 RADIO_2056_SYN_PLL_MAST2 |
20105 RADIO_2056_SYN);
20106 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN,
20107 savereg | 0x7);
20108 udelay(10);
20109
20110 write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
20111 0x1);
20112 udelay(10);
20113
20114 write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
20115 0x9);
20116
20117 for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
20118 rcal_reg = read_radio_reg(
20119 pi,
20120 RADIO_2056_SYN_RCAL_CODE_OUT |
20121 RADIO_2056_SYN);
20122 if (rcal_reg & 0x80)
20123 break;
20124
20125 udelay(100);
20126 }
20127
20128 if (WARN(i == MAX_205x_RCAL_WAITLOOPS,
20129 "HW error: radio calib3"))
20130 return 0;
20131
20132 write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
20133 0x1);
20134
20135 rcal_reg =
20136 read_radio_reg(pi,
20137 RADIO_2056_SYN_RCAL_CODE_OUT |
20138 RADIO_2056_SYN);
20139
20140 write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
20141 0x0);
20142
20143 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN,
20144 savereg);
20145
20146 return rcal_reg & 0x1f;
20147 }
20148 return rcal_reg & 0x3e;
20149}
20150
20151static u16 wlc_phy_radio2057_rccal(struct brcms_phy *pi)
20152{
20153 u16 rccal_valid;
20154 int i;
20155 bool chip43226_6362A0;
20156
20157 chip43226_6362A0 = ((pi->pubpi.radiorev == 3)
20158 || (pi->pubpi.radiorev == 4)
20159 || (pi->pubpi.radiorev == 6));
20160
20161 rccal_valid = 0;
20162 if (chip43226_6362A0) {
20163 write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x61);
20164 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xc0);
20165 } else {
20166 write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x61);
20167
20168 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xe9);
20169 }
20170 write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
20171 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
20172
20173 for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
20174 rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
20175 if (rccal_valid & 0x2)
20176 break;
20177
20178 udelay(500);
20179 }
20180
20181 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
20182
20183 rccal_valid = 0;
20184 if (chip43226_6362A0) {
20185 write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x69);
20186 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xb0);
20187 } else {
20188 write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x69);
20189
20190 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xd5);
20191 }
20192 write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
20193 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
20194
20195 for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
20196 rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
20197 if (rccal_valid & 0x2)
20198 break;
20199
20200 udelay(500);
20201 }
20202
20203 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
20204
20205 rccal_valid = 0;
20206 if (chip43226_6362A0) {
20207 write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x73);
20208
20209 write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x28);
20210 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xb0);
20211 } else {
20212 write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x73);
20213 write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
20214 write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0x99);
20215 }
20216 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
20217
20218 for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
20219 rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
20220 if (rccal_valid & 0x2)
20221 break;
20222
20223 udelay(500);
20224 }
20225
20226 if (WARN(!(rccal_valid & 0x2), "HW error: radio calib4"))
20227 return 0;
20228
20229 write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
20230
20231 return rccal_valid;
20232}
20233
20234static void wlc_phy_radio_postinit_2057(struct brcms_phy *pi)
20235{
20236
20237 mod_radio_reg(pi, RADIO_2057_XTALPUOVR_PINCTRL, 0x1, 0x1);
20238
20239 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x78);
20240 mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x80);
20241 mdelay(2);
20242 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x0);
20243 mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x0);
20244
20245 if (pi->phy_init_por) {
20246 wlc_phy_radio205x_rcal(pi);
20247 wlc_phy_radio2057_rccal(pi);
20248 }
20249
20250 mod_radio_reg(pi, RADIO_2057_RFPLL_MASTER, 0x8, 0x0);
20251}
20252
20253static void wlc_phy_radio_init_2056(struct brcms_phy *pi)
20254{
20255 const struct radio_regs *regs_SYN_2056_ptr = NULL;
20256 const struct radio_regs *regs_TX_2056_ptr = NULL;
20257 const struct radio_regs *regs_RX_2056_ptr = NULL;
20258
20259 if (NREV_IS(pi->pubpi.phy_rev, 3)) {
20260 regs_SYN_2056_ptr = regs_SYN_2056;
20261 regs_TX_2056_ptr = regs_TX_2056;
20262 regs_RX_2056_ptr = regs_RX_2056;
20263 } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
20264 regs_SYN_2056_ptr = regs_SYN_2056_A1;
20265 regs_TX_2056_ptr = regs_TX_2056_A1;
20266 regs_RX_2056_ptr = regs_RX_2056_A1;
20267 } else {
20268 switch (pi->pubpi.radiorev) {
20269 case 5:
20270 regs_SYN_2056_ptr = regs_SYN_2056_rev5;
20271 regs_TX_2056_ptr = regs_TX_2056_rev5;
20272 regs_RX_2056_ptr = regs_RX_2056_rev5;
20273 break;
20274
20275 case 6:
20276 regs_SYN_2056_ptr = regs_SYN_2056_rev6;
20277 regs_TX_2056_ptr = regs_TX_2056_rev6;
20278 regs_RX_2056_ptr = regs_RX_2056_rev6;
20279 break;
20280
20281 case 7:
20282 case 9:
20283 regs_SYN_2056_ptr = regs_SYN_2056_rev7;
20284 regs_TX_2056_ptr = regs_TX_2056_rev7;
20285 regs_RX_2056_ptr = regs_RX_2056_rev7;
20286 break;
20287
20288 case 8:
20289 regs_SYN_2056_ptr = regs_SYN_2056_rev8;
20290 regs_TX_2056_ptr = regs_TX_2056_rev8;
20291 regs_RX_2056_ptr = regs_RX_2056_rev8;
20292 break;
20293
20294 case 11:
20295 regs_SYN_2056_ptr = regs_SYN_2056_rev11;
20296 regs_TX_2056_ptr = regs_TX_2056_rev11;
20297 regs_RX_2056_ptr = regs_RX_2056_rev11;
20298 break;
20299
20300 default:
20301 break;
20302 }
20303 }
20304
20305 wlc_phy_init_radio_regs(pi, regs_SYN_2056_ptr, (u16) RADIO_2056_SYN);
20306
20307 wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX0);
20308
20309 wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX1);
20310
20311 wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX0);
20312
20313 wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX1);
20314}
20315
20316static void wlc_phy_radio_postinit_2056(struct brcms_phy *pi)
20317{
20318 mod_radio_reg(pi, RADIO_2056_SYN_COM_CTRL, 0xb, 0xb);
20319
20320 mod_radio_reg(pi, RADIO_2056_SYN_COM_PU, 0x2, 0x2);
20321 mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x2);
20322 udelay(1000);
20323 mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x0);
20324
20325 if ((pi->sh->boardflags2 & BFL2_LEGACY)
20326 || (pi->sh->boardflags2 & BFL2_XTALBUFOUTEN))
20327 mod_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2, 0xf4, 0x0);
20328 else
20329 mod_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2, 0xfc, 0x0);
20330
20331 mod_radio_reg(pi, RADIO_2056_SYN_RCCAL_CTRL0, 0x1, 0x0);
20332
20333 if (pi->phy_init_por)
20334 wlc_phy_radio205x_rcal(pi);
20335}
20336
20337static void wlc_phy_radio_preinit_2055(struct brcms_phy *pi)
20338{
20339
20340 and_phy_reg(pi, 0x78, ~RFCC_POR_FORCE);
20341 or_phy_reg(pi, 0x78, RFCC_CHIP0_PU | RFCC_OE_POR_FORCE);
20342
20343 or_phy_reg(pi, 0x78, RFCC_POR_FORCE);
20344}
20345
20346static void wlc_phy_radio_init_2055(struct brcms_phy *pi)
20347{
20348 wlc_phy_init_radio_regs(pi, regs_2055, RADIO_DEFAULT_CORE);
20349}
20350
20351static void wlc_phy_radio_postinit_2055(struct brcms_phy *pi)
20352{
20353
20354 and_radio_reg(pi, RADIO_2055_MASTER_CNTRL1,
20355 ~(RADIO_2055_JTAGCTRL_MASK | RADIO_2055_JTAGSYNC_MASK));
20356
20357 if (((pi->sh->sromrev >= 4)
20358 && !(pi->sh->boardflags2 & BFL2_RXBB_INT_REG_DIS))
20359 || ((pi->sh->sromrev < 4))) {
20360 and_radio_reg(pi, RADIO_2055_CORE1_RXBB_REGULATOR, 0x7F);
20361 and_radio_reg(pi, RADIO_2055_CORE2_RXBB_REGULATOR, 0x7F);
20362 }
20363
20364 mod_radio_reg(pi, RADIO_2055_RRCCAL_N_OPT_SEL, 0x3F, 0x2C);
20365 write_radio_reg(pi, RADIO_2055_CAL_MISC, 0x3C);
20366
20367 and_radio_reg(pi, RADIO_2055_CAL_MISC,
20368 ~(RADIO_2055_RRCAL_START | RADIO_2055_RRCAL_RST_N));
20369
20370 or_radio_reg(pi, RADIO_2055_CAL_LPO_CNTRL, RADIO_2055_CAL_LPO_ENABLE);
20371
20372 or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_RST_N);
20373
20374 udelay(1000);
20375
20376 or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_START);
20377
20378 SPINWAIT(((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
20379 RADIO_2055_RCAL_DONE) != RADIO_2055_RCAL_DONE), 2000);
20380
20381 if (WARN((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
20382 RADIO_2055_RCAL_DONE) != RADIO_2055_RCAL_DONE,
20383 "HW error: radio calibration1\n"))
20384 return;
20385
20386 and_radio_reg(pi, RADIO_2055_CAL_LPO_CNTRL,
20387 ~(RADIO_2055_CAL_LPO_ENABLE));
20388
20389 wlc_phy_chanspec_set((struct brcms_phy_pub *) pi, pi->radio_chanspec);
20390
20391 write_radio_reg(pi, RADIO_2055_CORE1_RXBB_LPF, 9);
20392 write_radio_reg(pi, RADIO_2055_CORE2_RXBB_LPF, 9);
20393
20394 write_radio_reg(pi, RADIO_2055_CORE1_RXBB_MIDAC_HIPAS, 0x83);
20395 write_radio_reg(pi, RADIO_2055_CORE2_RXBB_MIDAC_HIPAS, 0x83);
20396
20397 mod_radio_reg(pi, RADIO_2055_CORE1_LNA_GAINBST,
20398 RADIO_2055_GAINBST_VAL_MASK, RADIO_2055_GAINBST_CODE);
20399 mod_radio_reg(pi, RADIO_2055_CORE2_LNA_GAINBST,
20400 RADIO_2055_GAINBST_VAL_MASK, RADIO_2055_GAINBST_CODE);
20401 if (pi->nphy_gain_boost) {
20402 and_radio_reg(pi, RADIO_2055_CORE1_RXRF_SPC1,
20403 ~(RADIO_2055_GAINBST_DISABLE));
20404 and_radio_reg(pi, RADIO_2055_CORE2_RXRF_SPC1,
20405 ~(RADIO_2055_GAINBST_DISABLE));
20406 } else {
20407 or_radio_reg(pi, RADIO_2055_CORE1_RXRF_SPC1,
20408 RADIO_2055_GAINBST_DISABLE);
20409 or_radio_reg(pi, RADIO_2055_CORE2_RXRF_SPC1,
20410 RADIO_2055_GAINBST_DISABLE);
20411 }
20412
20413 udelay(2);
20414}
20415
20416void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on)
20417{
20418 if (on) {
20419 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
20420 if (!pi->radio_is_on) {
20421 wlc_phy_radio_preinit_205x(pi);
20422 wlc_phy_radio_init_2057(pi);
20423 wlc_phy_radio_postinit_2057(pi);
20424 }
20425
20426 wlc_phy_chanspec_set((struct brcms_phy_pub *) pi,
20427 pi->radio_chanspec);
20428 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
20429 wlc_phy_radio_preinit_205x(pi);
20430 wlc_phy_radio_init_2056(pi);
20431 wlc_phy_radio_postinit_2056(pi);
20432
20433 wlc_phy_chanspec_set((struct brcms_phy_pub *) pi,
20434 pi->radio_chanspec);
20435 } else {
20436 wlc_phy_radio_preinit_2055(pi);
20437 wlc_phy_radio_init_2055(pi);
20438 wlc_phy_radio_postinit_2055(pi);
20439 }
20440
20441 pi->radio_is_on = true;
20442
20443 } else {
20444
20445 if (NREV_GE(pi->pubpi.phy_rev, 3)
20446 && NREV_LT(pi->pubpi.phy_rev, 7)) {
20447 and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
20448 mod_radio_reg(pi, RADIO_2056_SYN_COM_PU, 0x2, 0x0);
20449
20450 write_radio_reg(pi,
20451 RADIO_2056_TX_PADA_BOOST_TUNE |
20452 RADIO_2056_TX0, 0);
20453 write_radio_reg(pi,
20454 RADIO_2056_TX_PADG_BOOST_TUNE |
20455 RADIO_2056_TX0, 0);
20456 write_radio_reg(pi,
20457 RADIO_2056_TX_PGAA_BOOST_TUNE |
20458 RADIO_2056_TX0, 0);
20459 write_radio_reg(pi,
20460 RADIO_2056_TX_PGAG_BOOST_TUNE |
20461 RADIO_2056_TX0, 0);
20462 mod_radio_reg(pi,
20463 RADIO_2056_TX_MIXA_BOOST_TUNE |
20464 RADIO_2056_TX0, 0xf0, 0);
20465 write_radio_reg(pi,
20466 RADIO_2056_TX_MIXG_BOOST_TUNE |
20467 RADIO_2056_TX0, 0);
20468
20469 write_radio_reg(pi,
20470 RADIO_2056_TX_PADA_BOOST_TUNE |
20471 RADIO_2056_TX1, 0);
20472 write_radio_reg(pi,
20473 RADIO_2056_TX_PADG_BOOST_TUNE |
20474 RADIO_2056_TX1, 0);
20475 write_radio_reg(pi,
20476 RADIO_2056_TX_PGAA_BOOST_TUNE |
20477 RADIO_2056_TX1, 0);
20478 write_radio_reg(pi,
20479 RADIO_2056_TX_PGAG_BOOST_TUNE |
20480 RADIO_2056_TX1, 0);
20481 mod_radio_reg(pi,
20482 RADIO_2056_TX_MIXA_BOOST_TUNE |
20483 RADIO_2056_TX1, 0xf0, 0);
20484 write_radio_reg(pi,
20485 RADIO_2056_TX_MIXG_BOOST_TUNE |
20486 RADIO_2056_TX1, 0);
20487
20488 pi->radio_is_on = false;
20489 }
20490
20491 if (NREV_GE(pi->pubpi.phy_rev, 8)) {
20492 and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
20493 pi->radio_is_on = false;
20494 }
20495
20496 }
20497}
20498
20499static bool
20500wlc_phy_chan2freq_nphy(struct brcms_phy *pi, uint channel, int *f,
20501 const struct chan_info_nphy_radio2057 **t0,
20502 const struct chan_info_nphy_radio205x **t1,
20503 const struct chan_info_nphy_radio2057_rev5 **t2,
20504 const struct chan_info_nphy_2055 **t3)
20505{
20506 uint i;
20507 const struct chan_info_nphy_radio2057 *chan_info_tbl_p_0 = NULL;
20508 const struct chan_info_nphy_radio205x *chan_info_tbl_p_1 = NULL;
20509 const struct chan_info_nphy_radio2057_rev5 *chan_info_tbl_p_2 = NULL;
20510 u32 tbl_len = 0;
20511
20512 int freq = 0;
20513
20514 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
20515
20516 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
20517
20518 chan_info_tbl_p_0 = chan_info_nphyrev7_2057_rev4;
20519 tbl_len = ARRAY_SIZE(chan_info_nphyrev7_2057_rev4);
20520
20521 } else if (NREV_IS(pi->pubpi.phy_rev, 8)
20522 || NREV_IS(pi->pubpi.phy_rev, 9)) {
20523 switch (pi->pubpi.radiorev) {
20524
20525 case 5:
20526
20527 if (pi->pubpi.radiover == 0x0) {
20528
20529 chan_info_tbl_p_2 =
20530 chan_info_nphyrev8_2057_rev5;
20531 tbl_len = ARRAY_SIZE(
20532 chan_info_nphyrev8_2057_rev5);
20533
20534 } else if (pi->pubpi.radiover == 0x1) {
20535
20536 chan_info_tbl_p_2 =
20537 chan_info_nphyrev9_2057_rev5v1;
20538 tbl_len = ARRAY_SIZE(
20539 chan_info_nphyrev9_2057_rev5v1);
20540
20541 }
20542 break;
20543
20544 case 7:
20545 chan_info_tbl_p_0 =
20546 chan_info_nphyrev8_2057_rev7;
20547 tbl_len = ARRAY_SIZE(
20548 chan_info_nphyrev8_2057_rev7);
20549 break;
20550
20551 case 8:
20552 chan_info_tbl_p_0 =
20553 chan_info_nphyrev8_2057_rev8;
20554 tbl_len = ARRAY_SIZE(
20555 chan_info_nphyrev8_2057_rev8);
20556 break;
20557
20558 default:
20559 break;
20560 }
20561 } else if (NREV_IS(pi->pubpi.phy_rev, 16)) {
20562
20563 chan_info_tbl_p_0 = chan_info_nphyrev8_2057_rev8;
20564 tbl_len = ARRAY_SIZE(chan_info_nphyrev8_2057_rev8);
20565 } else {
20566 goto fail;
20567 }
20568
20569 for (i = 0; i < tbl_len; i++) {
20570 if (pi->pubpi.radiorev == 5) {
20571
20572 if (chan_info_tbl_p_2[i].chan == channel)
20573 break;
20574 } else {
20575
20576 if (chan_info_tbl_p_0[i].chan == channel)
20577 break;
20578 }
20579 }
20580
20581 if (i >= tbl_len)
20582 goto fail;
20583
20584 if (pi->pubpi.radiorev == 5) {
20585 *t2 = &chan_info_tbl_p_2[i];
20586 freq = chan_info_tbl_p_2[i].freq;
20587 } else {
20588 *t0 = &chan_info_tbl_p_0[i];
20589 freq = chan_info_tbl_p_0[i].freq;
20590 }
20591
20592 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
20593 if (NREV_IS(pi->pubpi.phy_rev, 3)) {
20594 chan_info_tbl_p_1 = chan_info_nphyrev3_2056;
20595 tbl_len = ARRAY_SIZE(chan_info_nphyrev3_2056);
20596 } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
20597 chan_info_tbl_p_1 = chan_info_nphyrev4_2056_A1;
20598 tbl_len = ARRAY_SIZE(chan_info_nphyrev4_2056_A1);
20599 } else if (NREV_IS(pi->pubpi.phy_rev, 5)
20600 || NREV_IS(pi->pubpi.phy_rev, 6)) {
20601 switch (pi->pubpi.radiorev) {
20602 case 5:
20603 chan_info_tbl_p_1 = chan_info_nphyrev5_2056v5;
20604 tbl_len = ARRAY_SIZE(chan_info_nphyrev5_2056v5);
20605 break;
20606 case 6:
20607 chan_info_tbl_p_1 = chan_info_nphyrev6_2056v6;
20608 tbl_len = ARRAY_SIZE(chan_info_nphyrev6_2056v6);
20609 break;
20610 case 7:
20611 case 9:
20612 chan_info_tbl_p_1 = chan_info_nphyrev5n6_2056v7;
20613 tbl_len =
20614 ARRAY_SIZE(chan_info_nphyrev5n6_2056v7);
20615 break;
20616 case 8:
20617 chan_info_tbl_p_1 = chan_info_nphyrev6_2056v8;
20618 tbl_len = ARRAY_SIZE(chan_info_nphyrev6_2056v8);
20619 break;
20620 case 11:
20621 chan_info_tbl_p_1 = chan_info_nphyrev6_2056v11;
20622 tbl_len = ARRAY_SIZE(
20623 chan_info_nphyrev6_2056v11);
20624 break;
20625 default:
20626 break;
20627 }
20628 }
20629
20630 for (i = 0; i < tbl_len; i++) {
20631 if (chan_info_tbl_p_1[i].chan == channel)
20632 break;
20633 }
20634
20635 if (i >= tbl_len)
20636 goto fail;
20637
20638 *t1 = &chan_info_tbl_p_1[i];
20639 freq = chan_info_tbl_p_1[i].freq;
20640
20641 } else {
20642 for (i = 0; i < ARRAY_SIZE(chan_info_nphy_2055); i++)
20643 if (chan_info_nphy_2055[i].chan == channel)
20644 break;
20645
20646 if (i >= ARRAY_SIZE(chan_info_nphy_2055))
20647 goto fail;
20648
20649 *t3 = &chan_info_nphy_2055[i];
20650 freq = chan_info_nphy_2055[i].freq;
20651 }
20652
20653 *f = freq;
20654 return true;
20655
20656fail:
20657 *f = WL_CHAN_FREQ_RANGE_2G;
20658 return false;
20659}
20660
20661u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint channel)
20662{
20663 int freq;
20664 const struct chan_info_nphy_radio2057 *t0 = NULL;
20665 const struct chan_info_nphy_radio205x *t1 = NULL;
20666 const struct chan_info_nphy_radio2057_rev5 *t2 = NULL;
20667 const struct chan_info_nphy_2055 *t3 = NULL;
20668
20669 if (channel == 0)
20670 channel = CHSPEC_CHANNEL(pi->radio_chanspec);
20671
20672 wlc_phy_chan2freq_nphy(pi, channel, &freq, &t0, &t1, &t2, &t3);
20673
20674 if (CHSPEC_IS2G(pi->radio_chanspec))
20675 return WL_CHAN_FREQ_RANGE_2G;
20676
20677 if ((freq >= BASE_LOW_5G_CHAN) && (freq < BASE_MID_5G_CHAN))
20678 return WL_CHAN_FREQ_RANGE_5GL;
20679 else if ((freq >= BASE_MID_5G_CHAN) && (freq < BASE_HIGH_5G_CHAN))
20680 return WL_CHAN_FREQ_RANGE_5GM;
20681 else
20682 return WL_CHAN_FREQ_RANGE_5GH;
20683}
20684
20685static void
20686wlc_phy_chanspec_radio2055_setup(struct brcms_phy *pi,
20687 const struct chan_info_nphy_2055 *ci)
20688{
20689
20690 write_radio_reg(pi, RADIO_2055_PLL_REF, ci->RF_pll_ref);
20691 write_radio_reg(pi, RADIO_2055_RF_PLL_MOD0, ci->RF_rf_pll_mod0);
20692 write_radio_reg(pi, RADIO_2055_RF_PLL_MOD1, ci->RF_rf_pll_mod1);
20693 write_radio_reg(pi, RADIO_2055_VCO_CAP_TAIL, ci->RF_vco_cap_tail);
20694
20695 BRCMS_PHY_WAR_PR51571(pi);
20696
20697 write_radio_reg(pi, RADIO_2055_VCO_CAL1, ci->RF_vco_cal1);
20698 write_radio_reg(pi, RADIO_2055_VCO_CAL2, ci->RF_vco_cal2);
20699 write_radio_reg(pi, RADIO_2055_PLL_LF_C1, ci->RF_pll_lf_c1);
20700 write_radio_reg(pi, RADIO_2055_PLL_LF_R1, ci->RF_pll_lf_r1);
20701
20702 BRCMS_PHY_WAR_PR51571(pi);
20703
20704 write_radio_reg(pi, RADIO_2055_PLL_LF_C2, ci->RF_pll_lf_c2);
20705 write_radio_reg(pi, RADIO_2055_LGBUF_CEN_BUF, ci->RF_lgbuf_cen_buf);
20706 write_radio_reg(pi, RADIO_2055_LGEN_TUNE1, ci->RF_lgen_tune1);
20707 write_radio_reg(pi, RADIO_2055_LGEN_TUNE2, ci->RF_lgen_tune2);
20708
20709 BRCMS_PHY_WAR_PR51571(pi);
20710
20711 write_radio_reg(pi, RADIO_2055_CORE1_LGBUF_A_TUNE,
20712 ci->RF_core1_lgbuf_a_tune);
20713 write_radio_reg(pi, RADIO_2055_CORE1_LGBUF_G_TUNE,
20714 ci->RF_core1_lgbuf_g_tune);
20715 write_radio_reg(pi, RADIO_2055_CORE1_RXRF_REG1, ci->RF_core1_rxrf_reg1);
20716 write_radio_reg(pi, RADIO_2055_CORE1_TX_PGA_PAD_TN,
20717 ci->RF_core1_tx_pga_pad_tn);
20718
20719 BRCMS_PHY_WAR_PR51571(pi);
20720
20721 write_radio_reg(pi, RADIO_2055_CORE1_TX_MX_BGTRIM,
20722 ci->RF_core1_tx_mx_bgtrim);
20723 write_radio_reg(pi, RADIO_2055_CORE2_LGBUF_A_TUNE,
20724 ci->RF_core2_lgbuf_a_tune);
20725 write_radio_reg(pi, RADIO_2055_CORE2_LGBUF_G_TUNE,
20726 ci->RF_core2_lgbuf_g_tune);
20727 write_radio_reg(pi, RADIO_2055_CORE2_RXRF_REG1, ci->RF_core2_rxrf_reg1);
20728
20729 BRCMS_PHY_WAR_PR51571(pi);
20730
20731 write_radio_reg(pi, RADIO_2055_CORE2_TX_PGA_PAD_TN,
20732 ci->RF_core2_tx_pga_pad_tn);
20733 write_radio_reg(pi, RADIO_2055_CORE2_TX_MX_BGTRIM,
20734 ci->RF_core2_tx_mx_bgtrim);
20735
20736 udelay(50);
20737
20738 write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x05);
20739 write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x45);
20740
20741 BRCMS_PHY_WAR_PR51571(pi);
20742
20743 write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x65);
20744
20745 udelay(300);
20746}
20747
20748static void
20749wlc_phy_chanspec_radio2056_setup(struct brcms_phy *pi,
20750 const struct chan_info_nphy_radio205x *ci)
20751{
20752 const struct radio_regs *regs_SYN_2056_ptr = NULL;
20753
20754 write_radio_reg(pi,
20755 RADIO_2056_SYN_PLL_VCOCAL1 | RADIO_2056_SYN,
20756 ci->RF_SYN_pll_vcocal1);
20757 write_radio_reg(pi, RADIO_2056_SYN_PLL_VCOCAL2 | RADIO_2056_SYN,
20758 ci->RF_SYN_pll_vcocal2);
20759 write_radio_reg(pi, RADIO_2056_SYN_PLL_REFDIV | RADIO_2056_SYN,
20760 ci->RF_SYN_pll_refdiv);
20761 write_radio_reg(pi, RADIO_2056_SYN_PLL_MMD2 | RADIO_2056_SYN,
20762 ci->RF_SYN_pll_mmd2);
20763 write_radio_reg(pi, RADIO_2056_SYN_PLL_MMD1 | RADIO_2056_SYN,
20764 ci->RF_SYN_pll_mmd1);
20765 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 | RADIO_2056_SYN,
20766 ci->RF_SYN_pll_loopfilter1);
20767 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 | RADIO_2056_SYN,
20768 ci->RF_SYN_pll_loopfilter2);
20769 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER3 | RADIO_2056_SYN,
20770 ci->RF_SYN_pll_loopfilter3);
20771 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER4 | RADIO_2056_SYN,
20772 ci->RF_SYN_pll_loopfilter4);
20773 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER5 | RADIO_2056_SYN,
20774 ci->RF_SYN_pll_loopfilter5);
20775 write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR27 | RADIO_2056_SYN,
20776 ci->RF_SYN_reserved_addr27);
20777 write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR28 | RADIO_2056_SYN,
20778 ci->RF_SYN_reserved_addr28);
20779 write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR29 | RADIO_2056_SYN,
20780 ci->RF_SYN_reserved_addr29);
20781 write_radio_reg(pi, RADIO_2056_SYN_LOGEN_VCOBUF1 | RADIO_2056_SYN,
20782 ci->RF_SYN_logen_VCOBUF1);
20783 write_radio_reg(pi, RADIO_2056_SYN_LOGEN_MIXER2 | RADIO_2056_SYN,
20784 ci->RF_SYN_logen_MIXER2);
20785 write_radio_reg(pi, RADIO_2056_SYN_LOGEN_BUF3 | RADIO_2056_SYN,
20786 ci->RF_SYN_logen_BUF3);
20787 write_radio_reg(pi, RADIO_2056_SYN_LOGEN_BUF4 | RADIO_2056_SYN,
20788 ci->RF_SYN_logen_BUF4);
20789
20790 write_radio_reg(pi,
20791 RADIO_2056_RX_LNAA_TUNE | RADIO_2056_RX0,
20792 ci->RF_RX0_lnaa_tune);
20793 write_radio_reg(pi, RADIO_2056_RX_LNAG_TUNE | RADIO_2056_RX0,
20794 ci->RF_RX0_lnag_tune);
20795 write_radio_reg(pi, RADIO_2056_TX_INTPAA_BOOST_TUNE | RADIO_2056_TX0,
20796 ci->RF_TX0_intpaa_boost_tune);
20797 write_radio_reg(pi, RADIO_2056_TX_INTPAG_BOOST_TUNE | RADIO_2056_TX0,
20798 ci->RF_TX0_intpag_boost_tune);
20799 write_radio_reg(pi, RADIO_2056_TX_PADA_BOOST_TUNE | RADIO_2056_TX0,
20800 ci->RF_TX0_pada_boost_tune);
20801 write_radio_reg(pi, RADIO_2056_TX_PADG_BOOST_TUNE | RADIO_2056_TX0,
20802 ci->RF_TX0_padg_boost_tune);
20803 write_radio_reg(pi, RADIO_2056_TX_PGAA_BOOST_TUNE | RADIO_2056_TX0,
20804 ci->RF_TX0_pgaa_boost_tune);
20805 write_radio_reg(pi, RADIO_2056_TX_PGAG_BOOST_TUNE | RADIO_2056_TX0,
20806 ci->RF_TX0_pgag_boost_tune);
20807 write_radio_reg(pi, RADIO_2056_TX_MIXA_BOOST_TUNE | RADIO_2056_TX0,
20808 ci->RF_TX0_mixa_boost_tune);
20809 write_radio_reg(pi, RADIO_2056_TX_MIXG_BOOST_TUNE | RADIO_2056_TX0,
20810 ci->RF_TX0_mixg_boost_tune);
20811
20812 write_radio_reg(pi,
20813 RADIO_2056_RX_LNAA_TUNE | RADIO_2056_RX1,
20814 ci->RF_RX1_lnaa_tune);
20815 write_radio_reg(pi, RADIO_2056_RX_LNAG_TUNE | RADIO_2056_RX1,
20816 ci->RF_RX1_lnag_tune);
20817 write_radio_reg(pi, RADIO_2056_TX_INTPAA_BOOST_TUNE | RADIO_2056_TX1,
20818 ci->RF_TX1_intpaa_boost_tune);
20819 write_radio_reg(pi, RADIO_2056_TX_INTPAG_BOOST_TUNE | RADIO_2056_TX1,
20820 ci->RF_TX1_intpag_boost_tune);
20821 write_radio_reg(pi, RADIO_2056_TX_PADA_BOOST_TUNE | RADIO_2056_TX1,
20822 ci->RF_TX1_pada_boost_tune);
20823 write_radio_reg(pi, RADIO_2056_TX_PADG_BOOST_TUNE | RADIO_2056_TX1,
20824 ci->RF_TX1_padg_boost_tune);
20825 write_radio_reg(pi, RADIO_2056_TX_PGAA_BOOST_TUNE | RADIO_2056_TX1,
20826 ci->RF_TX1_pgaa_boost_tune);
20827 write_radio_reg(pi, RADIO_2056_TX_PGAG_BOOST_TUNE | RADIO_2056_TX1,
20828 ci->RF_TX1_pgag_boost_tune);
20829 write_radio_reg(pi, RADIO_2056_TX_MIXA_BOOST_TUNE | RADIO_2056_TX1,
20830 ci->RF_TX1_mixa_boost_tune);
20831 write_radio_reg(pi, RADIO_2056_TX_MIXG_BOOST_TUNE | RADIO_2056_TX1,
20832 ci->RF_TX1_mixg_boost_tune);
20833
20834 if (NREV_IS(pi->pubpi.phy_rev, 3))
20835 regs_SYN_2056_ptr = regs_SYN_2056;
20836 else if (NREV_IS(pi->pubpi.phy_rev, 4))
20837 regs_SYN_2056_ptr = regs_SYN_2056_A1;
20838 else {
20839 switch (pi->pubpi.radiorev) {
20840 case 5:
20841 regs_SYN_2056_ptr = regs_SYN_2056_rev5;
20842 break;
20843 case 6:
20844 regs_SYN_2056_ptr = regs_SYN_2056_rev6;
20845 break;
20846 case 7:
20847 case 9:
20848 regs_SYN_2056_ptr = regs_SYN_2056_rev7;
20849 break;
20850 case 8:
20851 regs_SYN_2056_ptr = regs_SYN_2056_rev8;
20852 break;
20853 case 11:
20854 regs_SYN_2056_ptr = regs_SYN_2056_rev11;
20855 break;
20856 }
20857 }
20858 if (CHSPEC_IS2G(pi->radio_chanspec))
20859 write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
20860 RADIO_2056_SYN,
20861 (u16) regs_SYN_2056_ptr[0x49 - 2].init_g);
20862 else
20863 write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
20864 RADIO_2056_SYN,
20865 (u16) regs_SYN_2056_ptr[0x49 - 2].init_a);
20866
20867 if (pi->sh->boardflags2 & BFL2_GPLL_WAR) {
20868 if (CHSPEC_IS2G(pi->radio_chanspec)) {
20869 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 |
20870 RADIO_2056_SYN, 0x1f);
20871 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
20872 RADIO_2056_SYN, 0x1f);
20873
20874 write_radio_reg(pi,
20875 RADIO_2056_SYN_PLL_LOOPFILTER4 |
20876 RADIO_2056_SYN, 0xb);
20877 write_radio_reg(pi,
20878 RADIO_2056_SYN_PLL_CP2 |
20879 RADIO_2056_SYN, 0x14);
20880 }
20881 }
20882
20883 if ((pi->sh->boardflags2 & BFL2_GPLL_WAR2) &&
20884 (CHSPEC_IS2G(pi->radio_chanspec))) {
20885 write_radio_reg(pi,
20886 RADIO_2056_SYN_PLL_LOOPFILTER1 | RADIO_2056_SYN,
20887 0x1f);
20888 write_radio_reg(pi,
20889 RADIO_2056_SYN_PLL_LOOPFILTER2 | RADIO_2056_SYN,
20890 0x1f);
20891 write_radio_reg(pi,
20892 RADIO_2056_SYN_PLL_LOOPFILTER4 | RADIO_2056_SYN,
20893 0xb);
20894 write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 | RADIO_2056_SYN,
20895 0x20);
20896 }
20897
20898 if (pi->sh->boardflags2 & BFL2_APLL_WAR) {
20899 if (CHSPEC_IS5G(pi->radio_chanspec)) {
20900 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 |
20901 RADIO_2056_SYN, 0x1f);
20902 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
20903 RADIO_2056_SYN, 0x1f);
20904 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER4 |
20905 RADIO_2056_SYN, 0x5);
20906 write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
20907 RADIO_2056_SYN, 0xc);
20908 }
20909 }
20910
20911 if (PHY_IPA(pi) && CHSPEC_IS2G(pi->radio_chanspec)) {
20912 u16 pag_boost_tune;
20913 u16 padg_boost_tune;
20914 u16 pgag_boost_tune;
20915 u16 mixg_boost_tune;
20916 u16 bias, cascbias;
20917 uint core;
20918
20919 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
20920
20921 if (NREV_GE(pi->pubpi.phy_rev, 5)) {
20922
20923 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20924 PADG_IDAC, 0xcc);
20925
20926 bias = 0x25;
20927 cascbias = 0x20;
20928
20929 if ((pi->sh->chip ==
20930 BCM43224_CHIP_ID)
20931 || (pi->sh->chip ==
20932 BCM43225_CHIP_ID)) {
20933 if (pi->sh->chippkg ==
20934 BCM43224_FAB_SMIC) {
20935 bias = 0x2a;
20936 cascbias = 0x38;
20937 }
20938 }
20939
20940 pag_boost_tune = 0x4;
20941 pgag_boost_tune = 0x03;
20942 padg_boost_tune = 0x77;
20943 mixg_boost_tune = 0x65;
20944
20945 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20946 INTPAG_IMAIN_STAT, bias);
20947 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20948 INTPAG_IAUX_STAT, bias);
20949 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20950 INTPAG_CASCBIAS, cascbias);
20951
20952 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20953 INTPAG_BOOST_TUNE,
20954 pag_boost_tune);
20955 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20956 PGAG_BOOST_TUNE,
20957 pgag_boost_tune);
20958 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20959 PADG_BOOST_TUNE,
20960 padg_boost_tune);
20961 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20962 MIXG_BOOST_TUNE,
20963 mixg_boost_tune);
20964 } else {
20965
20966 bias = (pi->bw == WL_CHANSPEC_BW_40) ?
20967 0x40 : 0x20;
20968
20969 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20970 INTPAG_IMAIN_STAT, bias);
20971 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20972 INTPAG_IAUX_STAT, bias);
20973 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
20974 INTPAG_CASCBIAS, 0x30);
20975 }
20976 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, PA_SPARE1,
20977 0xee);
20978 }
20979 }
20980
20981 if (PHY_IPA(pi) && NREV_IS(pi->pubpi.phy_rev, 6)
20982 && CHSPEC_IS5G(pi->radio_chanspec)) {
20983 u16 paa_boost_tune;
20984 u16 pada_boost_tune;
20985 u16 pgaa_boost_tune;
20986 u16 mixa_boost_tune;
20987 u16 freq, pabias, cascbias;
20988 uint core;
20989
20990 freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec));
20991
20992 if (freq < 5150) {
20993
20994 paa_boost_tune = 0xa;
20995 pada_boost_tune = 0x77;
20996 pgaa_boost_tune = 0xf;
20997 mixa_boost_tune = 0xf;
20998 } else if (freq < 5340) {
20999
21000 paa_boost_tune = 0x8;
21001 pada_boost_tune = 0x77;
21002 pgaa_boost_tune = 0xfb;
21003 mixa_boost_tune = 0xf;
21004 } else if (freq < 5650) {
21005
21006 paa_boost_tune = 0x0;
21007 pada_boost_tune = 0x77;
21008 pgaa_boost_tune = 0xb;
21009 mixa_boost_tune = 0xf;
21010 } else {
21011
21012 paa_boost_tune = 0x0;
21013 pada_boost_tune = 0x77;
21014 if (freq != 5825)
21015 pgaa_boost_tune = -(int)(freq - 18) / 36 + 168;
21016 else
21017 pgaa_boost_tune = 6;
21018
21019 mixa_boost_tune = 0xf;
21020 }
21021
21022 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
21023 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21024 INTPAA_BOOST_TUNE, paa_boost_tune);
21025 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21026 PADA_BOOST_TUNE, pada_boost_tune);
21027 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21028 PGAA_BOOST_TUNE, pgaa_boost_tune);
21029 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21030 MIXA_BOOST_TUNE, mixa_boost_tune);
21031
21032 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21033 TXSPARE1, 0x30);
21034 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21035 PA_SPARE2, 0xee);
21036
21037 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21038 PADA_CASCBIAS, 0x3);
21039
21040 cascbias = 0x30;
21041
21042 if ((pi->sh->chip == BCM43224_CHIP_ID) ||
21043 (pi->sh->chip == BCM43225_CHIP_ID)) {
21044 if (pi->sh->chippkg == BCM43224_FAB_SMIC)
21045 cascbias = 0x35;
21046 }
21047
21048 pabias = (pi->phy_pabias == 0) ? 0x30 : pi->phy_pabias;
21049
21050 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21051 INTPAA_IAUX_STAT, pabias);
21052 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21053 INTPAA_IMAIN_STAT, pabias);
21054 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
21055 INTPAA_CASCBIAS, cascbias);
21056 }
21057 }
21058
21059 udelay(50);
21060
21061 wlc_phy_radio205x_vcocal_nphy(pi);
21062}
21063
21064void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi)
21065{
21066 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21067 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_EN, 0x01, 0x0);
21068 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x04, 0x0);
21069 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x04,
21070 (1 << 2));
21071 mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_EN, 0x01, 0x01);
21072 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
21073 write_radio_reg(pi, RADIO_2056_SYN_PLL_VCOCAL12, 0x0);
21074 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x38);
21075 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x18);
21076 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x38);
21077 write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x39);
21078 }
21079
21080 udelay(300);
21081}
21082
21083static void
21084wlc_phy_chanspec_radio2057_setup(
21085 struct brcms_phy *pi,
21086 const struct chan_info_nphy_radio2057 *ci,
21087 const struct chan_info_nphy_radio2057_rev5 *
21088 ci2)
21089{
21090 int coreNum;
21091 u16 txmix2g_tune_boost_pu = 0;
21092 u16 pad2g_tune_pus = 0;
21093
21094 if (pi->pubpi.radiorev == 5) {
21095
21096 write_radio_reg(pi,
21097 RADIO_2057_VCOCAL_COUNTVAL0,
21098 ci2->RF_vcocal_countval0);
21099 write_radio_reg(pi, RADIO_2057_VCOCAL_COUNTVAL1,
21100 ci2->RF_vcocal_countval1);
21101 write_radio_reg(pi, RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE,
21102 ci2->RF_rfpll_refmaster_sparextalsize);
21103 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
21104 ci2->RF_rfpll_loopfilter_r1);
21105 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
21106 ci2->RF_rfpll_loopfilter_c2);
21107 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
21108 ci2->RF_rfpll_loopfilter_c1);
21109 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC,
21110 ci2->RF_cp_kpd_idac);
21111 write_radio_reg(pi, RADIO_2057_RFPLL_MMD0, ci2->RF_rfpll_mmd0);
21112 write_radio_reg(pi, RADIO_2057_RFPLL_MMD1, ci2->RF_rfpll_mmd1);
21113 write_radio_reg(pi,
21114 RADIO_2057_VCOBUF_TUNE, ci2->RF_vcobuf_tune);
21115 write_radio_reg(pi,
21116 RADIO_2057_LOGEN_MX2G_TUNE,
21117 ci2->RF_logen_mx2g_tune);
21118 write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF2G_TUNE,
21119 ci2->RF_logen_indbuf2g_tune);
21120
21121 write_radio_reg(pi,
21122 RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
21123 ci2->RF_txmix2g_tune_boost_pu_core0);
21124 write_radio_reg(pi,
21125 RADIO_2057_PAD2G_TUNE_PUS_CORE0,
21126 ci2->RF_pad2g_tune_pus_core0);
21127 write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE0,
21128 ci2->RF_lna2g_tune_core0);
21129
21130 write_radio_reg(pi,
21131 RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
21132 ci2->RF_txmix2g_tune_boost_pu_core1);
21133 write_radio_reg(pi,
21134 RADIO_2057_PAD2G_TUNE_PUS_CORE1,
21135 ci2->RF_pad2g_tune_pus_core1);
21136 write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE1,
21137 ci2->RF_lna2g_tune_core1);
21138
21139 } else {
21140
21141 write_radio_reg(pi,
21142 RADIO_2057_VCOCAL_COUNTVAL0,
21143 ci->RF_vcocal_countval0);
21144 write_radio_reg(pi, RADIO_2057_VCOCAL_COUNTVAL1,
21145 ci->RF_vcocal_countval1);
21146 write_radio_reg(pi, RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE,
21147 ci->RF_rfpll_refmaster_sparextalsize);
21148 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
21149 ci->RF_rfpll_loopfilter_r1);
21150 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
21151 ci->RF_rfpll_loopfilter_c2);
21152 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
21153 ci->RF_rfpll_loopfilter_c1);
21154 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, ci->RF_cp_kpd_idac);
21155 write_radio_reg(pi, RADIO_2057_RFPLL_MMD0, ci->RF_rfpll_mmd0);
21156 write_radio_reg(pi, RADIO_2057_RFPLL_MMD1, ci->RF_rfpll_mmd1);
21157 write_radio_reg(pi, RADIO_2057_VCOBUF_TUNE, ci->RF_vcobuf_tune);
21158 write_radio_reg(pi,
21159 RADIO_2057_LOGEN_MX2G_TUNE,
21160 ci->RF_logen_mx2g_tune);
21161 write_radio_reg(pi, RADIO_2057_LOGEN_MX5G_TUNE,
21162 ci->RF_logen_mx5g_tune);
21163 write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF2G_TUNE,
21164 ci->RF_logen_indbuf2g_tune);
21165 write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF5G_TUNE,
21166 ci->RF_logen_indbuf5g_tune);
21167
21168 write_radio_reg(pi,
21169 RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
21170 ci->RF_txmix2g_tune_boost_pu_core0);
21171 write_radio_reg(pi,
21172 RADIO_2057_PAD2G_TUNE_PUS_CORE0,
21173 ci->RF_pad2g_tune_pus_core0);
21174 write_radio_reg(pi, RADIO_2057_PGA_BOOST_TUNE_CORE0,
21175 ci->RF_pga_boost_tune_core0);
21176 write_radio_reg(pi, RADIO_2057_TXMIX5G_BOOST_TUNE_CORE0,
21177 ci->RF_txmix5g_boost_tune_core0);
21178 write_radio_reg(pi, RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE0,
21179 ci->RF_pad5g_tune_misc_pus_core0);
21180 write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE0,
21181 ci->RF_lna2g_tune_core0);
21182 write_radio_reg(pi, RADIO_2057_LNA5G_TUNE_CORE0,
21183 ci->RF_lna5g_tune_core0);
21184
21185 write_radio_reg(pi,
21186 RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
21187 ci->RF_txmix2g_tune_boost_pu_core1);
21188 write_radio_reg(pi,
21189 RADIO_2057_PAD2G_TUNE_PUS_CORE1,
21190 ci->RF_pad2g_tune_pus_core1);
21191 write_radio_reg(pi, RADIO_2057_PGA_BOOST_TUNE_CORE1,
21192 ci->RF_pga_boost_tune_core1);
21193 write_radio_reg(pi, RADIO_2057_TXMIX5G_BOOST_TUNE_CORE1,
21194 ci->RF_txmix5g_boost_tune_core1);
21195 write_radio_reg(pi, RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE1,
21196 ci->RF_pad5g_tune_misc_pus_core1);
21197 write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE1,
21198 ci->RF_lna2g_tune_core1);
21199 write_radio_reg(pi, RADIO_2057_LNA5G_TUNE_CORE1,
21200 ci->RF_lna5g_tune_core1);
21201 }
21202
21203 if ((pi->pubpi.radiorev <= 4) || (pi->pubpi.radiorev == 6)) {
21204
21205 if (CHSPEC_IS2G(pi->radio_chanspec)) {
21206 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
21207 0x3f);
21208 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
21209 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
21210 0x8);
21211 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
21212 0x8);
21213 } else {
21214 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
21215 0x1f);
21216 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
21217 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
21218 0x8);
21219 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
21220 0x8);
21221 }
21222 } else if ((pi->pubpi.radiorev == 5) || (pi->pubpi.radiorev == 7) ||
21223 (pi->pubpi.radiorev == 8)) {
21224
21225 if (CHSPEC_IS2G(pi->radio_chanspec)) {
21226 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
21227 0x1b);
21228 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x30);
21229 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
21230 0xa);
21231 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
21232 0xa);
21233 } else {
21234 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
21235 0x1f);
21236 write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
21237 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
21238 0x8);
21239 write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
21240 0x8);
21241 }
21242
21243 }
21244
21245 if (CHSPEC_IS2G(pi->radio_chanspec)) {
21246 if (PHY_IPA(pi)) {
21247 if (pi->pubpi.radiorev == 3)
21248 txmix2g_tune_boost_pu = 0x6b;
21249
21250 if (pi->pubpi.radiorev == 5)
21251 pad2g_tune_pus = 0x73;
21252
21253 } else {
21254 if (pi->pubpi.radiorev != 5) {
21255 pad2g_tune_pus = 0x3;
21256
21257 txmix2g_tune_boost_pu = 0x61;
21258 }
21259 }
21260
21261 for (coreNum = 0; coreNum <= 1; coreNum++) {
21262
21263 if (txmix2g_tune_boost_pu != 0)
21264 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
21265 TXMIX2G_TUNE_BOOST_PU,
21266 txmix2g_tune_boost_pu);
21267
21268 if (pad2g_tune_pus != 0)
21269 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
21270 PAD2G_TUNE_PUS,
21271 pad2g_tune_pus);
21272 }
21273 }
21274
21275 udelay(50);
21276
21277 wlc_phy_radio205x_vcocal_nphy(pi);
21278}
21279
21280static void
21281wlc_phy_chanspec_nphy_setup(struct brcms_phy *pi, u16 chanspec,
21282 const struct nphy_sfo_cfg *ci)
21283{
21284 u16 val;
21285
21286 val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
21287 if (CHSPEC_IS5G(chanspec) && !val) {
21288
21289 val = R_REG(&pi->regs->psm_phy_hdr_param);
21290 W_REG(&pi->regs->psm_phy_hdr_param,
21291 (val | MAC_PHY_FORCE_CLK));
21292
21293 or_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
21294 (BBCFG_RESETCCA | BBCFG_RESETRX));
21295
21296 W_REG(&pi->regs->psm_phy_hdr_param, val);
21297
21298 or_phy_reg(pi, 0x09, NPHY_BandControl_currentBand);
21299 } else if (!CHSPEC_IS5G(chanspec) && val) {
21300
21301 and_phy_reg(pi, 0x09, ~NPHY_BandControl_currentBand);
21302
21303 val = R_REG(&pi->regs->psm_phy_hdr_param);
21304 W_REG(&pi->regs->psm_phy_hdr_param,
21305 (val | MAC_PHY_FORCE_CLK));
21306
21307 and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
21308 (u16) (~(BBCFG_RESETCCA | BBCFG_RESETRX)));
21309
21310 W_REG(&pi->regs->psm_phy_hdr_param, val);
21311 }
21312
21313 write_phy_reg(pi, 0x1ce, ci->PHY_BW1a);
21314 write_phy_reg(pi, 0x1cf, ci->PHY_BW2);
21315 write_phy_reg(pi, 0x1d0, ci->PHY_BW3);
21316
21317 write_phy_reg(pi, 0x1d1, ci->PHY_BW4);
21318 write_phy_reg(pi, 0x1d2, ci->PHY_BW5);
21319 write_phy_reg(pi, 0x1d3, ci->PHY_BW6);
21320
21321 if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
21322 wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_ofdm_en, 0);
21323
21324 or_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_TEST, 0x800);
21325 } else {
21326 wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_ofdm_en,
21327 NPHY_ClassifierCtrl_ofdm_en);
21328
21329 if (CHSPEC_IS2G(chanspec))
21330 and_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_TEST, ~0x840);
21331 }
21332
21333 if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF)
21334 wlc_phy_txpwr_fixpower_nphy(pi);
21335
21336 if (NREV_LT(pi->pubpi.phy_rev, 3))
21337 wlc_phy_adjust_lnagaintbl_nphy(pi);
21338
21339 wlc_phy_txlpfbw_nphy(pi);
21340
21341 if (NREV_GE(pi->pubpi.phy_rev, 3)
21342 && (pi->phy_spuravoid != SPURAVOID_DISABLE)) {
21343 u8 spuravoid = 0;
21344
21345 val = CHSPEC_CHANNEL(chanspec);
21346 if (!CHSPEC_IS40(pi->radio_chanspec)) {
21347 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21348 if ((val == 13) || (val == 14) || (val == 153))
21349 spuravoid = 1;
21350 } else if (((val >= 5) && (val <= 8)) || (val == 13)
21351 || (val == 14)) {
21352 spuravoid = 1;
21353 }
21354 } else if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21355 if (val == 54)
21356 spuravoid = 1;
21357 } else {
21358 if (pi->nphy_aband_spurwar_en &&
21359 ((val == 38) || (val == 102)
21360 || (val == 118)))
21361 spuravoid = 1;
21362 }
21363
21364 if (pi->phy_spuravoid == SPURAVOID_FORCEON)
21365 spuravoid = 1;
21366
21367 wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
21368 si_pmu_spuravoid(pi->sh->sih, spuravoid);
21369 wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
21370
21371 if ((pi->sh->chip == BCM43224_CHIP_ID) ||
21372 (pi->sh->chip == BCM43225_CHIP_ID)) {
21373
21374 if (spuravoid == 1) {
21375
21376 W_REG(&pi->regs->tsf_clk_frac_l,
21377 0x5341);
21378 W_REG(&pi->regs->tsf_clk_frac_h,
21379 0x8);
21380 } else {
21381
21382 W_REG(&pi->regs->tsf_clk_frac_l,
21383 0x8889);
21384 W_REG(&pi->regs->tsf_clk_frac_h,
21385 0x8);
21386 }
21387 }
21388
21389 wlapi_bmac_core_phypll_reset(pi->sh->physhim);
21390
21391 mod_phy_reg(pi, 0x01, (0x1 << 15),
21392 ((spuravoid > 0) ? (0x1 << 15) : 0));
21393
21394 wlc_phy_resetcca_nphy(pi);
21395
21396 pi->phy_isspuravoid = (spuravoid > 0);
21397 }
21398
21399 if (NREV_LT(pi->pubpi.phy_rev, 7))
21400 write_phy_reg(pi, 0x17e, 0x3830);
21401
21402 wlc_phy_spurwar_nphy(pi);
21403}
21404
21405void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi, u16 chanspec)
21406{
21407 int freq;
21408 const struct chan_info_nphy_radio2057 *t0 = NULL;
21409 const struct chan_info_nphy_radio205x *t1 = NULL;
21410 const struct chan_info_nphy_radio2057_rev5 *t2 = NULL;
21411 const struct chan_info_nphy_2055 *t3 = NULL;
21412
21413 if (!wlc_phy_chan2freq_nphy
21414 (pi, CHSPEC_CHANNEL(chanspec), &freq, &t0, &t1, &t2, &t3))
21415 return;
21416
21417 wlc_phy_chanspec_radio_set((struct brcms_phy_pub *) pi, chanspec);
21418
21419 if (CHSPEC_BW(chanspec) != pi->bw)
21420 wlapi_bmac_bw_set(pi->sh->physhim, CHSPEC_BW(chanspec));
21421
21422 if (CHSPEC_IS40(chanspec)) {
21423 if (CHSPEC_SB_UPPER(chanspec)) {
21424 or_phy_reg(pi, 0xa0, BPHY_BAND_SEL_UP20);
21425 if (NREV_GE(pi->pubpi.phy_rev, 7))
21426 or_phy_reg(pi, 0x310, PRIM_SEL_UP20);
21427 } else {
21428 and_phy_reg(pi, 0xa0, ~BPHY_BAND_SEL_UP20);
21429 if (NREV_GE(pi->pubpi.phy_rev, 7))
21430 and_phy_reg(pi, 0x310,
21431 (~PRIM_SEL_UP20 & 0xffff));
21432 }
21433 }
21434
21435 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
21436 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21437
21438 if ((pi->pubpi.radiorev <= 4)
21439 || (pi->pubpi.radiorev == 6)) {
21440 mod_radio_reg(pi, RADIO_2057_TIA_CONFIG_CORE0,
21441 0x2,
21442 (CHSPEC_IS5G(chanspec) ? (1 << 1)
21443 : 0));
21444 mod_radio_reg(pi, RADIO_2057_TIA_CONFIG_CORE1,
21445 0x2,
21446 (CHSPEC_IS5G(chanspec) ? (1 << 1)
21447 : 0));
21448 }
21449
21450 wlc_phy_chanspec_radio2057_setup(pi, t0, t2);
21451 wlc_phy_chanspec_nphy_setup(pi, chanspec,
21452 (pi->pubpi.radiorev == 5) ?
21453 (const struct nphy_sfo_cfg *)&(t2->PHY_BW1a) :
21454 (const struct nphy_sfo_cfg *)&(t0->PHY_BW1a));
21455
21456 } else {
21457
21458 mod_radio_reg(pi,
21459 RADIO_2056_SYN_COM_CTRL | RADIO_2056_SYN,
21460 0x4,
21461 (CHSPEC_IS5G(chanspec) ? (0x1 << 2) : 0));
21462 wlc_phy_chanspec_radio2056_setup(pi, t1);
21463
21464 wlc_phy_chanspec_nphy_setup(pi, chanspec,
21465 (const struct nphy_sfo_cfg *) &(t1->PHY_BW1a));
21466 }
21467
21468 } else {
21469
21470 mod_radio_reg(pi, RADIO_2055_MASTER_CNTRL1, 0x70,
21471 (CHSPEC_IS5G(chanspec) ? (0x02 << 4)
21472 : (0x05 << 4)));
21473
21474 wlc_phy_chanspec_radio2055_setup(pi, t3);
21475 wlc_phy_chanspec_nphy_setup(pi, chanspec,
21476 (const struct nphy_sfo_cfg *)
21477 &(t3->PHY_BW1a));
21478 }
21479
21480}
21481
21482void wlc_phy_antsel_init(struct brcms_phy_pub *ppi, bool lut_init)
21483{
21484 struct brcms_phy *pi = (struct brcms_phy *) ppi;
21485 u16 mask = 0xfc00;
21486 u32 mc = 0;
21487
21488 if (NREV_GE(pi->pubpi.phy_rev, 7))
21489 return;
21490
21491 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
21492 u16 v0 = 0x211, v1 = 0x222, v2 = 0x144, v3 = 0x188;
21493
21494 if (lut_init == false)
21495 return;
21496
21497 if (pi->srom_fem2g.antswctrllut == 0) {
21498 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21499 1, 0x02, 16, &v0);
21500 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21501 1, 0x03, 16, &v1);
21502 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21503 1, 0x08, 16, &v2);
21504 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21505 1, 0x0C, 16, &v3);
21506 }
21507
21508 if (pi->srom_fem5g.antswctrllut == 0) {
21509 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21510 1, 0x12, 16, &v0);
21511 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21512 1, 0x13, 16, &v1);
21513 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21514 1, 0x18, 16, &v2);
21515 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
21516 1, 0x1C, 16, &v3);
21517 }
21518 } else {
21519
21520 write_phy_reg(pi, 0xc8, 0x0);
21521 write_phy_reg(pi, 0xc9, 0x0);
21522
21523 ai_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
21524
21525 mc = R_REG(&pi->regs->maccontrol);
21526 mc &= ~MCTL_GPOUT_SEL_MASK;
21527 W_REG(&pi->regs->maccontrol, mc);
21528
21529 OR_REG(&pi->regs->psm_gpio_oe, mask);
21530
21531 AND_REG(&pi->regs->psm_gpio_out, ~mask);
21532
21533 if (lut_init) {
21534 write_phy_reg(pi, 0xf8, 0x02d8);
21535 write_phy_reg(pi, 0xf9, 0x0301);
21536 write_phy_reg(pi, 0xfa, 0x02d8);
21537 write_phy_reg(pi, 0xfb, 0x0301);
21538 }
21539 }
21540}
21541
21542u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val)
21543{
21544 u16 curr_ctl, new_ctl;
21545 bool suspended = false;
21546
21547 if (D11REV_IS(pi->sh->corerev, 16)) {
21548 suspended =
21549 (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) ?
21550 false : true;
21551 if (!suspended)
21552 wlapi_suspend_mac_and_wait(pi->sh->physhim);
21553 }
21554
21555 curr_ctl = read_phy_reg(pi, 0xb0) & (0x7 << 0);
21556
21557 new_ctl = (curr_ctl & (~mask)) | (val & mask);
21558
21559 mod_phy_reg(pi, 0xb0, (0x7 << 0), new_ctl);
21560
21561 if (D11REV_IS(pi->sh->corerev, 16) && !suspended)
21562 wlapi_enable_mac(pi->sh->physhim);
21563
21564 return new_ctl;
21565}
21566
21567void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd)
21568{
21569 u16 trigger_mask, status_mask;
21570 u16 orig_RfseqCoreActv;
21571
21572 switch (cmd) {
21573 case NPHY_RFSEQ_RX2TX:
21574 trigger_mask = NPHY_RfseqTrigger_rx2tx;
21575 status_mask = NPHY_RfseqStatus_rx2tx;
21576 break;
21577 case NPHY_RFSEQ_TX2RX:
21578 trigger_mask = NPHY_RfseqTrigger_tx2rx;
21579 status_mask = NPHY_RfseqStatus_tx2rx;
21580 break;
21581 case NPHY_RFSEQ_RESET2RX:
21582 trigger_mask = NPHY_RfseqTrigger_reset2rx;
21583 status_mask = NPHY_RfseqStatus_reset2rx;
21584 break;
21585 case NPHY_RFSEQ_UPDATEGAINH:
21586 trigger_mask = NPHY_RfseqTrigger_updategainh;
21587 status_mask = NPHY_RfseqStatus_updategainh;
21588 break;
21589 case NPHY_RFSEQ_UPDATEGAINL:
21590 trigger_mask = NPHY_RfseqTrigger_updategainl;
21591 status_mask = NPHY_RfseqStatus_updategainl;
21592 break;
21593 case NPHY_RFSEQ_UPDATEGAINU:
21594 trigger_mask = NPHY_RfseqTrigger_updategainu;
21595 status_mask = NPHY_RfseqStatus_updategainu;
21596 break;
21597 default:
21598 return;
21599 }
21600
21601 orig_RfseqCoreActv = read_phy_reg(pi, 0xa1);
21602 or_phy_reg(pi, 0xa1,
21603 (NPHY_RfseqMode_CoreActv_override |
21604 NPHY_RfseqMode_Trigger_override));
21605 or_phy_reg(pi, 0xa3, trigger_mask);
21606 SPINWAIT((read_phy_reg(pi, 0xa4) & status_mask), 200000);
21607 write_phy_reg(pi, 0xa1, orig_RfseqCoreActv);
21608 WARN(read_phy_reg(pi, 0xa4) & status_mask, "HW error in rf");
21609}
21610
21611static void
21612wlc_phy_rfctrl_override_1tomany_nphy(struct brcms_phy *pi, u16 cmd, u16 value,
21613 u8 core_mask, u8 off)
21614{
21615 u16 rfmxgain = 0, lpfgain = 0;
21616 u16 tgain = 0;
21617
21618 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21619
21620 switch (cmd) {
21621 case NPHY_REV7_RfctrlOverride_cmd_rxrf_pu:
21622 wlc_phy_rfctrl_override_nphy_rev7(
21623 pi, (0x1 << 5),
21624 value, core_mask, off,
21625 NPHY_REV7_RFCTRLOVERRIDE_ID1);
21626 wlc_phy_rfctrl_override_nphy_rev7(
21627 pi, (0x1 << 4), value,
21628 core_mask, off,
21629 NPHY_REV7_RFCTRLOVERRIDE_ID1);
21630 wlc_phy_rfctrl_override_nphy_rev7(
21631 pi, (0x1 << 3), value,
21632 core_mask, off,
21633 NPHY_REV7_RFCTRLOVERRIDE_ID1);
21634 break;
21635 case NPHY_REV7_RfctrlOverride_cmd_rx_pu:
21636 wlc_phy_rfctrl_override_nphy_rev7(
21637 pi, (0x1 << 2),
21638 value, core_mask, off,
21639 NPHY_REV7_RFCTRLOVERRIDE_ID1);
21640 wlc_phy_rfctrl_override_nphy_rev7(
21641 pi, (0x1 << 1), value,
21642 core_mask, off,
21643 NPHY_REV7_RFCTRLOVERRIDE_ID1);
21644 wlc_phy_rfctrl_override_nphy_rev7(
21645 pi, (0x1 << 0), value,
21646 core_mask, off,
21647 NPHY_REV7_RFCTRLOVERRIDE_ID1);
21648 wlc_phy_rfctrl_override_nphy_rev7(
21649 pi, (0x1 << 1), value,
21650 core_mask, off,
21651 NPHY_REV7_RFCTRLOVERRIDE_ID2);
21652 wlc_phy_rfctrl_override_nphy_rev7(
21653 pi, (0x1 << 11), 0,
21654 core_mask, off,
21655 NPHY_REV7_RFCTRLOVERRIDE_ID1);
21656 break;
21657 case NPHY_REV7_RfctrlOverride_cmd_tx_pu:
21658 wlc_phy_rfctrl_override_nphy_rev7(
21659 pi, (0x1 << 2),
21660 value, core_mask, off,
21661 NPHY_REV7_RFCTRLOVERRIDE_ID0);
21662 wlc_phy_rfctrl_override_nphy_rev7(
21663 pi, (0x1 << 1), value,
21664 core_mask, off,
21665 NPHY_REV7_RFCTRLOVERRIDE_ID1);
21666 wlc_phy_rfctrl_override_nphy_rev7(
21667 pi, (0x1 << 0), value,
21668 core_mask, off,
21669 NPHY_REV7_RFCTRLOVERRIDE_ID2);
21670 wlc_phy_rfctrl_override_nphy_rev7(
21671 pi, (0x1 << 2), value,
21672 core_mask, off,
21673 NPHY_REV7_RFCTRLOVERRIDE_ID2);
21674 wlc_phy_rfctrl_override_nphy_rev7(
21675 pi, (0x1 << 11), 1,
21676 core_mask, off,
21677 NPHY_REV7_RFCTRLOVERRIDE_ID1);
21678 break;
21679 case NPHY_REV7_RfctrlOverride_cmd_rxgain:
21680 rfmxgain = value & 0x000ff;
21681 lpfgain = value & 0x0ff00;
21682 lpfgain = lpfgain >> 8;
21683
21684 wlc_phy_rfctrl_override_nphy_rev7(
21685 pi, (0x1 << 11),
21686 rfmxgain, core_mask,
21687 off,
21688 NPHY_REV7_RFCTRLOVERRIDE_ID0);
21689 wlc_phy_rfctrl_override_nphy_rev7(
21690 pi, (0x3 << 13),
21691 lpfgain, core_mask,
21692 off,
21693 NPHY_REV7_RFCTRLOVERRIDE_ID0);
21694 break;
21695 case NPHY_REV7_RfctrlOverride_cmd_txgain:
21696 tgain = value & 0x7fff;
21697 lpfgain = value & 0x8000;
21698 lpfgain = lpfgain >> 14;
21699
21700 wlc_phy_rfctrl_override_nphy_rev7(
21701 pi, (0x1 << 12),
21702 tgain, core_mask, off,
21703 NPHY_REV7_RFCTRLOVERRIDE_ID0);
21704 wlc_phy_rfctrl_override_nphy_rev7(
21705 pi, (0x1 << 13),
21706 lpfgain, core_mask,
21707 off,
21708 NPHY_REV7_RFCTRLOVERRIDE_ID0);
21709 break;
21710 }
21711 }
21712}
21713
21714static void
21715wlc_phy_scale_offset_rssi_nphy(struct brcms_phy *pi, u16 scale, s8 offset,
21716 u8 coresel, u8 rail, u8 rssi_type)
21717{
21718 u16 valuetostuff;
21719
21720 offset = (offset > NPHY_RSSICAL_MAXREAD) ?
21721 NPHY_RSSICAL_MAXREAD : offset;
21722 offset = (offset < (-NPHY_RSSICAL_MAXREAD - 1)) ?
21723 -NPHY_RSSICAL_MAXREAD - 1 : offset;
21724
21725 valuetostuff = ((scale & 0x3f) << 8) | (offset & 0x3f);
21726
21727 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21728 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21729 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_NB))
21730 write_phy_reg(pi, 0x1a6, valuetostuff);
21731
21732 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21733 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21734 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_NB))
21735 write_phy_reg(pi, 0x1ac, valuetostuff);
21736
21737 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21738 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21739 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_NB))
21740 write_phy_reg(pi, 0x1b2, valuetostuff);
21741
21742 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21743 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21744 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_NB))
21745 write_phy_reg(pi, 0x1b8, valuetostuff);
21746
21747 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21748 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21749 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W1))
21750 write_phy_reg(pi, 0x1a4, valuetostuff);
21751
21752 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21753 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21754 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W1))
21755 write_phy_reg(pi, 0x1aa, valuetostuff);
21756
21757 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21758 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21759 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W1))
21760 write_phy_reg(pi, 0x1b0, valuetostuff);
21761
21762 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21763 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21764 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W1))
21765 write_phy_reg(pi, 0x1b6, valuetostuff);
21766
21767 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21768 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21769 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W2))
21770 write_phy_reg(pi, 0x1a5, valuetostuff);
21771 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21772 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21773 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W2))
21774 write_phy_reg(pi, 0x1ab, valuetostuff);
21775
21776 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21777 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21778 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W2))
21779 write_phy_reg(pi, 0x1b1, valuetostuff);
21780
21781 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21782 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21783 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W2))
21784 write_phy_reg(pi, 0x1b7, valuetostuff);
21785
21786 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21787 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21788 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_TBD))
21789 write_phy_reg(pi, 0x1a7, valuetostuff);
21790 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21791 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21792 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_TBD))
21793 write_phy_reg(pi, 0x1ad, valuetostuff);
21794 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21795 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21796 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_TBD))
21797 write_phy_reg(pi, 0x1b3, valuetostuff);
21798 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21799 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21800 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_TBD))
21801 write_phy_reg(pi, 0x1b9, valuetostuff);
21802
21803 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21804 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21805 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_IQ))
21806 write_phy_reg(pi, 0x1a8, valuetostuff);
21807
21808 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21809 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21810 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_IQ))
21811 write_phy_reg(pi, 0x1ae, valuetostuff);
21812
21813 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21814 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21815 (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_IQ))
21816 write_phy_reg(pi, 0x1b4, valuetostuff);
21817
21818 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21819 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21820 (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_IQ))
21821 write_phy_reg(pi, 0x1ba, valuetostuff);
21822
21823 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21824 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21825 (rssi_type == NPHY_RSSI_SEL_TSSI_2G))
21826 write_phy_reg(pi, 0x1a9, valuetostuff);
21827 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21828 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21829 (rssi_type == NPHY_RSSI_SEL_TSSI_2G))
21830 write_phy_reg(pi, 0x1b5, valuetostuff);
21831
21832 if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
21833 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21834 (rssi_type == NPHY_RSSI_SEL_TSSI_5G))
21835 write_phy_reg(pi, 0x1af, valuetostuff);
21836
21837 if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
21838 (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
21839 (rssi_type == NPHY_RSSI_SEL_TSSI_5G))
21840 write_phy_reg(pi, 0x1bb, valuetostuff);
21841}
21842
21843static void brcms_phy_wr_tx_mux(struct brcms_phy *pi, u8 core)
21844{
21845 if (PHY_IPA(pi)) {
21846 if (NREV_GE(pi->pubpi.phy_rev, 7))
21847 write_radio_reg(pi,
21848 ((core == PHY_CORE_0) ?
21849 RADIO_2057_TX0_TX_SSI_MUX :
21850 RADIO_2057_TX1_TX_SSI_MUX),
21851 (CHSPEC_IS5G(pi->radio_chanspec) ?
21852 0xc : 0xe));
21853 else
21854 write_radio_reg(pi,
21855 RADIO_2056_TX_TX_SSI_MUX |
21856 ((core == PHY_CORE_0) ?
21857 RADIO_2056_TX0 : RADIO_2056_TX1),
21858 (CHSPEC_IS5G(pi->radio_chanspec) ?
21859 0xc : 0xe));
21860 } else {
21861 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
21862 write_radio_reg(pi,
21863 ((core == PHY_CORE_0) ?
21864 RADIO_2057_TX0_TX_SSI_MUX :
21865 RADIO_2057_TX1_TX_SSI_MUX),
21866 0x11);
21867
21868 if (pi->pubpi.radioid == BCM2057_ID)
21869 write_radio_reg(pi,
21870 RADIO_2057_IQTEST_SEL_PU, 0x1);
21871
21872 } else {
21873 write_radio_reg(pi,
21874 RADIO_2056_TX_TX_SSI_MUX |
21875 ((core == PHY_CORE_0) ?
21876 RADIO_2056_TX0 : RADIO_2056_TX1),
21877 0x11);
21878 }
21879 }
21880}
21881
21882void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core_code, u8 rssi_type)
21883{
21884 u16 mask, val;
21885 u16 afectrlovr_rssi_val, rfctrlcmd_rxen_val, rfctrlcmd_coresel_val,
21886 startseq;
21887 u16 rfctrlovr_rssi_val, rfctrlovr_rxen_val, rfctrlovr_coresel_val,
21888 rfctrlovr_trigger_val;
21889 u16 afectrlovr_rssi_mask, rfctrlcmd_mask, rfctrlovr_mask;
21890 u16 rfctrlcmd_val, rfctrlovr_val;
21891 u8 core;
21892
21893 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
21894 if (core_code == RADIO_MIMO_CORESEL_OFF) {
21895 mod_phy_reg(pi, 0x8f, (0x1 << 9), 0);
21896 mod_phy_reg(pi, 0xa5, (0x1 << 9), 0);
21897
21898 mod_phy_reg(pi, 0xa6, (0x3 << 8), 0);
21899 mod_phy_reg(pi, 0xa7, (0x3 << 8), 0);
21900
21901 mod_phy_reg(pi, 0xe5, (0x1 << 5), 0);
21902 mod_phy_reg(pi, 0xe6, (0x1 << 5), 0);
21903
21904 mask = (0x1 << 2) |
21905 (0x1 << 3) | (0x1 << 4) | (0x1 << 5);
21906 mod_phy_reg(pi, 0xf9, mask, 0);
21907 mod_phy_reg(pi, 0xfb, mask, 0);
21908
21909 } else {
21910 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
21911 if (core_code == RADIO_MIMO_CORESEL_CORE1
21912 && core == PHY_CORE_1)
21913 continue;
21914 else if (core_code == RADIO_MIMO_CORESEL_CORE2
21915 && core == PHY_CORE_0)
21916 continue;
21917
21918 mod_phy_reg(pi, (core == PHY_CORE_0) ?
21919 0x8f : 0xa5, (0x1 << 9), 1 << 9);
21920
21921 if (rssi_type == NPHY_RSSI_SEL_W1 ||
21922 rssi_type == NPHY_RSSI_SEL_W2 ||
21923 rssi_type == NPHY_RSSI_SEL_NB) {
21924 mod_phy_reg(pi,
21925 (core ==
21926 PHY_CORE_0) ? 0xa6 : 0xa7,
21927 (0x3 << 8), 0);
21928
21929 mask = (0x1 << 2) |
21930 (0x1 << 3) |
21931 (0x1 << 4) | (0x1 << 5);
21932 mod_phy_reg(pi,
21933 (core ==
21934 PHY_CORE_0) ? 0xf9 : 0xfb,
21935 mask, 0);
21936
21937 if (rssi_type == NPHY_RSSI_SEL_W1) {
21938 if (CHSPEC_IS5G(
21939 pi->radio_chanspec)) {
21940 mask = (0x1 << 2);
21941 val = 1 << 2;
21942 } else {
21943 mask = (0x1 << 3);
21944 val = 1 << 3;
21945 }
21946 } else if (rssi_type ==
21947 NPHY_RSSI_SEL_W2) {
21948 mask = (0x1 << 4);
21949 val = 1 << 4;
21950 } else {
21951 mask = (0x1 << 5);
21952 val = 1 << 5;
21953 }
21954 mod_phy_reg(pi,
21955 (core ==
21956 PHY_CORE_0) ? 0xf9 : 0xfb,
21957 mask, val);
21958
21959 mask = (0x1 << 5);
21960 val = 1 << 5;
21961 mod_phy_reg(pi, (core == PHY_CORE_0) ?
21962 0xe5 : 0xe6, mask, val);
21963 } else {
21964 if (rssi_type == NPHY_RSSI_SEL_TBD) {
21965 mask = (0x3 << 8);
21966 val = 1 << 8;
21967 mod_phy_reg(pi,
21968 (core ==
21969 PHY_CORE_0) ? 0xa6
21970 : 0xa7, mask, val);
21971 mask = (0x3 << 10);
21972 val = 1 << 10;
21973 mod_phy_reg(pi,
21974 (core ==
21975 PHY_CORE_0) ? 0xa6
21976 : 0xa7, mask, val);
21977 } else if (rssi_type ==
21978 NPHY_RSSI_SEL_IQ) {
21979 mask = (0x3 << 8);
21980 val = 2 << 8;
21981 mod_phy_reg(pi,
21982 (core ==
21983 PHY_CORE_0) ? 0xa6
21984 : 0xa7, mask, val);
21985 mask = (0x3 << 10);
21986 val = 2 << 10;
21987 mod_phy_reg(pi,
21988 (core ==
21989 PHY_CORE_0) ? 0xa6
21990 : 0xa7, mask, val);
21991 } else {
21992 mask = (0x3 << 8);
21993 val = 3 << 8;
21994 mod_phy_reg(pi,
21995 (core ==
21996 PHY_CORE_0) ? 0xa6
21997 : 0xa7, mask, val);
21998 mask = (0x3 << 10);
21999 val = 3 << 10;
22000 mod_phy_reg(pi,
22001 (core ==
22002 PHY_CORE_0) ? 0xa6
22003 : 0xa7, mask, val);
22004 brcms_phy_wr_tx_mux(pi, core);
22005 afectrlovr_rssi_val = 1 << 9;
22006 mod_phy_reg(pi,
22007 (core ==
22008 PHY_CORE_0) ? 0x8f
22009 : 0xa5, (0x1 << 9),
22010 afectrlovr_rssi_val);
22011 }
22012 }
22013 }
22014 }
22015 } else {
22016
22017 if ((rssi_type == NPHY_RSSI_SEL_W1) ||
22018 (rssi_type == NPHY_RSSI_SEL_W2) ||
22019 (rssi_type == NPHY_RSSI_SEL_NB))
22020 val = 0x0;
22021 else if (rssi_type == NPHY_RSSI_SEL_TBD)
22022 val = 0x1;
22023 else if (rssi_type == NPHY_RSSI_SEL_IQ)
22024 val = 0x2;
22025 else
22026 val = 0x3;
22027
22028 mask = ((0x3 << 12) | (0x3 << 14));
22029 val = (val << 12) | (val << 14);
22030 mod_phy_reg(pi, 0xa6, mask, val);
22031 mod_phy_reg(pi, 0xa7, mask, val);
22032
22033 if ((rssi_type == NPHY_RSSI_SEL_W1) ||
22034 (rssi_type == NPHY_RSSI_SEL_W2) ||
22035 (rssi_type == NPHY_RSSI_SEL_NB)) {
22036 if (rssi_type == NPHY_RSSI_SEL_W1)
22037 val = 0x1;
22038 if (rssi_type == NPHY_RSSI_SEL_W2)
22039 val = 0x2;
22040 if (rssi_type == NPHY_RSSI_SEL_NB)
22041 val = 0x3;
22042
22043 mask = (0x3 << 4);
22044 val = (val << 4);
22045 mod_phy_reg(pi, 0x7a, mask, val);
22046 mod_phy_reg(pi, 0x7d, mask, val);
22047 }
22048
22049 if (core_code == RADIO_MIMO_CORESEL_OFF) {
22050 afectrlovr_rssi_val = 0;
22051 rfctrlcmd_rxen_val = 0;
22052 rfctrlcmd_coresel_val = 0;
22053 rfctrlovr_rssi_val = 0;
22054 rfctrlovr_rxen_val = 0;
22055 rfctrlovr_coresel_val = 0;
22056 rfctrlovr_trigger_val = 0;
22057 startseq = 0;
22058 } else {
22059 afectrlovr_rssi_val = 1;
22060 rfctrlcmd_rxen_val = 1;
22061 rfctrlcmd_coresel_val = core_code;
22062 rfctrlovr_rssi_val = 1;
22063 rfctrlovr_rxen_val = 1;
22064 rfctrlovr_coresel_val = 1;
22065 rfctrlovr_trigger_val = 1;
22066 startseq = 1;
22067 }
22068
22069 afectrlovr_rssi_mask = ((0x1 << 12) | (0x1 << 13));
22070 afectrlovr_rssi_val = (afectrlovr_rssi_val <<
22071 12) | (afectrlovr_rssi_val << 13);
22072 mod_phy_reg(pi, 0xa5, afectrlovr_rssi_mask,
22073 afectrlovr_rssi_val);
22074
22075 if ((rssi_type == NPHY_RSSI_SEL_W1) ||
22076 (rssi_type == NPHY_RSSI_SEL_W2) ||
22077 (rssi_type == NPHY_RSSI_SEL_NB)) {
22078 rfctrlcmd_mask = ((0x1 << 8) | (0x7 << 3));
22079 rfctrlcmd_val = (rfctrlcmd_rxen_val << 8) |
22080 (rfctrlcmd_coresel_val << 3);
22081
22082 rfctrlovr_mask = ((0x1 << 5) |
22083 (0x1 << 12) |
22084 (0x1 << 1) | (0x1 << 0));
22085 rfctrlovr_val = (rfctrlovr_rssi_val <<
22086 5) |
22087 (rfctrlovr_rxen_val << 12) |
22088 (rfctrlovr_coresel_val << 1) |
22089 (rfctrlovr_trigger_val << 0);
22090
22091 mod_phy_reg(pi, 0x78, rfctrlcmd_mask, rfctrlcmd_val);
22092 mod_phy_reg(pi, 0xec, rfctrlovr_mask, rfctrlovr_val);
22093
22094 mod_phy_reg(pi, 0x78, (0x1 << 0), (startseq << 0));
22095 udelay(20);
22096
22097 mod_phy_reg(pi, 0xec, (0x1 << 0), 0);
22098 }
22099 }
22100}
22101
22102int
22103wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type, s32 *rssi_buf,
22104 u8 nsamps)
22105{
22106 s16 rssi0, rssi1;
22107 u16 afectrlCore1_save = 0;
22108 u16 afectrlCore2_save = 0;
22109 u16 afectrlOverride1_save = 0;
22110 u16 afectrlOverride2_save = 0;
22111 u16 rfctrlOverrideAux0_save = 0;
22112 u16 rfctrlOverrideAux1_save = 0;
22113 u16 rfctrlMiscReg1_save = 0;
22114 u16 rfctrlMiscReg2_save = 0;
22115 u16 rfctrlcmd_save = 0;
22116 u16 rfctrloverride_save = 0;
22117 u16 rfctrlrssiothers1_save = 0;
22118 u16 rfctrlrssiothers2_save = 0;
22119 s8 tmp_buf[4];
22120 u8 ctr = 0, samp = 0;
22121 s32 rssi_out_val;
22122 u16 gpiosel_orig;
22123
22124 afectrlCore1_save = read_phy_reg(pi, 0xa6);
22125 afectrlCore2_save = read_phy_reg(pi, 0xa7);
22126 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
22127 rfctrlMiscReg1_save = read_phy_reg(pi, 0xf9);
22128 rfctrlMiscReg2_save = read_phy_reg(pi, 0xfb);
22129 afectrlOverride1_save = read_phy_reg(pi, 0x8f);
22130 afectrlOverride2_save = read_phy_reg(pi, 0xa5);
22131 rfctrlOverrideAux0_save = read_phy_reg(pi, 0xe5);
22132 rfctrlOverrideAux1_save = read_phy_reg(pi, 0xe6);
22133 } else {
22134 afectrlOverride1_save = read_phy_reg(pi, 0xa5);
22135 rfctrlcmd_save = read_phy_reg(pi, 0x78);
22136 rfctrloverride_save = read_phy_reg(pi, 0xec);
22137 rfctrlrssiothers1_save = read_phy_reg(pi, 0x7a);
22138 rfctrlrssiothers2_save = read_phy_reg(pi, 0x7d);
22139 }
22140
22141 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_ALLRX, rssi_type);
22142
22143 gpiosel_orig = read_phy_reg(pi, 0xca);
22144 if (NREV_LT(pi->pubpi.phy_rev, 2))
22145 write_phy_reg(pi, 0xca, 5);
22146
22147 for (ctr = 0; ctr < 4; ctr++)
22148 rssi_buf[ctr] = 0;
22149
22150 for (samp = 0; samp < nsamps; samp++) {
22151 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
22152 rssi0 = read_phy_reg(pi, 0x1c9);
22153 rssi1 = read_phy_reg(pi, 0x1ca);
22154 } else {
22155 rssi0 = read_phy_reg(pi, 0x219);
22156 rssi1 = read_phy_reg(pi, 0x21a);
22157 }
22158
22159 ctr = 0;
22160 tmp_buf[ctr++] = ((s8) ((rssi0 & 0x3f) << 2)) >> 2;
22161 tmp_buf[ctr++] = ((s8) (((rssi0 >> 8) & 0x3f) << 2)) >> 2;
22162 tmp_buf[ctr++] = ((s8) ((rssi1 & 0x3f) << 2)) >> 2;
22163 tmp_buf[ctr++] = ((s8) (((rssi1 >> 8) & 0x3f) << 2)) >> 2;
22164
22165 for (ctr = 0; ctr < 4; ctr++)
22166 rssi_buf[ctr] += tmp_buf[ctr];
22167
22168 }
22169
22170 rssi_out_val = rssi_buf[3] & 0xff;
22171 rssi_out_val |= (rssi_buf[2] & 0xff) << 8;
22172 rssi_out_val |= (rssi_buf[1] & 0xff) << 16;
22173 rssi_out_val |= (rssi_buf[0] & 0xff) << 24;
22174
22175 if (NREV_LT(pi->pubpi.phy_rev, 2))
22176 write_phy_reg(pi, 0xca, gpiosel_orig);
22177
22178 write_phy_reg(pi, 0xa6, afectrlCore1_save);
22179 write_phy_reg(pi, 0xa7, afectrlCore2_save);
22180 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
22181 write_phy_reg(pi, 0xf9, rfctrlMiscReg1_save);
22182 write_phy_reg(pi, 0xfb, rfctrlMiscReg2_save);
22183 write_phy_reg(pi, 0x8f, afectrlOverride1_save);
22184 write_phy_reg(pi, 0xa5, afectrlOverride2_save);
22185 write_phy_reg(pi, 0xe5, rfctrlOverrideAux0_save);
22186 write_phy_reg(pi, 0xe6, rfctrlOverrideAux1_save);
22187 } else {
22188 write_phy_reg(pi, 0xa5, afectrlOverride1_save);
22189 write_phy_reg(pi, 0x78, rfctrlcmd_save);
22190 write_phy_reg(pi, 0xec, rfctrloverride_save);
22191 write_phy_reg(pi, 0x7a, rfctrlrssiothers1_save);
22192 write_phy_reg(pi, 0x7d, rfctrlrssiothers2_save);
22193 }
22194
22195 return rssi_out_val;
22196}
22197
22198s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi)
22199{
22200 u16 core1_txrf_iqcal1_save, core1_txrf_iqcal2_save;
22201 u16 core2_txrf_iqcal1_save, core2_txrf_iqcal2_save;
22202 u16 pwrdet_rxtx_core1_save;
22203 u16 pwrdet_rxtx_core2_save;
22204 u16 afectrlCore1_save;
22205 u16 afectrlCore2_save;
22206 u16 afectrlOverride_save;
22207 u16 afectrlOverride2_save;
22208 u16 pd_pll_ts_save;
22209 u16 gpioSel_save;
22210 s32 radio_temp[4];
22211 s32 radio_temp2[4];
22212 u16 syn_tempprocsense_save;
22213 s16 offset = 0;
22214
22215 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22216 u16 auxADC_Vmid, auxADC_Av, auxADC_Vmid_save, auxADC_Av_save;
22217 u16 auxADC_rssi_ctrlL_save, auxADC_rssi_ctrlH_save;
22218 u16 auxADC_rssi_ctrlL, auxADC_rssi_ctrlH;
22219 s32 auxADC_Vl;
22220 u16 RfctrlOverride5_save, RfctrlOverride6_save;
22221 u16 RfctrlMiscReg5_save, RfctrlMiscReg6_save;
22222 u16 RSSIMultCoef0QPowerDet_save;
22223 u16 tempsense_Rcal;
22224
22225 syn_tempprocsense_save =
22226 read_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG);
22227
22228 afectrlCore1_save = read_phy_reg(pi, 0xa6);
22229 afectrlCore2_save = read_phy_reg(pi, 0xa7);
22230 afectrlOverride_save = read_phy_reg(pi, 0x8f);
22231 afectrlOverride2_save = read_phy_reg(pi, 0xa5);
22232 RSSIMultCoef0QPowerDet_save = read_phy_reg(pi, 0x1ae);
22233 RfctrlOverride5_save = read_phy_reg(pi, 0x346);
22234 RfctrlOverride6_save = read_phy_reg(pi, 0x347);
22235 RfctrlMiscReg5_save = read_phy_reg(pi, 0x344);
22236 RfctrlMiscReg6_save = read_phy_reg(pi, 0x345);
22237
22238 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
22239 &auxADC_Vmid_save);
22240 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
22241 &auxADC_Av_save);
22242 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
22243 &auxADC_rssi_ctrlL_save);
22244 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
22245 &auxADC_rssi_ctrlH_save);
22246
22247 write_phy_reg(pi, 0x1ae, 0x0);
22248
22249 auxADC_rssi_ctrlL = 0x0;
22250 auxADC_rssi_ctrlH = 0x20;
22251 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
22252 &auxADC_rssi_ctrlL);
22253 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
22254 &auxADC_rssi_ctrlH);
22255
22256 tempsense_Rcal = syn_tempprocsense_save & 0x1c;
22257
22258 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
22259 tempsense_Rcal | 0x01);
22260
22261 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1),
22262 1, 0, 0,
22263 NPHY_REV7_RFCTRLOVERRIDE_ID2);
22264 mod_phy_reg(pi, 0xa6, (0x1 << 7), 0);
22265 mod_phy_reg(pi, 0xa7, (0x1 << 7), 0);
22266 mod_phy_reg(pi, 0x8f, (0x1 << 7), (0x1 << 7));
22267 mod_phy_reg(pi, 0xa5, (0x1 << 7), (0x1 << 7));
22268
22269 mod_phy_reg(pi, 0xa6, (0x1 << 2), (0x1 << 2));
22270 mod_phy_reg(pi, 0xa7, (0x1 << 2), (0x1 << 2));
22271 mod_phy_reg(pi, 0x8f, (0x1 << 2), (0x1 << 2));
22272 mod_phy_reg(pi, 0xa5, (0x1 << 2), (0x1 << 2));
22273 udelay(5);
22274 mod_phy_reg(pi, 0xa6, (0x1 << 2), 0);
22275 mod_phy_reg(pi, 0xa7, (0x1 << 2), 0);
22276 mod_phy_reg(pi, 0xa6, (0x1 << 3), 0);
22277 mod_phy_reg(pi, 0xa7, (0x1 << 3), 0);
22278 mod_phy_reg(pi, 0x8f, (0x1 << 3), (0x1 << 3));
22279 mod_phy_reg(pi, 0xa5, (0x1 << 3), (0x1 << 3));
22280 mod_phy_reg(pi, 0xa6, (0x1 << 6), 0);
22281 mod_phy_reg(pi, 0xa7, (0x1 << 6), 0);
22282 mod_phy_reg(pi, 0x8f, (0x1 << 6), (0x1 << 6));
22283 mod_phy_reg(pi, 0xa5, (0x1 << 6), (0x1 << 6));
22284
22285 auxADC_Vmid = 0xA3;
22286 auxADC_Av = 0x0;
22287 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
22288 &auxADC_Vmid);
22289 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
22290 &auxADC_Av);
22291
22292 udelay(3);
22293
22294 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22295 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
22296 tempsense_Rcal | 0x03);
22297
22298 udelay(5);
22299 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
22300
22301 auxADC_Av = 0x7;
22302 if (radio_temp[1] + radio_temp2[1] < -30) {
22303 auxADC_Vmid = 0x45;
22304 auxADC_Vl = 263;
22305 } else if (radio_temp[1] + radio_temp2[1] < -9) {
22306 auxADC_Vmid = 0x200;
22307 auxADC_Vl = 467;
22308 } else if (radio_temp[1] + radio_temp2[1] < 11) {
22309 auxADC_Vmid = 0x266;
22310 auxADC_Vl = 634;
22311 } else {
22312 auxADC_Vmid = 0x2D5;
22313 auxADC_Vl = 816;
22314 }
22315
22316 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
22317 &auxADC_Vmid);
22318 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
22319 &auxADC_Av);
22320
22321 udelay(3);
22322
22323 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
22324 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
22325 tempsense_Rcal | 0x01);
22326
22327 udelay(5);
22328 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22329
22330 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
22331 syn_tempprocsense_save);
22332
22333 write_phy_reg(pi, 0xa6, afectrlCore1_save);
22334 write_phy_reg(pi, 0xa7, afectrlCore2_save);
22335 write_phy_reg(pi, 0x8f, afectrlOverride_save);
22336 write_phy_reg(pi, 0xa5, afectrlOverride2_save);
22337 write_phy_reg(pi, 0x1ae, RSSIMultCoef0QPowerDet_save);
22338 write_phy_reg(pi, 0x346, RfctrlOverride5_save);
22339 write_phy_reg(pi, 0x347, RfctrlOverride6_save);
22340 write_phy_reg(pi, 0x344, RfctrlMiscReg5_save);
22341 write_phy_reg(pi, 0x345, RfctrlMiscReg5_save);
22342
22343 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
22344 &auxADC_Vmid_save);
22345 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
22346 &auxADC_Av_save);
22347 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
22348 &auxADC_rssi_ctrlL_save);
22349 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
22350 &auxADC_rssi_ctrlH_save);
22351
22352 radio_temp[0] = (179 * (radio_temp[1] + radio_temp2[1])
22353 + 82 * (auxADC_Vl) - 28861 +
22354 128) / 256;
22355
22356 offset = (s16) pi->phy_tempsense_offset;
22357
22358 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
22359 syn_tempprocsense_save =
22360 read_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE);
22361
22362 afectrlCore1_save = read_phy_reg(pi, 0xa6);
22363 afectrlCore2_save = read_phy_reg(pi, 0xa7);
22364 afectrlOverride_save = read_phy_reg(pi, 0x8f);
22365 afectrlOverride2_save = read_phy_reg(pi, 0xa5);
22366 gpioSel_save = read_phy_reg(pi, 0xca);
22367
22368 write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x01);
22369
22370 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22371 if (NREV_LT(pi->pubpi.phy_rev, 7))
22372 write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x05);
22373
22374 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
22375 if (NREV_GE(pi->pubpi.phy_rev, 7))
22376 write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG, 0x01);
22377 else
22378 write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x01);
22379
22380 radio_temp[0] =
22381 (126 * (radio_temp[1] + radio_temp2[1]) + 3987) / 64;
22382
22383 write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE,
22384 syn_tempprocsense_save);
22385
22386 write_phy_reg(pi, 0xca, gpioSel_save);
22387 write_phy_reg(pi, 0xa6, afectrlCore1_save);
22388 write_phy_reg(pi, 0xa7, afectrlCore2_save);
22389 write_phy_reg(pi, 0x8f, afectrlOverride_save);
22390 write_phy_reg(pi, 0xa5, afectrlOverride2_save);
22391
22392 offset = (s16) pi->phy_tempsense_offset;
22393 } else {
22394
22395 pwrdet_rxtx_core1_save =
22396 read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
22397 pwrdet_rxtx_core2_save =
22398 read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
22399 core1_txrf_iqcal1_save =
22400 read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
22401 core1_txrf_iqcal2_save =
22402 read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
22403 core2_txrf_iqcal1_save =
22404 read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
22405 core2_txrf_iqcal2_save =
22406 read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
22407 pd_pll_ts_save = read_radio_reg(pi, RADIO_2055_PD_PLL_TS);
22408
22409 afectrlCore1_save = read_phy_reg(pi, 0xa6);
22410 afectrlCore2_save = read_phy_reg(pi, 0xa7);
22411 afectrlOverride_save = read_phy_reg(pi, 0xa5);
22412 gpioSel_save = read_phy_reg(pi, 0xca);
22413
22414 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1, 0x01);
22415 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1, 0x01);
22416 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2, 0x08);
22417 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2, 0x08);
22418 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x04);
22419 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x04);
22420 write_radio_reg(pi, RADIO_2055_PD_PLL_TS, 0x00);
22421
22422 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22423 xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
22424
22425 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
22426 xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
22427
22428 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
22429 xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
22430
22431 radio_temp[0] = (radio_temp[0] + radio_temp2[0]);
22432 radio_temp[1] = (radio_temp[1] + radio_temp2[1]);
22433 radio_temp[2] = (radio_temp[2] + radio_temp2[2]);
22434 radio_temp[3] = (radio_temp[3] + radio_temp2[3]);
22435
22436 radio_temp[0] =
22437 (radio_temp[0] + radio_temp[1] + radio_temp[2] +
22438 radio_temp[3]);
22439
22440 radio_temp[0] =
22441 (radio_temp[0] +
22442 (8 * 32)) * (950 - 350) / 63 + (350 * 8);
22443
22444 radio_temp[0] = (radio_temp[0] - (8 * 420)) / 38;
22445
22446 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1,
22447 pwrdet_rxtx_core1_save);
22448 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2,
22449 pwrdet_rxtx_core2_save);
22450 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1,
22451 core1_txrf_iqcal1_save);
22452 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1,
22453 core2_txrf_iqcal1_save);
22454 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2,
22455 core1_txrf_iqcal2_save);
22456 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2,
22457 core2_txrf_iqcal2_save);
22458 write_radio_reg(pi, RADIO_2055_PD_PLL_TS, pd_pll_ts_save);
22459
22460 write_phy_reg(pi, 0xca, gpioSel_save);
22461 write_phy_reg(pi, 0xa6, afectrlCore1_save);
22462 write_phy_reg(pi, 0xa7, afectrlCore2_save);
22463 write_phy_reg(pi, 0xa5, afectrlOverride_save);
22464 }
22465
22466 return (s16) radio_temp[0] + offset;
22467}
22468
22469static void
22470wlc_phy_set_rssi_2055_vcm(struct brcms_phy *pi, u8 rssi_type, u8 *vcm_buf)
22471{
22472 u8 core;
22473
22474 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
22475 if (rssi_type == NPHY_RSSI_SEL_NB) {
22476 if (core == PHY_CORE_0) {
22477 mod_radio_reg(pi,
22478 RADIO_2055_CORE1_B0_NBRSSI_VCM,
22479 RADIO_2055_NBRSSI_VCM_I_MASK,
22480 vcm_buf[2 *
22481 core] <<
22482 RADIO_2055_NBRSSI_VCM_I_SHIFT);
22483 mod_radio_reg(pi,
22484 RADIO_2055_CORE1_RXBB_RSSI_CTRL5,
22485 RADIO_2055_NBRSSI_VCM_Q_MASK,
22486 vcm_buf[2 * core +
22487 1] <<
22488 RADIO_2055_NBRSSI_VCM_Q_SHIFT);
22489 } else {
22490 mod_radio_reg(pi,
22491 RADIO_2055_CORE2_B0_NBRSSI_VCM,
22492 RADIO_2055_NBRSSI_VCM_I_MASK,
22493 vcm_buf[2 *
22494 core] <<
22495 RADIO_2055_NBRSSI_VCM_I_SHIFT);
22496 mod_radio_reg(pi,
22497 RADIO_2055_CORE2_RXBB_RSSI_CTRL5,
22498 RADIO_2055_NBRSSI_VCM_Q_MASK,
22499 vcm_buf[2 * core +
22500 1] <<
22501 RADIO_2055_NBRSSI_VCM_Q_SHIFT);
22502 }
22503 } else {
22504 if (core == PHY_CORE_0)
22505 mod_radio_reg(pi,
22506 RADIO_2055_CORE1_RXBB_RSSI_CTRL5,
22507 RADIO_2055_WBRSSI_VCM_IQ_MASK,
22508 vcm_buf[2 *
22509 core] <<
22510 RADIO_2055_WBRSSI_VCM_IQ_SHIFT);
22511 else
22512 mod_radio_reg(pi,
22513 RADIO_2055_CORE2_RXBB_RSSI_CTRL5,
22514 RADIO_2055_WBRSSI_VCM_IQ_MASK,
22515 vcm_buf[2 *
22516 core] <<
22517 RADIO_2055_WBRSSI_VCM_IQ_SHIFT);
22518 }
22519 }
22520}
22521
22522static void wlc_phy_rssi_cal_nphy_rev3(struct brcms_phy *pi)
22523{
22524 u16 classif_state;
22525 u16 clip_state[2];
22526 u16 clip_off[] = { 0xffff, 0xffff };
22527 s32 target_code;
22528 u8 vcm, min_vcm;
22529 u8 vcm_final = 0;
22530 u8 result_idx;
22531 s32 poll_results[8][4] = {
22532 {0, 0, 0, 0},
22533 {0, 0, 0, 0},
22534 {0, 0, 0, 0},
22535 {0, 0, 0, 0},
22536 {0, 0, 0, 0},
22537 {0, 0, 0, 0},
22538 {0, 0, 0, 0},
22539 {0, 0, 0, 0}
22540 };
22541 s32 poll_result_core[4] = { 0, 0, 0, 0 };
22542 s32 min_d = NPHY_RSSICAL_MAXD, curr_d;
22543 s32 fine_digital_offset[4];
22544 s32 poll_results_min[4] = { 0, 0, 0, 0 };
22545 s32 min_poll;
22546 u8 vcm_level_max;
22547 u8 core;
22548 u8 wb_cnt;
22549 u8 rssi_type;
22550 u16 NPHY_Rfctrlintc1_save, NPHY_Rfctrlintc2_save;
22551 u16 NPHY_AfectrlOverride1_save, NPHY_AfectrlOverride2_save;
22552 u16 NPHY_AfectrlCore1_save, NPHY_AfectrlCore2_save;
22553 u16 NPHY_RfctrlOverride0_save, NPHY_RfctrlOverride1_save;
22554 u16 NPHY_RfctrlOverrideAux0_save, NPHY_RfctrlOverrideAux1_save;
22555 u16 NPHY_RfctrlCmd_save;
22556 u16 NPHY_RfctrlMiscReg1_save, NPHY_RfctrlMiscReg2_save;
22557 u16 NPHY_RfctrlRSSIOTHERS1_save, NPHY_RfctrlRSSIOTHERS2_save;
22558 u8 rxcore_state;
22559 u16 NPHY_REV7_RfctrlOverride3_save, NPHY_REV7_RfctrlOverride4_save;
22560 u16 NPHY_REV7_RfctrlOverride5_save, NPHY_REV7_RfctrlOverride6_save;
22561 u16 NPHY_REV7_RfctrlMiscReg3_save, NPHY_REV7_RfctrlMiscReg4_save;
22562 u16 NPHY_REV7_RfctrlMiscReg5_save, NPHY_REV7_RfctrlMiscReg6_save;
22563
22564 NPHY_REV7_RfctrlOverride3_save =
22565 NPHY_REV7_RfctrlOverride4_save =
22566 NPHY_REV7_RfctrlOverride5_save =
22567 NPHY_REV7_RfctrlOverride6_save =
22568 NPHY_REV7_RfctrlMiscReg3_save =
22569 NPHY_REV7_RfctrlMiscReg4_save =
22570 NPHY_REV7_RfctrlMiscReg5_save =
22571 NPHY_REV7_RfctrlMiscReg6_save = 0;
22572
22573 classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
22574 wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
22575 wlc_phy_clip_det_nphy(pi, 0, clip_state);
22576 wlc_phy_clip_det_nphy(pi, 1, clip_off);
22577
22578 NPHY_Rfctrlintc1_save = read_phy_reg(pi, 0x91);
22579 NPHY_Rfctrlintc2_save = read_phy_reg(pi, 0x92);
22580 NPHY_AfectrlOverride1_save = read_phy_reg(pi, 0x8f);
22581 NPHY_AfectrlOverride2_save = read_phy_reg(pi, 0xa5);
22582 NPHY_AfectrlCore1_save = read_phy_reg(pi, 0xa6);
22583 NPHY_AfectrlCore2_save = read_phy_reg(pi, 0xa7);
22584 NPHY_RfctrlOverride0_save = read_phy_reg(pi, 0xe7);
22585 NPHY_RfctrlOverride1_save = read_phy_reg(pi, 0xec);
22586 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22587 NPHY_REV7_RfctrlOverride3_save = read_phy_reg(pi, 0x342);
22588 NPHY_REV7_RfctrlOverride4_save = read_phy_reg(pi, 0x343);
22589 NPHY_REV7_RfctrlOverride5_save = read_phy_reg(pi, 0x346);
22590 NPHY_REV7_RfctrlOverride6_save = read_phy_reg(pi, 0x347);
22591 }
22592 NPHY_RfctrlOverrideAux0_save = read_phy_reg(pi, 0xe5);
22593 NPHY_RfctrlOverrideAux1_save = read_phy_reg(pi, 0xe6);
22594 NPHY_RfctrlCmd_save = read_phy_reg(pi, 0x78);
22595 NPHY_RfctrlMiscReg1_save = read_phy_reg(pi, 0xf9);
22596 NPHY_RfctrlMiscReg2_save = read_phy_reg(pi, 0xfb);
22597 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22598 NPHY_REV7_RfctrlMiscReg3_save = read_phy_reg(pi, 0x340);
22599 NPHY_REV7_RfctrlMiscReg4_save = read_phy_reg(pi, 0x341);
22600 NPHY_REV7_RfctrlMiscReg5_save = read_phy_reg(pi, 0x344);
22601 NPHY_REV7_RfctrlMiscReg6_save = read_phy_reg(pi, 0x345);
22602 }
22603 NPHY_RfctrlRSSIOTHERS1_save = read_phy_reg(pi, 0x7a);
22604 NPHY_RfctrlRSSIOTHERS2_save = read_phy_reg(pi, 0x7d);
22605
22606 wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_OFF, 0,
22607 RADIO_MIMO_CORESEL_ALLRXTX);
22608 wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_TRSW, 1,
22609 RADIO_MIMO_CORESEL_ALLRXTX);
22610
22611 if (NREV_GE(pi->pubpi.phy_rev, 7))
22612 wlc_phy_rfctrl_override_1tomany_nphy(
22613 pi,
22614 NPHY_REV7_RfctrlOverride_cmd_rxrf_pu,
22615 0, 0, 0);
22616 else
22617 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0, 0);
22618
22619 if (NREV_GE(pi->pubpi.phy_rev, 7))
22620 wlc_phy_rfctrl_override_1tomany_nphy(
22621 pi,
22622 NPHY_REV7_RfctrlOverride_cmd_rx_pu,
22623 1, 0, 0);
22624 else
22625 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 1, 0, 0);
22626
22627 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22628 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
22629 1, 0, 0,
22630 NPHY_REV7_RFCTRLOVERRIDE_ID0);
22631 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 6), 1, 0, 0,
22632 NPHY_REV7_RFCTRLOVERRIDE_ID0);
22633 } else {
22634 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 7), 1, 0, 0);
22635 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 6), 1, 0, 0);
22636 }
22637
22638 if (CHSPEC_IS5G(pi->radio_chanspec)) {
22639 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22640 wlc_phy_rfctrl_override_nphy_rev7(
22641 pi, (0x1 << 5),
22642 0, 0, 0,
22643 NPHY_REV7_RFCTRLOVERRIDE_ID0);
22644 wlc_phy_rfctrl_override_nphy_rev7(
22645 pi, (0x1 << 4), 1, 0,
22646 0,
22647 NPHY_REV7_RFCTRLOVERRIDE_ID0);
22648 } else {
22649 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 5), 0, 0, 0);
22650 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 4), 1, 0, 0);
22651 }
22652
22653 } else {
22654 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22655 wlc_phy_rfctrl_override_nphy_rev7(
22656 pi, (0x1 << 4),
22657 0, 0, 0,
22658 NPHY_REV7_RFCTRLOVERRIDE_ID0);
22659 wlc_phy_rfctrl_override_nphy_rev7(
22660 pi, (0x1 << 5), 1, 0,
22661 0,
22662 NPHY_REV7_RFCTRLOVERRIDE_ID0);
22663 } else {
22664 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 4), 0, 0, 0);
22665 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 5), 1, 0, 0);
22666 }
22667 }
22668
22669 rxcore_state = wlc_phy_rxcore_getstate_nphy(
22670 (struct brcms_phy_pub *) pi);
22671
22672 vcm_level_max = 8;
22673
22674 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
22675
22676 if ((rxcore_state & (1 << core)) == 0)
22677 continue;
22678
22679 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
22680 core ==
22681 PHY_CORE_0 ?
22682 RADIO_MIMO_CORESEL_CORE1 :
22683 RADIO_MIMO_CORESEL_CORE2,
22684 NPHY_RAIL_I, NPHY_RSSI_SEL_NB);
22685 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
22686 core ==
22687 PHY_CORE_0 ?
22688 RADIO_MIMO_CORESEL_CORE1 :
22689 RADIO_MIMO_CORESEL_CORE2,
22690 NPHY_RAIL_Q, NPHY_RSSI_SEL_NB);
22691
22692 for (vcm = 0; vcm < vcm_level_max; vcm++) {
22693 if (NREV_GE(pi->pubpi.phy_rev, 7))
22694 mod_radio_reg(pi, (core == PHY_CORE_0) ?
22695 RADIO_2057_NB_MASTER_CORE0 :
22696 RADIO_2057_NB_MASTER_CORE1,
22697 RADIO_2057_VCM_MASK, vcm);
22698 else
22699 mod_radio_reg(pi, RADIO_2056_RX_RSSI_MISC |
22700 ((core ==
22701 PHY_CORE_0) ? RADIO_2056_RX0 :
22702 RADIO_2056_RX1),
22703 RADIO_2056_VCM_MASK,
22704 vcm << RADIO_2056_RSSI_VCM_SHIFT);
22705
22706 wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_NB,
22707 &poll_results[vcm][0],
22708 NPHY_RSSICAL_NPOLL);
22709 }
22710
22711 for (result_idx = 0; result_idx < 4; result_idx++) {
22712 if ((core == result_idx / 2) &&
22713 (result_idx % 2 == 0)) {
22714
22715 min_d = NPHY_RSSICAL_MAXD;
22716 min_vcm = 0;
22717 min_poll =
22718 NPHY_RSSICAL_MAXREAD *
22719 NPHY_RSSICAL_NPOLL + 1;
22720 for (vcm = 0; vcm < vcm_level_max; vcm++) {
22721 curr_d =
22722 poll_results[vcm][result_idx] *
22723 poll_results[vcm][result_idx] +
22724 poll_results[vcm][result_idx +
22725 1] *
22726 poll_results[vcm][result_idx +
22727 1];
22728 if (curr_d < min_d) {
22729 min_d = curr_d;
22730 min_vcm = vcm;
22731 }
22732 if (poll_results[vcm][result_idx] <
22733 min_poll)
22734 min_poll =
22735 poll_results[vcm]
22736 [result_idx];
22737 }
22738 vcm_final = min_vcm;
22739 poll_results_min[result_idx] = min_poll;
22740 }
22741 }
22742
22743 if (NREV_GE(pi->pubpi.phy_rev, 7))
22744 mod_radio_reg(pi, (core == PHY_CORE_0) ?
22745 RADIO_2057_NB_MASTER_CORE0 :
22746 RADIO_2057_NB_MASTER_CORE1,
22747 RADIO_2057_VCM_MASK, vcm_final);
22748 else
22749 mod_radio_reg(pi, RADIO_2056_RX_RSSI_MISC |
22750 ((core ==
22751 PHY_CORE_0) ? RADIO_2056_RX0 :
22752 RADIO_2056_RX1), RADIO_2056_VCM_MASK,
22753 vcm_final << RADIO_2056_RSSI_VCM_SHIFT);
22754
22755 for (result_idx = 0; result_idx < 4; result_idx++) {
22756 if (core == result_idx / 2) {
22757 fine_digital_offset[result_idx] =
22758 (NPHY_RSSICAL_NB_TARGET *
22759 NPHY_RSSICAL_NPOLL) -
22760 poll_results[vcm_final][result_idx];
22761 if (fine_digital_offset[result_idx] < 0) {
22762 fine_digital_offset[result_idx] =
22763 abs(fine_digital_offset
22764 [result_idx]);
22765 fine_digital_offset[result_idx] +=
22766 (NPHY_RSSICAL_NPOLL / 2);
22767 fine_digital_offset[result_idx] /=
22768 NPHY_RSSICAL_NPOLL;
22769 fine_digital_offset[result_idx] =
22770 -fine_digital_offset[
22771 result_idx];
22772 } else {
22773 fine_digital_offset[result_idx] +=
22774 (NPHY_RSSICAL_NPOLL / 2);
22775 fine_digital_offset[result_idx] /=
22776 NPHY_RSSICAL_NPOLL;
22777 }
22778
22779 if (poll_results_min[result_idx] ==
22780 NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL)
22781 fine_digital_offset[result_idx] =
22782 (NPHY_RSSICAL_NB_TARGET -
22783 NPHY_RSSICAL_MAXREAD - 1);
22784
22785 wlc_phy_scale_offset_rssi_nphy(
22786 pi, 0x0,
22787 (s8)
22788 fine_digital_offset
22789 [result_idx],
22790 (result_idx / 2 == 0) ?
22791 RADIO_MIMO_CORESEL_CORE1 :
22792 RADIO_MIMO_CORESEL_CORE2,
22793 (result_idx % 2 == 0) ?
22794 NPHY_RAIL_I : NPHY_RAIL_Q,
22795 NPHY_RSSI_SEL_NB);
22796 }
22797 }
22798
22799 }
22800
22801 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
22802
22803 if ((rxcore_state & (1 << core)) == 0)
22804 continue;
22805
22806 for (wb_cnt = 0; wb_cnt < 2; wb_cnt++) {
22807 if (wb_cnt == 0) {
22808 rssi_type = NPHY_RSSI_SEL_W1;
22809 target_code = NPHY_RSSICAL_W1_TARGET_REV3;
22810 } else {
22811 rssi_type = NPHY_RSSI_SEL_W2;
22812 target_code = NPHY_RSSICAL_W2_TARGET_REV3;
22813 }
22814
22815 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
22816 core ==
22817 PHY_CORE_0 ?
22818 RADIO_MIMO_CORESEL_CORE1
22819 :
22820 RADIO_MIMO_CORESEL_CORE2,
22821 NPHY_RAIL_I, rssi_type);
22822 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
22823 core ==
22824 PHY_CORE_0 ?
22825 RADIO_MIMO_CORESEL_CORE1
22826 :
22827 RADIO_MIMO_CORESEL_CORE2,
22828 NPHY_RAIL_Q, rssi_type);
22829
22830 wlc_phy_poll_rssi_nphy(pi, rssi_type, poll_result_core,
22831 NPHY_RSSICAL_NPOLL);
22832
22833 for (result_idx = 0; result_idx < 4; result_idx++) {
22834 if (core == result_idx / 2) {
22835 fine_digital_offset[result_idx] =
22836 (target_code *
22837 NPHY_RSSICAL_NPOLL) -
22838 poll_result_core[result_idx];
22839 if (fine_digital_offset[result_idx] <
22840 0) {
22841 fine_digital_offset[result_idx]
22842 = abs(
22843 fine_digital_offset
22844 [result_idx]);
22845 fine_digital_offset[result_idx]
22846 += (NPHY_RSSICAL_NPOLL
22847 / 2);
22848 fine_digital_offset[result_idx]
22849 /= NPHY_RSSICAL_NPOLL;
22850 fine_digital_offset[result_idx]
22851 = -fine_digital_offset
22852 [result_idx];
22853 } else {
22854 fine_digital_offset[result_idx]
22855 += (NPHY_RSSICAL_NPOLL
22856 / 2);
22857 fine_digital_offset[result_idx]
22858 /= NPHY_RSSICAL_NPOLL;
22859 }
22860
22861 wlc_phy_scale_offset_rssi_nphy(
22862 pi, 0x0,
22863 (s8)
22864 fine_digital_offset
22865 [core *
22866 2],
22867 (core == PHY_CORE_0) ?
22868 RADIO_MIMO_CORESEL_CORE1 :
22869 RADIO_MIMO_CORESEL_CORE2,
22870 (result_idx % 2 == 0) ?
22871 NPHY_RAIL_I :
22872 NPHY_RAIL_Q,
22873 rssi_type);
22874 }
22875 }
22876
22877 }
22878 }
22879
22880 write_phy_reg(pi, 0x91, NPHY_Rfctrlintc1_save);
22881 write_phy_reg(pi, 0x92, NPHY_Rfctrlintc2_save);
22882
22883 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
22884
22885 mod_phy_reg(pi, 0xe7, (0x1 << 0), 1 << 0);
22886 mod_phy_reg(pi, 0x78, (0x1 << 0), 1 << 0);
22887 mod_phy_reg(pi, 0xe7, (0x1 << 0), 0);
22888
22889 mod_phy_reg(pi, 0xec, (0x1 << 0), 1 << 0);
22890 mod_phy_reg(pi, 0x78, (0x1 << 1), 1 << 1);
22891 mod_phy_reg(pi, 0xec, (0x1 << 0), 0);
22892
22893 write_phy_reg(pi, 0x8f, NPHY_AfectrlOverride1_save);
22894 write_phy_reg(pi, 0xa5, NPHY_AfectrlOverride2_save);
22895 write_phy_reg(pi, 0xa6, NPHY_AfectrlCore1_save);
22896 write_phy_reg(pi, 0xa7, NPHY_AfectrlCore2_save);
22897 write_phy_reg(pi, 0xe7, NPHY_RfctrlOverride0_save);
22898 write_phy_reg(pi, 0xec, NPHY_RfctrlOverride1_save);
22899 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22900 write_phy_reg(pi, 0x342, NPHY_REV7_RfctrlOverride3_save);
22901 write_phy_reg(pi, 0x343, NPHY_REV7_RfctrlOverride4_save);
22902 write_phy_reg(pi, 0x346, NPHY_REV7_RfctrlOverride5_save);
22903 write_phy_reg(pi, 0x347, NPHY_REV7_RfctrlOverride6_save);
22904 }
22905 write_phy_reg(pi, 0xe5, NPHY_RfctrlOverrideAux0_save);
22906 write_phy_reg(pi, 0xe6, NPHY_RfctrlOverrideAux1_save);
22907 write_phy_reg(pi, 0x78, NPHY_RfctrlCmd_save);
22908 write_phy_reg(pi, 0xf9, NPHY_RfctrlMiscReg1_save);
22909 write_phy_reg(pi, 0xfb, NPHY_RfctrlMiscReg2_save);
22910 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22911 write_phy_reg(pi, 0x340, NPHY_REV7_RfctrlMiscReg3_save);
22912 write_phy_reg(pi, 0x341, NPHY_REV7_RfctrlMiscReg4_save);
22913 write_phy_reg(pi, 0x344, NPHY_REV7_RfctrlMiscReg5_save);
22914 write_phy_reg(pi, 0x345, NPHY_REV7_RfctrlMiscReg6_save);
22915 }
22916 write_phy_reg(pi, 0x7a, NPHY_RfctrlRSSIOTHERS1_save);
22917 write_phy_reg(pi, 0x7d, NPHY_RfctrlRSSIOTHERS2_save);
22918
22919 if (CHSPEC_IS2G(pi->radio_chanspec)) {
22920 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22921 pi->rssical_cache.rssical_radio_regs_2G[0] =
22922 read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
22923 pi->rssical_cache.rssical_radio_regs_2G[1] =
22924 read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
22925 } else {
22926 pi->rssical_cache.rssical_radio_regs_2G[0] =
22927 read_radio_reg(pi,
22928 RADIO_2056_RX_RSSI_MISC |
22929 RADIO_2056_RX0);
22930 pi->rssical_cache.rssical_radio_regs_2G[1] =
22931 read_radio_reg(pi,
22932 RADIO_2056_RX_RSSI_MISC |
22933 RADIO_2056_RX1);
22934 }
22935
22936 pi->rssical_cache.rssical_phyregs_2G[0] =
22937 read_phy_reg(pi, 0x1a6);
22938 pi->rssical_cache.rssical_phyregs_2G[1] =
22939 read_phy_reg(pi, 0x1ac);
22940 pi->rssical_cache.rssical_phyregs_2G[2] =
22941 read_phy_reg(pi, 0x1b2);
22942 pi->rssical_cache.rssical_phyregs_2G[3] =
22943 read_phy_reg(pi, 0x1b8);
22944 pi->rssical_cache.rssical_phyregs_2G[4] =
22945 read_phy_reg(pi, 0x1a4);
22946 pi->rssical_cache.rssical_phyregs_2G[5] =
22947 read_phy_reg(pi, 0x1aa);
22948 pi->rssical_cache.rssical_phyregs_2G[6] =
22949 read_phy_reg(pi, 0x1b0);
22950 pi->rssical_cache.rssical_phyregs_2G[7] =
22951 read_phy_reg(pi, 0x1b6);
22952 pi->rssical_cache.rssical_phyregs_2G[8] =
22953 read_phy_reg(pi, 0x1a5);
22954 pi->rssical_cache.rssical_phyregs_2G[9] =
22955 read_phy_reg(pi, 0x1ab);
22956 pi->rssical_cache.rssical_phyregs_2G[10] =
22957 read_phy_reg(pi, 0x1b1);
22958 pi->rssical_cache.rssical_phyregs_2G[11] =
22959 read_phy_reg(pi, 0x1b7);
22960
22961 pi->nphy_rssical_chanspec_2G = pi->radio_chanspec;
22962 } else {
22963 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
22964 pi->rssical_cache.rssical_radio_regs_5G[0] =
22965 read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
22966 pi->rssical_cache.rssical_radio_regs_5G[1] =
22967 read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
22968 } else {
22969 pi->rssical_cache.rssical_radio_regs_5G[0] =
22970 read_radio_reg(pi,
22971 RADIO_2056_RX_RSSI_MISC |
22972 RADIO_2056_RX0);
22973 pi->rssical_cache.rssical_radio_regs_5G[1] =
22974 read_radio_reg(pi,
22975 RADIO_2056_RX_RSSI_MISC |
22976 RADIO_2056_RX1);
22977 }
22978
22979 pi->rssical_cache.rssical_phyregs_5G[0] =
22980 read_phy_reg(pi, 0x1a6);
22981 pi->rssical_cache.rssical_phyregs_5G[1] =
22982 read_phy_reg(pi, 0x1ac);
22983 pi->rssical_cache.rssical_phyregs_5G[2] =
22984 read_phy_reg(pi, 0x1b2);
22985 pi->rssical_cache.rssical_phyregs_5G[3] =
22986 read_phy_reg(pi, 0x1b8);
22987 pi->rssical_cache.rssical_phyregs_5G[4] =
22988 read_phy_reg(pi, 0x1a4);
22989 pi->rssical_cache.rssical_phyregs_5G[5] =
22990 read_phy_reg(pi, 0x1aa);
22991 pi->rssical_cache.rssical_phyregs_5G[6] =
22992 read_phy_reg(pi, 0x1b0);
22993 pi->rssical_cache.rssical_phyregs_5G[7] =
22994 read_phy_reg(pi, 0x1b6);
22995 pi->rssical_cache.rssical_phyregs_5G[8] =
22996 read_phy_reg(pi, 0x1a5);
22997 pi->rssical_cache.rssical_phyregs_5G[9] =
22998 read_phy_reg(pi, 0x1ab);
22999 pi->rssical_cache.rssical_phyregs_5G[10] =
23000 read_phy_reg(pi, 0x1b1);
23001 pi->rssical_cache.rssical_phyregs_5G[11] =
23002 read_phy_reg(pi, 0x1b7);
23003
23004 pi->nphy_rssical_chanspec_5G = pi->radio_chanspec;
23005 }
23006
23007 wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
23008 wlc_phy_clip_det_nphy(pi, 1, clip_state);
23009}
23010
23011static void wlc_phy_rssi_cal_nphy_rev2(struct brcms_phy *pi, u8 rssi_type)
23012{
23013 s32 target_code;
23014 u16 classif_state;
23015 u16 clip_state[2];
23016 u16 rssi_ctrl_state[2], pd_state[2];
23017 u16 rfctrlintc_state[2], rfpdcorerxtx_state[2];
23018 u16 rfctrlintc_override_val;
23019 u16 clip_off[] = { 0xffff, 0xffff };
23020 u16 rf_pd_val, pd_mask, rssi_ctrl_mask;
23021 u8 vcm, min_vcm, vcm_tmp[4];
23022 u8 vcm_final[4] = { 0, 0, 0, 0 };
23023 u8 result_idx, ctr;
23024 s32 poll_results[4][4] = {
23025 {0, 0, 0, 0},
23026 {0, 0, 0, 0},
23027 {0, 0, 0, 0},
23028 {0, 0, 0, 0}
23029 };
23030 s32 poll_miniq[4][2] = {
23031 {0, 0},
23032 {0, 0},
23033 {0, 0},
23034 {0, 0}
23035 };
23036 s32 min_d, curr_d;
23037 s32 fine_digital_offset[4];
23038 s32 poll_results_min[4] = { 0, 0, 0, 0 };
23039 s32 min_poll;
23040
23041 switch (rssi_type) {
23042 case NPHY_RSSI_SEL_NB:
23043 target_code = NPHY_RSSICAL_NB_TARGET;
23044 break;
23045 case NPHY_RSSI_SEL_W1:
23046 target_code = NPHY_RSSICAL_W1_TARGET;
23047 break;
23048 case NPHY_RSSI_SEL_W2:
23049 target_code = NPHY_RSSICAL_W2_TARGET;
23050 break;
23051 default:
23052 return;
23053 break;
23054 }
23055
23056 classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
23057 wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
23058 wlc_phy_clip_det_nphy(pi, 0, clip_state);
23059 wlc_phy_clip_det_nphy(pi, 1, clip_off);
23060
23061 rf_pd_val = (rssi_type == NPHY_RSSI_SEL_NB) ? 0x6 : 0x4;
23062 rfctrlintc_override_val =
23063 CHSPEC_IS5G(pi->radio_chanspec) ? 0x140 : 0x110;
23064
23065 rfctrlintc_state[0] = read_phy_reg(pi, 0x91);
23066 rfpdcorerxtx_state[0] = read_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX);
23067 write_phy_reg(pi, 0x91, rfctrlintc_override_val);
23068 write_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX, rf_pd_val);
23069
23070 rfctrlintc_state[1] = read_phy_reg(pi, 0x92);
23071 rfpdcorerxtx_state[1] = read_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX);
23072 write_phy_reg(pi, 0x92, rfctrlintc_override_val);
23073 write_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX, rf_pd_val);
23074
23075 pd_mask = RADIO_2055_NBRSSI_PD | RADIO_2055_WBRSSI_G1_PD |
23076 RADIO_2055_WBRSSI_G2_PD;
23077 pd_state[0] =
23078 read_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC) & pd_mask;
23079 pd_state[1] =
23080 read_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC) & pd_mask;
23081 mod_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC, pd_mask, 0);
23082 mod_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC, pd_mask, 0);
23083 rssi_ctrl_mask = RADIO_2055_NBRSSI_SEL | RADIO_2055_WBRSSI_G1_SEL |
23084 RADIO_2055_WBRSSI_G2_SEL;
23085 rssi_ctrl_state[0] =
23086 read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE1) & rssi_ctrl_mask;
23087 rssi_ctrl_state[1] =
23088 read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE2) & rssi_ctrl_mask;
23089 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_ALLRX, rssi_type);
23090
23091 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0, RADIO_MIMO_CORESEL_ALLRX,
23092 NPHY_RAIL_I, rssi_type);
23093 wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0, RADIO_MIMO_CORESEL_ALLRX,
23094 NPHY_RAIL_Q, rssi_type);
23095
23096 for (vcm = 0; vcm < 4; vcm++) {
23097
23098 vcm_tmp[0] = vcm_tmp[1] = vcm_tmp[2] = vcm_tmp[3] = vcm;
23099 if (rssi_type != NPHY_RSSI_SEL_W2)
23100 wlc_phy_set_rssi_2055_vcm(pi, rssi_type, vcm_tmp);
23101
23102 wlc_phy_poll_rssi_nphy(pi, rssi_type, &poll_results[vcm][0],
23103 NPHY_RSSICAL_NPOLL);
23104
23105 if ((rssi_type == NPHY_RSSI_SEL_W1)
23106 || (rssi_type == NPHY_RSSI_SEL_W2)) {
23107 for (ctr = 0; ctr < 2; ctr++)
23108 poll_miniq[vcm][ctr] =
23109 min(poll_results[vcm][ctr * 2 + 0],
23110 poll_results[vcm][ctr * 2 + 1]);
23111 }
23112 }
23113
23114 for (result_idx = 0; result_idx < 4; result_idx++) {
23115 min_d = NPHY_RSSICAL_MAXD;
23116 min_vcm = 0;
23117 min_poll = NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL + 1;
23118 for (vcm = 0; vcm < 4; vcm++) {
23119 curr_d = abs(((rssi_type == NPHY_RSSI_SEL_NB) ?
23120 poll_results[vcm][result_idx] :
23121 poll_miniq[vcm][result_idx / 2]) -
23122 (target_code * NPHY_RSSICAL_NPOLL));
23123 if (curr_d < min_d) {
23124 min_d = curr_d;
23125 min_vcm = vcm;
23126 }
23127 if (poll_results[vcm][result_idx] < min_poll)
23128 min_poll = poll_results[vcm][result_idx];
23129 }
23130 vcm_final[result_idx] = min_vcm;
23131 poll_results_min[result_idx] = min_poll;
23132 }
23133
23134 if (rssi_type != NPHY_RSSI_SEL_W2)
23135 wlc_phy_set_rssi_2055_vcm(pi, rssi_type, vcm_final);
23136
23137 for (result_idx = 0; result_idx < 4; result_idx++) {
23138 fine_digital_offset[result_idx] =
23139 (target_code * NPHY_RSSICAL_NPOLL) -
23140 poll_results[vcm_final[result_idx]][result_idx];
23141 if (fine_digital_offset[result_idx] < 0) {
23142 fine_digital_offset[result_idx] =
23143 abs(fine_digital_offset[result_idx]);
23144 fine_digital_offset[result_idx] +=
23145 (NPHY_RSSICAL_NPOLL / 2);
23146 fine_digital_offset[result_idx] /= NPHY_RSSICAL_NPOLL;
23147 fine_digital_offset[result_idx] =
23148 -fine_digital_offset[result_idx];
23149 } else {
23150 fine_digital_offset[result_idx] +=
23151 (NPHY_RSSICAL_NPOLL / 2);
23152 fine_digital_offset[result_idx] /= NPHY_RSSICAL_NPOLL;
23153 }
23154
23155 if (poll_results_min[result_idx] ==
23156 NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL)
23157 fine_digital_offset[result_idx] =
23158 (target_code - NPHY_RSSICAL_MAXREAD - 1);
23159
23160 wlc_phy_scale_offset_rssi_nphy(pi, 0x0,
23161 (s8)
23162 fine_digital_offset[result_idx],
23163 (result_idx / 2 ==
23164 0) ? RADIO_MIMO_CORESEL_CORE1 :
23165 RADIO_MIMO_CORESEL_CORE2,
23166 (result_idx % 2 ==
23167 0) ? NPHY_RAIL_I : NPHY_RAIL_Q,
23168 rssi_type);
23169 }
23170
23171 mod_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC, pd_mask, pd_state[0]);
23172 mod_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC, pd_mask, pd_state[1]);
23173 if (rssi_ctrl_state[0] == RADIO_2055_NBRSSI_SEL)
23174 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
23175 NPHY_RSSI_SEL_NB);
23176 else if (rssi_ctrl_state[0] == RADIO_2055_WBRSSI_G1_SEL)
23177 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
23178 NPHY_RSSI_SEL_W1);
23179 else if (rssi_ctrl_state[0] == RADIO_2055_WBRSSI_G2_SEL)
23180 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
23181 NPHY_RSSI_SEL_W2);
23182 else
23183 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
23184 NPHY_RSSI_SEL_W2);
23185 if (rssi_ctrl_state[1] == RADIO_2055_NBRSSI_SEL)
23186 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
23187 NPHY_RSSI_SEL_NB);
23188 else if (rssi_ctrl_state[1] == RADIO_2055_WBRSSI_G1_SEL)
23189 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
23190 NPHY_RSSI_SEL_W1);
23191 else if (rssi_ctrl_state[1] == RADIO_2055_WBRSSI_G2_SEL)
23192 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
23193 NPHY_RSSI_SEL_W2);
23194 else
23195 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
23196 NPHY_RSSI_SEL_W2);
23197
23198 wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_OFF, rssi_type);
23199
23200 write_phy_reg(pi, 0x91, rfctrlintc_state[0]);
23201 write_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX, rfpdcorerxtx_state[0]);
23202 write_phy_reg(pi, 0x92, rfctrlintc_state[1]);
23203 write_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX, rfpdcorerxtx_state[1]);
23204
23205 wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
23206 wlc_phy_clip_det_nphy(pi, 1, clip_state);
23207
23208 wlc_phy_resetcca_nphy(pi);
23209}
23210
23211void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi)
23212{
23213 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
23214 wlc_phy_rssi_cal_nphy_rev3(pi);
23215 } else {
23216 wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_NB);
23217 wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_W1);
23218 wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_W2);
23219 }
23220}
23221
23222int
23223wlc_phy_rssi_compute_nphy(struct brcms_phy *pi, struct d11rxhdr *rxh)
23224{
23225 s16 rxpwr, rxpwr0, rxpwr1;
23226 s16 phyRx0_l, phyRx2_l;
23227
23228 rxpwr = 0;
23229 rxpwr0 = rxh->PhyRxStatus_1 & PRXS1_nphy_PWR0_MASK;
23230 rxpwr1 = (rxh->PhyRxStatus_1 & PRXS1_nphy_PWR1_MASK) >> 8;
23231
23232 if (rxpwr0 > 127)
23233 rxpwr0 -= 256;
23234 if (rxpwr1 > 127)
23235 rxpwr1 -= 256;
23236
23237 phyRx0_l = rxh->PhyRxStatus_0 & 0x00ff;
23238 phyRx2_l = rxh->PhyRxStatus_2 & 0x00ff;
23239 if (phyRx2_l > 127)
23240 phyRx2_l -= 256;
23241
23242 if (((rxpwr0 == 16) || (rxpwr0 == 32))) {
23243 rxpwr0 = rxpwr1;
23244 rxpwr1 = phyRx2_l;
23245 }
23246
23247 if (pi->sh->rssi_mode == RSSI_ANT_MERGE_MAX)
23248 rxpwr = (rxpwr0 > rxpwr1) ? rxpwr0 : rxpwr1;
23249 else if (pi->sh->rssi_mode == RSSI_ANT_MERGE_MIN)
23250 rxpwr = (rxpwr0 < rxpwr1) ? rxpwr0 : rxpwr1;
23251 else if (pi->sh->rssi_mode == RSSI_ANT_MERGE_AVG)
23252 rxpwr = (rxpwr0 + rxpwr1) >> 1;
23253
23254 return rxpwr;
23255}
23256
23257static void
23258wlc_phy_loadsampletable_nphy(struct brcms_phy *pi, struct cordic_iq *tone_buf,
23259 u16 num_samps)
23260{
23261 u16 t;
23262 u32 *data_buf = NULL;
23263
23264 data_buf = kmalloc(sizeof(u32) * num_samps, GFP_ATOMIC);
23265 if (data_buf == NULL)
23266 return;
23267
23268 if (pi->phyhang_avoid)
23269 wlc_phy_stay_in_carriersearch_nphy(pi, true);
23270
23271 for (t = 0; t < num_samps; t++)
23272 data_buf[t] = ((((unsigned int)tone_buf[t].i) & 0x3ff) << 10) |
23273 (((unsigned int)tone_buf[t].q) & 0x3ff);
23274 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SAMPLEPLAY, num_samps, 0, 32,
23275 data_buf);
23276
23277 kfree(data_buf);
23278
23279 if (pi->phyhang_avoid)
23280 wlc_phy_stay_in_carriersearch_nphy(pi, false);
23281}
23282
23283static u16
23284wlc_phy_gen_load_samples_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val,
23285 u8 dac_test_mode)
23286{
23287 u8 phy_bw, is_phybw40;
23288 u16 num_samps, t, spur;
23289 s32 theta = 0, rot = 0;
23290 u32 tbl_len;
23291 struct cordic_iq *tone_buf = NULL;
23292
23293 is_phybw40 = CHSPEC_IS40(pi->radio_chanspec);
23294 phy_bw = (is_phybw40 == 1) ? 40 : 20;
23295 tbl_len = (phy_bw << 3);
23296
23297 if (dac_test_mode == 1) {
23298 spur = read_phy_reg(pi, 0x01);
23299 spur = (spur >> 15) & 1;
23300 phy_bw = (spur == 1) ? 82 : 80;
23301 phy_bw = (is_phybw40 == 1) ? (phy_bw << 1) : phy_bw;
23302
23303 tbl_len = (phy_bw << 1);
23304 }
23305
23306 tone_buf = kmalloc(sizeof(struct cordic_iq) * tbl_len, GFP_ATOMIC);
23307 if (tone_buf == NULL)
23308 return 0;
23309
23310 num_samps = (u16) tbl_len;
23311 rot = ((f_kHz * 36) / phy_bw) / 100;
23312 theta = 0;
23313
23314 for (t = 0; t < num_samps; t++) {
23315
23316 tone_buf[t] = cordic_calc_iq(theta);
23317
23318 theta += rot;
23319
23320 tone_buf[t].q = (s32) FLOAT(tone_buf[t].q * max_val);
23321 tone_buf[t].i = (s32) FLOAT(tone_buf[t].i * max_val);
23322 }
23323
23324 wlc_phy_loadsampletable_nphy(pi, tone_buf, num_samps);
23325
23326 kfree(tone_buf);
23327
23328 return num_samps;
23329}
23330
23331static void
23332wlc_phy_runsamples_nphy(struct brcms_phy *pi, u16 num_samps, u16 loops,
23333 u16 wait, u8 iqmode, u8 dac_test_mode,
23334 bool modify_bbmult)
23335{
23336 u16 bb_mult;
23337 u8 phy_bw, sample_cmd;
23338 u16 orig_RfseqCoreActv;
23339 u16 lpf_bw_ctl_override3, lpf_bw_ctl_override4, lpf_bw_ctl_miscreg3,
23340 lpf_bw_ctl_miscreg4;
23341
23342 if (pi->phyhang_avoid)
23343 wlc_phy_stay_in_carriersearch_nphy(pi, true);
23344
23345 phy_bw = 20;
23346 if (CHSPEC_IS40(pi->radio_chanspec))
23347 phy_bw = 40;
23348
23349 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
23350
23351 lpf_bw_ctl_override3 = read_phy_reg(pi, 0x342) & (0x1 << 7);
23352 lpf_bw_ctl_override4 = read_phy_reg(pi, 0x343) & (0x1 << 7);
23353 if (lpf_bw_ctl_override3 | lpf_bw_ctl_override4) {
23354 lpf_bw_ctl_miscreg3 = read_phy_reg(pi, 0x340) &
23355 (0x7 << 8);
23356 lpf_bw_ctl_miscreg4 = read_phy_reg(pi, 0x341) &
23357 (0x7 << 8);
23358 } else {
23359 wlc_phy_rfctrl_override_nphy_rev7(
23360 pi,
23361 (0x1 << 7),
23362 wlc_phy_read_lpf_bw_ctl_nphy
23363 (pi,
23364 0), 0, 0,
23365 NPHY_REV7_RFCTRLOVERRIDE_ID1);
23366
23367 pi->nphy_sample_play_lpf_bw_ctl_ovr = true;
23368
23369 lpf_bw_ctl_miscreg3 = read_phy_reg(pi, 0x340) &
23370 (0x7 << 8);
23371 lpf_bw_ctl_miscreg4 = read_phy_reg(pi, 0x341) &
23372 (0x7 << 8);
23373 }
23374 }
23375
23376 if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) == 0) {
23377
23378 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
23379 &bb_mult);
23380 pi->nphy_bb_mult_save =
23381 BB_MULT_VALID_MASK | (bb_mult & BB_MULT_MASK);
23382 }
23383
23384 if (modify_bbmult) {
23385 bb_mult = (phy_bw == 20) ? 100 : 71;
23386 bb_mult = (bb_mult << 8) + bb_mult;
23387 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
23388 &bb_mult);
23389 }
23390
23391 if (pi->phyhang_avoid)
23392 wlc_phy_stay_in_carriersearch_nphy(pi, false);
23393
23394 write_phy_reg(pi, 0xc6, num_samps - 1);
23395
23396 if (loops != 0xffff)
23397 write_phy_reg(pi, 0xc4, loops - 1);
23398 else
23399 write_phy_reg(pi, 0xc4, loops);
23400
23401 write_phy_reg(pi, 0xc5, wait);
23402
23403 orig_RfseqCoreActv = read_phy_reg(pi, 0xa1);
23404 or_phy_reg(pi, 0xa1, NPHY_RfseqMode_CoreActv_override);
23405 if (iqmode) {
23406
23407 and_phy_reg(pi, 0xc2, 0x7FFF);
23408
23409 or_phy_reg(pi, 0xc2, 0x8000);
23410 } else {
23411
23412 sample_cmd = (dac_test_mode == 1) ? 0x5 : 0x1;
23413 write_phy_reg(pi, 0xc3, sample_cmd);
23414 }
23415
23416 SPINWAIT(((read_phy_reg(pi, 0xa4) & 0x1) == 1), 1000);
23417
23418 write_phy_reg(pi, 0xa1, orig_RfseqCoreActv);
23419}
23420
23421int
23422wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val,
23423 u8 iqmode, u8 dac_test_mode, bool modify_bbmult)
23424{
23425 u16 num_samps;
23426 u16 loops = 0xffff;
23427 u16 wait = 0;
23428
23429 num_samps = wlc_phy_gen_load_samples_nphy(pi, f_kHz, max_val,
23430 dac_test_mode);
23431 if (num_samps == 0)
23432 return -EBADE;
23433
23434 wlc_phy_runsamples_nphy(pi, num_samps, loops, wait, iqmode,
23435 dac_test_mode, modify_bbmult);
23436
23437 return 0;
23438}
23439
23440void wlc_phy_stopplayback_nphy(struct brcms_phy *pi)
23441{
23442 u16 playback_status;
23443 u16 bb_mult;
23444
23445 if (pi->phyhang_avoid)
23446 wlc_phy_stay_in_carriersearch_nphy(pi, true);
23447
23448 playback_status = read_phy_reg(pi, 0xc7);
23449 if (playback_status & 0x1)
23450 or_phy_reg(pi, 0xc3, NPHY_sampleCmd_STOP);
23451 else if (playback_status & 0x2)
23452 and_phy_reg(pi, 0xc2,
23453 (u16) ~NPHY_iqloCalCmdGctl_IQLO_CAL_EN);
23454
23455 and_phy_reg(pi, 0xc3, (u16) ~(0x1 << 2));
23456
23457 if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) != 0) {
23458
23459 bb_mult = pi->nphy_bb_mult_save & BB_MULT_MASK;
23460 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
23461 &bb_mult);
23462
23463 pi->nphy_bb_mult_save = 0;
23464 }
23465
23466 if (NREV_IS(pi->pubpi.phy_rev, 7) || NREV_GE(pi->pubpi.phy_rev, 8)) {
23467 if (pi->nphy_sample_play_lpf_bw_ctl_ovr) {
23468 wlc_phy_rfctrl_override_nphy_rev7(
23469 pi,
23470 (0x1 << 7),
23471 0, 0, 1,
23472 NPHY_REV7_RFCTRLOVERRIDE_ID1);
23473 pi->nphy_sample_play_lpf_bw_ctl_ovr = false;
23474 }
23475 }
23476
23477 if (pi->phyhang_avoid)
23478 wlc_phy_stay_in_carriersearch_nphy(pi, false);
23479}
23480
23481static u32 *brcms_phy_get_tx_pwrctrl_tbl(struct brcms_phy *pi)
23482{
23483 u32 *tx_pwrctrl_tbl = NULL;
23484 uint phyrev = pi->pubpi.phy_rev;
23485
23486 if (PHY_IPA(pi)) {
23487 tx_pwrctrl_tbl =
23488 wlc_phy_get_ipa_gaintbl_nphy(pi);
23489 } else {
23490 if (CHSPEC_IS5G(pi->radio_chanspec)) {
23491 if (NREV_IS(phyrev, 3))
23492 tx_pwrctrl_tbl = nphy_tpc_5GHz_txgain_rev3;
23493 else if (NREV_IS(phyrev, 4))
23494 tx_pwrctrl_tbl =
23495 (pi->srom_fem5g.extpagain == 3) ?
23496 nphy_tpc_5GHz_txgain_HiPwrEPA :
23497 nphy_tpc_5GHz_txgain_rev4;
23498 else
23499 tx_pwrctrl_tbl = nphy_tpc_5GHz_txgain_rev5;
23500 } else {
23501 if (NREV_GE(phyrev, 7)) {
23502 if (pi->pubpi.radiorev == 3)
23503 tx_pwrctrl_tbl =
23504 nphy_tpc_txgain_epa_2057rev3;
23505 else if (pi->pubpi.radiorev == 5)
23506 tx_pwrctrl_tbl =
23507 nphy_tpc_txgain_epa_2057rev5;
23508 } else {
23509 if (NREV_GE(phyrev, 5) &&
23510 (pi->srom_fem2g.extpagain == 3))
23511 tx_pwrctrl_tbl =
23512 nphy_tpc_txgain_HiPwrEPA;
23513 else
23514 tx_pwrctrl_tbl =
23515 nphy_tpc_txgain_rev3;
23516 }
23517 }
23518 }
23519 return tx_pwrctrl_tbl;
23520}
23521
23522struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi)
23523{
23524 u16 base_idx[2], curr_gain[2];
23525 u8 core_no;
23526 struct nphy_txgains target_gain;
23527 u32 *tx_pwrctrl_tbl = NULL;
23528
23529 if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
23530 if (pi->phyhang_avoid)
23531 wlc_phy_stay_in_carriersearch_nphy(pi, true);
23532
23533 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
23534 curr_gain);
23535
23536 if (pi->phyhang_avoid)
23537 wlc_phy_stay_in_carriersearch_nphy(pi, false);
23538
23539 for (core_no = 0; core_no < 2; core_no++) {
23540 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
23541 target_gain.ipa[core_no] =
23542 curr_gain[core_no] & 0x0007;
23543 target_gain.pad[core_no] =
23544 ((curr_gain[core_no] & 0x00F8) >> 3);
23545 target_gain.pga[core_no] =
23546 ((curr_gain[core_no] & 0x0F00) >> 8);
23547 target_gain.txgm[core_no] =
23548 ((curr_gain[core_no] & 0x7000) >> 12);
23549 target_gain.txlpf[core_no] =
23550 ((curr_gain[core_no] & 0x8000) >> 15);
23551 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
23552 target_gain.ipa[core_no] =
23553 curr_gain[core_no] & 0x000F;
23554 target_gain.pad[core_no] =
23555 ((curr_gain[core_no] & 0x00F0) >> 4);
23556 target_gain.pga[core_no] =
23557 ((curr_gain[core_no] & 0x0F00) >> 8);
23558 target_gain.txgm[core_no] =
23559 ((curr_gain[core_no] & 0x7000) >> 12);
23560 } else {
23561 target_gain.ipa[core_no] =
23562 curr_gain[core_no] & 0x0003;
23563 target_gain.pad[core_no] =
23564 ((curr_gain[core_no] & 0x000C) >> 2);
23565 target_gain.pga[core_no] =
23566 ((curr_gain[core_no] & 0x0070) >> 4);
23567 target_gain.txgm[core_no] =
23568 ((curr_gain[core_no] & 0x0380) >> 7);
23569 }
23570 }
23571 } else {
23572 uint phyrev = pi->pubpi.phy_rev;
23573
23574 base_idx[0] = (read_phy_reg(pi, 0x1ed) >> 8) & 0x7f;
23575 base_idx[1] = (read_phy_reg(pi, 0x1ee) >> 8) & 0x7f;
23576 for (core_no = 0; core_no < 2; core_no++) {
23577 if (NREV_GE(phyrev, 3)) {
23578 tx_pwrctrl_tbl =
23579 brcms_phy_get_tx_pwrctrl_tbl(pi);
23580 if (NREV_GE(phyrev, 7)) {
23581 target_gain.ipa[core_no] =
23582 (tx_pwrctrl_tbl
23583 [base_idx[core_no]]
23584 >> 16) & 0x7;
23585 target_gain.pad[core_no] =
23586 (tx_pwrctrl_tbl
23587 [base_idx[core_no]]
23588 >> 19) & 0x1f;
23589 target_gain.pga[core_no] =
23590 (tx_pwrctrl_tbl
23591 [base_idx[core_no]]
23592 >> 24) & 0xf;
23593 target_gain.txgm[core_no] =
23594 (tx_pwrctrl_tbl
23595 [base_idx[core_no]]
23596 >> 28) & 0x7;
23597 target_gain.txlpf[core_no] =
23598 (tx_pwrctrl_tbl
23599 [base_idx[core_no]]
23600 >> 31) & 0x1;
23601 } else {
23602 target_gain.ipa[core_no] =
23603 (tx_pwrctrl_tbl
23604 [base_idx[core_no]]
23605 >> 16) & 0xf;
23606 target_gain.pad[core_no] =
23607 (tx_pwrctrl_tbl
23608 [base_idx[core_no]]
23609 >> 20) & 0xf;
23610 target_gain.pga[core_no] =
23611 (tx_pwrctrl_tbl
23612 [base_idx[core_no]]
23613 >> 24) & 0xf;
23614 target_gain.txgm[core_no] =
23615 (tx_pwrctrl_tbl
23616 [base_idx[core_no]]
23617 >> 28) & 0x7;
23618 }
23619 } else {
23620 target_gain.ipa[core_no] =
23621 (nphy_tpc_txgain[base_idx[core_no]] >>
23622 16) & 0x3;
23623 target_gain.pad[core_no] =
23624 (nphy_tpc_txgain[base_idx[core_no]] >>
23625 18) & 0x3;
23626 target_gain.pga[core_no] =
23627 (nphy_tpc_txgain[base_idx[core_no]] >>
23628 20) & 0x7;
23629 target_gain.txgm[core_no] =
23630 (nphy_tpc_txgain[base_idx[core_no]] >>
23631 23) & 0x7;
23632 }
23633 }
23634 }
23635
23636 return target_gain;
23637}
23638
23639static void
23640wlc_phy_iqcal_gainparams_nphy(struct brcms_phy *pi, u16 core_no,
23641 struct nphy_txgains target_gain,
23642 struct nphy_iqcal_params *params)
23643{
23644 u8 k;
23645 int idx;
23646 u16 gain_index;
23647 u8 band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0);
23648
23649 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
23650 if (NREV_GE(pi->pubpi.phy_rev, 7))
23651 params->txlpf = target_gain.txlpf[core_no];
23652
23653 params->txgm = target_gain.txgm[core_no];
23654 params->pga = target_gain.pga[core_no];
23655 params->pad = target_gain.pad[core_no];
23656 params->ipa = target_gain.ipa[core_no];
23657 if (NREV_GE(pi->pubpi.phy_rev, 7))
23658 params->cal_gain =
23659 ((params->txlpf << 15) | (params->txgm << 12) |
23660 (params->pga << 8) |
23661 (params->pad << 3) | (params->ipa));
23662 else
23663 params->cal_gain =
23664 ((params->txgm << 12) | (params->pga << 8) |
23665 (params->pad << 4) | (params->ipa));
23666
23667 params->ncorr[0] = 0x79;
23668 params->ncorr[1] = 0x79;
23669 params->ncorr[2] = 0x79;
23670 params->ncorr[3] = 0x79;
23671 params->ncorr[4] = 0x79;
23672 } else {
23673
23674 gain_index = ((target_gain.pad[core_no] << 0) |
23675 (target_gain.pga[core_no] << 4) |
23676 (target_gain.txgm[core_no] << 8));
23677
23678 idx = -1;
23679 for (k = 0; k < NPHY_IQCAL_NUMGAINS; k++) {
23680 if (tbl_iqcal_gainparams_nphy[band_idx][k][0] ==
23681 gain_index) {
23682 idx = k;
23683 break;
23684 }
23685 }
23686
23687 params->txgm = tbl_iqcal_gainparams_nphy[band_idx][k][1];
23688 params->pga = tbl_iqcal_gainparams_nphy[band_idx][k][2];
23689 params->pad = tbl_iqcal_gainparams_nphy[band_idx][k][3];
23690 params->cal_gain = ((params->txgm << 7) | (params->pga << 4) |
23691 (params->pad << 2));
23692 params->ncorr[0] = tbl_iqcal_gainparams_nphy[band_idx][k][4];
23693 params->ncorr[1] = tbl_iqcal_gainparams_nphy[band_idx][k][5];
23694 params->ncorr[2] = tbl_iqcal_gainparams_nphy[band_idx][k][6];
23695 params->ncorr[3] = tbl_iqcal_gainparams_nphy[band_idx][k][7];
23696 }
23697}
23698
23699static void wlc_phy_txcal_radio_setup_nphy(struct brcms_phy *pi)
23700{
23701 u16 jtag_core, core;
23702
23703 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
23704
23705 for (core = 0; core <= 1; core++) {
23706
23707 pi->tx_rx_cal_radio_saveregs[(core * 11) + 0] =
23708 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23709 TX_SSI_MASTER);
23710
23711 pi->tx_rx_cal_radio_saveregs[(core * 11) + 1] =
23712 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23713 IQCAL_VCM_HG);
23714
23715 pi->tx_rx_cal_radio_saveregs[(core * 11) + 2] =
23716 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23717 IQCAL_IDAC);
23718
23719 pi->tx_rx_cal_radio_saveregs[(core * 11) + 3] =
23720 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23721 TSSI_VCM);
23722
23723 pi->tx_rx_cal_radio_saveregs[(core * 11) + 4] = 0;
23724
23725 pi->tx_rx_cal_radio_saveregs[(core * 11) + 5] =
23726 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23727 TX_SSI_MUX);
23728
23729 if (pi->pubpi.radiorev != 5)
23730 pi->tx_rx_cal_radio_saveregs[(core * 11) + 6] =
23731 READ_RADIO_REG3(pi, RADIO_2057, TX,
23732 core,
23733 TSSIA);
23734
23735 pi->tx_rx_cal_radio_saveregs[(core * 11) + 7] =
23736 READ_RADIO_REG3(pi, RADIO_2057, TX, core, TSSIG);
23737
23738 pi->tx_rx_cal_radio_saveregs[(core * 11) + 8] =
23739 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
23740 TSSI_MISC1);
23741
23742 if (CHSPEC_IS5G(pi->radio_chanspec)) {
23743 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23744 TX_SSI_MASTER, 0x0a);
23745 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23746 IQCAL_VCM_HG, 0x43);
23747 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23748 IQCAL_IDAC, 0x55);
23749 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23750 TSSI_VCM, 0x00);
23751 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23752 TSSIG, 0x00);
23753 if (pi->use_int_tx_iqlo_cal_nphy) {
23754 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
23755 core, TX_SSI_MUX, 0x4);
23756 if (!(pi->
23757 internal_tx_iqlo_cal_tapoff_intpa_nphy))
23758 WRITE_RADIO_REG3(pi, RADIO_2057,
23759 TX, core,
23760 TSSIA, 0x31);
23761 else
23762 WRITE_RADIO_REG3(pi, RADIO_2057,
23763 TX, core,
23764 TSSIA, 0x21);
23765 }
23766 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23767 TSSI_MISC1, 0x00);
23768 } else {
23769 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23770 TX_SSI_MASTER, 0x06);
23771 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23772 IQCAL_VCM_HG, 0x43);
23773 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23774 IQCAL_IDAC, 0x55);
23775 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23776 TSSI_VCM, 0x00);
23777
23778 if (pi->pubpi.radiorev != 5)
23779 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
23780 core, TSSIA, 0x00);
23781 if (pi->use_int_tx_iqlo_cal_nphy) {
23782 WRITE_RADIO_REG3(pi, RADIO_2057, TX,
23783 core, TX_SSI_MUX,
23784 0x06);
23785 if (!(pi->
23786 internal_tx_iqlo_cal_tapoff_intpa_nphy))
23787 WRITE_RADIO_REG3(pi, RADIO_2057,
23788 TX, core,
23789 TSSIG, 0x31);
23790 else
23791 WRITE_RADIO_REG3(pi, RADIO_2057,
23792 TX, core,
23793 TSSIG, 0x21);
23794 }
23795 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
23796 TSSI_MISC1, 0x00);
23797 }
23798 }
23799 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
23800
23801 for (core = 0; core <= 1; core++) {
23802 jtag_core =
23803 (core ==
23804 PHY_CORE_0) ? RADIO_2056_TX0 : RADIO_2056_TX1;
23805
23806 pi->tx_rx_cal_radio_saveregs[(core * 11) + 0] =
23807 read_radio_reg(pi,
23808 RADIO_2056_TX_TX_SSI_MASTER |
23809 jtag_core);
23810
23811 pi->tx_rx_cal_radio_saveregs[(core * 11) + 1] =
23812 read_radio_reg(pi,
23813 RADIO_2056_TX_IQCAL_VCM_HG |
23814 jtag_core);
23815
23816 pi->tx_rx_cal_radio_saveregs[(core * 11) + 2] =
23817 read_radio_reg(pi,
23818 RADIO_2056_TX_IQCAL_IDAC |
23819 jtag_core);
23820
23821 pi->tx_rx_cal_radio_saveregs[(core * 11) + 3] =
23822 read_radio_reg(
23823 pi,
23824 RADIO_2056_TX_TSSI_VCM |
23825 jtag_core);
23826
23827 pi->tx_rx_cal_radio_saveregs[(core * 11) + 4] =
23828 read_radio_reg(pi,
23829 RADIO_2056_TX_TX_AMP_DET |
23830 jtag_core);
23831
23832 pi->tx_rx_cal_radio_saveregs[(core * 11) + 5] =
23833 read_radio_reg(pi,
23834 RADIO_2056_TX_TX_SSI_MUX |
23835 jtag_core);
23836
23837 pi->tx_rx_cal_radio_saveregs[(core * 11) + 6] =
23838 read_radio_reg(pi,
23839 RADIO_2056_TX_TSSIA | jtag_core);
23840
23841 pi->tx_rx_cal_radio_saveregs[(core * 11) + 7] =
23842 read_radio_reg(pi,
23843 RADIO_2056_TX_TSSIG | jtag_core);
23844
23845 pi->tx_rx_cal_radio_saveregs[(core * 11) + 8] =
23846 read_radio_reg(pi,
23847 RADIO_2056_TX_TSSI_MISC1 |
23848 jtag_core);
23849
23850 pi->tx_rx_cal_radio_saveregs[(core * 11) + 9] =
23851 read_radio_reg(pi,
23852 RADIO_2056_TX_TSSI_MISC2 |
23853 jtag_core);
23854
23855 pi->tx_rx_cal_radio_saveregs[(core * 11) + 10] =
23856 read_radio_reg(pi,
23857 RADIO_2056_TX_TSSI_MISC3 |
23858 jtag_core);
23859
23860 if (CHSPEC_IS5G(pi->radio_chanspec)) {
23861 write_radio_reg(pi,
23862 RADIO_2056_TX_TX_SSI_MASTER |
23863 jtag_core, 0x0a);
23864 write_radio_reg(pi,
23865 RADIO_2056_TX_IQCAL_VCM_HG |
23866 jtag_core, 0x40);
23867 write_radio_reg(pi,
23868 RADIO_2056_TX_IQCAL_IDAC |
23869 jtag_core, 0x55);
23870 write_radio_reg(pi,
23871 RADIO_2056_TX_TSSI_VCM |
23872 jtag_core, 0x00);
23873 write_radio_reg(pi,
23874 RADIO_2056_TX_TX_AMP_DET |
23875 jtag_core, 0x00);
23876
23877 if (PHY_IPA(pi)) {
23878 write_radio_reg(
23879 pi,
23880 RADIO_2056_TX_TX_SSI_MUX
23881 | jtag_core, 0x4);
23882 write_radio_reg(pi,
23883 RADIO_2056_TX_TSSIA |
23884 jtag_core, 0x1);
23885 } else {
23886 write_radio_reg(
23887 pi,
23888 RADIO_2056_TX_TX_SSI_MUX
23889 | jtag_core, 0x00);
23890 write_radio_reg(pi,
23891 RADIO_2056_TX_TSSIA |
23892 jtag_core, 0x2f);
23893 }
23894 write_radio_reg(pi,
23895 RADIO_2056_TX_TSSIG | jtag_core,
23896 0x00);
23897 write_radio_reg(pi,
23898 RADIO_2056_TX_TSSI_MISC1 |
23899 jtag_core, 0x00);
23900
23901 write_radio_reg(pi,
23902 RADIO_2056_TX_TSSI_MISC2 |
23903 jtag_core, 0x00);
23904 write_radio_reg(pi,
23905 RADIO_2056_TX_TSSI_MISC3 |
23906 jtag_core, 0x00);
23907 } else {
23908 write_radio_reg(pi,
23909 RADIO_2056_TX_TX_SSI_MASTER |
23910 jtag_core, 0x06);
23911 write_radio_reg(pi,
23912 RADIO_2056_TX_IQCAL_VCM_HG |
23913 jtag_core, 0x40);
23914 write_radio_reg(pi,
23915 RADIO_2056_TX_IQCAL_IDAC |
23916 jtag_core, 0x55);
23917 write_radio_reg(pi,
23918 RADIO_2056_TX_TSSI_VCM |
23919 jtag_core, 0x00);
23920 write_radio_reg(pi,
23921 RADIO_2056_TX_TX_AMP_DET |
23922 jtag_core, 0x00);
23923 write_radio_reg(pi,
23924 RADIO_2056_TX_TSSIA | jtag_core,
23925 0x00);
23926
23927 if (PHY_IPA(pi)) {
23928
23929 write_radio_reg(
23930 pi,
23931 RADIO_2056_TX_TX_SSI_MUX
23932 | jtag_core, 0x06);
23933 if (NREV_LT(pi->pubpi.phy_rev, 5))
23934 write_radio_reg(
23935 pi,
23936 RADIO_2056_TX_TSSIG
23937 | jtag_core,
23938 0x11);
23939 else
23940 write_radio_reg(
23941 pi,
23942 RADIO_2056_TX_TSSIG
23943 | jtag_core,
23944 0x1);
23945 } else {
23946 write_radio_reg(
23947 pi,
23948 RADIO_2056_TX_TX_SSI_MUX
23949 | jtag_core, 0x00);
23950 write_radio_reg(pi,
23951 RADIO_2056_TX_TSSIG |
23952 jtag_core, 0x20);
23953 }
23954
23955 write_radio_reg(pi,
23956 RADIO_2056_TX_TSSI_MISC1 |
23957 jtag_core, 0x00);
23958 write_radio_reg(pi,
23959 RADIO_2056_TX_TSSI_MISC2 |
23960 jtag_core, 0x00);
23961 write_radio_reg(pi,
23962 RADIO_2056_TX_TSSI_MISC3 |
23963 jtag_core, 0x00);
23964 }
23965 }
23966 } else {
23967
23968 pi->tx_rx_cal_radio_saveregs[0] =
23969 read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
23970 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1, 0x29);
23971 pi->tx_rx_cal_radio_saveregs[1] =
23972 read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
23973 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2, 0x54);
23974
23975 pi->tx_rx_cal_radio_saveregs[2] =
23976 read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
23977 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1, 0x29);
23978 pi->tx_rx_cal_radio_saveregs[3] =
23979 read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
23980 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2, 0x54);
23981
23982 pi->tx_rx_cal_radio_saveregs[4] =
23983 read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
23984 pi->tx_rx_cal_radio_saveregs[5] =
23985 read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
23986
23987 if ((read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand) ==
23988 0) {
23989
23990 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x04);
23991 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x04);
23992 } else {
23993
23994 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x20);
23995 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x20);
23996 }
23997
23998 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
23999
24000 or_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM, 0x20);
24001 or_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM, 0x20);
24002 } else {
24003
24004 and_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM, 0xdf);
24005 and_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM, 0xdf);
24006 }
24007 }
24008}
24009
24010static void wlc_phy_txcal_radio_cleanup_nphy(struct brcms_phy *pi)
24011{
24012 u16 jtag_core, core;
24013
24014 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
24015 for (core = 0; core <= 1; core++) {
24016
24017 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24018 TX_SSI_MASTER,
24019 pi->
24020 tx_rx_cal_radio_saveregs[(core * 11) +
24021 0]);
24022
24023 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_VCM_HG,
24024 pi->
24025 tx_rx_cal_radio_saveregs[(core * 11) +
24026 1]);
24027
24028 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_IDAC,
24029 pi->
24030 tx_rx_cal_radio_saveregs[(core * 11) +
24031 2]);
24032
24033 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM,
24034 pi->
24035 tx_rx_cal_radio_saveregs[(core * 11) +
24036 3]);
24037
24038 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TX_SSI_MUX,
24039 pi->
24040 tx_rx_cal_radio_saveregs[(core * 11) +
24041 5]);
24042
24043 if (pi->pubpi.radiorev != 5)
24044 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24045 TSSIA,
24046 pi->tx_rx_cal_radio_saveregs
24047 [(core * 11) + 6]);
24048
24049 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSIG,
24050 pi->
24051 tx_rx_cal_radio_saveregs[(core * 11) +
24052 7]);
24053
24054 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_MISC1,
24055 pi->
24056 tx_rx_cal_radio_saveregs[(core * 11) +
24057 8]);
24058 }
24059 } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
24060 for (core = 0; core <= 1; core++) {
24061 jtag_core = (core == PHY_CORE_0) ?
24062 RADIO_2056_TX0 : RADIO_2056_TX1;
24063
24064 write_radio_reg(pi,
24065 RADIO_2056_TX_TX_SSI_MASTER | jtag_core,
24066 pi->
24067 tx_rx_cal_radio_saveregs[(core * 11) +
24068 0]);
24069
24070 write_radio_reg(pi,
24071 RADIO_2056_TX_IQCAL_VCM_HG | jtag_core,
24072 pi->
24073 tx_rx_cal_radio_saveregs[(core * 11) +
24074 1]);
24075
24076 write_radio_reg(pi,
24077 RADIO_2056_TX_IQCAL_IDAC | jtag_core,
24078 pi->
24079 tx_rx_cal_radio_saveregs[(core * 11) +
24080 2]);
24081
24082 write_radio_reg(pi, RADIO_2056_TX_TSSI_VCM | jtag_core,
24083 pi->
24084 tx_rx_cal_radio_saveregs[(core * 11) +
24085 3]);
24086
24087 write_radio_reg(pi,
24088 RADIO_2056_TX_TX_AMP_DET | jtag_core,
24089 pi->
24090 tx_rx_cal_radio_saveregs[(core * 11) +
24091 4]);
24092
24093 write_radio_reg(pi,
24094 RADIO_2056_TX_TX_SSI_MUX | jtag_core,
24095 pi->
24096 tx_rx_cal_radio_saveregs[(core * 11) +
24097 5]);
24098
24099 write_radio_reg(pi, RADIO_2056_TX_TSSIA | jtag_core,
24100 pi->
24101 tx_rx_cal_radio_saveregs[(core * 11) +
24102 6]);
24103
24104 write_radio_reg(pi, RADIO_2056_TX_TSSIG | jtag_core,
24105 pi->
24106 tx_rx_cal_radio_saveregs[(core * 11) +
24107 7]);
24108
24109 write_radio_reg(pi,
24110 RADIO_2056_TX_TSSI_MISC1 | jtag_core,
24111 pi->
24112 tx_rx_cal_radio_saveregs[(core * 11) +
24113 8]);
24114
24115 write_radio_reg(pi,
24116 RADIO_2056_TX_TSSI_MISC2 | jtag_core,
24117 pi->
24118 tx_rx_cal_radio_saveregs[(core * 11) +
24119 9]);
24120
24121 write_radio_reg(pi,
24122 RADIO_2056_TX_TSSI_MISC3 | jtag_core,
24123 pi->
24124 tx_rx_cal_radio_saveregs[(core * 11) +
24125 10]);
24126 }
24127 } else {
24128
24129 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1,
24130 pi->tx_rx_cal_radio_saveregs[0]);
24131 write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2,
24132 pi->tx_rx_cal_radio_saveregs[1]);
24133 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1,
24134 pi->tx_rx_cal_radio_saveregs[2]);
24135 write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2,
24136 pi->tx_rx_cal_radio_saveregs[3]);
24137 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1,
24138 pi->tx_rx_cal_radio_saveregs[4]);
24139 write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2,
24140 pi->tx_rx_cal_radio_saveregs[5]);
24141 }
24142}
24143
24144static void wlc_phy_txcal_physetup_nphy(struct brcms_phy *pi)
24145{
24146 u16 val, mask;
24147
24148 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
24149 pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6);
24150 pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 0xa7);
24151
24152 mask = ((0x3 << 8) | (0x3 << 10));
24153 val = (0x2 << 8);
24154 val |= (0x2 << 10);
24155 mod_phy_reg(pi, 0xa6, mask, val);
24156 mod_phy_reg(pi, 0xa7, mask, val);
24157
24158 val = read_phy_reg(pi, 0x8f);
24159 pi->tx_rx_cal_phy_saveregs[2] = val;
24160 val |= ((0x1 << 9) | (0x1 << 10));
24161 write_phy_reg(pi, 0x8f, val);
24162
24163 val = read_phy_reg(pi, 0xa5);
24164 pi->tx_rx_cal_phy_saveregs[3] = val;
24165 val |= ((0x1 << 9) | (0x1 << 10));
24166 write_phy_reg(pi, 0xa5, val);
24167
24168 pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 0x01);
24169 mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
24170
24171 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
24172 &val);
24173 pi->tx_rx_cal_phy_saveregs[5] = val;
24174 val = 0;
24175 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
24176 &val);
24177
24178 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
24179 &val);
24180 pi->tx_rx_cal_phy_saveregs[6] = val;
24181 val = 0;
24182 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
24183 &val);
24184
24185 pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 0x91);
24186 pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 0x92);
24187
24188 if (!(pi->use_int_tx_iqlo_cal_nphy))
24189 wlc_phy_rfctrlintc_override_nphy(
24190 pi,
24191 NPHY_RfctrlIntc_override_PA,
24192 1,
24193 RADIO_MIMO_CORESEL_CORE1
24194 |
24195 RADIO_MIMO_CORESEL_CORE2);
24196 else
24197 wlc_phy_rfctrlintc_override_nphy(
24198 pi,
24199 NPHY_RfctrlIntc_override_PA,
24200 0,
24201 RADIO_MIMO_CORESEL_CORE1
24202 |
24203 RADIO_MIMO_CORESEL_CORE2);
24204
24205 wlc_phy_rfctrlintc_override_nphy(pi,
24206 NPHY_RfctrlIntc_override_TRSW,
24207 0x2, RADIO_MIMO_CORESEL_CORE1);
24208 wlc_phy_rfctrlintc_override_nphy(pi,
24209 NPHY_RfctrlIntc_override_TRSW,
24210 0x8, RADIO_MIMO_CORESEL_CORE2);
24211
24212 pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 0x297);
24213 pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 0x29b);
24214 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
24215 0x29b, (0x1 << 0), (0) << 0);
24216
24217 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
24218 0x29b, (0x1 << 0), (0) << 0);
24219
24220 if (NREV_IS(pi->pubpi.phy_rev, 7)
24221 || NREV_GE(pi->pubpi.phy_rev, 8))
24222 wlc_phy_rfctrl_override_nphy_rev7(
24223 pi, (0x1 << 7),
24224 wlc_phy_read_lpf_bw_ctl_nphy
24225 (pi,
24226 0), 0, 0,
24227 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24228
24229 if (pi->use_int_tx_iqlo_cal_nphy
24230 && !(pi->internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
24231
24232 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
24233
24234 mod_radio_reg(pi, RADIO_2057_OVR_REG0, 1 << 4,
24235 1 << 4);
24236
24237 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24238 mod_radio_reg(
24239 pi,
24240 RADIO_2057_PAD2G_TUNE_PUS_CORE0,
24241 1, 0);
24242 mod_radio_reg(
24243 pi,
24244 RADIO_2057_PAD2G_TUNE_PUS_CORE1,
24245 1, 0);
24246 } else {
24247 mod_radio_reg(
24248 pi,
24249 RADIO_2057_IPA5G_CASCOFFV_PU_CORE0,
24250 1, 0);
24251 mod_radio_reg(
24252 pi,
24253 RADIO_2057_IPA5G_CASCOFFV_PU_CORE1,
24254 1, 0);
24255 }
24256 } else if (NREV_GE(pi->pubpi.phy_rev, 8)) {
24257 wlc_phy_rfctrl_override_nphy_rev7(
24258 pi,
24259 (0x1 << 3), 0,
24260 0x3, 0,
24261 NPHY_REV7_RFCTRLOVERRIDE_ID0);
24262 }
24263 }
24264 } else {
24265 pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6);
24266 pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 0xa7);
24267
24268 mask = ((0x3 << 12) | (0x3 << 14));
24269 val = (0x2 << 12);
24270 val |= (0x2 << 14);
24271 mod_phy_reg(pi, 0xa6, mask, val);
24272 mod_phy_reg(pi, 0xa7, mask, val);
24273
24274 val = read_phy_reg(pi, 0xa5);
24275 pi->tx_rx_cal_phy_saveregs[2] = val;
24276 val |= ((0x1 << 12) | (0x1 << 13));
24277 write_phy_reg(pi, 0xa5, val);
24278
24279 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
24280 &val);
24281 pi->tx_rx_cal_phy_saveregs[3] = val;
24282 val |= 0x2000;
24283 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
24284 &val);
24285
24286 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
24287 &val);
24288 pi->tx_rx_cal_phy_saveregs[4] = val;
24289 val |= 0x2000;
24290 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
24291 &val);
24292
24293 pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 0x91);
24294 pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 0x92);
24295 val = CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 : 0x120;
24296 write_phy_reg(pi, 0x91, val);
24297 write_phy_reg(pi, 0x92, val);
24298 }
24299}
24300
24301static void wlc_phy_txcal_phycleanup_nphy(struct brcms_phy *pi)
24302{
24303 u16 mask;
24304
24305 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
24306 write_phy_reg(pi, 0xa6, pi->tx_rx_cal_phy_saveregs[0]);
24307 write_phy_reg(pi, 0xa7, pi->tx_rx_cal_phy_saveregs[1]);
24308 write_phy_reg(pi, 0x8f, pi->tx_rx_cal_phy_saveregs[2]);
24309 write_phy_reg(pi, 0xa5, pi->tx_rx_cal_phy_saveregs[3]);
24310 write_phy_reg(pi, 0x01, pi->tx_rx_cal_phy_saveregs[4]);
24311
24312 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
24313 &pi->tx_rx_cal_phy_saveregs[5]);
24314 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
24315 &pi->tx_rx_cal_phy_saveregs[6]);
24316
24317 write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[7]);
24318 write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[8]);
24319
24320 write_phy_reg(pi, 0x297, pi->tx_rx_cal_phy_saveregs[9]);
24321 write_phy_reg(pi, 0x29b, pi->tx_rx_cal_phy_saveregs[10]);
24322
24323 if (NREV_IS(pi->pubpi.phy_rev, 7)
24324 || NREV_GE(pi->pubpi.phy_rev, 8))
24325 wlc_phy_rfctrl_override_nphy_rev7(
24326 pi, (0x1 << 7), 0, 0,
24327 1,
24328 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24329
24330 wlc_phy_resetcca_nphy(pi);
24331
24332 if (pi->use_int_tx_iqlo_cal_nphy
24333 && !(pi->internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
24334
24335 if (NREV_IS(pi->pubpi.phy_rev, 7)) {
24336 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24337 mod_radio_reg(
24338 pi,
24339 RADIO_2057_PAD2G_TUNE_PUS_CORE0,
24340 1, 1);
24341 mod_radio_reg(
24342 pi,
24343 RADIO_2057_PAD2G_TUNE_PUS_CORE1,
24344 1, 1);
24345 } else {
24346 mod_radio_reg(
24347 pi,
24348 RADIO_2057_IPA5G_CASCOFFV_PU_CORE0,
24349 1, 1);
24350 mod_radio_reg(
24351 pi,
24352 RADIO_2057_IPA5G_CASCOFFV_PU_CORE1,
24353 1, 1);
24354 }
24355
24356 mod_radio_reg(pi, RADIO_2057_OVR_REG0, 1 << 4,
24357 0);
24358 } else if (NREV_GE(pi->pubpi.phy_rev, 8)) {
24359 wlc_phy_rfctrl_override_nphy_rev7(
24360 pi,
24361 (0x1 << 3), 0,
24362 0x3, 1,
24363 NPHY_REV7_RFCTRLOVERRIDE_ID0);
24364 }
24365 }
24366 } else {
24367 mask = ((0x3 << 12) | (0x3 << 14));
24368 mod_phy_reg(pi, 0xa6, mask, pi->tx_rx_cal_phy_saveregs[0]);
24369 mod_phy_reg(pi, 0xa7, mask, pi->tx_rx_cal_phy_saveregs[1]);
24370 write_phy_reg(pi, 0xa5, pi->tx_rx_cal_phy_saveregs[2]);
24371
24372 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
24373 &pi->tx_rx_cal_phy_saveregs[3]);
24374
24375 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
24376 &pi->tx_rx_cal_phy_saveregs[4]);
24377
24378 write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[5]);
24379 write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[6]);
24380 }
24381}
24382
24383void
24384wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf, u8 num_samps)
24385{
24386 u16 tssi_reg;
24387 s32 temp, pwrindex[2];
24388 s32 idle_tssi[2];
24389 s32 rssi_buf[4];
24390 s32 tssival[2];
24391 u8 tssi_type;
24392
24393 tssi_reg = read_phy_reg(pi, 0x1e9);
24394
24395 temp = (s32) (tssi_reg & 0x3f);
24396 idle_tssi[0] = (temp <= 31) ? temp : (temp - 64);
24397
24398 temp = (s32) ((tssi_reg >> 8) & 0x3f);
24399 idle_tssi[1] = (temp <= 31) ? temp : (temp - 64);
24400
24401 tssi_type =
24402 CHSPEC_IS5G(pi->radio_chanspec) ?
24403 (u8)NPHY_RSSI_SEL_TSSI_5G : (u8)NPHY_RSSI_SEL_TSSI_2G;
24404
24405 wlc_phy_poll_rssi_nphy(pi, tssi_type, rssi_buf, num_samps);
24406
24407 tssival[0] = rssi_buf[0] / ((s32) num_samps);
24408 tssival[1] = rssi_buf[2] / ((s32) num_samps);
24409
24410 pwrindex[0] = idle_tssi[0] - tssival[0] + 64;
24411 pwrindex[1] = idle_tssi[1] - tssival[1] + 64;
24412
24413 if (pwrindex[0] < 0)
24414 pwrindex[0] = 0;
24415 else if (pwrindex[0] > 63)
24416 pwrindex[0] = 63;
24417
24418 if (pwrindex[1] < 0)
24419 pwrindex[1] = 0;
24420 else if (pwrindex[1] > 63)
24421 pwrindex[1] = 63;
24422
24423 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 1,
24424 (u32) pwrindex[0], 32, &qdBm_pwrbuf[0]);
24425 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 1,
24426 (u32) pwrindex[1], 32, &qdBm_pwrbuf[1]);
24427}
24428
24429static void wlc_phy_update_txcal_ladder_nphy(struct brcms_phy *pi, u16 core)
24430{
24431 int index;
24432 u32 bbmult_scale;
24433 u16 bbmult;
24434 u16 tblentry;
24435
24436 struct nphy_txiqcal_ladder ladder_lo[] = {
24437 {3, 0}, {4, 0}, {6, 0}, {9, 0}, {13, 0}, {18, 0},
24438 {25, 0}, {25, 1}, {25, 2}, {25, 3}, {25, 4}, {25, 5},
24439 {25, 6}, {25, 7}, {35, 7}, {50, 7}, {71, 7}, {100, 7}
24440 };
24441
24442 struct nphy_txiqcal_ladder ladder_iq[] = {
24443 {3, 0}, {4, 0}, {6, 0}, {9, 0}, {13, 0}, {18, 0},
24444 {25, 0}, {35, 0}, {50, 0}, {71, 0}, {100, 0}, {100, 1},
24445 {100, 2}, {100, 3}, {100, 4}, {100, 5}, {100, 6}, {100, 7}
24446 };
24447
24448 bbmult = (core == PHY_CORE_0) ?
24449 ((pi->nphy_txcal_bbmult >> 8) & 0xff) :
24450 (pi->nphy_txcal_bbmult & 0xff);
24451
24452 for (index = 0; index < 18; index++) {
24453 bbmult_scale = ladder_lo[index].percent * bbmult;
24454 bbmult_scale /= 100;
24455
24456 tblentry =
24457 ((bbmult_scale & 0xff) << 8) | ladder_lo[index].g_env;
24458 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, index, 16,
24459 &tblentry);
24460
24461 bbmult_scale = ladder_iq[index].percent * bbmult;
24462 bbmult_scale /= 100;
24463
24464 tblentry =
24465 ((bbmult_scale & 0xff) << 8) | ladder_iq[index].g_env;
24466 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, index + 32,
24467 16, &tblentry);
24468 }
24469}
24470
24471static u8 wlc_phy_txpwr_idx_cur_get_nphy(struct brcms_phy *pi, u8 core)
24472{
24473 u16 tmp;
24474 tmp = read_phy_reg(pi, ((core == PHY_CORE_0) ? 0x1ed : 0x1ee));
24475
24476 tmp = (tmp & (0x7f << 8)) >> 8;
24477 return (u8) tmp;
24478}
24479
24480static void
24481wlc_phy_txpwr_idx_cur_set_nphy(struct brcms_phy *pi, u8 idx0, u8 idx1)
24482{
24483 mod_phy_reg(pi, 0x1e7, (0x7f << 0), idx0);
24484
24485 if (NREV_GT(pi->pubpi.phy_rev, 1))
24486 mod_phy_reg(pi, 0x222, (0xff << 0), idx1);
24487}
24488
24489static u16 wlc_phy_ipa_get_bbmult_nphy(struct brcms_phy *pi)
24490{
24491 u16 m0m1;
24492
24493 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1);
24494
24495 return m0m1;
24496}
24497
24498static void wlc_phy_ipa_set_bbmult_nphy(struct brcms_phy *pi, u8 m0, u8 m1)
24499{
24500 u16 m0m1 = (u16) ((m0 << 8) | m1);
24501
24502 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m0m1);
24503 wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &m0m1);
24504}
24505
24506static void
24507wlc_phy_papd_cal_setup_nphy(struct brcms_phy *pi,
24508 struct nphy_papd_restore_state *state, u8 core)
24509{
24510 s32 tone_freq;
24511 u8 off_core;
24512 u16 mixgain = 0;
24513
24514 off_core = core ^ 0x1;
24515 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
24516
24517 if (NREV_IS(pi->pubpi.phy_rev, 7)
24518 || NREV_GE(pi->pubpi.phy_rev, 8))
24519 wlc_phy_rfctrl_override_nphy_rev7(
24520 pi, (0x1 << 7),
24521 wlc_phy_read_lpf_bw_ctl_nphy
24522 (pi,
24523 0), 0, 0,
24524 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24525
24526 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24527 if (pi->pubpi.radiorev == 5)
24528 mixgain = (core == 0) ? 0x20 : 0x00;
24529 else if ((pi->pubpi.radiorev == 7)
24530 || (pi->pubpi.radiorev == 8))
24531 mixgain = 0x00;
24532 else if ((pi->pubpi.radiorev <= 4)
24533 || (pi->pubpi.radiorev == 6))
24534 mixgain = 0x00;
24535 } else {
24536 if ((pi->pubpi.radiorev == 4) ||
24537 (pi->pubpi.radiorev == 6))
24538 mixgain = 0x50;
24539 else if ((pi->pubpi.radiorev == 3)
24540 || (pi->pubpi.radiorev == 7)
24541 || (pi->pubpi.radiorev == 8))
24542 mixgain = 0x0;
24543 }
24544
24545 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11),
24546 mixgain, (1 << core), 0,
24547 NPHY_REV7_RFCTRLOVERRIDE_ID0);
24548
24549 wlc_phy_rfctrl_override_1tomany_nphy(
24550 pi,
24551 NPHY_REV7_RfctrlOverride_cmd_tx_pu,
24552 1, (1 << core), 0);
24553 wlc_phy_rfctrl_override_1tomany_nphy(
24554 pi,
24555 NPHY_REV7_RfctrlOverride_cmd_tx_pu,
24556 0, (1 << off_core), 0);
24557
24558 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
24559 0, 0x3, 0,
24560 NPHY_REV7_RFCTRLOVERRIDE_ID0);
24561 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 1,
24562 (1 << core), 0,
24563 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24564 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0,
24565 (1 << core), 0,
24566 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24567 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1,
24568 (1 << core), 0,
24569 NPHY_REV7_RFCTRLOVERRIDE_ID2);
24570 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 8), 0,
24571 (1 << core), 0,
24572 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24573 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 1,
24574 (1 << core), 0,
24575 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24576 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 0,
24577 (1 << core), 0,
24578 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24579 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 1,
24580 (1 << core), 0,
24581 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24582
24583 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5),
24584 0, (1 << core), 0,
24585 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24586 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 0,
24587 (1 << core), 0,
24588 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24589
24590 state->afectrl[core] = read_phy_reg(pi, (core == PHY_CORE_0) ?
24591 0xa6 : 0xa7);
24592 state->afeoverride[core] =
24593 read_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f : 0xa5);
24594 state->afectrl[off_core] =
24595 read_phy_reg(pi, (core == PHY_CORE_0) ? 0xa7 : 0xa6);
24596 state->afeoverride[off_core] =
24597 read_phy_reg(pi, (core == PHY_CORE_0) ? 0xa5 : 0x8f);
24598
24599 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa6 : 0xa7),
24600 (0x1 << 2), 0);
24601 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
24602 0xa5), (0x1 << 2), (0x1 << 2));
24603
24604 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa7 : 0xa6),
24605 (0x1 << 2), (0x1 << 2));
24606 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa5 :
24607 0x8f), (0x1 << 2), (0x1 << 2));
24608
24609 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24610 state->pwrup[core] =
24611 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
24612 TXRXCOUPLE_2G_PWRUP);
24613 state->atten[core] =
24614 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
24615 TXRXCOUPLE_2G_ATTEN);
24616 state->pwrup[off_core] =
24617 READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24618 TXRXCOUPLE_2G_PWRUP);
24619 state->atten[off_core] =
24620 READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24621 TXRXCOUPLE_2G_ATTEN);
24622
24623 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24624 TXRXCOUPLE_2G_PWRUP, 0xc);
24625
24626 if ((pi->pubpi.radiorev == 3) ||
24627 (pi->pubpi.radiorev == 4) ||
24628 (pi->pubpi.radiorev == 6))
24629 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24630 TXRXCOUPLE_2G_ATTEN, 0xf0);
24631 else if (pi->pubpi.radiorev == 5)
24632 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24633 TXRXCOUPLE_2G_ATTEN,
24634 (core == 0) ? 0xf7 : 0xf2);
24635 else if ((pi->pubpi.radiorev == 7)
24636 || (pi->pubpi.radiorev == 8))
24637 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24638 TXRXCOUPLE_2G_ATTEN, 0xf0);
24639
24640 WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24641 TXRXCOUPLE_2G_PWRUP, 0x0);
24642 WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24643 TXRXCOUPLE_2G_ATTEN, 0xff);
24644 } else {
24645 state->pwrup[core] =
24646 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
24647 TXRXCOUPLE_5G_PWRUP);
24648 state->atten[core] =
24649 READ_RADIO_REG3(pi, RADIO_2057, TX, core,
24650 TXRXCOUPLE_5G_ATTEN);
24651 state->pwrup[off_core] =
24652 READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24653 TXRXCOUPLE_5G_PWRUP);
24654 state->atten[off_core] =
24655 READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24656 TXRXCOUPLE_5G_ATTEN);
24657
24658 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24659 TXRXCOUPLE_5G_PWRUP, 0xc);
24660
24661 if ((pi->pubpi.radiorev == 7)
24662 || (pi->pubpi.radiorev == 8))
24663 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24664 TXRXCOUPLE_5G_ATTEN, 0xf4);
24665
24666 else
24667 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24668 TXRXCOUPLE_5G_ATTEN, 0xf0);
24669
24670 WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24671 TXRXCOUPLE_5G_PWRUP, 0x0);
24672 WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
24673 TXRXCOUPLE_5G_ATTEN, 0xff);
24674 }
24675
24676 tone_freq = 4000;
24677
24678 wlc_phy_tx_tone_nphy(pi, tone_freq, 181, 0, 0, false);
24679
24680 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
24681 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_ON) << 0);
24682
24683 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
24684 0x2a4, (0x1 << 13), (1) << 13);
24685
24686 mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x297 :
24687 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_OFF) << 0);
24688
24689 mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x2a3 :
24690 0x2a4, (0x1 << 13), (0) << 13);
24691
24692 } else {
24693
24694 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 0);
24695
24696 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 1, 0, 0);
24697
24698 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0x3, 0);
24699
24700 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 2), 1, 0x3, 0);
24701 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 1, 0x3, 0);
24702
24703 state->afectrl[core] = read_phy_reg(pi, (core == PHY_CORE_0) ?
24704 0xa6 : 0xa7);
24705 state->afeoverride[core] =
24706 read_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f : 0xa5);
24707
24708 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa6 : 0xa7),
24709 (0x1 << 0) | (0x1 << 1) | (0x1 << 2), 0);
24710 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
24711 0xa5),
24712 (0x1 << 0) |
24713 (0x1 << 1) |
24714 (0x1 << 2), (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
24715
24716 state->vga_master[core] =
24717 READ_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER);
24718 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER, 0x2b);
24719 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24720 state->fbmix[core] =
24721 READ_RADIO_REG2(pi, RADIO_2056, RX, core,
24722 TXFBMIX_G);
24723 state->intpa_master[core] =
24724 READ_RADIO_REG2(pi, RADIO_2056, TX, core,
24725 INTPAG_MASTER);
24726
24727 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, TXFBMIX_G,
24728 0x03);
24729 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
24730 INTPAG_MASTER, 0x04);
24731 } else {
24732 state->fbmix[core] =
24733 READ_RADIO_REG2(pi, RADIO_2056, RX, core,
24734 TXFBMIX_A);
24735 state->intpa_master[core] =
24736 READ_RADIO_REG2(pi, RADIO_2056, TX, core,
24737 INTPAA_MASTER);
24738
24739 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, TXFBMIX_A,
24740 0x03);
24741 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
24742 INTPAA_MASTER, 0x04);
24743
24744 }
24745
24746 tone_freq = 4000;
24747
24748 wlc_phy_tx_tone_nphy(pi, tone_freq, 181, 0, 0, false);
24749
24750 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
24751 0x29b, (0x1 << 0), (1) << 0);
24752
24753 mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x297 :
24754 0x29b, (0x1 << 0), (0) << 0);
24755
24756 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 0);
24757 }
24758}
24759
24760static void
24761wlc_phy_papd_cal_cleanup_nphy(struct brcms_phy *pi,
24762 struct nphy_papd_restore_state *state)
24763{
24764 u8 core;
24765
24766 wlc_phy_stopplayback_nphy(pi);
24767
24768 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
24769
24770 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
24771
24772 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24773 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24774 TXRXCOUPLE_2G_PWRUP, 0);
24775 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24776 TXRXCOUPLE_2G_ATTEN,
24777 state->atten[core]);
24778 } else {
24779 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24780 TXRXCOUPLE_5G_PWRUP, 0);
24781 WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
24782 TXRXCOUPLE_5G_ATTEN,
24783 state->atten[core]);
24784 }
24785 }
24786
24787 if ((pi->pubpi.radiorev == 4) || (pi->pubpi.radiorev == 6))
24788 wlc_phy_rfctrl_override_nphy_rev7(
24789 pi, (0x1 << 2),
24790 1, 0x3, 0,
24791 NPHY_REV7_RFCTRLOVERRIDE_ID0);
24792 else
24793 wlc_phy_rfctrl_override_nphy_rev7(
24794 pi, (0x1 << 2),
24795 0, 0x3, 1,
24796 NPHY_REV7_RFCTRLOVERRIDE_ID0);
24797
24798 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1),
24799 0, 0x3, 1,
24800 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24801 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0, 0x3, 1,
24802 NPHY_REV7_RFCTRLOVERRIDE_ID2);
24803 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 0, 0x3, 1,
24804 NPHY_REV7_RFCTRLOVERRIDE_ID2);
24805 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 1, 0x3, 1,
24806 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24807 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 0, 0x3, 1,
24808 NPHY_REV7_RFCTRLOVERRIDE_ID0);
24809 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0, 0x3, 1,
24810 NPHY_REV7_RFCTRLOVERRIDE_ID0);
24811 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12), 0, 0x3, 1,
24812 NPHY_REV7_RFCTRLOVERRIDE_ID0);
24813 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 1, 0x3, 1,
24814 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24815 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0, 0x3, 1,
24816 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24817 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1, 0x3, 1,
24818 NPHY_REV7_RFCTRLOVERRIDE_ID2);
24819 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 8), 0, 0x3, 1,
24820 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24821 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 1, 0x3, 1,
24822 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24823 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 0, 0x3, 1,
24824 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24825 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 1, 0x3, 1,
24826 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24827 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 0, 0x3, 1,
24828 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24829 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 0, 0x3, 1,
24830 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24831
24832 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
24833
24834 write_phy_reg(pi, (core == PHY_CORE_0) ?
24835 0xa6 : 0xa7, state->afectrl[core]);
24836 write_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f :
24837 0xa5, state->afeoverride[core]);
24838 }
24839
24840 wlc_phy_ipa_set_bbmult_nphy(pi, (state->mm >> 8) & 0xff,
24841 (state->mm & 0xff));
24842
24843 if (NREV_IS(pi->pubpi.phy_rev, 7)
24844 || NREV_GE(pi->pubpi.phy_rev, 8))
24845 wlc_phy_rfctrl_override_nphy_rev7(
24846 pi, (0x1 << 7), 0, 0,
24847 1,
24848 NPHY_REV7_RFCTRLOVERRIDE_ID1);
24849 } else {
24850 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 1);
24851 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 0x3, 1);
24852 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0x3, 1);
24853
24854 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 2), 0, 0x3, 1);
24855 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 0, 0x3, 1);
24856
24857 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
24858
24859 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER,
24860 state->vga_master[core]);
24861 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24862 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core,
24863 TXFBMIX_G, state->fbmix[core]);
24864 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
24865 INTPAG_MASTER,
24866 state->intpa_master[core]);
24867 } else {
24868 WRITE_RADIO_REG2(pi, RADIO_2056, RX, core,
24869 TXFBMIX_A, state->fbmix[core]);
24870 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
24871 INTPAA_MASTER,
24872 state->intpa_master[core]);
24873 }
24874
24875 write_phy_reg(pi, (core == PHY_CORE_0) ?
24876 0xa6 : 0xa7, state->afectrl[core]);
24877 write_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f :
24878 0xa5, state->afeoverride[core]);
24879 }
24880
24881 wlc_phy_ipa_set_bbmult_nphy(pi, (state->mm >> 8) & 0xff,
24882 (state->mm & 0xff));
24883
24884 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 1);
24885 }
24886}
24887
24888static void
24889wlc_phy_a1_nphy(struct brcms_phy *pi, u8 core, u32 winsz, u32 start,
24890 u32 end)
24891{
24892 u32 *buf, *src, *dst, sz;
24893
24894 sz = end - start + 1;
24895
24896 buf = kmalloc(2 * sizeof(u32) * NPHY_PAPD_EPS_TBL_SIZE, GFP_ATOMIC);
24897 if (NULL == buf)
24898 return;
24899
24900 src = buf;
24901 dst = buf + NPHY_PAPD_EPS_TBL_SIZE;
24902
24903 wlc_phy_table_read_nphy(pi,
24904 (core ==
24905 PHY_CORE_0 ? NPHY_TBL_ID_EPSILONTBL0 :
24906 NPHY_TBL_ID_EPSILONTBL1),
24907 NPHY_PAPD_EPS_TBL_SIZE, 0, 32, src);
24908
24909 do {
24910 u32 phy_a1, phy_a2;
24911 s32 phy_a3, phy_a4, phy_a5, phy_a6, phy_a7;
24912
24913 phy_a1 = end - min(end, (winsz >> 1));
24914 phy_a2 = min_t(u32, NPHY_PAPD_EPS_TBL_SIZE - 1,
24915 end + (winsz >> 1));
24916 phy_a3 = phy_a2 - phy_a1 + 1;
24917 phy_a6 = 0;
24918 phy_a7 = 0;
24919
24920 do {
24921 wlc_phy_papd_decode_epsilon(src[phy_a2], &phy_a4,
24922 &phy_a5);
24923 phy_a6 += phy_a4;
24924 phy_a7 += phy_a5;
24925 } while (phy_a2-- != phy_a1);
24926
24927 phy_a6 /= phy_a3;
24928 phy_a7 /= phy_a3;
24929 dst[end] = ((u32) phy_a7 << 13) | ((u32) phy_a6 & 0x1fff);
24930 } while (end-- != start);
24931
24932 wlc_phy_table_write_nphy(pi,
24933 (core ==
24934 PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0 :
24935 NPHY_TBL_ID_EPSILONTBL1, sz, start, 32, dst);
24936
24937 kfree(buf);
24938}
24939
24940static void
24941wlc_phy_a2_nphy(struct brcms_phy *pi, struct nphy_ipa_txcalgains *txgains,
24942 enum phy_cal_mode cal_mode, u8 core)
24943{
24944 u16 phy_a1, phy_a2, phy_a3;
24945 u16 phy_a4, phy_a5;
24946 bool phy_a6;
24947 u8 phy_a7, m[2];
24948 u32 phy_a8 = 0;
24949 struct nphy_txgains phy_a9;
24950
24951 if (NREV_LT(pi->pubpi.phy_rev, 3))
24952 return;
24953
24954 phy_a7 = (core == PHY_CORE_0) ? 1 : 0;
24955
24956 phy_a6 = ((cal_mode == CAL_GCTRL)
24957 || (cal_mode == CAL_SOFT)) ? true : false;
24958
24959 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
24960
24961 phy_a9 = wlc_phy_get_tx_gain_nphy(pi);
24962
24963 if (CHSPEC_IS2G(pi->radio_chanspec))
24964 phy_a5 = ((phy_a9.txlpf[core] << 15) |
24965 (phy_a9.txgm[core] << 12) |
24966 (phy_a9.pga[core] << 8) |
24967 (txgains->gains.pad[core] << 3) |
24968 (phy_a9.ipa[core]));
24969 else
24970 phy_a5 = ((phy_a9.txlpf[core] << 15) |
24971 (phy_a9.txgm[core] << 12) |
24972 (txgains->gains.pga[core] << 8) |
24973 (phy_a9.pad[core] << 3) | (phy_a9.ipa[core]));
24974
24975 wlc_phy_rfctrl_override_1tomany_nphy(
24976 pi,
24977 NPHY_REV7_RfctrlOverride_cmd_txgain,
24978 phy_a5, (1 << core), 0);
24979
24980 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24981 if ((pi->pubpi.radiorev <= 4)
24982 || (pi->pubpi.radiorev == 6))
24983 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ?
24984 60 : 79;
24985 else
24986 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ?
24987 45 : 64;
24988 } else {
24989 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ? 75 : 107;
24990 }
24991
24992 m[phy_a7] = 0;
24993 wlc_phy_ipa_set_bbmult_nphy(pi, m[0], m[1]);
24994
24995 phy_a2 = 63;
24996
24997 if (CHSPEC_IS2G(pi->radio_chanspec)) {
24998 if ((pi->pubpi.radiorev == 4)
24999 || (pi->pubpi.radiorev == 6)) {
25000 phy_a1 = 30;
25001 phy_a3 = 30;
25002 } else {
25003 phy_a1 = 25;
25004 phy_a3 = 25;
25005 }
25006 } else {
25007 if ((pi->pubpi.radiorev == 5)
25008 || (pi->pubpi.radiorev == 7)
25009 || (pi->pubpi.radiorev == 8)) {
25010 phy_a1 = 25;
25011 phy_a3 = 25;
25012 } else {
25013 phy_a1 = 35;
25014 phy_a3 = 35;
25015 }
25016 }
25017
25018 if (cal_mode == CAL_GCTRL) {
25019 if ((pi->pubpi.radiorev == 5)
25020 && (CHSPEC_IS2G(pi->radio_chanspec)))
25021 phy_a1 = 55;
25022 else if (((pi->pubpi.radiorev == 7) &&
25023 (CHSPEC_IS2G(pi->radio_chanspec))) ||
25024 ((pi->pubpi.radiorev == 8) &&
25025 (CHSPEC_IS2G(pi->radio_chanspec))))
25026 phy_a1 = 60;
25027 else
25028 phy_a1 = 63;
25029
25030 } else if ((cal_mode != CAL_FULL) && (cal_mode != CAL_SOFT)) {
25031
25032 phy_a1 = 35;
25033 phy_a3 = 35;
25034 }
25035
25036 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
25037 0x29b, (0x1 << 0), (1) << 0);
25038
25039 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x297 :
25040 0x29b, (0x1 << 0), (0) << 0);
25041
25042 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25043 0x2a4, (0x1 << 13), (1) << 13);
25044
25045 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
25046 0x2a4, (0x1 << 13), (0) << 13);
25047
25048 write_phy_reg(pi, 0x2a1, 0x80);
25049 write_phy_reg(pi, 0x2a2, 0x100);
25050
25051 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25052 0x2a4, (0x7 << 4), (11) << 4);
25053
25054 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25055 0x2a4, (0x7 << 8), (11) << 8);
25056
25057 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25058 0x2a4, (0x7 << 0), (0x3) << 0);
25059
25060 write_phy_reg(pi, 0x2e5, 0x20);
25061
25062 mod_phy_reg(pi, 0x2a0, (0x3f << 0), (phy_a3) << 0);
25063
25064 mod_phy_reg(pi, 0x29f, (0x3f << 0), (phy_a1) << 0);
25065
25066 mod_phy_reg(pi, 0x29f, (0x3f << 8), (phy_a2) << 8);
25067
25068 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
25069 1, ((core == 0) ? 1 : 2), 0,
25070 NPHY_REV7_RFCTRLOVERRIDE_ID0);
25071 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
25072 0, ((core == 0) ? 2 : 1), 0,
25073 NPHY_REV7_RFCTRLOVERRIDE_ID0);
25074
25075 write_phy_reg(pi, 0x2be, 1);
25076 SPINWAIT(read_phy_reg(pi, 0x2be), 10 * 1000 * 1000);
25077
25078 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
25079 0, 0x3, 0,
25080 NPHY_REV7_RFCTRLOVERRIDE_ID0);
25081
25082 wlc_phy_table_write_nphy(pi,
25083 (core ==
25084 PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0
25085 : NPHY_TBL_ID_EPSILONTBL1, 1, phy_a3,
25086 32, &phy_a8);
25087
25088 if (cal_mode != CAL_GCTRL) {
25089 if (CHSPEC_IS5G(pi->radio_chanspec))
25090 wlc_phy_a1_nphy(pi, core, 5, 0, 35);
25091 }
25092
25093 wlc_phy_rfctrl_override_1tomany_nphy(
25094 pi,
25095 NPHY_REV7_RfctrlOverride_cmd_txgain,
25096 phy_a5, (1 << core), 1);
25097
25098 } else {
25099
25100 if (txgains) {
25101 if (txgains->useindex) {
25102 phy_a4 = 15 - ((txgains->index) >> 3);
25103 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25104 if (NREV_GE(pi->pubpi.phy_rev, 6))
25105 phy_a5 = 0x00f7 | (phy_a4 << 8);
25106
25107 else
25108 if (NREV_IS(pi->pubpi.phy_rev, 5))
25109 phy_a5 = 0x10f7 | (phy_a4 << 8);
25110 else
25111 phy_a5 = 0x50f7 | (phy_a4 << 8);
25112 } else {
25113 phy_a5 = 0x70f7 | (phy_a4 << 8);
25114 }
25115 wlc_phy_rfctrl_override_nphy(pi,
25116 (0x1 << 13),
25117 phy_a5,
25118 (1 << core), 0);
25119 } else {
25120 wlc_phy_rfctrl_override_nphy(pi,
25121 (0x1 << 13),
25122 0x5bf7,
25123 (1 << core), 0);
25124 }
25125 }
25126
25127 if (CHSPEC_IS2G(pi->radio_chanspec))
25128 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ? 45 : 64;
25129 else
25130 m[core] = (pi->bw == WL_CHANSPEC_BW_40) ? 75 : 107;
25131
25132 m[phy_a7] = 0;
25133 wlc_phy_ipa_set_bbmult_nphy(pi, m[0], m[1]);
25134
25135 phy_a2 = 63;
25136
25137 if (cal_mode == CAL_FULL) {
25138 phy_a1 = 25;
25139 phy_a3 = 25;
25140 } else if (cal_mode == CAL_SOFT) {
25141 phy_a1 = 25;
25142 phy_a3 = 25;
25143 } else if (cal_mode == CAL_GCTRL) {
25144 phy_a1 = 63;
25145 phy_a3 = 25;
25146 } else {
25147
25148 phy_a1 = 25;
25149 phy_a3 = 25;
25150 }
25151
25152 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
25153 0x29b, (0x1 << 0), (1) << 0);
25154
25155 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x297 :
25156 0x29b, (0x1 << 0), (0) << 0);
25157
25158 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
25159 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25160 0x2a4, (0x1 << 13), (1) << 13);
25161
25162 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
25163 0x2a4, (0x1 << 13), (0) << 13);
25164
25165 write_phy_reg(pi, 0x2a1, 0x20);
25166 write_phy_reg(pi, 0x2a2, 0x60);
25167
25168 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25169 0x2a4, (0xf << 4), (9) << 4);
25170
25171 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25172 0x2a4, (0xf << 8), (9) << 8);
25173
25174 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25175 0x2a4, (0xf << 0), (0x2) << 0);
25176
25177 write_phy_reg(pi, 0x2e5, 0x20);
25178 } else {
25179 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25180 0x2a4, (0x1 << 11), (1) << 11);
25181
25182 mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
25183 0x2a4, (0x1 << 11), (0) << 11);
25184
25185 write_phy_reg(pi, 0x2a1, 0x80);
25186 write_phy_reg(pi, 0x2a2, 0x600);
25187
25188 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25189 0x2a4, (0x7 << 4), (0) << 4);
25190
25191 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25192 0x2a4, (0x7 << 8), (0) << 8);
25193
25194 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
25195 0x2a4, (0x7 << 0), (0x3) << 0);
25196
25197 mod_phy_reg(pi, 0x2a0, (0x3f << 8), (0x20) << 8);
25198
25199 }
25200
25201 mod_phy_reg(pi, 0x2a0, (0x3f << 0), (phy_a3) << 0);
25202
25203 mod_phy_reg(pi, 0x29f, (0x3f << 0), (phy_a1) << 0);
25204
25205 mod_phy_reg(pi, 0x29f, (0x3f << 8), (phy_a2) << 8);
25206
25207 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 1, 0x3, 0);
25208
25209 write_phy_reg(pi, 0x2be, 1);
25210 SPINWAIT(read_phy_reg(pi, 0x2be), 10 * 1000 * 1000);
25211
25212 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 0);
25213
25214 wlc_phy_table_write_nphy(pi,
25215 (core ==
25216 PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0
25217 : NPHY_TBL_ID_EPSILONTBL1, 1, phy_a3,
25218 32, &phy_a8);
25219
25220 if (cal_mode != CAL_GCTRL)
25221 wlc_phy_a1_nphy(pi, core, 5, 0, 40);
25222 }
25223}
25224
25225static u8 wlc_phy_a3_nphy(struct brcms_phy *pi, u8 start_gain, u8 core)
25226{
25227 int phy_a1;
25228 int phy_a2;
25229 bool phy_a3;
25230 struct nphy_ipa_txcalgains phy_a4;
25231 bool phy_a5 = false;
25232 bool phy_a6 = true;
25233 s32 phy_a7, phy_a8;
25234 u32 phy_a9;
25235 int phy_a10;
25236 bool phy_a11 = false;
25237 int phy_a12;
25238 u8 phy_a13 = 0;
25239 u8 phy_a14;
25240 u8 *phy_a15 = NULL;
25241
25242 phy_a4.useindex = true;
25243 phy_a12 = start_gain;
25244
25245 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
25246
25247 phy_a2 = 20;
25248 phy_a1 = 1;
25249
25250 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25251 if (pi->pubpi.radiorev == 5) {
25252
25253 phy_a15 = pad_gain_codes_used_2057rev5;
25254 phy_a13 =
25255 sizeof(pad_gain_codes_used_2057rev5) /
25256 sizeof(pad_gain_codes_used_2057rev5
25257 [0]) - 1;
25258
25259 } else if ((pi->pubpi.radiorev == 7)
25260 || (pi->pubpi.radiorev == 8)) {
25261
25262 phy_a15 = pad_gain_codes_used_2057rev7;
25263 phy_a13 =
25264 sizeof(pad_gain_codes_used_2057rev7) /
25265 sizeof(pad_gain_codes_used_2057rev7
25266 [0]) - 1;
25267
25268 } else {
25269
25270 phy_a15 = pad_all_gain_codes_2057;
25271 phy_a13 = sizeof(pad_all_gain_codes_2057) /
25272 sizeof(pad_all_gain_codes_2057[0]) -
25273 1;
25274 }
25275
25276 } else {
25277
25278 phy_a15 = pga_all_gain_codes_2057;
25279 phy_a13 = sizeof(pga_all_gain_codes_2057) /
25280 sizeof(pga_all_gain_codes_2057[0]) - 1;
25281 }
25282
25283 phy_a14 = 0;
25284
25285 for (phy_a10 = 0; phy_a10 < phy_a2; phy_a10++) {
25286 if (CHSPEC_IS2G(pi->radio_chanspec))
25287 phy_a4.gains.pad[core] =
25288 (u16) phy_a15[phy_a12];
25289 else
25290 phy_a4.gains.pga[core] =
25291 (u16) phy_a15[phy_a12];
25292
25293 wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core);
25294
25295 wlc_phy_table_read_nphy(pi,
25296 (core ==
25297 PHY_CORE_0 ?
25298 NPHY_TBL_ID_EPSILONTBL0 :
25299 NPHY_TBL_ID_EPSILONTBL1), 1,
25300 63, 32, &phy_a9);
25301
25302 wlc_phy_papd_decode_epsilon(phy_a9, &phy_a7, &phy_a8);
25303
25304 phy_a3 = ((phy_a7 == 4095) || (phy_a7 == -4096) ||
25305 (phy_a8 == 4095) || (phy_a8 == -4096));
25306
25307 if (!phy_a6 && (phy_a3 != phy_a5)) {
25308 if (!phy_a3)
25309 phy_a12 -= (u8) phy_a1;
25310
25311 phy_a11 = true;
25312 break;
25313 }
25314
25315 if (phy_a3)
25316 phy_a12 += (u8) phy_a1;
25317 else
25318 phy_a12 -= (u8) phy_a1;
25319
25320 if ((phy_a12 < phy_a14) || (phy_a12 > phy_a13)) {
25321 if (phy_a12 < phy_a14)
25322 phy_a12 = phy_a14;
25323 else
25324 phy_a12 = phy_a13;
25325
25326 phy_a11 = true;
25327 break;
25328 }
25329
25330 phy_a6 = false;
25331 phy_a5 = phy_a3;
25332 }
25333
25334 } else {
25335 phy_a2 = 10;
25336 phy_a1 = 8;
25337 for (phy_a10 = 0; phy_a10 < phy_a2; phy_a10++) {
25338 phy_a4.index = (u8) phy_a12;
25339 wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core);
25340
25341 wlc_phy_table_read_nphy(pi,
25342 (core ==
25343 PHY_CORE_0 ?
25344 NPHY_TBL_ID_EPSILONTBL0 :
25345 NPHY_TBL_ID_EPSILONTBL1), 1,
25346 63, 32, &phy_a9);
25347
25348 wlc_phy_papd_decode_epsilon(phy_a9, &phy_a7, &phy_a8);
25349
25350 phy_a3 = ((phy_a7 == 4095) || (phy_a7 == -4096) ||
25351 (phy_a8 == 4095) || (phy_a8 == -4096));
25352
25353 if (!phy_a6 && (phy_a3 != phy_a5)) {
25354 if (!phy_a3)
25355 phy_a12 -= (u8) phy_a1;
25356
25357 phy_a11 = true;
25358 break;
25359 }
25360
25361 if (phy_a3)
25362 phy_a12 += (u8) phy_a1;
25363 else
25364 phy_a12 -= (u8) phy_a1;
25365
25366 if ((phy_a12 < 0) || (phy_a12 > 127)) {
25367 if (phy_a12 < 0)
25368 phy_a12 = 0;
25369 else
25370 phy_a12 = 127;
25371
25372 phy_a11 = true;
25373 break;
25374 }
25375
25376 phy_a6 = false;
25377 phy_a5 = phy_a3;
25378 }
25379
25380 }
25381
25382 if (NREV_GE(pi->pubpi.phy_rev, 7))
25383 return (u8) phy_a15[phy_a12];
25384 else
25385 return (u8) phy_a12;
25386
25387}
25388
25389static void wlc_phy_a4(struct brcms_phy *pi, bool full_cal)
25390{
25391 struct nphy_ipa_txcalgains phy_b1[2];
25392 struct nphy_papd_restore_state phy_b2;
25393 bool phy_b3;
25394 u8 phy_b4;
25395 u8 phy_b5;
25396 s16 phy_b6, phy_b7, phy_b8;
25397 u16 phy_b9;
25398 s16 phy_b10, phy_b11, phy_b12;
25399
25400 phy_b11 = 0;
25401 phy_b12 = 0;
25402 phy_b7 = 0;
25403 phy_b8 = 0;
25404 phy_b6 = 0;
25405
25406 if (pi->nphy_papd_skip == 1)
25407 return;
25408
25409 phy_b3 = (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
25410 if (!phy_b3)
25411 wlapi_suspend_mac_and_wait(pi->sh->physhim);
25412
25413 wlc_phy_stay_in_carriersearch_nphy(pi, true);
25414
25415 pi->nphy_force_papd_cal = false;
25416
25417 for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++)
25418 pi->nphy_papd_tx_gain_at_last_cal[phy_b5] =
25419 wlc_phy_txpwr_idx_cur_get_nphy(pi, phy_b5);
25420
25421 pi->nphy_papd_last_cal = pi->sh->now;
25422 pi->nphy_papd_recal_counter++;
25423
25424 phy_b4 = pi->nphy_txpwrctrl;
25425 wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
25426
25427 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SCALARTBL0, 64, 0, 32,
25428 nphy_papd_scaltbl);
25429 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SCALARTBL1, 64, 0, 32,
25430 nphy_papd_scaltbl);
25431
25432 phy_b9 = read_phy_reg(pi, 0x01);
25433 mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
25434
25435 for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
25436 s32 i, val = 0;
25437 for (i = 0; i < 64; i++)
25438 wlc_phy_table_write_nphy(pi,
25439 ((phy_b5 ==
25440 PHY_CORE_0) ?
25441 NPHY_TBL_ID_EPSILONTBL0 :
25442 NPHY_TBL_ID_EPSILONTBL1), 1,
25443 i, 32, &val);
25444 }
25445
25446 wlc_phy_ipa_restore_tx_digi_filts_nphy(pi);
25447
25448 phy_b2.mm = wlc_phy_ipa_get_bbmult_nphy(pi);
25449 for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
25450 wlc_phy_papd_cal_setup_nphy(pi, &phy_b2, phy_b5);
25451
25452 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
25453 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25454 if ((pi->pubpi.radiorev == 3)
25455 || (pi->pubpi.radiorev == 4)
25456 || (pi->pubpi.radiorev == 6)) {
25457 pi->nphy_papd_cal_gain_index[phy_b5] =
25458 23;
25459 } else if (pi->pubpi.radiorev == 5) {
25460 pi->nphy_papd_cal_gain_index[phy_b5] =
25461 0;
25462 pi->nphy_papd_cal_gain_index[phy_b5] =
25463 wlc_phy_a3_nphy(
25464 pi,
25465 pi->
25466 nphy_papd_cal_gain_index
25467 [phy_b5],
25468 phy_b5);
25469
25470 } else if ((pi->pubpi.radiorev == 7)
25471 || (pi->pubpi.radiorev == 8)) {
25472
25473 pi->nphy_papd_cal_gain_index[phy_b5] =
25474 0;
25475 pi->nphy_papd_cal_gain_index[phy_b5] =
25476 wlc_phy_a3_nphy(
25477 pi,
25478 pi->
25479 nphy_papd_cal_gain_index
25480 [phy_b5],
25481 phy_b5);
25482
25483 }
25484
25485 phy_b1[phy_b5].gains.pad[phy_b5] =
25486 pi->nphy_papd_cal_gain_index[phy_b5];
25487
25488 } else {
25489 pi->nphy_papd_cal_gain_index[phy_b5] = 0;
25490 pi->nphy_papd_cal_gain_index[phy_b5] =
25491 wlc_phy_a3_nphy(
25492 pi,
25493 pi->
25494 nphy_papd_cal_gain_index
25495 [phy_b5], phy_b5);
25496 phy_b1[phy_b5].gains.pga[phy_b5] =
25497 pi->nphy_papd_cal_gain_index[phy_b5];
25498 }
25499 } else {
25500 phy_b1[phy_b5].useindex = true;
25501 phy_b1[phy_b5].index = 16;
25502 phy_b1[phy_b5].index =
25503 wlc_phy_a3_nphy(pi, phy_b1[phy_b5].index,
25504 phy_b5);
25505
25506 pi->nphy_papd_cal_gain_index[phy_b5] =
25507 15 - ((phy_b1[phy_b5].index) >> 3);
25508 }
25509
25510 switch (pi->nphy_papd_cal_type) {
25511 case 0:
25512 wlc_phy_a2_nphy(pi, &phy_b1[phy_b5], CAL_FULL, phy_b5);
25513 break;
25514 case 1:
25515 wlc_phy_a2_nphy(pi, &phy_b1[phy_b5], CAL_SOFT, phy_b5);
25516 break;
25517 }
25518
25519 if (NREV_GE(pi->pubpi.phy_rev, 7))
25520 wlc_phy_papd_cal_cleanup_nphy(pi, &phy_b2);
25521 }
25522
25523 if (NREV_LT(pi->pubpi.phy_rev, 7))
25524 wlc_phy_papd_cal_cleanup_nphy(pi, &phy_b2);
25525
25526 for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
25527 int eps_offset = 0;
25528
25529 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
25530 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25531 if (pi->pubpi.radiorev == 3)
25532 eps_offset = -2;
25533 else if (pi->pubpi.radiorev == 5)
25534 eps_offset = 3;
25535 else
25536 eps_offset = -1;
25537 } else {
25538 eps_offset = 2;
25539 }
25540
25541 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25542 phy_b8 = phy_b1[phy_b5].gains.pad[phy_b5];
25543 phy_b10 = 0;
25544 if ((pi->pubpi.radiorev == 3) ||
25545 (pi->pubpi.radiorev == 4) ||
25546 (pi->pubpi.radiorev == 6)) {
25547 phy_b12 = -(
25548 nphy_papd_padgain_dlt_2g_2057rev3n4
25549 [phy_b8] + 1) / 2;
25550 phy_b10 = -1;
25551 } else if (pi->pubpi.radiorev == 5) {
25552 phy_b12 = -(
25553 nphy_papd_padgain_dlt_2g_2057rev5
25554 [phy_b8] + 1) / 2;
25555 } else if ((pi->pubpi.radiorev == 7) ||
25556 (pi->pubpi.radiorev == 8)) {
25557 phy_b12 = -(
25558 nphy_papd_padgain_dlt_2g_2057rev7
25559 [phy_b8] + 1) / 2;
25560 }
25561 } else {
25562 phy_b7 = phy_b1[phy_b5].gains.pga[phy_b5];
25563 if ((pi->pubpi.radiorev == 3) ||
25564 (pi->pubpi.radiorev == 4) ||
25565 (pi->pubpi.radiorev == 6))
25566 phy_b11 =
25567 -(nphy_papd_pgagain_dlt_5g_2057
25568 [phy_b7]
25569 + 1) / 2;
25570 else if ((pi->pubpi.radiorev == 7)
25571 || (pi->pubpi.radiorev == 8))
25572 phy_b11 = -(
25573 nphy_papd_pgagain_dlt_5g_2057rev7
25574 [phy_b7] + 1) / 2;
25575
25576 phy_b10 = -9;
25577 }
25578
25579 if (CHSPEC_IS2G(pi->radio_chanspec))
25580 phy_b6 =
25581 -60 + 27 + eps_offset + phy_b12 +
25582 phy_b10;
25583 else
25584 phy_b6 =
25585 -60 + 27 + eps_offset + phy_b11 +
25586 phy_b10;
25587
25588 mod_phy_reg(pi, (phy_b5 == PHY_CORE_0) ? 0x298 :
25589 0x29c, (0x1ff << 7), (phy_b6) << 7);
25590
25591 pi->nphy_papd_epsilon_offset[phy_b5] = phy_b6;
25592 } else {
25593 if (NREV_LT(pi->pubpi.phy_rev, 5))
25594 eps_offset = 4;
25595 else
25596 eps_offset = 2;
25597
25598 phy_b7 = 15 - ((phy_b1[phy_b5].index) >> 3);
25599
25600 if (CHSPEC_IS2G(pi->radio_chanspec)) {
25601 phy_b11 =
25602 -(nphy_papd_pga_gain_delta_ipa_2g[
25603 phy_b7] +
25604 1) / 2;
25605 phy_b10 = 0;
25606 } else {
25607 phy_b11 =
25608 -(nphy_papd_pga_gain_delta_ipa_5g[
25609 phy_b7] +
25610 1) / 2;
25611 phy_b10 = -9;
25612 }
25613
25614 phy_b6 = -60 + 27 + eps_offset + phy_b11 + phy_b10;
25615
25616 mod_phy_reg(pi, (phy_b5 == PHY_CORE_0) ? 0x298 :
25617 0x29c, (0x1ff << 7), (phy_b6) << 7);
25618
25619 pi->nphy_papd_epsilon_offset[phy_b5] = phy_b6;
25620 }
25621 }
25622
25623 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
25624 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_ON) << 0);
25625
25626 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
25627 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_ON) << 0);
25628
25629 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
25630 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x2a3 :
25631 0x2a4, (0x1 << 13), (0) << 13);
25632
25633 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x2a3 :
25634 0x2a4, (0x1 << 13), (0) << 13);
25635
25636 } else {
25637 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x2a3 :
25638 0x2a4, (0x1 << 11), (0) << 11);
25639
25640 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x2a3 :
25641 0x2a4, (0x1 << 11), (0) << 11);
25642
25643 }
25644 pi->nphy_papdcomp = NPHY_PAPD_COMP_ON;
25645
25646 write_phy_reg(pi, 0x01, phy_b9);
25647
25648 wlc_phy_ipa_set_tx_digi_filts_nphy(pi);
25649
25650 wlc_phy_txpwrctrl_enable_nphy(pi, phy_b4);
25651 if (phy_b4 == PHY_TPC_HW_OFF) {
25652 wlc_phy_txpwr_index_nphy(pi, (1 << 0),
25653 (s8) (pi->nphy_txpwrindex[0].
25654 index_internal), false);
25655 wlc_phy_txpwr_index_nphy(pi, (1 << 1),
25656 (s8) (pi->nphy_txpwrindex[1].
25657 index_internal), false);
25658 }
25659
25660 wlc_phy_stay_in_carriersearch_nphy(pi, false);
25661
25662 if (!phy_b3)
25663 wlapi_enable_mac(pi->sh->physhim);
25664}
25665
25666void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype)
25667{
25668 struct nphy_txgains target_gain;
25669 u8 tx_pwr_ctrl_state;
25670 bool fullcal = true;
25671 bool restore_tx_gain = false;
25672 bool mphase;
25673
25674 if (PHY_MUTED(pi))
25675 return;
25676
25677 if (caltype == PHY_PERICAL_AUTO)
25678 fullcal = (pi->radio_chanspec != pi->nphy_txiqlocal_chanspec);
25679 else if (caltype == PHY_PERICAL_PARTIAL)
25680 fullcal = false;
25681
25682 if (pi->cal_type_override != PHY_PERICAL_AUTO)
25683 fullcal =
25684 (pi->cal_type_override ==
25685 PHY_PERICAL_FULL) ? true : false;
25686
25687 if ((pi->mphase_cal_phase_id > MPHASE_CAL_STATE_INIT)) {
25688 if (pi->nphy_txiqlocal_chanspec != pi->radio_chanspec)
25689 wlc_phy_cal_perical_mphase_restart(pi);
25690 }
25691
25692 if ((pi->mphase_cal_phase_id == MPHASE_CAL_STATE_RXCAL))
25693 wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
25694
25695 wlapi_suspend_mac_and_wait(pi->sh->physhim);
25696
25697 wlc_phyreg_enter((struct brcms_phy_pub *) pi);
25698
25699 if ((pi->mphase_cal_phase_id == MPHASE_CAL_STATE_IDLE) ||
25700 (pi->mphase_cal_phase_id == MPHASE_CAL_STATE_INIT)) {
25701 pi->nphy_cal_orig_pwr_idx[0] =
25702 (u8) ((read_phy_reg(pi, 0x1ed) >> 8) & 0x7f);
25703 pi->nphy_cal_orig_pwr_idx[1] =
25704 (u8) ((read_phy_reg(pi, 0x1ee) >> 8) & 0x7f);
25705
25706 if (pi->nphy_txpwrctrl != PHY_TPC_HW_OFF) {
25707 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2,
25708 0x110, 16,
25709 pi->nphy_cal_orig_tx_gain);
25710 } else {
25711 pi->nphy_cal_orig_tx_gain[0] = 0;
25712 pi->nphy_cal_orig_tx_gain[1] = 0;
25713 }
25714 }
25715 target_gain = wlc_phy_get_tx_gain_nphy(pi);
25716 tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
25717 wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
25718
25719 if (pi->antsel_type == ANTSEL_2x3)
25720 wlc_phy_antsel_init((struct brcms_phy_pub *) pi, true);
25721
25722 mphase = (pi->mphase_cal_phase_id != MPHASE_CAL_STATE_IDLE);
25723 if (!mphase) {
25724
25725 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
25726 wlc_phy_precal_txgain_nphy(pi);
25727 pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi);
25728 restore_tx_gain = true;
25729
25730 target_gain = pi->nphy_cal_target_gain;
25731 }
25732 if (0 ==
25733 wlc_phy_cal_txiqlo_nphy(pi, target_gain, fullcal,
25734 mphase)) {
25735 if (PHY_IPA(pi))
25736 wlc_phy_a4(pi, true);
25737
25738 wlc_phyreg_exit((struct brcms_phy_pub *) pi);
25739 wlapi_enable_mac(pi->sh->physhim);
25740 wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION,
25741 10000);
25742 wlapi_suspend_mac_and_wait(pi->sh->physhim);
25743 wlc_phyreg_enter((struct brcms_phy_pub *) pi);
25744
25745 if (0 == wlc_phy_cal_rxiq_nphy(pi, target_gain,
25746 (pi->first_cal_after_assoc ||
25747 (pi->cal_type_override ==
25748 PHY_PERICAL_FULL)) ? 2 : 0, false)) {
25749 wlc_phy_savecal_nphy(pi);
25750
25751 wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
25752
25753 pi->nphy_perical_last = pi->sh->now;
25754 }
25755 }
25756 if (caltype != PHY_PERICAL_AUTO)
25757 wlc_phy_rssi_cal_nphy(pi);
25758
25759 if (pi->first_cal_after_assoc
25760 || (pi->cal_type_override == PHY_PERICAL_FULL)) {
25761 pi->first_cal_after_assoc = false;
25762 wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
25763 wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
25764 }
25765
25766 if (NREV_GE(pi->pubpi.phy_rev, 3))
25767 wlc_phy_radio205x_vcocal_nphy(pi);
25768 } else {
25769 switch (pi->mphase_cal_phase_id) {
25770 case MPHASE_CAL_STATE_INIT:
25771 pi->nphy_perical_last = pi->sh->now;
25772 pi->nphy_txiqlocal_chanspec = pi->radio_chanspec;
25773
25774 if (NREV_GE(pi->pubpi.phy_rev, 3))
25775 wlc_phy_precal_txgain_nphy(pi);
25776
25777 pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi);
25778 pi->mphase_cal_phase_id++;
25779 break;
25780
25781 case MPHASE_CAL_STATE_TXPHASE0:
25782 case MPHASE_CAL_STATE_TXPHASE1:
25783 case MPHASE_CAL_STATE_TXPHASE2:
25784 case MPHASE_CAL_STATE_TXPHASE3:
25785 case MPHASE_CAL_STATE_TXPHASE4:
25786 case MPHASE_CAL_STATE_TXPHASE5:
25787 if ((pi->radar_percal_mask & 0x10) != 0)
25788 pi->nphy_rxcal_active = true;
25789
25790 if (wlc_phy_cal_txiqlo_nphy
25791 (pi, pi->nphy_cal_target_gain, fullcal,
25792 true) != 0) {
25793
25794 wlc_phy_cal_perical_mphase_reset(pi);
25795 break;
25796 }
25797
25798 if (NREV_LE(pi->pubpi.phy_rev, 2) &&
25799 (pi->mphase_cal_phase_id ==
25800 MPHASE_CAL_STATE_TXPHASE4))
25801 pi->mphase_cal_phase_id += 2;
25802 else
25803 pi->mphase_cal_phase_id++;
25804 break;
25805
25806 case MPHASE_CAL_STATE_PAPDCAL:
25807 if ((pi->radar_percal_mask & 0x2) != 0)
25808 pi->nphy_rxcal_active = true;
25809
25810 if (PHY_IPA(pi))
25811 wlc_phy_a4(pi, true);
25812
25813 pi->mphase_cal_phase_id++;
25814 break;
25815
25816 case MPHASE_CAL_STATE_RXCAL:
25817 if ((pi->radar_percal_mask & 0x1) != 0)
25818 pi->nphy_rxcal_active = true;
25819 if (wlc_phy_cal_rxiq_nphy(pi, target_gain,
25820 (pi->first_cal_after_assoc ||
25821 (pi->cal_type_override ==
25822 PHY_PERICAL_FULL)) ? 2 : 0,
25823 false) == 0)
25824 wlc_phy_savecal_nphy(pi);
25825
25826 pi->mphase_cal_phase_id++;
25827 break;
25828
25829 case MPHASE_CAL_STATE_RSSICAL:
25830 if ((pi->radar_percal_mask & 0x4) != 0)
25831 pi->nphy_rxcal_active = true;
25832 wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
25833 wlc_phy_rssi_cal_nphy(pi);
25834
25835 if (NREV_GE(pi->pubpi.phy_rev, 3))
25836 wlc_phy_radio205x_vcocal_nphy(pi);
25837
25838 restore_tx_gain = true;
25839
25840 if (pi->first_cal_after_assoc)
25841 pi->mphase_cal_phase_id++;
25842 else
25843 wlc_phy_cal_perical_mphase_reset(pi);
25844
25845 break;
25846
25847 case MPHASE_CAL_STATE_IDLETSSI:
25848 if ((pi->radar_percal_mask & 0x8) != 0)
25849 pi->nphy_rxcal_active = true;
25850
25851 if (pi->first_cal_after_assoc) {
25852 pi->first_cal_after_assoc = false;
25853 wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
25854 wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
25855 }
25856
25857 wlc_phy_cal_perical_mphase_reset(pi);
25858 break;
25859
25860 default:
25861 wlc_phy_cal_perical_mphase_reset(pi);
25862 break;
25863 }
25864 }
25865
25866 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
25867 if (restore_tx_gain) {
25868 if (tx_pwr_ctrl_state != PHY_TPC_HW_OFF) {
25869
25870 wlc_phy_txpwr_index_nphy(pi, 1,
25871 pi->
25872 nphy_cal_orig_pwr_idx
25873 [0], false);
25874 wlc_phy_txpwr_index_nphy(pi, 2,
25875 pi->
25876 nphy_cal_orig_pwr_idx
25877 [1], false);
25878
25879 pi->nphy_txpwrindex[0].index = -1;
25880 pi->nphy_txpwrindex[1].index = -1;
25881 } else {
25882 wlc_phy_txpwr_index_nphy(pi, (1 << 0),
25883 (s8) (pi->
25884 nphy_txpwrindex
25885 [0].
25886 index_internal),
25887 false);
25888 wlc_phy_txpwr_index_nphy(pi, (1 << 1),
25889 (s8) (pi->
25890 nphy_txpwrindex
25891 [1].
25892 index_internal),
25893 false);
25894 }
25895 }
25896 }
25897
25898 wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
25899 wlc_phyreg_exit((struct brcms_phy_pub *) pi);
25900 wlapi_enable_mac(pi->sh->physhim);
25901}
25902
25903int
25904wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi, struct nphy_txgains target_gain,
25905 bool fullcal, bool mphase)
25906{
25907 u16 val;
25908 u16 tbl_buf[11];
25909 u8 cal_cnt;
25910 u16 cal_cmd;
25911 u8 num_cals, max_cal_cmds;
25912 u16 core_no, cal_type;
25913 u16 diq_start = 0;
25914 u8 phy_bw;
25915 u16 max_val;
25916 u16 tone_freq;
25917 u16 gain_save[2];
25918 u16 cal_gain[2];
25919 struct nphy_iqcal_params cal_params[2];
25920 u32 tbl_len;
25921 void *tbl_ptr;
25922 bool ladder_updated[2];
25923 u8 mphase_cal_lastphase = 0;
25924 int bcmerror = 0;
25925 bool phyhang_avoid_state = false;
25926
25927 u16 tbl_tx_iqlo_cal_loft_ladder_20[] = {
25928 0x0300, 0x0500, 0x0700, 0x0900, 0x0d00, 0x1100, 0x1900, 0x1901,
25929 0x1902,
25930 0x1903, 0x1904, 0x1905, 0x1906, 0x1907, 0x2407, 0x3207, 0x4607,
25931 0x6407
25932 };
25933
25934 u16 tbl_tx_iqlo_cal_iqimb_ladder_20[] = {
25935 0x0200, 0x0300, 0x0600, 0x0900, 0x0d00, 0x1100, 0x1900, 0x2400,
25936 0x3200,
25937 0x4600, 0x6400, 0x6401, 0x6402, 0x6403, 0x6404, 0x6405, 0x6406,
25938 0x6407
25939 };
25940
25941 u16 tbl_tx_iqlo_cal_loft_ladder_40[] = {
25942 0x0200, 0x0300, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1201,
25943 0x1202,
25944 0x1203, 0x1204, 0x1205, 0x1206, 0x1207, 0x1907, 0x2307, 0x3207,
25945 0x4707
25946 };
25947
25948 u16 tbl_tx_iqlo_cal_iqimb_ladder_40[] = {
25949 0x0100, 0x0200, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1900,
25950 0x2300,
25951 0x3200, 0x4700, 0x4701, 0x4702, 0x4703, 0x4704, 0x4705, 0x4706,
25952 0x4707
25953 };
25954
25955 u16 tbl_tx_iqlo_cal_startcoefs[] = {
25956 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
25957 0x0000
25958 };
25959
25960 u16 tbl_tx_iqlo_cal_cmds_fullcal[] = {
25961 0x8123, 0x8264, 0x8086, 0x8245, 0x8056,
25962 0x9123, 0x9264, 0x9086, 0x9245, 0x9056
25963 };
25964
25965 u16 tbl_tx_iqlo_cal_cmds_recal[] = {
25966 0x8101, 0x8253, 0x8053, 0x8234, 0x8034,
25967 0x9101, 0x9253, 0x9053, 0x9234, 0x9034
25968 };
25969
25970 u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[] = {
25971 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
25972 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
25973 0x0000
25974 };
25975
25976 u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = {
25977 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234,
25978 0x9434, 0x9334, 0x9084, 0x9267, 0x9056, 0x9234
25979 };
25980
25981 u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = {
25982 0x8423, 0x8323, 0x8073, 0x8256, 0x8045, 0x8223,
25983 0x9423, 0x9323, 0x9073, 0x9256, 0x9045, 0x9223
25984 };
25985
25986 wlc_phy_stay_in_carriersearch_nphy(pi, true);
25987
25988 if (NREV_GE(pi->pubpi.phy_rev, 4)) {
25989 phyhang_avoid_state = pi->phyhang_avoid;
25990 pi->phyhang_avoid = false;
25991 }
25992
25993 if (CHSPEC_IS40(pi->radio_chanspec))
25994 phy_bw = 40;
25995 else
25996 phy_bw = 20;
25997
25998 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
25999
26000 for (core_no = 0; core_no <= 1; core_no++) {
26001 wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
26002 &cal_params[core_no]);
26003 cal_gain[core_no] = cal_params[core_no].cal_gain;
26004 }
26005
26006 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
26007
26008 wlc_phy_txcal_radio_setup_nphy(pi);
26009
26010 wlc_phy_txcal_physetup_nphy(pi);
26011
26012 ladder_updated[0] = ladder_updated[1] = false;
26013 if (!(NREV_GE(pi->pubpi.phy_rev, 6) ||
26014 (NREV_IS(pi->pubpi.phy_rev, 5) && PHY_IPA(pi)
26015 && (CHSPEC_IS2G(pi->radio_chanspec))))) {
26016
26017 if (phy_bw == 40) {
26018 tbl_ptr = tbl_tx_iqlo_cal_loft_ladder_40;
26019 tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_loft_ladder_40);
26020 } else {
26021 tbl_ptr = tbl_tx_iqlo_cal_loft_ladder_20;
26022 tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_loft_ladder_20);
26023 }
26024 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 0,
26025 16, tbl_ptr);
26026
26027 if (phy_bw == 40) {
26028 tbl_ptr = tbl_tx_iqlo_cal_iqimb_ladder_40;
26029 tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_iqimb_ladder_40);
26030 } else {
26031 tbl_ptr = tbl_tx_iqlo_cal_iqimb_ladder_20;
26032 tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_iqimb_ladder_20);
26033 }
26034 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 32,
26035 16, tbl_ptr);
26036 }
26037
26038 if (NREV_GE(pi->pubpi.phy_rev, 7))
26039 write_phy_reg(pi, 0xc2, 0x8ad9);
26040 else
26041 write_phy_reg(pi, 0xc2, 0x8aa9);
26042
26043 max_val = 250;
26044 tone_freq = (phy_bw == 20) ? 2500 : 5000;
26045
26046 if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
26047 wlc_phy_runsamples_nphy(pi, phy_bw * 8, 0xffff, 0, 1, 0, false);
26048 bcmerror = 0;
26049 } else {
26050 bcmerror =
26051 wlc_phy_tx_tone_nphy(pi, tone_freq, max_val, 1, 0,
26052 false);
26053 }
26054
26055 if (bcmerror == 0) {
26056
26057 if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
26058 tbl_ptr = pi->mphase_txcal_bestcoeffs;
26059 tbl_len = ARRAY_SIZE(pi->mphase_txcal_bestcoeffs);
26060 if (NREV_LT(pi->pubpi.phy_rev, 3))
26061 tbl_len -= 2;
26062 } else {
26063 if ((!fullcal) && (pi->nphy_txiqlocal_coeffsvalid)) {
26064
26065 tbl_ptr = pi->nphy_txiqlocal_bestc;
26066 tbl_len = ARRAY_SIZE(pi->nphy_txiqlocal_bestc);
26067 if (NREV_LT(pi->pubpi.phy_rev, 3))
26068 tbl_len -= 2;
26069 } else {
26070
26071 fullcal = true;
26072
26073 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
26074 tbl_ptr =
26075 tbl_tx_iqlo_cal_startcoefs_nphyrev3;
26076 tbl_len = ARRAY_SIZE(
26077 tbl_tx_iqlo_cal_startcoefs_nphyrev3);
26078 } else {
26079 tbl_ptr = tbl_tx_iqlo_cal_startcoefs;
26080 tbl_len = ARRAY_SIZE(
26081 tbl_tx_iqlo_cal_startcoefs);
26082 }
26083 }
26084 }
26085 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 64,
26086 16, tbl_ptr);
26087
26088 if (fullcal) {
26089 max_cal_cmds = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
26090 ARRAY_SIZE(
26091 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3) :
26092 ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_fullcal);
26093 } else {
26094 max_cal_cmds = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
26095 ARRAY_SIZE(
26096 tbl_tx_iqlo_cal_cmds_recal_nphyrev3) :
26097 ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_recal);
26098 }
26099
26100 if (mphase) {
26101 cal_cnt = pi->mphase_txcal_cmdidx;
26102 if ((cal_cnt + pi->mphase_txcal_numcmds) < max_cal_cmds)
26103 num_cals = cal_cnt + pi->mphase_txcal_numcmds;
26104 else
26105 num_cals = max_cal_cmds;
26106 } else {
26107 cal_cnt = 0;
26108 num_cals = max_cal_cmds;
26109 }
26110
26111 for (; cal_cnt < num_cals; cal_cnt++) {
26112
26113 if (fullcal) {
26114 cal_cmd = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
26115 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3
26116 [cal_cnt] :
26117 tbl_tx_iqlo_cal_cmds_fullcal[cal_cnt];
26118 } else {
26119 cal_cmd = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
26120 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[
26121 cal_cnt]
26122 : tbl_tx_iqlo_cal_cmds_recal[cal_cnt];
26123 }
26124
26125 core_no = ((cal_cmd & 0x3000) >> 12);
26126 cal_type = ((cal_cmd & 0x0F00) >> 8);
26127
26128 if (NREV_GE(pi->pubpi.phy_rev, 6) ||
26129 (NREV_IS(pi->pubpi.phy_rev, 5) &&
26130 PHY_IPA(pi)
26131 && (CHSPEC_IS2G(pi->radio_chanspec)))) {
26132 if (!ladder_updated[core_no]) {
26133 wlc_phy_update_txcal_ladder_nphy(
26134 pi,
26135 core_no);
26136 ladder_updated[core_no] = true;
26137 }
26138 }
26139
26140 val =
26141 (cal_params[core_no].
26142 ncorr[cal_type] << 8) | NPHY_N_GCTL;
26143 write_phy_reg(pi, 0xc1, val);
26144
26145 if ((cal_type == 1) || (cal_type == 3)
26146 || (cal_type == 4)) {
26147
26148 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
26149 1, 69 + core_no, 16,
26150 tbl_buf);
26151
26152 diq_start = tbl_buf[0];
26153
26154 tbl_buf[0] = 0;
26155 wlc_phy_table_write_nphy(pi,
26156 NPHY_TBL_ID_IQLOCAL, 1,
26157 69 + core_no, 16,
26158 tbl_buf);
26159 }
26160
26161 write_phy_reg(pi, 0xc0, cal_cmd);
26162
26163 SPINWAIT(((read_phy_reg(pi, 0xc0) & 0xc000) != 0),
26164 20000);
26165 if (WARN(read_phy_reg(pi, 0xc0) & 0xc000,
26166 "HW error: txiq calib"))
26167 return -EIO;
26168
26169 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
26170 tbl_len, 96, 16, tbl_buf);
26171 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL,
26172 tbl_len, 64, 16, tbl_buf);
26173
26174 if ((cal_type == 1) || (cal_type == 3)
26175 || (cal_type == 4)) {
26176
26177 tbl_buf[0] = diq_start;
26178
26179 }
26180
26181 }
26182
26183 if (mphase) {
26184 pi->mphase_txcal_cmdidx = num_cals;
26185 if (pi->mphase_txcal_cmdidx >= max_cal_cmds)
26186 pi->mphase_txcal_cmdidx = 0;
26187 }
26188
26189 mphase_cal_lastphase =
26190 (NREV_LE(pi->pubpi.phy_rev, 2)) ?
26191 MPHASE_CAL_STATE_TXPHASE4 : MPHASE_CAL_STATE_TXPHASE5;
26192
26193 if (!mphase
26194 || (pi->mphase_cal_phase_id == mphase_cal_lastphase)) {
26195
26196 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 96,
26197 16, tbl_buf);
26198 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80,
26199 16, tbl_buf);
26200
26201 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
26202
26203 tbl_buf[0] = 0;
26204 tbl_buf[1] = 0;
26205 tbl_buf[2] = 0;
26206 tbl_buf[3] = 0;
26207
26208 }
26209 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88,
26210 16, tbl_buf);
26211
26212 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 101,
26213 16, tbl_buf);
26214 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85,
26215 16, tbl_buf);
26216
26217 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93,
26218 16, tbl_buf);
26219
26220 tbl_len = ARRAY_SIZE(pi->nphy_txiqlocal_bestc);
26221 if (NREV_LT(pi->pubpi.phy_rev, 3))
26222 tbl_len -= 2;
26223
26224 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
26225 tbl_len, 96, 16,
26226 pi->nphy_txiqlocal_bestc);
26227
26228 pi->nphy_txiqlocal_coeffsvalid = true;
26229 pi->nphy_txiqlocal_chanspec = pi->radio_chanspec;
26230 } else {
26231 tbl_len = ARRAY_SIZE(pi->mphase_txcal_bestcoeffs);
26232 if (NREV_LT(pi->pubpi.phy_rev, 3))
26233 tbl_len -= 2;
26234
26235 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
26236 tbl_len, 96, 16,
26237 pi->mphase_txcal_bestcoeffs);
26238 }
26239
26240 wlc_phy_stopplayback_nphy(pi);
26241
26242 write_phy_reg(pi, 0xc2, 0x0000);
26243
26244 }
26245
26246 wlc_phy_txcal_phycleanup_nphy(pi);
26247
26248 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
26249 gain_save);
26250
26251 wlc_phy_txcal_radio_cleanup_nphy(pi);
26252
26253 if (NREV_LT(pi->pubpi.phy_rev, 2)) {
26254 if (!mphase
26255 || (pi->mphase_cal_phase_id == mphase_cal_lastphase))
26256 wlc_phy_tx_iq_war_nphy(pi);
26257 }
26258
26259 if (NREV_GE(pi->pubpi.phy_rev, 4))
26260 pi->phyhang_avoid = phyhang_avoid_state;
26261
26262 wlc_phy_stay_in_carriersearch_nphy(pi, false);
26263
26264 return bcmerror;
26265}
26266
26267static void wlc_phy_reapply_txcal_coeffs_nphy(struct brcms_phy *pi)
26268{
26269 u16 tbl_buf[7];
26270
26271 if ((pi->nphy_txiqlocal_chanspec == pi->radio_chanspec) &&
26272 (pi->nphy_txiqlocal_coeffsvalid)) {
26273 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
26274 ARRAY_SIZE(tbl_buf), 80, 16, tbl_buf);
26275
26276 if ((pi->nphy_txiqlocal_bestc[0] != tbl_buf[0]) ||
26277 (pi->nphy_txiqlocal_bestc[1] != tbl_buf[1]) ||
26278 (pi->nphy_txiqlocal_bestc[2] != tbl_buf[2]) ||
26279 (pi->nphy_txiqlocal_bestc[3] != tbl_buf[3])) {
26280
26281 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80,
26282 16, pi->nphy_txiqlocal_bestc);
26283
26284 tbl_buf[0] = 0;
26285 tbl_buf[1] = 0;
26286 tbl_buf[2] = 0;
26287 tbl_buf[3] = 0;
26288 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88,
26289 16, tbl_buf);
26290
26291 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85,
26292 16,
26293 &pi->nphy_txiqlocal_bestc[5]);
26294
26295 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93,
26296 16,
26297 &pi->nphy_txiqlocal_bestc[5]);
26298 }
26299 }
26300}
26301
26302void
26303wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
26304 struct nphy_iq_comp *pcomp)
26305{
26306 if (write) {
26307 write_phy_reg(pi, 0x9a, pcomp->a0);
26308 write_phy_reg(pi, 0x9b, pcomp->b0);
26309 write_phy_reg(pi, 0x9c, pcomp->a1);
26310 write_phy_reg(pi, 0x9d, pcomp->b1);
26311 } else {
26312 pcomp->a0 = read_phy_reg(pi, 0x9a);
26313 pcomp->b0 = read_phy_reg(pi, 0x9b);
26314 pcomp->a1 = read_phy_reg(pi, 0x9c);
26315 pcomp->b1 = read_phy_reg(pi, 0x9d);
26316 }
26317}
26318
26319void
26320wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
26321 u16 num_samps, u8 wait_time, u8 wait_for_crs)
26322{
26323 u8 core;
26324
26325 write_phy_reg(pi, 0x12b, num_samps);
26326 mod_phy_reg(pi, 0x12a, (0xff << 0), (wait_time << 0));
26327 mod_phy_reg(pi, 0x129, NPHY_IqestCmd_iqMode,
26328 (wait_for_crs) ? NPHY_IqestCmd_iqMode : 0);
26329
26330 mod_phy_reg(pi, 0x129, NPHY_IqestCmd_iqstart, NPHY_IqestCmd_iqstart);
26331
26332 SPINWAIT(((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) != 0),
26333 10000);
26334 if (WARN(read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart,
26335 "HW error: rxiq est"))
26336 return;
26337
26338 if ((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) == 0) {
26339 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
26340 est[core].i_pwr =
26341 (read_phy_reg(pi,
26342 NPHY_IqestipwrAccHi(core)) << 16)
26343 | read_phy_reg(pi, NPHY_IqestipwrAccLo(core));
26344 est[core].q_pwr =
26345 (read_phy_reg(pi,
26346 NPHY_IqestqpwrAccHi(core)) << 16)
26347 | read_phy_reg(pi, NPHY_IqestqpwrAccLo(core));
26348 est[core].iq_prod =
26349 (read_phy_reg(pi,
26350 NPHY_IqestIqAccHi(core)) << 16) |
26351 read_phy_reg(pi, NPHY_IqestIqAccLo(core));
26352 }
26353 }
26354}
26355
26356#define CAL_RETRY_CNT 2
26357static void wlc_phy_calc_rx_iq_comp_nphy(struct brcms_phy *pi, u8 core_mask)
26358{
26359 u8 curr_core;
26360 struct phy_iq_est est[PHY_CORE_MAX];
26361 struct nphy_iq_comp old_comp, new_comp;
26362 s32 iq = 0;
26363 u32 ii = 0, qq = 0;
26364 s16 iq_nbits, qq_nbits, brsh, arsh;
26365 s32 a, b, temp;
26366 int bcmerror = 0;
26367 uint cal_retry = 0;
26368
26369 if (core_mask == 0x0)
26370 return;
26371
26372 wlc_phy_rx_iq_coeffs_nphy(pi, 0, &old_comp);
26373 new_comp.a0 = new_comp.b0 = new_comp.a1 = new_comp.b1 = 0x0;
26374 wlc_phy_rx_iq_coeffs_nphy(pi, 1, &new_comp);
26375
26376cal_try:
26377 wlc_phy_rx_iq_est_nphy(pi, est, 0x4000, 32, 0);
26378
26379 new_comp = old_comp;
26380
26381 for (curr_core = 0; curr_core < pi->pubpi.phy_corenum; curr_core++) {
26382
26383 if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) {
26384 iq = est[curr_core].iq_prod;
26385 ii = est[curr_core].i_pwr;
26386 qq = est[curr_core].q_pwr;
26387 } else if ((curr_core == PHY_CORE_1) && (core_mask & 0x2)) {
26388 iq = est[curr_core].iq_prod;
26389 ii = est[curr_core].i_pwr;
26390 qq = est[curr_core].q_pwr;
26391 } else {
26392 continue;
26393 }
26394
26395 if ((ii + qq) < NPHY_MIN_RXIQ_PWR) {
26396 bcmerror = -EBADE;
26397 break;
26398 }
26399
26400 iq_nbits = wlc_phy_nbits(iq);
26401 qq_nbits = wlc_phy_nbits(qq);
26402
26403 arsh = 10 - (30 - iq_nbits);
26404 if (arsh >= 0) {
26405 a = (-(iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
26406 temp = (s32) (ii >> arsh);
26407 if (temp == 0) {
26408 bcmerror = -EBADE;
26409 break;
26410 }
26411 } else {
26412 a = (-(iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
26413 temp = (s32) (ii << -arsh);
26414 if (temp == 0) {
26415 bcmerror = -EBADE;
26416 break;
26417 }
26418 }
26419
26420 a /= temp;
26421
26422 brsh = qq_nbits - 31 + 20;
26423 if (brsh >= 0) {
26424 b = (qq << (31 - qq_nbits));
26425 temp = (s32) (ii >> brsh);
26426 if (temp == 0) {
26427 bcmerror = -EBADE;
26428 break;
26429 }
26430 } else {
26431 b = (qq << (31 - qq_nbits));
26432 temp = (s32) (ii << -brsh);
26433 if (temp == 0) {
26434 bcmerror = -EBADE;
26435 break;
26436 }
26437 }
26438 b /= temp;
26439 b -= a * a;
26440 b = (s32) int_sqrt((unsigned long) b);
26441 b -= (1 << 10);
26442
26443 if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) {
26444 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
26445 new_comp.a0 = (s16) a & 0x3ff;
26446 new_comp.b0 = (s16) b & 0x3ff;
26447 } else {
26448
26449 new_comp.a0 = (s16) b & 0x3ff;
26450 new_comp.b0 = (s16) a & 0x3ff;
26451 }
26452 }
26453 if ((curr_core == PHY_CORE_1) && (core_mask & 0x2)) {
26454 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
26455 new_comp.a1 = (s16) a & 0x3ff;
26456 new_comp.b1 = (s16) b & 0x3ff;
26457 } else {
26458
26459 new_comp.a1 = (s16) b & 0x3ff;
26460 new_comp.b1 = (s16) a & 0x3ff;
26461 }
26462 }
26463 }
26464
26465 if (bcmerror != 0) {
26466 printk(KERN_DEBUG "%s: Failed, cnt = %d\n", __func__,
26467 cal_retry);
26468
26469 if (cal_retry < CAL_RETRY_CNT) {
26470 cal_retry++;
26471 goto cal_try;
26472 }
26473
26474 new_comp = old_comp;
26475 }
26476
26477 wlc_phy_rx_iq_coeffs_nphy(pi, 1, &new_comp);
26478}
26479
26480static void wlc_phy_rxcal_radio_setup_nphy(struct brcms_phy *pi, u8 rx_core)
26481{
26482 u16 offtune_val;
26483 u16 bias_g = 0;
26484 u16 bias_a = 0;
26485
26486 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
26487 if (rx_core == PHY_CORE_0) {
26488 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26489 pi->tx_rx_cal_radio_saveregs[0] =
26490 read_radio_reg(pi,
26491 RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP);
26492 pi->tx_rx_cal_radio_saveregs[1] =
26493 read_radio_reg(pi,
26494 RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN);
26495
26496 write_radio_reg(pi,
26497 RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP,
26498 0x3);
26499 write_radio_reg(pi,
26500 RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN,
26501 0xaf);
26502
26503 } else {
26504 pi->tx_rx_cal_radio_saveregs[0] =
26505 read_radio_reg(pi,
26506 RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP);
26507 pi->tx_rx_cal_radio_saveregs[1] =
26508 read_radio_reg(pi,
26509 RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN);
26510
26511 write_radio_reg(
26512 pi,
26513 RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP,
26514 0x3);
26515 write_radio_reg(
26516 pi,
26517 RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN,
26518 0x7f);
26519 }
26520
26521 } else {
26522 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26523 pi->tx_rx_cal_radio_saveregs[0] =
26524 read_radio_reg(pi,
26525 RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP);
26526 pi->tx_rx_cal_radio_saveregs[1] =
26527 read_radio_reg(pi,
26528 RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN);
26529
26530 write_radio_reg(
26531 pi,
26532 RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP,
26533 0x3);
26534 write_radio_reg(
26535 pi,
26536 RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN,
26537 0xaf);
26538
26539 } else {
26540 pi->tx_rx_cal_radio_saveregs[0] =
26541 read_radio_reg(pi,
26542 RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP);
26543 pi->tx_rx_cal_radio_saveregs[1] =
26544 read_radio_reg(pi,
26545 RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN);
26546
26547 write_radio_reg(pi,
26548 RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP,
26549 0x3);
26550 write_radio_reg(pi,
26551 RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN,
26552 0x7f);
26553 }
26554 }
26555
26556 } else {
26557 if (rx_core == PHY_CORE_0) {
26558 pi->tx_rx_cal_radio_saveregs[0] =
26559 read_radio_reg(pi,
26560 RADIO_2056_TX_RXIQCAL_TXMUX |
26561 RADIO_2056_TX1);
26562 pi->tx_rx_cal_radio_saveregs[1] =
26563 read_radio_reg(pi,
26564 RADIO_2056_RX_RXIQCAL_RXMUX |
26565 RADIO_2056_RX0);
26566
26567 if (pi->pubpi.radiorev >= 5) {
26568 pi->tx_rx_cal_radio_saveregs[2] =
26569 read_radio_reg(pi,
26570 RADIO_2056_RX_RXSPARE2 |
26571 RADIO_2056_RX0);
26572 pi->tx_rx_cal_radio_saveregs[3] =
26573 read_radio_reg(pi,
26574 RADIO_2056_TX_TXSPARE2 |
26575 RADIO_2056_TX1);
26576 }
26577
26578 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26579
26580 if (pi->pubpi.radiorev >= 5) {
26581 pi->tx_rx_cal_radio_saveregs[4] =
26582 read_radio_reg(pi,
26583 RADIO_2056_RX_LNAA_MASTER
26584 | RADIO_2056_RX0);
26585
26586 write_radio_reg(
26587 pi,
26588 RADIO_2056_RX_LNAA_MASTER
26589 | RADIO_2056_RX0, 0x40);
26590
26591 write_radio_reg(pi,
26592 RADIO_2056_TX_TXSPARE2 |
26593 RADIO_2056_TX1, bias_a);
26594
26595 write_radio_reg(pi,
26596 RADIO_2056_RX_RXSPARE2 |
26597 RADIO_2056_RX0, bias_a);
26598 } else {
26599 pi->tx_rx_cal_radio_saveregs[4] =
26600 read_radio_reg(pi,
26601 RADIO_2056_RX_LNAA_TUNE
26602 | RADIO_2056_RX0);
26603
26604 offtune_val =
26605 (pi->tx_rx_cal_radio_saveregs
26606 [2] & 0xF0) >> 8;
26607 offtune_val =
26608 (offtune_val <= 0x7) ? 0xF : 0;
26609
26610 mod_radio_reg(pi,
26611 RADIO_2056_RX_LNAA_TUNE |
26612 RADIO_2056_RX0, 0xF0,
26613 (offtune_val << 8));
26614 }
26615
26616 write_radio_reg(pi,
26617 RADIO_2056_TX_RXIQCAL_TXMUX |
26618 RADIO_2056_TX1, 0x9);
26619 write_radio_reg(pi,
26620 RADIO_2056_RX_RXIQCAL_RXMUX |
26621 RADIO_2056_RX0, 0x9);
26622 } else {
26623 if (pi->pubpi.radiorev >= 5) {
26624 pi->tx_rx_cal_radio_saveregs[4] =
26625 read_radio_reg(
26626 pi,
26627 RADIO_2056_RX_LNAG_MASTER
26628 | RADIO_2056_RX0);
26629
26630 write_radio_reg(
26631 pi,
26632 RADIO_2056_RX_LNAG_MASTER
26633 | RADIO_2056_RX0, 0x40);
26634
26635 write_radio_reg(
26636 pi,
26637 RADIO_2056_TX_TXSPARE2
26638 |
26639 RADIO_2056_TX1, bias_g);
26640
26641 write_radio_reg(
26642 pi,
26643 RADIO_2056_RX_RXSPARE2
26644 |
26645 RADIO_2056_RX0, bias_g);
26646
26647 } else {
26648 pi->tx_rx_cal_radio_saveregs[4] =
26649 read_radio_reg(
26650 pi,
26651 RADIO_2056_RX_LNAG_TUNE
26652 | RADIO_2056_RX0);
26653
26654 offtune_val =
26655 (pi->
26656 tx_rx_cal_radio_saveregs[2] &
26657 0xF0) >> 8;
26658 offtune_val =
26659 (offtune_val <= 0x7) ? 0xF : 0;
26660
26661 mod_radio_reg(pi,
26662 RADIO_2056_RX_LNAG_TUNE |
26663 RADIO_2056_RX0, 0xF0,
26664 (offtune_val << 8));
26665 }
26666
26667 write_radio_reg(pi,
26668 RADIO_2056_TX_RXIQCAL_TXMUX |
26669 RADIO_2056_TX1, 0x6);
26670 write_radio_reg(pi,
26671 RADIO_2056_RX_RXIQCAL_RXMUX |
26672 RADIO_2056_RX0, 0x6);
26673 }
26674
26675 } else {
26676 pi->tx_rx_cal_radio_saveregs[0] =
26677 read_radio_reg(pi,
26678 RADIO_2056_TX_RXIQCAL_TXMUX |
26679 RADIO_2056_TX0);
26680 pi->tx_rx_cal_radio_saveregs[1] =
26681 read_radio_reg(pi,
26682 RADIO_2056_RX_RXIQCAL_RXMUX |
26683 RADIO_2056_RX1);
26684
26685 if (pi->pubpi.radiorev >= 5) {
26686 pi->tx_rx_cal_radio_saveregs[2] =
26687 read_radio_reg(pi,
26688 RADIO_2056_RX_RXSPARE2 |
26689 RADIO_2056_RX1);
26690 pi->tx_rx_cal_radio_saveregs[3] =
26691 read_radio_reg(pi,
26692 RADIO_2056_TX_TXSPARE2 |
26693 RADIO_2056_TX0);
26694 }
26695
26696 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26697
26698 if (pi->pubpi.radiorev >= 5) {
26699 pi->tx_rx_cal_radio_saveregs[4] =
26700 read_radio_reg(
26701 pi,
26702 RADIO_2056_RX_LNAA_MASTER
26703 | RADIO_2056_RX1);
26704
26705 write_radio_reg(
26706 pi,
26707 RADIO_2056_RX_LNAA_MASTER |
26708 RADIO_2056_RX1, 0x40);
26709
26710 write_radio_reg(
26711 pi,
26712 RADIO_2056_TX_TXSPARE2
26713 |
26714 RADIO_2056_TX0, bias_a);
26715
26716 write_radio_reg(
26717 pi,
26718 RADIO_2056_RX_RXSPARE2
26719 |
26720 RADIO_2056_RX1, bias_a);
26721 } else {
26722 pi->tx_rx_cal_radio_saveregs[4] =
26723 read_radio_reg(
26724 pi,
26725 RADIO_2056_RX_LNAA_TUNE
26726 | RADIO_2056_RX1);
26727
26728 offtune_val =
26729 (pi->
26730 tx_rx_cal_radio_saveregs[2] &
26731 0xF0) >> 8;
26732 offtune_val =
26733 (offtune_val <= 0x7) ? 0xF : 0;
26734
26735 mod_radio_reg(pi,
26736 RADIO_2056_RX_LNAA_TUNE |
26737 RADIO_2056_RX1, 0xF0,
26738 (offtune_val << 8));
26739 }
26740
26741 write_radio_reg(pi,
26742 RADIO_2056_TX_RXIQCAL_TXMUX |
26743 RADIO_2056_TX0, 0x9);
26744 write_radio_reg(pi,
26745 RADIO_2056_RX_RXIQCAL_RXMUX |
26746 RADIO_2056_RX1, 0x9);
26747 } else {
26748 if (pi->pubpi.radiorev >= 5) {
26749 pi->tx_rx_cal_radio_saveregs[4] =
26750 read_radio_reg(
26751 pi,
26752 RADIO_2056_RX_LNAG_MASTER
26753 | RADIO_2056_RX1);
26754
26755 write_radio_reg(
26756 pi,
26757 RADIO_2056_RX_LNAG_MASTER
26758 | RADIO_2056_RX1, 0x40);
26759
26760 write_radio_reg(
26761 pi,
26762 RADIO_2056_TX_TXSPARE2
26763 |
26764 RADIO_2056_TX0, bias_g);
26765
26766 write_radio_reg(
26767 pi,
26768 RADIO_2056_RX_RXSPARE2
26769 |
26770 RADIO_2056_RX1, bias_g);
26771 } else {
26772 pi->tx_rx_cal_radio_saveregs[4] =
26773 read_radio_reg(
26774 pi,
26775 RADIO_2056_RX_LNAG_TUNE
26776 | RADIO_2056_RX1);
26777
26778 offtune_val =
26779 (pi->
26780 tx_rx_cal_radio_saveregs[2] &
26781 0xF0) >> 8;
26782 offtune_val =
26783 (offtune_val <= 0x7) ? 0xF : 0;
26784
26785 mod_radio_reg(pi,
26786 RADIO_2056_RX_LNAG_TUNE |
26787 RADIO_2056_RX1, 0xF0,
26788 (offtune_val << 8));
26789 }
26790
26791 write_radio_reg(pi,
26792 RADIO_2056_TX_RXIQCAL_TXMUX |
26793 RADIO_2056_TX0, 0x6);
26794 write_radio_reg(pi,
26795 RADIO_2056_RX_RXIQCAL_RXMUX |
26796 RADIO_2056_RX1, 0x6);
26797 }
26798 }
26799 }
26800}
26801
26802static void wlc_phy_rxcal_radio_cleanup_nphy(struct brcms_phy *pi, u8 rx_core)
26803{
26804 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
26805 if (rx_core == PHY_CORE_0) {
26806 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26807 write_radio_reg(
26808 pi,
26809 RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP,
26810 pi->
26811 tx_rx_cal_radio_saveregs[0]);
26812 write_radio_reg(
26813 pi,
26814 RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN,
26815 pi->
26816 tx_rx_cal_radio_saveregs[1]);
26817
26818 } else {
26819 write_radio_reg(
26820 pi,
26821 RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP,
26822 pi->
26823 tx_rx_cal_radio_saveregs[0]);
26824 write_radio_reg(
26825 pi,
26826 RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN,
26827 pi->
26828 tx_rx_cal_radio_saveregs[1]);
26829 }
26830
26831 } else {
26832 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26833 write_radio_reg(
26834 pi,
26835 RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP,
26836 pi->
26837 tx_rx_cal_radio_saveregs[0]);
26838 write_radio_reg(
26839 pi,
26840 RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN,
26841 pi->
26842 tx_rx_cal_radio_saveregs[1]);
26843
26844 } else {
26845 write_radio_reg(
26846 pi,
26847 RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP,
26848 pi->
26849 tx_rx_cal_radio_saveregs[0]);
26850 write_radio_reg(
26851 pi,
26852 RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN,
26853 pi->
26854 tx_rx_cal_radio_saveregs[1]);
26855 }
26856 }
26857
26858 } else {
26859 if (rx_core == PHY_CORE_0) {
26860 write_radio_reg(pi,
26861 RADIO_2056_TX_RXIQCAL_TXMUX |
26862 RADIO_2056_TX1,
26863 pi->tx_rx_cal_radio_saveregs[0]);
26864
26865 write_radio_reg(pi,
26866 RADIO_2056_RX_RXIQCAL_RXMUX |
26867 RADIO_2056_RX0,
26868 pi->tx_rx_cal_radio_saveregs[1]);
26869
26870 if (pi->pubpi.radiorev >= 5) {
26871 write_radio_reg(pi,
26872 RADIO_2056_RX_RXSPARE2 |
26873 RADIO_2056_RX0,
26874 pi->
26875 tx_rx_cal_radio_saveregs[2]);
26876
26877 write_radio_reg(pi,
26878 RADIO_2056_TX_TXSPARE2 |
26879 RADIO_2056_TX1,
26880 pi->
26881 tx_rx_cal_radio_saveregs[3]);
26882 }
26883
26884 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26885 if (pi->pubpi.radiorev >= 5)
26886 write_radio_reg(
26887 pi,
26888 RADIO_2056_RX_LNAA_MASTER
26889 | RADIO_2056_RX0,
26890 pi->
26891 tx_rx_cal_radio_saveregs
26892 [4]);
26893 else
26894 write_radio_reg(
26895 pi,
26896 RADIO_2056_RX_LNAA_TUNE
26897 | RADIO_2056_RX0,
26898 pi->
26899 tx_rx_cal_radio_saveregs
26900 [4]);
26901 } else {
26902 if (pi->pubpi.radiorev >= 5)
26903 write_radio_reg(
26904 pi,
26905 RADIO_2056_RX_LNAG_MASTER
26906 | RADIO_2056_RX0,
26907 pi->
26908 tx_rx_cal_radio_saveregs
26909 [4]);
26910 else
26911 write_radio_reg(
26912 pi,
26913 RADIO_2056_RX_LNAG_TUNE
26914 | RADIO_2056_RX0,
26915 pi->
26916 tx_rx_cal_radio_saveregs
26917 [4]);
26918 }
26919
26920 } else {
26921 write_radio_reg(pi,
26922 RADIO_2056_TX_RXIQCAL_TXMUX |
26923 RADIO_2056_TX0,
26924 pi->tx_rx_cal_radio_saveregs[0]);
26925
26926 write_radio_reg(pi,
26927 RADIO_2056_RX_RXIQCAL_RXMUX |
26928 RADIO_2056_RX1,
26929 pi->tx_rx_cal_radio_saveregs[1]);
26930
26931 if (pi->pubpi.radiorev >= 5) {
26932 write_radio_reg(pi,
26933 RADIO_2056_RX_RXSPARE2 |
26934 RADIO_2056_RX1,
26935 pi->
26936 tx_rx_cal_radio_saveregs[2]);
26937
26938 write_radio_reg(pi,
26939 RADIO_2056_TX_TXSPARE2 |
26940 RADIO_2056_TX0,
26941 pi->
26942 tx_rx_cal_radio_saveregs[3]);
26943 }
26944
26945 if (CHSPEC_IS5G(pi->radio_chanspec)) {
26946 if (pi->pubpi.radiorev >= 5)
26947 write_radio_reg(
26948 pi,
26949 RADIO_2056_RX_LNAA_MASTER
26950 | RADIO_2056_RX1,
26951 pi->
26952 tx_rx_cal_radio_saveregs
26953 [4]);
26954 else
26955 write_radio_reg(
26956 pi,
26957 RADIO_2056_RX_LNAA_TUNE
26958 | RADIO_2056_RX1,
26959 pi->
26960 tx_rx_cal_radio_saveregs
26961 [4]);
26962 } else {
26963 if (pi->pubpi.radiorev >= 5)
26964 write_radio_reg(
26965 pi,
26966 RADIO_2056_RX_LNAG_MASTER
26967 | RADIO_2056_RX1,
26968 pi->
26969 tx_rx_cal_radio_saveregs
26970 [4]);
26971 else
26972 write_radio_reg(
26973 pi,
26974 RADIO_2056_RX_LNAG_TUNE
26975 | RADIO_2056_RX1,
26976 pi->
26977 tx_rx_cal_radio_saveregs
26978 [4]);
26979 }
26980 }
26981 }
26982}
26983
26984static void wlc_phy_rxcal_physetup_nphy(struct brcms_phy *pi, u8 rx_core)
26985{
26986 u8 tx_core;
26987 u16 rx_antval, tx_antval;
26988
26989 if (NREV_GE(pi->pubpi.phy_rev, 7))
26990 tx_core = rx_core;
26991 else
26992 tx_core = (rx_core == PHY_CORE_0) ? 1 : 0;
26993
26994 pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa2);
26995 pi->tx_rx_cal_phy_saveregs[1] =
26996 read_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 : 0xa7);
26997 pi->tx_rx_cal_phy_saveregs[2] =
26998 read_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5);
26999 pi->tx_rx_cal_phy_saveregs[3] = read_phy_reg(pi, 0x91);
27000 pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 0x92);
27001 pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 0x7a);
27002 pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 0x7d);
27003 pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 0xe7);
27004 pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 0xec);
27005 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
27006 pi->tx_rx_cal_phy_saveregs[11] = read_phy_reg(pi, 0x342);
27007 pi->tx_rx_cal_phy_saveregs[12] = read_phy_reg(pi, 0x343);
27008 pi->tx_rx_cal_phy_saveregs[13] = read_phy_reg(pi, 0x346);
27009 pi->tx_rx_cal_phy_saveregs[14] = read_phy_reg(pi, 0x347);
27010 }
27011
27012 pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 0x297);
27013 pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 0x29b);
27014 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
27015 0x29b, (0x1 << 0), (0) << 0);
27016
27017 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
27018 0x29b, (0x1 << 0), (0) << 0);
27019
27020 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
27021
27022 mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
27023
27024 mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << (1 - rx_core)) << 12);
27025
27026 } else {
27027
27028 mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << tx_core) << 12);
27029 mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
27030 mod_phy_reg(pi, 0xa2, (0xf << 4), (1 << rx_core) << 4);
27031 mod_phy_reg(pi, 0xa2, (0xf << 8), (1 << rx_core) << 8);
27032 }
27033
27034 mod_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7), (0x1 << 2), 0);
27035 mod_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5,
27036 (0x1 << 2), (0x1 << 2));
27037 if (NREV_LT(pi->pubpi.phy_rev, 7)) {
27038 mod_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7),
27039 (0x1 << 0) | (0x1 << 1), 0);
27040 mod_phy_reg(pi, (rx_core == PHY_CORE_0) ?
27041 0x8f : 0xa5,
27042 (0x1 << 0) | (0x1 << 1), (0x1 << 0) | (0x1 << 1));
27043 }
27044
27045 wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_PA, 0,
27046 RADIO_MIMO_CORESEL_CORE1 |
27047 RADIO_MIMO_CORESEL_CORE2);
27048
27049 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
27050 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
27051 0, 0, 0,
27052 NPHY_REV7_RFCTRLOVERRIDE_ID0);
27053 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 0, 0, 0,
27054 NPHY_REV7_RFCTRLOVERRIDE_ID1);
27055 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 1, 0, 0,
27056 NPHY_REV7_RFCTRLOVERRIDE_ID1);
27057 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 1, 0, 0,
27058 NPHY_REV7_RFCTRLOVERRIDE_ID1);
27059 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1, 0, 0,
27060 NPHY_REV7_RFCTRLOVERRIDE_ID2);
27061 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0, 0, 0,
27062 NPHY_REV7_RFCTRLOVERRIDE_ID1);
27063 if (CHSPEC_IS40(pi->radio_chanspec))
27064 wlc_phy_rfctrl_override_nphy_rev7(
27065 pi,
27066 (0x1 << 7),
27067 2, 0, 0,
27068 NPHY_REV7_RFCTRLOVERRIDE_ID1);
27069 else
27070 wlc_phy_rfctrl_override_nphy_rev7(
27071 pi,
27072 (0x1 << 7),
27073 0, 0, 0,
27074 NPHY_REV7_RFCTRLOVERRIDE_ID1);
27075
27076 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
27077 0, 0, 0,
27078 NPHY_REV7_RFCTRLOVERRIDE_ID1);
27079 wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 0, 0, 0,
27080 NPHY_REV7_RFCTRLOVERRIDE_ID1);
27081 } else {
27082 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 3, 0);
27083 }
27084
27085 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX);
27086
27087 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
27088
27089 wlc_phy_rfctrlintc_override_nphy(pi,
27090 NPHY_RfctrlIntc_override_TRSW,
27091 0x1, rx_core + 1);
27092 } else {
27093
27094 if (rx_core == PHY_CORE_0) {
27095 rx_antval = 0x1;
27096 tx_antval = 0x8;
27097 } else {
27098 rx_antval = 0x4;
27099 tx_antval = 0x2;
27100 }
27101
27102 wlc_phy_rfctrlintc_override_nphy(pi,
27103 NPHY_RfctrlIntc_override_TRSW,
27104 rx_antval, rx_core + 1);
27105 wlc_phy_rfctrlintc_override_nphy(pi,
27106 NPHY_RfctrlIntc_override_TRSW,
27107 tx_antval, tx_core + 1);
27108 }
27109}
27110
27111static void wlc_phy_rxcal_phycleanup_nphy(struct brcms_phy *pi, u8 rx_core)
27112{
27113
27114 write_phy_reg(pi, 0xa2, pi->tx_rx_cal_phy_saveregs[0]);
27115 write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 : 0xa7,
27116 pi->tx_rx_cal_phy_saveregs[1]);
27117 write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5,
27118 pi->tx_rx_cal_phy_saveregs[2]);
27119 write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[3]);
27120 write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[4]);
27121
27122 write_phy_reg(pi, 0x7a, pi->tx_rx_cal_phy_saveregs[5]);
27123 write_phy_reg(pi, 0x7d, pi->tx_rx_cal_phy_saveregs[6]);
27124 write_phy_reg(pi, 0xe7, pi->tx_rx_cal_phy_saveregs[7]);
27125 write_phy_reg(pi, 0xec, pi->tx_rx_cal_phy_saveregs[8]);
27126 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
27127 write_phy_reg(pi, 0x342, pi->tx_rx_cal_phy_saveregs[11]);
27128 write_phy_reg(pi, 0x343, pi->tx_rx_cal_phy_saveregs[12]);
27129 write_phy_reg(pi, 0x346, pi->tx_rx_cal_phy_saveregs[13]);
27130 write_phy_reg(pi, 0x347, pi->tx_rx_cal_phy_saveregs[14]);
27131 }
27132
27133 write_phy_reg(pi, 0x297, pi->tx_rx_cal_phy_saveregs[9]);
27134 write_phy_reg(pi, 0x29b, pi->tx_rx_cal_phy_saveregs[10]);
27135}
27136
27137static void
27138wlc_phy_rxcal_gainctrl_nphy_rev5(struct brcms_phy *pi, u8 rx_core,
27139 u16 *rxgain, u8 cal_type)
27140{
27141
27142 u16 num_samps;
27143 struct phy_iq_est est[PHY_CORE_MAX];
27144 u8 tx_core;
27145 struct nphy_iq_comp save_comp, zero_comp;
27146 u32 i_pwr, q_pwr, curr_pwr, optim_pwr = 0, prev_pwr = 0,
27147 thresh_pwr = 10000;
27148 s16 desired_log2_pwr, actual_log2_pwr, delta_pwr;
27149 bool gainctrl_done = false;
27150 u8 mix_tia_gain = 3;
27151 s8 optim_gaintbl_index = 0, prev_gaintbl_index = 0;
27152 s8 curr_gaintbl_index = 3;
27153 u8 gainctrl_dirn = NPHY_RXCAL_GAIN_INIT;
27154 const struct nphy_ipa_txrxgain *nphy_rxcal_gaintbl;
27155 u16 hpvga, lpf_biq1, lpf_biq0, lna2, lna1;
27156 int fine_gain_idx;
27157 s8 txpwrindex;
27158 u16 nphy_rxcal_txgain[2];
27159
27160 if (NREV_GE(pi->pubpi.phy_rev, 7))
27161 tx_core = rx_core;
27162 else
27163 tx_core = 1 - rx_core;
27164
27165 num_samps = 1024;
27166 desired_log2_pwr = (cal_type == 0) ? 13 : 13;
27167
27168 wlc_phy_rx_iq_coeffs_nphy(pi, 0, &save_comp);
27169 zero_comp.a0 = zero_comp.b0 = zero_comp.a1 = zero_comp.b1 = 0x0;
27170 wlc_phy_rx_iq_coeffs_nphy(pi, 1, &zero_comp);
27171
27172 if (CHSPEC_IS5G(pi->radio_chanspec)) {
27173 if (NREV_GE(pi->pubpi.phy_rev, 7))
27174 mix_tia_gain = 3;
27175 else if (NREV_GE(pi->pubpi.phy_rev, 4))
27176 mix_tia_gain = 4;
27177 else
27178 mix_tia_gain = 6;
27179 if (NREV_GE(pi->pubpi.phy_rev, 7))
27180 nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_5GHz_rev7;
27181 else
27182 nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_5GHz;
27183 } else {
27184 if (NREV_GE(pi->pubpi.phy_rev, 7))
27185 nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_2GHz_rev7;
27186 else
27187 nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_2GHz;
27188 }
27189
27190 do {
27191
27192 hpvga = (NREV_GE(pi->pubpi.phy_rev, 7)) ?
27193 0 : nphy_rxcal_gaintbl[curr_gaintbl_index].hpvga;
27194 lpf_biq1 = nphy_rxcal_gaintbl[curr_gaintbl_index].lpf_biq1;
27195 lpf_biq0 = nphy_rxcal_gaintbl[curr_gaintbl_index].lpf_biq0;
27196 lna2 = nphy_rxcal_gaintbl[curr_gaintbl_index].lna2;
27197 lna1 = nphy_rxcal_gaintbl[curr_gaintbl_index].lna1;
27198 txpwrindex = nphy_rxcal_gaintbl[curr_gaintbl_index].txpwrindex;
27199
27200 if (NREV_GE(pi->pubpi.phy_rev, 7))
27201 wlc_phy_rfctrl_override_1tomany_nphy(
27202 pi,
27203 NPHY_REV7_RfctrlOverride_cmd_rxgain,
27204 ((lpf_biq1 << 12) |
27205 (lpf_biq0 << 8) |
27206 (mix_tia_gain << 4) | (lna2 << 2)
27207 | lna1), 0x3, 0);
27208 else
27209 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12),
27210 ((hpvga << 12) |
27211 (lpf_biq1 << 10) |
27212 (lpf_biq0 << 8) |
27213 (mix_tia_gain << 4) |
27214 (lna2 << 2) | lna1), 0x3,
27215 0);
27216
27217 pi->nphy_rxcal_pwr_idx[tx_core] = txpwrindex;
27218
27219 if (txpwrindex == -1) {
27220 nphy_rxcal_txgain[0] = 0x8ff0 | pi->nphy_gmval;
27221 nphy_rxcal_txgain[1] = 0x8ff0 | pi->nphy_gmval;
27222 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
27223 2, 0x110, 16,
27224 nphy_rxcal_txgain);
27225 } else {
27226 wlc_phy_txpwr_index_nphy(pi, tx_core + 1, txpwrindex,
27227 false);
27228 }
27229
27230 wlc_phy_tx_tone_nphy(pi, (CHSPEC_IS40(pi->radio_chanspec)) ?
27231 NPHY_RXCAL_TONEFREQ_40MHz :
27232 NPHY_RXCAL_TONEFREQ_20MHz,
27233 NPHY_RXCAL_TONEAMP, 0, cal_type, false);
27234
27235 wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
27236 i_pwr = (est[rx_core].i_pwr + num_samps / 2) / num_samps;
27237 q_pwr = (est[rx_core].q_pwr + num_samps / 2) / num_samps;
27238 curr_pwr = i_pwr + q_pwr;
27239
27240 switch (gainctrl_dirn) {
27241 case NPHY_RXCAL_GAIN_INIT:
27242 if (curr_pwr > thresh_pwr) {
27243 gainctrl_dirn = NPHY_RXCAL_GAIN_DOWN;
27244 prev_gaintbl_index = curr_gaintbl_index;
27245 curr_gaintbl_index--;
27246 } else {
27247 gainctrl_dirn = NPHY_RXCAL_GAIN_UP;
27248 prev_gaintbl_index = curr_gaintbl_index;
27249 curr_gaintbl_index++;
27250 }
27251 break;
27252
27253 case NPHY_RXCAL_GAIN_UP:
27254 if (curr_pwr > thresh_pwr) {
27255 gainctrl_done = true;
27256 optim_pwr = prev_pwr;
27257 optim_gaintbl_index = prev_gaintbl_index;
27258 } else {
27259 prev_gaintbl_index = curr_gaintbl_index;
27260 curr_gaintbl_index++;
27261 }
27262 break;
27263
27264 case NPHY_RXCAL_GAIN_DOWN:
27265 if (curr_pwr > thresh_pwr) {
27266 prev_gaintbl_index = curr_gaintbl_index;
27267 curr_gaintbl_index--;
27268 } else {
27269 gainctrl_done = true;
27270 optim_pwr = curr_pwr;
27271 optim_gaintbl_index = curr_gaintbl_index;
27272 }
27273 break;
27274
27275 default:
27276 break;
27277 }
27278
27279 if ((curr_gaintbl_index < 0) ||
27280 (curr_gaintbl_index > NPHY_IPA_RXCAL_MAXGAININDEX)) {
27281 gainctrl_done = true;
27282 optim_pwr = curr_pwr;
27283 optim_gaintbl_index = prev_gaintbl_index;
27284 } else {
27285 prev_pwr = curr_pwr;
27286 }
27287
27288 wlc_phy_stopplayback_nphy(pi);
27289 } while (!gainctrl_done);
27290
27291 hpvga = nphy_rxcal_gaintbl[optim_gaintbl_index].hpvga;
27292 lpf_biq1 = nphy_rxcal_gaintbl[optim_gaintbl_index].lpf_biq1;
27293 lpf_biq0 = nphy_rxcal_gaintbl[optim_gaintbl_index].lpf_biq0;
27294 lna2 = nphy_rxcal_gaintbl[optim_gaintbl_index].lna2;
27295 lna1 = nphy_rxcal_gaintbl[optim_gaintbl_index].lna1;
27296 txpwrindex = nphy_rxcal_gaintbl[optim_gaintbl_index].txpwrindex;
27297
27298 actual_log2_pwr = wlc_phy_nbits(optim_pwr);
27299 delta_pwr = desired_log2_pwr - actual_log2_pwr;
27300
27301 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
27302 fine_gain_idx = (int)lpf_biq1 + delta_pwr;
27303
27304 if (fine_gain_idx + (int)lpf_biq0 > 10)
27305 lpf_biq1 = 10 - lpf_biq0;
27306 else
27307 lpf_biq1 = (u16) max(fine_gain_idx, 0);
27308
27309 wlc_phy_rfctrl_override_1tomany_nphy(
27310 pi,
27311 NPHY_REV7_RfctrlOverride_cmd_rxgain,
27312 ((lpf_biq1 << 12) |
27313 (lpf_biq0 << 8) |
27314 (mix_tia_gain << 4) |
27315 (lna2 << 2) | lna1), 0x3,
27316 0);
27317 } else {
27318 hpvga = (u16) max(min(((int)hpvga) + delta_pwr, 10), 0);
27319 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12),
27320 ((hpvga << 12) |
27321 (lpf_biq1 << 10) |
27322 (lpf_biq0 << 8) |
27323 (mix_tia_gain << 4) |
27324 (lna2 << 2) |
27325 lna1), 0x3, 0);
27326 }
27327
27328 if (rxgain != NULL) {
27329 *rxgain++ = lna1;
27330 *rxgain++ = lna2;
27331 *rxgain++ = mix_tia_gain;
27332 *rxgain++ = lpf_biq0;
27333 *rxgain++ = lpf_biq1;
27334 *rxgain = hpvga;
27335 }
27336
27337 wlc_phy_rx_iq_coeffs_nphy(pi, 1, &save_comp);
27338}
27339
27340static void
27341wlc_phy_rxcal_gainctrl_nphy(struct brcms_phy *pi, u8 rx_core, u16 *rxgain,
27342 u8 cal_type)
27343{
27344 wlc_phy_rxcal_gainctrl_nphy_rev5(pi, rx_core, rxgain, cal_type);
27345}
27346
27347static u8
27348wlc_phy_rc_sweep_nphy(struct brcms_phy *pi, u8 core_idx, u8 loopback_type)
27349{
27350 u32 target_bws[2] = { 9500, 21000 };
27351 u32 ref_tones[2] = { 3000, 6000 };
27352 u32 target_bw, ref_tone;
27353
27354 u32 target_pwr_ratios[2] = { 28606, 18468 };
27355 u32 target_pwr_ratio, pwr_ratio, last_pwr_ratio = 0;
27356
27357 u16 start_rccal_ovr_val = 128;
27358 u16 txlpf_rccal_lpc_ovr_val = 128;
27359 u16 rxlpf_rccal_hpc_ovr_val = 159;
27360
27361 u16 orig_txlpf_rccal_lpc_ovr_val;
27362 u16 orig_rxlpf_rccal_hpc_ovr_val;
27363 u16 radio_addr_offset_rx;
27364 u16 radio_addr_offset_tx;
27365 u16 orig_dcBypass;
27366 u16 orig_RxStrnFilt40Num[6];
27367 u16 orig_RxStrnFilt40Den[4];
27368 u16 orig_rfctrloverride[2];
27369 u16 orig_rfctrlauxreg[2];
27370 u16 orig_rfctrlrssiothers;
27371 u16 tx_lpf_bw = 4;
27372
27373 u16 rx_lpf_bw, rx_lpf_bws[2] = { 2, 4 };
27374 u16 lpf_hpc = 7, hpvga_hpc = 7;
27375
27376 s8 rccal_stepsize;
27377 u16 rccal_val, last_rccal_val = 0, best_rccal_val = 0;
27378 u32 ref_iq_vals = 0, target_iq_vals = 0;
27379 u16 num_samps, log_num_samps = 10;
27380 struct phy_iq_est est[PHY_CORE_MAX];
27381
27382 if (NREV_GE(pi->pubpi.phy_rev, 7))
27383 return 0;
27384
27385 num_samps = (1 << log_num_samps);
27386
27387 if (CHSPEC_IS40(pi->radio_chanspec)) {
27388 target_bw = target_bws[1];
27389 target_pwr_ratio = target_pwr_ratios[1];
27390 ref_tone = ref_tones[1];
27391 rx_lpf_bw = rx_lpf_bws[1];
27392 } else {
27393 target_bw = target_bws[0];
27394 target_pwr_ratio = target_pwr_ratios[0];
27395 ref_tone = ref_tones[0];
27396 rx_lpf_bw = rx_lpf_bws[0];
27397 }
27398
27399 if (core_idx == 0) {
27400 radio_addr_offset_rx = RADIO_2056_RX0;
27401 radio_addr_offset_tx =
27402 (loopback_type == 0) ? RADIO_2056_TX0 : RADIO_2056_TX1;
27403 } else {
27404 radio_addr_offset_rx = RADIO_2056_RX1;
27405 radio_addr_offset_tx =
27406 (loopback_type == 0) ? RADIO_2056_TX1 : RADIO_2056_TX0;
27407 }
27408
27409 orig_txlpf_rccal_lpc_ovr_val =
27410 read_radio_reg(pi,
27411 (RADIO_2056_TX_TXLPF_RCCAL |
27412 radio_addr_offset_tx));
27413 orig_rxlpf_rccal_hpc_ovr_val =
27414 read_radio_reg(pi,
27415 (RADIO_2056_RX_RXLPF_RCCAL_HPC |
27416 radio_addr_offset_rx));
27417
27418 orig_dcBypass = ((read_phy_reg(pi, 0x48) >> 8) & 1);
27419
27420 orig_RxStrnFilt40Num[0] = read_phy_reg(pi, 0x267);
27421 orig_RxStrnFilt40Num[1] = read_phy_reg(pi, 0x268);
27422 orig_RxStrnFilt40Num[2] = read_phy_reg(pi, 0x269);
27423 orig_RxStrnFilt40Den[0] = read_phy_reg(pi, 0x26a);
27424 orig_RxStrnFilt40Den[1] = read_phy_reg(pi, 0x26b);
27425 orig_RxStrnFilt40Num[3] = read_phy_reg(pi, 0x26c);
27426 orig_RxStrnFilt40Num[4] = read_phy_reg(pi, 0x26d);
27427 orig_RxStrnFilt40Num[5] = read_phy_reg(pi, 0x26e);
27428 orig_RxStrnFilt40Den[2] = read_phy_reg(pi, 0x26f);
27429 orig_RxStrnFilt40Den[3] = read_phy_reg(pi, 0x270);
27430
27431 orig_rfctrloverride[0] = read_phy_reg(pi, 0xe7);
27432 orig_rfctrloverride[1] = read_phy_reg(pi, 0xec);
27433 orig_rfctrlauxreg[0] = read_phy_reg(pi, 0xf8);
27434 orig_rfctrlauxreg[1] = read_phy_reg(pi, 0xfa);
27435 orig_rfctrlrssiothers = read_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d);
27436
27437 write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx),
27438 txlpf_rccal_lpc_ovr_val);
27439
27440 write_radio_reg(pi,
27441 (RADIO_2056_RX_RXLPF_RCCAL_HPC | radio_addr_offset_rx),
27442 rxlpf_rccal_hpc_ovr_val);
27443
27444 mod_phy_reg(pi, 0x48, (0x1 << 8), (0x1 << 8));
27445
27446 write_phy_reg(pi, 0x267, 0x02d4);
27447 write_phy_reg(pi, 0x268, 0x0000);
27448 write_phy_reg(pi, 0x269, 0x0000);
27449 write_phy_reg(pi, 0x26a, 0x0000);
27450 write_phy_reg(pi, 0x26b, 0x0000);
27451 write_phy_reg(pi, 0x26c, 0x02d4);
27452 write_phy_reg(pi, 0x26d, 0x0000);
27453 write_phy_reg(pi, 0x26e, 0x0000);
27454 write_phy_reg(pi, 0x26f, 0x0000);
27455 write_phy_reg(pi, 0x270, 0x0000);
27456
27457 or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 8));
27458 or_phy_reg(pi, (core_idx == 0) ? 0xec : 0xe7, (0x1 << 15));
27459 or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 9));
27460 or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 10));
27461
27462 mod_phy_reg(pi, (core_idx == 0) ? 0xfa : 0xf8,
27463 (0x7 << 10), (tx_lpf_bw << 10));
27464 mod_phy_reg(pi, (core_idx == 0) ? 0xf8 : 0xfa,
27465 (0x7 << 0), (hpvga_hpc << 0));
27466 mod_phy_reg(pi, (core_idx == 0) ? 0xf8 : 0xfa,
27467 (0x7 << 4), (lpf_hpc << 4));
27468 mod_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d,
27469 (0x7 << 8), (rx_lpf_bw << 8));
27470
27471 rccal_stepsize = 16;
27472 rccal_val = start_rccal_ovr_val + rccal_stepsize;
27473
27474 while (rccal_stepsize >= 0) {
27475 write_radio_reg(pi,
27476 (RADIO_2056_RX_RXLPF_RCCAL_LPC |
27477 radio_addr_offset_rx), rccal_val);
27478
27479 if (rccal_stepsize == 16) {
27480
27481 wlc_phy_tx_tone_nphy(pi, ref_tone, NPHY_RXCAL_TONEAMP,
27482 0, 1, false);
27483 udelay(2);
27484
27485 wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
27486
27487 if (core_idx == 0)
27488 ref_iq_vals =
27489 max_t(u32, (est[0].i_pwr +
27490 est[0].q_pwr) >>
27491 (log_num_samps + 1),
27492 1);
27493 else
27494 ref_iq_vals =
27495 max_t(u32, (est[1].i_pwr +
27496 est[1].q_pwr) >>
27497 (log_num_samps + 1),
27498 1);
27499
27500 wlc_phy_tx_tone_nphy(pi, target_bw, NPHY_RXCAL_TONEAMP,
27501 0, 1, false);
27502 udelay(2);
27503 }
27504
27505 wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
27506
27507 if (core_idx == 0)
27508 target_iq_vals = (est[0].i_pwr + est[0].q_pwr) >>
27509 (log_num_samps + 1);
27510 else
27511 target_iq_vals =
27512 (est[1].i_pwr +
27513 est[1].q_pwr) >> (log_num_samps + 1);
27514
27515 pwr_ratio = (uint) ((target_iq_vals << 16) / ref_iq_vals);
27516
27517 if (rccal_stepsize == 0)
27518 rccal_stepsize--;
27519 else if (rccal_stepsize == 1) {
27520 last_rccal_val = rccal_val;
27521 rccal_val += (pwr_ratio > target_pwr_ratio) ? 1 : -1;
27522 last_pwr_ratio = pwr_ratio;
27523 rccal_stepsize--;
27524 } else {
27525 rccal_stepsize = (rccal_stepsize >> 1);
27526 rccal_val += ((pwr_ratio > target_pwr_ratio) ?
27527 rccal_stepsize : (-rccal_stepsize));
27528 }
27529
27530 if (rccal_stepsize == -1) {
27531 best_rccal_val =
27532 (abs((int)last_pwr_ratio -
27533 (int)target_pwr_ratio) <
27534 abs((int)pwr_ratio -
27535 (int)target_pwr_ratio)) ? last_rccal_val :
27536 rccal_val;
27537
27538 if (CHSPEC_IS40(pi->radio_chanspec)) {
27539 if ((best_rccal_val > 140)
27540 || (best_rccal_val < 135))
27541 best_rccal_val = 138;
27542 } else {
27543 if ((best_rccal_val > 142)
27544 || (best_rccal_val < 137))
27545 best_rccal_val = 140;
27546 }
27547
27548 write_radio_reg(pi,
27549 (RADIO_2056_RX_RXLPF_RCCAL_LPC |
27550 radio_addr_offset_rx), best_rccal_val);
27551 }
27552 }
27553
27554 wlc_phy_stopplayback_nphy(pi);
27555
27556 write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx),
27557 orig_txlpf_rccal_lpc_ovr_val);
27558 write_radio_reg(pi,
27559 (RADIO_2056_RX_RXLPF_RCCAL_HPC | radio_addr_offset_rx),
27560 orig_rxlpf_rccal_hpc_ovr_val);
27561
27562 mod_phy_reg(pi, 0x48, (0x1 << 8), (orig_dcBypass << 8));
27563
27564 write_phy_reg(pi, 0x267, orig_RxStrnFilt40Num[0]);
27565 write_phy_reg(pi, 0x268, orig_RxStrnFilt40Num[1]);
27566 write_phy_reg(pi, 0x269, orig_RxStrnFilt40Num[2]);
27567 write_phy_reg(pi, 0x26a, orig_RxStrnFilt40Den[0]);
27568 write_phy_reg(pi, 0x26b, orig_RxStrnFilt40Den[1]);
27569 write_phy_reg(pi, 0x26c, orig_RxStrnFilt40Num[3]);
27570 write_phy_reg(pi, 0x26d, orig_RxStrnFilt40Num[4]);
27571 write_phy_reg(pi, 0x26e, orig_RxStrnFilt40Num[5]);
27572 write_phy_reg(pi, 0x26f, orig_RxStrnFilt40Den[2]);
27573 write_phy_reg(pi, 0x270, orig_RxStrnFilt40Den[3]);
27574
27575 write_phy_reg(pi, 0xe7, orig_rfctrloverride[0]);
27576 write_phy_reg(pi, 0xec, orig_rfctrloverride[1]);
27577 write_phy_reg(pi, 0xf8, orig_rfctrlauxreg[0]);
27578 write_phy_reg(pi, 0xfa, orig_rfctrlauxreg[1]);
27579 write_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d, orig_rfctrlrssiothers);
27580
27581 pi->nphy_anarxlpf_adjusted = false;
27582
27583 return best_rccal_val - 0x80;
27584}
27585
27586#define WAIT_FOR_SCOPE 4000
27587static int wlc_phy_cal_rxiq_nphy_rev3(struct brcms_phy *pi,
27588 struct nphy_txgains target_gain,
27589 u8 cal_type, bool debug)
27590{
27591 u16 orig_BBConfig;
27592 u8 core_no, rx_core;
27593 u8 best_rccal[2];
27594 u16 gain_save[2];
27595 u16 cal_gain[2];
27596 struct nphy_iqcal_params cal_params[2];
27597 u8 rxcore_state;
27598 s8 rxlpf_rccal_hpc, txlpf_rccal_lpc;
27599 s8 txlpf_idac;
27600 bool phyhang_avoid_state = false;
27601 bool skip_rxiqcal = false;
27602
27603 orig_BBConfig = read_phy_reg(pi, 0x01);
27604 mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
27605
27606 wlc_phy_stay_in_carriersearch_nphy(pi, true);
27607
27608 if (NREV_GE(pi->pubpi.phy_rev, 4)) {
27609 phyhang_avoid_state = pi->phyhang_avoid;
27610 pi->phyhang_avoid = false;
27611 }
27612
27613 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
27614
27615 for (core_no = 0; core_no <= 1; core_no++) {
27616 wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
27617 &cal_params[core_no]);
27618 cal_gain[core_no] = cal_params[core_no].cal_gain;
27619 }
27620
27621 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
27622
27623 rxcore_state = wlc_phy_rxcore_getstate_nphy(
27624 (struct brcms_phy_pub *) pi);
27625
27626 for (rx_core = 0; rx_core < pi->pubpi.phy_corenum; rx_core++) {
27627
27628 skip_rxiqcal =
27629 ((rxcore_state & (1 << rx_core)) == 0) ? true : false;
27630
27631 wlc_phy_rxcal_physetup_nphy(pi, rx_core);
27632
27633 wlc_phy_rxcal_radio_setup_nphy(pi, rx_core);
27634
27635 if ((!skip_rxiqcal) && ((cal_type == 0) || (cal_type == 2))) {
27636
27637 wlc_phy_rxcal_gainctrl_nphy(pi, rx_core, NULL, 0);
27638
27639 wlc_phy_tx_tone_nphy(pi,
27640 (CHSPEC_IS40(
27641 pi->radio_chanspec)) ?
27642 NPHY_RXCAL_TONEFREQ_40MHz :
27643 NPHY_RXCAL_TONEFREQ_20MHz,
27644 NPHY_RXCAL_TONEAMP, 0, cal_type,
27645 false);
27646
27647 if (debug)
27648 mdelay(WAIT_FOR_SCOPE);
27649
27650 wlc_phy_calc_rx_iq_comp_nphy(pi, rx_core + 1);
27651 wlc_phy_stopplayback_nphy(pi);
27652 }
27653
27654 if (((cal_type == 1) || (cal_type == 2))
27655 && NREV_LT(pi->pubpi.phy_rev, 7)) {
27656
27657 if (rx_core == PHY_CORE_1) {
27658
27659 if (rxcore_state == 1)
27660 wlc_phy_rxcore_setstate_nphy(
27661 (struct brcms_phy_pub *) pi, 3);
27662
27663 wlc_phy_rxcal_gainctrl_nphy(pi, rx_core, NULL,
27664 1);
27665
27666 best_rccal[rx_core] =
27667 wlc_phy_rc_sweep_nphy(pi, rx_core, 1);
27668 pi->nphy_rccal_value = best_rccal[rx_core];
27669
27670 if (rxcore_state == 1)
27671 wlc_phy_rxcore_setstate_nphy(
27672 (struct brcms_phy_pub *) pi,
27673 rxcore_state);
27674 }
27675 }
27676
27677 wlc_phy_rxcal_radio_cleanup_nphy(pi, rx_core);
27678
27679 wlc_phy_rxcal_phycleanup_nphy(pi, rx_core);
27680 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
27681 }
27682
27683 if ((cal_type == 1) || (cal_type == 2)) {
27684
27685 best_rccal[0] = best_rccal[1];
27686 write_radio_reg(pi,
27687 (RADIO_2056_RX_RXLPF_RCCAL_LPC |
27688 RADIO_2056_RX0), (best_rccal[0] | 0x80));
27689
27690 for (rx_core = 0; rx_core < pi->pubpi.phy_corenum; rx_core++) {
27691 rxlpf_rccal_hpc =
27692 (((int)best_rccal[rx_core] - 12) >> 1) + 10;
27693 txlpf_rccal_lpc = ((int)best_rccal[rx_core] - 12) + 10;
27694
27695 if (PHY_IPA(pi)) {
27696 txlpf_rccal_lpc +=
27697 (pi->bw == WL_CHANSPEC_BW_40) ? 24 : 12;
27698 txlpf_idac = (pi->bw == WL_CHANSPEC_BW_40) ?
27699 0x0e : 0x13;
27700 WRITE_RADIO_REG2(pi, RADIO_2056, TX, rx_core,
27701 TXLPF_IDAC_4, txlpf_idac);
27702 }
27703
27704 rxlpf_rccal_hpc = max(min_t(u8, rxlpf_rccal_hpc, 31),
27705 0);
27706 txlpf_rccal_lpc = max(min_t(u8, txlpf_rccal_lpc, 31),
27707 0);
27708
27709 write_radio_reg(pi, (RADIO_2056_RX_RXLPF_RCCAL_HPC |
27710 ((rx_core ==
27711 PHY_CORE_0) ? RADIO_2056_RX0 :
27712 RADIO_2056_RX1)),
27713 (rxlpf_rccal_hpc | 0x80));
27714
27715 write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL |
27716 ((rx_core ==
27717 PHY_CORE_0) ? RADIO_2056_TX0 :
27718 RADIO_2056_TX1)),
27719 (txlpf_rccal_lpc | 0x80));
27720 }
27721 }
27722
27723 write_phy_reg(pi, 0x01, orig_BBConfig);
27724
27725 wlc_phy_resetcca_nphy(pi);
27726
27727 if (NREV_GE(pi->pubpi.phy_rev, 7))
27728 wlc_phy_rfctrl_override_1tomany_nphy(
27729 pi,
27730 NPHY_REV7_RfctrlOverride_cmd_rxgain,
27731 0, 0x3, 1);
27732 else
27733 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 1);
27734
27735 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
27736
27737 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
27738 gain_save);
27739
27740 if (NREV_GE(pi->pubpi.phy_rev, 4))
27741 pi->phyhang_avoid = phyhang_avoid_state;
27742
27743 wlc_phy_stay_in_carriersearch_nphy(pi, false);
27744
27745 return 0;
27746}
27747
27748static int
27749wlc_phy_cal_rxiq_nphy_rev2(struct brcms_phy *pi,
27750 struct nphy_txgains target_gain, bool debug)
27751{
27752 struct phy_iq_est est[PHY_CORE_MAX];
27753 u8 core_num, rx_core, tx_core;
27754 u16 lna_vals[] = { 0x3, 0x3, 0x1 };
27755 u16 hpf1_vals[] = { 0x7, 0x2, 0x0 };
27756 u16 hpf2_vals[] = { 0x2, 0x0, 0x0 };
27757 s16 curr_hpf1, curr_hpf2, curr_hpf, curr_lna;
27758 s16 desired_log2_pwr, actual_log2_pwr, hpf_change;
27759 u16 orig_RfseqCoreActv, orig_AfectrlCore, orig_AfectrlOverride;
27760 u16 orig_RfctrlIntcRx, orig_RfctrlIntcTx;
27761 u16 num_samps;
27762 u32 i_pwr, q_pwr, tot_pwr[3];
27763 u8 gain_pass, use_hpf_num;
27764 u16 mask, val1, val2;
27765 u16 core_no;
27766 u16 gain_save[2];
27767 u16 cal_gain[2];
27768 struct nphy_iqcal_params cal_params[2];
27769 u8 phy_bw;
27770 int bcmerror = 0;
27771 bool first_playtone = true;
27772
27773 wlc_phy_stay_in_carriersearch_nphy(pi, true);
27774
27775 if (NREV_LT(pi->pubpi.phy_rev, 2))
27776 wlc_phy_reapply_txcal_coeffs_nphy(pi);
27777
27778 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
27779
27780 for (core_no = 0; core_no <= 1; core_no++) {
27781 wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
27782 &cal_params[core_no]);
27783 cal_gain[core_no] = cal_params[core_no].cal_gain;
27784 }
27785
27786 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
27787
27788 num_samps = 1024;
27789 desired_log2_pwr = 13;
27790
27791 for (core_num = 0; core_num < 2; core_num++) {
27792
27793 rx_core = core_num;
27794 tx_core = 1 - core_num;
27795
27796 orig_RfseqCoreActv = read_phy_reg(pi, 0xa2);
27797 orig_AfectrlCore = read_phy_reg(pi, (rx_core == PHY_CORE_0) ?
27798 0xa6 : 0xa7);
27799 orig_AfectrlOverride = read_phy_reg(pi, 0xa5);
27800 orig_RfctrlIntcRx = read_phy_reg(pi, (rx_core == PHY_CORE_0) ?
27801 0x91 : 0x92);
27802 orig_RfctrlIntcTx = read_phy_reg(pi, (tx_core == PHY_CORE_0) ?
27803 0x91 : 0x92);
27804
27805 mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << tx_core) << 12);
27806 mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
27807
27808 or_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7),
27809 ((0x1 << 1) | (0x1 << 2)));
27810 or_phy_reg(pi, 0xa5, ((0x1 << 1) | (0x1 << 2)));
27811
27812 if (((pi->nphy_rxcalparams) & 0xff000000))
27813 write_phy_reg(pi,
27814 (rx_core == PHY_CORE_0) ? 0x91 : 0x92,
27815 (CHSPEC_IS5G(pi->radio_chanspec) ?
27816 0x140 : 0x110));
27817 else
27818 write_phy_reg(pi,
27819 (rx_core == PHY_CORE_0) ? 0x91 : 0x92,
27820 (CHSPEC_IS5G(pi->radio_chanspec) ?
27821 0x180 : 0x120));
27822
27823 write_phy_reg(pi, (tx_core == PHY_CORE_0) ? 0x91 : 0x92,
27824 (CHSPEC_IS5G(pi->radio_chanspec) ? 0x148 :
27825 0x114));
27826
27827 mask = RADIO_2055_COUPLE_RX_MASK | RADIO_2055_COUPLE_TX_MASK;
27828 if (rx_core == PHY_CORE_0) {
27829 val1 = RADIO_2055_COUPLE_RX_MASK;
27830 val2 = RADIO_2055_COUPLE_TX_MASK;
27831 } else {
27832 val1 = RADIO_2055_COUPLE_TX_MASK;
27833 val2 = RADIO_2055_COUPLE_RX_MASK;
27834 }
27835
27836 if ((pi->nphy_rxcalparams & 0x10000)) {
27837 mod_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, mask,
27838 val1);
27839 mod_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, mask,
27840 val2);
27841 }
27842
27843 for (gain_pass = 0; gain_pass < 4; gain_pass++) {
27844
27845 if (debug)
27846 mdelay(WAIT_FOR_SCOPE);
27847
27848 if (gain_pass < 3) {
27849 curr_lna = lna_vals[gain_pass];
27850 curr_hpf1 = hpf1_vals[gain_pass];
27851 curr_hpf2 = hpf2_vals[gain_pass];
27852 } else {
27853
27854 if (tot_pwr[1] > 10000) {
27855 curr_lna = lna_vals[2];
27856 curr_hpf1 = hpf1_vals[2];
27857 curr_hpf2 = hpf2_vals[2];
27858 use_hpf_num = 1;
27859 curr_hpf = curr_hpf1;
27860 actual_log2_pwr =
27861 wlc_phy_nbits(tot_pwr[2]);
27862 } else {
27863 if (tot_pwr[0] > 10000) {
27864 curr_lna = lna_vals[1];
27865 curr_hpf1 = hpf1_vals[1];
27866 curr_hpf2 = hpf2_vals[1];
27867 use_hpf_num = 1;
27868 curr_hpf = curr_hpf1;
27869 actual_log2_pwr =
27870 wlc_phy_nbits(
27871 tot_pwr[1]);
27872 } else {
27873 curr_lna = lna_vals[0];
27874 curr_hpf1 = hpf1_vals[0];
27875 curr_hpf2 = hpf2_vals[0];
27876 use_hpf_num = 2;
27877 curr_hpf = curr_hpf2;
27878 actual_log2_pwr =
27879 wlc_phy_nbits(
27880 tot_pwr[0]);
27881 }
27882 }
27883
27884 hpf_change = desired_log2_pwr - actual_log2_pwr;
27885 curr_hpf += hpf_change;
27886 curr_hpf = max(min_t(u16, curr_hpf, 10), 0);
27887 if (use_hpf_num == 1)
27888 curr_hpf1 = curr_hpf;
27889 else
27890 curr_hpf2 = curr_hpf;
27891 }
27892
27893 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 10),
27894 ((curr_hpf2 << 8) |
27895 (curr_hpf1 << 4) |
27896 (curr_lna << 2)), 0x3, 0);
27897 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
27898
27899 wlc_phy_stopplayback_nphy(pi);
27900
27901 if (first_playtone) {
27902 bcmerror = wlc_phy_tx_tone_nphy(pi, 4000,
27903 (u16) (pi->nphy_rxcalparams &
27904 0xffff), 0, 0, true);
27905 first_playtone = false;
27906 } else {
27907 phy_bw = (CHSPEC_IS40(pi->radio_chanspec)) ?
27908 40 : 20;
27909 wlc_phy_runsamples_nphy(pi, phy_bw * 8, 0xffff,
27910 0, 0, 0, true);
27911 }
27912
27913 if (bcmerror == 0) {
27914 if (gain_pass < 3) {
27915
27916 wlc_phy_rx_iq_est_nphy(pi, est,
27917 num_samps, 32,
27918 0);
27919 i_pwr = (est[rx_core].i_pwr +
27920 num_samps / 2) / num_samps;
27921 q_pwr = (est[rx_core].q_pwr +
27922 num_samps / 2) / num_samps;
27923 tot_pwr[gain_pass] = i_pwr + q_pwr;
27924 } else {
27925
27926 wlc_phy_calc_rx_iq_comp_nphy(pi,
27927 (1 <<
27928 rx_core));
27929 }
27930
27931 wlc_phy_stopplayback_nphy(pi);
27932 }
27933
27934 if (bcmerror != 0)
27935 break;
27936 }
27937
27938 and_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, ~mask);
27939 and_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, ~mask);
27940
27941 write_phy_reg(pi, (tx_core == PHY_CORE_0) ? 0x91 :
27942 0x92, orig_RfctrlIntcTx);
27943 write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x91 :
27944 0x92, orig_RfctrlIntcRx);
27945 write_phy_reg(pi, 0xa5, orig_AfectrlOverride);
27946 write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 :
27947 0xa7, orig_AfectrlCore);
27948 write_phy_reg(pi, 0xa2, orig_RfseqCoreActv);
27949
27950 if (bcmerror != 0)
27951 break;
27952 }
27953
27954 wlc_phy_rfctrl_override_nphy(pi, (0x1 << 10), 0, 0x3, 1);
27955 wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
27956
27957 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
27958 gain_save);
27959
27960 wlc_phy_stay_in_carriersearch_nphy(pi, false);
27961
27962 return bcmerror;
27963}
27964
27965int
27966wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi, struct nphy_txgains target_gain,
27967 u8 cal_type, bool debug)
27968{
27969 if (NREV_GE(pi->pubpi.phy_rev, 7))
27970 cal_type = 0;
27971
27972 if (NREV_GE(pi->pubpi.phy_rev, 3))
27973 return wlc_phy_cal_rxiq_nphy_rev3(pi, target_gain, cal_type,
27974 debug);
27975 else
27976 return wlc_phy_cal_rxiq_nphy_rev2(pi, target_gain, debug);
27977}
27978
27979void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi)
27980{
27981 uint core;
27982 u32 txgain;
27983 u16 rad_gain, dac_gain, bbmult, m1m2;
27984 u8 txpi[2], chan_freq_range;
27985 s32 rfpwr_offset;
27986
27987 if (pi->phyhang_avoid)
27988 wlc_phy_stay_in_carriersearch_nphy(pi, true);
27989
27990 if (pi->sh->sromrev < 4) {
27991 txpi[0] = txpi[1] = 72;
27992 } else {
27993
27994 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
27995 switch (chan_freq_range) {
27996 case WL_CHAN_FREQ_RANGE_2G:
27997 txpi[0] = pi->nphy_txpid2g[0];
27998 txpi[1] = pi->nphy_txpid2g[1];
27999 break;
28000 case WL_CHAN_FREQ_RANGE_5GL:
28001 txpi[0] = pi->nphy_txpid5gl[0];
28002 txpi[1] = pi->nphy_txpid5gl[1];
28003 break;
28004 case WL_CHAN_FREQ_RANGE_5GM:
28005 txpi[0] = pi->nphy_txpid5g[0];
28006 txpi[1] = pi->nphy_txpid5g[1];
28007 break;
28008 case WL_CHAN_FREQ_RANGE_5GH:
28009 txpi[0] = pi->nphy_txpid5gh[0];
28010 txpi[1] = pi->nphy_txpid5gh[1];
28011 break;
28012 default:
28013 txpi[0] = txpi[1] = 91;
28014 break;
28015 }
28016 }
28017
28018 if (NREV_GE(pi->pubpi.phy_rev, 7))
28019 txpi[0] = txpi[1] = 30;
28020 else if (NREV_GE(pi->pubpi.phy_rev, 3))
28021 txpi[0] = txpi[1] = 40;
28022
28023 if (NREV_LT(pi->pubpi.phy_rev, 7)) {
28024
28025 if ((txpi[0] < 40) || (txpi[0] > 100) ||
28026 (txpi[1] < 40) || (txpi[1] > 100))
28027 txpi[0] = txpi[1] = 91;
28028 }
28029
28030 pi->nphy_txpwrindex[PHY_CORE_0].index_internal = txpi[0];
28031 pi->nphy_txpwrindex[PHY_CORE_1].index_internal = txpi[1];
28032 pi->nphy_txpwrindex[PHY_CORE_0].index_internal_save = txpi[0];
28033 pi->nphy_txpwrindex[PHY_CORE_1].index_internal_save = txpi[1];
28034
28035 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
28036 uint phyrev = pi->pubpi.phy_rev;
28037
28038 if (NREV_GE(phyrev, 3)) {
28039 if (PHY_IPA(pi)) {
28040 u32 *tx_gaintbl =
28041 wlc_phy_get_ipa_gaintbl_nphy(pi);
28042 txgain = tx_gaintbl[txpi[core]];
28043 } else {
28044 if (CHSPEC_IS5G(pi->radio_chanspec)) {
28045 if (NREV_IS(phyrev, 3)) {
28046 txgain =
28047 nphy_tpc_5GHz_txgain_rev3
28048 [txpi[core]];
28049 } else if (NREV_IS(phyrev, 4)) {
28050 txgain = (
28051 pi->srom_fem5g.extpagain ==
28052 3) ?
28053 nphy_tpc_5GHz_txgain_HiPwrEPA
28054 [txpi[core]] :
28055 nphy_tpc_5GHz_txgain_rev4
28056 [txpi[core]];
28057 } else {
28058 txgain =
28059 nphy_tpc_5GHz_txgain_rev5
28060 [txpi[core]];
28061 }
28062 } else {
28063 if (NREV_GE(phyrev, 5) &&
28064 (pi->srom_fem2g.extpagain == 3)) {
28065 txgain =
28066 nphy_tpc_txgain_HiPwrEPA
28067 [txpi[core]];
28068 } else {
28069 txgain = nphy_tpc_txgain_rev3
28070 [txpi[core]];
28071 }
28072 }
28073 }
28074 } else {
28075 txgain = nphy_tpc_txgain[txpi[core]];
28076 }
28077
28078 if (NREV_GE(phyrev, 3))
28079 rad_gain = (txgain >> 16) & ((1 << (32 - 16 + 1)) - 1);
28080 else
28081 rad_gain = (txgain >> 16) & ((1 << (28 - 16 + 1)) - 1);
28082
28083 if (NREV_GE(phyrev, 7))
28084 dac_gain = (txgain >> 8) & ((1 << (10 - 8 + 1)) - 1);
28085 else
28086 dac_gain = (txgain >> 8) & ((1 << (13 - 8 + 1)) - 1);
28087
28088 bbmult = (txgain >> 0) & ((1 << (7 - 0 + 1)) - 1);
28089
28090 if (NREV_GE(phyrev, 3))
28091 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
28092 0xa5), (0x1 << 8), (0x1 << 8));
28093 else
28094 mod_phy_reg(pi, 0xa5, (0x1 << 14), (0x1 << 14));
28095
28096 write_phy_reg(pi, (core == PHY_CORE_0) ? 0xaa : 0xab, dac_gain);
28097
28098 wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
28099 &rad_gain);
28100
28101 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
28102 m1m2 &= ((core == PHY_CORE_0) ? 0x00ff : 0xff00);
28103 m1m2 |= ((core == PHY_CORE_0) ? (bbmult << 8) : (bbmult << 0));
28104 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
28105
28106 if (PHY_IPA(pi)) {
28107 wlc_phy_table_read_nphy(pi,
28108 (core ==
28109 PHY_CORE_0 ?
28110 NPHY_TBL_ID_CORE1TXPWRCTL :
28111 NPHY_TBL_ID_CORE2TXPWRCTL), 1,
28112 576 + txpi[core], 32,
28113 &rfpwr_offset);
28114
28115 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
28116 0x29b, (0x1ff << 4),
28117 ((s16) rfpwr_offset) << 4);
28118
28119 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
28120 0x29b, (0x1 << 2), (1) << 2);
28121
28122 }
28123 }
28124
28125 and_phy_reg(pi, 0xbf, (u16) (~(0x1f << 0)));
28126
28127 if (pi->phyhang_avoid)
28128 wlc_phy_stay_in_carriersearch_nphy(pi, false);
28129}
28130
28131static void
28132wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max, u16 *pwr_offset,
28133 u8 tmp_max_pwr, u8 rate_start,
28134 u8 rate_end)
28135{
28136 u8 rate;
28137 u8 word_num, nibble_num;
28138 u8 tmp_nibble;
28139
28140 for (rate = rate_start; rate <= rate_end; rate++) {
28141 word_num = (rate - rate_start) >> 2;
28142 nibble_num = (rate - rate_start) & 0x3;
28143 tmp_nibble = (pwr_offset[word_num] >> 4 * nibble_num) & 0xf;
28144
28145 srom_max[rate] = tmp_max_pwr - 2 * tmp_nibble;
28146 }
28147}
28148
28149static void
28150wlc_phy_txpwr_nphy_po_apply(u8 *srom_max, u8 pwr_offset,
28151 u8 rate_start, u8 rate_end)
28152{
28153 u8 rate;
28154
28155 for (rate = rate_start; rate <= rate_end; rate++)
28156 srom_max[rate] -= 2 * pwr_offset;
28157}
28158
28159void
28160wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
28161 u8 rate_mcs_end, u8 rate_ofdm_start)
28162{
28163 u8 rate1, rate2;
28164
28165 rate2 = rate_ofdm_start;
28166 for (rate1 = rate_mcs_start; rate1 <= rate_mcs_end - 1; rate1++) {
28167 power[rate1] = power[rate2];
28168 rate2 += (rate1 == rate_mcs_start) ? 2 : 1;
28169 }
28170 power[rate_mcs_end] = power[rate_mcs_end - 1];
28171}
28172
28173void
28174wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power, u8 rate_ofdm_start,
28175 u8 rate_ofdm_end, u8 rate_mcs_start)
28176{
28177 u8 rate1, rate2;
28178
28179 for (rate1 = rate_ofdm_start, rate2 = rate_mcs_start;
28180 rate1 <= rate_ofdm_end; rate1++, rate2++) {
28181 power[rate1] = power[rate2];
28182 if (rate1 == rate_ofdm_start)
28183 power[++rate1] = power[rate2];
28184 }
28185}
28186
28187void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi)
28188{
28189 uint rate1, rate2, band_num;
28190 u8 tmp_bw40po = 0, tmp_cddpo = 0, tmp_stbcpo = 0;
28191 u8 tmp_max_pwr = 0;
28192 u16 pwr_offsets1[2], *pwr_offsets2 = NULL;
28193 u8 *tx_srom_max_rate = NULL;
28194
28195 for (band_num = 0; band_num < (CH_2G_GROUP + CH_5G_GROUP);
28196 band_num++) {
28197 switch (band_num) {
28198 case 0:
28199
28200 tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_2g,
28201 pi->nphy_pwrctrl_info[1].max_pwr_2g);
28202
28203 pwr_offsets1[0] = pi->cck2gpo;
28204 wlc_phy_txpwr_nphy_srom_convert(pi->tx_srom_max_rate_2g,
28205 pwr_offsets1,
28206 tmp_max_pwr,
28207 TXP_FIRST_CCK,
28208 TXP_LAST_CCK);
28209
28210 pwr_offsets1[0] = (u16) (pi->ofdm2gpo & 0xffff);
28211 pwr_offsets1[1] =
28212 (u16) (pi->ofdm2gpo >> 16) & 0xffff;
28213
28214 pwr_offsets2 = pi->mcs2gpo;
28215
28216 tmp_cddpo = pi->cdd2gpo;
28217 tmp_stbcpo = pi->stbc2gpo;
28218 tmp_bw40po = pi->bw402gpo;
28219
28220 tx_srom_max_rate = pi->tx_srom_max_rate_2g;
28221 break;
28222 case 1:
28223
28224 tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gm,
28225 pi->nphy_pwrctrl_info[1].max_pwr_5gm);
28226
28227 pwr_offsets1[0] = (u16) (pi->ofdm5gpo & 0xffff);
28228 pwr_offsets1[1] =
28229 (u16) (pi->ofdm5gpo >> 16) & 0xffff;
28230
28231 pwr_offsets2 = pi->mcs5gpo;
28232
28233 tmp_cddpo = pi->cdd5gpo;
28234 tmp_stbcpo = pi->stbc5gpo;
28235 tmp_bw40po = pi->bw405gpo;
28236
28237 tx_srom_max_rate = pi->tx_srom_max_rate_5g_mid;
28238 break;
28239 case 2:
28240
28241 tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gl,
28242 pi->nphy_pwrctrl_info[1].max_pwr_5gl);
28243
28244 pwr_offsets1[0] = (u16) (pi->ofdm5glpo & 0xffff);
28245 pwr_offsets1[1] =
28246 (u16) (pi->ofdm5glpo >> 16) & 0xffff;
28247
28248 pwr_offsets2 = pi->mcs5glpo;
28249
28250 tmp_cddpo = pi->cdd5glpo;
28251 tmp_stbcpo = pi->stbc5glpo;
28252 tmp_bw40po = pi->bw405glpo;
28253
28254 tx_srom_max_rate = pi->tx_srom_max_rate_5g_low;
28255 break;
28256 case 3:
28257
28258 tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gh,
28259 pi->nphy_pwrctrl_info[1].max_pwr_5gh);
28260
28261 pwr_offsets1[0] = (u16) (pi->ofdm5ghpo & 0xffff);
28262 pwr_offsets1[1] =
28263 (u16) (pi->ofdm5ghpo >> 16) & 0xffff;
28264
28265 pwr_offsets2 = pi->mcs5ghpo;
28266
28267 tmp_cddpo = pi->cdd5ghpo;
28268 tmp_stbcpo = pi->stbc5ghpo;
28269 tmp_bw40po = pi->bw405ghpo;
28270
28271 tx_srom_max_rate = pi->tx_srom_max_rate_5g_hi;
28272 break;
28273 }
28274
28275 wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets1,
28276 tmp_max_pwr, TXP_FIRST_OFDM,
28277 TXP_LAST_OFDM);
28278
28279 wlc_phy_ofdm_to_mcs_powers_nphy(tx_srom_max_rate,
28280 TXP_FIRST_MCS_20_SISO,
28281 TXP_LAST_MCS_20_SISO,
28282 TXP_FIRST_OFDM);
28283
28284 wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2,
28285 tmp_max_pwr,
28286 TXP_FIRST_MCS_20_CDD,
28287 TXP_LAST_MCS_20_CDD);
28288
28289 if (NREV_GE(pi->pubpi.phy_rev, 3))
28290 wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, tmp_cddpo,
28291 TXP_FIRST_MCS_20_CDD,
28292 TXP_LAST_MCS_20_CDD);
28293
28294 wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate,
28295 TXP_FIRST_OFDM_20_CDD,
28296 TXP_LAST_OFDM_20_CDD,
28297 TXP_FIRST_MCS_20_CDD);
28298
28299 wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2,
28300 tmp_max_pwr,
28301 TXP_FIRST_MCS_20_STBC,
28302 TXP_LAST_MCS_20_STBC);
28303
28304 if (NREV_GE(pi->pubpi.phy_rev, 3))
28305 wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate,
28306 tmp_stbcpo,
28307 TXP_FIRST_MCS_20_STBC,
28308 TXP_LAST_MCS_20_STBC);
28309
28310 wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
28311 &pwr_offsets2[2], tmp_max_pwr,
28312 TXP_FIRST_MCS_20_SDM,
28313 TXP_LAST_MCS_20_SDM);
28314
28315 if (NPHY_IS_SROM_REINTERPRET) {
28316
28317 wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
28318 &pwr_offsets2[4],
28319 tmp_max_pwr,
28320 TXP_FIRST_MCS_40_SISO,
28321 TXP_LAST_MCS_40_SISO);
28322
28323 wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate,
28324 TXP_FIRST_OFDM_40_SISO,
28325 TXP_LAST_OFDM_40_SISO,
28326 TXP_FIRST_MCS_40_SISO);
28327
28328 wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
28329 &pwr_offsets2[4],
28330 tmp_max_pwr,
28331 TXP_FIRST_MCS_40_CDD,
28332 TXP_LAST_MCS_40_CDD);
28333
28334 wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, tmp_cddpo,
28335 TXP_FIRST_MCS_40_CDD,
28336 TXP_LAST_MCS_40_CDD);
28337
28338 wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate,
28339 TXP_FIRST_OFDM_40_CDD,
28340 TXP_LAST_OFDM_40_CDD,
28341 TXP_FIRST_MCS_40_CDD);
28342
28343 wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
28344 &pwr_offsets2[4],
28345 tmp_max_pwr,
28346 TXP_FIRST_MCS_40_STBC,
28347 TXP_LAST_MCS_40_STBC);
28348
28349 wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate,
28350 tmp_stbcpo,
28351 TXP_FIRST_MCS_40_STBC,
28352 TXP_LAST_MCS_40_STBC);
28353
28354 wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
28355 &pwr_offsets2[6],
28356 tmp_max_pwr,
28357 TXP_FIRST_MCS_40_SDM,
28358 TXP_LAST_MCS_40_SDM);
28359 } else {
28360
28361 for (rate1 = TXP_FIRST_OFDM_40_SISO, rate2 =
28362 TXP_FIRST_OFDM;
28363 rate1 <= TXP_LAST_MCS_40_SDM;
28364 rate1++, rate2++)
28365 tx_srom_max_rate[rate1] =
28366 tx_srom_max_rate[rate2];
28367 }
28368
28369 if (NREV_GE(pi->pubpi.phy_rev, 3))
28370 wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate,
28371 tmp_bw40po,
28372 TXP_FIRST_OFDM_40_SISO,
28373 TXP_LAST_MCS_40_SDM);
28374
28375 tx_srom_max_rate[TXP_MCS_32] =
28376 tx_srom_max_rate[TXP_FIRST_MCS_40_CDD];
28377 }
28378
28379 return;
28380}
28381
28382void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi)
28383{
28384 u8 tx_pwr_ctrl_state;
28385 wlc_phy_txpwr_limit_to_tbl_nphy(pi);
28386 wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
28387
28388 tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
28389
28390 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
28391 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
28392 (void)R_REG(&pi->regs->maccontrol);
28393 udelay(1);
28394 }
28395
28396 wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
28397
28398 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
28399 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
28400}
28401
28402static bool wlc_phy_txpwr_ison_nphy(struct brcms_phy *pi)
28403{
28404 return read_phy_reg((pi), 0x1e7) & ((0x1 << 15) |
28405 (0x1 << 14) | (0x1 << 13));
28406}
28407
28408u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi)
28409{
28410 u16 tmp;
28411 u16 pwr_idx[2];
28412
28413 if (wlc_phy_txpwr_ison_nphy(pi)) {
28414 pwr_idx[0] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_0);
28415 pwr_idx[1] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_1);
28416
28417 tmp = (pwr_idx[0] << 8) | pwr_idx[1];
28418 } else {
28419 tmp = ((pi->nphy_txpwrindex[PHY_CORE_0].index_internal & 0xff)
28420 << 8) |
28421 (pi->nphy_txpwrindex[PHY_CORE_1].index_internal & 0xff);
28422 }
28423
28424 return tmp;
28425}
28426
28427void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi)
28428{
28429 if (PHY_IPA(pi)
28430 && (pi->nphy_force_papd_cal
28431 || (wlc_phy_txpwr_ison_nphy(pi)
28432 &&
28433 (((u32)
28434 abs(wlc_phy_txpwr_idx_cur_get_nphy(pi, 0) -
28435 pi->nphy_papd_tx_gain_at_last_cal[0]) >= 4)
28436 || ((u32)
28437 abs(wlc_phy_txpwr_idx_cur_get_nphy(pi, 1) -
28438 pi->nphy_papd_tx_gain_at_last_cal[1]) >= 4)))))
28439 wlc_phy_a4(pi, true);
28440}
28441
28442void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type)
28443{
28444 u16 mask = 0, val = 0, ishw = 0;
28445 u8 ctr;
28446 uint core;
28447 u32 tbl_offset;
28448 u32 tbl_len;
28449 u16 regval[84];
28450
28451 if (pi->phyhang_avoid)
28452 wlc_phy_stay_in_carriersearch_nphy(pi, true);
28453
28454 switch (ctrl_type) {
28455 case PHY_TPC_HW_OFF:
28456 case PHY_TPC_HW_ON:
28457 pi->nphy_txpwrctrl = ctrl_type;
28458 break;
28459 default:
28460 break;
28461 }
28462
28463 if (ctrl_type == PHY_TPC_HW_OFF) {
28464 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28465
28466 if (wlc_phy_txpwr_ison_nphy(pi)) {
28467 for (core = 0; core < pi->pubpi.phy_corenum;
28468 core++)
28469 pi->nphy_txpwr_idx[core] =
28470 wlc_phy_txpwr_idx_cur_get_nphy(
28471 pi,
28472 (u8) core);
28473 }
28474
28475 }
28476
28477 tbl_len = 84;
28478 tbl_offset = 64;
28479 for (ctr = 0; ctr < tbl_len; ctr++)
28480 regval[ctr] = 0;
28481 wlc_phy_table_write_nphy(pi, 26, tbl_len, tbl_offset, 16,
28482 regval);
28483 wlc_phy_table_write_nphy(pi, 27, tbl_len, tbl_offset, 16,
28484 regval);
28485
28486 if (NREV_GE(pi->pubpi.phy_rev, 3))
28487 and_phy_reg(pi, 0x1e7,
28488 (u16) (~((0x1 << 15) |
28489 (0x1 << 14) | (0x1 << 13))));
28490 else
28491 and_phy_reg(pi, 0x1e7,
28492 (u16) (~((0x1 << 14) | (0x1 << 13))));
28493
28494 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28495 or_phy_reg(pi, 0x8f, (0x1 << 8));
28496 or_phy_reg(pi, 0xa5, (0x1 << 8));
28497 } else {
28498 or_phy_reg(pi, 0xa5, (0x1 << 14));
28499 }
28500
28501 if (NREV_IS(pi->pubpi.phy_rev, 2))
28502 mod_phy_reg(pi, 0xdc, 0x00ff, 0x53);
28503 else if (NREV_LT(pi->pubpi.phy_rev, 2))
28504 mod_phy_reg(pi, 0xdc, 0x00ff, 0x5a);
28505
28506 if (NREV_LT(pi->pubpi.phy_rev, 2) &&
28507 pi->bw == WL_CHANSPEC_BW_40)
28508 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_IQSWAP_WAR,
28509 MHF1_IQSWAP_WAR, BRCM_BAND_ALL);
28510
28511 } else {
28512
28513 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 84, 64,
28514 8, pi->adj_pwr_tbl_nphy);
28515 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 84, 64,
28516 8, pi->adj_pwr_tbl_nphy);
28517
28518 ishw = (ctrl_type == PHY_TPC_HW_ON) ? 0x1 : 0x0;
28519 mask = (0x1 << 14) | (0x1 << 13);
28520 val = (ishw << 14) | (ishw << 13);
28521
28522 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28523 mask |= (0x1 << 15);
28524 val |= (ishw << 15);
28525 }
28526
28527 mod_phy_reg(pi, 0x1e7, mask, val);
28528
28529 if (CHSPEC_IS5G(pi->radio_chanspec)) {
28530 if (NREV_GE(pi->pubpi.phy_rev, 7)) {
28531 mod_phy_reg(pi, 0x1e7, (0x7f << 0), 0x32);
28532 mod_phy_reg(pi, 0x222, (0xff << 0), 0x32);
28533 } else {
28534 mod_phy_reg(pi, 0x1e7, (0x7f << 0), 0x64);
28535 if (NREV_GT(pi->pubpi.phy_rev, 1))
28536 mod_phy_reg(pi, 0x222,
28537 (0xff << 0), 0x64);
28538 }
28539 }
28540
28541 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28542 if ((pi->nphy_txpwr_idx[0] != 128)
28543 && (pi->nphy_txpwr_idx[1] != 128))
28544 wlc_phy_txpwr_idx_cur_set_nphy(pi,
28545 pi->
28546 nphy_txpwr_idx
28547 [0],
28548 pi->
28549 nphy_txpwr_idx
28550 [1]);
28551 }
28552
28553 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28554 and_phy_reg(pi, 0x8f, ~(0x1 << 8));
28555 and_phy_reg(pi, 0xa5, ~(0x1 << 8));
28556 } else {
28557 and_phy_reg(pi, 0xa5, ~(0x1 << 14));
28558 }
28559
28560 if (NREV_IS(pi->pubpi.phy_rev, 2))
28561 mod_phy_reg(pi, 0xdc, 0x00ff, 0x3b);
28562 else if (NREV_LT(pi->pubpi.phy_rev, 2))
28563 mod_phy_reg(pi, 0xdc, 0x00ff, 0x40);
28564
28565 if (NREV_LT(pi->pubpi.phy_rev, 2) &&
28566 pi->bw == WL_CHANSPEC_BW_40)
28567 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_IQSWAP_WAR,
28568 0x0, BRCM_BAND_ALL);
28569
28570 if (PHY_IPA(pi)) {
28571 mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
28572 0x29b, (0x1 << 2), (0) << 2);
28573
28574 mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
28575 0x29b, (0x1 << 2), (0) << 2);
28576
28577 }
28578
28579 }
28580
28581 if (pi->phyhang_avoid)
28582 wlc_phy_stay_in_carriersearch_nphy(pi, false);
28583}
28584
28585void
28586wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask, s8 txpwrindex,
28587 bool restore_cals)
28588{
28589 u8 core, txpwrctl_tbl;
28590 u16 tx_ind0, iq_ind0, lo_ind0;
28591 u16 m1m2;
28592 u32 txgain;
28593 u16 rad_gain, dac_gain;
28594 u8 bbmult;
28595 u32 iqcomp;
28596 u16 iqcomp_a, iqcomp_b;
28597 u32 locomp;
28598 u16 tmpval;
28599 u8 tx_pwr_ctrl_state;
28600 s32 rfpwr_offset;
28601 u16 regval[2];
28602
28603 if (pi->phyhang_avoid)
28604 wlc_phy_stay_in_carriersearch_nphy(pi, true);
28605
28606 tx_ind0 = 192;
28607 iq_ind0 = 320;
28608 lo_ind0 = 448;
28609
28610 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
28611
28612 if ((core_mask & (1 << core)) == 0)
28613 continue;
28614
28615 txpwrctl_tbl = (core == PHY_CORE_0) ? 26 : 27;
28616
28617 if (txpwrindex < 0) {
28618 if (pi->nphy_txpwrindex[core].index < 0)
28619 continue;
28620
28621 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28622 mod_phy_reg(pi, 0x8f,
28623 (0x1 << 8),
28624 pi->nphy_txpwrindex[core].
28625 AfectrlOverride);
28626 mod_phy_reg(pi, 0xa5, (0x1 << 8),
28627 pi->nphy_txpwrindex[core].
28628 AfectrlOverride);
28629 } else {
28630 mod_phy_reg(pi, 0xa5,
28631 (0x1 << 14),
28632 pi->nphy_txpwrindex[core].
28633 AfectrlOverride);
28634 }
28635
28636 write_phy_reg(pi, (core == PHY_CORE_0) ?
28637 0xaa : 0xab,
28638 pi->nphy_txpwrindex[core].AfeCtrlDacGain);
28639
28640 wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
28641 &pi->nphy_txpwrindex[core].
28642 rad_gain);
28643
28644 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
28645 m1m2 &= ((core == PHY_CORE_0) ? 0x00ff : 0xff00);
28646 m1m2 |= ((core == PHY_CORE_0) ?
28647 (pi->nphy_txpwrindex[core].bbmult << 8) :
28648 (pi->nphy_txpwrindex[core].bbmult << 0));
28649 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
28650
28651 if (restore_cals) {
28652 wlc_phy_table_write_nphy(
28653 pi, 15, 2, (80 + 2 * core), 16,
28654 &pi->nphy_txpwrindex[core].iqcomp_a);
28655 wlc_phy_table_write_nphy(
28656 pi, 15, 1, (85 + core), 16,
28657 &pi->nphy_txpwrindex[core].locomp);
28658 wlc_phy_table_write_nphy(
28659 pi, 15, 1, (93 + core), 16,
28660 &pi->nphy_txpwrindex[core].locomp);
28661 }
28662
28663 wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
28664
28665 pi->nphy_txpwrindex[core].index_internal =
28666 pi->nphy_txpwrindex[core].index_internal_save;
28667 } else {
28668
28669 if (pi->nphy_txpwrindex[core].index < 0) {
28670
28671 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
28672 mod_phy_reg(pi, 0x8f,
28673 (0x1 << 8),
28674 pi->nphy_txpwrindex[core].
28675 AfectrlOverride);
28676 mod_phy_reg(pi, 0xa5, (0x1 << 8),
28677 pi->nphy_txpwrindex[core].
28678 AfectrlOverride);
28679 } else {
28680 pi->nphy_txpwrindex[core].
28681 AfectrlOverride =
28682 read_phy_reg(pi, 0xa5);
28683 }
28684
28685 pi->nphy_txpwrindex[core].AfeCtrlDacGain =
28686 read_phy_reg(pi, (core == PHY_CORE_0) ?
28687 0xaa : 0xab);
28688
28689 wlc_phy_table_read_nphy(pi, 7, 1,
28690 (0x110 + core), 16,
28691 &pi->
28692 nphy_txpwrindex[core].
28693 rad_gain);
28694
28695 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16,
28696 &tmpval);
28697 tmpval >>= ((core == PHY_CORE_0) ? 8 : 0);
28698 tmpval &= 0xff;
28699 pi->nphy_txpwrindex[core].bbmult = (u8) tmpval;
28700
28701 wlc_phy_table_read_nphy(pi, 15, 2,
28702 (80 + 2 * core), 16,
28703 &pi->
28704 nphy_txpwrindex[core].
28705 iqcomp_a);
28706
28707 wlc_phy_table_read_nphy(pi, 15, 1, (85 + core),
28708 16,
28709 &pi->
28710 nphy_txpwrindex[core].
28711 locomp);
28712
28713 pi->nphy_txpwrindex[core].index_internal_save =
28714 pi->nphy_txpwrindex[core].
28715 index_internal;
28716 }
28717
28718 tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
28719 wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
28720
28721 if (NREV_IS(pi->pubpi.phy_rev, 1))
28722 wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
28723
28724 wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
28725 (tx_ind0 + txpwrindex), 32,
28726 &txgain);
28727
28728 if (NREV_GE(pi->pubpi.phy_rev, 3))
28729 rad_gain = (txgain >> 16) &
28730 ((1 << (32 - 16 + 1)) - 1);
28731 else
28732 rad_gain = (txgain >> 16) &
28733 ((1 << (28 - 16 + 1)) - 1);
28734
28735 dac_gain = (txgain >> 8) & ((1 << (13 - 8 + 1)) - 1);
28736 bbmult = (txgain >> 0) & ((1 << (7 - 0 + 1)) - 1);
28737
28738 if (NREV_GE(pi->pubpi.phy_rev, 3))
28739 mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
28740 0xa5), (0x1 << 8), (0x1 << 8));
28741 else
28742 mod_phy_reg(pi, 0xa5, (0x1 << 14), (0x1 << 14));
28743
28744 write_phy_reg(pi, (core == PHY_CORE_0) ?
28745 0xaa : 0xab, dac_gain);
28746
28747 wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
28748 &rad_gain);
28749
28750 wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
28751 m1m2 &= ((core == PHY_CORE_0) ? 0x00ff : 0xff00);
28752 m1m2 |= ((core == PHY_CORE_0) ?
28753 (bbmult << 8) : (bbmult << 0));
28754
28755 wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
28756
28757 wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
28758 (iq_ind0 + txpwrindex), 32,
28759 &iqcomp);
28760 iqcomp_a = (iqcomp >> 10) & ((1 << (19 - 10 + 1)) - 1);
28761 iqcomp_b = (iqcomp >> 0) & ((1 << (9 - 0 + 1)) - 1);
28762
28763 if (restore_cals) {
28764 regval[0] = (u16) iqcomp_a;
28765 regval[1] = (u16) iqcomp_b;
28766 wlc_phy_table_write_nphy(pi, 15, 2,
28767 (80 + 2 * core), 16,
28768 regval);
28769 }
28770
28771 wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
28772 (lo_ind0 + txpwrindex), 32,
28773 &locomp);
28774 if (restore_cals)
28775 wlc_phy_table_write_nphy(pi, 15, 1, (85 + core),
28776 16, &locomp);
28777
28778 if (NREV_IS(pi->pubpi.phy_rev, 1))
28779 wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
28780
28781 if (PHY_IPA(pi)) {
28782 wlc_phy_table_read_nphy(pi,
28783 (core == PHY_CORE_0 ?
28784 NPHY_TBL_ID_CORE1TXPWRCTL :
28785 NPHY_TBL_ID_CORE2TXPWRCTL),
28786 1, 576 + txpwrindex, 32,
28787 &rfpwr_offset);
28788
28789 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
28790 0x29b, (0x1ff << 4),
28791 ((s16) rfpwr_offset) << 4);
28792
28793 mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
28794 0x29b, (0x1 << 2), (1) << 2);
28795
28796 }
28797
28798 wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
28799 }
28800
28801 pi->nphy_txpwrindex[core].index = txpwrindex;
28802 }
28803
28804 if (pi->phyhang_avoid)
28805 wlc_phy_stay_in_carriersearch_nphy(pi, false);
28806}
28807
28808void
28809wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan, u8 *max_pwr,
28810 u8 txp_rate_idx)
28811{
28812 u8 chan_freq_range;
28813
28814 chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, chan);
28815 switch (chan_freq_range) {
28816 case WL_CHAN_FREQ_RANGE_2G:
28817 *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
28818 break;
28819 case WL_CHAN_FREQ_RANGE_5GM:
28820 *max_pwr = pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
28821 break;
28822 case WL_CHAN_FREQ_RANGE_5GL:
28823 *max_pwr = pi->tx_srom_max_rate_5g_low[txp_rate_idx];
28824 break;
28825 case WL_CHAN_FREQ_RANGE_5GH:
28826 *max_pwr = pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
28827 break;
28828 default:
28829 *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
28830 break;
28831 }
28832
28833 return;
28834}
28835
28836void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi, bool enable)
28837{
28838 u16 clip_off[] = { 0xffff, 0xffff };
28839
28840 if (enable) {
28841 if (pi->nphy_deaf_count == 0) {
28842 pi->classifier_state =
28843 wlc_phy_classifier_nphy(pi, 0, 0);
28844 wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
28845 wlc_phy_clip_det_nphy(pi, 0, pi->clip_state);
28846 wlc_phy_clip_det_nphy(pi, 1, clip_off);
28847 }
28848
28849 pi->nphy_deaf_count++;
28850
28851 wlc_phy_resetcca_nphy(pi);
28852
28853 } else {
28854 pi->nphy_deaf_count--;
28855
28856 if (pi->nphy_deaf_count == 0) {
28857 wlc_phy_classifier_nphy(pi, (0x7 << 0),
28858 pi->classifier_state);
28859 wlc_phy_clip_det_nphy(pi, 1, pi->clip_state);
28860 }
28861 }
28862}
28863
28864void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode)
28865{
28866 wlapi_suspend_mac_and_wait(pi->sh->physhim);
28867
28868 if (mode) {
28869 if (pi->nphy_deaf_count == 0)
28870 wlc_phy_stay_in_carriersearch_nphy(pi, true);
28871 } else if (pi->nphy_deaf_count > 0) {
28872 wlc_phy_stay_in_carriersearch_nphy(pi, false);
28873 }
28874
28875 wlapi_enable_mac(pi->sh->physhim);
28876}
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.c b/drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.c
deleted file mode 100644
index faf1ebe7606..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.c
+++ /dev/null
@@ -1,308 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "phy_qmath.h"
18
19/*
20 * Description: This function make 16 bit unsigned multiplication.
21 * To fit the output into 16 bits the 32 bit multiplication result is right
22 * shifted by 16 bits.
23 */
24u16 qm_mulu16(u16 op1, u16 op2)
25{
26 return (u16) (((u32) op1 * (u32) op2) >> 16);
27}
28
29/*
30 * Description: This function make 16 bit multiplication and return the result
31 * in 16 bits. To fit the multiplication result into 16 bits the multiplication
32 * result is right shifted by 15 bits. Right shifting 15 bits instead of 16 bits
33 * is done to remove the extra sign bit formed due to the multiplication.
34 * When both the 16bit inputs are 0x8000 then the output is saturated to
35 * 0x7fffffff.
36 */
37s16 qm_muls16(s16 op1, s16 op2)
38{
39 s32 result;
40 if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000)
41 result = 0x7fffffff;
42 else
43 result = ((s32) (op1) * (s32) (op2));
44
45 return (s16) (result >> 15);
46}
47
48/*
49 * Description: This function add two 32 bit numbers and return the 32bit
50 * result. If the result overflow 32 bits, the output will be saturated to
51 * 32bits.
52 */
53s32 qm_add32(s32 op1, s32 op2)
54{
55 s32 result;
56 result = op1 + op2;
57 if (op1 < 0 && op2 < 0 && result > 0)
58 result = 0x80000000;
59 else if (op1 > 0 && op2 > 0 && result < 0)
60 result = 0x7fffffff;
61
62 return result;
63}
64
65/*
66 * Description: This function add two 16 bit numbers and return the 16bit
67 * result. If the result overflow 16 bits, the output will be saturated to
68 * 16bits.
69 */
70s16 qm_add16(s16 op1, s16 op2)
71{
72 s16 result;
73 s32 temp = (s32) op1 + (s32) op2;
74 if (temp > (s32) 0x7fff)
75 result = (s16) 0x7fff;
76 else if (temp < (s32) 0xffff8000)
77 result = (s16) 0xffff8000;
78 else
79 result = (s16) temp;
80
81 return result;
82}
83
84/*
85 * Description: This function make 16 bit subtraction and return the 16bit
86 * result. If the result overflow 16 bits, the output will be saturated to
87 * 16bits.
88 */
89s16 qm_sub16(s16 op1, s16 op2)
90{
91 s16 result;
92 s32 temp = (s32) op1 - (s32) op2;
93 if (temp > (s32) 0x7fff)
94 result = (s16) 0x7fff;
95 else if (temp < (s32) 0xffff8000)
96 result = (s16) 0xffff8000;
97 else
98 result = (s16) temp;
99
100 return result;
101}
102
103/*
104 * Description: This function make a 32 bit saturated left shift when the
105 * specified shift is +ve. This function will make a 32 bit right shift when
106 * the specified shift is -ve. This function return the result after shifting
107 * operation.
108 */
109s32 qm_shl32(s32 op, int shift)
110{
111 int i;
112 s32 result;
113 result = op;
114 if (shift > 31)
115 shift = 31;
116 else if (shift < -31)
117 shift = -31;
118 if (shift >= 0) {
119 for (i = 0; i < shift; i++)
120 result = qm_add32(result, result);
121 } else {
122 result = result >> (-shift);
123 }
124
125 return result;
126}
127
128/*
129 * Description: This function make a 16 bit saturated left shift when the
130 * specified shift is +ve. This function will make a 16 bit right shift when
131 * the specified shift is -ve. This function return the result after shifting
132 * operation.
133 */
134s16 qm_shl16(s16 op, int shift)
135{
136 int i;
137 s16 result;
138 result = op;
139 if (shift > 15)
140 shift = 15;
141 else if (shift < -15)
142 shift = -15;
143 if (shift > 0) {
144 for (i = 0; i < shift; i++)
145 result = qm_add16(result, result);
146 } else {
147 result = result >> (-shift);
148 }
149
150 return result;
151}
152
153/*
154 * Description: This function make a 16 bit right shift when shift is +ve.
155 * This function make a 16 bit saturated left shift when shift is -ve. This
156 * function return the result of the shift operation.
157 */
158s16 qm_shr16(s16 op, int shift)
159{
160 return qm_shl16(op, -shift);
161}
162
163/*
164 * Description: This function return the number of redundant sign bits in a
165 * 32 bit number. Example: qm_norm32(0x00000080) = 23
166 */
167s16 qm_norm32(s32 op)
168{
169 u16 u16extraSignBits;
170 if (op == 0) {
171 return 31;
172 } else {
173 u16extraSignBits = 0;
174 while ((op >> 31) == (op >> 30)) {
175 u16extraSignBits++;
176 op = op << 1;
177 }
178 }
179 return u16extraSignBits;
180}
181
182/* This table is log2(1+(i/32)) where i=[0:1:31], in q.15 format */
183static const s16 log_table[] = {
184 0,
185 1455,
186 2866,
187 4236,
188 5568,
189 6863,
190 8124,
191 9352,
192 10549,
193 11716,
194 12855,
195 13968,
196 15055,
197 16117,
198 17156,
199 18173,
200 19168,
201 20143,
202 21098,
203 22034,
204 22952,
205 23852,
206 24736,
207 25604,
208 26455,
209 27292,
210 28114,
211 28922,
212 29717,
213 30498,
214 31267,
215 32024
216};
217
218#define LOG_TABLE_SIZE 32 /* log_table size */
219#define LOG2_LOG_TABLE_SIZE 5 /* log2(log_table size) */
220#define Q_LOG_TABLE 15 /* qformat of log_table */
221#define LOG10_2 19728 /* log10(2) in q.16 */
222
223/*
224 * Description:
225 * This routine takes the input number N and its q format qN and compute
226 * the log10(N). This routine first normalizes the input no N. Then N is in
227 * mag*(2^x) format. mag is any number in the range 2^30-(2^31 - 1).
228 * Then log2(mag * 2^x) = log2(mag) + x is computed. From that
229 * log10(mag * 2^x) = log2(mag * 2^x) * log10(2) is computed.
230 * This routine looks the log2 value in the table considering
231 * LOG2_LOG_TABLE_SIZE+1 MSBs. As the MSB is always 1, only next
232 * LOG2_OF_LOG_TABLE_SIZE MSBs are used for table lookup. Next 16 MSBs are used
233 * for interpolation.
234 * Inputs:
235 * N - number to which log10 has to be found.
236 * qN - q format of N
237 * log10N - address where log10(N) will be written.
238 * qLog10N - address where log10N qformat will be written.
239 * Note/Problem:
240 * For accurate results input should be in normalized or near normalized form.
241 */
242void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N)
243{
244 s16 s16norm, s16tableIndex, s16errorApproximation;
245 u16 u16offset;
246 s32 s32log;
247
248 /* normalize the N. */
249 s16norm = qm_norm32(N);
250 N = N << s16norm;
251
252 /* The qformat of N after normalization.
253 * -30 is added to treat the no as between 1.0 to 2.0
254 * i.e. after adding the -30 to the qformat the decimal point will be
255 * just rigtht of the MSB. (i.e. after sign bit and 1st MSB). i.e.
256 * at the right side of 30th bit.
257 */
258 qN = qN + s16norm - 30;
259
260 /* take the table index as the LOG2_OF_LOG_TABLE_SIZE bits right of the
261 * MSB */
262 s16tableIndex = (s16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE)));
263
264 /* remove the MSB. the MSB is always 1 after normalization. */
265 s16tableIndex =
266 s16tableIndex & (s16) ((1 << LOG2_LOG_TABLE_SIZE) - 1);
267
268 /* remove the (1+LOG2_OF_LOG_TABLE_SIZE) MSBs in the N. */
269 N = N & ((1 << (32 - (2 + LOG2_LOG_TABLE_SIZE))) - 1);
270
271 /* take the offset as the 16 MSBS after table index.
272 */
273 u16offset = (u16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE + 16)));
274
275 /* look the log value in the table. */
276 s32log = log_table[s16tableIndex]; /* q.15 format */
277
278 /* interpolate using the offset. q.15 format. */
279 s16errorApproximation = (s16) qm_mulu16(u16offset,
280 (u16) (log_table[s16tableIndex + 1] -
281 log_table[s16tableIndex]));
282
283 /* q.15 format */
284 s32log = qm_add16((s16) s32log, s16errorApproximation);
285
286 /* adjust for the qformat of the N as
287 * log2(mag * 2^x) = log2(mag) + x
288 */
289 s32log = qm_add32(s32log, ((s32) -qN) << 15); /* q.15 format */
290
291 /* normalize the result. */
292 s16norm = qm_norm32(s32log);
293
294 /* bring all the important bits into lower 16 bits */
295 /* q.15+s16norm-16 format */
296 s32log = qm_shl32(s32log, s16norm - 16);
297
298 /* compute the log10(N) by multiplying log2(N) with log10(2).
299 * as log10(mag * 2^x) = log2(mag * 2^x) * log10(2)
300 * log10N in q.15+s16norm-16+1 (LOG10_2 is in q.16)
301 */
302 *log10N = qm_muls16((s16) s32log, (s16) LOG10_2);
303
304 /* write the q format of the result. */
305 *qLog10N = 15 + s16norm - 16 + 1;
306
307 return;
308}
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.h b/drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.h
deleted file mode 100644
index 20e3783f921..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_QMATH_H_
18#define _BRCM_QMATH_H_
19
20#include <types.h>
21
22u16 qm_mulu16(u16 op1, u16 op2);
23
24s16 qm_muls16(s16 op1, s16 op2);
25
26s32 qm_add32(s32 op1, s32 op2);
27
28s16 qm_add16(s16 op1, s16 op2);
29
30s16 qm_sub16(s16 op1, s16 op2);
31
32s32 qm_shl32(s32 op, int shift);
33
34s16 qm_shl16(s16 op, int shift);
35
36s16 qm_shr16(s16 op, int shift);
37
38s16 qm_norm32(s32 op);
39
40void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N);
41
42#endif /* #ifndef _BRCM_QMATH_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_radio.h b/drivers/staging/brcm80211/brcmsmac/phy/phy_radio.h
deleted file mode 100644
index c3a675455ff..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_radio.h
+++ /dev/null
@@ -1,1533 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_PHY_RADIO_H_
18#define _BRCM_PHY_RADIO_H_
19
20#define RADIO_IDCODE 0x01
21
22#define RADIO_DEFAULT_CORE 0
23
24#define RXC0_RSSI_RST 0x80
25#define RXC0_MODE_RSSI 0x40
26#define RXC0_MODE_OFF 0x20
27#define RXC0_MODE_CM 0x10
28#define RXC0_LAN_LOAD 0x08
29#define RXC0_OFF_ADJ_MASK 0x07
30
31#define TXC0_MODE_TXLPF 0x04
32#define TXC0_PA_TSSI_EN 0x02
33#define TXC0_TSSI_EN 0x01
34
35#define TXC1_PA_GAIN_MASK 0x60
36#define TXC1_PA_GAIN_3DB 0x40
37#define TXC1_PA_GAIN_2DB 0x20
38#define TXC1_TX_MIX_GAIN 0x10
39#define TXC1_OFF_I_MASK 0x0c
40#define TXC1_OFF_Q_MASK 0x03
41
42#define RADIO_2055_READ_OFF 0x100
43#define RADIO_2057_READ_OFF 0x200
44
45#define RADIO_2055_GEN_SPARE 0x00
46#define RADIO_2055_SP_PIN_PD 0x02
47#define RADIO_2055_SP_RSSI_CORE1 0x03
48#define RADIO_2055_SP_PD_MISC_CORE1 0x04
49#define RADIO_2055_SP_RSSI_CORE2 0x05
50#define RADIO_2055_SP_PD_MISC_CORE2 0x06
51#define RADIO_2055_SP_RX_GC1_CORE1 0x07
52#define RADIO_2055_SP_RX_GC2_CORE1 0x08
53#define RADIO_2055_SP_RX_GC1_CORE2 0x09
54#define RADIO_2055_SP_RX_GC2_CORE2 0x0a
55#define RADIO_2055_SP_LPF_BW_SELECT_CORE1 0x0b
56#define RADIO_2055_SP_LPF_BW_SELECT_CORE2 0x0c
57#define RADIO_2055_SP_TX_GC1_CORE1 0x0d
58#define RADIO_2055_SP_TX_GC2_CORE1 0x0e
59#define RADIO_2055_SP_TX_GC1_CORE2 0x0f
60#define RADIO_2055_SP_TX_GC2_CORE2 0x10
61#define RADIO_2055_MASTER_CNTRL1 0x11
62#define RADIO_2055_MASTER_CNTRL2 0x12
63#define RADIO_2055_PD_LGEN 0x13
64#define RADIO_2055_PD_PLL_TS 0x14
65#define RADIO_2055_PD_CORE1_LGBUF 0x15
66#define RADIO_2055_PD_CORE1_TX 0x16
67#define RADIO_2055_PD_CORE1_RXTX 0x17
68#define RADIO_2055_PD_CORE1_RSSI_MISC 0x18
69#define RADIO_2055_PD_CORE2_LGBUF 0x19
70#define RADIO_2055_PD_CORE2_TX 0x1a
71#define RADIO_2055_PD_CORE2_RXTX 0x1b
72#define RADIO_2055_PD_CORE2_RSSI_MISC 0x1c
73#define RADIO_2055_PWRDET_LGEN 0x1d
74#define RADIO_2055_PWRDET_LGBUF_CORE1 0x1e
75#define RADIO_2055_PWRDET_RXTX_CORE1 0x1f
76#define RADIO_2055_PWRDET_LGBUF_CORE2 0x20
77#define RADIO_2055_PWRDET_RXTX_CORE2 0x21
78#define RADIO_2055_RRCCAL_CNTRL_SPARE 0x22
79#define RADIO_2055_RRCCAL_N_OPT_SEL 0x23
80#define RADIO_2055_CAL_MISC 0x24
81#define RADIO_2055_CAL_COUNTER_OUT 0x25
82#define RADIO_2055_CAL_COUNTER_OUT2 0x26
83#define RADIO_2055_CAL_CVAR_CNTRL 0x27
84#define RADIO_2055_CAL_RVAR_CNTRL 0x28
85#define RADIO_2055_CAL_LPO_CNTRL 0x29
86#define RADIO_2055_CAL_TS 0x2a
87#define RADIO_2055_CAL_RCCAL_READ_TS 0x2b
88#define RADIO_2055_CAL_RCAL_READ_TS 0x2c
89#define RADIO_2055_PAD_DRIVER 0x2d
90#define RADIO_2055_XO_CNTRL1 0x2e
91#define RADIO_2055_XO_CNTRL2 0x2f
92#define RADIO_2055_XO_REGULATOR 0x30
93#define RADIO_2055_XO_MISC 0x31
94#define RADIO_2055_PLL_LF_C1 0x32
95#define RADIO_2055_PLL_CAL_VTH 0x33
96#define RADIO_2055_PLL_LF_C2 0x34
97#define RADIO_2055_PLL_REF 0x35
98#define RADIO_2055_PLL_LF_R1 0x36
99#define RADIO_2055_PLL_PFD_CP 0x37
100#define RADIO_2055_PLL_IDAC_CPOPAMP 0x38
101#define RADIO_2055_PLL_CP_REGULATOR 0x39
102#define RADIO_2055_PLL_RCAL 0x3a
103#define RADIO_2055_RF_PLL_MOD0 0x3b
104#define RADIO_2055_RF_PLL_MOD1 0x3c
105#define RADIO_2055_RF_MMD_IDAC1 0x3d
106#define RADIO_2055_RF_MMD_IDAC0 0x3e
107#define RADIO_2055_RF_MMD_SPARE 0x3f
108#define RADIO_2055_VCO_CAL1 0x40
109#define RADIO_2055_VCO_CAL2 0x41
110#define RADIO_2055_VCO_CAL3 0x42
111#define RADIO_2055_VCO_CAL4 0x43
112#define RADIO_2055_VCO_CAL5 0x44
113#define RADIO_2055_VCO_CAL6 0x45
114#define RADIO_2055_VCO_CAL7 0x46
115#define RADIO_2055_VCO_CAL8 0x47
116#define RADIO_2055_VCO_CAL9 0x48
117#define RADIO_2055_VCO_CAL10 0x49
118#define RADIO_2055_VCO_CAL11 0x4a
119#define RADIO_2055_VCO_CAL12 0x4b
120#define RADIO_2055_VCO_CAL13 0x4c
121#define RADIO_2055_VCO_CAL14 0x4d
122#define RADIO_2055_VCO_CAL15 0x4e
123#define RADIO_2055_VCO_CAL16 0x4f
124#define RADIO_2055_VCO_KVCO 0x50
125#define RADIO_2055_VCO_CAP_TAIL 0x51
126#define RADIO_2055_VCO_IDAC_VCO 0x52
127#define RADIO_2055_VCO_REGULATOR 0x53
128#define RADIO_2055_PLL_RF_VTH 0x54
129#define RADIO_2055_LGBUF_CEN_BUF 0x55
130#define RADIO_2055_LGEN_TUNE1 0x56
131#define RADIO_2055_LGEN_TUNE2 0x57
132#define RADIO_2055_LGEN_IDAC1 0x58
133#define RADIO_2055_LGEN_IDAC2 0x59
134#define RADIO_2055_LGEN_BIAS_CNT 0x5a
135#define RADIO_2055_LGEN_BIAS_IDAC 0x5b
136#define RADIO_2055_LGEN_RCAL 0x5c
137#define RADIO_2055_LGEN_DIV 0x5d
138#define RADIO_2055_LGEN_SPARE2 0x5e
139#define RADIO_2055_CORE1_LGBUF_A_TUNE 0x5f
140#define RADIO_2055_CORE1_LGBUF_G_TUNE 0x60
141#define RADIO_2055_CORE1_LGBUF_DIV 0x61
142#define RADIO_2055_CORE1_LGBUF_A_IDAC 0x62
143#define RADIO_2055_CORE1_LGBUF_G_IDAC 0x63
144#define RADIO_2055_CORE1_LGBUF_IDACFIL_OVR 0x64
145#define RADIO_2055_CORE1_LGBUF_SPARE 0x65
146#define RADIO_2055_CORE1_RXRF_SPC1 0x66
147#define RADIO_2055_CORE1_RXRF_REG1 0x67
148#define RADIO_2055_CORE1_RXRF_REG2 0x68
149#define RADIO_2055_CORE1_RXRF_RCAL 0x69
150#define RADIO_2055_CORE1_RXBB_BUFI_LPFCMP 0x6a
151#define RADIO_2055_CORE1_RXBB_LPF 0x6b
152#define RADIO_2055_CORE1_RXBB_MIDAC_HIPAS 0x6c
153#define RADIO_2055_CORE1_RXBB_VGA1_IDAC 0x6d
154#define RADIO_2055_CORE1_RXBB_VGA2_IDAC 0x6e
155#define RADIO_2055_CORE1_RXBB_VGA3_IDAC 0x6f
156#define RADIO_2055_CORE1_RXBB_BUFO_CTRL 0x70
157#define RADIO_2055_CORE1_RXBB_RCCAL_CTRL 0x71
158#define RADIO_2055_CORE1_RXBB_RSSI_CTRL1 0x72
159#define RADIO_2055_CORE1_RXBB_RSSI_CTRL2 0x73
160#define RADIO_2055_CORE1_RXBB_RSSI_CTRL3 0x74
161#define RADIO_2055_CORE1_RXBB_RSSI_CTRL4 0x75
162#define RADIO_2055_CORE1_RXBB_RSSI_CTRL5 0x76
163#define RADIO_2055_CORE1_RXBB_REGULATOR 0x77
164#define RADIO_2055_CORE1_RXBB_SPARE1 0x78
165#define RADIO_2055_CORE1_RXTXBB_RCAL 0x79
166#define RADIO_2055_CORE1_TXRF_SGM_PGA 0x7a
167#define RADIO_2055_CORE1_TXRF_SGM_PAD 0x7b
168#define RADIO_2055_CORE1_TXRF_CNTR_PGA1 0x7c
169#define RADIO_2055_CORE1_TXRF_CNTR_PAD1 0x7d
170#define RADIO_2055_CORE1_TX_RFPGA_IDAC 0x7e
171#define RADIO_2055_CORE1_TX_PGA_PAD_TN 0x7f
172#define RADIO_2055_CORE1_TX_PAD_IDAC1 0x80
173#define RADIO_2055_CORE1_TX_PAD_IDAC2 0x81
174#define RADIO_2055_CORE1_TX_MX_BGTRIM 0x82
175#define RADIO_2055_CORE1_TXRF_RCAL 0x83
176#define RADIO_2055_CORE1_TXRF_PAD_TSSI1 0x84
177#define RADIO_2055_CORE1_TXRF_PAD_TSSI2 0x85
178#define RADIO_2055_CORE1_TX_RF_SPARE 0x86
179#define RADIO_2055_CORE1_TXRF_IQCAL1 0x87
180#define RADIO_2055_CORE1_TXRF_IQCAL2 0x88
181#define RADIO_2055_CORE1_TXBB_RCCAL_CTRL 0x89
182#define RADIO_2055_CORE1_TXBB_LPF1 0x8a
183#define RADIO_2055_CORE1_TX_VOS_CNCL 0x8b
184#define RADIO_2055_CORE1_TX_LPF_MXGM_IDAC 0x8c
185#define RADIO_2055_CORE1_TX_BB_MXGM 0x8d
186#define RADIO_2055_CORE2_LGBUF_A_TUNE 0x8e
187#define RADIO_2055_CORE2_LGBUF_G_TUNE 0x8f
188#define RADIO_2055_CORE2_LGBUF_DIV 0x90
189#define RADIO_2055_CORE2_LGBUF_A_IDAC 0x91
190#define RADIO_2055_CORE2_LGBUF_G_IDAC 0x92
191#define RADIO_2055_CORE2_LGBUF_IDACFIL_OVR 0x93
192#define RADIO_2055_CORE2_LGBUF_SPARE 0x94
193#define RADIO_2055_CORE2_RXRF_SPC1 0x95
194#define RADIO_2055_CORE2_RXRF_REG1 0x96
195#define RADIO_2055_CORE2_RXRF_REG2 0x97
196#define RADIO_2055_CORE2_RXRF_RCAL 0x98
197#define RADIO_2055_CORE2_RXBB_BUFI_LPFCMP 0x99
198#define RADIO_2055_CORE2_RXBB_LPF 0x9a
199#define RADIO_2055_CORE2_RXBB_MIDAC_HIPAS 0x9b
200#define RADIO_2055_CORE2_RXBB_VGA1_IDAC 0x9c
201#define RADIO_2055_CORE2_RXBB_VGA2_IDAC 0x9d
202#define RADIO_2055_CORE2_RXBB_VGA3_IDAC 0x9e
203#define RADIO_2055_CORE2_RXBB_BUFO_CTRL 0x9f
204#define RADIO_2055_CORE2_RXBB_RCCAL_CTRL 0xa0
205#define RADIO_2055_CORE2_RXBB_RSSI_CTRL1 0xa1
206#define RADIO_2055_CORE2_RXBB_RSSI_CTRL2 0xa2
207#define RADIO_2055_CORE2_RXBB_RSSI_CTRL3 0xa3
208#define RADIO_2055_CORE2_RXBB_RSSI_CTRL4 0xa4
209#define RADIO_2055_CORE2_RXBB_RSSI_CTRL5 0xa5
210#define RADIO_2055_CORE2_RXBB_REGULATOR 0xa6
211#define RADIO_2055_CORE2_RXBB_SPARE1 0xa7
212#define RADIO_2055_CORE2_RXTXBB_RCAL 0xa8
213#define RADIO_2055_CORE2_TXRF_SGM_PGA 0xa9
214#define RADIO_2055_CORE2_TXRF_SGM_PAD 0xaa
215#define RADIO_2055_CORE2_TXRF_CNTR_PGA1 0xab
216#define RADIO_2055_CORE2_TXRF_CNTR_PAD1 0xac
217#define RADIO_2055_CORE2_TX_RFPGA_IDAC 0xad
218#define RADIO_2055_CORE2_TX_PGA_PAD_TN 0xae
219#define RADIO_2055_CORE2_TX_PAD_IDAC1 0xaf
220#define RADIO_2055_CORE2_TX_PAD_IDAC2 0xb0
221#define RADIO_2055_CORE2_TX_MX_BGTRIM 0xb1
222#define RADIO_2055_CORE2_TXRF_RCAL 0xb2
223#define RADIO_2055_CORE2_TXRF_PAD_TSSI1 0xb3
224#define RADIO_2055_CORE2_TXRF_PAD_TSSI2 0xb4
225#define RADIO_2055_CORE2_TX_RF_SPARE 0xb5
226#define RADIO_2055_CORE2_TXRF_IQCAL1 0xb6
227#define RADIO_2055_CORE2_TXRF_IQCAL2 0xb7
228#define RADIO_2055_CORE2_TXBB_RCCAL_CTRL 0xb8
229#define RADIO_2055_CORE2_TXBB_LPF1 0xb9
230#define RADIO_2055_CORE2_TX_VOS_CNCL 0xba
231#define RADIO_2055_CORE2_TX_LPF_MXGM_IDAC 0xbb
232#define RADIO_2055_CORE2_TX_BB_MXGM 0xbc
233#define RADIO_2055_PRG_GC_HPVGA23_21 0xbd
234#define RADIO_2055_PRG_GC_HPVGA23_22 0xbe
235#define RADIO_2055_PRG_GC_HPVGA23_23 0xbf
236#define RADIO_2055_PRG_GC_HPVGA23_24 0xc0
237#define RADIO_2055_PRG_GC_HPVGA23_25 0xc1
238#define RADIO_2055_PRG_GC_HPVGA23_26 0xc2
239#define RADIO_2055_PRG_GC_HPVGA23_27 0xc3
240#define RADIO_2055_PRG_GC_HPVGA23_28 0xc4
241#define RADIO_2055_PRG_GC_HPVGA23_29 0xc5
242#define RADIO_2055_PRG_GC_HPVGA23_30 0xc6
243#define RADIO_2055_CORE1_LNA_GAINBST 0xcd
244#define RADIO_2055_CORE1_B0_NBRSSI_VCM 0xd2
245#define RADIO_2055_CORE1_GEN_SPARE2 0xd6
246#define RADIO_2055_CORE2_LNA_GAINBST 0xd9
247#define RADIO_2055_CORE2_B0_NBRSSI_VCM 0xde
248#define RADIO_2055_CORE2_GEN_SPARE2 0xe2
249
250#define RADIO_2055_GAINBST_GAIN_DB 6
251#define RADIO_2055_GAINBST_CODE 0x6
252
253#define RADIO_2055_JTAGCTRL_MASK 0x04
254#define RADIO_2055_JTAGSYNC_MASK 0x08
255#define RADIO_2055_RRCAL_START 0x40
256#define RADIO_2055_RRCAL_RST_N 0x01
257#define RADIO_2055_CAL_LPO_ENABLE 0x80
258#define RADIO_2055_RCAL_DONE 0x80
259#define RADIO_2055_NBRSSI_VCM_I_MASK 0x03
260#define RADIO_2055_NBRSSI_VCM_I_SHIFT 0x00
261#define RADIO_2055_NBRSSI_VCM_Q_MASK 0x03
262#define RADIO_2055_NBRSSI_VCM_Q_SHIFT 0x00
263#define RADIO_2055_WBRSSI_VCM_IQ_MASK 0x0c
264#define RADIO_2055_WBRSSI_VCM_IQ_SHIFT 0x02
265#define RADIO_2055_NBRSSI_PD 0x01
266#define RADIO_2055_WBRSSI_G1_PD 0x04
267#define RADIO_2055_WBRSSI_G2_PD 0x02
268#define RADIO_2055_NBRSSI_SEL 0x01
269#define RADIO_2055_WBRSSI_G1_SEL 0x04
270#define RADIO_2055_WBRSSI_G2_SEL 0x02
271#define RADIO_2055_COUPLE_RX_MASK 0x01
272#define RADIO_2055_COUPLE_TX_MASK 0x02
273#define RADIO_2055_GAINBST_DISABLE 0x02
274#define RADIO_2055_GAINBST_VAL_MASK 0x07
275#define RADIO_2055_RXMX_GC_MASK 0x0c
276
277#define RADIO_MIMO_CORESEL_OFF 0x0
278#define RADIO_MIMO_CORESEL_CORE1 0x1
279#define RADIO_MIMO_CORESEL_CORE2 0x2
280#define RADIO_MIMO_CORESEL_CORE3 0x3
281#define RADIO_MIMO_CORESEL_CORE4 0x4
282#define RADIO_MIMO_CORESEL_ALLRX 0x5
283#define RADIO_MIMO_CORESEL_ALLTX 0x6
284#define RADIO_MIMO_CORESEL_ALLRXTX 0x7
285
286#define RADIO_2064_READ_OFF 0x200
287
288#define RADIO_2064_REG000 0x0
289#define RADIO_2064_REG001 0x1
290#define RADIO_2064_REG002 0x2
291#define RADIO_2064_REG003 0x3
292#define RADIO_2064_REG004 0x4
293#define RADIO_2064_REG005 0x5
294#define RADIO_2064_REG006 0x6
295#define RADIO_2064_REG007 0x7
296#define RADIO_2064_REG008 0x8
297#define RADIO_2064_REG009 0x9
298#define RADIO_2064_REG00A 0xa
299#define RADIO_2064_REG00B 0xb
300#define RADIO_2064_REG00C 0xc
301#define RADIO_2064_REG00D 0xd
302#define RADIO_2064_REG00E 0xe
303#define RADIO_2064_REG00F 0xf
304#define RADIO_2064_REG010 0x10
305#define RADIO_2064_REG011 0x11
306#define RADIO_2064_REG012 0x12
307#define RADIO_2064_REG013 0x13
308#define RADIO_2064_REG014 0x14
309#define RADIO_2064_REG015 0x15
310#define RADIO_2064_REG016 0x16
311#define RADIO_2064_REG017 0x17
312#define RADIO_2064_REG018 0x18
313#define RADIO_2064_REG019 0x19
314#define RADIO_2064_REG01A 0x1a
315#define RADIO_2064_REG01B 0x1b
316#define RADIO_2064_REG01C 0x1c
317#define RADIO_2064_REG01D 0x1d
318#define RADIO_2064_REG01E 0x1e
319#define RADIO_2064_REG01F 0x1f
320#define RADIO_2064_REG020 0x20
321#define RADIO_2064_REG021 0x21
322#define RADIO_2064_REG022 0x22
323#define RADIO_2064_REG023 0x23
324#define RADIO_2064_REG024 0x24
325#define RADIO_2064_REG025 0x25
326#define RADIO_2064_REG026 0x26
327#define RADIO_2064_REG027 0x27
328#define RADIO_2064_REG028 0x28
329#define RADIO_2064_REG029 0x29
330#define RADIO_2064_REG02A 0x2a
331#define RADIO_2064_REG02B 0x2b
332#define RADIO_2064_REG02C 0x2c
333#define RADIO_2064_REG02D 0x2d
334#define RADIO_2064_REG02E 0x2e
335#define RADIO_2064_REG02F 0x2f
336#define RADIO_2064_REG030 0x30
337#define RADIO_2064_REG031 0x31
338#define RADIO_2064_REG032 0x32
339#define RADIO_2064_REG033 0x33
340#define RADIO_2064_REG034 0x34
341#define RADIO_2064_REG035 0x35
342#define RADIO_2064_REG036 0x36
343#define RADIO_2064_REG037 0x37
344#define RADIO_2064_REG038 0x38
345#define RADIO_2064_REG039 0x39
346#define RADIO_2064_REG03A 0x3a
347#define RADIO_2064_REG03B 0x3b
348#define RADIO_2064_REG03C 0x3c
349#define RADIO_2064_REG03D 0x3d
350#define RADIO_2064_REG03E 0x3e
351#define RADIO_2064_REG03F 0x3f
352#define RADIO_2064_REG040 0x40
353#define RADIO_2064_REG041 0x41
354#define RADIO_2064_REG042 0x42
355#define RADIO_2064_REG043 0x43
356#define RADIO_2064_REG044 0x44
357#define RADIO_2064_REG045 0x45
358#define RADIO_2064_REG046 0x46
359#define RADIO_2064_REG047 0x47
360#define RADIO_2064_REG048 0x48
361#define RADIO_2064_REG049 0x49
362#define RADIO_2064_REG04A 0x4a
363#define RADIO_2064_REG04B 0x4b
364#define RADIO_2064_REG04C 0x4c
365#define RADIO_2064_REG04D 0x4d
366#define RADIO_2064_REG04E 0x4e
367#define RADIO_2064_REG04F 0x4f
368#define RADIO_2064_REG050 0x50
369#define RADIO_2064_REG051 0x51
370#define RADIO_2064_REG052 0x52
371#define RADIO_2064_REG053 0x53
372#define RADIO_2064_REG054 0x54
373#define RADIO_2064_REG055 0x55
374#define RADIO_2064_REG056 0x56
375#define RADIO_2064_REG057 0x57
376#define RADIO_2064_REG058 0x58
377#define RADIO_2064_REG059 0x59
378#define RADIO_2064_REG05A 0x5a
379#define RADIO_2064_REG05B 0x5b
380#define RADIO_2064_REG05C 0x5c
381#define RADIO_2064_REG05D 0x5d
382#define RADIO_2064_REG05E 0x5e
383#define RADIO_2064_REG05F 0x5f
384#define RADIO_2064_REG060 0x60
385#define RADIO_2064_REG061 0x61
386#define RADIO_2064_REG062 0x62
387#define RADIO_2064_REG063 0x63
388#define RADIO_2064_REG064 0x64
389#define RADIO_2064_REG065 0x65
390#define RADIO_2064_REG066 0x66
391#define RADIO_2064_REG067 0x67
392#define RADIO_2064_REG068 0x68
393#define RADIO_2064_REG069 0x69
394#define RADIO_2064_REG06A 0x6a
395#define RADIO_2064_REG06B 0x6b
396#define RADIO_2064_REG06C 0x6c
397#define RADIO_2064_REG06D 0x6d
398#define RADIO_2064_REG06E 0x6e
399#define RADIO_2064_REG06F 0x6f
400#define RADIO_2064_REG070 0x70
401#define RADIO_2064_REG071 0x71
402#define RADIO_2064_REG072 0x72
403#define RADIO_2064_REG073 0x73
404#define RADIO_2064_REG074 0x74
405#define RADIO_2064_REG075 0x75
406#define RADIO_2064_REG076 0x76
407#define RADIO_2064_REG077 0x77
408#define RADIO_2064_REG078 0x78
409#define RADIO_2064_REG079 0x79
410#define RADIO_2064_REG07A 0x7a
411#define RADIO_2064_REG07B 0x7b
412#define RADIO_2064_REG07C 0x7c
413#define RADIO_2064_REG07D 0x7d
414#define RADIO_2064_REG07E 0x7e
415#define RADIO_2064_REG07F 0x7f
416#define RADIO_2064_REG080 0x80
417#define RADIO_2064_REG081 0x81
418#define RADIO_2064_REG082 0x82
419#define RADIO_2064_REG083 0x83
420#define RADIO_2064_REG084 0x84
421#define RADIO_2064_REG085 0x85
422#define RADIO_2064_REG086 0x86
423#define RADIO_2064_REG087 0x87
424#define RADIO_2064_REG088 0x88
425#define RADIO_2064_REG089 0x89
426#define RADIO_2064_REG08A 0x8a
427#define RADIO_2064_REG08B 0x8b
428#define RADIO_2064_REG08C 0x8c
429#define RADIO_2064_REG08D 0x8d
430#define RADIO_2064_REG08E 0x8e
431#define RADIO_2064_REG08F 0x8f
432#define RADIO_2064_REG090 0x90
433#define RADIO_2064_REG091 0x91
434#define RADIO_2064_REG092 0x92
435#define RADIO_2064_REG093 0x93
436#define RADIO_2064_REG094 0x94
437#define RADIO_2064_REG095 0x95
438#define RADIO_2064_REG096 0x96
439#define RADIO_2064_REG097 0x97
440#define RADIO_2064_REG098 0x98
441#define RADIO_2064_REG099 0x99
442#define RADIO_2064_REG09A 0x9a
443#define RADIO_2064_REG09B 0x9b
444#define RADIO_2064_REG09C 0x9c
445#define RADIO_2064_REG09D 0x9d
446#define RADIO_2064_REG09E 0x9e
447#define RADIO_2064_REG09F 0x9f
448#define RADIO_2064_REG0A0 0xa0
449#define RADIO_2064_REG0A1 0xa1
450#define RADIO_2064_REG0A2 0xa2
451#define RADIO_2064_REG0A3 0xa3
452#define RADIO_2064_REG0A4 0xa4
453#define RADIO_2064_REG0A5 0xa5
454#define RADIO_2064_REG0A6 0xa6
455#define RADIO_2064_REG0A7 0xa7
456#define RADIO_2064_REG0A8 0xa8
457#define RADIO_2064_REG0A9 0xa9
458#define RADIO_2064_REG0AA 0xaa
459#define RADIO_2064_REG0AB 0xab
460#define RADIO_2064_REG0AC 0xac
461#define RADIO_2064_REG0AD 0xad
462#define RADIO_2064_REG0AE 0xae
463#define RADIO_2064_REG0AF 0xaf
464#define RADIO_2064_REG0B0 0xb0
465#define RADIO_2064_REG0B1 0xb1
466#define RADIO_2064_REG0B2 0xb2
467#define RADIO_2064_REG0B3 0xb3
468#define RADIO_2064_REG0B4 0xb4
469#define RADIO_2064_REG0B5 0xb5
470#define RADIO_2064_REG0B6 0xb6
471#define RADIO_2064_REG0B7 0xb7
472#define RADIO_2064_REG0B8 0xb8
473#define RADIO_2064_REG0B9 0xb9
474#define RADIO_2064_REG0BA 0xba
475#define RADIO_2064_REG0BB 0xbb
476#define RADIO_2064_REG0BC 0xbc
477#define RADIO_2064_REG0BD 0xbd
478#define RADIO_2064_REG0BE 0xbe
479#define RADIO_2064_REG0BF 0xbf
480#define RADIO_2064_REG0C0 0xc0
481#define RADIO_2064_REG0C1 0xc1
482#define RADIO_2064_REG0C2 0xc2
483#define RADIO_2064_REG0C3 0xc3
484#define RADIO_2064_REG0C4 0xc4
485#define RADIO_2064_REG0C5 0xc5
486#define RADIO_2064_REG0C6 0xc6
487#define RADIO_2064_REG0C7 0xc7
488#define RADIO_2064_REG0C8 0xc8
489#define RADIO_2064_REG0C9 0xc9
490#define RADIO_2064_REG0CA 0xca
491#define RADIO_2064_REG0CB 0xcb
492#define RADIO_2064_REG0CC 0xcc
493#define RADIO_2064_REG0CD 0xcd
494#define RADIO_2064_REG0CE 0xce
495#define RADIO_2064_REG0CF 0xcf
496#define RADIO_2064_REG0D0 0xd0
497#define RADIO_2064_REG0D1 0xd1
498#define RADIO_2064_REG0D2 0xd2
499#define RADIO_2064_REG0D3 0xd3
500#define RADIO_2064_REG0D4 0xd4
501#define RADIO_2064_REG0D5 0xd5
502#define RADIO_2064_REG0D6 0xd6
503#define RADIO_2064_REG0D7 0xd7
504#define RADIO_2064_REG0D8 0xd8
505#define RADIO_2064_REG0D9 0xd9
506#define RADIO_2064_REG0DA 0xda
507#define RADIO_2064_REG0DB 0xdb
508#define RADIO_2064_REG0DC 0xdc
509#define RADIO_2064_REG0DD 0xdd
510#define RADIO_2064_REG0DE 0xde
511#define RADIO_2064_REG0DF 0xdf
512#define RADIO_2064_REG0E0 0xe0
513#define RADIO_2064_REG0E1 0xe1
514#define RADIO_2064_REG0E2 0xe2
515#define RADIO_2064_REG0E3 0xe3
516#define RADIO_2064_REG0E4 0xe4
517#define RADIO_2064_REG0E5 0xe5
518#define RADIO_2064_REG0E6 0xe6
519#define RADIO_2064_REG0E7 0xe7
520#define RADIO_2064_REG0E8 0xe8
521#define RADIO_2064_REG0E9 0xe9
522#define RADIO_2064_REG0EA 0xea
523#define RADIO_2064_REG0EB 0xeb
524#define RADIO_2064_REG0EC 0xec
525#define RADIO_2064_REG0ED 0xed
526#define RADIO_2064_REG0EE 0xee
527#define RADIO_2064_REG0EF 0xef
528#define RADIO_2064_REG0F0 0xf0
529#define RADIO_2064_REG0F1 0xf1
530#define RADIO_2064_REG0F2 0xf2
531#define RADIO_2064_REG0F3 0xf3
532#define RADIO_2064_REG0F4 0xf4
533#define RADIO_2064_REG0F5 0xf5
534#define RADIO_2064_REG0F6 0xf6
535#define RADIO_2064_REG0F7 0xf7
536#define RADIO_2064_REG0F8 0xf8
537#define RADIO_2064_REG0F9 0xf9
538#define RADIO_2064_REG0FA 0xfa
539#define RADIO_2064_REG0FB 0xfb
540#define RADIO_2064_REG0FC 0xfc
541#define RADIO_2064_REG0FD 0xfd
542#define RADIO_2064_REG0FE 0xfe
543#define RADIO_2064_REG0FF 0xff
544#define RADIO_2064_REG100 0x100
545#define RADIO_2064_REG101 0x101
546#define RADIO_2064_REG102 0x102
547#define RADIO_2064_REG103 0x103
548#define RADIO_2064_REG104 0x104
549#define RADIO_2064_REG105 0x105
550#define RADIO_2064_REG106 0x106
551#define RADIO_2064_REG107 0x107
552#define RADIO_2064_REG108 0x108
553#define RADIO_2064_REG109 0x109
554#define RADIO_2064_REG10A 0x10a
555#define RADIO_2064_REG10B 0x10b
556#define RADIO_2064_REG10C 0x10c
557#define RADIO_2064_REG10D 0x10d
558#define RADIO_2064_REG10E 0x10e
559#define RADIO_2064_REG10F 0x10f
560#define RADIO_2064_REG110 0x110
561#define RADIO_2064_REG111 0x111
562#define RADIO_2064_REG112 0x112
563#define RADIO_2064_REG113 0x113
564#define RADIO_2064_REG114 0x114
565#define RADIO_2064_REG115 0x115
566#define RADIO_2064_REG116 0x116
567#define RADIO_2064_REG117 0x117
568#define RADIO_2064_REG118 0x118
569#define RADIO_2064_REG119 0x119
570#define RADIO_2064_REG11A 0x11a
571#define RADIO_2064_REG11B 0x11b
572#define RADIO_2064_REG11C 0x11c
573#define RADIO_2064_REG11D 0x11d
574#define RADIO_2064_REG11E 0x11e
575#define RADIO_2064_REG11F 0x11f
576#define RADIO_2064_REG120 0x120
577#define RADIO_2064_REG121 0x121
578#define RADIO_2064_REG122 0x122
579#define RADIO_2064_REG123 0x123
580#define RADIO_2064_REG124 0x124
581#define RADIO_2064_REG125 0x125
582#define RADIO_2064_REG126 0x126
583#define RADIO_2064_REG127 0x127
584#define RADIO_2064_REG128 0x128
585#define RADIO_2064_REG129 0x129
586#define RADIO_2064_REG12A 0x12a
587#define RADIO_2064_REG12B 0x12b
588#define RADIO_2064_REG12C 0x12c
589#define RADIO_2064_REG12D 0x12d
590#define RADIO_2064_REG12E 0x12e
591#define RADIO_2064_REG12F 0x12f
592#define RADIO_2064_REG130 0x130
593
594#define RADIO_2056_SYN (0x0 << 12)
595#define RADIO_2056_TX0 (0x2 << 12)
596#define RADIO_2056_TX1 (0x3 << 12)
597#define RADIO_2056_RX0 (0x6 << 12)
598#define RADIO_2056_RX1 (0x7 << 12)
599#define RADIO_2056_ALLTX (0xe << 12)
600#define RADIO_2056_ALLRX (0xf << 12)
601
602#define RADIO_2056_SYN_RESERVED_ADDR0 0x0
603#define RADIO_2056_SYN_IDCODE 0x1
604#define RADIO_2056_SYN_RESERVED_ADDR2 0x2
605#define RADIO_2056_SYN_RESERVED_ADDR3 0x3
606#define RADIO_2056_SYN_RESERVED_ADDR4 0x4
607#define RADIO_2056_SYN_RESERVED_ADDR5 0x5
608#define RADIO_2056_SYN_RESERVED_ADDR6 0x6
609#define RADIO_2056_SYN_RESERVED_ADDR7 0x7
610#define RADIO_2056_SYN_COM_CTRL 0x8
611#define RADIO_2056_SYN_COM_PU 0x9
612#define RADIO_2056_SYN_COM_OVR 0xa
613#define RADIO_2056_SYN_COM_RESET 0xb
614#define RADIO_2056_SYN_COM_RCAL 0xc
615#define RADIO_2056_SYN_COM_RC_RXLPF 0xd
616#define RADIO_2056_SYN_COM_RC_TXLPF 0xe
617#define RADIO_2056_SYN_COM_RC_RXHPF 0xf
618#define RADIO_2056_SYN_RESERVED_ADDR16 0x10
619#define RADIO_2056_SYN_RESERVED_ADDR17 0x11
620#define RADIO_2056_SYN_RESERVED_ADDR18 0x12
621#define RADIO_2056_SYN_RESERVED_ADDR19 0x13
622#define RADIO_2056_SYN_RESERVED_ADDR20 0x14
623#define RADIO_2056_SYN_RESERVED_ADDR21 0x15
624#define RADIO_2056_SYN_RESERVED_ADDR22 0x16
625#define RADIO_2056_SYN_RESERVED_ADDR23 0x17
626#define RADIO_2056_SYN_RESERVED_ADDR24 0x18
627#define RADIO_2056_SYN_RESERVED_ADDR25 0x19
628#define RADIO_2056_SYN_RESERVED_ADDR26 0x1a
629#define RADIO_2056_SYN_RESERVED_ADDR27 0x1b
630#define RADIO_2056_SYN_RESERVED_ADDR28 0x1c
631#define RADIO_2056_SYN_RESERVED_ADDR29 0x1d
632#define RADIO_2056_SYN_RESERVED_ADDR30 0x1e
633#define RADIO_2056_SYN_RESERVED_ADDR31 0x1f
634#define RADIO_2056_SYN_GPIO_MASTER1 0x20
635#define RADIO_2056_SYN_GPIO_MASTER2 0x21
636#define RADIO_2056_SYN_TOPBIAS_MASTER 0x22
637#define RADIO_2056_SYN_TOPBIAS_RCAL 0x23
638#define RADIO_2056_SYN_AFEREG 0x24
639#define RADIO_2056_SYN_TEMPPROCSENSE 0x25
640#define RADIO_2056_SYN_TEMPPROCSENSEIDAC 0x26
641#define RADIO_2056_SYN_TEMPPROCSENSERCAL 0x27
642#define RADIO_2056_SYN_LPO 0x28
643#define RADIO_2056_SYN_VDDCAL_MASTER 0x29
644#define RADIO_2056_SYN_VDDCAL_IDAC 0x2a
645#define RADIO_2056_SYN_VDDCAL_STATUS 0x2b
646#define RADIO_2056_SYN_RCAL_MASTER 0x2c
647#define RADIO_2056_SYN_RCAL_CODE_OUT 0x2d
648#define RADIO_2056_SYN_RCCAL_CTRL0 0x2e
649#define RADIO_2056_SYN_RCCAL_CTRL1 0x2f
650#define RADIO_2056_SYN_RCCAL_CTRL2 0x30
651#define RADIO_2056_SYN_RCCAL_CTRL3 0x31
652#define RADIO_2056_SYN_RCCAL_CTRL4 0x32
653#define RADIO_2056_SYN_RCCAL_CTRL5 0x33
654#define RADIO_2056_SYN_RCCAL_CTRL6 0x34
655#define RADIO_2056_SYN_RCCAL_CTRL7 0x35
656#define RADIO_2056_SYN_RCCAL_CTRL8 0x36
657#define RADIO_2056_SYN_RCCAL_CTRL9 0x37
658#define RADIO_2056_SYN_RCCAL_CTRL10 0x38
659#define RADIO_2056_SYN_RCCAL_CTRL11 0x39
660#define RADIO_2056_SYN_ZCAL_SPARE1 0x3a
661#define RADIO_2056_SYN_ZCAL_SPARE2 0x3b
662#define RADIO_2056_SYN_PLL_MAST1 0x3c
663#define RADIO_2056_SYN_PLL_MAST2 0x3d
664#define RADIO_2056_SYN_PLL_MAST3 0x3e
665#define RADIO_2056_SYN_PLL_BIAS_RESET 0x3f
666#define RADIO_2056_SYN_PLL_XTAL0 0x40
667#define RADIO_2056_SYN_PLL_XTAL1 0x41
668#define RADIO_2056_SYN_PLL_XTAL3 0x42
669#define RADIO_2056_SYN_PLL_XTAL4 0x43
670#define RADIO_2056_SYN_PLL_XTAL5 0x44
671#define RADIO_2056_SYN_PLL_XTAL6 0x45
672#define RADIO_2056_SYN_PLL_REFDIV 0x46
673#define RADIO_2056_SYN_PLL_PFD 0x47
674#define RADIO_2056_SYN_PLL_CP1 0x48
675#define RADIO_2056_SYN_PLL_CP2 0x49
676#define RADIO_2056_SYN_PLL_CP3 0x4a
677#define RADIO_2056_SYN_PLL_LOOPFILTER1 0x4b
678#define RADIO_2056_SYN_PLL_LOOPFILTER2 0x4c
679#define RADIO_2056_SYN_PLL_LOOPFILTER3 0x4d
680#define RADIO_2056_SYN_PLL_LOOPFILTER4 0x4e
681#define RADIO_2056_SYN_PLL_LOOPFILTER5 0x4f
682#define RADIO_2056_SYN_PLL_MMD1 0x50
683#define RADIO_2056_SYN_PLL_MMD2 0x51
684#define RADIO_2056_SYN_PLL_VCO1 0x52
685#define RADIO_2056_SYN_PLL_VCO2 0x53
686#define RADIO_2056_SYN_PLL_MONITOR1 0x54
687#define RADIO_2056_SYN_PLL_MONITOR2 0x55
688#define RADIO_2056_SYN_PLL_VCOCAL1 0x56
689#define RADIO_2056_SYN_PLL_VCOCAL2 0x57
690#define RADIO_2056_SYN_PLL_VCOCAL4 0x58
691#define RADIO_2056_SYN_PLL_VCOCAL5 0x59
692#define RADIO_2056_SYN_PLL_VCOCAL6 0x5a
693#define RADIO_2056_SYN_PLL_VCOCAL7 0x5b
694#define RADIO_2056_SYN_PLL_VCOCAL8 0x5c
695#define RADIO_2056_SYN_PLL_VCOCAL9 0x5d
696#define RADIO_2056_SYN_PLL_VCOCAL10 0x5e
697#define RADIO_2056_SYN_PLL_VCOCAL11 0x5f
698#define RADIO_2056_SYN_PLL_VCOCAL12 0x60
699#define RADIO_2056_SYN_PLL_VCOCAL13 0x61
700#define RADIO_2056_SYN_PLL_VREG 0x62
701#define RADIO_2056_SYN_PLL_STATUS1 0x63
702#define RADIO_2056_SYN_PLL_STATUS2 0x64
703#define RADIO_2056_SYN_PLL_STATUS3 0x65
704#define RADIO_2056_SYN_LOGEN_PU0 0x66
705#define RADIO_2056_SYN_LOGEN_PU1 0x67
706#define RADIO_2056_SYN_LOGEN_PU2 0x68
707#define RADIO_2056_SYN_LOGEN_PU3 0x69
708#define RADIO_2056_SYN_LOGEN_PU5 0x6a
709#define RADIO_2056_SYN_LOGEN_PU6 0x6b
710#define RADIO_2056_SYN_LOGEN_PU7 0x6c
711#define RADIO_2056_SYN_LOGEN_PU8 0x6d
712#define RADIO_2056_SYN_LOGEN_BIAS_RESET 0x6e
713#define RADIO_2056_SYN_LOGEN_RCCR1 0x6f
714#define RADIO_2056_SYN_LOGEN_VCOBUF1 0x70
715#define RADIO_2056_SYN_LOGEN_MIXER1 0x71
716#define RADIO_2056_SYN_LOGEN_MIXER2 0x72
717#define RADIO_2056_SYN_LOGEN_BUF1 0x73
718#define RADIO_2056_SYN_LOGENBUF2 0x74
719#define RADIO_2056_SYN_LOGEN_BUF3 0x75
720#define RADIO_2056_SYN_LOGEN_BUF4 0x76
721#define RADIO_2056_SYN_LOGEN_DIV1 0x77
722#define RADIO_2056_SYN_LOGEN_DIV2 0x78
723#define RADIO_2056_SYN_LOGEN_DIV3 0x79
724#define RADIO_2056_SYN_LOGEN_ACL1 0x7a
725#define RADIO_2056_SYN_LOGEN_ACL2 0x7b
726#define RADIO_2056_SYN_LOGEN_ACL3 0x7c
727#define RADIO_2056_SYN_LOGEN_ACL4 0x7d
728#define RADIO_2056_SYN_LOGEN_ACL5 0x7e
729#define RADIO_2056_SYN_LOGEN_ACL6 0x7f
730#define RADIO_2056_SYN_LOGEN_ACLOUT 0x80
731#define RADIO_2056_SYN_LOGEN_ACLCAL1 0x81
732#define RADIO_2056_SYN_LOGEN_ACLCAL2 0x82
733#define RADIO_2056_SYN_LOGEN_ACLCAL3 0x83
734#define RADIO_2056_SYN_CALEN 0x84
735#define RADIO_2056_SYN_LOGEN_PEAKDET1 0x85
736#define RADIO_2056_SYN_LOGEN_CORE_ACL_OVR 0x86
737#define RADIO_2056_SYN_LOGEN_RX_DIFF_ACL_OVR 0x87
738#define RADIO_2056_SYN_LOGEN_TX_DIFF_ACL_OVR 0x88
739#define RADIO_2056_SYN_LOGEN_RX_CMOS_ACL_OVR 0x89
740#define RADIO_2056_SYN_LOGEN_TX_CMOS_ACL_OVR 0x8a
741#define RADIO_2056_SYN_LOGEN_VCOBUF2 0x8b
742#define RADIO_2056_SYN_LOGEN_MIXER3 0x8c
743#define RADIO_2056_SYN_LOGEN_BUF5 0x8d
744#define RADIO_2056_SYN_LOGEN_BUF6 0x8e
745#define RADIO_2056_SYN_LOGEN_CBUFRX1 0x8f
746#define RADIO_2056_SYN_LOGEN_CBUFRX2 0x90
747#define RADIO_2056_SYN_LOGEN_CBUFRX3 0x91
748#define RADIO_2056_SYN_LOGEN_CBUFRX4 0x92
749#define RADIO_2056_SYN_LOGEN_CBUFTX1 0x93
750#define RADIO_2056_SYN_LOGEN_CBUFTX2 0x94
751#define RADIO_2056_SYN_LOGEN_CBUFTX3 0x95
752#define RADIO_2056_SYN_LOGEN_CBUFTX4 0x96
753#define RADIO_2056_SYN_LOGEN_CMOSRX1 0x97
754#define RADIO_2056_SYN_LOGEN_CMOSRX2 0x98
755#define RADIO_2056_SYN_LOGEN_CMOSRX3 0x99
756#define RADIO_2056_SYN_LOGEN_CMOSRX4 0x9a
757#define RADIO_2056_SYN_LOGEN_CMOSTX1 0x9b
758#define RADIO_2056_SYN_LOGEN_CMOSTX2 0x9c
759#define RADIO_2056_SYN_LOGEN_CMOSTX3 0x9d
760#define RADIO_2056_SYN_LOGEN_CMOSTX4 0x9e
761#define RADIO_2056_SYN_LOGEN_VCOBUF2_OVRVAL 0x9f
762#define RADIO_2056_SYN_LOGEN_MIXER3_OVRVAL 0xa0
763#define RADIO_2056_SYN_LOGEN_BUF5_OVRVAL 0xa1
764#define RADIO_2056_SYN_LOGEN_BUF6_OVRVAL 0xa2
765#define RADIO_2056_SYN_LOGEN_CBUFRX1_OVRVAL 0xa3
766#define RADIO_2056_SYN_LOGEN_CBUFRX2_OVRVAL 0xa4
767#define RADIO_2056_SYN_LOGEN_CBUFRX3_OVRVAL 0xa5
768#define RADIO_2056_SYN_LOGEN_CBUFRX4_OVRVAL 0xa6
769#define RADIO_2056_SYN_LOGEN_CBUFTX1_OVRVAL 0xa7
770#define RADIO_2056_SYN_LOGEN_CBUFTX2_OVRVAL 0xa8
771#define RADIO_2056_SYN_LOGEN_CBUFTX3_OVRVAL 0xa9
772#define RADIO_2056_SYN_LOGEN_CBUFTX4_OVRVAL 0xaa
773#define RADIO_2056_SYN_LOGEN_CMOSRX1_OVRVAL 0xab
774#define RADIO_2056_SYN_LOGEN_CMOSRX2_OVRVAL 0xac
775#define RADIO_2056_SYN_LOGEN_CMOSRX3_OVRVAL 0xad
776#define RADIO_2056_SYN_LOGEN_CMOSRX4_OVRVAL 0xae
777#define RADIO_2056_SYN_LOGEN_CMOSTX1_OVRVAL 0xaf
778#define RADIO_2056_SYN_LOGEN_CMOSTX2_OVRVAL 0xb0
779#define RADIO_2056_SYN_LOGEN_CMOSTX3_OVRVAL 0xb1
780#define RADIO_2056_SYN_LOGEN_CMOSTX4_OVRVAL 0xb2
781#define RADIO_2056_SYN_LOGEN_ACL_WAITCNT 0xb3
782#define RADIO_2056_SYN_LOGEN_CORE_CALVALID 0xb4
783#define RADIO_2056_SYN_LOGEN_RX_CMOS_CALVALID 0xb5
784#define RADIO_2056_SYN_LOGEN_TX_CMOS_VALID 0xb6
785
786#define RADIO_2056_TX_RESERVED_ADDR0 0x0
787#define RADIO_2056_TX_IDCODE 0x1
788#define RADIO_2056_TX_RESERVED_ADDR2 0x2
789#define RADIO_2056_TX_RESERVED_ADDR3 0x3
790#define RADIO_2056_TX_RESERVED_ADDR4 0x4
791#define RADIO_2056_TX_RESERVED_ADDR5 0x5
792#define RADIO_2056_TX_RESERVED_ADDR6 0x6
793#define RADIO_2056_TX_RESERVED_ADDR7 0x7
794#define RADIO_2056_TX_COM_CTRL 0x8
795#define RADIO_2056_TX_COM_PU 0x9
796#define RADIO_2056_TX_COM_OVR 0xa
797#define RADIO_2056_TX_COM_RESET 0xb
798#define RADIO_2056_TX_COM_RCAL 0xc
799#define RADIO_2056_TX_COM_RC_RXLPF 0xd
800#define RADIO_2056_TX_COM_RC_TXLPF 0xe
801#define RADIO_2056_TX_COM_RC_RXHPF 0xf
802#define RADIO_2056_TX_RESERVED_ADDR16 0x10
803#define RADIO_2056_TX_RESERVED_ADDR17 0x11
804#define RADIO_2056_TX_RESERVED_ADDR18 0x12
805#define RADIO_2056_TX_RESERVED_ADDR19 0x13
806#define RADIO_2056_TX_RESERVED_ADDR20 0x14
807#define RADIO_2056_TX_RESERVED_ADDR21 0x15
808#define RADIO_2056_TX_RESERVED_ADDR22 0x16
809#define RADIO_2056_TX_RESERVED_ADDR23 0x17
810#define RADIO_2056_TX_RESERVED_ADDR24 0x18
811#define RADIO_2056_TX_RESERVED_ADDR25 0x19
812#define RADIO_2056_TX_RESERVED_ADDR26 0x1a
813#define RADIO_2056_TX_RESERVED_ADDR27 0x1b
814#define RADIO_2056_TX_RESERVED_ADDR28 0x1c
815#define RADIO_2056_TX_RESERVED_ADDR29 0x1d
816#define RADIO_2056_TX_RESERVED_ADDR30 0x1e
817#define RADIO_2056_TX_RESERVED_ADDR31 0x1f
818#define RADIO_2056_TX_IQCAL_GAIN_BW 0x20
819#define RADIO_2056_TX_LOFT_FINE_I 0x21
820#define RADIO_2056_TX_LOFT_FINE_Q 0x22
821#define RADIO_2056_TX_LOFT_COARSE_I 0x23
822#define RADIO_2056_TX_LOFT_COARSE_Q 0x24
823#define RADIO_2056_TX_TX_COM_MASTER1 0x25
824#define RADIO_2056_TX_TX_COM_MASTER2 0x26
825#define RADIO_2056_TX_RXIQCAL_TXMUX 0x27
826#define RADIO_2056_TX_TX_SSI_MASTER 0x28
827#define RADIO_2056_TX_IQCAL_VCM_HG 0x29
828#define RADIO_2056_TX_IQCAL_IDAC 0x2a
829#define RADIO_2056_TX_TSSI_VCM 0x2b
830#define RADIO_2056_TX_TX_AMP_DET 0x2c
831#define RADIO_2056_TX_TX_SSI_MUX 0x2d
832#define RADIO_2056_TX_TSSIA 0x2e
833#define RADIO_2056_TX_TSSIG 0x2f
834#define RADIO_2056_TX_TSSI_MISC1 0x30
835#define RADIO_2056_TX_TSSI_MISC2 0x31
836#define RADIO_2056_TX_TSSI_MISC3 0x32
837#define RADIO_2056_TX_PA_SPARE1 0x33
838#define RADIO_2056_TX_PA_SPARE2 0x34
839#define RADIO_2056_TX_INTPAA_MASTER 0x35
840#define RADIO_2056_TX_INTPAA_GAIN 0x36
841#define RADIO_2056_TX_INTPAA_BOOST_TUNE 0x37
842#define RADIO_2056_TX_INTPAA_IAUX_STAT 0x38
843#define RADIO_2056_TX_INTPAA_IAUX_DYN 0x39
844#define RADIO_2056_TX_INTPAA_IMAIN_STAT 0x3a
845#define RADIO_2056_TX_INTPAA_IMAIN_DYN 0x3b
846#define RADIO_2056_TX_INTPAA_CASCBIAS 0x3c
847#define RADIO_2056_TX_INTPAA_PASLOPE 0x3d
848#define RADIO_2056_TX_INTPAA_PA_MISC 0x3e
849#define RADIO_2056_TX_INTPAG_MASTER 0x3f
850#define RADIO_2056_TX_INTPAG_GAIN 0x40
851#define RADIO_2056_TX_INTPAG_BOOST_TUNE 0x41
852#define RADIO_2056_TX_INTPAG_IAUX_STAT 0x42
853#define RADIO_2056_TX_INTPAG_IAUX_DYN 0x43
854#define RADIO_2056_TX_INTPAG_IMAIN_STAT 0x44
855#define RADIO_2056_TX_INTPAG_IMAIN_DYN 0x45
856#define RADIO_2056_TX_INTPAG_CASCBIAS 0x46
857#define RADIO_2056_TX_INTPAG_PASLOPE 0x47
858#define RADIO_2056_TX_INTPAG_PA_MISC 0x48
859#define RADIO_2056_TX_PADA_MASTER 0x49
860#define RADIO_2056_TX_PADA_IDAC 0x4a
861#define RADIO_2056_TX_PADA_CASCBIAS 0x4b
862#define RADIO_2056_TX_PADA_GAIN 0x4c
863#define RADIO_2056_TX_PADA_BOOST_TUNE 0x4d
864#define RADIO_2056_TX_PADA_SLOPE 0x4e
865#define RADIO_2056_TX_PADG_MASTER 0x4f
866#define RADIO_2056_TX_PADG_IDAC 0x50
867#define RADIO_2056_TX_PADG_CASCBIAS 0x51
868#define RADIO_2056_TX_PADG_GAIN 0x52
869#define RADIO_2056_TX_PADG_BOOST_TUNE 0x53
870#define RADIO_2056_TX_PADG_SLOPE 0x54
871#define RADIO_2056_TX_PGAA_MASTER 0x55
872#define RADIO_2056_TX_PGAA_IDAC 0x56
873#define RADIO_2056_TX_PGAA_GAIN 0x57
874#define RADIO_2056_TX_PGAA_BOOST_TUNE 0x58
875#define RADIO_2056_TX_PGAA_SLOPE 0x59
876#define RADIO_2056_TX_PGAA_MISC 0x5a
877#define RADIO_2056_TX_PGAG_MASTER 0x5b
878#define RADIO_2056_TX_PGAG_IDAC 0x5c
879#define RADIO_2056_TX_PGAG_GAIN 0x5d
880#define RADIO_2056_TX_PGAG_BOOST_TUNE 0x5e
881#define RADIO_2056_TX_PGAG_SLOPE 0x5f
882#define RADIO_2056_TX_PGAG_MISC 0x60
883#define RADIO_2056_TX_MIXA_MASTER 0x61
884#define RADIO_2056_TX_MIXA_BOOST_TUNE 0x62
885#define RADIO_2056_TX_MIXG 0x63
886#define RADIO_2056_TX_MIXG_BOOST_TUNE 0x64
887#define RADIO_2056_TX_BB_GM_MASTER 0x65
888#define RADIO_2056_TX_GMBB_GM 0x66
889#define RADIO_2056_TX_GMBB_IDAC 0x67
890#define RADIO_2056_TX_TXLPF_MASTER 0x68
891#define RADIO_2056_TX_TXLPF_RCCAL 0x69
892#define RADIO_2056_TX_TXLPF_RCCAL_OFF0 0x6a
893#define RADIO_2056_TX_TXLPF_RCCAL_OFF1 0x6b
894#define RADIO_2056_TX_TXLPF_RCCAL_OFF2 0x6c
895#define RADIO_2056_TX_TXLPF_RCCAL_OFF3 0x6d
896#define RADIO_2056_TX_TXLPF_RCCAL_OFF4 0x6e
897#define RADIO_2056_TX_TXLPF_RCCAL_OFF5 0x6f
898#define RADIO_2056_TX_TXLPF_RCCAL_OFF6 0x70
899#define RADIO_2056_TX_TXLPF_BW 0x71
900#define RADIO_2056_TX_TXLPF_GAIN 0x72
901#define RADIO_2056_TX_TXLPF_IDAC 0x73
902#define RADIO_2056_TX_TXLPF_IDAC_0 0x74
903#define RADIO_2056_TX_TXLPF_IDAC_1 0x75
904#define RADIO_2056_TX_TXLPF_IDAC_2 0x76
905#define RADIO_2056_TX_TXLPF_IDAC_3 0x77
906#define RADIO_2056_TX_TXLPF_IDAC_4 0x78
907#define RADIO_2056_TX_TXLPF_IDAC_5 0x79
908#define RADIO_2056_TX_TXLPF_IDAC_6 0x7a
909#define RADIO_2056_TX_TXLPF_OPAMP_IDAC 0x7b
910#define RADIO_2056_TX_TXLPF_MISC 0x7c
911#define RADIO_2056_TX_TXSPARE1 0x7d
912#define RADIO_2056_TX_TXSPARE2 0x7e
913#define RADIO_2056_TX_TXSPARE3 0x7f
914#define RADIO_2056_TX_TXSPARE4 0x80
915#define RADIO_2056_TX_TXSPARE5 0x81
916#define RADIO_2056_TX_TXSPARE6 0x82
917#define RADIO_2056_TX_TXSPARE7 0x83
918#define RADIO_2056_TX_TXSPARE8 0x84
919#define RADIO_2056_TX_TXSPARE9 0x85
920#define RADIO_2056_TX_TXSPARE10 0x86
921#define RADIO_2056_TX_TXSPARE11 0x87
922#define RADIO_2056_TX_TXSPARE12 0x88
923#define RADIO_2056_TX_TXSPARE13 0x89
924#define RADIO_2056_TX_TXSPARE14 0x8a
925#define RADIO_2056_TX_TXSPARE15 0x8b
926#define RADIO_2056_TX_TXSPARE16 0x8c
927#define RADIO_2056_TX_STATUS_INTPA_GAIN 0x8d
928#define RADIO_2056_TX_STATUS_PAD_GAIN 0x8e
929#define RADIO_2056_TX_STATUS_PGA_GAIN 0x8f
930#define RADIO_2056_TX_STATUS_GM_TXLPF_GAIN 0x90
931#define RADIO_2056_TX_STATUS_TXLPF_BW 0x91
932#define RADIO_2056_TX_STATUS_TXLPF_RC 0x92
933#define RADIO_2056_TX_GMBB_IDAC0 0x93
934#define RADIO_2056_TX_GMBB_IDAC1 0x94
935#define RADIO_2056_TX_GMBB_IDAC2 0x95
936#define RADIO_2056_TX_GMBB_IDAC3 0x96
937#define RADIO_2056_TX_GMBB_IDAC4 0x97
938#define RADIO_2056_TX_GMBB_IDAC5 0x98
939#define RADIO_2056_TX_GMBB_IDAC6 0x99
940#define RADIO_2056_TX_GMBB_IDAC7 0x9a
941
942#define RADIO_2056_RX_RESERVED_ADDR0 0x0
943#define RADIO_2056_RX_IDCODE 0x1
944#define RADIO_2056_RX_RESERVED_ADDR2 0x2
945#define RADIO_2056_RX_RESERVED_ADDR3 0x3
946#define RADIO_2056_RX_RESERVED_ADDR4 0x4
947#define RADIO_2056_RX_RESERVED_ADDR5 0x5
948#define RADIO_2056_RX_RESERVED_ADDR6 0x6
949#define RADIO_2056_RX_RESERVED_ADDR7 0x7
950#define RADIO_2056_RX_COM_CTRL 0x8
951#define RADIO_2056_RX_COM_PU 0x9
952#define RADIO_2056_RX_COM_OVR 0xa
953#define RADIO_2056_RX_COM_RESET 0xb
954#define RADIO_2056_RX_COM_RCAL 0xc
955#define RADIO_2056_RX_COM_RC_RXLPF 0xd
956#define RADIO_2056_RX_COM_RC_TXLPF 0xe
957#define RADIO_2056_RX_COM_RC_RXHPF 0xf
958#define RADIO_2056_RX_RESERVED_ADDR16 0x10
959#define RADIO_2056_RX_RESERVED_ADDR17 0x11
960#define RADIO_2056_RX_RESERVED_ADDR18 0x12
961#define RADIO_2056_RX_RESERVED_ADDR19 0x13
962#define RADIO_2056_RX_RESERVED_ADDR20 0x14
963#define RADIO_2056_RX_RESERVED_ADDR21 0x15
964#define RADIO_2056_RX_RESERVED_ADDR22 0x16
965#define RADIO_2056_RX_RESERVED_ADDR23 0x17
966#define RADIO_2056_RX_RESERVED_ADDR24 0x18
967#define RADIO_2056_RX_RESERVED_ADDR25 0x19
968#define RADIO_2056_RX_RESERVED_ADDR26 0x1a
969#define RADIO_2056_RX_RESERVED_ADDR27 0x1b
970#define RADIO_2056_RX_RESERVED_ADDR28 0x1c
971#define RADIO_2056_RX_RESERVED_ADDR29 0x1d
972#define RADIO_2056_RX_RESERVED_ADDR30 0x1e
973#define RADIO_2056_RX_RESERVED_ADDR31 0x1f
974#define RADIO_2056_RX_RXIQCAL_RXMUX 0x20
975#define RADIO_2056_RX_RSSI_PU 0x21
976#define RADIO_2056_RX_RSSI_SEL 0x22
977#define RADIO_2056_RX_RSSI_GAIN 0x23
978#define RADIO_2056_RX_RSSI_NB_IDAC 0x24
979#define RADIO_2056_RX_RSSI_WB2I_IDAC_1 0x25
980#define RADIO_2056_RX_RSSI_WB2I_IDAC_2 0x26
981#define RADIO_2056_RX_RSSI_WB2Q_IDAC_1 0x27
982#define RADIO_2056_RX_RSSI_WB2Q_IDAC_2 0x28
983#define RADIO_2056_RX_RSSI_POLE 0x29
984#define RADIO_2056_RX_RSSI_WB1_IDAC 0x2a
985#define RADIO_2056_RX_RSSI_MISC 0x2b
986#define RADIO_2056_RX_LNAA_MASTER 0x2c
987#define RADIO_2056_RX_LNAA_TUNE 0x2d
988#define RADIO_2056_RX_LNAA_GAIN 0x2e
989#define RADIO_2056_RX_LNA_A_SLOPE 0x2f
990#define RADIO_2056_RX_BIASPOLE_LNAA1_IDAC 0x30
991#define RADIO_2056_RX_LNAA2_IDAC 0x31
992#define RADIO_2056_RX_LNA1A_MISC 0x32
993#define RADIO_2056_RX_LNAG_MASTER 0x33
994#define RADIO_2056_RX_LNAG_TUNE 0x34
995#define RADIO_2056_RX_LNAG_GAIN 0x35
996#define RADIO_2056_RX_LNA_G_SLOPE 0x36
997#define RADIO_2056_RX_BIASPOLE_LNAG1_IDAC 0x37
998#define RADIO_2056_RX_LNAG2_IDAC 0x38
999#define RADIO_2056_RX_LNA1G_MISC 0x39
1000#define RADIO_2056_RX_MIXA_MASTER 0x3a
1001#define RADIO_2056_RX_MIXA_VCM 0x3b
1002#define RADIO_2056_RX_MIXA_CTRLPTAT 0x3c
1003#define RADIO_2056_RX_MIXA_LOB_BIAS 0x3d
1004#define RADIO_2056_RX_MIXA_CORE_IDAC 0x3e
1005#define RADIO_2056_RX_MIXA_CMFB_IDAC 0x3f
1006#define RADIO_2056_RX_MIXA_BIAS_AUX 0x40
1007#define RADIO_2056_RX_MIXA_BIAS_MAIN 0x41
1008#define RADIO_2056_RX_MIXA_BIAS_MISC 0x42
1009#define RADIO_2056_RX_MIXA_MAST_BIAS 0x43
1010#define RADIO_2056_RX_MIXG_MASTER 0x44
1011#define RADIO_2056_RX_MIXG_VCM 0x45
1012#define RADIO_2056_RX_MIXG_CTRLPTAT 0x46
1013#define RADIO_2056_RX_MIXG_LOB_BIAS 0x47
1014#define RADIO_2056_RX_MIXG_CORE_IDAC 0x48
1015#define RADIO_2056_RX_MIXG_CMFB_IDAC 0x49
1016#define RADIO_2056_RX_MIXG_BIAS_AUX 0x4a
1017#define RADIO_2056_RX_MIXG_BIAS_MAIN 0x4b
1018#define RADIO_2056_RX_MIXG_BIAS_MISC 0x4c
1019#define RADIO_2056_RX_MIXG_MAST_BIAS 0x4d
1020#define RADIO_2056_RX_TIA_MASTER 0x4e
1021#define RADIO_2056_RX_TIA_IOPAMP 0x4f
1022#define RADIO_2056_RX_TIA_QOPAMP 0x50
1023#define RADIO_2056_RX_TIA_IMISC 0x51
1024#define RADIO_2056_RX_TIA_QMISC 0x52
1025#define RADIO_2056_RX_TIA_GAIN 0x53
1026#define RADIO_2056_RX_TIA_SPARE1 0x54
1027#define RADIO_2056_RX_TIA_SPARE2 0x55
1028#define RADIO_2056_RX_BB_LPF_MASTER 0x56
1029#define RADIO_2056_RX_AACI_MASTER 0x57
1030#define RADIO_2056_RX_RXLPF_IDAC 0x58
1031#define RADIO_2056_RX_RXLPF_OPAMPBIAS_LOWQ 0x59
1032#define RADIO_2056_RX_RXLPF_OPAMPBIAS_HIGHQ 0x5a
1033#define RADIO_2056_RX_RXLPF_BIAS_DCCANCEL 0x5b
1034#define RADIO_2056_RX_RXLPF_OUTVCM 0x5c
1035#define RADIO_2056_RX_RXLPF_INVCM_BODY 0x5d
1036#define RADIO_2056_RX_RXLPF_CC_OP 0x5e
1037#define RADIO_2056_RX_RXLPF_GAIN 0x5f
1038#define RADIO_2056_RX_RXLPF_Q_BW 0x60
1039#define RADIO_2056_RX_RXLPF_HP_CORNER_BW 0x61
1040#define RADIO_2056_RX_RXLPF_RCCAL_HPC 0x62
1041#define RADIO_2056_RX_RXHPF_OFF0 0x63
1042#define RADIO_2056_RX_RXHPF_OFF1 0x64
1043#define RADIO_2056_RX_RXHPF_OFF2 0x65
1044#define RADIO_2056_RX_RXHPF_OFF3 0x66
1045#define RADIO_2056_RX_RXHPF_OFF4 0x67
1046#define RADIO_2056_RX_RXHPF_OFF5 0x68
1047#define RADIO_2056_RX_RXHPF_OFF6 0x69
1048#define RADIO_2056_RX_RXHPF_OFF7 0x6a
1049#define RADIO_2056_RX_RXLPF_RCCAL_LPC 0x6b
1050#define RADIO_2056_RX_RXLPF_OFF_0 0x6c
1051#define RADIO_2056_RX_RXLPF_OFF_1 0x6d
1052#define RADIO_2056_RX_RXLPF_OFF_2 0x6e
1053#define RADIO_2056_RX_RXLPF_OFF_3 0x6f
1054#define RADIO_2056_RX_RXLPF_OFF_4 0x70
1055#define RADIO_2056_RX_UNUSED 0x71
1056#define RADIO_2056_RX_VGA_MASTER 0x72
1057#define RADIO_2056_RX_VGA_BIAS 0x73
1058#define RADIO_2056_RX_VGA_BIAS_DCCANCEL 0x74
1059#define RADIO_2056_RX_VGA_GAIN 0x75
1060#define RADIO_2056_RX_VGA_HP_CORNER_BW 0x76
1061#define RADIO_2056_RX_VGABUF_BIAS 0x77
1062#define RADIO_2056_RX_VGABUF_GAIN_BW 0x78
1063#define RADIO_2056_RX_TXFBMIX_A 0x79
1064#define RADIO_2056_RX_TXFBMIX_G 0x7a
1065#define RADIO_2056_RX_RXSPARE1 0x7b
1066#define RADIO_2056_RX_RXSPARE2 0x7c
1067#define RADIO_2056_RX_RXSPARE3 0x7d
1068#define RADIO_2056_RX_RXSPARE4 0x7e
1069#define RADIO_2056_RX_RXSPARE5 0x7f
1070#define RADIO_2056_RX_RXSPARE6 0x80
1071#define RADIO_2056_RX_RXSPARE7 0x81
1072#define RADIO_2056_RX_RXSPARE8 0x82
1073#define RADIO_2056_RX_RXSPARE9 0x83
1074#define RADIO_2056_RX_RXSPARE10 0x84
1075#define RADIO_2056_RX_RXSPARE11 0x85
1076#define RADIO_2056_RX_RXSPARE12 0x86
1077#define RADIO_2056_RX_RXSPARE13 0x87
1078#define RADIO_2056_RX_RXSPARE14 0x88
1079#define RADIO_2056_RX_RXSPARE15 0x89
1080#define RADIO_2056_RX_RXSPARE16 0x8a
1081#define RADIO_2056_RX_STATUS_LNAA_GAIN 0x8b
1082#define RADIO_2056_RX_STATUS_LNAG_GAIN 0x8c
1083#define RADIO_2056_RX_STATUS_MIXTIA_GAIN 0x8d
1084#define RADIO_2056_RX_STATUS_RXLPF_GAIN 0x8e
1085#define RADIO_2056_RX_STATUS_VGA_BUF_GAIN 0x8f
1086#define RADIO_2056_RX_STATUS_RXLPF_Q 0x90
1087#define RADIO_2056_RX_STATUS_RXLPF_BUF_BW 0x91
1088#define RADIO_2056_RX_STATUS_RXLPF_VGA_HPC 0x92
1089#define RADIO_2056_RX_STATUS_RXLPF_RC 0x93
1090#define RADIO_2056_RX_STATUS_HPC_RC 0x94
1091
1092#define RADIO_2056_LNA1_A_PU 0x01
1093#define RADIO_2056_LNA2_A_PU 0x02
1094#define RADIO_2056_LNA1_G_PU 0x01
1095#define RADIO_2056_LNA2_G_PU 0x02
1096#define RADIO_2056_MIXA_PU_I 0x01
1097#define RADIO_2056_MIXA_PU_Q 0x02
1098#define RADIO_2056_MIXA_PU_GM 0x10
1099#define RADIO_2056_MIXG_PU_I 0x01
1100#define RADIO_2056_MIXG_PU_Q 0x02
1101#define RADIO_2056_MIXG_PU_GM 0x10
1102#define RADIO_2056_TIA_PU 0x01
1103#define RADIO_2056_BB_LPF_PU 0x20
1104#define RADIO_2056_W1_PU 0x02
1105#define RADIO_2056_W2_PU 0x04
1106#define RADIO_2056_NB_PU 0x08
1107#define RADIO_2056_RSSI_W1_SEL 0x02
1108#define RADIO_2056_RSSI_W2_SEL 0x04
1109#define RADIO_2056_RSSI_NB_SEL 0x08
1110#define RADIO_2056_VCM_MASK 0x1c
1111#define RADIO_2056_RSSI_VCM_SHIFT 0x02
1112
1113#define RADIO_2057_DACBUF_VINCM_CORE0 0x0
1114#define RADIO_2057_IDCODE 0x1
1115#define RADIO_2057_RCCAL_MASTER 0x2
1116#define RADIO_2057_RCCAL_CAP_SIZE 0x3
1117#define RADIO_2057_RCAL_CONFIG 0x4
1118#define RADIO_2057_GPAIO_CONFIG 0x5
1119#define RADIO_2057_GPAIO_SEL1 0x6
1120#define RADIO_2057_GPAIO_SEL0 0x7
1121#define RADIO_2057_CLPO_CONFIG 0x8
1122#define RADIO_2057_BANDGAP_CONFIG 0x9
1123#define RADIO_2057_BANDGAP_RCAL_TRIM 0xa
1124#define RADIO_2057_AFEREG_CONFIG 0xb
1125#define RADIO_2057_TEMPSENSE_CONFIG 0xc
1126#define RADIO_2057_XTAL_CONFIG1 0xd
1127#define RADIO_2057_XTAL_ICORE_SIZE 0xe
1128#define RADIO_2057_XTAL_BUF_SIZE 0xf
1129#define RADIO_2057_XTAL_PULLCAP_SIZE 0x10
1130#define RADIO_2057_RFPLL_MASTER 0x11
1131#define RADIO_2057_VCOMONITOR_VTH_L 0x12
1132#define RADIO_2057_VCOMONITOR_VTH_H 0x13
1133#define RADIO_2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x14
1134#define RADIO_2057_VCO_VARCSIZE_IDAC 0x15
1135#define RADIO_2057_VCOCAL_COUNTVAL0 0x16
1136#define RADIO_2057_VCOCAL_COUNTVAL1 0x17
1137#define RADIO_2057_VCOCAL_INTCLK_COUNT 0x18
1138#define RADIO_2057_VCOCAL_MASTER 0x19
1139#define RADIO_2057_VCOCAL_NUMCAPCHANGE 0x1a
1140#define RADIO_2057_VCOCAL_WINSIZE 0x1b
1141#define RADIO_2057_VCOCAL_DELAY_AFTER_REFRESH 0x1c
1142#define RADIO_2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x1d
1143#define RADIO_2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x1e
1144#define RADIO_2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x1f
1145#define RADIO_2057_VCO_FORCECAPEN_FORCECAP1 0x20
1146#define RADIO_2057_VCO_FORCECAP0 0x21
1147#define RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x22
1148#define RADIO_2057_RFPLL_PFD_RESET_PW 0x23
1149#define RADIO_2057_RFPLL_LOOPFILTER_R2 0x24
1150#define RADIO_2057_RFPLL_LOOPFILTER_R1 0x25
1151#define RADIO_2057_RFPLL_LOOPFILTER_C3 0x26
1152#define RADIO_2057_RFPLL_LOOPFILTER_C2 0x27
1153#define RADIO_2057_RFPLL_LOOPFILTER_C1 0x28
1154#define RADIO_2057_CP_KPD_IDAC 0x29
1155#define RADIO_2057_RFPLL_IDACS 0x2a
1156#define RADIO_2057_RFPLL_MISC_EN 0x2b
1157#define RADIO_2057_RFPLL_MMD0 0x2c
1158#define RADIO_2057_RFPLL_MMD1 0x2d
1159#define RADIO_2057_RFPLL_MISC_CAL_RESETN 0x2e
1160#define RADIO_2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x2f
1161#define RADIO_2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x30
1162#define RADIO_2057_VCOCAL_READCAP0 0x31
1163#define RADIO_2057_VCOCAL_READCAP1 0x32
1164#define RADIO_2057_VCOCAL_STATUS 0x33
1165#define RADIO_2057_LOGEN_PUS 0x34
1166#define RADIO_2057_LOGEN_PTAT_RESETS 0x35
1167#define RADIO_2057_VCOBUF_IDACS 0x36
1168#define RADIO_2057_VCOBUF_TUNE 0x37
1169#define RADIO_2057_CMOSBUF_TX2GQ_IDACS 0x38
1170#define RADIO_2057_CMOSBUF_TX2GI_IDACS 0x39
1171#define RADIO_2057_CMOSBUF_TX5GQ_IDACS 0x3a
1172#define RADIO_2057_CMOSBUF_TX5GI_IDACS 0x3b
1173#define RADIO_2057_CMOSBUF_RX2GQ_IDACS 0x3c
1174#define RADIO_2057_CMOSBUF_RX2GI_IDACS 0x3d
1175#define RADIO_2057_CMOSBUF_RX5GQ_IDACS 0x3e
1176#define RADIO_2057_CMOSBUF_RX5GI_IDACS 0x3f
1177#define RADIO_2057_LOGEN_MX2G_IDACS 0x40
1178#define RADIO_2057_LOGEN_MX2G_TUNE 0x41
1179#define RADIO_2057_LOGEN_MX5G_IDACS 0x42
1180#define RADIO_2057_LOGEN_MX5G_TUNE 0x43
1181#define RADIO_2057_LOGEN_MX5G_RCCR 0x44
1182#define RADIO_2057_LOGEN_INDBUF2G_IDAC 0x45
1183#define RADIO_2057_LOGEN_INDBUF2G_IBOOST 0x46
1184#define RADIO_2057_LOGEN_INDBUF2G_TUNE 0x47
1185#define RADIO_2057_LOGEN_INDBUF5G_IDAC 0x48
1186#define RADIO_2057_LOGEN_INDBUF5G_IBOOST 0x49
1187#define RADIO_2057_LOGEN_INDBUF5G_TUNE 0x4a
1188#define RADIO_2057_CMOSBUF_TX_RCCR 0x4b
1189#define RADIO_2057_CMOSBUF_RX_RCCR 0x4c
1190#define RADIO_2057_LOGEN_SEL_PKDET 0x4d
1191#define RADIO_2057_CMOSBUF_SHAREIQ_PTAT 0x4e
1192#define RADIO_2057_RXTXBIAS_CONFIG_CORE0 0x4f
1193#define RADIO_2057_TXGM_TXRF_PUS_CORE0 0x50
1194#define RADIO_2057_TXGM_IDAC_BLEED_CORE0 0x51
1195#define RADIO_2057_TXGM_GAIN_CORE0 0x56
1196#define RADIO_2057_TXGM2G_PKDET_PUS_CORE0 0x57
1197#define RADIO_2057_PAD2G_PTATS_CORE0 0x58
1198#define RADIO_2057_PAD2G_IDACS_CORE0 0x59
1199#define RADIO_2057_PAD2G_BOOST_PU_CORE0 0x5a
1200#define RADIO_2057_PAD2G_CASCV_GAIN_CORE0 0x5b
1201#define RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x5c
1202#define RADIO_2057_TXMIX2G_LODC_CORE0 0x5d
1203#define RADIO_2057_PAD2G_TUNE_PUS_CORE0 0x5e
1204#define RADIO_2057_IPA2G_GAIN_CORE0 0x5f
1205#define RADIO_2057_TSSI2G_SPARE1_CORE0 0x60
1206#define RADIO_2057_TSSI2G_SPARE2_CORE0 0x61
1207#define RADIO_2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x62
1208#define RADIO_2057_IPA2G_IMAIN_CORE0 0x63
1209#define RADIO_2057_IPA2G_CASCONV_CORE0 0x64
1210#define RADIO_2057_IPA2G_CASCOFFV_CORE0 0x65
1211#define RADIO_2057_IPA2G_BIAS_FILTER_CORE0 0x66
1212#define RADIO_2057_TX5G_PKDET_CORE0 0x69
1213#define RADIO_2057_PGA_PTAT_TXGM5G_PU_CORE0 0x6a
1214#define RADIO_2057_PAD5G_PTATS1_CORE0 0x6b
1215#define RADIO_2057_PAD5G_CLASS_PTATS2_CORE0 0x6c
1216#define RADIO_2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x6d
1217#define RADIO_2057_PAD5G_CASCV_IMAIN_CORE0 0x6e
1218#define RADIO_2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x6f
1219#define RADIO_2057_PGA_BOOST_TUNE_CORE0 0x70
1220#define RADIO_2057_PGA_GAIN_CORE0 0x71
1221#define RADIO_2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x72
1222#define RADIO_2057_TXMIX5G_BOOST_TUNE_CORE0 0x73
1223#define RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE0 0x74
1224#define RADIO_2057_IPA5G_IAUX_CORE0 0x75
1225#define RADIO_2057_IPA5G_GAIN_CORE0 0x76
1226#define RADIO_2057_TSSI5G_SPARE1_CORE0 0x77
1227#define RADIO_2057_TSSI5G_SPARE2_CORE0 0x78
1228#define RADIO_2057_IPA5G_CASCOFFV_PU_CORE0 0x79
1229#define RADIO_2057_IPA5G_PTAT_CORE0 0x7a
1230#define RADIO_2057_IPA5G_IMAIN_CORE0 0x7b
1231#define RADIO_2057_IPA5G_CASCONV_CORE0 0x7c
1232#define RADIO_2057_IPA5G_BIAS_FILTER_CORE0 0x7d
1233#define RADIO_2057_PAD_BIAS_FILTER_BWS_CORE0 0x80
1234#define RADIO_2057_TR2G_CONFIG1_CORE0_NU 0x81
1235#define RADIO_2057_TR2G_CONFIG2_CORE0_NU 0x82
1236#define RADIO_2057_LNA5G_RFEN_CORE0 0x83
1237#define RADIO_2057_TR5G_CONFIG2_CORE0_NU 0x84
1238#define RADIO_2057_RXRFBIAS_IBOOST_PU_CORE0 0x85
1239#define RADIO_2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x86
1240#define RADIO_2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x87
1241#define RADIO_2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x88
1242#define RADIO_2057_RXMIX_CMFBITAIL_PU_CORE0 0x89
1243#define RADIO_2057_LNA2_IMAIN_PTAT_PU_CORE0 0x8a
1244#define RADIO_2057_LNA2_IAUX_PTAT_CORE0 0x8b
1245#define RADIO_2057_LNA1_IMAIN_PTAT_PU_CORE0 0x8c
1246#define RADIO_2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x8d
1247#define RADIO_2057_RXRFBIAS_BANDSEL_CORE0 0x8e
1248#define RADIO_2057_TIA_CONFIG_CORE0 0x8f
1249#define RADIO_2057_TIA_IQGAIN_CORE0 0x90
1250#define RADIO_2057_TIA_IBIAS2_CORE0 0x91
1251#define RADIO_2057_TIA_IBIAS1_CORE0 0x92
1252#define RADIO_2057_TIA_SPARE_Q_CORE0 0x93
1253#define RADIO_2057_TIA_SPARE_I_CORE0 0x94
1254#define RADIO_2057_RXMIX2G_PUS_CORE0 0x95
1255#define RADIO_2057_RXMIX2G_VCMREFS_CORE0 0x96
1256#define RADIO_2057_RXMIX2G_LODC_QI_CORE0 0x97
1257#define RADIO_2057_W12G_BW_LNA2G_PUS_CORE0 0x98
1258#define RADIO_2057_LNA2G_GAIN_CORE0 0x99
1259#define RADIO_2057_LNA2G_TUNE_CORE0 0x9a
1260#define RADIO_2057_RXMIX5G_PUS_CORE0 0x9b
1261#define RADIO_2057_RXMIX5G_VCMREFS_CORE0 0x9c
1262#define RADIO_2057_RXMIX5G_LODC_QI_CORE0 0x9d
1263#define RADIO_2057_W15G_BW_LNA5G_PUS_CORE0 0x9e
1264#define RADIO_2057_LNA5G_GAIN_CORE0 0x9f
1265#define RADIO_2057_LNA5G_TUNE_CORE0 0xa0
1266#define RADIO_2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0xa1
1267#define RADIO_2057_RXBB_BIAS_MASTER_CORE0 0xa2
1268#define RADIO_2057_RXBB_VGABUF_IDACS_CORE0 0xa3
1269#define RADIO_2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0xa4
1270#define RADIO_2057_TXBUF_VINCM_CORE0 0xa5
1271#define RADIO_2057_TXBUF_IDACS_CORE0 0xa6
1272#define RADIO_2057_LPF_RESP_RXBUF_BW_CORE0 0xa7
1273#define RADIO_2057_RXBB_CC_CORE0 0xa8
1274#define RADIO_2057_RXBB_SPARE3_CORE0 0xa9
1275#define RADIO_2057_RXBB_RCCAL_HPC_CORE0 0xaa
1276#define RADIO_2057_LPF_IDACS_CORE0 0xab
1277#define RADIO_2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0xac
1278#define RADIO_2057_TXBUF_GAIN_CORE0 0xad
1279#define RADIO_2057_AFELOOPBACK_AACI_RESP_CORE0 0xae
1280#define RADIO_2057_RXBUF_DEGEN_CORE0 0xaf
1281#define RADIO_2057_RXBB_SPARE2_CORE0 0xb0
1282#define RADIO_2057_RXBB_SPARE1_CORE0 0xb1
1283#define RADIO_2057_RSSI_MASTER_CORE0 0xb2
1284#define RADIO_2057_W2_MASTER_CORE0 0xb3
1285#define RADIO_2057_NB_MASTER_CORE0 0xb4
1286#define RADIO_2057_W2_IDACS0_Q_CORE0 0xb5
1287#define RADIO_2057_W2_IDACS1_Q_CORE0 0xb6
1288#define RADIO_2057_W2_IDACS0_I_CORE0 0xb7
1289#define RADIO_2057_W2_IDACS1_I_CORE0 0xb8
1290#define RADIO_2057_RSSI_GPAIOSEL_W1_IDACS_CORE0 0xb9
1291#define RADIO_2057_NB_IDACS_Q_CORE0 0xba
1292#define RADIO_2057_NB_IDACS_I_CORE0 0xbb
1293#define RADIO_2057_BACKUP4_CORE0 0xc1
1294#define RADIO_2057_BACKUP3_CORE0 0xc2
1295#define RADIO_2057_BACKUP2_CORE0 0xc3
1296#define RADIO_2057_BACKUP1_CORE0 0xc4
1297#define RADIO_2057_SPARE16_CORE0 0xc5
1298#define RADIO_2057_SPARE15_CORE0 0xc6
1299#define RADIO_2057_SPARE14_CORE0 0xc7
1300#define RADIO_2057_SPARE13_CORE0 0xc8
1301#define RADIO_2057_SPARE12_CORE0 0xc9
1302#define RADIO_2057_SPARE11_CORE0 0xca
1303#define RADIO_2057_TX2G_BIAS_RESETS_CORE0 0xcb
1304#define RADIO_2057_TX5G_BIAS_RESETS_CORE0 0xcc
1305#define RADIO_2057_IQTEST_SEL_PU 0xcd
1306#define RADIO_2057_XTAL_CONFIG2 0xce
1307#define RADIO_2057_BUFS_MISC_LPFBW_CORE0 0xcf
1308#define RADIO_2057_TXLPF_RCCAL_CORE0 0xd0
1309#define RADIO_2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0xd1
1310#define RADIO_2057_LPF_GAIN_CORE0 0xd2
1311#define RADIO_2057_DACBUF_IDACS_BW_CORE0 0xd3
1312#define RADIO_2057_RXTXBIAS_CONFIG_CORE1 0xd4
1313#define RADIO_2057_TXGM_TXRF_PUS_CORE1 0xd5
1314#define RADIO_2057_TXGM_IDAC_BLEED_CORE1 0xd6
1315#define RADIO_2057_TXGM_GAIN_CORE1 0xdb
1316#define RADIO_2057_TXGM2G_PKDET_PUS_CORE1 0xdc
1317#define RADIO_2057_PAD2G_PTATS_CORE1 0xdd
1318#define RADIO_2057_PAD2G_IDACS_CORE1 0xde
1319#define RADIO_2057_PAD2G_BOOST_PU_CORE1 0xdf
1320#define RADIO_2057_PAD2G_CASCV_GAIN_CORE1 0xe0
1321#define RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0xe1
1322#define RADIO_2057_TXMIX2G_LODC_CORE1 0xe2
1323#define RADIO_2057_PAD2G_TUNE_PUS_CORE1 0xe3
1324#define RADIO_2057_IPA2G_GAIN_CORE1 0xe4
1325#define RADIO_2057_TSSI2G_SPARE1_CORE1 0xe5
1326#define RADIO_2057_TSSI2G_SPARE2_CORE1 0xe6
1327#define RADIO_2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0xe7
1328#define RADIO_2057_IPA2G_IMAIN_CORE1 0xe8
1329#define RADIO_2057_IPA2G_CASCONV_CORE1 0xe9
1330#define RADIO_2057_IPA2G_CASCOFFV_CORE1 0xea
1331#define RADIO_2057_IPA2G_BIAS_FILTER_CORE1 0xeb
1332#define RADIO_2057_TX5G_PKDET_CORE1 0xee
1333#define RADIO_2057_PGA_PTAT_TXGM5G_PU_CORE1 0xef
1334#define RADIO_2057_PAD5G_PTATS1_CORE1 0xf0
1335#define RADIO_2057_PAD5G_CLASS_PTATS2_CORE1 0xf1
1336#define RADIO_2057_PGA_BOOSTPTAT_IMAIN_CORE1 0xf2
1337#define RADIO_2057_PAD5G_CASCV_IMAIN_CORE1 0xf3
1338#define RADIO_2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0xf4
1339#define RADIO_2057_PGA_BOOST_TUNE_CORE1 0xf5
1340#define RADIO_2057_PGA_GAIN_CORE1 0xf6
1341#define RADIO_2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0xf7
1342#define RADIO_2057_TXMIX5G_BOOST_TUNE_CORE1 0xf8
1343#define RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE1 0xf9
1344#define RADIO_2057_IPA5G_IAUX_CORE1 0xfa
1345#define RADIO_2057_IPA5G_GAIN_CORE1 0xfb
1346#define RADIO_2057_TSSI5G_SPARE1_CORE1 0xfc
1347#define RADIO_2057_TSSI5G_SPARE2_CORE1 0xfd
1348#define RADIO_2057_IPA5G_CASCOFFV_PU_CORE1 0xfe
1349#define RADIO_2057_IPA5G_PTAT_CORE1 0xff
1350#define RADIO_2057_IPA5G_IMAIN_CORE1 0x100
1351#define RADIO_2057_IPA5G_CASCONV_CORE1 0x101
1352#define RADIO_2057_IPA5G_BIAS_FILTER_CORE1 0x102
1353#define RADIO_2057_PAD_BIAS_FILTER_BWS_CORE1 0x105
1354#define RADIO_2057_TR2G_CONFIG1_CORE1_NU 0x106
1355#define RADIO_2057_TR2G_CONFIG2_CORE1_NU 0x107
1356#define RADIO_2057_LNA5G_RFEN_CORE1 0x108
1357#define RADIO_2057_TR5G_CONFIG2_CORE1_NU 0x109
1358#define RADIO_2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a
1359#define RADIO_2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b
1360#define RADIO_2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c
1361#define RADIO_2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d
1362#define RADIO_2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e
1363#define RADIO_2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f
1364#define RADIO_2057_LNA2_IAUX_PTAT_CORE1 0x110
1365#define RADIO_2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111
1366#define RADIO_2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112
1367#define RADIO_2057_RXRFBIAS_BANDSEL_CORE1 0x113
1368#define RADIO_2057_TIA_CONFIG_CORE1 0x114
1369#define RADIO_2057_TIA_IQGAIN_CORE1 0x115
1370#define RADIO_2057_TIA_IBIAS2_CORE1 0x116
1371#define RADIO_2057_TIA_IBIAS1_CORE1 0x117
1372#define RADIO_2057_TIA_SPARE_Q_CORE1 0x118
1373#define RADIO_2057_TIA_SPARE_I_CORE1 0x119
1374#define RADIO_2057_RXMIX2G_PUS_CORE1 0x11a
1375#define RADIO_2057_RXMIX2G_VCMREFS_CORE1 0x11b
1376#define RADIO_2057_RXMIX2G_LODC_QI_CORE1 0x11c
1377#define RADIO_2057_W12G_BW_LNA2G_PUS_CORE1 0x11d
1378#define RADIO_2057_LNA2G_GAIN_CORE1 0x11e
1379#define RADIO_2057_LNA2G_TUNE_CORE1 0x11f
1380#define RADIO_2057_RXMIX5G_PUS_CORE1 0x120
1381#define RADIO_2057_RXMIX5G_VCMREFS_CORE1 0x121
1382#define RADIO_2057_RXMIX5G_LODC_QI_CORE1 0x122
1383#define RADIO_2057_W15G_BW_LNA5G_PUS_CORE1 0x123
1384#define RADIO_2057_LNA5G_GAIN_CORE1 0x124
1385#define RADIO_2057_LNA5G_TUNE_CORE1 0x125
1386#define RADIO_2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126
1387#define RADIO_2057_RXBB_BIAS_MASTER_CORE1 0x127
1388#define RADIO_2057_RXBB_VGABUF_IDACS_CORE1 0x128
1389#define RADIO_2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129
1390#define RADIO_2057_TXBUF_VINCM_CORE1 0x12a
1391#define RADIO_2057_TXBUF_IDACS_CORE1 0x12b
1392#define RADIO_2057_LPF_RESP_RXBUF_BW_CORE1 0x12c
1393#define RADIO_2057_RXBB_CC_CORE1 0x12d
1394#define RADIO_2057_RXBB_SPARE3_CORE1 0x12e
1395#define RADIO_2057_RXBB_RCCAL_HPC_CORE1 0x12f
1396#define RADIO_2057_LPF_IDACS_CORE1 0x130
1397#define RADIO_2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131
1398#define RADIO_2057_TXBUF_GAIN_CORE1 0x132
1399#define RADIO_2057_AFELOOPBACK_AACI_RESP_CORE1 0x133
1400#define RADIO_2057_RXBUF_DEGEN_CORE1 0x134
1401#define RADIO_2057_RXBB_SPARE2_CORE1 0x135
1402#define RADIO_2057_RXBB_SPARE1_CORE1 0x136
1403#define RADIO_2057_RSSI_MASTER_CORE1 0x137
1404#define RADIO_2057_W2_MASTER_CORE1 0x138
1405#define RADIO_2057_NB_MASTER_CORE1 0x139
1406#define RADIO_2057_W2_IDACS0_Q_CORE1 0x13a
1407#define RADIO_2057_W2_IDACS1_Q_CORE1 0x13b
1408#define RADIO_2057_W2_IDACS0_I_CORE1 0x13c
1409#define RADIO_2057_W2_IDACS1_I_CORE1 0x13d
1410#define RADIO_2057_RSSI_GPAIOSEL_W1_IDACS_CORE1 0x13e
1411#define RADIO_2057_NB_IDACS_Q_CORE1 0x13f
1412#define RADIO_2057_NB_IDACS_I_CORE1 0x140
1413#define RADIO_2057_BACKUP4_CORE1 0x146
1414#define RADIO_2057_BACKUP3_CORE1 0x147
1415#define RADIO_2057_BACKUP2_CORE1 0x148
1416#define RADIO_2057_BACKUP1_CORE1 0x149
1417#define RADIO_2057_SPARE16_CORE1 0x14a
1418#define RADIO_2057_SPARE15_CORE1 0x14b
1419#define RADIO_2057_SPARE14_CORE1 0x14c
1420#define RADIO_2057_SPARE13_CORE1 0x14d
1421#define RADIO_2057_SPARE12_CORE1 0x14e
1422#define RADIO_2057_SPARE11_CORE1 0x14f
1423#define RADIO_2057_TX2G_BIAS_RESETS_CORE1 0x150
1424#define RADIO_2057_TX5G_BIAS_RESETS_CORE1 0x151
1425#define RADIO_2057_SPARE8_CORE1 0x152
1426#define RADIO_2057_SPARE7_CORE1 0x153
1427#define RADIO_2057_BUFS_MISC_LPFBW_CORE1 0x154
1428#define RADIO_2057_TXLPF_RCCAL_CORE1 0x155
1429#define RADIO_2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156
1430#define RADIO_2057_LPF_GAIN_CORE1 0x157
1431#define RADIO_2057_DACBUF_IDACS_BW_CORE1 0x158
1432#define RADIO_2057_DACBUF_VINCM_CORE1 0x159
1433#define RADIO_2057_RCCAL_START_R1_Q1_P1 0x15a
1434#define RADIO_2057_RCCAL_X1 0x15b
1435#define RADIO_2057_RCCAL_TRC0 0x15c
1436#define RADIO_2057_RCCAL_TRC1 0x15d
1437#define RADIO_2057_RCCAL_DONE_OSCCAP 0x15e
1438#define RADIO_2057_RCCAL_N0_0 0x15f
1439#define RADIO_2057_RCCAL_N0_1 0x160
1440#define RADIO_2057_RCCAL_N1_0 0x161
1441#define RADIO_2057_RCCAL_N1_1 0x162
1442#define RADIO_2057_RCAL_STATUS 0x163
1443#define RADIO_2057_XTALPUOVR_PINCTRL 0x164
1444#define RADIO_2057_OVR_REG0 0x165
1445#define RADIO_2057_OVR_REG1 0x166
1446#define RADIO_2057_OVR_REG2 0x167
1447#define RADIO_2057_OVR_REG3 0x168
1448#define RADIO_2057_OVR_REG4 0x169
1449#define RADIO_2057_RCCAL_SCAP_VAL 0x16a
1450#define RADIO_2057_RCCAL_BCAP_VAL 0x16b
1451#define RADIO_2057_RCCAL_HPC_VAL 0x16c
1452#define RADIO_2057_RCCAL_OVERRIDES 0x16d
1453#define RADIO_2057_TX0_IQCAL_GAIN_BW 0x170
1454#define RADIO_2057_TX0_LOFT_FINE_I 0x171
1455#define RADIO_2057_TX0_LOFT_FINE_Q 0x172
1456#define RADIO_2057_TX0_LOFT_COARSE_I 0x173
1457#define RADIO_2057_TX0_LOFT_COARSE_Q 0x174
1458#define RADIO_2057_TX0_TX_SSI_MASTER 0x175
1459#define RADIO_2057_TX0_IQCAL_VCM_HG 0x176
1460#define RADIO_2057_TX0_IQCAL_IDAC 0x177
1461#define RADIO_2057_TX0_TSSI_VCM 0x178
1462#define RADIO_2057_TX0_TX_SSI_MUX 0x179
1463#define RADIO_2057_TX0_TSSIA 0x17a
1464#define RADIO_2057_TX0_TSSIG 0x17b
1465#define RADIO_2057_TX0_TSSI_MISC1 0x17c
1466#define RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d
1467#define RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e
1468#define RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f
1469#define RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180
1470#define RADIO_2057_TX1_IQCAL_GAIN_BW 0x190
1471#define RADIO_2057_TX1_LOFT_FINE_I 0x191
1472#define RADIO_2057_TX1_LOFT_FINE_Q 0x192
1473#define RADIO_2057_TX1_LOFT_COARSE_I 0x193
1474#define RADIO_2057_TX1_LOFT_COARSE_Q 0x194
1475#define RADIO_2057_TX1_TX_SSI_MASTER 0x195
1476#define RADIO_2057_TX1_IQCAL_VCM_HG 0x196
1477#define RADIO_2057_TX1_IQCAL_IDAC 0x197
1478#define RADIO_2057_TX1_TSSI_VCM 0x198
1479#define RADIO_2057_TX1_TX_SSI_MUX 0x199
1480#define RADIO_2057_TX1_TSSIA 0x19a
1481#define RADIO_2057_TX1_TSSIG 0x19b
1482#define RADIO_2057_TX1_TSSI_MISC1 0x19c
1483#define RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d
1484#define RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e
1485#define RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f
1486#define RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0
1487#define RADIO_2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1
1488#define RADIO_2057_AFE_SET_VCM_I_CORE0 0x1a2
1489#define RADIO_2057_AFE_SET_VCM_Q_CORE0 0x1a3
1490#define RADIO_2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4
1491#define RADIO_2057_AFE_STATUS_VCM_I_CORE0 0x1a5
1492#define RADIO_2057_AFE_STATUS_VCM_Q_CORE0 0x1a6
1493#define RADIO_2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7
1494#define RADIO_2057_AFE_SET_VCM_I_CORE1 0x1a8
1495#define RADIO_2057_AFE_SET_VCM_Q_CORE1 0x1a9
1496#define RADIO_2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa
1497#define RADIO_2057_AFE_STATUS_VCM_I_CORE1 0x1ab
1498#define RADIO_2057_AFE_STATUS_VCM_Q_CORE1 0x1ac
1499
1500#define RADIO_2057v7_DACBUF_VINCM_CORE0 0x1ad
1501#define RADIO_2057v7_RCCAL_MASTER 0x1ae
1502#define RADIO_2057v7_TR2G_CONFIG3_CORE0_NU 0x1af
1503#define RADIO_2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0
1504#define RADIO_2057v7_LOGEN_PUS1 0x1b1
1505#define RADIO_2057v7_OVR_REG5 0x1b2
1506#define RADIO_2057v7_OVR_REG6 0x1b3
1507#define RADIO_2057v7_OVR_REG7 0x1b4
1508#define RADIO_2057v7_OVR_REG8 0x1b5
1509#define RADIO_2057v7_OVR_REG9 0x1b6
1510#define RADIO_2057v7_OVR_REG10 0x1b7
1511#define RADIO_2057v7_OVR_REG11 0x1b8
1512#define RADIO_2057v7_OVR_REG12 0x1b9
1513#define RADIO_2057v7_OVR_REG13 0x1ba
1514#define RADIO_2057v7_OVR_REG14 0x1bb
1515#define RADIO_2057v7_OVR_REG15 0x1bc
1516#define RADIO_2057v7_OVR_REG16 0x1bd
1517#define RADIO_2057v7_OVR_REG1 0x1be
1518#define RADIO_2057v7_OVR_REG18 0x1bf
1519#define RADIO_2057v7_OVR_REG19 0x1c0
1520#define RADIO_2057v7_OVR_REG20 0x1c1
1521#define RADIO_2057v7_OVR_REG21 0x1c2
1522#define RADIO_2057v7_OVR_REG2 0x1c3
1523#define RADIO_2057v7_OVR_REG23 0x1c4
1524#define RADIO_2057v7_OVR_REG24 0x1c5
1525#define RADIO_2057v7_OVR_REG25 0x1c6
1526#define RADIO_2057v7_OVR_REG26 0x1c7
1527#define RADIO_2057v7_OVR_REG27 0x1c8
1528#define RADIO_2057v7_OVR_REG28 0x1c9
1529#define RADIO_2057v7_IQTEST_SEL_PU2 0x1ca
1530
1531#define RADIO_2057_VCM_MASK 0x7
1532
1533#endif /* _BRCM_PHY_RADIO_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h b/drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h
deleted file mode 100644
index a97c3a79947..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define NPHY_TBL_ID_GAIN1 0
18#define NPHY_TBL_ID_GAIN2 1
19#define NPHY_TBL_ID_GAINBITS1 2
20#define NPHY_TBL_ID_GAINBITS2 3
21#define NPHY_TBL_ID_GAINLIMIT 4
22#define NPHY_TBL_ID_WRSSIGainLimit 5
23#define NPHY_TBL_ID_RFSEQ 7
24#define NPHY_TBL_ID_AFECTRL 8
25#define NPHY_TBL_ID_ANTSWCTRLLUT 9
26#define NPHY_TBL_ID_IQLOCAL 15
27#define NPHY_TBL_ID_NOISEVAR 16
28#define NPHY_TBL_ID_SAMPLEPLAY 17
29#define NPHY_TBL_ID_CORE1TXPWRCTL 26
30#define NPHY_TBL_ID_CORE2TXPWRCTL 27
31#define NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL 30
32
33#define NPHY_TBL_ID_EPSILONTBL0 31
34#define NPHY_TBL_ID_SCALARTBL0 32
35#define NPHY_TBL_ID_EPSILONTBL1 33
36#define NPHY_TBL_ID_SCALARTBL1 34
37
38#define NPHY_TO_BPHY_OFF 0xc00
39
40#define NPHY_BandControl_currentBand 0x0001
41#define RFCC_CHIP0_PU 0x0400
42#define RFCC_POR_FORCE 0x0040
43#define RFCC_OE_POR_FORCE 0x0080
44#define NPHY_RfctrlIntc_override_OFF 0
45#define NPHY_RfctrlIntc_override_TRSW 1
46#define NPHY_RfctrlIntc_override_PA 2
47#define NPHY_RfctrlIntc_override_EXT_LNA_PU 3
48#define NPHY_RfctrlIntc_override_EXT_LNA_GAIN 4
49#define RIFS_ENABLE 0x80
50#define BPHY_BAND_SEL_UP20 0x10
51#define NPHY_MLenable 0x02
52
53#define NPHY_RfseqMode_CoreActv_override 0x0001
54#define NPHY_RfseqMode_Trigger_override 0x0002
55#define NPHY_RfseqCoreActv_TxRxChain0 (0x11)
56#define NPHY_RfseqCoreActv_TxRxChain1 (0x22)
57
58#define NPHY_RfseqTrigger_rx2tx 0x0001
59#define NPHY_RfseqTrigger_tx2rx 0x0002
60#define NPHY_RfseqTrigger_updategainh 0x0004
61#define NPHY_RfseqTrigger_updategainl 0x0008
62#define NPHY_RfseqTrigger_updategainu 0x0010
63#define NPHY_RfseqTrigger_reset2rx 0x0020
64#define NPHY_RfseqStatus_rx2tx 0x0001
65#define NPHY_RfseqStatus_tx2rx 0x0002
66#define NPHY_RfseqStatus_updategainh 0x0004
67#define NPHY_RfseqStatus_updategainl 0x0008
68#define NPHY_RfseqStatus_updategainu 0x0010
69#define NPHY_RfseqStatus_reset2rx 0x0020
70#define NPHY_ClassifierCtrl_cck_en 0x1
71#define NPHY_ClassifierCtrl_ofdm_en 0x2
72#define NPHY_ClassifierCtrl_waited_en 0x4
73#define NPHY_IQFlip_ADC1 0x0001
74#define NPHY_IQFlip_ADC2 0x0010
75#define NPHY_sampleCmd_STOP 0x0002
76
77#define RX_GF_OR_MM 0x0004
78#define RX_GF_MM_AUTO 0x0100
79
80#define NPHY_iqloCalCmdGctl_IQLO_CAL_EN 0x8000
81
82#define NPHY_IqestCmd_iqstart 0x1
83#define NPHY_IqestCmd_iqMode 0x2
84
85#define NPHY_TxPwrCtrlCmd_pwrIndex_init 0x40
86#define NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 0x19
87
88#define PRIM_SEL_UP20 0x8000
89
90#define NPHY_RFSEQ_RX2TX 0x0
91#define NPHY_RFSEQ_TX2RX 0x1
92#define NPHY_RFSEQ_RESET2RX 0x2
93#define NPHY_RFSEQ_UPDATEGAINH 0x3
94#define NPHY_RFSEQ_UPDATEGAINL 0x4
95#define NPHY_RFSEQ_UPDATEGAINU 0x5
96
97#define NPHY_RFSEQ_CMD_NOP 0x0
98#define NPHY_RFSEQ_CMD_RXG_FBW 0x1
99#define NPHY_RFSEQ_CMD_TR_SWITCH 0x2
100#define NPHY_RFSEQ_CMD_EXT_PA 0x3
101#define NPHY_RFSEQ_CMD_RXPD_TXPD 0x4
102#define NPHY_RFSEQ_CMD_TX_GAIN 0x5
103#define NPHY_RFSEQ_CMD_RX_GAIN 0x6
104#define NPHY_RFSEQ_CMD_SET_HPF_BW 0x7
105#define NPHY_RFSEQ_CMD_CLR_HIQ_DIS 0x8
106#define NPHY_RFSEQ_CMD_END 0xf
107
108#define NPHY_REV3_RFSEQ_CMD_NOP 0x0
109#define NPHY_REV3_RFSEQ_CMD_RXG_FBW 0x1
110#define NPHY_REV3_RFSEQ_CMD_TR_SWITCH 0x2
111#define NPHY_REV3_RFSEQ_CMD_INT_PA_PU 0x3
112#define NPHY_REV3_RFSEQ_CMD_EXT_PA 0x4
113#define NPHY_REV3_RFSEQ_CMD_RXPD_TXPD 0x5
114#define NPHY_REV3_RFSEQ_CMD_TX_GAIN 0x6
115#define NPHY_REV3_RFSEQ_CMD_RX_GAIN 0x7
116#define NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS 0x8
117#define NPHY_REV3_RFSEQ_CMD_SET_HPF_H_HPC 0x9
118#define NPHY_REV3_RFSEQ_CMD_SET_LPF_H_HPC 0xa
119#define NPHY_REV3_RFSEQ_CMD_SET_HPF_M_HPC 0xb
120#define NPHY_REV3_RFSEQ_CMD_SET_LPF_M_HPC 0xc
121#define NPHY_REV3_RFSEQ_CMD_SET_HPF_L_HPC 0xd
122#define NPHY_REV3_RFSEQ_CMD_SET_LPF_L_HPC 0xe
123#define NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS 0xf
124#define NPHY_REV3_RFSEQ_CMD_END 0x1f
125
126#define NPHY_RSSI_SEL_W1 0x0
127#define NPHY_RSSI_SEL_W2 0x1
128#define NPHY_RSSI_SEL_NB 0x2
129#define NPHY_RSSI_SEL_IQ 0x3
130#define NPHY_RSSI_SEL_TSSI_2G 0x4
131#define NPHY_RSSI_SEL_TSSI_5G 0x5
132#define NPHY_RSSI_SEL_TBD 0x6
133
134#define NPHY_RAIL_I 0x0
135#define NPHY_RAIL_Q 0x1
136
137#define NPHY_FORCESIG_DECODEGATEDCLKS 0x8
138
139#define NPHY_REV7_RfctrlOverride_cmd_rxrf_pu 0x0
140#define NPHY_REV7_RfctrlOverride_cmd_rx_pu 0x1
141#define NPHY_REV7_RfctrlOverride_cmd_tx_pu 0x2
142#define NPHY_REV7_RfctrlOverride_cmd_rxgain 0x3
143#define NPHY_REV7_RfctrlOverride_cmd_txgain 0x4
144
145#define NPHY_REV7_RXGAINCODE_RFMXGAIN_MASK 0x000ff
146#define NPHY_REV7_RXGAINCODE_LPFGAIN_MASK 0x0ff00
147#define NPHY_REV7_RXGAINCODE_DVGAGAIN_MASK 0xf0000
148
149#define NPHY_REV7_TXGAINCODE_TGAIN_MASK 0x7fff
150#define NPHY_REV7_TXGAINCODE_LPFGAIN_MASK 0x8000
151#define NPHY_REV7_TXGAINCODE_BIQ0GAIN_SHIFT 14
152
153#define NPHY_REV7_RFCTRLOVERRIDE_ID0 0x0
154#define NPHY_REV7_RFCTRLOVERRIDE_ID1 0x1
155#define NPHY_REV7_RFCTRLOVERRIDE_ID2 0x2
156
157#define NPHY_IqestIqAccLo(core) ((core == 0) ? 0x12c : 0x134)
158
159#define NPHY_IqestIqAccHi(core) ((core == 0) ? 0x12d : 0x135)
160
161#define NPHY_IqestipwrAccLo(core) ((core == 0) ? 0x12e : 0x136)
162
163#define NPHY_IqestipwrAccHi(core) ((core == 0) ? 0x12f : 0x137)
164
165#define NPHY_IqestqpwrAccLo(core) ((core == 0) ? 0x130 : 0x138)
166
167#define NPHY_IqestqpwrAccHi(core) ((core == 0) ? 0x131 : 0x139)
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.c b/drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.c
deleted file mode 100644
index 622c01ca72c..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.c
+++ /dev/null
@@ -1,3250 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <types.h>
18#include "phytbl_lcn.h"
19
20static const u32 dot11lcn_gain_tbl_rev0[] = {
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x00000000,
28 0x00000000,
29 0x00000004,
30 0x00000000,
31 0x00000004,
32 0x00000008,
33 0x00000001,
34 0x00000005,
35 0x00000009,
36 0x0000000d,
37 0x0000004d,
38 0x0000008d,
39 0x0000000d,
40 0x0000004d,
41 0x0000008d,
42 0x000000cd,
43 0x0000004f,
44 0x0000008f,
45 0x000000cf,
46 0x000000d3,
47 0x00000113,
48 0x00000513,
49 0x00000913,
50 0x00000953,
51 0x00000d53,
52 0x00001153,
53 0x00001193,
54 0x00005193,
55 0x00009193,
56 0x0000d193,
57 0x00011193,
58 0x00000000,
59 0x00000000,
60 0x00000000,
61 0x00000000,
62 0x00000000,
63 0x00000000,
64 0x00000004,
65 0x00000000,
66 0x00000004,
67 0x00000008,
68 0x00000001,
69 0x00000005,
70 0x00000009,
71 0x0000000d,
72 0x0000004d,
73 0x0000008d,
74 0x0000000d,
75 0x0000004d,
76 0x0000008d,
77 0x000000cd,
78 0x0000004f,
79 0x0000008f,
80 0x000000cf,
81 0x000000d3,
82 0x00000113,
83 0x00000513,
84 0x00000913,
85 0x00000953,
86 0x00000d53,
87 0x00001153,
88 0x00005153,
89 0x00009153,
90 0x0000d153,
91 0x00011153,
92 0x00015153,
93 0x00019153,
94 0x0001d153,
95 0x00000000,
96 0x00000000,
97 0x00000000,
98 0x00000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0x00000000,
103 0x00000000,
104 0x00000000,
105 0x00000000,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x00000000,
115 0x00000000,
116 0x00000000,
117};
118
119static const u32 dot11lcn_gain_tbl_rev1[] = {
120 0x00000000,
121 0x00000000,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000008,
129 0x00000004,
130 0x00000008,
131 0x00000001,
132 0x00000005,
133 0x00000009,
134 0x0000000D,
135 0x00000011,
136 0x00000051,
137 0x00000091,
138 0x00000011,
139 0x00000051,
140 0x00000091,
141 0x000000d1,
142 0x00000053,
143 0x00000093,
144 0x000000d3,
145 0x000000d7,
146 0x00000117,
147 0x00000517,
148 0x00000917,
149 0x00000957,
150 0x00000d57,
151 0x00001157,
152 0x00001197,
153 0x00005197,
154 0x00009197,
155 0x0000d197,
156 0x00011197,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000008,
164 0x00000004,
165 0x00000008,
166 0x00000001,
167 0x00000005,
168 0x00000009,
169 0x0000000D,
170 0x00000011,
171 0x00000051,
172 0x00000091,
173 0x00000011,
174 0x00000051,
175 0x00000091,
176 0x000000d1,
177 0x00000053,
178 0x00000093,
179 0x000000d3,
180 0x000000d7,
181 0x00000117,
182 0x00000517,
183 0x00000917,
184 0x00000957,
185 0x00000d57,
186 0x00001157,
187 0x00005157,
188 0x00009157,
189 0x0000d157,
190 0x00011157,
191 0x00015157,
192 0x00019157,
193 0x0001d157,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204 0x00000000,
205 0x00000000,
206 0x00000000,
207 0x00000000,
208 0x00000000,
209 0x00000000,
210 0x00000000,
211 0x00000000,
212 0x00000000,
213 0x00000000,
214 0x00000000,
215 0x00000000,
216};
217
218static const u16 dot11lcn_aux_gain_idx_tbl_rev0[] = {
219 0x0401,
220 0x0402,
221 0x0403,
222 0x0404,
223 0x0405,
224 0x0406,
225 0x0407,
226 0x0408,
227 0x0409,
228 0x040a,
229 0x058b,
230 0x058c,
231 0x058d,
232 0x058e,
233 0x058f,
234 0x0090,
235 0x0091,
236 0x0092,
237 0x0193,
238 0x0194,
239 0x0195,
240 0x0196,
241 0x0197,
242 0x0198,
243 0x0199,
244 0x019a,
245 0x019b,
246 0x019c,
247 0x019d,
248 0x019e,
249 0x019f,
250 0x01a0,
251 0x01a1,
252 0x01a2,
253 0x01a3,
254 0x01a4,
255 0x01a5,
256 0x0000,
257};
258
259static const u32 dot11lcn_gain_idx_tbl_rev0[] = {
260 0x00000000,
261 0x00000000,
262 0x10000000,
263 0x00000000,
264 0x20000000,
265 0x00000000,
266 0x30000000,
267 0x00000000,
268 0x40000000,
269 0x00000000,
270 0x50000000,
271 0x00000000,
272 0x60000000,
273 0x00000000,
274 0x70000000,
275 0x00000000,
276 0x80000000,
277 0x00000000,
278 0x90000000,
279 0x00000008,
280 0xa0000000,
281 0x00000008,
282 0xb0000000,
283 0x00000008,
284 0xc0000000,
285 0x00000008,
286 0xd0000000,
287 0x00000008,
288 0xe0000000,
289 0x00000008,
290 0xf0000000,
291 0x00000008,
292 0x00000000,
293 0x00000009,
294 0x10000000,
295 0x00000009,
296 0x20000000,
297 0x00000019,
298 0x30000000,
299 0x00000019,
300 0x40000000,
301 0x00000019,
302 0x50000000,
303 0x00000019,
304 0x60000000,
305 0x00000019,
306 0x70000000,
307 0x00000019,
308 0x80000000,
309 0x00000019,
310 0x90000000,
311 0x00000019,
312 0xa0000000,
313 0x00000019,
314 0xb0000000,
315 0x00000019,
316 0xc0000000,
317 0x00000019,
318 0xd0000000,
319 0x00000019,
320 0xe0000000,
321 0x00000019,
322 0xf0000000,
323 0x00000019,
324 0x00000000,
325 0x0000001a,
326 0x10000000,
327 0x0000001a,
328 0x20000000,
329 0x0000001a,
330 0x30000000,
331 0x0000001a,
332 0x40000000,
333 0x0000001a,
334 0x50000000,
335 0x00000002,
336 0x60000000,
337 0x00000002,
338 0x70000000,
339 0x00000002,
340 0x80000000,
341 0x00000002,
342 0x90000000,
343 0x00000002,
344 0xa0000000,
345 0x00000002,
346 0xb0000000,
347 0x00000002,
348 0xc0000000,
349 0x0000000a,
350 0xd0000000,
351 0x0000000a,
352 0xe0000000,
353 0x0000000a,
354 0xf0000000,
355 0x0000000a,
356 0x00000000,
357 0x0000000b,
358 0x10000000,
359 0x0000000b,
360 0x20000000,
361 0x0000000b,
362 0x30000000,
363 0x0000000b,
364 0x40000000,
365 0x0000000b,
366 0x50000000,
367 0x0000001b,
368 0x60000000,
369 0x0000001b,
370 0x70000000,
371 0x0000001b,
372 0x80000000,
373 0x0000001b,
374 0x90000000,
375 0x0000001b,
376 0xa0000000,
377 0x0000001b,
378 0xb0000000,
379 0x0000001b,
380 0xc0000000,
381 0x0000001b,
382 0xd0000000,
383 0x0000001b,
384 0xe0000000,
385 0x0000001b,
386 0xf0000000,
387 0x0000001b,
388 0x00000000,
389 0x0000001c,
390 0x10000000,
391 0x0000001c,
392 0x20000000,
393 0x0000001c,
394 0x30000000,
395 0x0000001c,
396 0x40000000,
397 0x0000001c,
398 0x50000000,
399 0x0000001c,
400 0x60000000,
401 0x0000001c,
402 0x70000000,
403 0x0000001c,
404 0x80000000,
405 0x0000001c,
406 0x90000000,
407 0x0000001c,
408};
409
410static const u16 dot11lcn_aux_gain_idx_tbl_2G[] = {
411 0x0000,
412 0x0000,
413 0x0000,
414 0x0000,
415 0x0001,
416 0x0080,
417 0x0081,
418 0x0100,
419 0x0101,
420 0x0180,
421 0x0181,
422 0x0182,
423 0x0183,
424 0x0184,
425 0x0185,
426 0x0186,
427 0x0187,
428 0x0188,
429 0x0285,
430 0x0289,
431 0x028a,
432 0x028b,
433 0x028c,
434 0x028d,
435 0x028e,
436 0x028f,
437 0x0290,
438 0x0291,
439 0x0292,
440 0x0293,
441 0x0294,
442 0x0295,
443 0x0296,
444 0x0297,
445 0x0298,
446 0x0299,
447 0x029a,
448 0x0000
449};
450
451static const u8 dot11lcn_gain_val_tbl_2G[] = {
452 0xfc,
453 0x02,
454 0x08,
455 0x0e,
456 0x13,
457 0x1b,
458 0xfc,
459 0x02,
460 0x08,
461 0x0e,
462 0x13,
463 0x1b,
464 0xfc,
465 0x00,
466 0x0c,
467 0x03,
468 0xeb,
469 0xfe,
470 0x07,
471 0x0b,
472 0x0f,
473 0xfb,
474 0xfe,
475 0x01,
476 0x05,
477 0x08,
478 0x0b,
479 0x0e,
480 0x11,
481 0x14,
482 0x17,
483 0x00,
484 0x00,
485 0x00,
486 0x00,
487 0x00,
488 0x00,
489 0x00,
490 0x03,
491 0x06,
492 0x09,
493 0x0c,
494 0x0f,
495 0x12,
496 0x00,
497 0x00,
498 0x00,
499 0x00,
500 0x00,
501 0x00,
502 0x00,
503 0x00,
504 0x00,
505 0x00,
506 0x03,
507 0x06,
508 0x09,
509 0x0c,
510 0x0f,
511 0x12,
512 0x15,
513 0x18,
514 0x1b,
515 0x00,
516 0x00,
517 0x00,
518 0x00,
519 0x00
520};
521
522static const u32 dot11lcn_gain_idx_tbl_2G[] = {
523 0x00000000,
524 0x00000000,
525 0x00000000,
526 0x00000000,
527 0x00000000,
528 0x00000000,
529 0x00000000,
530 0x00000000,
531 0x10000000,
532 0x00000000,
533 0x00000000,
534 0x00000008,
535 0x10000000,
536 0x00000008,
537 0x00000000,
538 0x00000010,
539 0x10000000,
540 0x00000010,
541 0x00000000,
542 0x00000018,
543 0x10000000,
544 0x00000018,
545 0x20000000,
546 0x00000018,
547 0x30000000,
548 0x00000018,
549 0x40000000,
550 0x00000018,
551 0x50000000,
552 0x00000018,
553 0x60000000,
554 0x00000018,
555 0x70000000,
556 0x00000018,
557 0x80000000,
558 0x00000018,
559 0x50000000,
560 0x00000028,
561 0x90000000,
562 0x00000028,
563 0xa0000000,
564 0x00000028,
565 0xb0000000,
566 0x00000028,
567 0xc0000000,
568 0x00000028,
569 0xd0000000,
570 0x00000028,
571 0xe0000000,
572 0x00000028,
573 0xf0000000,
574 0x00000028,
575 0x00000000,
576 0x00000029,
577 0x10000000,
578 0x00000029,
579 0x20000000,
580 0x00000029,
581 0x30000000,
582 0x00000029,
583 0x40000000,
584 0x00000029,
585 0x50000000,
586 0x00000029,
587 0x60000000,
588 0x00000029,
589 0x70000000,
590 0x00000029,
591 0x80000000,
592 0x00000029,
593 0x90000000,
594 0x00000029,
595 0xa0000000,
596 0x00000029,
597 0x00000000,
598 0x00000000,
599 0x00000000,
600 0x00000000,
601 0x10000000,
602 0x00000000,
603 0x00000000,
604 0x00000008,
605 0x10000000,
606 0x00000008,
607 0x00000000,
608 0x00000010,
609 0x10000000,
610 0x00000010,
611 0x00000000,
612 0x00000018,
613 0x10000000,
614 0x00000018,
615 0x20000000,
616 0x00000018,
617 0x30000000,
618 0x00000018,
619 0x40000000,
620 0x00000018,
621 0x50000000,
622 0x00000018,
623 0x60000000,
624 0x00000018,
625 0x70000000,
626 0x00000018,
627 0x80000000,
628 0x00000018,
629 0x50000000,
630 0x00000028,
631 0x90000000,
632 0x00000028,
633 0xa0000000,
634 0x00000028,
635 0xb0000000,
636 0x00000028,
637 0xc0000000,
638 0x00000028,
639 0xd0000000,
640 0x00000028,
641 0xe0000000,
642 0x00000028,
643 0xf0000000,
644 0x00000028,
645 0x00000000,
646 0x00000029,
647 0x10000000,
648 0x00000029,
649 0x20000000,
650 0x00000029,
651 0x30000000,
652 0x00000029,
653 0x40000000,
654 0x00000029,
655 0x50000000,
656 0x00000029,
657 0x60000000,
658 0x00000029,
659 0x70000000,
660 0x00000029,
661 0x80000000,
662 0x00000029,
663 0x90000000,
664 0x00000029,
665 0xa0000000,
666 0x00000029,
667 0xb0000000,
668 0x00000029,
669 0xc0000000,
670 0x00000029,
671 0x00000000,
672 0x00000000,
673 0x00000000,
674 0x00000000
675};
676
677static const u32 dot11lcn_gain_tbl_2G[] = {
678 0x00000000,
679 0x00000004,
680 0x00000008,
681 0x00000001,
682 0x00000005,
683 0x00000009,
684 0x0000000d,
685 0x0000004d,
686 0x0000008d,
687 0x00000049,
688 0x00000089,
689 0x000000c9,
690 0x0000004b,
691 0x0000008b,
692 0x000000cb,
693 0x000000cf,
694 0x0000010f,
695 0x0000050f,
696 0x0000090f,
697 0x0000094f,
698 0x00000d4f,
699 0x0000114f,
700 0x0000118f,
701 0x0000518f,
702 0x0000918f,
703 0x0000d18f,
704 0x0001118f,
705 0x0001518f,
706 0x0001918f,
707 0x00000000,
708 0x00000000,
709 0x00000000,
710 0x00000000,
711 0x00000000,
712 0x00000000,
713 0x00000000,
714 0x00000000,
715 0x00000000,
716 0x00000000,
717 0x00000000,
718 0x00000000,
719 0x00000000,
720 0x00000000,
721 0x00000000,
722 0x00000000,
723 0x00000000,
724 0x00000000,
725 0x00000000,
726 0x00000000,
727 0x00000000,
728 0x00000000,
729 0x00000000,
730 0x00000000,
731 0x00000000,
732 0x00000000,
733 0x00000000,
734 0x00000000,
735 0x00000000,
736 0x00000000,
737 0x00000000,
738 0x00000000,
739 0x00000000,
740 0x00000000,
741 0x00000000,
742 0x00000000,
743 0x00000000,
744 0x00000000,
745 0x00000000,
746 0x00000000,
747 0x00000000,
748 0x00000000,
749 0x00000000,
750 0x00000000,
751 0x00000000,
752 0x00000000,
753 0x00000000,
754 0x00000000,
755 0x00000000,
756 0x00000000,
757 0x00000000,
758 0x00000000,
759 0x00000000,
760 0x00000000,
761 0x00000000,
762 0x00000000,
763 0x00000000,
764 0x00000000,
765 0x00000000,
766 0x00000000,
767 0x00000000,
768 0x00000000,
769 0x00000000,
770 0x00000000,
771 0x00000000,
772 0x00000000,
773 0x00000000
774};
775
776static const u32 dot11lcn_gain_tbl_extlna_2G[] = {
777 0x00000000,
778 0x00000004,
779 0x00000008,
780 0x00000001,
781 0x00000005,
782 0x00000009,
783 0x0000000d,
784 0x00000003,
785 0x00000007,
786 0x0000000b,
787 0x0000000f,
788 0x0000004f,
789 0x0000008f,
790 0x000000cf,
791 0x0000010f,
792 0x0000014f,
793 0x0000018f,
794 0x0000058f,
795 0x0000098f,
796 0x00000d8f,
797 0x00008000,
798 0x00008004,
799 0x00008008,
800 0x00008001,
801 0x00008005,
802 0x00008009,
803 0x0000800d,
804 0x00008003,
805 0x00008007,
806 0x0000800b,
807 0x0000800f,
808 0x0000804f,
809 0x0000808f,
810 0x000080cf,
811 0x0000810f,
812 0x0000814f,
813 0x0000818f,
814 0x0000858f,
815 0x0000898f,
816 0x00008d8f,
817 0x00000000,
818 0x00000000,
819 0x00000000,
820 0x00000000,
821 0x00000000,
822 0x00000000,
823 0x00000000,
824 0x00000000,
825 0x00000000,
826 0x00000000,
827 0x00000000,
828 0x00000000,
829 0x00000000,
830 0x00000000,
831 0x00000000,
832 0x00000000,
833 0x00000000,
834 0x00000000,
835 0x00000000,
836 0x00000000,
837 0x00000000,
838 0x00000000,
839 0x00000000,
840 0x00000000,
841 0x00000000,
842 0x00000000,
843 0x00000000,
844 0x00000000,
845 0x00000000,
846 0x00000000,
847 0x00000000,
848 0x00000000,
849 0x00000000,
850 0x00000000,
851 0x00000000,
852 0x00000000,
853 0x00000000,
854 0x00000000,
855 0x00000000,
856 0x00000000,
857 0x00000000,
858 0x00000000,
859 0x00000000,
860 0x00000000,
861 0x00000000,
862 0x00000000,
863 0x00000000,
864 0x00000000,
865 0x00000000,
866 0x00000000,
867 0x00000000,
868 0x00000000,
869 0x00000000,
870 0x00000000,
871 0x00000000,
872 0x00000000
873};
874
875static const u16 dot11lcn_aux_gain_idx_tbl_extlna_2G[] = {
876 0x0400,
877 0x0400,
878 0x0400,
879 0x0400,
880 0x0400,
881 0x0400,
882 0x0400,
883 0x0400,
884 0x0400,
885 0x0401,
886 0x0402,
887 0x0403,
888 0x0404,
889 0x0483,
890 0x0484,
891 0x0485,
892 0x0486,
893 0x0583,
894 0x0584,
895 0x0585,
896 0x0587,
897 0x0588,
898 0x0589,
899 0x058a,
900 0x0687,
901 0x0688,
902 0x0689,
903 0x068a,
904 0x068b,
905 0x068c,
906 0x068d,
907 0x068e,
908 0x068f,
909 0x0690,
910 0x0691,
911 0x0692,
912 0x0693,
913 0x0000
914};
915
916static const u8 dot11lcn_gain_val_tbl_extlna_2G[] = {
917 0xfc,
918 0x02,
919 0x08,
920 0x0e,
921 0x13,
922 0x1b,
923 0xfc,
924 0x02,
925 0x08,
926 0x0e,
927 0x13,
928 0x1b,
929 0xfc,
930 0x00,
931 0x0f,
932 0x03,
933 0xeb,
934 0xfe,
935 0x07,
936 0x0b,
937 0x0f,
938 0xfb,
939 0xfe,
940 0x01,
941 0x05,
942 0x08,
943 0x0b,
944 0x0e,
945 0x11,
946 0x14,
947 0x17,
948 0x00,
949 0x00,
950 0x00,
951 0x00,
952 0x00,
953 0x00,
954 0x00,
955 0x03,
956 0x06,
957 0x09,
958 0x0c,
959 0x0f,
960 0x12,
961 0x00,
962 0x00,
963 0x00,
964 0x00,
965 0x00,
966 0x00,
967 0x00,
968 0x00,
969 0x00,
970 0x00,
971 0x03,
972 0x06,
973 0x09,
974 0x0c,
975 0x0f,
976 0x12,
977 0x15,
978 0x18,
979 0x1b,
980 0x00,
981 0x00,
982 0x00,
983 0x00,
984 0x00
985};
986
987static const u32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
988 0x00000000,
989 0x00000040,
990 0x00000000,
991 0x00000040,
992 0x00000000,
993 0x00000040,
994 0x00000000,
995 0x00000040,
996 0x00000000,
997 0x00000040,
998 0x00000000,
999 0x00000040,
1000 0x00000000,
1001 0x00000040,
1002 0x00000000,
1003 0x00000040,
1004 0x00000000,
1005 0x00000040,
1006 0x10000000,
1007 0x00000040,
1008 0x20000000,
1009 0x00000040,
1010 0x30000000,
1011 0x00000040,
1012 0x40000000,
1013 0x00000040,
1014 0x30000000,
1015 0x00000048,
1016 0x40000000,
1017 0x00000048,
1018 0x50000000,
1019 0x00000048,
1020 0x60000000,
1021 0x00000048,
1022 0x30000000,
1023 0x00000058,
1024 0x40000000,
1025 0x00000058,
1026 0x50000000,
1027 0x00000058,
1028 0x70000000,
1029 0x00000058,
1030 0x80000000,
1031 0x00000058,
1032 0x90000000,
1033 0x00000058,
1034 0xa0000000,
1035 0x00000058,
1036 0x70000000,
1037 0x00000068,
1038 0x80000000,
1039 0x00000068,
1040 0x90000000,
1041 0x00000068,
1042 0xa0000000,
1043 0x00000068,
1044 0xb0000000,
1045 0x00000068,
1046 0xc0000000,
1047 0x00000068,
1048 0xd0000000,
1049 0x00000068,
1050 0xe0000000,
1051 0x00000068,
1052 0xf0000000,
1053 0x00000068,
1054 0x00000000,
1055 0x00000069,
1056 0x10000000,
1057 0x00000069,
1058 0x20000000,
1059 0x00000069,
1060 0x30000000,
1061 0x00000069,
1062 0x40000000,
1063 0x00000041,
1064 0x40000000,
1065 0x00000041,
1066 0x40000000,
1067 0x00000041,
1068 0x40000000,
1069 0x00000041,
1070 0x40000000,
1071 0x00000041,
1072 0x40000000,
1073 0x00000041,
1074 0x40000000,
1075 0x00000041,
1076 0x40000000,
1077 0x00000041,
1078 0x40000000,
1079 0x00000041,
1080 0x50000000,
1081 0x00000041,
1082 0x60000000,
1083 0x00000041,
1084 0x70000000,
1085 0x00000041,
1086 0x80000000,
1087 0x00000041,
1088 0x70000000,
1089 0x00000049,
1090 0x80000000,
1091 0x00000049,
1092 0x90000000,
1093 0x00000049,
1094 0xa0000000,
1095 0x00000049,
1096 0x70000000,
1097 0x00000059,
1098 0x80000000,
1099 0x00000059,
1100 0x90000000,
1101 0x00000059,
1102 0xb0000000,
1103 0x00000059,
1104 0xc0000000,
1105 0x00000059,
1106 0xd0000000,
1107 0x00000059,
1108 0xe0000000,
1109 0x00000059,
1110 0xb0000000,
1111 0x00000069,
1112 0xc0000000,
1113 0x00000069,
1114 0xd0000000,
1115 0x00000069,
1116 0xe0000000,
1117 0x00000069,
1118 0xf0000000,
1119 0x00000069,
1120 0x00000000,
1121 0x0000006a,
1122 0x10000000,
1123 0x0000006a,
1124 0x20000000,
1125 0x0000006a,
1126 0x30000000,
1127 0x0000006a,
1128 0x40000000,
1129 0x0000006a,
1130 0x50000000,
1131 0x0000006a,
1132 0x60000000,
1133 0x0000006a,
1134 0x70000000,
1135 0x0000006a,
1136 0x00000000,
1137 0x00000000,
1138 0x00000000,
1139 0x00000000
1140};
1141
1142static const u32 dot11lcn_aux_gain_idx_tbl_5G[] = {
1143 0x0000,
1144 0x0000,
1145 0x0000,
1146 0x0000,
1147 0x0001,
1148 0x0002,
1149 0x0003,
1150 0x0004,
1151 0x0083,
1152 0x0084,
1153 0x0085,
1154 0x0086,
1155 0x0087,
1156 0x0186,
1157 0x0187,
1158 0x0188,
1159 0x0189,
1160 0x018a,
1161 0x018b,
1162 0x018c,
1163 0x018d,
1164 0x018e,
1165 0x018f,
1166 0x0190,
1167 0x0191,
1168 0x0192,
1169 0x0193,
1170 0x0194,
1171 0x0195,
1172 0x0196,
1173 0x0197,
1174 0x0198,
1175 0x0199,
1176 0x019a,
1177 0x019b,
1178 0x019c,
1179 0x019d,
1180 0x0000
1181};
1182
1183static const u32 dot11lcn_gain_val_tbl_5G[] = {
1184 0xf7,
1185 0xfd,
1186 0x00,
1187 0x04,
1188 0x04,
1189 0x04,
1190 0xf7,
1191 0xfd,
1192 0x00,
1193 0x04,
1194 0x04,
1195 0x04,
1196 0xf6,
1197 0x00,
1198 0x0c,
1199 0x03,
1200 0xeb,
1201 0xfe,
1202 0x06,
1203 0x0a,
1204 0x10,
1205 0x00,
1206 0x03,
1207 0x06,
1208 0x09,
1209 0x0c,
1210 0x0f,
1211 0x12,
1212 0x15,
1213 0x18,
1214 0x1b,
1215 0x00,
1216 0x00,
1217 0x00,
1218 0x00,
1219 0x00,
1220 0x00,
1221 0x00,
1222 0x03,
1223 0x06,
1224 0x09,
1225 0x0c,
1226 0x0f,
1227 0x12,
1228 0x00,
1229 0x00,
1230 0x00,
1231 0x00,
1232 0x00,
1233 0x00,
1234 0x00,
1235 0x00,
1236 0x00,
1237 0x00,
1238 0x03,
1239 0x06,
1240 0x09,
1241 0x0c,
1242 0x0f,
1243 0x12,
1244 0x15,
1245 0x18,
1246 0x1b,
1247 0x00,
1248 0x00,
1249 0x00,
1250 0x00,
1251 0x00
1252};
1253
1254static const u32 dot11lcn_gain_idx_tbl_5G[] = {
1255 0x00000000,
1256 0x00000000,
1257 0x00000000,
1258 0x00000000,
1259 0x00000000,
1260 0x00000000,
1261 0x00000000,
1262 0x00000000,
1263 0x10000000,
1264 0x00000000,
1265 0x20000000,
1266 0x00000000,
1267 0x30000000,
1268 0x00000000,
1269 0x40000000,
1270 0x00000000,
1271 0x30000000,
1272 0x00000008,
1273 0x40000000,
1274 0x00000008,
1275 0x50000000,
1276 0x00000008,
1277 0x60000000,
1278 0x00000008,
1279 0x70000000,
1280 0x00000008,
1281 0x60000000,
1282 0x00000018,
1283 0x70000000,
1284 0x00000018,
1285 0x80000000,
1286 0x00000018,
1287 0x90000000,
1288 0x00000018,
1289 0xa0000000,
1290 0x00000018,
1291 0xb0000000,
1292 0x00000018,
1293 0xc0000000,
1294 0x00000018,
1295 0xd0000000,
1296 0x00000018,
1297 0xe0000000,
1298 0x00000018,
1299 0xf0000000,
1300 0x00000018,
1301 0x00000000,
1302 0x00000019,
1303 0x10000000,
1304 0x00000019,
1305 0x20000000,
1306 0x00000019,
1307 0x30000000,
1308 0x00000019,
1309 0x40000000,
1310 0x00000019,
1311 0x50000000,
1312 0x00000019,
1313 0x60000000,
1314 0x00000019,
1315 0x70000000,
1316 0x00000019,
1317 0x80000000,
1318 0x00000019,
1319 0x90000000,
1320 0x00000019,
1321 0xa0000000,
1322 0x00000019,
1323 0xb0000000,
1324 0x00000019,
1325 0xc0000000,
1326 0x00000019,
1327 0xd0000000,
1328 0x00000019,
1329 0x00000000,
1330 0x00000000,
1331 0x00000000,
1332 0x00000000,
1333 0x00000000,
1334 0x00000000,
1335 0x00000000,
1336 0x00000000,
1337 0x00000000,
1338 0x00000000,
1339 0x00000000,
1340 0x00000000,
1341 0x00000000,
1342 0x00000000,
1343 0x00000000,
1344 0x00000000,
1345 0x00000000,
1346 0x00000000,
1347 0x00000000,
1348 0x00000000,
1349 0x00000000,
1350 0x00000000,
1351 0x00000000,
1352 0x00000000,
1353 0x00000000,
1354 0x00000000,
1355 0x00000000,
1356 0x00000000,
1357 0x00000000,
1358 0x00000000,
1359 0x00000000,
1360 0x00000000,
1361 0x00000000,
1362 0x00000000,
1363 0x00000000,
1364 0x00000000,
1365 0x00000000,
1366 0x00000000,
1367 0x00000000,
1368 0x00000000,
1369 0x00000000,
1370 0x00000000,
1371 0x00000000,
1372 0x00000000,
1373 0x00000000,
1374 0x00000000,
1375 0x00000000,
1376 0x00000000,
1377 0x00000000,
1378 0x00000000,
1379 0x00000000,
1380 0x00000000,
1381 0x00000000,
1382 0x00000000,
1383 0x00000000,
1384 0x00000000,
1385 0x00000000,
1386 0x00000000,
1387 0x00000000,
1388 0x00000000,
1389 0x00000000,
1390 0x00000000,
1391 0x00000000,
1392 0x00000000,
1393 0x00000000,
1394 0x00000000,
1395 0x00000000,
1396 0x00000000,
1397 0x00000000,
1398 0x00000000,
1399 0x00000000,
1400 0x00000000,
1401 0x00000000,
1402 0x00000000,
1403 0x00000000,
1404 0x00000000,
1405 0x00000000,
1406 0x00000000
1407};
1408
1409static const u32 dot11lcn_gain_tbl_5G[] = {
1410 0x00000000,
1411 0x00000040,
1412 0x00000080,
1413 0x00000001,
1414 0x00000005,
1415 0x00000009,
1416 0x0000000d,
1417 0x00000011,
1418 0x00000015,
1419 0x00000055,
1420 0x00000095,
1421 0x00000017,
1422 0x0000001b,
1423 0x0000005b,
1424 0x0000009b,
1425 0x000000db,
1426 0x0000011b,
1427 0x0000015b,
1428 0x0000019b,
1429 0x0000059b,
1430 0x0000099b,
1431 0x00000d9b,
1432 0x0000119b,
1433 0x0000519b,
1434 0x0000919b,
1435 0x0000d19b,
1436 0x0001119b,
1437 0x0001519b,
1438 0x0001919b,
1439 0x0001d19b,
1440 0x00000000,
1441 0x00000000,
1442 0x00000000,
1443 0x00000000,
1444 0x00000000,
1445 0x00000000,
1446 0x00000000,
1447 0x00000000,
1448 0x00000000,
1449 0x00000000,
1450 0x00000000,
1451 0x00000000,
1452 0x00000000,
1453 0x00000000,
1454 0x00000000,
1455 0x00000000,
1456 0x00000000,
1457 0x00000000,
1458 0x00000000,
1459 0x00000000,
1460 0x00000000,
1461 0x00000000,
1462 0x00000000,
1463 0x00000000,
1464 0x00000000,
1465 0x00000000,
1466 0x00000000,
1467 0x00000000,
1468 0x00000000,
1469 0x00000000,
1470 0x00000000,
1471 0x00000000,
1472 0x00000000,
1473 0x00000000,
1474 0x00000000,
1475 0x00000000,
1476 0x00000000,
1477 0x00000000,
1478 0x00000000,
1479 0x00000000,
1480 0x00000000,
1481 0x00000000,
1482 0x00000000,
1483 0x00000000,
1484 0x00000000,
1485 0x00000000,
1486 0x00000000,
1487 0x00000000,
1488 0x00000000,
1489 0x00000000,
1490 0x00000000,
1491 0x00000000,
1492 0x00000000,
1493 0x00000000,
1494 0x00000000,
1495 0x00000000,
1496 0x00000000,
1497 0x00000000,
1498 0x00000000,
1499 0x00000000,
1500 0x00000000,
1501 0x00000000,
1502 0x00000000,
1503 0x00000000,
1504 0x00000000,
1505 0x00000000
1506};
1507
1508const struct phytbl_info dot11lcnphytbl_rx_gain_info_rev0[] = {
1509 {&dot11lcn_gain_tbl_rev0,
1510 sizeof(dot11lcn_gain_tbl_rev0) / sizeof(dot11lcn_gain_tbl_rev0[0]), 18,
1511 0, 32}
1512 ,
1513 {&dot11lcn_aux_gain_idx_tbl_rev0,
1514 sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
1515 sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
1516 ,
1517 {&dot11lcn_gain_idx_tbl_rev0,
1518 sizeof(dot11lcn_gain_idx_tbl_rev0) /
1519 sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
1520 ,
1521};
1522
1523static const struct phytbl_info dot11lcnphytbl_rx_gain_info_rev1[] = {
1524 {&dot11lcn_gain_tbl_rev1,
1525 sizeof(dot11lcn_gain_tbl_rev1) / sizeof(dot11lcn_gain_tbl_rev1[0]), 18,
1526 0, 32}
1527 ,
1528 {&dot11lcn_aux_gain_idx_tbl_rev0,
1529 sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
1530 sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
1531 ,
1532 {&dot11lcn_gain_idx_tbl_rev0,
1533 sizeof(dot11lcn_gain_idx_tbl_rev0) /
1534 sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
1535 ,
1536};
1537
1538const struct phytbl_info dot11lcnphytbl_rx_gain_info_2G_rev2[] = {
1539 {&dot11lcn_gain_tbl_2G,
1540 sizeof(dot11lcn_gain_tbl_2G) / sizeof(dot11lcn_gain_tbl_2G[0]), 18, 0,
1541 32}
1542 ,
1543 {&dot11lcn_aux_gain_idx_tbl_2G,
1544 sizeof(dot11lcn_aux_gain_idx_tbl_2G) /
1545 sizeof(dot11lcn_aux_gain_idx_tbl_2G[0]), 14, 0, 16}
1546 ,
1547 {&dot11lcn_gain_idx_tbl_2G,
1548 sizeof(dot11lcn_gain_idx_tbl_2G) / sizeof(dot11lcn_gain_idx_tbl_2G[0]),
1549 13, 0, 32}
1550 ,
1551 {&dot11lcn_gain_val_tbl_2G,
1552 sizeof(dot11lcn_gain_val_tbl_2G) / sizeof(dot11lcn_gain_val_tbl_2G[0]),
1553 17, 0, 8}
1554};
1555
1556const struct phytbl_info dot11lcnphytbl_rx_gain_info_5G_rev2[] = {
1557 {&dot11lcn_gain_tbl_5G,
1558 sizeof(dot11lcn_gain_tbl_5G) / sizeof(dot11lcn_gain_tbl_5G[0]), 18, 0,
1559 32}
1560 ,
1561 {&dot11lcn_aux_gain_idx_tbl_5G,
1562 sizeof(dot11lcn_aux_gain_idx_tbl_5G) /
1563 sizeof(dot11lcn_aux_gain_idx_tbl_5G[0]), 14, 0, 16}
1564 ,
1565 {&dot11lcn_gain_idx_tbl_5G,
1566 sizeof(dot11lcn_gain_idx_tbl_5G) / sizeof(dot11lcn_gain_idx_tbl_5G[0]),
1567 13, 0, 32}
1568 ,
1569 {&dot11lcn_gain_val_tbl_5G,
1570 sizeof(dot11lcn_gain_val_tbl_5G) / sizeof(dot11lcn_gain_val_tbl_5G[0]),
1571 17, 0, 8}
1572};
1573
1574const struct phytbl_info dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[] = {
1575 {&dot11lcn_gain_tbl_extlna_2G,
1576 sizeof(dot11lcn_gain_tbl_extlna_2G) /
1577 sizeof(dot11lcn_gain_tbl_extlna_2G[0]), 18, 0, 32}
1578 ,
1579 {&dot11lcn_aux_gain_idx_tbl_extlna_2G,
1580 sizeof(dot11lcn_aux_gain_idx_tbl_extlna_2G) /
1581 sizeof(dot11lcn_aux_gain_idx_tbl_extlna_2G[0]), 14, 0, 16}
1582 ,
1583 {&dot11lcn_gain_idx_tbl_extlna_2G,
1584 sizeof(dot11lcn_gain_idx_tbl_extlna_2G) /
1585 sizeof(dot11lcn_gain_idx_tbl_extlna_2G[0]), 13, 0, 32}
1586 ,
1587 {&dot11lcn_gain_val_tbl_extlna_2G,
1588 sizeof(dot11lcn_gain_val_tbl_extlna_2G) /
1589 sizeof(dot11lcn_gain_val_tbl_extlna_2G[0]), 17, 0, 8}
1590};
1591
1592const struct phytbl_info dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[] = {
1593 {&dot11lcn_gain_tbl_5G,
1594 sizeof(dot11lcn_gain_tbl_5G) / sizeof(dot11lcn_gain_tbl_5G[0]), 18, 0,
1595 32}
1596 ,
1597 {&dot11lcn_aux_gain_idx_tbl_5G,
1598 sizeof(dot11lcn_aux_gain_idx_tbl_5G) /
1599 sizeof(dot11lcn_aux_gain_idx_tbl_5G[0]), 14, 0, 16}
1600 ,
1601 {&dot11lcn_gain_idx_tbl_5G,
1602 sizeof(dot11lcn_gain_idx_tbl_5G) / sizeof(dot11lcn_gain_idx_tbl_5G[0]),
1603 13, 0, 32}
1604 ,
1605 {&dot11lcn_gain_val_tbl_5G,
1606 sizeof(dot11lcn_gain_val_tbl_5G) / sizeof(dot11lcn_gain_val_tbl_5G[0]),
1607 17, 0, 8}
1608};
1609
1610const u32 dot11lcnphytbl_rx_gain_info_sz_rev0 =
1611 sizeof(dot11lcnphytbl_rx_gain_info_rev0) /
1612 sizeof(dot11lcnphytbl_rx_gain_info_rev0[0]);
1613
1614const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz =
1615 sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2) /
1616 sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2[0]);
1617
1618const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz =
1619 sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) /
1620 sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]);
1621
1622static const u16 dot11lcn_min_sig_sq_tbl_rev0[] = {
1623 0x014d,
1624 0x014d,
1625 0x014d,
1626 0x014d,
1627 0x014d,
1628 0x014d,
1629 0x014d,
1630 0x014d,
1631 0x014d,
1632 0x014d,
1633 0x014d,
1634 0x014d,
1635 0x014d,
1636 0x014d,
1637 0x014d,
1638 0x014d,
1639 0x014d,
1640 0x014d,
1641 0x014d,
1642 0x014d,
1643 0x014d,
1644 0x014d,
1645 0x014d,
1646 0x014d,
1647 0x014d,
1648 0x014d,
1649 0x014d,
1650 0x014d,
1651 0x014d,
1652 0x014d,
1653 0x014d,
1654 0x014d,
1655 0x014d,
1656 0x014d,
1657 0x014d,
1658 0x014d,
1659 0x014d,
1660 0x014d,
1661 0x014d,
1662 0x014d,
1663 0x014d,
1664 0x014d,
1665 0x014d,
1666 0x014d,
1667 0x014d,
1668 0x014d,
1669 0x014d,
1670 0x014d,
1671 0x014d,
1672 0x014d,
1673 0x014d,
1674 0x014d,
1675 0x014d,
1676 0x014d,
1677 0x014d,
1678 0x014d,
1679 0x014d,
1680 0x014d,
1681 0x014d,
1682 0x014d,
1683 0x014d,
1684 0x014d,
1685 0x014d,
1686 0x014d,
1687};
1688
1689static const u16 dot11lcn_noise_scale_tbl_rev0[] = {
1690 0x0000,
1691 0x0000,
1692 0x0000,
1693 0x0000,
1694 0x0000,
1695 0x0000,
1696 0x0000,
1697 0x0000,
1698 0x0000,
1699 0x0000,
1700 0x0000,
1701 0x0000,
1702 0x0000,
1703 0x0000,
1704 0x0000,
1705 0x0000,
1706 0x0000,
1707 0x0000,
1708 0x0000,
1709 0x0000,
1710 0x0000,
1711 0x0000,
1712 0x0000,
1713 0x0000,
1714 0x0000,
1715 0x0000,
1716 0x0000,
1717 0x0000,
1718 0x0000,
1719 0x0000,
1720 0x0000,
1721 0x0000,
1722 0x0000,
1723 0x0000,
1724 0x0000,
1725 0x0000,
1726 0x0000,
1727 0x0000,
1728 0x0000,
1729 0x0000,
1730 0x0000,
1731 0x0000,
1732 0x0000,
1733 0x0000,
1734 0x0000,
1735 0x0000,
1736 0x0000,
1737 0x0000,
1738 0x0000,
1739 0x0000,
1740 0x0000,
1741 0x0000,
1742 0x0000,
1743 0x0000,
1744 0x0000,
1745 0x0000,
1746 0x0000,
1747 0x0000,
1748 0x0000,
1749 0x0000,
1750 0x0000,
1751 0x0000,
1752 0x0000,
1753 0x0000,
1754};
1755
1756static const u32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
1757 0x000141f8,
1758 0x000021f8,
1759 0x000021fb,
1760 0x000041fb,
1761 0x0001fe4b,
1762 0x0000217b,
1763 0x00002133,
1764 0x000040eb,
1765 0x0001fea3,
1766 0x0000024b,
1767};
1768
1769static const u32 dot11lcn_ps_ctrl_tbl_rev0[] = {
1770 0x00100001,
1771 0x00200010,
1772 0x00300001,
1773 0x00400010,
1774 0x00500022,
1775 0x00600122,
1776 0x00700222,
1777 0x00800322,
1778 0x00900422,
1779 0x00a00522,
1780 0x00b00622,
1781 0x00c00722,
1782 0x00d00822,
1783 0x00f00922,
1784 0x00100a22,
1785 0x00200b22,
1786 0x00300c22,
1787 0x00400d22,
1788 0x00500e22,
1789 0x00600f22,
1790};
1791
1792static const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[] = {
1793 0x0007,
1794 0x0005,
1795 0x0006,
1796 0x0004,
1797 0x0007,
1798 0x0005,
1799 0x0006,
1800 0x0004,
1801 0x0007,
1802 0x0005,
1803 0x0006,
1804 0x0004,
1805 0x0007,
1806 0x0005,
1807 0x0006,
1808 0x0004,
1809 0x000b,
1810 0x000b,
1811 0x000a,
1812 0x000a,
1813 0x000b,
1814 0x000b,
1815 0x000a,
1816 0x000a,
1817 0x000b,
1818 0x000b,
1819 0x000a,
1820 0x000a,
1821 0x000b,
1822 0x000b,
1823 0x000a,
1824 0x000a,
1825 0x0007,
1826 0x0005,
1827 0x0006,
1828 0x0004,
1829 0x0007,
1830 0x0005,
1831 0x0006,
1832 0x0004,
1833 0x0007,
1834 0x0005,
1835 0x0006,
1836 0x0004,
1837 0x0007,
1838 0x0005,
1839 0x0006,
1840 0x0004,
1841 0x000b,
1842 0x000b,
1843 0x000a,
1844 0x000a,
1845 0x000b,
1846 0x000b,
1847 0x000a,
1848 0x000a,
1849 0x000b,
1850 0x000b,
1851 0x000a,
1852 0x000a,
1853 0x000b,
1854 0x000b,
1855 0x000a,
1856 0x000a,
1857
1858};
1859
1860static const u16 dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[] = {
1861 0x0007,
1862 0x0005,
1863 0x0002,
1864 0x0000,
1865 0x0007,
1866 0x0005,
1867 0x0002,
1868 0x0000,
1869 0x0007,
1870 0x0005,
1871 0x0002,
1872 0x0000,
1873 0x0007,
1874 0x0005,
1875 0x0002,
1876 0x0000,
1877 0x0007,
1878 0x0007,
1879 0x0002,
1880 0x0002,
1881 0x0007,
1882 0x0007,
1883 0x0002,
1884 0x0002,
1885 0x0007,
1886 0x0007,
1887 0x0002,
1888 0x0002,
1889 0x0007,
1890 0x0007,
1891 0x0002,
1892 0x0002,
1893 0x0007,
1894 0x0005,
1895 0x0002,
1896 0x0000,
1897 0x0007,
1898 0x0005,
1899 0x0002,
1900 0x0000,
1901 0x0007,
1902 0x0005,
1903 0x0002,
1904 0x0000,
1905 0x0007,
1906 0x0005,
1907 0x0002,
1908 0x0000,
1909 0x0007,
1910 0x0007,
1911 0x0002,
1912 0x0002,
1913 0x0007,
1914 0x0007,
1915 0x0002,
1916 0x0002,
1917 0x0007,
1918 0x0007,
1919 0x0002,
1920 0x0002,
1921 0x0007,
1922 0x0007,
1923 0x0002,
1924 0x0002,
1925};
1926
1927static const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0[] = {
1928 0x0002,
1929 0x0008,
1930 0x0004,
1931 0x0001,
1932 0x0002,
1933 0x0008,
1934 0x0004,
1935 0x0001,
1936 0x0002,
1937 0x0008,
1938 0x0004,
1939 0x0001,
1940 0x0002,
1941 0x0008,
1942 0x0004,
1943 0x0001,
1944 0x0002,
1945 0x0008,
1946 0x0004,
1947 0x0001,
1948 0x0002,
1949 0x0008,
1950 0x0004,
1951 0x0001,
1952 0x0002,
1953 0x0008,
1954 0x0004,
1955 0x0001,
1956 0x0002,
1957 0x0008,
1958 0x0004,
1959 0x0001,
1960 0x0002,
1961 0x0008,
1962 0x0004,
1963 0x0001,
1964 0x0002,
1965 0x0008,
1966 0x0004,
1967 0x0001,
1968 0x0002,
1969 0x0008,
1970 0x0004,
1971 0x0001,
1972 0x0002,
1973 0x0008,
1974 0x0004,
1975 0x0001,
1976 0x0002,
1977 0x0008,
1978 0x0004,
1979 0x0001,
1980 0x0002,
1981 0x0008,
1982 0x0004,
1983 0x0001,
1984 0x0002,
1985 0x0008,
1986 0x0004,
1987 0x0001,
1988 0x0002,
1989 0x0008,
1990 0x0004,
1991 0x0001,
1992};
1993
1994static const u16 dot11lcn_sw_ctrl_tbl_4313_rev0[] = {
1995 0x000a,
1996 0x0009,
1997 0x0006,
1998 0x0005,
1999 0x000a,
2000 0x0009,
2001 0x0006,
2002 0x0005,
2003 0x000a,
2004 0x0009,
2005 0x0006,
2006 0x0005,
2007 0x000a,
2008 0x0009,
2009 0x0006,
2010 0x0005,
2011 0x000a,
2012 0x0009,
2013 0x0006,
2014 0x0005,
2015 0x000a,
2016 0x0009,
2017 0x0006,
2018 0x0005,
2019 0x000a,
2020 0x0009,
2021 0x0006,
2022 0x0005,
2023 0x000a,
2024 0x0009,
2025 0x0006,
2026 0x0005,
2027 0x000a,
2028 0x0009,
2029 0x0006,
2030 0x0005,
2031 0x000a,
2032 0x0009,
2033 0x0006,
2034 0x0005,
2035 0x000a,
2036 0x0009,
2037 0x0006,
2038 0x0005,
2039 0x000a,
2040 0x0009,
2041 0x0006,
2042 0x0005,
2043 0x000a,
2044 0x0009,
2045 0x0006,
2046 0x0005,
2047 0x000a,
2048 0x0009,
2049 0x0006,
2050 0x0005,
2051 0x000a,
2052 0x0009,
2053 0x0006,
2054 0x0005,
2055 0x000a,
2056 0x0009,
2057 0x0006,
2058 0x0005,
2059};
2060
2061static const u16 dot11lcn_sw_ctrl_tbl_rev0[] = {
2062 0x0004,
2063 0x0004,
2064 0x0002,
2065 0x0002,
2066 0x0004,
2067 0x0004,
2068 0x0002,
2069 0x0002,
2070 0x0004,
2071 0x0004,
2072 0x0002,
2073 0x0002,
2074 0x0004,
2075 0x0004,
2076 0x0002,
2077 0x0002,
2078 0x0004,
2079 0x0004,
2080 0x0002,
2081 0x0002,
2082 0x0004,
2083 0x0004,
2084 0x0002,
2085 0x0002,
2086 0x0004,
2087 0x0004,
2088 0x0002,
2089 0x0002,
2090 0x0004,
2091 0x0004,
2092 0x0002,
2093 0x0002,
2094 0x0004,
2095 0x0004,
2096 0x0002,
2097 0x0002,
2098 0x0004,
2099 0x0004,
2100 0x0002,
2101 0x0002,
2102 0x0004,
2103 0x0004,
2104 0x0002,
2105 0x0002,
2106 0x0004,
2107 0x0004,
2108 0x0002,
2109 0x0002,
2110 0x0004,
2111 0x0004,
2112 0x0002,
2113 0x0002,
2114 0x0004,
2115 0x0004,
2116 0x0002,
2117 0x0002,
2118 0x0004,
2119 0x0004,
2120 0x0002,
2121 0x0002,
2122 0x0004,
2123 0x0004,
2124 0x0002,
2125 0x0002,
2126};
2127
2128static const u8 dot11lcn_nf_table_rev0[] = {
2129 0x5f,
2130 0x36,
2131 0x29,
2132 0x1f,
2133 0x5f,
2134 0x36,
2135 0x29,
2136 0x1f,
2137 0x5f,
2138 0x36,
2139 0x29,
2140 0x1f,
2141 0x5f,
2142 0x36,
2143 0x29,
2144 0x1f,
2145};
2146
2147static const u8 dot11lcn_gain_val_tbl_rev0[] = {
2148 0x09,
2149 0x0f,
2150 0x14,
2151 0x18,
2152 0xfe,
2153 0x07,
2154 0x0b,
2155 0x0f,
2156 0xfb,
2157 0xfe,
2158 0x01,
2159 0x05,
2160 0x08,
2161 0x0b,
2162 0x0e,
2163 0x11,
2164 0x14,
2165 0x17,
2166 0x00,
2167 0x00,
2168 0x00,
2169 0x00,
2170 0x00,
2171 0x00,
2172 0x00,
2173 0x03,
2174 0x06,
2175 0x09,
2176 0x0c,
2177 0x0f,
2178 0x12,
2179 0x00,
2180 0x00,
2181 0x00,
2182 0x00,
2183 0x00,
2184 0x00,
2185 0x00,
2186 0x00,
2187 0x00,
2188 0x00,
2189 0x03,
2190 0x06,
2191 0x09,
2192 0x0c,
2193 0x0f,
2194 0x12,
2195 0x15,
2196 0x18,
2197 0x1b,
2198 0x00,
2199 0x00,
2200 0x00,
2201 0x00,
2202 0x00,
2203 0x00,
2204 0x03,
2205 0xeb,
2206 0x00,
2207 0x00,
2208};
2209
2210static const u8 dot11lcn_spur_tbl_rev0[] = {
2211 0x01,
2212 0x01,
2213 0x01,
2214 0x01,
2215 0x01,
2216 0x01,
2217 0x01,
2218 0x01,
2219 0x01,
2220 0x01,
2221 0x01,
2222 0x01,
2223 0x01,
2224 0x01,
2225 0x01,
2226 0x01,
2227 0x01,
2228 0x01,
2229 0x01,
2230 0x01,
2231 0x01,
2232 0x01,
2233 0x01,
2234 0x01,
2235 0x01,
2236 0x01,
2237 0x01,
2238 0x01,
2239 0x01,
2240 0x01,
2241 0x02,
2242 0x03,
2243 0x01,
2244 0x03,
2245 0x02,
2246 0x01,
2247 0x01,
2248 0x01,
2249 0x01,
2250 0x01,
2251 0x01,
2252 0x01,
2253 0x01,
2254 0x01,
2255 0x01,
2256 0x01,
2257 0x01,
2258 0x01,
2259 0x01,
2260 0x01,
2261 0x01,
2262 0x01,
2263 0x01,
2264 0x01,
2265 0x01,
2266 0x01,
2267 0x01,
2268 0x01,
2269 0x01,
2270 0x01,
2271 0x01,
2272 0x01,
2273 0x01,
2274 0x01,
2275 0x01,
2276 0x01,
2277 0x01,
2278 0x01,
2279 0x01,
2280 0x01,
2281 0x01,
2282 0x01,
2283 0x01,
2284 0x01,
2285 0x01,
2286 0x01,
2287 0x01,
2288 0x01,
2289 0x01,
2290 0x01,
2291 0x01,
2292 0x01,
2293 0x01,
2294 0x01,
2295 0x01,
2296 0x01,
2297 0x01,
2298 0x01,
2299 0x01,
2300 0x01,
2301 0x01,
2302 0x01,
2303 0x01,
2304 0x01,
2305 0x02,
2306 0x03,
2307 0x01,
2308 0x03,
2309 0x02,
2310 0x01,
2311 0x01,
2312 0x01,
2313 0x01,
2314 0x01,
2315 0x01,
2316 0x01,
2317 0x01,
2318 0x01,
2319 0x01,
2320 0x01,
2321 0x01,
2322 0x01,
2323 0x01,
2324 0x01,
2325 0x01,
2326 0x01,
2327 0x01,
2328 0x01,
2329 0x01,
2330 0x01,
2331 0x01,
2332 0x01,
2333 0x01,
2334 0x01,
2335 0x01,
2336 0x01,
2337 0x01,
2338 0x01,
2339};
2340
2341static const u16 dot11lcn_unsup_mcs_tbl_rev0[] = {
2342 0x001a,
2343 0x0034,
2344 0x004e,
2345 0x0068,
2346 0x009c,
2347 0x00d0,
2348 0x00ea,
2349 0x0104,
2350 0x0034,
2351 0x0068,
2352 0x009c,
2353 0x00d0,
2354 0x0138,
2355 0x01a0,
2356 0x01d4,
2357 0x0208,
2358 0x004e,
2359 0x009c,
2360 0x00ea,
2361 0x0138,
2362 0x01d4,
2363 0x0270,
2364 0x02be,
2365 0x030c,
2366 0x0068,
2367 0x00d0,
2368 0x0138,
2369 0x01a0,
2370 0x0270,
2371 0x0340,
2372 0x03a8,
2373 0x0410,
2374 0x0018,
2375 0x009c,
2376 0x00d0,
2377 0x0104,
2378 0x00ea,
2379 0x0138,
2380 0x0186,
2381 0x00d0,
2382 0x0104,
2383 0x0104,
2384 0x0138,
2385 0x016c,
2386 0x016c,
2387 0x01a0,
2388 0x0138,
2389 0x0186,
2390 0x0186,
2391 0x01d4,
2392 0x0222,
2393 0x0222,
2394 0x0270,
2395 0x0104,
2396 0x0138,
2397 0x016c,
2398 0x0138,
2399 0x016c,
2400 0x01a0,
2401 0x01d4,
2402 0x01a0,
2403 0x01d4,
2404 0x0208,
2405 0x0208,
2406 0x023c,
2407 0x0186,
2408 0x01d4,
2409 0x0222,
2410 0x01d4,
2411 0x0222,
2412 0x0270,
2413 0x02be,
2414 0x0270,
2415 0x02be,
2416 0x030c,
2417 0x030c,
2418 0x035a,
2419 0x0036,
2420 0x006c,
2421 0x00a2,
2422 0x00d8,
2423 0x0144,
2424 0x01b0,
2425 0x01e6,
2426 0x021c,
2427 0x006c,
2428 0x00d8,
2429 0x0144,
2430 0x01b0,
2431 0x0288,
2432 0x0360,
2433 0x03cc,
2434 0x0438,
2435 0x00a2,
2436 0x0144,
2437 0x01e6,
2438 0x0288,
2439 0x03cc,
2440 0x0510,
2441 0x05b2,
2442 0x0654,
2443 0x00d8,
2444 0x01b0,
2445 0x0288,
2446 0x0360,
2447 0x0510,
2448 0x06c0,
2449 0x0798,
2450 0x0870,
2451 0x0018,
2452 0x0144,
2453 0x01b0,
2454 0x021c,
2455 0x01e6,
2456 0x0288,
2457 0x032a,
2458 0x01b0,
2459 0x021c,
2460 0x021c,
2461 0x0288,
2462 0x02f4,
2463 0x02f4,
2464 0x0360,
2465 0x0288,
2466 0x032a,
2467 0x032a,
2468 0x03cc,
2469 0x046e,
2470 0x046e,
2471 0x0510,
2472 0x021c,
2473 0x0288,
2474 0x02f4,
2475 0x0288,
2476 0x02f4,
2477 0x0360,
2478 0x03cc,
2479 0x0360,
2480 0x03cc,
2481 0x0438,
2482 0x0438,
2483 0x04a4,
2484 0x032a,
2485 0x03cc,
2486 0x046e,
2487 0x03cc,
2488 0x046e,
2489 0x0510,
2490 0x05b2,
2491 0x0510,
2492 0x05b2,
2493 0x0654,
2494 0x0654,
2495 0x06f6,
2496};
2497
2498static const u16 dot11lcn_iq_local_tbl_rev0[] = {
2499 0x0200,
2500 0x0300,
2501 0x0400,
2502 0x0600,
2503 0x0800,
2504 0x0b00,
2505 0x1000,
2506 0x1001,
2507 0x1002,
2508 0x1003,
2509 0x1004,
2510 0x1005,
2511 0x1006,
2512 0x1007,
2513 0x1707,
2514 0x2007,
2515 0x2d07,
2516 0x4007,
2517 0x0000,
2518 0x0000,
2519 0x0000,
2520 0x0000,
2521 0x0000,
2522 0x0000,
2523 0x0000,
2524 0x0000,
2525 0x0000,
2526 0x0000,
2527 0x0000,
2528 0x0000,
2529 0x0000,
2530 0x0000,
2531 0x0200,
2532 0x0300,
2533 0x0400,
2534 0x0600,
2535 0x0800,
2536 0x0b00,
2537 0x1000,
2538 0x1001,
2539 0x1002,
2540 0x1003,
2541 0x1004,
2542 0x1005,
2543 0x1006,
2544 0x1007,
2545 0x1707,
2546 0x2007,
2547 0x2d07,
2548 0x4007,
2549 0x0000,
2550 0x0000,
2551 0x0000,
2552 0x0000,
2553 0x0000,
2554 0x0000,
2555 0x0000,
2556 0x0000,
2557 0x0000,
2558 0x0000,
2559 0x0000,
2560 0x0000,
2561 0x0000,
2562 0x0000,
2563 0x0000,
2564 0x0000,
2565 0x0000,
2566 0x0000,
2567 0x0000,
2568 0x0000,
2569 0x0000,
2570 0x0000,
2571 0x0000,
2572 0x0000,
2573 0x0000,
2574 0x0000,
2575 0x0000,
2576 0x0000,
2577 0x0000,
2578 0x0000,
2579 0x0000,
2580 0x0000,
2581 0x0000,
2582 0x0000,
2583 0x0000,
2584 0x0000,
2585 0x0000,
2586 0x4000,
2587 0x0000,
2588 0x0000,
2589 0x0000,
2590 0x0000,
2591 0x0000,
2592 0x0000,
2593 0x0000,
2594 0x0000,
2595 0x0000,
2596 0x0000,
2597 0x0000,
2598 0x0000,
2599 0x0000,
2600 0x0000,
2601 0x0000,
2602 0x0000,
2603 0x0000,
2604 0x0000,
2605 0x0000,
2606 0x0000,
2607};
2608
2609static const u32 dot11lcn_papd_compdelta_tbl_rev0[] = {
2610 0x00080000,
2611 0x00080000,
2612 0x00080000,
2613 0x00080000,
2614 0x00080000,
2615 0x00080000,
2616 0x00080000,
2617 0x00080000,
2618 0x00080000,
2619 0x00080000,
2620 0x00080000,
2621 0x00080000,
2622 0x00080000,
2623 0x00080000,
2624 0x00080000,
2625 0x00080000,
2626 0x00080000,
2627 0x00080000,
2628 0x00080000,
2629 0x00080000,
2630 0x00080000,
2631 0x00080000,
2632 0x00080000,
2633 0x00080000,
2634 0x00080000,
2635 0x00080000,
2636 0x00080000,
2637 0x00080000,
2638 0x00080000,
2639 0x00080000,
2640 0x00080000,
2641 0x00080000,
2642 0x00080000,
2643 0x00080000,
2644 0x00080000,
2645 0x00080000,
2646 0x00080000,
2647 0x00080000,
2648 0x00080000,
2649 0x00080000,
2650 0x00080000,
2651 0x00080000,
2652 0x00080000,
2653 0x00080000,
2654 0x00080000,
2655 0x00080000,
2656 0x00080000,
2657 0x00080000,
2658 0x00080000,
2659 0x00080000,
2660 0x00080000,
2661 0x00080000,
2662 0x00080000,
2663 0x00080000,
2664 0x00080000,
2665 0x00080000,
2666 0x00080000,
2667 0x00080000,
2668 0x00080000,
2669 0x00080000,
2670 0x00080000,
2671 0x00080000,
2672 0x00080000,
2673 0x00080000,
2674 0x00080000,
2675 0x00080000,
2676 0x00080000,
2677 0x00080000,
2678 0x00080000,
2679 0x00080000,
2680 0x00080000,
2681 0x00080000,
2682 0x00080000,
2683 0x00080000,
2684 0x00080000,
2685 0x00080000,
2686 0x00080000,
2687 0x00080000,
2688 0x00080000,
2689 0x00080000,
2690 0x00080000,
2691 0x00080000,
2692 0x00080000,
2693 0x00080000,
2694 0x00080000,
2695 0x00080000,
2696 0x00080000,
2697 0x00080000,
2698 0x00080000,
2699 0x00080000,
2700 0x00080000,
2701 0x00080000,
2702 0x00080000,
2703 0x00080000,
2704 0x00080000,
2705 0x00080000,
2706 0x00080000,
2707 0x00080000,
2708 0x00080000,
2709 0x00080000,
2710 0x00080000,
2711 0x00080000,
2712 0x00080000,
2713 0x00080000,
2714 0x00080000,
2715 0x00080000,
2716 0x00080000,
2717 0x00080000,
2718 0x00080000,
2719 0x00080000,
2720 0x00080000,
2721 0x00080000,
2722 0x00080000,
2723 0x00080000,
2724 0x00080000,
2725 0x00080000,
2726 0x00080000,
2727 0x00080000,
2728 0x00080000,
2729 0x00080000,
2730 0x00080000,
2731 0x00080000,
2732 0x00080000,
2733 0x00080000,
2734 0x00080000,
2735 0x00080000,
2736 0x00080000,
2737 0x00080000,
2738 0x00080000,
2739 0x00080000,
2740 0x00080000,
2741 0x00080000,
2742 0x00080000,
2743 0x00080000,
2744 0x00080000,
2745 0x00080000,
2746 0x00080000,
2747 0x00080000,
2748 0x00080000,
2749 0x00080000,
2750 0x00080000,
2751 0x00080000,
2752 0x00080000,
2753 0x00080000,
2754 0x00080000,
2755 0x00080000,
2756 0x00080000,
2757 0x00080000,
2758 0x00080000,
2759 0x00080000,
2760 0x00080000,
2761 0x00080000,
2762 0x00080000,
2763 0x00080000,
2764 0x00080000,
2765 0x00080000,
2766 0x00080000,
2767 0x00080000,
2768 0x00080000,
2769 0x00080000,
2770};
2771
2772const struct phytbl_info dot11lcnphytbl_info_rev0[] = {
2773 {&dot11lcn_min_sig_sq_tbl_rev0,
2774 sizeof(dot11lcn_min_sig_sq_tbl_rev0) /
2775 sizeof(dot11lcn_min_sig_sq_tbl_rev0[0]), 2, 0, 16}
2776 ,
2777 {&dot11lcn_noise_scale_tbl_rev0,
2778 sizeof(dot11lcn_noise_scale_tbl_rev0) /
2779 sizeof(dot11lcn_noise_scale_tbl_rev0[0]), 1, 0, 16}
2780 ,
2781 {&dot11lcn_fltr_ctrl_tbl_rev0,
2782 sizeof(dot11lcn_fltr_ctrl_tbl_rev0) /
2783 sizeof(dot11lcn_fltr_ctrl_tbl_rev0[0]), 11, 0, 32}
2784 ,
2785 {&dot11lcn_ps_ctrl_tbl_rev0,
2786 sizeof(dot11lcn_ps_ctrl_tbl_rev0) /
2787 sizeof(dot11lcn_ps_ctrl_tbl_rev0[0]), 12, 0, 32}
2788 ,
2789 {&dot11lcn_gain_idx_tbl_rev0,
2790 sizeof(dot11lcn_gain_idx_tbl_rev0) /
2791 sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
2792 ,
2793 {&dot11lcn_aux_gain_idx_tbl_rev0,
2794 sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
2795 sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
2796 ,
2797 {&dot11lcn_sw_ctrl_tbl_rev0,
2798 sizeof(dot11lcn_sw_ctrl_tbl_rev0) /
2799 sizeof(dot11lcn_sw_ctrl_tbl_rev0[0]), 15, 0, 16}
2800 ,
2801 {&dot11lcn_nf_table_rev0,
2802 sizeof(dot11lcn_nf_table_rev0) / sizeof(dot11lcn_nf_table_rev0[0]), 16,
2803 0, 8}
2804 ,
2805 {&dot11lcn_gain_val_tbl_rev0,
2806 sizeof(dot11lcn_gain_val_tbl_rev0) /
2807 sizeof(dot11lcn_gain_val_tbl_rev0[0]), 17, 0, 8}
2808 ,
2809 {&dot11lcn_gain_tbl_rev0,
2810 sizeof(dot11lcn_gain_tbl_rev0) / sizeof(dot11lcn_gain_tbl_rev0[0]), 18,
2811 0, 32}
2812 ,
2813 {&dot11lcn_spur_tbl_rev0,
2814 sizeof(dot11lcn_spur_tbl_rev0) / sizeof(dot11lcn_spur_tbl_rev0[0]), 20,
2815 0, 8}
2816 ,
2817 {&dot11lcn_unsup_mcs_tbl_rev0,
2818 sizeof(dot11lcn_unsup_mcs_tbl_rev0) /
2819 sizeof(dot11lcn_unsup_mcs_tbl_rev0[0]), 23, 0, 16}
2820 ,
2821 {&dot11lcn_iq_local_tbl_rev0,
2822 sizeof(dot11lcn_iq_local_tbl_rev0) /
2823 sizeof(dot11lcn_iq_local_tbl_rev0[0]), 0, 0, 16}
2824 ,
2825 {&dot11lcn_papd_compdelta_tbl_rev0,
2826 sizeof(dot11lcn_papd_compdelta_tbl_rev0) /
2827 sizeof(dot11lcn_papd_compdelta_tbl_rev0[0]), 24, 0, 32}
2828 ,
2829};
2830
2831const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313 = {
2832 &dot11lcn_sw_ctrl_tbl_4313_rev0,
2833 sizeof(dot11lcn_sw_ctrl_tbl_4313_rev0) /
2834 sizeof(dot11lcn_sw_ctrl_tbl_4313_rev0[0]), 15, 0, 16
2835};
2836
2837const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_epa = {
2838 &dot11lcn_sw_ctrl_tbl_4313_epa_rev0,
2839 sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0) /
2840 sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0[0]), 15, 0, 16
2841};
2842
2843const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_bt_epa = {
2844 &dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo,
2845 sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo) /
2846 sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[0]), 15, 0, 16
2847};
2848
2849const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 = {
2850 &dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0,
2851 sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0) /
2852 sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[0]), 15, 0, 16
2853};
2854
2855const u32 dot11lcnphytbl_info_sz_rev0 =
2856 sizeof(dot11lcnphytbl_info_rev0) / sizeof(dot11lcnphytbl_info_rev0[0]);
2857
2858const struct lcnphy_tx_gain_tbl_entry
2859dot11lcnphy_2GHz_extPA_gaintable_rev0[128] = {
2860 {3, 0, 31, 0, 72},
2861 {3, 0, 31, 0, 70},
2862 {3, 0, 31, 0, 68},
2863 {3, 0, 30, 0, 67},
2864 {3, 0, 29, 0, 68},
2865 {3, 0, 28, 0, 68},
2866 {3, 0, 27, 0, 69},
2867 {3, 0, 26, 0, 70},
2868 {3, 0, 25, 0, 70},
2869 {3, 0, 24, 0, 71},
2870 {3, 0, 23, 0, 72},
2871 {3, 0, 23, 0, 70},
2872 {3, 0, 22, 0, 71},
2873 {3, 0, 21, 0, 72},
2874 {3, 0, 21, 0, 70},
2875 {3, 0, 21, 0, 68},
2876 {3, 0, 21, 0, 66},
2877 {3, 0, 21, 0, 64},
2878 {3, 0, 21, 0, 63},
2879 {3, 0, 20, 0, 64},
2880 {3, 0, 19, 0, 65},
2881 {3, 0, 19, 0, 64},
2882 {3, 0, 18, 0, 65},
2883 {3, 0, 18, 0, 64},
2884 {3, 0, 17, 0, 65},
2885 {3, 0, 17, 0, 64},
2886 {3, 0, 16, 0, 65},
2887 {3, 0, 16, 0, 64},
2888 {3, 0, 16, 0, 62},
2889 {3, 0, 16, 0, 60},
2890 {3, 0, 16, 0, 58},
2891 {3, 0, 15, 0, 61},
2892 {3, 0, 15, 0, 59},
2893 {3, 0, 14, 0, 61},
2894 {3, 0, 14, 0, 60},
2895 {3, 0, 14, 0, 58},
2896 {3, 0, 13, 0, 60},
2897 {3, 0, 13, 0, 59},
2898 {3, 0, 12, 0, 62},
2899 {3, 0, 12, 0, 60},
2900 {3, 0, 12, 0, 58},
2901 {3, 0, 11, 0, 62},
2902 {3, 0, 11, 0, 60},
2903 {3, 0, 11, 0, 59},
2904 {3, 0, 11, 0, 57},
2905 {3, 0, 10, 0, 61},
2906 {3, 0, 10, 0, 59},
2907 {3, 0, 10, 0, 57},
2908 {3, 0, 9, 0, 62},
2909 {3, 0, 9, 0, 60},
2910 {3, 0, 9, 0, 58},
2911 {3, 0, 9, 0, 57},
2912 {3, 0, 8, 0, 62},
2913 {3, 0, 8, 0, 60},
2914 {3, 0, 8, 0, 58},
2915 {3, 0, 8, 0, 57},
2916 {3, 0, 8, 0, 55},
2917 {3, 0, 7, 0, 61},
2918 {3, 0, 7, 0, 60},
2919 {3, 0, 7, 0, 58},
2920 {3, 0, 7, 0, 56},
2921 {3, 0, 7, 0, 55},
2922 {3, 0, 6, 0, 62},
2923 {3, 0, 6, 0, 60},
2924 {3, 0, 6, 0, 58},
2925 {3, 0, 6, 0, 57},
2926 {3, 0, 6, 0, 55},
2927 {3, 0, 6, 0, 54},
2928 {3, 0, 6, 0, 52},
2929 {3, 0, 5, 0, 61},
2930 {3, 0, 5, 0, 59},
2931 {3, 0, 5, 0, 57},
2932 {3, 0, 5, 0, 56},
2933 {3, 0, 5, 0, 54},
2934 {3, 0, 5, 0, 53},
2935 {3, 0, 5, 0, 51},
2936 {3, 0, 4, 0, 62},
2937 {3, 0, 4, 0, 60},
2938 {3, 0, 4, 0, 58},
2939 {3, 0, 4, 0, 57},
2940 {3, 0, 4, 0, 55},
2941 {3, 0, 4, 0, 54},
2942 {3, 0, 4, 0, 52},
2943 {3, 0, 4, 0, 51},
2944 {3, 0, 4, 0, 49},
2945 {3, 0, 4, 0, 48},
2946 {3, 0, 4, 0, 46},
2947 {3, 0, 3, 0, 60},
2948 {3, 0, 3, 0, 58},
2949 {3, 0, 3, 0, 57},
2950 {3, 0, 3, 0, 55},
2951 {3, 0, 3, 0, 54},
2952 {3, 0, 3, 0, 52},
2953 {3, 0, 3, 0, 51},
2954 {3, 0, 3, 0, 49},
2955 {3, 0, 3, 0, 48},
2956 {3, 0, 3, 0, 46},
2957 {3, 0, 3, 0, 45},
2958 {3, 0, 3, 0, 44},
2959 {3, 0, 3, 0, 43},
2960 {3, 0, 3, 0, 41},
2961 {3, 0, 2, 0, 61},
2962 {3, 0, 2, 0, 59},
2963 {3, 0, 2, 0, 57},
2964 {3, 0, 2, 0, 56},
2965 {3, 0, 2, 0, 54},
2966 {3, 0, 2, 0, 53},
2967 {3, 0, 2, 0, 51},
2968 {3, 0, 2, 0, 50},
2969 {3, 0, 2, 0, 48},
2970 {3, 0, 2, 0, 47},
2971 {3, 0, 2, 0, 46},
2972 {3, 0, 2, 0, 44},
2973 {3, 0, 2, 0, 43},
2974 {3, 0, 2, 0, 42},
2975 {3, 0, 2, 0, 41},
2976 {3, 0, 2, 0, 39},
2977 {3, 0, 2, 0, 38},
2978 {3, 0, 2, 0, 37},
2979 {3, 0, 2, 0, 36},
2980 {3, 0, 2, 0, 35},
2981 {3, 0, 2, 0, 34},
2982 {3, 0, 2, 0, 33},
2983 {3, 0, 2, 0, 32},
2984 {3, 0, 1, 0, 63},
2985 {3, 0, 1, 0, 61},
2986 {3, 0, 1, 0, 59},
2987 {3, 0, 1, 0, 57},
2988};
2989
2990const struct lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_gaintable_rev0[128] = {
2991 {7, 0, 31, 0, 72},
2992 {7, 0, 31, 0, 70},
2993 {7, 0, 31, 0, 68},
2994 {7, 0, 30, 0, 67},
2995 {7, 0, 29, 0, 68},
2996 {7, 0, 28, 0, 68},
2997 {7, 0, 27, 0, 69},
2998 {7, 0, 26, 0, 70},
2999 {7, 0, 25, 0, 70},
3000 {7, 0, 24, 0, 71},
3001 {7, 0, 23, 0, 72},
3002 {7, 0, 23, 0, 70},
3003 {7, 0, 22, 0, 71},
3004 {7, 0, 21, 0, 72},
3005 {7, 0, 21, 0, 70},
3006 {7, 0, 21, 0, 68},
3007 {7, 0, 21, 0, 66},
3008 {7, 0, 21, 0, 64},
3009 {7, 0, 21, 0, 63},
3010 {7, 0, 20, 0, 64},
3011 {7, 0, 19, 0, 65},
3012 {7, 0, 19, 0, 64},
3013 {7, 0, 18, 0, 65},
3014 {7, 0, 18, 0, 64},
3015 {7, 0, 17, 0, 65},
3016 {7, 0, 17, 0, 64},
3017 {7, 0, 16, 0, 65},
3018 {7, 0, 16, 0, 64},
3019 {7, 0, 16, 0, 62},
3020 {7, 0, 16, 0, 60},
3021 {7, 0, 16, 0, 58},
3022 {7, 0, 15, 0, 61},
3023 {7, 0, 15, 0, 59},
3024 {7, 0, 14, 0, 61},
3025 {7, 0, 14, 0, 60},
3026 {7, 0, 14, 0, 58},
3027 {7, 0, 13, 0, 60},
3028 {7, 0, 13, 0, 59},
3029 {7, 0, 12, 0, 62},
3030 {7, 0, 12, 0, 60},
3031 {7, 0, 12, 0, 58},
3032 {7, 0, 11, 0, 62},
3033 {7, 0, 11, 0, 60},
3034 {7, 0, 11, 0, 59},
3035 {7, 0, 11, 0, 57},
3036 {7, 0, 10, 0, 61},
3037 {7, 0, 10, 0, 59},
3038 {7, 0, 10, 0, 57},
3039 {7, 0, 9, 0, 62},
3040 {7, 0, 9, 0, 60},
3041 {7, 0, 9, 0, 58},
3042 {7, 0, 9, 0, 57},
3043 {7, 0, 8, 0, 62},
3044 {7, 0, 8, 0, 60},
3045 {7, 0, 8, 0, 58},
3046 {7, 0, 8, 0, 57},
3047 {7, 0, 8, 0, 55},
3048 {7, 0, 7, 0, 61},
3049 {7, 0, 7, 0, 60},
3050 {7, 0, 7, 0, 58},
3051 {7, 0, 7, 0, 56},
3052 {7, 0, 7, 0, 55},
3053 {7, 0, 6, 0, 62},
3054 {7, 0, 6, 0, 60},
3055 {7, 0, 6, 0, 58},
3056 {7, 0, 6, 0, 57},
3057 {7, 0, 6, 0, 55},
3058 {7, 0, 6, 0, 54},
3059 {7, 0, 6, 0, 52},
3060 {7, 0, 5, 0, 61},
3061 {7, 0, 5, 0, 59},
3062 {7, 0, 5, 0, 57},
3063 {7, 0, 5, 0, 56},
3064 {7, 0, 5, 0, 54},
3065 {7, 0, 5, 0, 53},
3066 {7, 0, 5, 0, 51},
3067 {7, 0, 4, 0, 62},
3068 {7, 0, 4, 0, 60},
3069 {7, 0, 4, 0, 58},
3070 {7, 0, 4, 0, 57},
3071 {7, 0, 4, 0, 55},
3072 {7, 0, 4, 0, 54},
3073 {7, 0, 4, 0, 52},
3074 {7, 0, 4, 0, 51},
3075 {7, 0, 4, 0, 49},
3076 {7, 0, 4, 0, 48},
3077 {7, 0, 4, 0, 46},
3078 {7, 0, 3, 0, 60},
3079 {7, 0, 3, 0, 58},
3080 {7, 0, 3, 0, 57},
3081 {7, 0, 3, 0, 55},
3082 {7, 0, 3, 0, 54},
3083 {7, 0, 3, 0, 52},
3084 {7, 0, 3, 0, 51},
3085 {7, 0, 3, 0, 49},
3086 {7, 0, 3, 0, 48},
3087 {7, 0, 3, 0, 46},
3088 {7, 0, 3, 0, 45},
3089 {7, 0, 3, 0, 44},
3090 {7, 0, 3, 0, 43},
3091 {7, 0, 3, 0, 41},
3092 {7, 0, 2, 0, 61},
3093 {7, 0, 2, 0, 59},
3094 {7, 0, 2, 0, 57},
3095 {7, 0, 2, 0, 56},
3096 {7, 0, 2, 0, 54},
3097 {7, 0, 2, 0, 53},
3098 {7, 0, 2, 0, 51},
3099 {7, 0, 2, 0, 50},
3100 {7, 0, 2, 0, 48},
3101 {7, 0, 2, 0, 47},
3102 {7, 0, 2, 0, 46},
3103 {7, 0, 2, 0, 44},
3104 {7, 0, 2, 0, 43},
3105 {7, 0, 2, 0, 42},
3106 {7, 0, 2, 0, 41},
3107 {7, 0, 2, 0, 39},
3108 {7, 0, 2, 0, 38},
3109 {7, 0, 2, 0, 37},
3110 {7, 0, 2, 0, 36},
3111 {7, 0, 2, 0, 35},
3112 {7, 0, 2, 0, 34},
3113 {7, 0, 2, 0, 33},
3114 {7, 0, 2, 0, 32},
3115 {7, 0, 1, 0, 63},
3116 {7, 0, 1, 0, 61},
3117 {7, 0, 1, 0, 59},
3118 {7, 0, 1, 0, 57},
3119};
3120
3121const struct lcnphy_tx_gain_tbl_entry dot11lcnphy_5GHz_gaintable_rev0[128] = {
3122 {255, 255, 0xf0, 0, 152},
3123 {255, 255, 0xf0, 0, 147},
3124 {255, 255, 0xf0, 0, 143},
3125 {255, 255, 0xf0, 0, 139},
3126 {255, 255, 0xf0, 0, 135},
3127 {255, 255, 0xf0, 0, 131},
3128 {255, 255, 0xf0, 0, 128},
3129 {255, 255, 0xf0, 0, 124},
3130 {255, 255, 0xf0, 0, 121},
3131 {255, 255, 0xf0, 0, 117},
3132 {255, 255, 0xf0, 0, 114},
3133 {255, 255, 0xf0, 0, 111},
3134 {255, 255, 0xf0, 0, 107},
3135 {255, 255, 0xf0, 0, 104},
3136 {255, 255, 0xf0, 0, 101},
3137 {255, 255, 0xf0, 0, 99},
3138 {255, 255, 0xf0, 0, 96},
3139 {255, 255, 0xf0, 0, 93},
3140 {255, 255, 0xf0, 0, 90},
3141 {255, 255, 0xf0, 0, 88},
3142 {255, 255, 0xf0, 0, 85},
3143 {255, 255, 0xf0, 0, 83},
3144 {255, 255, 0xf0, 0, 81},
3145 {255, 255, 0xf0, 0, 78},
3146 {255, 255, 0xf0, 0, 76},
3147 {255, 255, 0xf0, 0, 74},
3148 {255, 255, 0xf0, 0, 72},
3149 {255, 255, 0xf0, 0, 70},
3150 {255, 255, 0xf0, 0, 68},
3151 {255, 255, 0xf0, 0, 66},
3152 {255, 255, 0xf0, 0, 64},
3153 {255, 248, 0xf0, 0, 64},
3154 {255, 241, 0xf0, 0, 64},
3155 {255, 251, 0xe0, 0, 64},
3156 {255, 244, 0xe0, 0, 64},
3157 {255, 254, 0xd0, 0, 64},
3158 {255, 246, 0xd0, 0, 64},
3159 {255, 239, 0xd0, 0, 64},
3160 {255, 249, 0xc0, 0, 64},
3161 {255, 242, 0xc0, 0, 64},
3162 {255, 255, 0xb0, 0, 64},
3163 {255, 248, 0xb0, 0, 64},
3164 {255, 241, 0xb0, 0, 64},
3165 {255, 254, 0xa0, 0, 64},
3166 {255, 246, 0xa0, 0, 64},
3167 {255, 239, 0xa0, 0, 64},
3168 {255, 255, 0x90, 0, 64},
3169 {255, 248, 0x90, 0, 64},
3170 {255, 241, 0x90, 0, 64},
3171 {255, 234, 0x90, 0, 64},
3172 {255, 255, 0x80, 0, 64},
3173 {255, 248, 0x80, 0, 64},
3174 {255, 241, 0x80, 0, 64},
3175 {255, 234, 0x80, 0, 64},
3176 {255, 255, 0x70, 0, 64},
3177 {255, 248, 0x70, 0, 64},
3178 {255, 241, 0x70, 0, 64},
3179 {255, 234, 0x70, 0, 64},
3180 {255, 227, 0x70, 0, 64},
3181 {255, 221, 0x70, 0, 64},
3182 {255, 215, 0x70, 0, 64},
3183 {255, 208, 0x70, 0, 64},
3184 {255, 203, 0x70, 0, 64},
3185 {255, 197, 0x70, 0, 64},
3186 {255, 255, 0x60, 0, 64},
3187 {255, 248, 0x60, 0, 64},
3188 {255, 241, 0x60, 0, 64},
3189 {255, 234, 0x60, 0, 64},
3190 {255, 227, 0x60, 0, 64},
3191 {255, 221, 0x60, 0, 64},
3192 {255, 255, 0x50, 0, 64},
3193 {255, 248, 0x50, 0, 64},
3194 {255, 241, 0x50, 0, 64},
3195 {255, 234, 0x50, 0, 64},
3196 {255, 227, 0x50, 0, 64},
3197 {255, 221, 0x50, 0, 64},
3198 {255, 215, 0x50, 0, 64},
3199 {255, 208, 0x50, 0, 64},
3200 {255, 255, 0x40, 0, 64},
3201 {255, 248, 0x40, 0, 64},
3202 {255, 241, 0x40, 0, 64},
3203 {255, 234, 0x40, 0, 64},
3204 {255, 227, 0x40, 0, 64},
3205 {255, 221, 0x40, 0, 64},
3206 {255, 215, 0x40, 0, 64},
3207 {255, 208, 0x40, 0, 64},
3208 {255, 203, 0x40, 0, 64},
3209 {255, 197, 0x40, 0, 64},
3210 {255, 255, 0x30, 0, 64},
3211 {255, 248, 0x30, 0, 64},
3212 {255, 241, 0x30, 0, 64},
3213 {255, 234, 0x30, 0, 64},
3214 {255, 227, 0x30, 0, 64},
3215 {255, 221, 0x30, 0, 64},
3216 {255, 215, 0x30, 0, 64},
3217 {255, 208, 0x30, 0, 64},
3218 {255, 203, 0x30, 0, 64},
3219 {255, 197, 0x30, 0, 64},
3220 {255, 191, 0x30, 0, 64},
3221 {255, 186, 0x30, 0, 64},
3222 {255, 181, 0x30, 0, 64},
3223 {255, 175, 0x30, 0, 64},
3224 {255, 255, 0x20, 0, 64},
3225 {255, 248, 0x20, 0, 64},
3226 {255, 241, 0x20, 0, 64},
3227 {255, 234, 0x20, 0, 64},
3228 {255, 227, 0x20, 0, 64},
3229 {255, 221, 0x20, 0, 64},
3230 {255, 215, 0x20, 0, 64},
3231 {255, 208, 0x20, 0, 64},
3232 {255, 203, 0x20, 0, 64},
3233 {255, 197, 0x20, 0, 64},
3234 {255, 191, 0x20, 0, 64},
3235 {255, 186, 0x20, 0, 64},
3236 {255, 181, 0x20, 0, 64},
3237 {255, 175, 0x20, 0, 64},
3238 {255, 170, 0x20, 0, 64},
3239 {255, 166, 0x20, 0, 64},
3240 {255, 161, 0x20, 0, 64},
3241 {255, 156, 0x20, 0, 64},
3242 {255, 152, 0x20, 0, 64},
3243 {255, 148, 0x20, 0, 64},
3244 {255, 143, 0x20, 0, 64},
3245 {255, 139, 0x20, 0, 64},
3246 {255, 135, 0x20, 0, 64},
3247 {255, 132, 0x20, 0, 64},
3248 {255, 255, 0x10, 0, 64},
3249 {255, 248, 0x10, 0, 64},
3250};
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.h b/drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.h
deleted file mode 100644
index 5f75e16bf5a..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <types.h>
18#include "phy_int.h"
19
20extern const struct phytbl_info dot11lcnphytbl_rx_gain_info_rev0[];
21extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev0;
22extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313;
23extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_epa;
24extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_epa_combo;
25extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_bt_epa;
26extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250;
27
28extern const struct phytbl_info dot11lcnphytbl_info_rev0[];
29extern const u32 dot11lcnphytbl_info_sz_rev0;
30
31extern const struct phytbl_info dot11lcnphytbl_rx_gain_info_2G_rev2[];
32extern const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
33
34extern const struct phytbl_info dot11lcnphytbl_rx_gain_info_5G_rev2[];
35extern const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
36
37extern const struct phytbl_info dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[];
38
39extern const struct phytbl_info dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[];
40
41struct lcnphy_tx_gain_tbl_entry {
42 unsigned char gm;
43 unsigned char pga;
44 unsigned char pad;
45 unsigned char dac;
46 unsigned char bb_mult;
47};
48
49extern const struct lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_gaintable_rev0[];
50
51extern const struct
52lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[];
53
54extern const struct lcnphy_tx_gain_tbl_entry dot11lcnphy_5GHz_gaintable_rev0[];
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.c b/drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.c
deleted file mode 100644
index dbf50ef6cd7..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.c
+++ /dev/null
@@ -1,10630 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <types.h>
18#include "phytbl_n.h"
19
20static const u32 frame_struct_rev0[] = {
21 0x08004a04,
22 0x00100000,
23 0x01000a05,
24 0x00100020,
25 0x09804506,
26 0x00100030,
27 0x09804507,
28 0x00100030,
29 0x00000000,
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x08004a0c,
38 0x00100004,
39 0x01000a0d,
40 0x00100024,
41 0x0980450e,
42 0x00100034,
43 0x0980450f,
44 0x00100034,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x00000000,
49 0x00000000,
50 0x00000000,
51 0x00000000,
52 0x00000000,
53 0x00000a04,
54 0x00100000,
55 0x11008a05,
56 0x00100020,
57 0x1980c506,
58 0x00100030,
59 0x21810506,
60 0x00100030,
61 0x21810506,
62 0x00100030,
63 0x01800504,
64 0x00100030,
65 0x11808505,
66 0x00100030,
67 0x29814507,
68 0x01100030,
69 0x00000a04,
70 0x00100000,
71 0x11008a05,
72 0x00100020,
73 0x21810506,
74 0x00100030,
75 0x21810506,
76 0x00100030,
77 0x29814507,
78 0x01100030,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000a0c,
86 0x00100008,
87 0x11008a0d,
88 0x00100028,
89 0x1980c50e,
90 0x00100038,
91 0x2181050e,
92 0x00100038,
93 0x2181050e,
94 0x00100038,
95 0x0180050c,
96 0x00100038,
97 0x1180850d,
98 0x00100038,
99 0x2981450f,
100 0x01100038,
101 0x00000a0c,
102 0x00100008,
103 0x11008a0d,
104 0x00100028,
105 0x2181050e,
106 0x00100038,
107 0x2181050e,
108 0x00100038,
109 0x2981450f,
110 0x01100038,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x00000000,
115 0x00000000,
116 0x00000000,
117 0x08004a04,
118 0x00100000,
119 0x01000a05,
120 0x00100020,
121 0x1980c506,
122 0x00100030,
123 0x1980c506,
124 0x00100030,
125 0x11808504,
126 0x00100030,
127 0x3981ca05,
128 0x00100030,
129 0x29814507,
130 0x01100030,
131 0x00000000,
132 0x00000000,
133 0x10008a04,
134 0x00100000,
135 0x3981ca05,
136 0x00100030,
137 0x1980c506,
138 0x00100030,
139 0x29814507,
140 0x01100030,
141 0x00000000,
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x08004a0c,
150 0x00100008,
151 0x01000a0d,
152 0x00100028,
153 0x1980c50e,
154 0x00100038,
155 0x1980c50e,
156 0x00100038,
157 0x1180850c,
158 0x00100038,
159 0x3981ca0d,
160 0x00100038,
161 0x2981450f,
162 0x01100038,
163 0x00000000,
164 0x00000000,
165 0x10008a0c,
166 0x00100008,
167 0x3981ca0d,
168 0x00100038,
169 0x1980c50e,
170 0x00100038,
171 0x2981450f,
172 0x01100038,
173 0x00000000,
174 0x00000000,
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x40021404,
182 0x00100000,
183 0x02001405,
184 0x00100040,
185 0x0b004a06,
186 0x01900060,
187 0x13008a06,
188 0x01900060,
189 0x13008a06,
190 0x01900060,
191 0x43020a04,
192 0x00100060,
193 0x1b00ca05,
194 0x00100060,
195 0x23010a07,
196 0x01500060,
197 0x40021404,
198 0x00100000,
199 0x1a00d405,
200 0x00100040,
201 0x13008a06,
202 0x01900060,
203 0x13008a06,
204 0x01900060,
205 0x23010a07,
206 0x01500060,
207 0x00000000,
208 0x00000000,
209 0x00000000,
210 0x00000000,
211 0x00000000,
212 0x00000000,
213 0x4002140c,
214 0x00100010,
215 0x0200140d,
216 0x00100050,
217 0x0b004a0e,
218 0x01900070,
219 0x13008a0e,
220 0x01900070,
221 0x13008a0e,
222 0x01900070,
223 0x43020a0c,
224 0x00100070,
225 0x1b00ca0d,
226 0x00100070,
227 0x23010a0f,
228 0x01500070,
229 0x4002140c,
230 0x00100010,
231 0x1a00d40d,
232 0x00100050,
233 0x13008a0e,
234 0x01900070,
235 0x13008a0e,
236 0x01900070,
237 0x23010a0f,
238 0x01500070,
239 0x00000000,
240 0x00000000,
241 0x00000000,
242 0x00000000,
243 0x00000000,
244 0x00000000,
245 0x50029404,
246 0x00100000,
247 0x32019405,
248 0x00100040,
249 0x0b004a06,
250 0x01900060,
251 0x0b004a06,
252 0x01900060,
253 0x5b02ca04,
254 0x00100060,
255 0x3b01d405,
256 0x00100060,
257 0x23010a07,
258 0x01500060,
259 0x00000000,
260 0x00000000,
261 0x5802d404,
262 0x00100000,
263 0x3b01d405,
264 0x00100060,
265 0x0b004a06,
266 0x01900060,
267 0x23010a07,
268 0x01500060,
269 0x00000000,
270 0x00000000,
271 0x00000000,
272 0x00000000,
273 0x00000000,
274 0x00000000,
275 0x00000000,
276 0x00000000,
277 0x5002940c,
278 0x00100010,
279 0x3201940d,
280 0x00100050,
281 0x0b004a0e,
282 0x01900070,
283 0x0b004a0e,
284 0x01900070,
285 0x5b02ca0c,
286 0x00100070,
287 0x3b01d40d,
288 0x00100070,
289 0x23010a0f,
290 0x01500070,
291 0x00000000,
292 0x00000000,
293 0x5802d40c,
294 0x00100010,
295 0x3b01d40d,
296 0x00100070,
297 0x0b004a0e,
298 0x01900070,
299 0x23010a0f,
300 0x01500070,
301 0x00000000,
302 0x00000000,
303 0x00000000,
304 0x00000000,
305 0x00000000,
306 0x00000000,
307 0x00000000,
308 0x00000000,
309 0x40021404,
310 0x000f4800,
311 0x62031405,
312 0x00100040,
313 0x53028a06,
314 0x01900060,
315 0x53028a07,
316 0x01900060,
317 0x00000000,
318 0x00000000,
319 0x00000000,
320 0x00000000,
321 0x00000000,
322 0x00000000,
323 0x00000000,
324 0x00000000,
325 0x4002140c,
326 0x000f4808,
327 0x6203140d,
328 0x00100048,
329 0x53028a0e,
330 0x01900068,
331 0x53028a0f,
332 0x01900068,
333 0x00000000,
334 0x00000000,
335 0x00000000,
336 0x00000000,
337 0x00000000,
338 0x00000000,
339 0x00000000,
340 0x00000000,
341 0x00000a0c,
342 0x00100004,
343 0x11008a0d,
344 0x00100024,
345 0x1980c50e,
346 0x00100034,
347 0x2181050e,
348 0x00100034,
349 0x2181050e,
350 0x00100034,
351 0x0180050c,
352 0x00100038,
353 0x1180850d,
354 0x00100038,
355 0x1181850d,
356 0x00100038,
357 0x2981450f,
358 0x01100038,
359 0x00000000,
360 0x00000000,
361 0x00000000,
362 0x00000000,
363 0x00000000,
364 0x00000000,
365 0x00000000,
366 0x00000000,
367 0x00000000,
368 0x00000000,
369 0x00000000,
370 0x00000000,
371 0x00000000,
372 0x00000000,
373 0x00000a0c,
374 0x00100008,
375 0x11008a0d,
376 0x00100028,
377 0x2181050e,
378 0x00100038,
379 0x2181050e,
380 0x00100038,
381 0x1181850d,
382 0x00100038,
383 0x2981450f,
384 0x01100038,
385 0x00000000,
386 0x00000000,
387 0x00000000,
388 0x00000000,
389 0x00000000,
390 0x00000000,
391 0x00000000,
392 0x00000000,
393 0x00000000,
394 0x00000000,
395 0x00000000,
396 0x00000000,
397 0x00000000,
398 0x00000000,
399 0x00000000,
400 0x00000000,
401 0x00000000,
402 0x00000000,
403 0x00000000,
404 0x00000000,
405 0x08004a04,
406 0x00100000,
407 0x01000a05,
408 0x00100020,
409 0x0180c506,
410 0x00100030,
411 0x0180c506,
412 0x00100030,
413 0x2180c50c,
414 0x00100030,
415 0x49820a0d,
416 0x0016a130,
417 0x41824a0d,
418 0x0016a130,
419 0x2981450f,
420 0x01100030,
421 0x00000000,
422 0x00000000,
423 0x00000000,
424 0x00000000,
425 0x00000000,
426 0x00000000,
427 0x00000000,
428 0x00000000,
429 0x00000000,
430 0x00000000,
431 0x00000000,
432 0x00000000,
433 0x00000000,
434 0x00000000,
435 0x00000000,
436 0x00000000,
437 0x2000ca0c,
438 0x00100000,
439 0x49820a0d,
440 0x0016a130,
441 0x1980c50e,
442 0x00100030,
443 0x41824a0d,
444 0x0016a130,
445 0x2981450f,
446 0x01100030,
447 0x00000000,
448 0x00000000,
449 0x00000000,
450 0x00000000,
451 0x00000000,
452 0x00000000,
453 0x00000000,
454 0x00000000,
455 0x00000000,
456 0x00000000,
457 0x00000000,
458 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x4002140c,
470 0x00100008,
471 0x0200140d,
472 0x00100048,
473 0x0b004a0e,
474 0x01900068,
475 0x13008a0e,
476 0x01900068,
477 0x13008a0e,
478 0x01900068,
479 0x43020a0c,
480 0x00100070,
481 0x1b00ca0d,
482 0x00100070,
483 0x1b014a0d,
484 0x00100070,
485 0x23010a0f,
486 0x01500070,
487 0x00000000,
488 0x00000000,
489 0x00000000,
490 0x00000000,
491 0x00000000,
492 0x00000000,
493 0x00000000,
494 0x00000000,
495 0x00000000,
496 0x00000000,
497 0x00000000,
498 0x00000000,
499 0x00000000,
500 0x00000000,
501 0x4002140c,
502 0x00100010,
503 0x1a00d40d,
504 0x00100050,
505 0x13008a0e,
506 0x01900070,
507 0x13008a0e,
508 0x01900070,
509 0x1b014a0d,
510 0x00100070,
511 0x23010a0f,
512 0x01500070,
513 0x00000000,
514 0x00000000,
515 0x00000000,
516 0x00000000,
517 0x00000000,
518 0x00000000,
519 0x00000000,
520 0x00000000,
521 0x00000000,
522 0x00000000,
523 0x00000000,
524 0x00000000,
525 0x00000000,
526 0x00000000,
527 0x00000000,
528 0x00000000,
529 0x00000000,
530 0x00000000,
531 0x00000000,
532 0x00000000,
533 0x50029404,
534 0x00100000,
535 0x32019405,
536 0x00100040,
537 0x03004a06,
538 0x01900060,
539 0x03004a06,
540 0x01900060,
541 0x6b030a0c,
542 0x00100060,
543 0x4b02140d,
544 0x0016a160,
545 0x4302540d,
546 0x0016a160,
547 0x23010a0f,
548 0x01500060,
549 0x00000000,
550 0x00000000,
551 0x00000000,
552 0x00000000,
553 0x00000000,
554 0x00000000,
555 0x00000000,
556 0x00000000,
557 0x00000000,
558 0x00000000,
559 0x00000000,
560 0x00000000,
561 0x00000000,
562 0x00000000,
563 0x00000000,
564 0x00000000,
565 0x6b03140c,
566 0x00100060,
567 0x4b02140d,
568 0x0016a160,
569 0x0b004a0e,
570 0x01900060,
571 0x4302540d,
572 0x0016a160,
573 0x23010a0f,
574 0x01500060,
575 0x00000000,
576 0x00000000,
577 0x00000000,
578 0x00000000,
579 0x00000000,
580 0x00000000,
581 0x00000000,
582 0x00000000,
583 0x00000000,
584 0x00000000,
585 0x00000000,
586 0x00000000,
587 0x00000000,
588 0x00000000,
589 0x00000000,
590 0x00000000,
591 0x00000000,
592 0x00000000,
593 0x00000000,
594 0x00000000,
595 0x00000000,
596 0x00000000,
597 0x40021404,
598 0x00100000,
599 0x1a00d405,
600 0x00100040,
601 0x53028a06,
602 0x01900060,
603 0x5b02ca06,
604 0x01900060,
605 0x5b02ca06,
606 0x01900060,
607 0x43020a04,
608 0x00100060,
609 0x1b00ca05,
610 0x00100060,
611 0x53028a07,
612 0x0190c060,
613 0x00000000,
614 0x00000000,
615 0x00000000,
616 0x00000000,
617 0x00000000,
618 0x00000000,
619 0x00000000,
620 0x00000000,
621 0x00000000,
622 0x00000000,
623 0x00000000,
624 0x00000000,
625 0x00000000,
626 0x00000000,
627 0x00000000,
628 0x00000000,
629 0x4002140c,
630 0x00100010,
631 0x1a00d40d,
632 0x00100050,
633 0x53028a0e,
634 0x01900070,
635 0x5b02ca0e,
636 0x01900070,
637 0x5b02ca0e,
638 0x01900070,
639 0x43020a0c,
640 0x00100070,
641 0x1b00ca0d,
642 0x00100070,
643 0x53028a0f,
644 0x0190c070,
645 0x00000000,
646 0x00000000,
647 0x00000000,
648 0x00000000,
649 0x00000000,
650 0x00000000,
651 0x00000000,
652 0x00000000,
653 0x00000000,
654 0x00000000,
655 0x00000000,
656 0x00000000,
657 0x00000000,
658 0x00000000,
659 0x00000000,
660 0x00000000,
661 0x40021404,
662 0x00100000,
663 0x1a00d405,
664 0x00100040,
665 0x5b02ca06,
666 0x01900060,
667 0x5b02ca06,
668 0x01900060,
669 0x53028a07,
670 0x0190c060,
671 0x00000000,
672 0x00000000,
673 0x00000000,
674 0x00000000,
675 0x00000000,
676 0x00000000,
677 0x00000000,
678 0x00000000,
679 0x00000000,
680 0x00000000,
681 0x00000000,
682 0x00000000,
683 0x00000000,
684 0x00000000,
685 0x00000000,
686 0x00000000,
687 0x00000000,
688 0x00000000,
689 0x00000000,
690 0x00000000,
691 0x00000000,
692 0x00000000,
693 0x4002140c,
694 0x00100010,
695 0x1a00d40d,
696 0x00100050,
697 0x5b02ca0e,
698 0x01900070,
699 0x5b02ca0e,
700 0x01900070,
701 0x53028a0f,
702 0x0190c070,
703 0x00000000,
704 0x00000000,
705 0x00000000,
706 0x00000000,
707 0x00000000,
708 0x00000000,
709 0x00000000,
710 0x00000000,
711 0x00000000,
712 0x00000000,
713 0x00000000,
714 0x00000000,
715 0x00000000,
716 0x00000000,
717 0x00000000,
718 0x00000000,
719 0x00000000,
720 0x00000000,
721 0x00000000,
722 0x00000000,
723 0x00000000,
724 0x00000000,
725 0x00000000,
726 0x00000000,
727 0x00000000,
728 0x00000000,
729 0x00000000,
730 0x00000000,
731 0x00000000,
732 0x00000000,
733 0x00000000,
734 0x00000000,
735 0x00000000,
736 0x00000000,
737 0x00000000,
738 0x00000000,
739 0x00000000,
740 0x00000000,
741 0x00000000,
742 0x00000000,
743 0x00000000,
744 0x00000000,
745 0x00000000,
746 0x00000000,
747 0x00000000,
748 0x00000000,
749 0x00000000,
750 0x00000000,
751 0x00000000,
752 0x00000000,
753 0x00000000,
754 0x00000000,
755 0x00000000,
756 0x00000000,
757 0x00000000,
758 0x00000000,
759 0x00000000,
760 0x00000000,
761 0x00000000,
762 0x00000000,
763 0x00000000,
764 0x00000000,
765 0x00000000,
766 0x00000000,
767 0x00000000,
768 0x00000000,
769 0x00000000,
770 0x00000000,
771 0x00000000,
772 0x00000000,
773 0x00000000,
774 0x00000000,
775 0x00000000,
776 0x00000000,
777 0x00000000,
778 0x00000000,
779 0x00000000,
780 0x00000000,
781 0x00000000,
782 0x00000000,
783 0x00000000,
784 0x00000000,
785 0x00000000,
786 0x00000000,
787 0x00000000,
788 0x00000000,
789 0x00000000,
790 0x00000000,
791 0x00000000,
792 0x00000000,
793 0x00000000,
794 0x00000000,
795 0x00000000,
796 0x00000000,
797 0x00000000,
798 0x00000000,
799 0x00000000,
800 0x00000000,
801 0x00000000,
802 0x00000000,
803 0x00000000,
804 0x00000000,
805 0x00000000,
806 0x00000000,
807 0x00000000,
808 0x00000000,
809 0x00000000,
810 0x00000000,
811 0x00000000,
812 0x00000000,
813 0x00000000,
814 0x00000000,
815 0x00000000,
816 0x00000000,
817 0x00000000,
818 0x00000000,
819 0x00000000,
820 0x00000000,
821 0x00000000,
822 0x00000000,
823 0x00000000,
824 0x00000000,
825 0x00000000,
826 0x00000000,
827 0x00000000,
828 0x00000000,
829 0x00000000,
830 0x00000000,
831 0x00000000,
832 0x00000000,
833 0x00000000,
834 0x00000000,
835 0x00000000,
836 0x00000000,
837 0x00000000,
838 0x00000000,
839 0x00000000,
840 0x00000000,
841 0x00000000,
842 0x00000000,
843 0x00000000,
844 0x00000000,
845 0x00000000,
846 0x00000000,
847 0x00000000,
848 0x00000000,
849 0x00000000,
850 0x00000000,
851 0x00000000,
852 0x00000000,
853};
854
855static const u8 frame_lut_rev0[] = {
856 0x02,
857 0x04,
858 0x14,
859 0x14,
860 0x03,
861 0x05,
862 0x16,
863 0x16,
864 0x0a,
865 0x0c,
866 0x1c,
867 0x1c,
868 0x0b,
869 0x0d,
870 0x1e,
871 0x1e,
872 0x06,
873 0x08,
874 0x18,
875 0x18,
876 0x07,
877 0x09,
878 0x1a,
879 0x1a,
880 0x0e,
881 0x10,
882 0x20,
883 0x28,
884 0x0f,
885 0x11,
886 0x22,
887 0x2a,
888};
889
890static const u32 tmap_tbl_rev0[] = {
891 0x8a88aa80,
892 0x8aaaaa8a,
893 0x8a8a8aa8,
894 0x00000888,
895 0x88000000,
896 0x8a8a88aa,
897 0x8aa88888,
898 0x8888a8a8,
899 0xf1111110,
900 0x11111111,
901 0x11f11111,
902 0x00000111,
903 0x11000000,
904 0x1111f111,
905 0x11111111,
906 0x111111f1,
907 0x8a88aa80,
908 0x8aaaaa8a,
909 0x8a8a8aa8,
910 0x000aa888,
911 0x88880000,
912 0x8a8a88aa,
913 0x8aa88888,
914 0x8888a8a8,
915 0xa1111110,
916 0x11111111,
917 0x11c11111,
918 0x00000111,
919 0x11000000,
920 0x1111a111,
921 0x11111111,
922 0x111111a1,
923 0xa2222220,
924 0x22222222,
925 0x22c22222,
926 0x00000222,
927 0x22000000,
928 0x2222a222,
929 0x22222222,
930 0x222222a2,
931 0xf1111110,
932 0x11111111,
933 0x11f11111,
934 0x00011111,
935 0x11110000,
936 0x1111f111,
937 0x11111111,
938 0x111111f1,
939 0xa8aa88a0,
940 0xa88888a8,
941 0xa8a8a88a,
942 0x00088aaa,
943 0xaaaa0000,
944 0xa8a8aa88,
945 0xa88aaaaa,
946 0xaaaa8a8a,
947 0xaaa8aaa0,
948 0x8aaa8aaa,
949 0xaa8a8a8a,
950 0x000aaa88,
951 0x8aaa0000,
952 0xaaa8a888,
953 0x8aa88a8a,
954 0x8a88a888,
955 0x08080a00,
956 0x0a08080a,
957 0x080a0a08,
958 0x00080808,
959 0x080a0000,
960 0x080a0808,
961 0x080a0808,
962 0x0a0a0a08,
963 0xa0a0a0a0,
964 0x80a0a080,
965 0x8080a0a0,
966 0x00008080,
967 0x80a00000,
968 0x80a080a0,
969 0xa080a0a0,
970 0x8080a0a0,
971 0x00000000,
972 0x00000000,
973 0x00000000,
974 0x00000000,
975 0x00000000,
976 0x00000000,
977 0x00000000,
978 0x00000000,
979 0x00000000,
980 0x00000000,
981 0x00000000,
982 0x00000000,
983 0x00000000,
984 0x00000000,
985 0x00000000,
986 0x00000000,
987 0x00000000,
988 0x00000000,
989 0x00000000,
990 0x00000000,
991 0x00000000,
992 0x00000000,
993 0x00000000,
994 0x00000000,
995 0x00000000,
996 0x00000000,
997 0x00000000,
998 0x00000000,
999 0x00000000,
1000 0x00000000,
1001 0x00000000,
1002 0x00000000,
1003 0x00000000,
1004 0x00000000,
1005 0x00000000,
1006 0x00000000,
1007 0x00000000,
1008 0x00000000,
1009 0x00000000,
1010 0x00000000,
1011 0x00000000,
1012 0x00000000,
1013 0x00000000,
1014 0x00000000,
1015 0x00000000,
1016 0x00000000,
1017 0x00000000,
1018 0x00000000,
1019 0x99999000,
1020 0x9b9b99bb,
1021 0x9bb99999,
1022 0x9999b9b9,
1023 0x9b99bb90,
1024 0x9bbbbb9b,
1025 0x9b9b9bb9,
1026 0x00000999,
1027 0x88000000,
1028 0x8a8a88aa,
1029 0x8aa88888,
1030 0x8888a8a8,
1031 0x8a88aa80,
1032 0x8aaaaa8a,
1033 0x8a8a8aa8,
1034 0x00aaa888,
1035 0x22000000,
1036 0x2222b222,
1037 0x22222222,
1038 0x222222b2,
1039 0xb2222220,
1040 0x22222222,
1041 0x22d22222,
1042 0x00000222,
1043 0x11000000,
1044 0x1111a111,
1045 0x11111111,
1046 0x111111a1,
1047 0xa1111110,
1048 0x11111111,
1049 0x11c11111,
1050 0x00000111,
1051 0x33000000,
1052 0x3333b333,
1053 0x33333333,
1054 0x333333b3,
1055 0xb3333330,
1056 0x33333333,
1057 0x33d33333,
1058 0x00000333,
1059 0x22000000,
1060 0x2222a222,
1061 0x22222222,
1062 0x222222a2,
1063 0xa2222220,
1064 0x22222222,
1065 0x22c22222,
1066 0x00000222,
1067 0x99b99b00,
1068 0x9b9b99bb,
1069 0x9bb99999,
1070 0x9999b9b9,
1071 0x9b99bb99,
1072 0x9bbbbb9b,
1073 0x9b9b9bb9,
1074 0x00000999,
1075 0x88000000,
1076 0x8a8a88aa,
1077 0x8aa88888,
1078 0x8888a8a8,
1079 0x8a88aa88,
1080 0x8aaaaa8a,
1081 0x8a8a8aa8,
1082 0x08aaa888,
1083 0x22222200,
1084 0x2222f222,
1085 0x22222222,
1086 0x222222f2,
1087 0x22222222,
1088 0x22222222,
1089 0x22f22222,
1090 0x00000222,
1091 0x11000000,
1092 0x1111f111,
1093 0x11111111,
1094 0x11111111,
1095 0xf1111111,
1096 0x11111111,
1097 0x11f11111,
1098 0x01111111,
1099 0xbb9bb900,
1100 0xb9b9bb99,
1101 0xb99bbbbb,
1102 0xbbbb9b9b,
1103 0xb9bb99bb,
1104 0xb99999b9,
1105 0xb9b9b99b,
1106 0x00000bbb,
1107 0xaa000000,
1108 0xa8a8aa88,
1109 0xa88aaaaa,
1110 0xaaaa8a8a,
1111 0xa8aa88aa,
1112 0xa88888a8,
1113 0xa8a8a88a,
1114 0x0a888aaa,
1115 0xaa000000,
1116 0xa8a8aa88,
1117 0xa88aaaaa,
1118 0xaaaa8a8a,
1119 0xa8aa88a0,
1120 0xa88888a8,
1121 0xa8a8a88a,
1122 0x00000aaa,
1123 0x88000000,
1124 0x8a8a88aa,
1125 0x8aa88888,
1126 0x8888a8a8,
1127 0x8a88aa80,
1128 0x8aaaaa8a,
1129 0x8a8a8aa8,
1130 0x00000888,
1131 0xbbbbbb00,
1132 0x999bbbbb,
1133 0x9bb99b9b,
1134 0xb9b9b9bb,
1135 0xb9b99bbb,
1136 0xb9b9b9bb,
1137 0xb9bb9b99,
1138 0x00000999,
1139 0x8a000000,
1140 0xaa88a888,
1141 0xa88888aa,
1142 0xa88a8a88,
1143 0xa88aa88a,
1144 0x88a8aaaa,
1145 0xa8aa8aaa,
1146 0x0888a88a,
1147 0x0b0b0b00,
1148 0x090b0b0b,
1149 0x0b090b0b,
1150 0x0909090b,
1151 0x09090b0b,
1152 0x09090b0b,
1153 0x09090b09,
1154 0x00000909,
1155 0x0a000000,
1156 0x0a080808,
1157 0x080a080a,
1158 0x080a0a08,
1159 0x080a080a,
1160 0x0808080a,
1161 0x0a0a0a08,
1162 0x0808080a,
1163 0xb0b0b000,
1164 0x9090b0b0,
1165 0x90b09090,
1166 0xb0b0b090,
1167 0xb0b090b0,
1168 0x90b0b0b0,
1169 0xb0b09090,
1170 0x00000090,
1171 0x80000000,
1172 0xa080a080,
1173 0xa08080a0,
1174 0xa0808080,
1175 0xa080a080,
1176 0x80a0a0a0,
1177 0xa0a080a0,
1178 0x00a0a0a0,
1179 0x22000000,
1180 0x2222f222,
1181 0x22222222,
1182 0x222222f2,
1183 0xf2222220,
1184 0x22222222,
1185 0x22f22222,
1186 0x00000222,
1187 0x11000000,
1188 0x1111f111,
1189 0x11111111,
1190 0x111111f1,
1191 0xf1111110,
1192 0x11111111,
1193 0x11f11111,
1194 0x00000111,
1195 0x33000000,
1196 0x3333f333,
1197 0x33333333,
1198 0x333333f3,
1199 0xf3333330,
1200 0x33333333,
1201 0x33f33333,
1202 0x00000333,
1203 0x22000000,
1204 0x2222f222,
1205 0x22222222,
1206 0x222222f2,
1207 0xf2222220,
1208 0x22222222,
1209 0x22f22222,
1210 0x00000222,
1211 0x99000000,
1212 0x9b9b99bb,
1213 0x9bb99999,
1214 0x9999b9b9,
1215 0x9b99bb90,
1216 0x9bbbbb9b,
1217 0x9b9b9bb9,
1218 0x00000999,
1219 0x88000000,
1220 0x8a8a88aa,
1221 0x8aa88888,
1222 0x8888a8a8,
1223 0x8a88aa80,
1224 0x8aaaaa8a,
1225 0x8a8a8aa8,
1226 0x00000888,
1227 0x88888000,
1228 0x8a8a88aa,
1229 0x8aa88888,
1230 0x8888a8a8,
1231 0x8a88aa80,
1232 0x8aaaaa8a,
1233 0x8a8a8aa8,
1234 0x00000888,
1235 0x88000000,
1236 0x8a8a88aa,
1237 0x8aa88888,
1238 0x8888a8a8,
1239 0x8a88aa80,
1240 0x8aaaaa8a,
1241 0x8a8a8aa8,
1242 0x00aaa888,
1243 0x88a88a00,
1244 0x8a8a88aa,
1245 0x8aa88888,
1246 0x8888a8a8,
1247 0x8a88aa88,
1248 0x8aaaaa8a,
1249 0x8a8a8aa8,
1250 0x00000888,
1251 0x88000000,
1252 0x8a8a88aa,
1253 0x8aa88888,
1254 0x8888a8a8,
1255 0x8a88aa88,
1256 0x8aaaaa8a,
1257 0x8a8a8aa8,
1258 0x08aaa888,
1259 0x11000000,
1260 0x1111a111,
1261 0x11111111,
1262 0x111111a1,
1263 0xa1111110,
1264 0x11111111,
1265 0x11c11111,
1266 0x00000111,
1267 0x11000000,
1268 0x1111a111,
1269 0x11111111,
1270 0x111111a1,
1271 0xa1111110,
1272 0x11111111,
1273 0x11c11111,
1274 0x00000111,
1275 0x88000000,
1276 0x8a8a88aa,
1277 0x8aa88888,
1278 0x8888a8a8,
1279 0x8a88aa80,
1280 0x8aaaaa8a,
1281 0x8a8a8aa8,
1282 0x00000888,
1283 0x88000000,
1284 0x8a8a88aa,
1285 0x8aa88888,
1286 0x8888a8a8,
1287 0x8a88aa80,
1288 0x8aaaaa8a,
1289 0x8a8a8aa8,
1290 0x00000888,
1291 0x00000000,
1292 0x00000000,
1293 0x00000000,
1294 0x00000000,
1295 0x00000000,
1296 0x00000000,
1297 0x00000000,
1298 0x00000000,
1299 0x00000000,
1300 0x00000000,
1301 0x00000000,
1302 0x00000000,
1303 0x00000000,
1304 0x00000000,
1305 0x00000000,
1306 0x00000000,
1307 0x00000000,
1308 0x00000000,
1309 0x00000000,
1310 0x00000000,
1311 0x00000000,
1312 0x00000000,
1313 0x00000000,
1314 0x00000000,
1315 0x00000000,
1316 0x00000000,
1317 0x00000000,
1318 0x00000000,
1319 0x00000000,
1320 0x00000000,
1321 0x00000000,
1322 0x00000000,
1323 0x00000000,
1324 0x00000000,
1325 0x00000000,
1326 0x00000000,
1327 0x00000000,
1328 0x00000000,
1329 0x00000000,
1330 0x00000000,
1331 0x00000000,
1332 0x00000000,
1333 0x00000000,
1334 0x00000000,
1335 0x00000000,
1336 0x00000000,
1337 0x00000000,
1338 0x00000000,
1339};
1340
1341static const u32 tdtrn_tbl_rev0[] = {
1342 0x061c061c,
1343 0x0050ee68,
1344 0xf592fe36,
1345 0xfe5212f6,
1346 0x00000c38,
1347 0xfe5212f6,
1348 0xf592fe36,
1349 0x0050ee68,
1350 0x061c061c,
1351 0xee680050,
1352 0xfe36f592,
1353 0x12f6fe52,
1354 0x0c380000,
1355 0x12f6fe52,
1356 0xfe36f592,
1357 0xee680050,
1358 0x061c061c,
1359 0x0050ee68,
1360 0xf592fe36,
1361 0xfe5212f6,
1362 0x00000c38,
1363 0xfe5212f6,
1364 0xf592fe36,
1365 0x0050ee68,
1366 0x061c061c,
1367 0xee680050,
1368 0xfe36f592,
1369 0x12f6fe52,
1370 0x0c380000,
1371 0x12f6fe52,
1372 0xfe36f592,
1373 0xee680050,
1374 0x05e305e3,
1375 0x004def0c,
1376 0xf5f3fe47,
1377 0xfe611246,
1378 0x00000bc7,
1379 0xfe611246,
1380 0xf5f3fe47,
1381 0x004def0c,
1382 0x05e305e3,
1383 0xef0c004d,
1384 0xfe47f5f3,
1385 0x1246fe61,
1386 0x0bc70000,
1387 0x1246fe61,
1388 0xfe47f5f3,
1389 0xef0c004d,
1390 0x05e305e3,
1391 0x004def0c,
1392 0xf5f3fe47,
1393 0xfe611246,
1394 0x00000bc7,
1395 0xfe611246,
1396 0xf5f3fe47,
1397 0x004def0c,
1398 0x05e305e3,
1399 0xef0c004d,
1400 0xfe47f5f3,
1401 0x1246fe61,
1402 0x0bc70000,
1403 0x1246fe61,
1404 0xfe47f5f3,
1405 0xef0c004d,
1406 0xfa58fa58,
1407 0xf895043b,
1408 0xff4c09c0,
1409 0xfbc6ffa8,
1410 0xfb84f384,
1411 0x0798f6f9,
1412 0x05760122,
1413 0x058409f6,
1414 0x0b500000,
1415 0x05b7f542,
1416 0x08860432,
1417 0x06ddfee7,
1418 0xfb84f384,
1419 0xf9d90664,
1420 0xf7e8025c,
1421 0x00fff7bd,
1422 0x05a805a8,
1423 0xf7bd00ff,
1424 0x025cf7e8,
1425 0x0664f9d9,
1426 0xf384fb84,
1427 0xfee706dd,
1428 0x04320886,
1429 0xf54205b7,
1430 0x00000b50,
1431 0x09f60584,
1432 0x01220576,
1433 0xf6f90798,
1434 0xf384fb84,
1435 0xffa8fbc6,
1436 0x09c0ff4c,
1437 0x043bf895,
1438 0x02d402d4,
1439 0x07de0270,
1440 0xfc96079c,
1441 0xf90afe94,
1442 0xfe00ff2c,
1443 0x02d4065d,
1444 0x092a0096,
1445 0x0014fbb8,
1446 0xfd2cfd2c,
1447 0x076afb3c,
1448 0x0096f752,
1449 0xf991fd87,
1450 0xfb2c0200,
1451 0xfeb8f960,
1452 0x08e0fc96,
1453 0x049802a8,
1454 0xfd2cfd2c,
1455 0x02a80498,
1456 0xfc9608e0,
1457 0xf960feb8,
1458 0x0200fb2c,
1459 0xfd87f991,
1460 0xf7520096,
1461 0xfb3c076a,
1462 0xfd2cfd2c,
1463 0xfbb80014,
1464 0x0096092a,
1465 0x065d02d4,
1466 0xff2cfe00,
1467 0xfe94f90a,
1468 0x079cfc96,
1469 0x027007de,
1470 0x02d402d4,
1471 0x027007de,
1472 0x079cfc96,
1473 0xfe94f90a,
1474 0xff2cfe00,
1475 0x065d02d4,
1476 0x0096092a,
1477 0xfbb80014,
1478 0xfd2cfd2c,
1479 0xfb3c076a,
1480 0xf7520096,
1481 0xfd87f991,
1482 0x0200fb2c,
1483 0xf960feb8,
1484 0xfc9608e0,
1485 0x02a80498,
1486 0xfd2cfd2c,
1487 0x049802a8,
1488 0x08e0fc96,
1489 0xfeb8f960,
1490 0xfb2c0200,
1491 0xf991fd87,
1492 0x0096f752,
1493 0x076afb3c,
1494 0xfd2cfd2c,
1495 0x0014fbb8,
1496 0x092a0096,
1497 0x02d4065d,
1498 0xfe00ff2c,
1499 0xf90afe94,
1500 0xfc96079c,
1501 0x07de0270,
1502 0x00000000,
1503 0x00000000,
1504 0x00000000,
1505 0x00000000,
1506 0x00000000,
1507 0x00000000,
1508 0x00000000,
1509 0x00000000,
1510 0x00000000,
1511 0x00000000,
1512 0x00000000,
1513 0x00000000,
1514 0x00000000,
1515 0x00000000,
1516 0x00000000,
1517 0x00000000,
1518 0x00000000,
1519 0x00000000,
1520 0x00000000,
1521 0x00000000,
1522 0x00000000,
1523 0x00000000,
1524 0x00000000,
1525 0x00000000,
1526 0x00000000,
1527 0x00000000,
1528 0x00000000,
1529 0x00000000,
1530 0x00000000,
1531 0x00000000,
1532 0x00000000,
1533 0x00000000,
1534 0x00000000,
1535 0x00000000,
1536 0x00000000,
1537 0x00000000,
1538 0x00000000,
1539 0x00000000,
1540 0x00000000,
1541 0x00000000,
1542 0x00000000,
1543 0x00000000,
1544 0x00000000,
1545 0x00000000,
1546 0x00000000,
1547 0x00000000,
1548 0x00000000,
1549 0x00000000,
1550 0x00000000,
1551 0x00000000,
1552 0x00000000,
1553 0x00000000,
1554 0x00000000,
1555 0x00000000,
1556 0x00000000,
1557 0x00000000,
1558 0x00000000,
1559 0x00000000,
1560 0x00000000,
1561 0x00000000,
1562 0x00000000,
1563 0x00000000,
1564 0x00000000,
1565 0x00000000,
1566 0x00000000,
1567 0x00000000,
1568 0x00000000,
1569 0x00000000,
1570 0x00000000,
1571 0x00000000,
1572 0x00000000,
1573 0x00000000,
1574 0x00000000,
1575 0x00000000,
1576 0x00000000,
1577 0x00000000,
1578 0x00000000,
1579 0x00000000,
1580 0x00000000,
1581 0x00000000,
1582 0x00000000,
1583 0x00000000,
1584 0x00000000,
1585 0x00000000,
1586 0x00000000,
1587 0x00000000,
1588 0x00000000,
1589 0x00000000,
1590 0x00000000,
1591 0x00000000,
1592 0x00000000,
1593 0x00000000,
1594 0x00000000,
1595 0x00000000,
1596 0x00000000,
1597 0x00000000,
1598 0x062a0000,
1599 0xfefa0759,
1600 0x08b80908,
1601 0xf396fc2d,
1602 0xf9d6045c,
1603 0xfc4ef608,
1604 0xf748f596,
1605 0x07b207bf,
1606 0x062a062a,
1607 0xf84ef841,
1608 0xf748f596,
1609 0x03b209f8,
1610 0xf9d6045c,
1611 0x0c6a03d3,
1612 0x08b80908,
1613 0x0106f8a7,
1614 0x062a0000,
1615 0xfefaf8a7,
1616 0x08b8f6f8,
1617 0xf39603d3,
1618 0xf9d6fba4,
1619 0xfc4e09f8,
1620 0xf7480a6a,
1621 0x07b2f841,
1622 0x062af9d6,
1623 0xf84e07bf,
1624 0xf7480a6a,
1625 0x03b2f608,
1626 0xf9d6fba4,
1627 0x0c6afc2d,
1628 0x08b8f6f8,
1629 0x01060759,
1630 0x062a0000,
1631 0xfefa0759,
1632 0x08b80908,
1633 0xf396fc2d,
1634 0xf9d6045c,
1635 0xfc4ef608,
1636 0xf748f596,
1637 0x07b207bf,
1638 0x062a062a,
1639 0xf84ef841,
1640 0xf748f596,
1641 0x03b209f8,
1642 0xf9d6045c,
1643 0x0c6a03d3,
1644 0x08b80908,
1645 0x0106f8a7,
1646 0x062a0000,
1647 0xfefaf8a7,
1648 0x08b8f6f8,
1649 0xf39603d3,
1650 0xf9d6fba4,
1651 0xfc4e09f8,
1652 0xf7480a6a,
1653 0x07b2f841,
1654 0x062af9d6,
1655 0xf84e07bf,
1656 0xf7480a6a,
1657 0x03b2f608,
1658 0xf9d6fba4,
1659 0x0c6afc2d,
1660 0x08b8f6f8,
1661 0x01060759,
1662 0x061c061c,
1663 0xff30009d,
1664 0xffb21141,
1665 0xfd87fb54,
1666 0xf65dfe59,
1667 0x02eef99e,
1668 0x0166f03c,
1669 0xfff809b6,
1670 0x000008a4,
1671 0x000af42b,
1672 0x00eff577,
1673 0xfa840bf2,
1674 0xfc02ff51,
1675 0x08260f67,
1676 0xfff0036f,
1677 0x0842f9c3,
1678 0x00000000,
1679 0x063df7be,
1680 0xfc910010,
1681 0xf099f7da,
1682 0x00af03fe,
1683 0xf40e057c,
1684 0x0a89ff11,
1685 0x0bd5fff6,
1686 0xf75c0000,
1687 0xf64a0008,
1688 0x0fc4fe9a,
1689 0x0662fd12,
1690 0x01a709a3,
1691 0x04ac0279,
1692 0xeebf004e,
1693 0xff6300d0,
1694 0xf9e4f9e4,
1695 0x00d0ff63,
1696 0x004eeebf,
1697 0x027904ac,
1698 0x09a301a7,
1699 0xfd120662,
1700 0xfe9a0fc4,
1701 0x0008f64a,
1702 0x0000f75c,
1703 0xfff60bd5,
1704 0xff110a89,
1705 0x057cf40e,
1706 0x03fe00af,
1707 0xf7daf099,
1708 0x0010fc91,
1709 0xf7be063d,
1710 0x00000000,
1711 0xf9c30842,
1712 0x036ffff0,
1713 0x0f670826,
1714 0xff51fc02,
1715 0x0bf2fa84,
1716 0xf57700ef,
1717 0xf42b000a,
1718 0x08a40000,
1719 0x09b6fff8,
1720 0xf03c0166,
1721 0xf99e02ee,
1722 0xfe59f65d,
1723 0xfb54fd87,
1724 0x1141ffb2,
1725 0x009dff30,
1726 0x05e30000,
1727 0xff060705,
1728 0x085408a0,
1729 0xf425fc59,
1730 0xfa1d042a,
1731 0xfc78f67a,
1732 0xf7acf60e,
1733 0x075a0766,
1734 0x05e305e3,
1735 0xf8a6f89a,
1736 0xf7acf60e,
1737 0x03880986,
1738 0xfa1d042a,
1739 0x0bdb03a7,
1740 0x085408a0,
1741 0x00faf8fb,
1742 0x05e30000,
1743 0xff06f8fb,
1744 0x0854f760,
1745 0xf42503a7,
1746 0xfa1dfbd6,
1747 0xfc780986,
1748 0xf7ac09f2,
1749 0x075af89a,
1750 0x05e3fa1d,
1751 0xf8a60766,
1752 0xf7ac09f2,
1753 0x0388f67a,
1754 0xfa1dfbd6,
1755 0x0bdbfc59,
1756 0x0854f760,
1757 0x00fa0705,
1758 0x05e30000,
1759 0xff060705,
1760 0x085408a0,
1761 0xf425fc59,
1762 0xfa1d042a,
1763 0xfc78f67a,
1764 0xf7acf60e,
1765 0x075a0766,
1766 0x05e305e3,
1767 0xf8a6f89a,
1768 0xf7acf60e,
1769 0x03880986,
1770 0xfa1d042a,
1771 0x0bdb03a7,
1772 0x085408a0,
1773 0x00faf8fb,
1774 0x05e30000,
1775 0xff06f8fb,
1776 0x0854f760,
1777 0xf42503a7,
1778 0xfa1dfbd6,
1779 0xfc780986,
1780 0xf7ac09f2,
1781 0x075af89a,
1782 0x05e3fa1d,
1783 0xf8a60766,
1784 0xf7ac09f2,
1785 0x0388f67a,
1786 0xfa1dfbd6,
1787 0x0bdbfc59,
1788 0x0854f760,
1789 0x00fa0705,
1790 0xfa58fa58,
1791 0xf8f0fe00,
1792 0x0448073d,
1793 0xfdc9fe46,
1794 0xf9910258,
1795 0x089d0407,
1796 0xfd5cf71a,
1797 0x02affde0,
1798 0x083e0496,
1799 0xff5a0740,
1800 0xff7afd97,
1801 0x00fe01f1,
1802 0x0009082e,
1803 0xfa94ff75,
1804 0xfecdf8ea,
1805 0xffb0f693,
1806 0xfd2cfa58,
1807 0x0433ff16,
1808 0xfba405dd,
1809 0xfa610341,
1810 0x06a606cb,
1811 0x0039fd2d,
1812 0x0677fa97,
1813 0x01fa05e0,
1814 0xf896003e,
1815 0x075a068b,
1816 0x012cfc3e,
1817 0xfa23f98d,
1818 0xfc7cfd43,
1819 0xff90fc0d,
1820 0x01c10982,
1821 0x00c601d6,
1822 0xfd2cfd2c,
1823 0x01d600c6,
1824 0x098201c1,
1825 0xfc0dff90,
1826 0xfd43fc7c,
1827 0xf98dfa23,
1828 0xfc3e012c,
1829 0x068b075a,
1830 0x003ef896,
1831 0x05e001fa,
1832 0xfa970677,
1833 0xfd2d0039,
1834 0x06cb06a6,
1835 0x0341fa61,
1836 0x05ddfba4,
1837 0xff160433,
1838 0xfa58fd2c,
1839 0xf693ffb0,
1840 0xf8eafecd,
1841 0xff75fa94,
1842 0x082e0009,
1843 0x01f100fe,
1844 0xfd97ff7a,
1845 0x0740ff5a,
1846 0x0496083e,
1847 0xfde002af,
1848 0xf71afd5c,
1849 0x0407089d,
1850 0x0258f991,
1851 0xfe46fdc9,
1852 0x073d0448,
1853 0xfe00f8f0,
1854 0xfd2cfd2c,
1855 0xfce00500,
1856 0xfc09fddc,
1857 0xfe680157,
1858 0x04c70571,
1859 0xfc3aff21,
1860 0xfcd70228,
1861 0x056d0277,
1862 0x0200fe00,
1863 0x0022f927,
1864 0xfe3c032b,
1865 0xfc44ff3c,
1866 0x03e9fbdb,
1867 0x04570313,
1868 0x04c9ff5c,
1869 0x000d03b8,
1870 0xfa580000,
1871 0xfbe900d2,
1872 0xf9d0fe0b,
1873 0x0125fdf9,
1874 0x042501bf,
1875 0x0328fa2b,
1876 0xffa902f0,
1877 0xfa250157,
1878 0x0200fe00,
1879 0x03740438,
1880 0xff0405fd,
1881 0x030cfe52,
1882 0x0037fb39,
1883 0xff6904c5,
1884 0x04f8fd23,
1885 0xfd31fc1b,
1886 0xfd2cfd2c,
1887 0xfc1bfd31,
1888 0xfd2304f8,
1889 0x04c5ff69,
1890 0xfb390037,
1891 0xfe52030c,
1892 0x05fdff04,
1893 0x04380374,
1894 0xfe000200,
1895 0x0157fa25,
1896 0x02f0ffa9,
1897 0xfa2b0328,
1898 0x01bf0425,
1899 0xfdf90125,
1900 0xfe0bf9d0,
1901 0x00d2fbe9,
1902 0x0000fa58,
1903 0x03b8000d,
1904 0xff5c04c9,
1905 0x03130457,
1906 0xfbdb03e9,
1907 0xff3cfc44,
1908 0x032bfe3c,
1909 0xf9270022,
1910 0xfe000200,
1911 0x0277056d,
1912 0x0228fcd7,
1913 0xff21fc3a,
1914 0x057104c7,
1915 0x0157fe68,
1916 0xfddcfc09,
1917 0x0500fce0,
1918 0xfd2cfd2c,
1919 0x0500fce0,
1920 0xfddcfc09,
1921 0x0157fe68,
1922 0x057104c7,
1923 0xff21fc3a,
1924 0x0228fcd7,
1925 0x0277056d,
1926 0xfe000200,
1927 0xf9270022,
1928 0x032bfe3c,
1929 0xff3cfc44,
1930 0xfbdb03e9,
1931 0x03130457,
1932 0xff5c04c9,
1933 0x03b8000d,
1934 0x0000fa58,
1935 0x00d2fbe9,
1936 0xfe0bf9d0,
1937 0xfdf90125,
1938 0x01bf0425,
1939 0xfa2b0328,
1940 0x02f0ffa9,
1941 0x0157fa25,
1942 0xfe000200,
1943 0x04380374,
1944 0x05fdff04,
1945 0xfe52030c,
1946 0xfb390037,
1947 0x04c5ff69,
1948 0xfd2304f8,
1949 0xfc1bfd31,
1950 0xfd2cfd2c,
1951 0xfd31fc1b,
1952 0x04f8fd23,
1953 0xff6904c5,
1954 0x0037fb39,
1955 0x030cfe52,
1956 0xff0405fd,
1957 0x03740438,
1958 0x0200fe00,
1959 0xfa250157,
1960 0xffa902f0,
1961 0x0328fa2b,
1962 0x042501bf,
1963 0x0125fdf9,
1964 0xf9d0fe0b,
1965 0xfbe900d2,
1966 0xfa580000,
1967 0x000d03b8,
1968 0x04c9ff5c,
1969 0x04570313,
1970 0x03e9fbdb,
1971 0xfc44ff3c,
1972 0xfe3c032b,
1973 0x0022f927,
1974 0x0200fe00,
1975 0x056d0277,
1976 0xfcd70228,
1977 0xfc3aff21,
1978 0x04c70571,
1979 0xfe680157,
1980 0xfc09fddc,
1981 0xfce00500,
1982 0x05a80000,
1983 0xff1006be,
1984 0x0800084a,
1985 0xf49cfc7e,
1986 0xfa580400,
1987 0xfc9cf6da,
1988 0xf800f672,
1989 0x0710071c,
1990 0x05a805a8,
1991 0xf8f0f8e4,
1992 0xf800f672,
1993 0x03640926,
1994 0xfa580400,
1995 0x0b640382,
1996 0x0800084a,
1997 0x00f0f942,
1998 0x05a80000,
1999 0xff10f942,
2000 0x0800f7b6,
2001 0xf49c0382,
2002 0xfa58fc00,
2003 0xfc9c0926,
2004 0xf800098e,
2005 0x0710f8e4,
2006 0x05a8fa58,
2007 0xf8f0071c,
2008 0xf800098e,
2009 0x0364f6da,
2010 0xfa58fc00,
2011 0x0b64fc7e,
2012 0x0800f7b6,
2013 0x00f006be,
2014 0x05a80000,
2015 0xff1006be,
2016 0x0800084a,
2017 0xf49cfc7e,
2018 0xfa580400,
2019 0xfc9cf6da,
2020 0xf800f672,
2021 0x0710071c,
2022 0x05a805a8,
2023 0xf8f0f8e4,
2024 0xf800f672,
2025 0x03640926,
2026 0xfa580400,
2027 0x0b640382,
2028 0x0800084a,
2029 0x00f0f942,
2030 0x05a80000,
2031 0xff10f942,
2032 0x0800f7b6,
2033 0xf49c0382,
2034 0xfa58fc00,
2035 0xfc9c0926,
2036 0xf800098e,
2037 0x0710f8e4,
2038 0x05a8fa58,
2039 0xf8f0071c,
2040 0xf800098e,
2041 0x0364f6da,
2042 0xfa58fc00,
2043 0x0b64fc7e,
2044 0x0800f7b6,
2045 0x00f006be,
2046};
2047
2048static const u32 intlv_tbl_rev0[] = {
2049 0x00802070,
2050 0x0671188d,
2051 0x0a60192c,
2052 0x0a300e46,
2053 0x00c1188d,
2054 0x080024d2,
2055 0x00000070,
2056};
2057
2058static const u16 pilot_tbl_rev0[] = {
2059 0xff08,
2060 0xff08,
2061 0xff08,
2062 0xff08,
2063 0xff08,
2064 0xff08,
2065 0xff08,
2066 0xff08,
2067 0x80d5,
2068 0x80d5,
2069 0x80d5,
2070 0x80d5,
2071 0x80d5,
2072 0x80d5,
2073 0x80d5,
2074 0x80d5,
2075 0xff0a,
2076 0xff82,
2077 0xffa0,
2078 0xff28,
2079 0xffff,
2080 0xffff,
2081 0xffff,
2082 0xffff,
2083 0xff82,
2084 0xffa0,
2085 0xff28,
2086 0xff0a,
2087 0xffff,
2088 0xffff,
2089 0xffff,
2090 0xffff,
2091 0xf83f,
2092 0xfa1f,
2093 0xfa97,
2094 0xfab5,
2095 0xf2bd,
2096 0xf0bf,
2097 0xffff,
2098 0xffff,
2099 0xf017,
2100 0xf815,
2101 0xf215,
2102 0xf095,
2103 0xf035,
2104 0xf01d,
2105 0xffff,
2106 0xffff,
2107 0xff08,
2108 0xff02,
2109 0xff80,
2110 0xff20,
2111 0xff08,
2112 0xff02,
2113 0xff80,
2114 0xff20,
2115 0xf01f,
2116 0xf817,
2117 0xfa15,
2118 0xf295,
2119 0xf0b5,
2120 0xf03d,
2121 0xffff,
2122 0xffff,
2123 0xf82a,
2124 0xfa0a,
2125 0xfa82,
2126 0xfaa0,
2127 0xf2a8,
2128 0xf0aa,
2129 0xffff,
2130 0xffff,
2131 0xf002,
2132 0xf800,
2133 0xf200,
2134 0xf080,
2135 0xf020,
2136 0xf008,
2137 0xffff,
2138 0xffff,
2139 0xf00a,
2140 0xf802,
2141 0xfa00,
2142 0xf280,
2143 0xf0a0,
2144 0xf028,
2145 0xffff,
2146 0xffff,
2147};
2148
2149static const u32 pltlut_tbl_rev0[] = {
2150 0x76540123,
2151 0x62407351,
2152 0x76543201,
2153 0x76540213,
2154 0x76540123,
2155 0x76430521,
2156};
2157
2158static const u32 tdi_tbl20_ant0_rev0[] = {
2159 0x00091226,
2160 0x000a1429,
2161 0x000b56ad,
2162 0x000c58b0,
2163 0x000d5ab3,
2164 0x000e9cb6,
2165 0x000f9eba,
2166 0x0000c13d,
2167 0x00020301,
2168 0x00030504,
2169 0x00040708,
2170 0x0005090b,
2171 0x00064b8e,
2172 0x00095291,
2173 0x000a5494,
2174 0x000b9718,
2175 0x000c9927,
2176 0x000d9b2a,
2177 0x000edd2e,
2178 0x000fdf31,
2179 0x000101b4,
2180 0x000243b7,
2181 0x000345bb,
2182 0x000447be,
2183 0x00058982,
2184 0x00068c05,
2185 0x00099309,
2186 0x000a950c,
2187 0x000bd78f,
2188 0x000cd992,
2189 0x000ddb96,
2190 0x000f1d99,
2191 0x00005fa8,
2192 0x0001422c,
2193 0x0002842f,
2194 0x00038632,
2195 0x00048835,
2196 0x0005ca38,
2197 0x0006ccbc,
2198 0x0009d3bf,
2199 0x000b1603,
2200 0x000c1806,
2201 0x000d1a0a,
2202 0x000e1c0d,
2203 0x000f5e10,
2204 0x00008093,
2205 0x00018297,
2206 0x0002c49a,
2207 0x0003c680,
2208 0x0004c880,
2209 0x00060b00,
2210 0x00070d00,
2211 0x00000000,
2212 0x00000000,
2213 0x00000000,
2214};
2215
2216static const u32 tdi_tbl20_ant1_rev0[] = {
2217 0x00014b26,
2218 0x00028d29,
2219 0x000393ad,
2220 0x00049630,
2221 0x0005d833,
2222 0x0006da36,
2223 0x00099c3a,
2224 0x000a9e3d,
2225 0x000bc081,
2226 0x000cc284,
2227 0x000dc488,
2228 0x000f068b,
2229 0x0000488e,
2230 0x00018b91,
2231 0x0002d214,
2232 0x0003d418,
2233 0x0004d6a7,
2234 0x000618aa,
2235 0x00071aae,
2236 0x0009dcb1,
2237 0x000b1eb4,
2238 0x000c0137,
2239 0x000d033b,
2240 0x000e053e,
2241 0x000f4702,
2242 0x00008905,
2243 0x00020c09,
2244 0x0003128c,
2245 0x0004148f,
2246 0x00051712,
2247 0x00065916,
2248 0x00091b19,
2249 0x000a1d28,
2250 0x000b5f2c,
2251 0x000c41af,
2252 0x000d43b2,
2253 0x000e85b5,
2254 0x000f87b8,
2255 0x0000c9bc,
2256 0x00024cbf,
2257 0x00035303,
2258 0x00045506,
2259 0x0005978a,
2260 0x0006998d,
2261 0x00095b90,
2262 0x000a5d93,
2263 0x000b9f97,
2264 0x000c821a,
2265 0x000d8400,
2266 0x000ec600,
2267 0x000fc800,
2268 0x00010a00,
2269 0x00000000,
2270 0x00000000,
2271 0x00000000,
2272};
2273
2274static const u32 tdi_tbl40_ant0_rev0[] = {
2275 0x0011a346,
2276 0x00136ccf,
2277 0x0014f5d9,
2278 0x001641e2,
2279 0x0017cb6b,
2280 0x00195475,
2281 0x001b2383,
2282 0x001cad0c,
2283 0x001e7616,
2284 0x0000821f,
2285 0x00020ba8,
2286 0x0003d4b2,
2287 0x00056447,
2288 0x00072dd0,
2289 0x0008b6da,
2290 0x000a02e3,
2291 0x000b8c6c,
2292 0x000d15f6,
2293 0x0011e484,
2294 0x0013ae0d,
2295 0x00153717,
2296 0x00168320,
2297 0x00180ca9,
2298 0x00199633,
2299 0x001b6548,
2300 0x001ceed1,
2301 0x001eb7db,
2302 0x0000c3e4,
2303 0x00024d6d,
2304 0x000416f7,
2305 0x0005a585,
2306 0x00076f0f,
2307 0x0008f818,
2308 0x000a4421,
2309 0x000bcdab,
2310 0x000d9734,
2311 0x00122649,
2312 0x0013efd2,
2313 0x001578dc,
2314 0x0016c4e5,
2315 0x00184e6e,
2316 0x001a17f8,
2317 0x001ba686,
2318 0x001d3010,
2319 0x001ef999,
2320 0x00010522,
2321 0x00028eac,
2322 0x00045835,
2323 0x0005e74a,
2324 0x0007b0d3,
2325 0x00093a5d,
2326 0x000a85e6,
2327 0x000c0f6f,
2328 0x000dd8f9,
2329 0x00126787,
2330 0x00143111,
2331 0x0015ba9a,
2332 0x00170623,
2333 0x00188fad,
2334 0x001a5936,
2335 0x001be84b,
2336 0x001db1d4,
2337 0x001f3b5e,
2338 0x000146e7,
2339 0x00031070,
2340 0x000499fa,
2341 0x00062888,
2342 0x0007f212,
2343 0x00097b9b,
2344 0x000ac7a4,
2345 0x000c50ae,
2346 0x000e1a37,
2347 0x0012a94c,
2348 0x001472d5,
2349 0x0015fc5f,
2350 0x00174868,
2351 0x0018d171,
2352 0x001a9afb,
2353 0x001c2989,
2354 0x001df313,
2355 0x001f7c9c,
2356 0x000188a5,
2357 0x000351af,
2358 0x0004db38,
2359 0x0006aa4d,
2360 0x000833d7,
2361 0x0009bd60,
2362 0x000b0969,
2363 0x000c9273,
2364 0x000e5bfc,
2365 0x00132a8a,
2366 0x0014b414,
2367 0x00163d9d,
2368 0x001789a6,
2369 0x001912b0,
2370 0x001adc39,
2371 0x001c6bce,
2372 0x001e34d8,
2373 0x001fbe61,
2374 0x0001ca6a,
2375 0x00039374,
2376 0x00051cfd,
2377 0x0006ec0b,
2378 0x00087515,
2379 0x0009fe9e,
2380 0x000b4aa7,
2381 0x000cd3b1,
2382 0x000e9d3a,
2383 0x00000000,
2384 0x00000000,
2385};
2386
2387static const u32 tdi_tbl40_ant1_rev0[] = {
2388 0x001edb36,
2389 0x000129ca,
2390 0x0002b353,
2391 0x00047cdd,
2392 0x0005c8e6,
2393 0x000791ef,
2394 0x00091bf9,
2395 0x000aaa07,
2396 0x000c3391,
2397 0x000dfd1a,
2398 0x00120923,
2399 0x0013d22d,
2400 0x00155c37,
2401 0x0016eacb,
2402 0x00187454,
2403 0x001a3dde,
2404 0x001b89e7,
2405 0x001d12f0,
2406 0x001f1cfa,
2407 0x00016b88,
2408 0x00033492,
2409 0x0004be1b,
2410 0x00060a24,
2411 0x0007d32e,
2412 0x00095d38,
2413 0x000aec4c,
2414 0x000c7555,
2415 0x000e3edf,
2416 0x00124ae8,
2417 0x001413f1,
2418 0x0015a37b,
2419 0x00172c89,
2420 0x0018b593,
2421 0x001a419c,
2422 0x001bcb25,
2423 0x001d942f,
2424 0x001f63b9,
2425 0x0001ad4d,
2426 0x00037657,
2427 0x0004c260,
2428 0x00068be9,
2429 0x000814f3,
2430 0x0009a47c,
2431 0x000b2d8a,
2432 0x000cb694,
2433 0x000e429d,
2434 0x00128c26,
2435 0x001455b0,
2436 0x0015e4ba,
2437 0x00176e4e,
2438 0x0018f758,
2439 0x001a8361,
2440 0x001c0cea,
2441 0x001dd674,
2442 0x001fa57d,
2443 0x0001ee8b,
2444 0x0003b795,
2445 0x0005039e,
2446 0x0006cd27,
2447 0x000856b1,
2448 0x0009e5c6,
2449 0x000b6f4f,
2450 0x000cf859,
2451 0x000e8462,
2452 0x00130deb,
2453 0x00149775,
2454 0x00162603,
2455 0x0017af8c,
2456 0x00193896,
2457 0x001ac49f,
2458 0x001c4e28,
2459 0x001e17b2,
2460 0x0000a6c7,
2461 0x00023050,
2462 0x0003f9da,
2463 0x00054563,
2464 0x00070eec,
2465 0x00089876,
2466 0x000a2704,
2467 0x000bb08d,
2468 0x000d3a17,
2469 0x001185a0,
2470 0x00134f29,
2471 0x0014d8b3,
2472 0x001667c8,
2473 0x0017f151,
2474 0x00197adb,
2475 0x001b0664,
2476 0x001c8fed,
2477 0x001e5977,
2478 0x0000e805,
2479 0x0002718f,
2480 0x00043b18,
2481 0x000586a1,
2482 0x0007502b,
2483 0x0008d9b4,
2484 0x000a68c9,
2485 0x000bf252,
2486 0x000dbbdc,
2487 0x0011c7e5,
2488 0x001390ee,
2489 0x00151a78,
2490 0x0016a906,
2491 0x00183290,
2492 0x0019bc19,
2493 0x001b4822,
2494 0x001cd12c,
2495 0x001e9ab5,
2496 0x00000000,
2497 0x00000000,
2498};
2499
2500static const u16 bdi_tbl_rev0[] = {
2501 0x0070,
2502 0x0126,
2503 0x012c,
2504 0x0246,
2505 0x048d,
2506 0x04d2,
2507};
2508
2509static const u32 chanest_tbl_rev0[] = {
2510 0x44444444,
2511 0x44444444,
2512 0x44444444,
2513 0x44444444,
2514 0x44444444,
2515 0x44444444,
2516 0x44444444,
2517 0x44444444,
2518 0x10101010,
2519 0x10101010,
2520 0x10101010,
2521 0x10101010,
2522 0x10101010,
2523 0x10101010,
2524 0x10101010,
2525 0x10101010,
2526 0x44444444,
2527 0x44444444,
2528 0x44444444,
2529 0x44444444,
2530 0x44444444,
2531 0x44444444,
2532 0x44444444,
2533 0x44444444,
2534 0x10101010,
2535 0x10101010,
2536 0x10101010,
2537 0x10101010,
2538 0x10101010,
2539 0x10101010,
2540 0x10101010,
2541 0x10101010,
2542 0x44444444,
2543 0x44444444,
2544 0x44444444,
2545 0x44444444,
2546 0x44444444,
2547 0x44444444,
2548 0x44444444,
2549 0x44444444,
2550 0x44444444,
2551 0x44444444,
2552 0x44444444,
2553 0x44444444,
2554 0x44444444,
2555 0x44444444,
2556 0x44444444,
2557 0x44444444,
2558 0x10101010,
2559 0x10101010,
2560 0x10101010,
2561 0x10101010,
2562 0x10101010,
2563 0x10101010,
2564 0x10101010,
2565 0x10101010,
2566 0x10101010,
2567 0x10101010,
2568 0x10101010,
2569 0x10101010,
2570 0x10101010,
2571 0x10101010,
2572 0x10101010,
2573 0x10101010,
2574 0x44444444,
2575 0x44444444,
2576 0x44444444,
2577 0x44444444,
2578 0x44444444,
2579 0x44444444,
2580 0x44444444,
2581 0x44444444,
2582 0x44444444,
2583 0x44444444,
2584 0x44444444,
2585 0x44444444,
2586 0x44444444,
2587 0x44444444,
2588 0x44444444,
2589 0x44444444,
2590 0x10101010,
2591 0x10101010,
2592 0x10101010,
2593 0x10101010,
2594 0x10101010,
2595 0x10101010,
2596 0x10101010,
2597 0x10101010,
2598 0x10101010,
2599 0x10101010,
2600 0x10101010,
2601 0x10101010,
2602 0x10101010,
2603 0x10101010,
2604 0x10101010,
2605 0x10101010,
2606};
2607
2608static const u8 mcs_tbl_rev0[] = {
2609 0x00,
2610 0x08,
2611 0x0a,
2612 0x10,
2613 0x12,
2614 0x19,
2615 0x1a,
2616 0x1c,
2617 0x40,
2618 0x48,
2619 0x4a,
2620 0x50,
2621 0x52,
2622 0x59,
2623 0x5a,
2624 0x5c,
2625 0x80,
2626 0x88,
2627 0x8a,
2628 0x90,
2629 0x92,
2630 0x99,
2631 0x9a,
2632 0x9c,
2633 0xc0,
2634 0xc8,
2635 0xca,
2636 0xd0,
2637 0xd2,
2638 0xd9,
2639 0xda,
2640 0xdc,
2641 0x00,
2642 0x00,
2643 0x00,
2644 0x00,
2645 0x00,
2646 0x00,
2647 0x00,
2648 0x00,
2649 0x00,
2650 0x00,
2651 0x00,
2652 0x00,
2653 0x00,
2654 0x00,
2655 0x00,
2656 0x00,
2657 0x00,
2658 0x00,
2659 0x00,
2660 0x00,
2661 0x00,
2662 0x00,
2663 0x00,
2664 0x00,
2665 0x00,
2666 0x00,
2667 0x00,
2668 0x00,
2669 0x00,
2670 0x00,
2671 0x00,
2672 0x00,
2673 0x00,
2674 0x01,
2675 0x02,
2676 0x04,
2677 0x08,
2678 0x09,
2679 0x0a,
2680 0x0c,
2681 0x10,
2682 0x11,
2683 0x12,
2684 0x14,
2685 0x18,
2686 0x19,
2687 0x1a,
2688 0x1c,
2689 0x20,
2690 0x21,
2691 0x22,
2692 0x24,
2693 0x40,
2694 0x41,
2695 0x42,
2696 0x44,
2697 0x48,
2698 0x49,
2699 0x4a,
2700 0x4c,
2701 0x50,
2702 0x51,
2703 0x52,
2704 0x54,
2705 0x58,
2706 0x59,
2707 0x5a,
2708 0x5c,
2709 0x60,
2710 0x61,
2711 0x62,
2712 0x64,
2713 0x00,
2714 0x00,
2715 0x00,
2716 0x00,
2717 0x00,
2718 0x00,
2719 0x00,
2720 0x00,
2721 0x00,
2722 0x00,
2723 0x00,
2724 0x00,
2725 0x00,
2726 0x00,
2727 0x00,
2728 0x00,
2729 0x00,
2730 0x00,
2731 0x00,
2732 0x00,
2733 0x00,
2734 0x00,
2735 0x00,
2736 0x00,
2737};
2738
2739static const u32 noise_var_tbl0_rev0[] = {
2740 0x020c020c,
2741 0x0000014d,
2742 0x020c020c,
2743 0x0000014d,
2744 0x020c020c,
2745 0x0000014d,
2746 0x020c020c,
2747 0x0000014d,
2748 0x020c020c,
2749 0x0000014d,
2750 0x020c020c,
2751 0x0000014d,
2752 0x020c020c,
2753 0x0000014d,
2754 0x020c020c,
2755 0x0000014d,
2756 0x020c020c,
2757 0x0000014d,
2758 0x020c020c,
2759 0x0000014d,
2760 0x020c020c,
2761 0x0000014d,
2762 0x020c020c,
2763 0x0000014d,
2764 0x020c020c,
2765 0x0000014d,
2766 0x020c020c,
2767 0x0000014d,
2768 0x020c020c,
2769 0x0000014d,
2770 0x020c020c,
2771 0x0000014d,
2772 0x020c020c,
2773 0x0000014d,
2774 0x020c020c,
2775 0x0000014d,
2776 0x020c020c,
2777 0x0000014d,
2778 0x020c020c,
2779 0x0000014d,
2780 0x020c020c,
2781 0x0000014d,
2782 0x020c020c,
2783 0x0000014d,
2784 0x020c020c,
2785 0x0000014d,
2786 0x020c020c,
2787 0x0000014d,
2788 0x020c020c,
2789 0x0000014d,
2790 0x020c020c,
2791 0x0000014d,
2792 0x020c020c,
2793 0x0000014d,
2794 0x020c020c,
2795 0x0000014d,
2796 0x020c020c,
2797 0x0000014d,
2798 0x020c020c,
2799 0x0000014d,
2800 0x020c020c,
2801 0x0000014d,
2802 0x020c020c,
2803 0x0000014d,
2804 0x020c020c,
2805 0x0000014d,
2806 0x020c020c,
2807 0x0000014d,
2808 0x020c020c,
2809 0x0000014d,
2810 0x020c020c,
2811 0x0000014d,
2812 0x020c020c,
2813 0x0000014d,
2814 0x020c020c,
2815 0x0000014d,
2816 0x020c020c,
2817 0x0000014d,
2818 0x020c020c,
2819 0x0000014d,
2820 0x020c020c,
2821 0x0000014d,
2822 0x020c020c,
2823 0x0000014d,
2824 0x020c020c,
2825 0x0000014d,
2826 0x020c020c,
2827 0x0000014d,
2828 0x020c020c,
2829 0x0000014d,
2830 0x020c020c,
2831 0x0000014d,
2832 0x020c020c,
2833 0x0000014d,
2834 0x020c020c,
2835 0x0000014d,
2836 0x020c020c,
2837 0x0000014d,
2838 0x020c020c,
2839 0x0000014d,
2840 0x020c020c,
2841 0x0000014d,
2842 0x020c020c,
2843 0x0000014d,
2844 0x020c020c,
2845 0x0000014d,
2846 0x020c020c,
2847 0x0000014d,
2848 0x020c020c,
2849 0x0000014d,
2850 0x020c020c,
2851 0x0000014d,
2852 0x020c020c,
2853 0x0000014d,
2854 0x020c020c,
2855 0x0000014d,
2856 0x020c020c,
2857 0x0000014d,
2858 0x020c020c,
2859 0x0000014d,
2860 0x020c020c,
2861 0x0000014d,
2862 0x020c020c,
2863 0x0000014d,
2864 0x020c020c,
2865 0x0000014d,
2866 0x020c020c,
2867 0x0000014d,
2868 0x020c020c,
2869 0x0000014d,
2870 0x020c020c,
2871 0x0000014d,
2872 0x020c020c,
2873 0x0000014d,
2874 0x020c020c,
2875 0x0000014d,
2876 0x020c020c,
2877 0x0000014d,
2878 0x020c020c,
2879 0x0000014d,
2880 0x020c020c,
2881 0x0000014d,
2882 0x020c020c,
2883 0x0000014d,
2884 0x020c020c,
2885 0x0000014d,
2886 0x020c020c,
2887 0x0000014d,
2888 0x020c020c,
2889 0x0000014d,
2890 0x020c020c,
2891 0x0000014d,
2892 0x020c020c,
2893 0x0000014d,
2894 0x020c020c,
2895 0x0000014d,
2896 0x020c020c,
2897 0x0000014d,
2898 0x020c020c,
2899 0x0000014d,
2900 0x020c020c,
2901 0x0000014d,
2902 0x020c020c,
2903 0x0000014d,
2904 0x020c020c,
2905 0x0000014d,
2906 0x020c020c,
2907 0x0000014d,
2908 0x020c020c,
2909 0x0000014d,
2910 0x020c020c,
2911 0x0000014d,
2912 0x020c020c,
2913 0x0000014d,
2914 0x020c020c,
2915 0x0000014d,
2916 0x020c020c,
2917 0x0000014d,
2918 0x020c020c,
2919 0x0000014d,
2920 0x020c020c,
2921 0x0000014d,
2922 0x020c020c,
2923 0x0000014d,
2924 0x020c020c,
2925 0x0000014d,
2926 0x020c020c,
2927 0x0000014d,
2928 0x020c020c,
2929 0x0000014d,
2930 0x020c020c,
2931 0x0000014d,
2932 0x020c020c,
2933 0x0000014d,
2934 0x020c020c,
2935 0x0000014d,
2936 0x020c020c,
2937 0x0000014d,
2938 0x020c020c,
2939 0x0000014d,
2940 0x020c020c,
2941 0x0000014d,
2942 0x020c020c,
2943 0x0000014d,
2944 0x020c020c,
2945 0x0000014d,
2946 0x020c020c,
2947 0x0000014d,
2948 0x020c020c,
2949 0x0000014d,
2950 0x020c020c,
2951 0x0000014d,
2952 0x020c020c,
2953 0x0000014d,
2954 0x020c020c,
2955 0x0000014d,
2956 0x020c020c,
2957 0x0000014d,
2958 0x020c020c,
2959 0x0000014d,
2960 0x020c020c,
2961 0x0000014d,
2962 0x020c020c,
2963 0x0000014d,
2964 0x020c020c,
2965 0x0000014d,
2966 0x020c020c,
2967 0x0000014d,
2968 0x020c020c,
2969 0x0000014d,
2970 0x020c020c,
2971 0x0000014d,
2972 0x020c020c,
2973 0x0000014d,
2974 0x020c020c,
2975 0x0000014d,
2976 0x020c020c,
2977 0x0000014d,
2978 0x020c020c,
2979 0x0000014d,
2980 0x020c020c,
2981 0x0000014d,
2982 0x020c020c,
2983 0x0000014d,
2984 0x020c020c,
2985 0x0000014d,
2986 0x020c020c,
2987 0x0000014d,
2988 0x020c020c,
2989 0x0000014d,
2990 0x020c020c,
2991 0x0000014d,
2992 0x020c020c,
2993 0x0000014d,
2994 0x020c020c,
2995 0x0000014d,
2996};
2997
2998static const u32 noise_var_tbl1_rev0[] = {
2999 0x020c020c,
3000 0x0000014d,
3001 0x020c020c,
3002 0x0000014d,
3003 0x020c020c,
3004 0x0000014d,
3005 0x020c020c,
3006 0x0000014d,
3007 0x020c020c,
3008 0x0000014d,
3009 0x020c020c,
3010 0x0000014d,
3011 0x020c020c,
3012 0x0000014d,
3013 0x020c020c,
3014 0x0000014d,
3015 0x020c020c,
3016 0x0000014d,
3017 0x020c020c,
3018 0x0000014d,
3019 0x020c020c,
3020 0x0000014d,
3021 0x020c020c,
3022 0x0000014d,
3023 0x020c020c,
3024 0x0000014d,
3025 0x020c020c,
3026 0x0000014d,
3027 0x020c020c,
3028 0x0000014d,
3029 0x020c020c,
3030 0x0000014d,
3031 0x020c020c,
3032 0x0000014d,
3033 0x020c020c,
3034 0x0000014d,
3035 0x020c020c,
3036 0x0000014d,
3037 0x020c020c,
3038 0x0000014d,
3039 0x020c020c,
3040 0x0000014d,
3041 0x020c020c,
3042 0x0000014d,
3043 0x020c020c,
3044 0x0000014d,
3045 0x020c020c,
3046 0x0000014d,
3047 0x020c020c,
3048 0x0000014d,
3049 0x020c020c,
3050 0x0000014d,
3051 0x020c020c,
3052 0x0000014d,
3053 0x020c020c,
3054 0x0000014d,
3055 0x020c020c,
3056 0x0000014d,
3057 0x020c020c,
3058 0x0000014d,
3059 0x020c020c,
3060 0x0000014d,
3061 0x020c020c,
3062 0x0000014d,
3063 0x020c020c,
3064 0x0000014d,
3065 0x020c020c,
3066 0x0000014d,
3067 0x020c020c,
3068 0x0000014d,
3069 0x020c020c,
3070 0x0000014d,
3071 0x020c020c,
3072 0x0000014d,
3073 0x020c020c,
3074 0x0000014d,
3075 0x020c020c,
3076 0x0000014d,
3077 0x020c020c,
3078 0x0000014d,
3079 0x020c020c,
3080 0x0000014d,
3081 0x020c020c,
3082 0x0000014d,
3083 0x020c020c,
3084 0x0000014d,
3085 0x020c020c,
3086 0x0000014d,
3087 0x020c020c,
3088 0x0000014d,
3089 0x020c020c,
3090 0x0000014d,
3091 0x020c020c,
3092 0x0000014d,
3093 0x020c020c,
3094 0x0000014d,
3095 0x020c020c,
3096 0x0000014d,
3097 0x020c020c,
3098 0x0000014d,
3099 0x020c020c,
3100 0x0000014d,
3101 0x020c020c,
3102 0x0000014d,
3103 0x020c020c,
3104 0x0000014d,
3105 0x020c020c,
3106 0x0000014d,
3107 0x020c020c,
3108 0x0000014d,
3109 0x020c020c,
3110 0x0000014d,
3111 0x020c020c,
3112 0x0000014d,
3113 0x020c020c,
3114 0x0000014d,
3115 0x020c020c,
3116 0x0000014d,
3117 0x020c020c,
3118 0x0000014d,
3119 0x020c020c,
3120 0x0000014d,
3121 0x020c020c,
3122 0x0000014d,
3123 0x020c020c,
3124 0x0000014d,
3125 0x020c020c,
3126 0x0000014d,
3127 0x020c020c,
3128 0x0000014d,
3129 0x020c020c,
3130 0x0000014d,
3131 0x020c020c,
3132 0x0000014d,
3133 0x020c020c,
3134 0x0000014d,
3135 0x020c020c,
3136 0x0000014d,
3137 0x020c020c,
3138 0x0000014d,
3139 0x020c020c,
3140 0x0000014d,
3141 0x020c020c,
3142 0x0000014d,
3143 0x020c020c,
3144 0x0000014d,
3145 0x020c020c,
3146 0x0000014d,
3147 0x020c020c,
3148 0x0000014d,
3149 0x020c020c,
3150 0x0000014d,
3151 0x020c020c,
3152 0x0000014d,
3153 0x020c020c,
3154 0x0000014d,
3155 0x020c020c,
3156 0x0000014d,
3157 0x020c020c,
3158 0x0000014d,
3159 0x020c020c,
3160 0x0000014d,
3161 0x020c020c,
3162 0x0000014d,
3163 0x020c020c,
3164 0x0000014d,
3165 0x020c020c,
3166 0x0000014d,
3167 0x020c020c,
3168 0x0000014d,
3169 0x020c020c,
3170 0x0000014d,
3171 0x020c020c,
3172 0x0000014d,
3173 0x020c020c,
3174 0x0000014d,
3175 0x020c020c,
3176 0x0000014d,
3177 0x020c020c,
3178 0x0000014d,
3179 0x020c020c,
3180 0x0000014d,
3181 0x020c020c,
3182 0x0000014d,
3183 0x020c020c,
3184 0x0000014d,
3185 0x020c020c,
3186 0x0000014d,
3187 0x020c020c,
3188 0x0000014d,
3189 0x020c020c,
3190 0x0000014d,
3191 0x020c020c,
3192 0x0000014d,
3193 0x020c020c,
3194 0x0000014d,
3195 0x020c020c,
3196 0x0000014d,
3197 0x020c020c,
3198 0x0000014d,
3199 0x020c020c,
3200 0x0000014d,
3201 0x020c020c,
3202 0x0000014d,
3203 0x020c020c,
3204 0x0000014d,
3205 0x020c020c,
3206 0x0000014d,
3207 0x020c020c,
3208 0x0000014d,
3209 0x020c020c,
3210 0x0000014d,
3211 0x020c020c,
3212 0x0000014d,
3213 0x020c020c,
3214 0x0000014d,
3215 0x020c020c,
3216 0x0000014d,
3217 0x020c020c,
3218 0x0000014d,
3219 0x020c020c,
3220 0x0000014d,
3221 0x020c020c,
3222 0x0000014d,
3223 0x020c020c,
3224 0x0000014d,
3225 0x020c020c,
3226 0x0000014d,
3227 0x020c020c,
3228 0x0000014d,
3229 0x020c020c,
3230 0x0000014d,
3231 0x020c020c,
3232 0x0000014d,
3233 0x020c020c,
3234 0x0000014d,
3235 0x020c020c,
3236 0x0000014d,
3237 0x020c020c,
3238 0x0000014d,
3239 0x020c020c,
3240 0x0000014d,
3241 0x020c020c,
3242 0x0000014d,
3243 0x020c020c,
3244 0x0000014d,
3245 0x020c020c,
3246 0x0000014d,
3247 0x020c020c,
3248 0x0000014d,
3249 0x020c020c,
3250 0x0000014d,
3251 0x020c020c,
3252 0x0000014d,
3253 0x020c020c,
3254 0x0000014d,
3255};
3256
3257static const u8 est_pwr_lut_core0_rev0[] = {
3258 0x50,
3259 0x4f,
3260 0x4e,
3261 0x4d,
3262 0x4c,
3263 0x4b,
3264 0x4a,
3265 0x49,
3266 0x48,
3267 0x47,
3268 0x46,
3269 0x45,
3270 0x44,
3271 0x43,
3272 0x42,
3273 0x41,
3274 0x40,
3275 0x3f,
3276 0x3e,
3277 0x3d,
3278 0x3c,
3279 0x3b,
3280 0x3a,
3281 0x39,
3282 0x38,
3283 0x37,
3284 0x36,
3285 0x35,
3286 0x34,
3287 0x33,
3288 0x32,
3289 0x31,
3290 0x30,
3291 0x2f,
3292 0x2e,
3293 0x2d,
3294 0x2c,
3295 0x2b,
3296 0x2a,
3297 0x29,
3298 0x28,
3299 0x27,
3300 0x26,
3301 0x25,
3302 0x24,
3303 0x23,
3304 0x22,
3305 0x21,
3306 0x20,
3307 0x1f,
3308 0x1e,
3309 0x1d,
3310 0x1c,
3311 0x1b,
3312 0x1a,
3313 0x19,
3314 0x18,
3315 0x17,
3316 0x16,
3317 0x15,
3318 0x14,
3319 0x13,
3320 0x12,
3321 0x11,
3322};
3323
3324static const u8 est_pwr_lut_core1_rev0[] = {
3325 0x50,
3326 0x4f,
3327 0x4e,
3328 0x4d,
3329 0x4c,
3330 0x4b,
3331 0x4a,
3332 0x49,
3333 0x48,
3334 0x47,
3335 0x46,
3336 0x45,
3337 0x44,
3338 0x43,
3339 0x42,
3340 0x41,
3341 0x40,
3342 0x3f,
3343 0x3e,
3344 0x3d,
3345 0x3c,
3346 0x3b,
3347 0x3a,
3348 0x39,
3349 0x38,
3350 0x37,
3351 0x36,
3352 0x35,
3353 0x34,
3354 0x33,
3355 0x32,
3356 0x31,
3357 0x30,
3358 0x2f,
3359 0x2e,
3360 0x2d,
3361 0x2c,
3362 0x2b,
3363 0x2a,
3364 0x29,
3365 0x28,
3366 0x27,
3367 0x26,
3368 0x25,
3369 0x24,
3370 0x23,
3371 0x22,
3372 0x21,
3373 0x20,
3374 0x1f,
3375 0x1e,
3376 0x1d,
3377 0x1c,
3378 0x1b,
3379 0x1a,
3380 0x19,
3381 0x18,
3382 0x17,
3383 0x16,
3384 0x15,
3385 0x14,
3386 0x13,
3387 0x12,
3388 0x11,
3389};
3390
3391static const u8 adj_pwr_lut_core0_rev0[] = {
3392 0x00,
3393 0x00,
3394 0x00,
3395 0x00,
3396 0x00,
3397 0x00,
3398 0x00,
3399 0x00,
3400 0x00,
3401 0x00,
3402 0x00,
3403 0x00,
3404 0x00,
3405 0x00,
3406 0x00,
3407 0x00,
3408 0x00,
3409 0x00,
3410 0x00,
3411 0x00,
3412 0x00,
3413 0x00,
3414 0x00,
3415 0x00,
3416 0x00,
3417 0x00,
3418 0x00,
3419 0x00,
3420 0x00,
3421 0x00,
3422 0x00,
3423 0x00,
3424 0x00,
3425 0x00,
3426 0x00,
3427 0x00,
3428 0x00,
3429 0x00,
3430 0x00,
3431 0x00,
3432 0x00,
3433 0x00,
3434 0x00,
3435 0x00,
3436 0x00,
3437 0x00,
3438 0x00,
3439 0x00,
3440 0x00,
3441 0x00,
3442 0x00,
3443 0x00,
3444 0x00,
3445 0x00,
3446 0x00,
3447 0x00,
3448 0x00,
3449 0x00,
3450 0x00,
3451 0x00,
3452 0x00,
3453 0x00,
3454 0x00,
3455 0x00,
3456 0x00,
3457 0x00,
3458 0x00,
3459 0x00,
3460 0x00,
3461 0x00,
3462 0x00,
3463 0x00,
3464 0x00,
3465 0x00,
3466 0x00,
3467 0x00,
3468 0x00,
3469 0x00,
3470 0x00,
3471 0x00,
3472 0x00,
3473 0x00,
3474 0x00,
3475 0x00,
3476 0x00,
3477 0x00,
3478 0x00,
3479 0x00,
3480 0x00,
3481 0x00,
3482 0x00,
3483 0x00,
3484 0x00,
3485 0x00,
3486 0x00,
3487 0x00,
3488 0x00,
3489 0x00,
3490 0x00,
3491 0x00,
3492 0x00,
3493 0x00,
3494 0x00,
3495 0x00,
3496 0x00,
3497 0x00,
3498 0x00,
3499 0x00,
3500 0x00,
3501 0x00,
3502 0x00,
3503 0x00,
3504 0x00,
3505 0x00,
3506 0x00,
3507 0x00,
3508 0x00,
3509 0x00,
3510 0x00,
3511 0x00,
3512 0x00,
3513 0x00,
3514 0x00,
3515 0x00,
3516 0x00,
3517 0x00,
3518 0x00,
3519 0x00,
3520};
3521
3522static const u8 adj_pwr_lut_core1_rev0[] = {
3523 0x00,
3524 0x00,
3525 0x00,
3526 0x00,
3527 0x00,
3528 0x00,
3529 0x00,
3530 0x00,
3531 0x00,
3532 0x00,
3533 0x00,
3534 0x00,
3535 0x00,
3536 0x00,
3537 0x00,
3538 0x00,
3539 0x00,
3540 0x00,
3541 0x00,
3542 0x00,
3543 0x00,
3544 0x00,
3545 0x00,
3546 0x00,
3547 0x00,
3548 0x00,
3549 0x00,
3550 0x00,
3551 0x00,
3552 0x00,
3553 0x00,
3554 0x00,
3555 0x00,
3556 0x00,
3557 0x00,
3558 0x00,
3559 0x00,
3560 0x00,
3561 0x00,
3562 0x00,
3563 0x00,
3564 0x00,
3565 0x00,
3566 0x00,
3567 0x00,
3568 0x00,
3569 0x00,
3570 0x00,
3571 0x00,
3572 0x00,
3573 0x00,
3574 0x00,
3575 0x00,
3576 0x00,
3577 0x00,
3578 0x00,
3579 0x00,
3580 0x00,
3581 0x00,
3582 0x00,
3583 0x00,
3584 0x00,
3585 0x00,
3586 0x00,
3587 0x00,
3588 0x00,
3589 0x00,
3590 0x00,
3591 0x00,
3592 0x00,
3593 0x00,
3594 0x00,
3595 0x00,
3596 0x00,
3597 0x00,
3598 0x00,
3599 0x00,
3600 0x00,
3601 0x00,
3602 0x00,
3603 0x00,
3604 0x00,
3605 0x00,
3606 0x00,
3607 0x00,
3608 0x00,
3609 0x00,
3610 0x00,
3611 0x00,
3612 0x00,
3613 0x00,
3614 0x00,
3615 0x00,
3616 0x00,
3617 0x00,
3618 0x00,
3619 0x00,
3620 0x00,
3621 0x00,
3622 0x00,
3623 0x00,
3624 0x00,
3625 0x00,
3626 0x00,
3627 0x00,
3628 0x00,
3629 0x00,
3630 0x00,
3631 0x00,
3632 0x00,
3633 0x00,
3634 0x00,
3635 0x00,
3636 0x00,
3637 0x00,
3638 0x00,
3639 0x00,
3640 0x00,
3641 0x00,
3642 0x00,
3643 0x00,
3644 0x00,
3645 0x00,
3646 0x00,
3647 0x00,
3648 0x00,
3649 0x00,
3650 0x00,
3651};
3652
3653static const u32 gainctrl_lut_core0_rev0[] = {
3654 0x03cc2b44,
3655 0x03cc2b42,
3656 0x03cc2b40,
3657 0x03cc2b3e,
3658 0x03cc2b3d,
3659 0x03cc2b3b,
3660 0x03c82b44,
3661 0x03c82b42,
3662 0x03c82b40,
3663 0x03c82b3e,
3664 0x03c82b3d,
3665 0x03c82b3b,
3666 0x03c82b39,
3667 0x03c82b38,
3668 0x03c82b36,
3669 0x03c82b34,
3670 0x03c42b44,
3671 0x03c42b42,
3672 0x03c42b40,
3673 0x03c42b3e,
3674 0x03c42b3d,
3675 0x03c42b3b,
3676 0x03c42b39,
3677 0x03c42b38,
3678 0x03c42b36,
3679 0x03c42b34,
3680 0x03c42b33,
3681 0x03c42b32,
3682 0x03c42b30,
3683 0x03c42b2f,
3684 0x03c42b2d,
3685 0x03c02b44,
3686 0x03c02b42,
3687 0x03c02b40,
3688 0x03c02b3e,
3689 0x03c02b3d,
3690 0x03c02b3b,
3691 0x03c02b39,
3692 0x03c02b38,
3693 0x03c02b36,
3694 0x03c02b34,
3695 0x03b02b44,
3696 0x03b02b42,
3697 0x03b02b40,
3698 0x03b02b3e,
3699 0x03b02b3d,
3700 0x03b02b3b,
3701 0x03b02b39,
3702 0x03b02b38,
3703 0x03b02b36,
3704 0x03b02b34,
3705 0x03b02b33,
3706 0x03b02b32,
3707 0x03b02b30,
3708 0x03b02b2f,
3709 0x03b02b2d,
3710 0x03a02b44,
3711 0x03a02b42,
3712 0x03a02b40,
3713 0x03a02b3e,
3714 0x03a02b3d,
3715 0x03a02b3b,
3716 0x03a02b39,
3717 0x03a02b38,
3718 0x03a02b36,
3719 0x03a02b34,
3720 0x03902b44,
3721 0x03902b42,
3722 0x03902b40,
3723 0x03902b3e,
3724 0x03902b3d,
3725 0x03902b3b,
3726 0x03902b39,
3727 0x03902b38,
3728 0x03902b36,
3729 0x03902b34,
3730 0x03902b33,
3731 0x03902b32,
3732 0x03902b30,
3733 0x03802b44,
3734 0x03802b42,
3735 0x03802b40,
3736 0x03802b3e,
3737 0x03802b3d,
3738 0x03802b3b,
3739 0x03802b39,
3740 0x03802b38,
3741 0x03802b36,
3742 0x03802b34,
3743 0x03802b33,
3744 0x03802b32,
3745 0x03802b30,
3746 0x03802b2f,
3747 0x03802b2d,
3748 0x03802b2c,
3749 0x03802b2b,
3750 0x03802b2a,
3751 0x03802b29,
3752 0x03802b27,
3753 0x03802b26,
3754 0x03802b25,
3755 0x03802b24,
3756 0x03802b23,
3757 0x03802b22,
3758 0x03802b21,
3759 0x03802b20,
3760 0x03802b1f,
3761 0x03802b1e,
3762 0x03802b1e,
3763 0x03802b1d,
3764 0x03802b1c,
3765 0x03802b1b,
3766 0x03802b1a,
3767 0x03802b1a,
3768 0x03802b19,
3769 0x03802b18,
3770 0x03802b18,
3771 0x03802b18,
3772 0x03802b18,
3773 0x03802b18,
3774 0x03802b18,
3775 0x03802b18,
3776 0x03802b18,
3777 0x03802b18,
3778 0x03802b18,
3779 0x03802b18,
3780 0x03802b18,
3781 0x00002b00,
3782};
3783
3784static const u32 gainctrl_lut_core1_rev0[] = {
3785 0x03cc2b44,
3786 0x03cc2b42,
3787 0x03cc2b40,
3788 0x03cc2b3e,
3789 0x03cc2b3d,
3790 0x03cc2b3b,
3791 0x03c82b44,
3792 0x03c82b42,
3793 0x03c82b40,
3794 0x03c82b3e,
3795 0x03c82b3d,
3796 0x03c82b3b,
3797 0x03c82b39,
3798 0x03c82b38,
3799 0x03c82b36,
3800 0x03c82b34,
3801 0x03c42b44,
3802 0x03c42b42,
3803 0x03c42b40,
3804 0x03c42b3e,
3805 0x03c42b3d,
3806 0x03c42b3b,
3807 0x03c42b39,
3808 0x03c42b38,
3809 0x03c42b36,
3810 0x03c42b34,
3811 0x03c42b33,
3812 0x03c42b32,
3813 0x03c42b30,
3814 0x03c42b2f,
3815 0x03c42b2d,
3816 0x03c02b44,
3817 0x03c02b42,
3818 0x03c02b40,
3819 0x03c02b3e,
3820 0x03c02b3d,
3821 0x03c02b3b,
3822 0x03c02b39,
3823 0x03c02b38,
3824 0x03c02b36,
3825 0x03c02b34,
3826 0x03b02b44,
3827 0x03b02b42,
3828 0x03b02b40,
3829 0x03b02b3e,
3830 0x03b02b3d,
3831 0x03b02b3b,
3832 0x03b02b39,
3833 0x03b02b38,
3834 0x03b02b36,
3835 0x03b02b34,
3836 0x03b02b33,
3837 0x03b02b32,
3838 0x03b02b30,
3839 0x03b02b2f,
3840 0x03b02b2d,
3841 0x03a02b44,
3842 0x03a02b42,
3843 0x03a02b40,
3844 0x03a02b3e,
3845 0x03a02b3d,
3846 0x03a02b3b,
3847 0x03a02b39,
3848 0x03a02b38,
3849 0x03a02b36,
3850 0x03a02b34,
3851 0x03902b44,
3852 0x03902b42,
3853 0x03902b40,
3854 0x03902b3e,
3855 0x03902b3d,
3856 0x03902b3b,
3857 0x03902b39,
3858 0x03902b38,
3859 0x03902b36,
3860 0x03902b34,
3861 0x03902b33,
3862 0x03902b32,
3863 0x03902b30,
3864 0x03802b44,
3865 0x03802b42,
3866 0x03802b40,
3867 0x03802b3e,
3868 0x03802b3d,
3869 0x03802b3b,
3870 0x03802b39,
3871 0x03802b38,
3872 0x03802b36,
3873 0x03802b34,
3874 0x03802b33,
3875 0x03802b32,
3876 0x03802b30,
3877 0x03802b2f,
3878 0x03802b2d,
3879 0x03802b2c,
3880 0x03802b2b,
3881 0x03802b2a,
3882 0x03802b29,
3883 0x03802b27,
3884 0x03802b26,
3885 0x03802b25,
3886 0x03802b24,
3887 0x03802b23,
3888 0x03802b22,
3889 0x03802b21,
3890 0x03802b20,
3891 0x03802b1f,
3892 0x03802b1e,
3893 0x03802b1e,
3894 0x03802b1d,
3895 0x03802b1c,
3896 0x03802b1b,
3897 0x03802b1a,
3898 0x03802b1a,
3899 0x03802b19,
3900 0x03802b18,
3901 0x03802b18,
3902 0x03802b18,
3903 0x03802b18,
3904 0x03802b18,
3905 0x03802b18,
3906 0x03802b18,
3907 0x03802b18,
3908 0x03802b18,
3909 0x03802b18,
3910 0x03802b18,
3911 0x03802b18,
3912 0x00002b00,
3913};
3914
3915static const u32 iq_lut_core0_rev0[] = {
3916 0x0000007f,
3917 0x0000007f,
3918 0x0000007f,
3919 0x0000007f,
3920 0x0000007f,
3921 0x0000007f,
3922 0x0000007f,
3923 0x0000007f,
3924 0x0000007f,
3925 0x0000007f,
3926 0x0000007f,
3927 0x0000007f,
3928 0x0000007f,
3929 0x0000007f,
3930 0x0000007f,
3931 0x0000007f,
3932 0x0000007f,
3933 0x0000007f,
3934 0x0000007f,
3935 0x0000007f,
3936 0x0000007f,
3937 0x0000007f,
3938 0x0000007f,
3939 0x0000007f,
3940 0x0000007f,
3941 0x0000007f,
3942 0x0000007f,
3943 0x0000007f,
3944 0x0000007f,
3945 0x0000007f,
3946 0x0000007f,
3947 0x0000007f,
3948 0x0000007f,
3949 0x0000007f,
3950 0x0000007f,
3951 0x0000007f,
3952 0x0000007f,
3953 0x0000007f,
3954 0x0000007f,
3955 0x0000007f,
3956 0x0000007f,
3957 0x0000007f,
3958 0x0000007f,
3959 0x0000007f,
3960 0x0000007f,
3961 0x0000007f,
3962 0x0000007f,
3963 0x0000007f,
3964 0x0000007f,
3965 0x0000007f,
3966 0x0000007f,
3967 0x0000007f,
3968 0x0000007f,
3969 0x0000007f,
3970 0x0000007f,
3971 0x0000007f,
3972 0x0000007f,
3973 0x0000007f,
3974 0x0000007f,
3975 0x0000007f,
3976 0x0000007f,
3977 0x0000007f,
3978 0x0000007f,
3979 0x0000007f,
3980 0x0000007f,
3981 0x0000007f,
3982 0x0000007f,
3983 0x0000007f,
3984 0x0000007f,
3985 0x0000007f,
3986 0x0000007f,
3987 0x0000007f,
3988 0x0000007f,
3989 0x0000007f,
3990 0x0000007f,
3991 0x0000007f,
3992 0x0000007f,
3993 0x0000007f,
3994 0x0000007f,
3995 0x0000007f,
3996 0x0000007f,
3997 0x0000007f,
3998 0x0000007f,
3999 0x0000007f,
4000 0x0000007f,
4001 0x0000007f,
4002 0x0000007f,
4003 0x0000007f,
4004 0x0000007f,
4005 0x0000007f,
4006 0x0000007f,
4007 0x0000007f,
4008 0x0000007f,
4009 0x0000007f,
4010 0x0000007f,
4011 0x0000007f,
4012 0x0000007f,
4013 0x0000007f,
4014 0x0000007f,
4015 0x0000007f,
4016 0x0000007f,
4017 0x0000007f,
4018 0x0000007f,
4019 0x0000007f,
4020 0x0000007f,
4021 0x0000007f,
4022 0x0000007f,
4023 0x0000007f,
4024 0x0000007f,
4025 0x0000007f,
4026 0x0000007f,
4027 0x0000007f,
4028 0x0000007f,
4029 0x0000007f,
4030 0x0000007f,
4031 0x0000007f,
4032 0x0000007f,
4033 0x0000007f,
4034 0x0000007f,
4035 0x0000007f,
4036 0x0000007f,
4037 0x0000007f,
4038 0x0000007f,
4039 0x0000007f,
4040 0x0000007f,
4041 0x0000007f,
4042 0x0000007f,
4043 0x0000007f,
4044};
4045
4046static const u32 iq_lut_core1_rev0[] = {
4047 0x0000007f,
4048 0x0000007f,
4049 0x0000007f,
4050 0x0000007f,
4051 0x0000007f,
4052 0x0000007f,
4053 0x0000007f,
4054 0x0000007f,
4055 0x0000007f,
4056 0x0000007f,
4057 0x0000007f,
4058 0x0000007f,
4059 0x0000007f,
4060 0x0000007f,
4061 0x0000007f,
4062 0x0000007f,
4063 0x0000007f,
4064 0x0000007f,
4065 0x0000007f,
4066 0x0000007f,
4067 0x0000007f,
4068 0x0000007f,
4069 0x0000007f,
4070 0x0000007f,
4071 0x0000007f,
4072 0x0000007f,
4073 0x0000007f,
4074 0x0000007f,
4075 0x0000007f,
4076 0x0000007f,
4077 0x0000007f,
4078 0x0000007f,
4079 0x0000007f,
4080 0x0000007f,
4081 0x0000007f,
4082 0x0000007f,
4083 0x0000007f,
4084 0x0000007f,
4085 0x0000007f,
4086 0x0000007f,
4087 0x0000007f,
4088 0x0000007f,
4089 0x0000007f,
4090 0x0000007f,
4091 0x0000007f,
4092 0x0000007f,
4093 0x0000007f,
4094 0x0000007f,
4095 0x0000007f,
4096 0x0000007f,
4097 0x0000007f,
4098 0x0000007f,
4099 0x0000007f,
4100 0x0000007f,
4101 0x0000007f,
4102 0x0000007f,
4103 0x0000007f,
4104 0x0000007f,
4105 0x0000007f,
4106 0x0000007f,
4107 0x0000007f,
4108 0x0000007f,
4109 0x0000007f,
4110 0x0000007f,
4111 0x0000007f,
4112 0x0000007f,
4113 0x0000007f,
4114 0x0000007f,
4115 0x0000007f,
4116 0x0000007f,
4117 0x0000007f,
4118 0x0000007f,
4119 0x0000007f,
4120 0x0000007f,
4121 0x0000007f,
4122 0x0000007f,
4123 0x0000007f,
4124 0x0000007f,
4125 0x0000007f,
4126 0x0000007f,
4127 0x0000007f,
4128 0x0000007f,
4129 0x0000007f,
4130 0x0000007f,
4131 0x0000007f,
4132 0x0000007f,
4133 0x0000007f,
4134 0x0000007f,
4135 0x0000007f,
4136 0x0000007f,
4137 0x0000007f,
4138 0x0000007f,
4139 0x0000007f,
4140 0x0000007f,
4141 0x0000007f,
4142 0x0000007f,
4143 0x0000007f,
4144 0x0000007f,
4145 0x0000007f,
4146 0x0000007f,
4147 0x0000007f,
4148 0x0000007f,
4149 0x0000007f,
4150 0x0000007f,
4151 0x0000007f,
4152 0x0000007f,
4153 0x0000007f,
4154 0x0000007f,
4155 0x0000007f,
4156 0x0000007f,
4157 0x0000007f,
4158 0x0000007f,
4159 0x0000007f,
4160 0x0000007f,
4161 0x0000007f,
4162 0x0000007f,
4163 0x0000007f,
4164 0x0000007f,
4165 0x0000007f,
4166 0x0000007f,
4167 0x0000007f,
4168 0x0000007f,
4169 0x0000007f,
4170 0x0000007f,
4171 0x0000007f,
4172 0x0000007f,
4173 0x0000007f,
4174 0x0000007f,
4175};
4176
4177static const u16 loft_lut_core0_rev0[] = {
4178 0x0000,
4179 0x0101,
4180 0x0002,
4181 0x0103,
4182 0x0000,
4183 0x0101,
4184 0x0002,
4185 0x0103,
4186 0x0000,
4187 0x0101,
4188 0x0002,
4189 0x0103,
4190 0x0000,
4191 0x0101,
4192 0x0002,
4193 0x0103,
4194 0x0000,
4195 0x0101,
4196 0x0002,
4197 0x0103,
4198 0x0000,
4199 0x0101,
4200 0x0002,
4201 0x0103,
4202 0x0000,
4203 0x0101,
4204 0x0002,
4205 0x0103,
4206 0x0000,
4207 0x0101,
4208 0x0002,
4209 0x0103,
4210 0x0000,
4211 0x0101,
4212 0x0002,
4213 0x0103,
4214 0x0000,
4215 0x0101,
4216 0x0002,
4217 0x0103,
4218 0x0000,
4219 0x0101,
4220 0x0002,
4221 0x0103,
4222 0x0000,
4223 0x0101,
4224 0x0002,
4225 0x0103,
4226 0x0000,
4227 0x0101,
4228 0x0002,
4229 0x0103,
4230 0x0000,
4231 0x0101,
4232 0x0002,
4233 0x0103,
4234 0x0000,
4235 0x0101,
4236 0x0002,
4237 0x0103,
4238 0x0000,
4239 0x0101,
4240 0x0002,
4241 0x0103,
4242 0x0000,
4243 0x0101,
4244 0x0002,
4245 0x0103,
4246 0x0000,
4247 0x0101,
4248 0x0002,
4249 0x0103,
4250 0x0000,
4251 0x0101,
4252 0x0002,
4253 0x0103,
4254 0x0000,
4255 0x0101,
4256 0x0002,
4257 0x0103,
4258 0x0000,
4259 0x0101,
4260 0x0002,
4261 0x0103,
4262 0x0000,
4263 0x0101,
4264 0x0002,
4265 0x0103,
4266 0x0000,
4267 0x0101,
4268 0x0002,
4269 0x0103,
4270 0x0000,
4271 0x0101,
4272 0x0002,
4273 0x0103,
4274 0x0000,
4275 0x0101,
4276 0x0002,
4277 0x0103,
4278 0x0000,
4279 0x0101,
4280 0x0002,
4281 0x0103,
4282 0x0000,
4283 0x0101,
4284 0x0002,
4285 0x0103,
4286 0x0000,
4287 0x0101,
4288 0x0002,
4289 0x0103,
4290 0x0000,
4291 0x0101,
4292 0x0002,
4293 0x0103,
4294 0x0000,
4295 0x0101,
4296 0x0002,
4297 0x0103,
4298 0x0000,
4299 0x0101,
4300 0x0002,
4301 0x0103,
4302 0x0000,
4303 0x0101,
4304 0x0002,
4305 0x0103,
4306};
4307
4308static const u16 loft_lut_core1_rev0[] = {
4309 0x0000,
4310 0x0101,
4311 0x0002,
4312 0x0103,
4313 0x0000,
4314 0x0101,
4315 0x0002,
4316 0x0103,
4317 0x0000,
4318 0x0101,
4319 0x0002,
4320 0x0103,
4321 0x0000,
4322 0x0101,
4323 0x0002,
4324 0x0103,
4325 0x0000,
4326 0x0101,
4327 0x0002,
4328 0x0103,
4329 0x0000,
4330 0x0101,
4331 0x0002,
4332 0x0103,
4333 0x0000,
4334 0x0101,
4335 0x0002,
4336 0x0103,
4337 0x0000,
4338 0x0101,
4339 0x0002,
4340 0x0103,
4341 0x0000,
4342 0x0101,
4343 0x0002,
4344 0x0103,
4345 0x0000,
4346 0x0101,
4347 0x0002,
4348 0x0103,
4349 0x0000,
4350 0x0101,
4351 0x0002,
4352 0x0103,
4353 0x0000,
4354 0x0101,
4355 0x0002,
4356 0x0103,
4357 0x0000,
4358 0x0101,
4359 0x0002,
4360 0x0103,
4361 0x0000,
4362 0x0101,
4363 0x0002,
4364 0x0103,
4365 0x0000,
4366 0x0101,
4367 0x0002,
4368 0x0103,
4369 0x0000,
4370 0x0101,
4371 0x0002,
4372 0x0103,
4373 0x0000,
4374 0x0101,
4375 0x0002,
4376 0x0103,
4377 0x0000,
4378 0x0101,
4379 0x0002,
4380 0x0103,
4381 0x0000,
4382 0x0101,
4383 0x0002,
4384 0x0103,
4385 0x0000,
4386 0x0101,
4387 0x0002,
4388 0x0103,
4389 0x0000,
4390 0x0101,
4391 0x0002,
4392 0x0103,
4393 0x0000,
4394 0x0101,
4395 0x0002,
4396 0x0103,
4397 0x0000,
4398 0x0101,
4399 0x0002,
4400 0x0103,
4401 0x0000,
4402 0x0101,
4403 0x0002,
4404 0x0103,
4405 0x0000,
4406 0x0101,
4407 0x0002,
4408 0x0103,
4409 0x0000,
4410 0x0101,
4411 0x0002,
4412 0x0103,
4413 0x0000,
4414 0x0101,
4415 0x0002,
4416 0x0103,
4417 0x0000,
4418 0x0101,
4419 0x0002,
4420 0x0103,
4421 0x0000,
4422 0x0101,
4423 0x0002,
4424 0x0103,
4425 0x0000,
4426 0x0101,
4427 0x0002,
4428 0x0103,
4429 0x0000,
4430 0x0101,
4431 0x0002,
4432 0x0103,
4433 0x0000,
4434 0x0101,
4435 0x0002,
4436 0x0103,
4437};
4438
4439const struct phytbl_info mimophytbl_info_rev0_volatile[] = {
4440 {&bdi_tbl_rev0, sizeof(bdi_tbl_rev0) / sizeof(bdi_tbl_rev0[0]), 21, 0,
4441 16}
4442 ,
4443 {&pltlut_tbl_rev0, sizeof(pltlut_tbl_rev0) / sizeof(pltlut_tbl_rev0[0]),
4444 20, 0, 32}
4445 ,
4446 {&gainctrl_lut_core0_rev0,
4447 sizeof(gainctrl_lut_core0_rev0) / sizeof(gainctrl_lut_core0_rev0[0]),
4448 26, 192, 32}
4449 ,
4450 {&gainctrl_lut_core1_rev0,
4451 sizeof(gainctrl_lut_core1_rev0) / sizeof(gainctrl_lut_core1_rev0[0]),
4452 27, 192, 32}
4453 ,
4454
4455 {&est_pwr_lut_core0_rev0,
4456 sizeof(est_pwr_lut_core0_rev0) / sizeof(est_pwr_lut_core0_rev0[0]), 26,
4457 0, 8}
4458 ,
4459 {&est_pwr_lut_core1_rev0,
4460 sizeof(est_pwr_lut_core1_rev0) / sizeof(est_pwr_lut_core1_rev0[0]), 27,
4461 0, 8}
4462 ,
4463 {&adj_pwr_lut_core0_rev0,
4464 sizeof(adj_pwr_lut_core0_rev0) / sizeof(adj_pwr_lut_core0_rev0[0]), 26,
4465 64, 8}
4466 ,
4467 {&adj_pwr_lut_core1_rev0,
4468 sizeof(adj_pwr_lut_core1_rev0) / sizeof(adj_pwr_lut_core1_rev0[0]), 27,
4469 64, 8}
4470 ,
4471 {&iq_lut_core0_rev0,
4472 sizeof(iq_lut_core0_rev0) / sizeof(iq_lut_core0_rev0[0]), 26, 320, 32}
4473 ,
4474 {&iq_lut_core1_rev0,
4475 sizeof(iq_lut_core1_rev0) / sizeof(iq_lut_core1_rev0[0]), 27, 320, 32}
4476 ,
4477 {&loft_lut_core0_rev0,
4478 sizeof(loft_lut_core0_rev0) / sizeof(loft_lut_core0_rev0[0]), 26, 448,
4479 16}
4480 ,
4481 {&loft_lut_core1_rev0,
4482 sizeof(loft_lut_core1_rev0) / sizeof(loft_lut_core1_rev0[0]), 27, 448,
4483 16}
4484 ,
4485};
4486
4487const struct phytbl_info mimophytbl_info_rev0[] = {
4488 {&frame_struct_rev0,
4489 sizeof(frame_struct_rev0) / sizeof(frame_struct_rev0[0]), 10, 0, 32}
4490 ,
4491 {&frame_lut_rev0, sizeof(frame_lut_rev0) / sizeof(frame_lut_rev0[0]),
4492 24, 0, 8}
4493 ,
4494 {&tmap_tbl_rev0, sizeof(tmap_tbl_rev0) / sizeof(tmap_tbl_rev0[0]), 12,
4495 0, 32}
4496 ,
4497 {&tdtrn_tbl_rev0, sizeof(tdtrn_tbl_rev0) / sizeof(tdtrn_tbl_rev0[0]),
4498 14, 0, 32}
4499 ,
4500 {&intlv_tbl_rev0, sizeof(intlv_tbl_rev0) / sizeof(intlv_tbl_rev0[0]),
4501 13, 0, 32}
4502 ,
4503 {&pilot_tbl_rev0, sizeof(pilot_tbl_rev0) / sizeof(pilot_tbl_rev0[0]),
4504 11, 0, 16}
4505 ,
4506 {&tdi_tbl20_ant0_rev0,
4507 sizeof(tdi_tbl20_ant0_rev0) / sizeof(tdi_tbl20_ant0_rev0[0]), 19, 128,
4508 32}
4509 ,
4510 {&tdi_tbl20_ant1_rev0,
4511 sizeof(tdi_tbl20_ant1_rev0) / sizeof(tdi_tbl20_ant1_rev0[0]), 19, 256,
4512 32}
4513 ,
4514 {&tdi_tbl40_ant0_rev0,
4515 sizeof(tdi_tbl40_ant0_rev0) / sizeof(tdi_tbl40_ant0_rev0[0]), 19, 640,
4516 32}
4517 ,
4518 {&tdi_tbl40_ant1_rev0,
4519 sizeof(tdi_tbl40_ant1_rev0) / sizeof(tdi_tbl40_ant1_rev0[0]), 19, 768,
4520 32}
4521 ,
4522 {&chanest_tbl_rev0,
4523 sizeof(chanest_tbl_rev0) / sizeof(chanest_tbl_rev0[0]), 22, 0, 32}
4524 ,
4525 {&mcs_tbl_rev0, sizeof(mcs_tbl_rev0) / sizeof(mcs_tbl_rev0[0]), 18, 0,
4526 8}
4527 ,
4528 {&noise_var_tbl0_rev0,
4529 sizeof(noise_var_tbl0_rev0) / sizeof(noise_var_tbl0_rev0[0]), 16, 0,
4530 32}
4531 ,
4532 {&noise_var_tbl1_rev0,
4533 sizeof(noise_var_tbl1_rev0) / sizeof(noise_var_tbl1_rev0[0]), 16, 128,
4534 32}
4535 ,
4536};
4537
4538const u32 mimophytbl_info_sz_rev0 =
4539 sizeof(mimophytbl_info_rev0) / sizeof(mimophytbl_info_rev0[0]);
4540const u32 mimophytbl_info_sz_rev0_volatile =
4541 sizeof(mimophytbl_info_rev0_volatile) /
4542 sizeof(mimophytbl_info_rev0_volatile[0]);
4543
4544static const u16 ant_swctrl_tbl_rev3[] = {
4545 0x0082,
4546 0x0082,
4547 0x0211,
4548 0x0222,
4549 0x0328,
4550 0x0000,
4551 0x0000,
4552 0x0000,
4553 0x0144,
4554 0x0000,
4555 0x0000,
4556 0x0000,
4557 0x0188,
4558 0x0000,
4559 0x0000,
4560 0x0000,
4561 0x0082,
4562 0x0082,
4563 0x0211,
4564 0x0222,
4565 0x0328,
4566 0x0000,
4567 0x0000,
4568 0x0000,
4569 0x0144,
4570 0x0000,
4571 0x0000,
4572 0x0000,
4573 0x0188,
4574 0x0000,
4575 0x0000,
4576 0x0000,
4577};
4578
4579static const u16 ant_swctrl_tbl_rev3_1[] = {
4580 0x0022,
4581 0x0022,
4582 0x0011,
4583 0x0022,
4584 0x0022,
4585 0x0000,
4586 0x0000,
4587 0x0000,
4588 0x0011,
4589 0x0000,
4590 0x0000,
4591 0x0000,
4592 0x0022,
4593 0x0000,
4594 0x0000,
4595 0x0000,
4596 0x0022,
4597 0x0022,
4598 0x0011,
4599 0x0022,
4600 0x0022,
4601 0x0000,
4602 0x0000,
4603 0x0000,
4604 0x0011,
4605 0x0000,
4606 0x0000,
4607 0x0000,
4608 0x0022,
4609 0x0000,
4610 0x0000,
4611 0x0000,
4612};
4613
4614static const u16 ant_swctrl_tbl_rev3_2[] = {
4615 0x0088,
4616 0x0088,
4617 0x0044,
4618 0x0088,
4619 0x0088,
4620 0x0000,
4621 0x0000,
4622 0x0000,
4623 0x0044,
4624 0x0000,
4625 0x0000,
4626 0x0000,
4627 0x0088,
4628 0x0000,
4629 0x0000,
4630 0x0000,
4631 0x0088,
4632 0x0088,
4633 0x0044,
4634 0x0088,
4635 0x0088,
4636 0x0000,
4637 0x0000,
4638 0x0000,
4639 0x0044,
4640 0x0000,
4641 0x0000,
4642 0x0000,
4643 0x0088,
4644 0x0000,
4645 0x0000,
4646 0x0000,
4647};
4648
4649static const u16 ant_swctrl_tbl_rev3_3[] = {
4650 0x022,
4651 0x022,
4652 0x011,
4653 0x022,
4654 0x000,
4655 0x000,
4656 0x000,
4657 0x000,
4658 0x011,
4659 0x000,
4660 0x000,
4661 0x000,
4662 0x022,
4663 0x000,
4664 0x000,
4665 0x3cc,
4666 0x022,
4667 0x022,
4668 0x011,
4669 0x022,
4670 0x000,
4671 0x000,
4672 0x000,
4673 0x000,
4674 0x011,
4675 0x000,
4676 0x000,
4677 0x000,
4678 0x022,
4679 0x000,
4680 0x000,
4681 0x3cc
4682};
4683
4684static const u32 frame_struct_rev3[] = {
4685 0x08004a04,
4686 0x00100000,
4687 0x01000a05,
4688 0x00100020,
4689 0x09804506,
4690 0x00100030,
4691 0x09804507,
4692 0x00100030,
4693 0x00000000,
4694 0x00000000,
4695 0x00000000,
4696 0x00000000,
4697 0x00000000,
4698 0x00000000,
4699 0x00000000,
4700 0x00000000,
4701 0x08004a0c,
4702 0x00100004,
4703 0x01000a0d,
4704 0x00100024,
4705 0x0980450e,
4706 0x00100034,
4707 0x0980450f,
4708 0x00100034,
4709 0x00000000,
4710 0x00000000,
4711 0x00000000,
4712 0x00000000,
4713 0x00000000,
4714 0x00000000,
4715 0x00000000,
4716 0x00000000,
4717 0x00000a04,
4718 0x00100000,
4719 0x11008a05,
4720 0x00100020,
4721 0x1980c506,
4722 0x00100030,
4723 0x21810506,
4724 0x00100030,
4725 0x21810506,
4726 0x00100030,
4727 0x01800504,
4728 0x00100030,
4729 0x11808505,
4730 0x00100030,
4731 0x29814507,
4732 0x01100030,
4733 0x00000a04,
4734 0x00100000,
4735 0x11008a05,
4736 0x00100020,
4737 0x21810506,
4738 0x00100030,
4739 0x21810506,
4740 0x00100030,
4741 0x29814507,
4742 0x01100030,
4743 0x00000000,
4744 0x00000000,
4745 0x00000000,
4746 0x00000000,
4747 0x00000000,
4748 0x00000000,
4749 0x00000a0c,
4750 0x00100008,
4751 0x11008a0d,
4752 0x00100028,
4753 0x1980c50e,
4754 0x00100038,
4755 0x2181050e,
4756 0x00100038,
4757 0x2181050e,
4758 0x00100038,
4759 0x0180050c,
4760 0x00100038,
4761 0x1180850d,
4762 0x00100038,
4763 0x2981450f,
4764 0x01100038,
4765 0x00000a0c,
4766 0x00100008,
4767 0x11008a0d,
4768 0x00100028,
4769 0x2181050e,
4770 0x00100038,
4771 0x2181050e,
4772 0x00100038,
4773 0x2981450f,
4774 0x01100038,
4775 0x00000000,
4776 0x00000000,
4777 0x00000000,
4778 0x00000000,
4779 0x00000000,
4780 0x00000000,
4781 0x08004a04,
4782 0x00100000,
4783 0x01000a05,
4784 0x00100020,
4785 0x1980c506,
4786 0x00100030,
4787 0x1980c506,
4788 0x00100030,
4789 0x11808504,
4790 0x00100030,
4791 0x3981ca05,
4792 0x00100030,
4793 0x29814507,
4794 0x01100030,
4795 0x00000000,
4796 0x00000000,
4797 0x10008a04,
4798 0x00100000,
4799 0x3981ca05,
4800 0x00100030,
4801 0x1980c506,
4802 0x00100030,
4803 0x29814507,
4804 0x01100030,
4805 0x00000000,
4806 0x00000000,
4807 0x00000000,
4808 0x00000000,
4809 0x00000000,
4810 0x00000000,
4811 0x00000000,
4812 0x00000000,
4813 0x08004a0c,
4814 0x00100008,
4815 0x01000a0d,
4816 0x00100028,
4817 0x1980c50e,
4818 0x00100038,
4819 0x1980c50e,
4820 0x00100038,
4821 0x1180850c,
4822 0x00100038,
4823 0x3981ca0d,
4824 0x00100038,
4825 0x2981450f,
4826 0x01100038,
4827 0x00000000,
4828 0x00000000,
4829 0x10008a0c,
4830 0x00100008,
4831 0x3981ca0d,
4832 0x00100038,
4833 0x1980c50e,
4834 0x00100038,
4835 0x2981450f,
4836 0x01100038,
4837 0x00000000,
4838 0x00000000,
4839 0x00000000,
4840 0x00000000,
4841 0x00000000,
4842 0x00000000,
4843 0x00000000,
4844 0x00000000,
4845 0x40021404,
4846 0x00100000,
4847 0x02001405,
4848 0x00100040,
4849 0x0b004a06,
4850 0x01900060,
4851 0x13008a06,
4852 0x01900060,
4853 0x13008a06,
4854 0x01900060,
4855 0x43020a04,
4856 0x00100060,
4857 0x1b00ca05,
4858 0x00100060,
4859 0x23010a07,
4860 0x01500060,
4861 0x40021404,
4862 0x00100000,
4863 0x1a00d405,
4864 0x00100040,
4865 0x13008a06,
4866 0x01900060,
4867 0x13008a06,
4868 0x01900060,
4869 0x23010a07,
4870 0x01500060,
4871 0x00000000,
4872 0x00000000,
4873 0x00000000,
4874 0x00000000,
4875 0x00000000,
4876 0x00000000,
4877 0x4002140c,
4878 0x00100010,
4879 0x0200140d,
4880 0x00100050,
4881 0x0b004a0e,
4882 0x01900070,
4883 0x13008a0e,
4884 0x01900070,
4885 0x13008a0e,
4886 0x01900070,
4887 0x43020a0c,
4888 0x00100070,
4889 0x1b00ca0d,
4890 0x00100070,
4891 0x23010a0f,
4892 0x01500070,
4893 0x4002140c,
4894 0x00100010,
4895 0x1a00d40d,
4896 0x00100050,
4897 0x13008a0e,
4898 0x01900070,
4899 0x13008a0e,
4900 0x01900070,
4901 0x23010a0f,
4902 0x01500070,
4903 0x00000000,
4904 0x00000000,
4905 0x00000000,
4906 0x00000000,
4907 0x00000000,
4908 0x00000000,
4909 0x50029404,
4910 0x00100000,
4911 0x32019405,
4912 0x00100040,
4913 0x0b004a06,
4914 0x01900060,
4915 0x0b004a06,
4916 0x01900060,
4917 0x5b02ca04,
4918 0x00100060,
4919 0x3b01d405,
4920 0x00100060,
4921 0x23010a07,
4922 0x01500060,
4923 0x00000000,
4924 0x00000000,
4925 0x5802d404,
4926 0x00100000,
4927 0x3b01d405,
4928 0x00100060,
4929 0x0b004a06,
4930 0x01900060,
4931 0x23010a07,
4932 0x01500060,
4933 0x00000000,
4934 0x00000000,
4935 0x00000000,
4936 0x00000000,
4937 0x00000000,
4938 0x00000000,
4939 0x00000000,
4940 0x00000000,
4941 0x5002940c,
4942 0x00100010,
4943 0x3201940d,
4944 0x00100050,
4945 0x0b004a0e,
4946 0x01900070,
4947 0x0b004a0e,
4948 0x01900070,
4949 0x5b02ca0c,
4950 0x00100070,
4951 0x3b01d40d,
4952 0x00100070,
4953 0x23010a0f,
4954 0x01500070,
4955 0x00000000,
4956 0x00000000,
4957 0x5802d40c,
4958 0x00100010,
4959 0x3b01d40d,
4960 0x00100070,
4961 0x0b004a0e,
4962 0x01900070,
4963 0x23010a0f,
4964 0x01500070,
4965 0x00000000,
4966 0x00000000,
4967 0x00000000,
4968 0x00000000,
4969 0x00000000,
4970 0x00000000,
4971 0x00000000,
4972 0x00000000,
4973 0x40021404,
4974 0x000f4800,
4975 0x62031405,
4976 0x00100040,
4977 0x53028a06,
4978 0x01900060,
4979 0x53028a07,
4980 0x01900060,
4981 0x00000000,
4982 0x00000000,
4983 0x00000000,
4984 0x00000000,
4985 0x00000000,
4986 0x00000000,
4987 0x00000000,
4988 0x00000000,
4989 0x4002140c,
4990 0x000f4808,
4991 0x6203140d,
4992 0x00100048,
4993 0x53028a0e,
4994 0x01900068,
4995 0x53028a0f,
4996 0x01900068,
4997 0x00000000,
4998 0x00000000,
4999 0x00000000,
5000 0x00000000,
5001 0x00000000,
5002 0x00000000,
5003 0x00000000,
5004 0x00000000,
5005 0x00000a0c,
5006 0x00100004,
5007 0x11008a0d,
5008 0x00100024,
5009 0x1980c50e,
5010 0x00100034,
5011 0x2181050e,
5012 0x00100034,
5013 0x2181050e,
5014 0x00100034,
5015 0x0180050c,
5016 0x00100038,
5017 0x1180850d,
5018 0x00100038,
5019 0x1181850d,
5020 0x00100038,
5021 0x2981450f,
5022 0x01100038,
5023 0x00000000,
5024 0x00000000,
5025 0x00000000,
5026 0x00000000,
5027 0x00000000,
5028 0x00000000,
5029 0x00000000,
5030 0x00000000,
5031 0x00000000,
5032 0x00000000,
5033 0x00000000,
5034 0x00000000,
5035 0x00000000,
5036 0x00000000,
5037 0x00000a0c,
5038 0x00100008,
5039 0x11008a0d,
5040 0x00100028,
5041 0x2181050e,
5042 0x00100038,
5043 0x2181050e,
5044 0x00100038,
5045 0x1181850d,
5046 0x00100038,
5047 0x2981450f,
5048 0x01100038,
5049 0x00000000,
5050 0x00000000,
5051 0x00000000,
5052 0x00000000,
5053 0x00000000,
5054 0x00000000,
5055 0x00000000,
5056 0x00000000,
5057 0x00000000,
5058 0x00000000,
5059 0x00000000,
5060 0x00000000,
5061 0x00000000,
5062 0x00000000,
5063 0x00000000,
5064 0x00000000,
5065 0x00000000,
5066 0x00000000,
5067 0x00000000,
5068 0x00000000,
5069 0x08004a04,
5070 0x00100000,
5071 0x01000a05,
5072 0x00100020,
5073 0x0180c506,
5074 0x00100030,
5075 0x0180c506,
5076 0x00100030,
5077 0x2180c50c,
5078 0x00100030,
5079 0x49820a0d,
5080 0x0016a130,
5081 0x41824a0d,
5082 0x0016a130,
5083 0x2981450f,
5084 0x01100030,
5085 0x00000000,
5086 0x00000000,
5087 0x00000000,
5088 0x00000000,
5089 0x00000000,
5090 0x00000000,
5091 0x00000000,
5092 0x00000000,
5093 0x00000000,
5094 0x00000000,
5095 0x00000000,
5096 0x00000000,
5097 0x00000000,
5098 0x00000000,
5099 0x00000000,
5100 0x00000000,
5101 0x2000ca0c,
5102 0x00100000,
5103 0x49820a0d,
5104 0x0016a130,
5105 0x1980c50e,
5106 0x00100030,
5107 0x41824a0d,
5108 0x0016a130,
5109 0x2981450f,
5110 0x01100030,
5111 0x00000000,
5112 0x00000000,
5113 0x00000000,
5114 0x00000000,
5115 0x00000000,
5116 0x00000000,
5117 0x00000000,
5118 0x00000000,
5119 0x00000000,
5120 0x00000000,
5121 0x00000000,
5122 0x00000000,
5123 0x00000000,
5124 0x00000000,
5125 0x00000000,
5126 0x00000000,
5127 0x00000000,
5128 0x00000000,
5129 0x00000000,
5130 0x00000000,
5131 0x00000000,
5132 0x00000000,
5133 0x4002140c,
5134 0x00100008,
5135 0x0200140d,
5136 0x00100048,
5137 0x0b004a0e,
5138 0x01900068,
5139 0x13008a0e,
5140 0x01900068,
5141 0x13008a0e,
5142 0x01900068,
5143 0x43020a0c,
5144 0x00100070,
5145 0x1b00ca0d,
5146 0x00100070,
5147 0x1b014a0d,
5148 0x00100070,
5149 0x23010a0f,
5150 0x01500070,
5151 0x00000000,
5152 0x00000000,
5153 0x00000000,
5154 0x00000000,
5155 0x00000000,
5156 0x00000000,
5157 0x00000000,
5158 0x00000000,
5159 0x00000000,
5160 0x00000000,
5161 0x00000000,
5162 0x00000000,
5163 0x00000000,
5164 0x00000000,
5165 0x4002140c,
5166 0x00100010,
5167 0x1a00d40d,
5168 0x00100050,
5169 0x13008a0e,
5170 0x01900070,
5171 0x13008a0e,
5172 0x01900070,
5173 0x1b014a0d,
5174 0x00100070,
5175 0x23010a0f,
5176 0x01500070,
5177 0x00000000,
5178 0x00000000,
5179 0x00000000,
5180 0x00000000,
5181 0x00000000,
5182 0x00000000,
5183 0x00000000,
5184 0x00000000,
5185 0x00000000,
5186 0x00000000,
5187 0x00000000,
5188 0x00000000,
5189 0x00000000,
5190 0x00000000,
5191 0x00000000,
5192 0x00000000,
5193 0x00000000,
5194 0x00000000,
5195 0x00000000,
5196 0x00000000,
5197 0x50029404,
5198 0x00100000,
5199 0x32019405,
5200 0x00100040,
5201 0x03004a06,
5202 0x01900060,
5203 0x03004a06,
5204 0x01900060,
5205 0x6b030a0c,
5206 0x00100060,
5207 0x4b02140d,
5208 0x0016a160,
5209 0x4302540d,
5210 0x0016a160,
5211 0x23010a0f,
5212 0x01500060,
5213 0x00000000,
5214 0x00000000,
5215 0x00000000,
5216 0x00000000,
5217 0x00000000,
5218 0x00000000,
5219 0x00000000,
5220 0x00000000,
5221 0x00000000,
5222 0x00000000,
5223 0x00000000,
5224 0x00000000,
5225 0x00000000,
5226 0x00000000,
5227 0x00000000,
5228 0x00000000,
5229 0x6b03140c,
5230 0x00100060,
5231 0x4b02140d,
5232 0x0016a160,
5233 0x0b004a0e,
5234 0x01900060,
5235 0x4302540d,
5236 0x0016a160,
5237 0x23010a0f,
5238 0x01500060,
5239 0x00000000,
5240 0x00000000,
5241 0x00000000,
5242 0x00000000,
5243 0x00000000,
5244 0x00000000,
5245 0x00000000,
5246 0x00000000,
5247 0x00000000,
5248 0x00000000,
5249 0x00000000,
5250 0x00000000,
5251 0x00000000,
5252 0x00000000,
5253 0x00000000,
5254 0x00000000,
5255 0x00000000,
5256 0x00000000,
5257 0x00000000,
5258 0x00000000,
5259 0x00000000,
5260 0x00000000,
5261 0x40021404,
5262 0x00100000,
5263 0x1a00d405,
5264 0x00100040,
5265 0x53028a06,
5266 0x01900060,
5267 0x5b02ca06,
5268 0x01900060,
5269 0x5b02ca06,
5270 0x01900060,
5271 0x43020a04,
5272 0x00100060,
5273 0x1b00ca05,
5274 0x00100060,
5275 0x53028a07,
5276 0x0190c060,
5277 0x00000000,
5278 0x00000000,
5279 0x00000000,
5280 0x00000000,
5281 0x00000000,
5282 0x00000000,
5283 0x00000000,
5284 0x00000000,
5285 0x00000000,
5286 0x00000000,
5287 0x00000000,
5288 0x00000000,
5289 0x00000000,
5290 0x00000000,
5291 0x00000000,
5292 0x00000000,
5293 0x4002140c,
5294 0x00100010,
5295 0x1a00d40d,
5296 0x00100050,
5297 0x53028a0e,
5298 0x01900070,
5299 0x5b02ca0e,
5300 0x01900070,
5301 0x5b02ca0e,
5302 0x01900070,
5303 0x43020a0c,
5304 0x00100070,
5305 0x1b00ca0d,
5306 0x00100070,
5307 0x53028a0f,
5308 0x0190c070,
5309 0x00000000,
5310 0x00000000,
5311 0x00000000,
5312 0x00000000,
5313 0x00000000,
5314 0x00000000,
5315 0x00000000,
5316 0x00000000,
5317 0x00000000,
5318 0x00000000,
5319 0x00000000,
5320 0x00000000,
5321 0x00000000,
5322 0x00000000,
5323 0x00000000,
5324 0x00000000,
5325 0x40021404,
5326 0x00100000,
5327 0x1a00d405,
5328 0x00100040,
5329 0x5b02ca06,
5330 0x01900060,
5331 0x5b02ca06,
5332 0x01900060,
5333 0x53028a07,
5334 0x0190c060,
5335 0x00000000,
5336 0x00000000,
5337 0x00000000,
5338 0x00000000,
5339 0x00000000,
5340 0x00000000,
5341 0x00000000,
5342 0x00000000,
5343 0x00000000,
5344 0x00000000,
5345 0x00000000,
5346 0x00000000,
5347 0x00000000,
5348 0x00000000,
5349 0x00000000,
5350 0x00000000,
5351 0x00000000,
5352 0x00000000,
5353 0x00000000,
5354 0x00000000,
5355 0x00000000,
5356 0x00000000,
5357 0x4002140c,
5358 0x00100010,
5359 0x1a00d40d,
5360 0x00100050,
5361 0x5b02ca0e,
5362 0x01900070,
5363 0x5b02ca0e,
5364 0x01900070,
5365 0x53028a0f,
5366 0x0190c070,
5367 0x00000000,
5368 0x00000000,
5369 0x00000000,
5370 0x00000000,
5371 0x00000000,
5372 0x00000000,
5373 0x00000000,
5374 0x00000000,
5375 0x00000000,
5376 0x00000000,
5377 0x00000000,
5378 0x00000000,
5379 0x00000000,
5380 0x00000000,
5381 0x00000000,
5382 0x00000000,
5383 0x00000000,
5384 0x00000000,
5385 0x00000000,
5386 0x00000000,
5387 0x00000000,
5388 0x00000000,
5389 0x00000000,
5390 0x00000000,
5391 0x00000000,
5392 0x00000000,
5393 0x00000000,
5394 0x00000000,
5395 0x00000000,
5396 0x00000000,
5397 0x00000000,
5398 0x00000000,
5399 0x00000000,
5400 0x00000000,
5401 0x00000000,
5402 0x00000000,
5403 0x00000000,
5404 0x00000000,
5405 0x00000000,
5406 0x00000000,
5407 0x00000000,
5408 0x00000000,
5409 0x00000000,
5410 0x00000000,
5411 0x00000000,
5412 0x00000000,
5413 0x00000000,
5414 0x00000000,
5415 0x00000000,
5416 0x00000000,
5417 0x00000000,
5418 0x00000000,
5419 0x00000000,
5420 0x00000000,
5421 0x00000000,
5422 0x00000000,
5423 0x00000000,
5424 0x00000000,
5425 0x00000000,
5426 0x00000000,
5427 0x00000000,
5428 0x00000000,
5429 0x00000000,
5430 0x00000000,
5431 0x00000000,
5432 0x00000000,
5433 0x00000000,
5434 0x00000000,
5435 0x00000000,
5436 0x00000000,
5437 0x00000000,
5438 0x00000000,
5439 0x00000000,
5440 0x00000000,
5441 0x00000000,
5442 0x00000000,
5443 0x00000000,
5444 0x00000000,
5445 0x00000000,
5446 0x00000000,
5447 0x00000000,
5448 0x00000000,
5449 0x00000000,
5450 0x00000000,
5451 0x00000000,
5452 0x00000000,
5453 0x00000000,
5454 0x00000000,
5455 0x00000000,
5456 0x00000000,
5457 0x00000000,
5458 0x00000000,
5459 0x00000000,
5460 0x00000000,
5461 0x00000000,
5462 0x00000000,
5463 0x00000000,
5464 0x00000000,
5465 0x00000000,
5466 0x00000000,
5467 0x00000000,
5468 0x00000000,
5469 0x00000000,
5470 0x00000000,
5471 0x00000000,
5472 0x00000000,
5473 0x00000000,
5474 0x00000000,
5475 0x00000000,
5476 0x00000000,
5477 0x00000000,
5478 0x00000000,
5479 0x00000000,
5480 0x00000000,
5481 0x00000000,
5482 0x00000000,
5483 0x00000000,
5484 0x00000000,
5485 0x00000000,
5486 0x00000000,
5487 0x00000000,
5488 0x00000000,
5489 0x00000000,
5490 0x00000000,
5491 0x00000000,
5492 0x00000000,
5493 0x00000000,
5494 0x00000000,
5495 0x00000000,
5496 0x00000000,
5497 0x00000000,
5498 0x00000000,
5499 0x00000000,
5500 0x00000000,
5501 0x00000000,
5502 0x00000000,
5503 0x00000000,
5504 0x00000000,
5505 0x00000000,
5506 0x00000000,
5507 0x00000000,
5508 0x00000000,
5509 0x00000000,
5510 0x00000000,
5511 0x00000000,
5512 0x00000000,
5513 0x00000000,
5514 0x00000000,
5515 0x00000000,
5516 0x00000000,
5517};
5518
5519static const u16 pilot_tbl_rev3[] = {
5520 0xff08,
5521 0xff08,
5522 0xff08,
5523 0xff08,
5524 0xff08,
5525 0xff08,
5526 0xff08,
5527 0xff08,
5528 0x80d5,
5529 0x80d5,
5530 0x80d5,
5531 0x80d5,
5532 0x80d5,
5533 0x80d5,
5534 0x80d5,
5535 0x80d5,
5536 0xff0a,
5537 0xff82,
5538 0xffa0,
5539 0xff28,
5540 0xffff,
5541 0xffff,
5542 0xffff,
5543 0xffff,
5544 0xff82,
5545 0xffa0,
5546 0xff28,
5547 0xff0a,
5548 0xffff,
5549 0xffff,
5550 0xffff,
5551 0xffff,
5552 0xf83f,
5553 0xfa1f,
5554 0xfa97,
5555 0xfab5,
5556 0xf2bd,
5557 0xf0bf,
5558 0xffff,
5559 0xffff,
5560 0xf017,
5561 0xf815,
5562 0xf215,
5563 0xf095,
5564 0xf035,
5565 0xf01d,
5566 0xffff,
5567 0xffff,
5568 0xff08,
5569 0xff02,
5570 0xff80,
5571 0xff20,
5572 0xff08,
5573 0xff02,
5574 0xff80,
5575 0xff20,
5576 0xf01f,
5577 0xf817,
5578 0xfa15,
5579 0xf295,
5580 0xf0b5,
5581 0xf03d,
5582 0xffff,
5583 0xffff,
5584 0xf82a,
5585 0xfa0a,
5586 0xfa82,
5587 0xfaa0,
5588 0xf2a8,
5589 0xf0aa,
5590 0xffff,
5591 0xffff,
5592 0xf002,
5593 0xf800,
5594 0xf200,
5595 0xf080,
5596 0xf020,
5597 0xf008,
5598 0xffff,
5599 0xffff,
5600 0xf00a,
5601 0xf802,
5602 0xfa00,
5603 0xf280,
5604 0xf0a0,
5605 0xf028,
5606 0xffff,
5607 0xffff,
5608};
5609
5610static const u32 tmap_tbl_rev3[] = {
5611 0x8a88aa80,
5612 0x8aaaaa8a,
5613 0x8a8a8aa8,
5614 0x00000888,
5615 0x88000000,
5616 0x8a8a88aa,
5617 0x8aa88888,
5618 0x8888a8a8,
5619 0xf1111110,
5620 0x11111111,
5621 0x11f11111,
5622 0x00000111,
5623 0x11000000,
5624 0x1111f111,
5625 0x11111111,
5626 0x111111f1,
5627 0x8a88aa80,
5628 0x8aaaaa8a,
5629 0x8a8a8aa8,
5630 0x000aa888,
5631 0x88880000,
5632 0x8a8a88aa,
5633 0x8aa88888,
5634 0x8888a8a8,
5635 0xa1111110,
5636 0x11111111,
5637 0x11c11111,
5638 0x00000111,
5639 0x11000000,
5640 0x1111a111,
5641 0x11111111,
5642 0x111111a1,
5643 0xa2222220,
5644 0x22222222,
5645 0x22c22222,
5646 0x00000222,
5647 0x22000000,
5648 0x2222a222,
5649 0x22222222,
5650 0x222222a2,
5651 0xf1111110,
5652 0x11111111,
5653 0x11f11111,
5654 0x00011111,
5655 0x11110000,
5656 0x1111f111,
5657 0x11111111,
5658 0x111111f1,
5659 0xa8aa88a0,
5660 0xa88888a8,
5661 0xa8a8a88a,
5662 0x00088aaa,
5663 0xaaaa0000,
5664 0xa8a8aa88,
5665 0xa88aaaaa,
5666 0xaaaa8a8a,
5667 0xaaa8aaa0,
5668 0x8aaa8aaa,
5669 0xaa8a8a8a,
5670 0x000aaa88,
5671 0x8aaa0000,
5672 0xaaa8a888,
5673 0x8aa88a8a,
5674 0x8a88a888,
5675 0x08080a00,
5676 0x0a08080a,
5677 0x080a0a08,
5678 0x00080808,
5679 0x080a0000,
5680 0x080a0808,
5681 0x080a0808,
5682 0x0a0a0a08,
5683 0xa0a0a0a0,
5684 0x80a0a080,
5685 0x8080a0a0,
5686 0x00008080,
5687 0x80a00000,
5688 0x80a080a0,
5689 0xa080a0a0,
5690 0x8080a0a0,
5691 0x00000000,
5692 0x00000000,
5693 0x00000000,
5694 0x00000000,
5695 0x00000000,
5696 0x00000000,
5697 0x00000000,
5698 0x00000000,
5699 0x00000000,
5700 0x00000000,
5701 0x00000000,
5702 0x00000000,
5703 0x00000000,
5704 0x00000000,
5705 0x00000000,
5706 0x00000000,
5707 0x00000000,
5708 0x00000000,
5709 0x00000000,
5710 0x00000000,
5711 0x00000000,
5712 0x00000000,
5713 0x00000000,
5714 0x00000000,
5715 0x00000000,
5716 0x00000000,
5717 0x00000000,
5718 0x00000000,
5719 0x00000000,
5720 0x00000000,
5721 0x00000000,
5722 0x00000000,
5723 0x00000000,
5724 0x00000000,
5725 0x00000000,
5726 0x00000000,
5727 0x00000000,
5728 0x00000000,
5729 0x00000000,
5730 0x00000000,
5731 0x00000000,
5732 0x00000000,
5733 0x00000000,
5734 0x00000000,
5735 0x00000000,
5736 0x00000000,
5737 0x00000000,
5738 0x00000000,
5739 0x99999000,
5740 0x9b9b99bb,
5741 0x9bb99999,
5742 0x9999b9b9,
5743 0x9b99bb90,
5744 0x9bbbbb9b,
5745 0x9b9b9bb9,
5746 0x00000999,
5747 0x88000000,
5748 0x8a8a88aa,
5749 0x8aa88888,
5750 0x8888a8a8,
5751 0x8a88aa80,
5752 0x8aaaaa8a,
5753 0x8a8a8aa8,
5754 0x00aaa888,
5755 0x22000000,
5756 0x2222b222,
5757 0x22222222,
5758 0x222222b2,
5759 0xb2222220,
5760 0x22222222,
5761 0x22d22222,
5762 0x00000222,
5763 0x11000000,
5764 0x1111a111,
5765 0x11111111,
5766 0x111111a1,
5767 0xa1111110,
5768 0x11111111,
5769 0x11c11111,
5770 0x00000111,
5771 0x33000000,
5772 0x3333b333,
5773 0x33333333,
5774 0x333333b3,
5775 0xb3333330,
5776 0x33333333,
5777 0x33d33333,
5778 0x00000333,
5779 0x22000000,
5780 0x2222a222,
5781 0x22222222,
5782 0x222222a2,
5783 0xa2222220,
5784 0x22222222,
5785 0x22c22222,
5786 0x00000222,
5787 0x99b99b00,
5788 0x9b9b99bb,
5789 0x9bb99999,
5790 0x9999b9b9,
5791 0x9b99bb99,
5792 0x9bbbbb9b,
5793 0x9b9b9bb9,
5794 0x00000999,
5795 0x88000000,
5796 0x8a8a88aa,
5797 0x8aa88888,
5798 0x8888a8a8,
5799 0x8a88aa88,
5800 0x8aaaaa8a,
5801 0x8a8a8aa8,
5802 0x08aaa888,
5803 0x22222200,
5804 0x2222f222,
5805 0x22222222,
5806 0x222222f2,
5807 0x22222222,
5808 0x22222222,
5809 0x22f22222,
5810 0x00000222,
5811 0x11000000,
5812 0x1111f111,
5813 0x11111111,
5814 0x11111111,
5815 0xf1111111,
5816 0x11111111,
5817 0x11f11111,
5818 0x01111111,
5819 0xbb9bb900,
5820 0xb9b9bb99,
5821 0xb99bbbbb,
5822 0xbbbb9b9b,
5823 0xb9bb99bb,
5824 0xb99999b9,
5825 0xb9b9b99b,
5826 0x00000bbb,
5827 0xaa000000,
5828 0xa8a8aa88,
5829 0xa88aaaaa,
5830 0xaaaa8a8a,
5831 0xa8aa88aa,
5832 0xa88888a8,
5833 0xa8a8a88a,
5834 0x0a888aaa,
5835 0xaa000000,
5836 0xa8a8aa88,
5837 0xa88aaaaa,
5838 0xaaaa8a8a,
5839 0xa8aa88a0,
5840 0xa88888a8,
5841 0xa8a8a88a,
5842 0x00000aaa,
5843 0x88000000,
5844 0x8a8a88aa,
5845 0x8aa88888,
5846 0x8888a8a8,
5847 0x8a88aa80,
5848 0x8aaaaa8a,
5849 0x8a8a8aa8,
5850 0x00000888,
5851 0xbbbbbb00,
5852 0x999bbbbb,
5853 0x9bb99b9b,
5854 0xb9b9b9bb,
5855 0xb9b99bbb,
5856 0xb9b9b9bb,
5857 0xb9bb9b99,
5858 0x00000999,
5859 0x8a000000,
5860 0xaa88a888,
5861 0xa88888aa,
5862 0xa88a8a88,
5863 0xa88aa88a,
5864 0x88a8aaaa,
5865 0xa8aa8aaa,
5866 0x0888a88a,
5867 0x0b0b0b00,
5868 0x090b0b0b,
5869 0x0b090b0b,
5870 0x0909090b,
5871 0x09090b0b,
5872 0x09090b0b,
5873 0x09090b09,
5874 0x00000909,
5875 0x0a000000,
5876 0x0a080808,
5877 0x080a080a,
5878 0x080a0a08,
5879 0x080a080a,
5880 0x0808080a,
5881 0x0a0a0a08,
5882 0x0808080a,
5883 0xb0b0b000,
5884 0x9090b0b0,
5885 0x90b09090,
5886 0xb0b0b090,
5887 0xb0b090b0,
5888 0x90b0b0b0,
5889 0xb0b09090,
5890 0x00000090,
5891 0x80000000,
5892 0xa080a080,
5893 0xa08080a0,
5894 0xa0808080,
5895 0xa080a080,
5896 0x80a0a0a0,
5897 0xa0a080a0,
5898 0x00a0a0a0,
5899 0x22000000,
5900 0x2222f222,
5901 0x22222222,
5902 0x222222f2,
5903 0xf2222220,
5904 0x22222222,
5905 0x22f22222,
5906 0x00000222,
5907 0x11000000,
5908 0x1111f111,
5909 0x11111111,
5910 0x111111f1,
5911 0xf1111110,
5912 0x11111111,
5913 0x11f11111,
5914 0x00000111,
5915 0x33000000,
5916 0x3333f333,
5917 0x33333333,
5918 0x333333f3,
5919 0xf3333330,
5920 0x33333333,
5921 0x33f33333,
5922 0x00000333,
5923 0x22000000,
5924 0x2222f222,
5925 0x22222222,
5926 0x222222f2,
5927 0xf2222220,
5928 0x22222222,
5929 0x22f22222,
5930 0x00000222,
5931 0x99000000,
5932 0x9b9b99bb,
5933 0x9bb99999,
5934 0x9999b9b9,
5935 0x9b99bb90,
5936 0x9bbbbb9b,
5937 0x9b9b9bb9,
5938 0x00000999,
5939 0x88000000,
5940 0x8a8a88aa,
5941 0x8aa88888,
5942 0x8888a8a8,
5943 0x8a88aa80,
5944 0x8aaaaa8a,
5945 0x8a8a8aa8,
5946 0x00000888,
5947 0x88888000,
5948 0x8a8a88aa,
5949 0x8aa88888,
5950 0x8888a8a8,
5951 0x8a88aa80,
5952 0x8aaaaa8a,
5953 0x8a8a8aa8,
5954 0x00000888,
5955 0x88000000,
5956 0x8a8a88aa,
5957 0x8aa88888,
5958 0x8888a8a8,
5959 0x8a88aa80,
5960 0x8aaaaa8a,
5961 0x8a8a8aa8,
5962 0x00aaa888,
5963 0x88a88a00,
5964 0x8a8a88aa,
5965 0x8aa88888,
5966 0x8888a8a8,
5967 0x8a88aa88,
5968 0x8aaaaa8a,
5969 0x8a8a8aa8,
5970 0x00000888,
5971 0x88000000,
5972 0x8a8a88aa,
5973 0x8aa88888,
5974 0x8888a8a8,
5975 0x8a88aa88,
5976 0x8aaaaa8a,
5977 0x8a8a8aa8,
5978 0x08aaa888,
5979 0x11000000,
5980 0x1111a111,
5981 0x11111111,
5982 0x111111a1,
5983 0xa1111110,
5984 0x11111111,
5985 0x11c11111,
5986 0x00000111,
5987 0x11000000,
5988 0x1111a111,
5989 0x11111111,
5990 0x111111a1,
5991 0xa1111110,
5992 0x11111111,
5993 0x11c11111,
5994 0x00000111,
5995 0x88000000,
5996 0x8a8a88aa,
5997 0x8aa88888,
5998 0x8888a8a8,
5999 0x8a88aa80,
6000 0x8aaaaa8a,
6001 0x8a8a8aa8,
6002 0x00000888,
6003 0x88000000,
6004 0x8a8a88aa,
6005 0x8aa88888,
6006 0x8888a8a8,
6007 0x8a88aa80,
6008 0x8aaaaa8a,
6009 0x8a8a8aa8,
6010 0x00000888,
6011 0x00000000,
6012 0x00000000,
6013 0x00000000,
6014 0x00000000,
6015 0x00000000,
6016 0x00000000,
6017 0x00000000,
6018 0x00000000,
6019 0x00000000,
6020 0x00000000,
6021 0x00000000,
6022 0x00000000,
6023 0x00000000,
6024 0x00000000,
6025 0x00000000,
6026 0x00000000,
6027 0x00000000,
6028 0x00000000,
6029 0x00000000,
6030 0x00000000,
6031 0x00000000,
6032 0x00000000,
6033 0x00000000,
6034 0x00000000,
6035 0x00000000,
6036 0x00000000,
6037 0x00000000,
6038 0x00000000,
6039 0x00000000,
6040 0x00000000,
6041 0x00000000,
6042 0x00000000,
6043 0x00000000,
6044 0x00000000,
6045 0x00000000,
6046 0x00000000,
6047 0x00000000,
6048 0x00000000,
6049 0x00000000,
6050 0x00000000,
6051 0x00000000,
6052 0x00000000,
6053 0x00000000,
6054 0x00000000,
6055 0x00000000,
6056 0x00000000,
6057 0x00000000,
6058 0x00000000,
6059};
6060
6061static const u32 intlv_tbl_rev3[] = {
6062 0x00802070,
6063 0x0671188d,
6064 0x0a60192c,
6065 0x0a300e46,
6066 0x00c1188d,
6067 0x080024d2,
6068 0x00000070,
6069};
6070
6071static const u32 tdtrn_tbl_rev3[] = {
6072 0x061c061c,
6073 0x0050ee68,
6074 0xf592fe36,
6075 0xfe5212f6,
6076 0x00000c38,
6077 0xfe5212f6,
6078 0xf592fe36,
6079 0x0050ee68,
6080 0x061c061c,
6081 0xee680050,
6082 0xfe36f592,
6083 0x12f6fe52,
6084 0x0c380000,
6085 0x12f6fe52,
6086 0xfe36f592,
6087 0xee680050,
6088 0x061c061c,
6089 0x0050ee68,
6090 0xf592fe36,
6091 0xfe5212f6,
6092 0x00000c38,
6093 0xfe5212f6,
6094 0xf592fe36,
6095 0x0050ee68,
6096 0x061c061c,
6097 0xee680050,
6098 0xfe36f592,
6099 0x12f6fe52,
6100 0x0c380000,
6101 0x12f6fe52,
6102 0xfe36f592,
6103 0xee680050,
6104 0x05e305e3,
6105 0x004def0c,
6106 0xf5f3fe47,
6107 0xfe611246,
6108 0x00000bc7,
6109 0xfe611246,
6110 0xf5f3fe47,
6111 0x004def0c,
6112 0x05e305e3,
6113 0xef0c004d,
6114 0xfe47f5f3,
6115 0x1246fe61,
6116 0x0bc70000,
6117 0x1246fe61,
6118 0xfe47f5f3,
6119 0xef0c004d,
6120 0x05e305e3,
6121 0x004def0c,
6122 0xf5f3fe47,
6123 0xfe611246,
6124 0x00000bc7,
6125 0xfe611246,
6126 0xf5f3fe47,
6127 0x004def0c,
6128 0x05e305e3,
6129 0xef0c004d,
6130 0xfe47f5f3,
6131 0x1246fe61,
6132 0x0bc70000,
6133 0x1246fe61,
6134 0xfe47f5f3,
6135 0xef0c004d,
6136 0xfa58fa58,
6137 0xf895043b,
6138 0xff4c09c0,
6139 0xfbc6ffa8,
6140 0xfb84f384,
6141 0x0798f6f9,
6142 0x05760122,
6143 0x058409f6,
6144 0x0b500000,
6145 0x05b7f542,
6146 0x08860432,
6147 0x06ddfee7,
6148 0xfb84f384,
6149 0xf9d90664,
6150 0xf7e8025c,
6151 0x00fff7bd,
6152 0x05a805a8,
6153 0xf7bd00ff,
6154 0x025cf7e8,
6155 0x0664f9d9,
6156 0xf384fb84,
6157 0xfee706dd,
6158 0x04320886,
6159 0xf54205b7,
6160 0x00000b50,
6161 0x09f60584,
6162 0x01220576,
6163 0xf6f90798,
6164 0xf384fb84,
6165 0xffa8fbc6,
6166 0x09c0ff4c,
6167 0x043bf895,
6168 0x02d402d4,
6169 0x07de0270,
6170 0xfc96079c,
6171 0xf90afe94,
6172 0xfe00ff2c,
6173 0x02d4065d,
6174 0x092a0096,
6175 0x0014fbb8,
6176 0xfd2cfd2c,
6177 0x076afb3c,
6178 0x0096f752,
6179 0xf991fd87,
6180 0xfb2c0200,
6181 0xfeb8f960,
6182 0x08e0fc96,
6183 0x049802a8,
6184 0xfd2cfd2c,
6185 0x02a80498,
6186 0xfc9608e0,
6187 0xf960feb8,
6188 0x0200fb2c,
6189 0xfd87f991,
6190 0xf7520096,
6191 0xfb3c076a,
6192 0xfd2cfd2c,
6193 0xfbb80014,
6194 0x0096092a,
6195 0x065d02d4,
6196 0xff2cfe00,
6197 0xfe94f90a,
6198 0x079cfc96,
6199 0x027007de,
6200 0x02d402d4,
6201 0x027007de,
6202 0x079cfc96,
6203 0xfe94f90a,
6204 0xff2cfe00,
6205 0x065d02d4,
6206 0x0096092a,
6207 0xfbb80014,
6208 0xfd2cfd2c,
6209 0xfb3c076a,
6210 0xf7520096,
6211 0xfd87f991,
6212 0x0200fb2c,
6213 0xf960feb8,
6214 0xfc9608e0,
6215 0x02a80498,
6216 0xfd2cfd2c,
6217 0x049802a8,
6218 0x08e0fc96,
6219 0xfeb8f960,
6220 0xfb2c0200,
6221 0xf991fd87,
6222 0x0096f752,
6223 0x076afb3c,
6224 0xfd2cfd2c,
6225 0x0014fbb8,
6226 0x092a0096,
6227 0x02d4065d,
6228 0xfe00ff2c,
6229 0xf90afe94,
6230 0xfc96079c,
6231 0x07de0270,
6232 0x00000000,
6233 0x00000000,
6234 0x00000000,
6235 0x00000000,
6236 0x00000000,
6237 0x00000000,
6238 0x00000000,
6239 0x00000000,
6240 0x00000000,
6241 0x00000000,
6242 0x00000000,
6243 0x00000000,
6244 0x00000000,
6245 0x00000000,
6246 0x00000000,
6247 0x00000000,
6248 0x00000000,
6249 0x00000000,
6250 0x00000000,
6251 0x00000000,
6252 0x00000000,
6253 0x00000000,
6254 0x00000000,
6255 0x00000000,
6256 0x00000000,
6257 0x00000000,
6258 0x00000000,
6259 0x00000000,
6260 0x00000000,
6261 0x00000000,
6262 0x00000000,
6263 0x00000000,
6264 0x00000000,
6265 0x00000000,
6266 0x00000000,
6267 0x00000000,
6268 0x00000000,
6269 0x00000000,
6270 0x00000000,
6271 0x00000000,
6272 0x00000000,
6273 0x00000000,
6274 0x00000000,
6275 0x00000000,
6276 0x00000000,
6277 0x00000000,
6278 0x00000000,
6279 0x00000000,
6280 0x00000000,
6281 0x00000000,
6282 0x00000000,
6283 0x00000000,
6284 0x00000000,
6285 0x00000000,
6286 0x00000000,
6287 0x00000000,
6288 0x00000000,
6289 0x00000000,
6290 0x00000000,
6291 0x00000000,
6292 0x00000000,
6293 0x00000000,
6294 0x00000000,
6295 0x00000000,
6296 0x00000000,
6297 0x00000000,
6298 0x00000000,
6299 0x00000000,
6300 0x00000000,
6301 0x00000000,
6302 0x00000000,
6303 0x00000000,
6304 0x00000000,
6305 0x00000000,
6306 0x00000000,
6307 0x00000000,
6308 0x00000000,
6309 0x00000000,
6310 0x00000000,
6311 0x00000000,
6312 0x00000000,
6313 0x00000000,
6314 0x00000000,
6315 0x00000000,
6316 0x00000000,
6317 0x00000000,
6318 0x00000000,
6319 0x00000000,
6320 0x00000000,
6321 0x00000000,
6322 0x00000000,
6323 0x00000000,
6324 0x00000000,
6325 0x00000000,
6326 0x00000000,
6327 0x00000000,
6328 0x062a0000,
6329 0xfefa0759,
6330 0x08b80908,
6331 0xf396fc2d,
6332 0xf9d6045c,
6333 0xfc4ef608,
6334 0xf748f596,
6335 0x07b207bf,
6336 0x062a062a,
6337 0xf84ef841,
6338 0xf748f596,
6339 0x03b209f8,
6340 0xf9d6045c,
6341 0x0c6a03d3,
6342 0x08b80908,
6343 0x0106f8a7,
6344 0x062a0000,
6345 0xfefaf8a7,
6346 0x08b8f6f8,
6347 0xf39603d3,
6348 0xf9d6fba4,
6349 0xfc4e09f8,
6350 0xf7480a6a,
6351 0x07b2f841,
6352 0x062af9d6,
6353 0xf84e07bf,
6354 0xf7480a6a,
6355 0x03b2f608,
6356 0xf9d6fba4,
6357 0x0c6afc2d,
6358 0x08b8f6f8,
6359 0x01060759,
6360 0x062a0000,
6361 0xfefa0759,
6362 0x08b80908,
6363 0xf396fc2d,
6364 0xf9d6045c,
6365 0xfc4ef608,
6366 0xf748f596,
6367 0x07b207bf,
6368 0x062a062a,
6369 0xf84ef841,
6370 0xf748f596,
6371 0x03b209f8,
6372 0xf9d6045c,
6373 0x0c6a03d3,
6374 0x08b80908,
6375 0x0106f8a7,
6376 0x062a0000,
6377 0xfefaf8a7,
6378 0x08b8f6f8,
6379 0xf39603d3,
6380 0xf9d6fba4,
6381 0xfc4e09f8,
6382 0xf7480a6a,
6383 0x07b2f841,
6384 0x062af9d6,
6385 0xf84e07bf,
6386 0xf7480a6a,
6387 0x03b2f608,
6388 0xf9d6fba4,
6389 0x0c6afc2d,
6390 0x08b8f6f8,
6391 0x01060759,
6392 0x061c061c,
6393 0xff30009d,
6394 0xffb21141,
6395 0xfd87fb54,
6396 0xf65dfe59,
6397 0x02eef99e,
6398 0x0166f03c,
6399 0xfff809b6,
6400 0x000008a4,
6401 0x000af42b,
6402 0x00eff577,
6403 0xfa840bf2,
6404 0xfc02ff51,
6405 0x08260f67,
6406 0xfff0036f,
6407 0x0842f9c3,
6408 0x00000000,
6409 0x063df7be,
6410 0xfc910010,
6411 0xf099f7da,
6412 0x00af03fe,
6413 0xf40e057c,
6414 0x0a89ff11,
6415 0x0bd5fff6,
6416 0xf75c0000,
6417 0xf64a0008,
6418 0x0fc4fe9a,
6419 0x0662fd12,
6420 0x01a709a3,
6421 0x04ac0279,
6422 0xeebf004e,
6423 0xff6300d0,
6424 0xf9e4f9e4,
6425 0x00d0ff63,
6426 0x004eeebf,
6427 0x027904ac,
6428 0x09a301a7,
6429 0xfd120662,
6430 0xfe9a0fc4,
6431 0x0008f64a,
6432 0x0000f75c,
6433 0xfff60bd5,
6434 0xff110a89,
6435 0x057cf40e,
6436 0x03fe00af,
6437 0xf7daf099,
6438 0x0010fc91,
6439 0xf7be063d,
6440 0x00000000,
6441 0xf9c30842,
6442 0x036ffff0,
6443 0x0f670826,
6444 0xff51fc02,
6445 0x0bf2fa84,
6446 0xf57700ef,
6447 0xf42b000a,
6448 0x08a40000,
6449 0x09b6fff8,
6450 0xf03c0166,
6451 0xf99e02ee,
6452 0xfe59f65d,
6453 0xfb54fd87,
6454 0x1141ffb2,
6455 0x009dff30,
6456 0x05e30000,
6457 0xff060705,
6458 0x085408a0,
6459 0xf425fc59,
6460 0xfa1d042a,
6461 0xfc78f67a,
6462 0xf7acf60e,
6463 0x075a0766,
6464 0x05e305e3,
6465 0xf8a6f89a,
6466 0xf7acf60e,
6467 0x03880986,
6468 0xfa1d042a,
6469 0x0bdb03a7,
6470 0x085408a0,
6471 0x00faf8fb,
6472 0x05e30000,
6473 0xff06f8fb,
6474 0x0854f760,
6475 0xf42503a7,
6476 0xfa1dfbd6,
6477 0xfc780986,
6478 0xf7ac09f2,
6479 0x075af89a,
6480 0x05e3fa1d,
6481 0xf8a60766,
6482 0xf7ac09f2,
6483 0x0388f67a,
6484 0xfa1dfbd6,
6485 0x0bdbfc59,
6486 0x0854f760,
6487 0x00fa0705,
6488 0x05e30000,
6489 0xff060705,
6490 0x085408a0,
6491 0xf425fc59,
6492 0xfa1d042a,
6493 0xfc78f67a,
6494 0xf7acf60e,
6495 0x075a0766,
6496 0x05e305e3,
6497 0xf8a6f89a,
6498 0xf7acf60e,
6499 0x03880986,
6500 0xfa1d042a,
6501 0x0bdb03a7,
6502 0x085408a0,
6503 0x00faf8fb,
6504 0x05e30000,
6505 0xff06f8fb,
6506 0x0854f760,
6507 0xf42503a7,
6508 0xfa1dfbd6,
6509 0xfc780986,
6510 0xf7ac09f2,
6511 0x075af89a,
6512 0x05e3fa1d,
6513 0xf8a60766,
6514 0xf7ac09f2,
6515 0x0388f67a,
6516 0xfa1dfbd6,
6517 0x0bdbfc59,
6518 0x0854f760,
6519 0x00fa0705,
6520 0xfa58fa58,
6521 0xf8f0fe00,
6522 0x0448073d,
6523 0xfdc9fe46,
6524 0xf9910258,
6525 0x089d0407,
6526 0xfd5cf71a,
6527 0x02affde0,
6528 0x083e0496,
6529 0xff5a0740,
6530 0xff7afd97,
6531 0x00fe01f1,
6532 0x0009082e,
6533 0xfa94ff75,
6534 0xfecdf8ea,
6535 0xffb0f693,
6536 0xfd2cfa58,
6537 0x0433ff16,
6538 0xfba405dd,
6539 0xfa610341,
6540 0x06a606cb,
6541 0x0039fd2d,
6542 0x0677fa97,
6543 0x01fa05e0,
6544 0xf896003e,
6545 0x075a068b,
6546 0x012cfc3e,
6547 0xfa23f98d,
6548 0xfc7cfd43,
6549 0xff90fc0d,
6550 0x01c10982,
6551 0x00c601d6,
6552 0xfd2cfd2c,
6553 0x01d600c6,
6554 0x098201c1,
6555 0xfc0dff90,
6556 0xfd43fc7c,
6557 0xf98dfa23,
6558 0xfc3e012c,
6559 0x068b075a,
6560 0x003ef896,
6561 0x05e001fa,
6562 0xfa970677,
6563 0xfd2d0039,
6564 0x06cb06a6,
6565 0x0341fa61,
6566 0x05ddfba4,
6567 0xff160433,
6568 0xfa58fd2c,
6569 0xf693ffb0,
6570 0xf8eafecd,
6571 0xff75fa94,
6572 0x082e0009,
6573 0x01f100fe,
6574 0xfd97ff7a,
6575 0x0740ff5a,
6576 0x0496083e,
6577 0xfde002af,
6578 0xf71afd5c,
6579 0x0407089d,
6580 0x0258f991,
6581 0xfe46fdc9,
6582 0x073d0448,
6583 0xfe00f8f0,
6584 0xfd2cfd2c,
6585 0xfce00500,
6586 0xfc09fddc,
6587 0xfe680157,
6588 0x04c70571,
6589 0xfc3aff21,
6590 0xfcd70228,
6591 0x056d0277,
6592 0x0200fe00,
6593 0x0022f927,
6594 0xfe3c032b,
6595 0xfc44ff3c,
6596 0x03e9fbdb,
6597 0x04570313,
6598 0x04c9ff5c,
6599 0x000d03b8,
6600 0xfa580000,
6601 0xfbe900d2,
6602 0xf9d0fe0b,
6603 0x0125fdf9,
6604 0x042501bf,
6605 0x0328fa2b,
6606 0xffa902f0,
6607 0xfa250157,
6608 0x0200fe00,
6609 0x03740438,
6610 0xff0405fd,
6611 0x030cfe52,
6612 0x0037fb39,
6613 0xff6904c5,
6614 0x04f8fd23,
6615 0xfd31fc1b,
6616 0xfd2cfd2c,
6617 0xfc1bfd31,
6618 0xfd2304f8,
6619 0x04c5ff69,
6620 0xfb390037,
6621 0xfe52030c,
6622 0x05fdff04,
6623 0x04380374,
6624 0xfe000200,
6625 0x0157fa25,
6626 0x02f0ffa9,
6627 0xfa2b0328,
6628 0x01bf0425,
6629 0xfdf90125,
6630 0xfe0bf9d0,
6631 0x00d2fbe9,
6632 0x0000fa58,
6633 0x03b8000d,
6634 0xff5c04c9,
6635 0x03130457,
6636 0xfbdb03e9,
6637 0xff3cfc44,
6638 0x032bfe3c,
6639 0xf9270022,
6640 0xfe000200,
6641 0x0277056d,
6642 0x0228fcd7,
6643 0xff21fc3a,
6644 0x057104c7,
6645 0x0157fe68,
6646 0xfddcfc09,
6647 0x0500fce0,
6648 0xfd2cfd2c,
6649 0x0500fce0,
6650 0xfddcfc09,
6651 0x0157fe68,
6652 0x057104c7,
6653 0xff21fc3a,
6654 0x0228fcd7,
6655 0x0277056d,
6656 0xfe000200,
6657 0xf9270022,
6658 0x032bfe3c,
6659 0xff3cfc44,
6660 0xfbdb03e9,
6661 0x03130457,
6662 0xff5c04c9,
6663 0x03b8000d,
6664 0x0000fa58,
6665 0x00d2fbe9,
6666 0xfe0bf9d0,
6667 0xfdf90125,
6668 0x01bf0425,
6669 0xfa2b0328,
6670 0x02f0ffa9,
6671 0x0157fa25,
6672 0xfe000200,
6673 0x04380374,
6674 0x05fdff04,
6675 0xfe52030c,
6676 0xfb390037,
6677 0x04c5ff69,
6678 0xfd2304f8,
6679 0xfc1bfd31,
6680 0xfd2cfd2c,
6681 0xfd31fc1b,
6682 0x04f8fd23,
6683 0xff6904c5,
6684 0x0037fb39,
6685 0x030cfe52,
6686 0xff0405fd,
6687 0x03740438,
6688 0x0200fe00,
6689 0xfa250157,
6690 0xffa902f0,
6691 0x0328fa2b,
6692 0x042501bf,
6693 0x0125fdf9,
6694 0xf9d0fe0b,
6695 0xfbe900d2,
6696 0xfa580000,
6697 0x000d03b8,
6698 0x04c9ff5c,
6699 0x04570313,
6700 0x03e9fbdb,
6701 0xfc44ff3c,
6702 0xfe3c032b,
6703 0x0022f927,
6704 0x0200fe00,
6705 0x056d0277,
6706 0xfcd70228,
6707 0xfc3aff21,
6708 0x04c70571,
6709 0xfe680157,
6710 0xfc09fddc,
6711 0xfce00500,
6712 0x05a80000,
6713 0xff1006be,
6714 0x0800084a,
6715 0xf49cfc7e,
6716 0xfa580400,
6717 0xfc9cf6da,
6718 0xf800f672,
6719 0x0710071c,
6720 0x05a805a8,
6721 0xf8f0f8e4,
6722 0xf800f672,
6723 0x03640926,
6724 0xfa580400,
6725 0x0b640382,
6726 0x0800084a,
6727 0x00f0f942,
6728 0x05a80000,
6729 0xff10f942,
6730 0x0800f7b6,
6731 0xf49c0382,
6732 0xfa58fc00,
6733 0xfc9c0926,
6734 0xf800098e,
6735 0x0710f8e4,
6736 0x05a8fa58,
6737 0xf8f0071c,
6738 0xf800098e,
6739 0x0364f6da,
6740 0xfa58fc00,
6741 0x0b64fc7e,
6742 0x0800f7b6,
6743 0x00f006be,
6744 0x05a80000,
6745 0xff1006be,
6746 0x0800084a,
6747 0xf49cfc7e,
6748 0xfa580400,
6749 0xfc9cf6da,
6750 0xf800f672,
6751 0x0710071c,
6752 0x05a805a8,
6753 0xf8f0f8e4,
6754 0xf800f672,
6755 0x03640926,
6756 0xfa580400,
6757 0x0b640382,
6758 0x0800084a,
6759 0x00f0f942,
6760 0x05a80000,
6761 0xff10f942,
6762 0x0800f7b6,
6763 0xf49c0382,
6764 0xfa58fc00,
6765 0xfc9c0926,
6766 0xf800098e,
6767 0x0710f8e4,
6768 0x05a8fa58,
6769 0xf8f0071c,
6770 0xf800098e,
6771 0x0364f6da,
6772 0xfa58fc00,
6773 0x0b64fc7e,
6774 0x0800f7b6,
6775 0x00f006be,
6776};
6777
6778const u32 noise_var_tbl_rev3[] = {
6779 0x02110211,
6780 0x0000014d,
6781 0x02110211,
6782 0x0000014d,
6783 0x02110211,
6784 0x0000014d,
6785 0x02110211,
6786 0x0000014d,
6787 0x02110211,
6788 0x0000014d,
6789 0x02110211,
6790 0x0000014d,
6791 0x02110211,
6792 0x0000014d,
6793 0x02110211,
6794 0x0000014d,
6795 0x02110211,
6796 0x0000014d,
6797 0x02110211,
6798 0x0000014d,
6799 0x02110211,
6800 0x0000014d,
6801 0x02110211,
6802 0x0000014d,
6803 0x02110211,
6804 0x0000014d,
6805 0x02110211,
6806 0x0000014d,
6807 0x02110211,
6808 0x0000014d,
6809 0x02110211,
6810 0x0000014d,
6811 0x02110211,
6812 0x0000014d,
6813 0x02110211,
6814 0x0000014d,
6815 0x02110211,
6816 0x0000014d,
6817 0x02110211,
6818 0x0000014d,
6819 0x02110211,
6820 0x0000014d,
6821 0x02110211,
6822 0x0000014d,
6823 0x02110211,
6824 0x0000014d,
6825 0x02110211,
6826 0x0000014d,
6827 0x02110211,
6828 0x0000014d,
6829 0x02110211,
6830 0x0000014d,
6831 0x02110211,
6832 0x0000014d,
6833 0x02110211,
6834 0x0000014d,
6835 0x02110211,
6836 0x0000014d,
6837 0x02110211,
6838 0x0000014d,
6839 0x02110211,
6840 0x0000014d,
6841 0x02110211,
6842 0x0000014d,
6843 0x02110211,
6844 0x0000014d,
6845 0x02110211,
6846 0x0000014d,
6847 0x02110211,
6848 0x0000014d,
6849 0x02110211,
6850 0x0000014d,
6851 0x02110211,
6852 0x0000014d,
6853 0x02110211,
6854 0x0000014d,
6855 0x02110211,
6856 0x0000014d,
6857 0x02110211,
6858 0x0000014d,
6859 0x02110211,
6860 0x0000014d,
6861 0x02110211,
6862 0x0000014d,
6863 0x02110211,
6864 0x0000014d,
6865 0x02110211,
6866 0x0000014d,
6867 0x02110211,
6868 0x0000014d,
6869 0x02110211,
6870 0x0000014d,
6871 0x02110211,
6872 0x0000014d,
6873 0x02110211,
6874 0x0000014d,
6875 0x02110211,
6876 0x0000014d,
6877 0x02110211,
6878 0x0000014d,
6879 0x02110211,
6880 0x0000014d,
6881 0x02110211,
6882 0x0000014d,
6883 0x02110211,
6884 0x0000014d,
6885 0x02110211,
6886 0x0000014d,
6887 0x02110211,
6888 0x0000014d,
6889 0x02110211,
6890 0x0000014d,
6891 0x02110211,
6892 0x0000014d,
6893 0x02110211,
6894 0x0000014d,
6895 0x02110211,
6896 0x0000014d,
6897 0x02110211,
6898 0x0000014d,
6899 0x02110211,
6900 0x0000014d,
6901 0x02110211,
6902 0x0000014d,
6903 0x02110211,
6904 0x0000014d,
6905 0x02110211,
6906 0x0000014d,
6907 0x02110211,
6908 0x0000014d,
6909 0x02110211,
6910 0x0000014d,
6911 0x02110211,
6912 0x0000014d,
6913 0x02110211,
6914 0x0000014d,
6915 0x02110211,
6916 0x0000014d,
6917 0x02110211,
6918 0x0000014d,
6919 0x02110211,
6920 0x0000014d,
6921 0x02110211,
6922 0x0000014d,
6923 0x02110211,
6924 0x0000014d,
6925 0x02110211,
6926 0x0000014d,
6927 0x02110211,
6928 0x0000014d,
6929 0x02110211,
6930 0x0000014d,
6931 0x02110211,
6932 0x0000014d,
6933 0x02110211,
6934 0x0000014d,
6935 0x02110211,
6936 0x0000014d,
6937 0x02110211,
6938 0x0000014d,
6939 0x02110211,
6940 0x0000014d,
6941 0x02110211,
6942 0x0000014d,
6943 0x02110211,
6944 0x0000014d,
6945 0x02110211,
6946 0x0000014d,
6947 0x02110211,
6948 0x0000014d,
6949 0x02110211,
6950 0x0000014d,
6951 0x02110211,
6952 0x0000014d,
6953 0x02110211,
6954 0x0000014d,
6955 0x02110211,
6956 0x0000014d,
6957 0x02110211,
6958 0x0000014d,
6959 0x02110211,
6960 0x0000014d,
6961 0x02110211,
6962 0x0000014d,
6963 0x02110211,
6964 0x0000014d,
6965 0x02110211,
6966 0x0000014d,
6967 0x02110211,
6968 0x0000014d,
6969 0x02110211,
6970 0x0000014d,
6971 0x02110211,
6972 0x0000014d,
6973 0x02110211,
6974 0x0000014d,
6975 0x02110211,
6976 0x0000014d,
6977 0x02110211,
6978 0x0000014d,
6979 0x02110211,
6980 0x0000014d,
6981 0x02110211,
6982 0x0000014d,
6983 0x02110211,
6984 0x0000014d,
6985 0x02110211,
6986 0x0000014d,
6987 0x02110211,
6988 0x0000014d,
6989 0x02110211,
6990 0x0000014d,
6991 0x02110211,
6992 0x0000014d,
6993 0x02110211,
6994 0x0000014d,
6995 0x02110211,
6996 0x0000014d,
6997 0x02110211,
6998 0x0000014d,
6999 0x02110211,
7000 0x0000014d,
7001 0x02110211,
7002 0x0000014d,
7003 0x02110211,
7004 0x0000014d,
7005 0x02110211,
7006 0x0000014d,
7007 0x02110211,
7008 0x0000014d,
7009 0x02110211,
7010 0x0000014d,
7011 0x02110211,
7012 0x0000014d,
7013 0x02110211,
7014 0x0000014d,
7015 0x02110211,
7016 0x0000014d,
7017 0x02110211,
7018 0x0000014d,
7019 0x02110211,
7020 0x0000014d,
7021 0x02110211,
7022 0x0000014d,
7023 0x02110211,
7024 0x0000014d,
7025 0x02110211,
7026 0x0000014d,
7027 0x02110211,
7028 0x0000014d,
7029 0x02110211,
7030 0x0000014d,
7031 0x02110211,
7032 0x0000014d,
7033 0x02110211,
7034 0x0000014d,
7035};
7036
7037static const u16 mcs_tbl_rev3[] = {
7038 0x0000,
7039 0x0008,
7040 0x000a,
7041 0x0010,
7042 0x0012,
7043 0x0019,
7044 0x001a,
7045 0x001c,
7046 0x0080,
7047 0x0088,
7048 0x008a,
7049 0x0090,
7050 0x0092,
7051 0x0099,
7052 0x009a,
7053 0x009c,
7054 0x0100,
7055 0x0108,
7056 0x010a,
7057 0x0110,
7058 0x0112,
7059 0x0119,
7060 0x011a,
7061 0x011c,
7062 0x0180,
7063 0x0188,
7064 0x018a,
7065 0x0190,
7066 0x0192,
7067 0x0199,
7068 0x019a,
7069 0x019c,
7070 0x0000,
7071 0x0098,
7072 0x00a0,
7073 0x00a8,
7074 0x009a,
7075 0x00a2,
7076 0x00aa,
7077 0x0120,
7078 0x0128,
7079 0x0128,
7080 0x0130,
7081 0x0138,
7082 0x0138,
7083 0x0140,
7084 0x0122,
7085 0x012a,
7086 0x012a,
7087 0x0132,
7088 0x013a,
7089 0x013a,
7090 0x0142,
7091 0x01a8,
7092 0x01b0,
7093 0x01b8,
7094 0x01b0,
7095 0x01b8,
7096 0x01c0,
7097 0x01c8,
7098 0x01c0,
7099 0x01c8,
7100 0x01d0,
7101 0x01d0,
7102 0x01d8,
7103 0x01aa,
7104 0x01b2,
7105 0x01ba,
7106 0x01b2,
7107 0x01ba,
7108 0x01c2,
7109 0x01ca,
7110 0x01c2,
7111 0x01ca,
7112 0x01d2,
7113 0x01d2,
7114 0x01da,
7115 0x0001,
7116 0x0002,
7117 0x0004,
7118 0x0009,
7119 0x000c,
7120 0x0011,
7121 0x0014,
7122 0x0018,
7123 0x0020,
7124 0x0021,
7125 0x0022,
7126 0x0024,
7127 0x0081,
7128 0x0082,
7129 0x0084,
7130 0x0089,
7131 0x008c,
7132 0x0091,
7133 0x0094,
7134 0x0098,
7135 0x00a0,
7136 0x00a1,
7137 0x00a2,
7138 0x00a4,
7139 0x0007,
7140 0x0007,
7141 0x0007,
7142 0x0007,
7143 0x0007,
7144 0x0007,
7145 0x0007,
7146 0x0007,
7147 0x0007,
7148 0x0007,
7149 0x0007,
7150 0x0007,
7151 0x0007,
7152 0x0007,
7153 0x0007,
7154 0x0007,
7155 0x0007,
7156 0x0007,
7157 0x0007,
7158 0x0007,
7159 0x0007,
7160 0x0007,
7161 0x0007,
7162 0x0007,
7163 0x0007,
7164 0x0007,
7165 0x0007,
7166};
7167
7168static const u32 tdi_tbl20_ant0_rev3[] = {
7169 0x00091226,
7170 0x000a1429,
7171 0x000b56ad,
7172 0x000c58b0,
7173 0x000d5ab3,
7174 0x000e9cb6,
7175 0x000f9eba,
7176 0x0000c13d,
7177 0x00020301,
7178 0x00030504,
7179 0x00040708,
7180 0x0005090b,
7181 0x00064b8e,
7182 0x00095291,
7183 0x000a5494,
7184 0x000b9718,
7185 0x000c9927,
7186 0x000d9b2a,
7187 0x000edd2e,
7188 0x000fdf31,
7189 0x000101b4,
7190 0x000243b7,
7191 0x000345bb,
7192 0x000447be,
7193 0x00058982,
7194 0x00068c05,
7195 0x00099309,
7196 0x000a950c,
7197 0x000bd78f,
7198 0x000cd992,
7199 0x000ddb96,
7200 0x000f1d99,
7201 0x00005fa8,
7202 0x0001422c,
7203 0x0002842f,
7204 0x00038632,
7205 0x00048835,
7206 0x0005ca38,
7207 0x0006ccbc,
7208 0x0009d3bf,
7209 0x000b1603,
7210 0x000c1806,
7211 0x000d1a0a,
7212 0x000e1c0d,
7213 0x000f5e10,
7214 0x00008093,
7215 0x00018297,
7216 0x0002c49a,
7217 0x0003c680,
7218 0x0004c880,
7219 0x00060b00,
7220 0x00070d00,
7221 0x00000000,
7222 0x00000000,
7223 0x00000000,
7224};
7225
7226static const u32 tdi_tbl20_ant1_rev3[] = {
7227 0x00014b26,
7228 0x00028d29,
7229 0x000393ad,
7230 0x00049630,
7231 0x0005d833,
7232 0x0006da36,
7233 0x00099c3a,
7234 0x000a9e3d,
7235 0x000bc081,
7236 0x000cc284,
7237 0x000dc488,
7238 0x000f068b,
7239 0x0000488e,
7240 0x00018b91,
7241 0x0002d214,
7242 0x0003d418,
7243 0x0004d6a7,
7244 0x000618aa,
7245 0x00071aae,
7246 0x0009dcb1,
7247 0x000b1eb4,
7248 0x000c0137,
7249 0x000d033b,
7250 0x000e053e,
7251 0x000f4702,
7252 0x00008905,
7253 0x00020c09,
7254 0x0003128c,
7255 0x0004148f,
7256 0x00051712,
7257 0x00065916,
7258 0x00091b19,
7259 0x000a1d28,
7260 0x000b5f2c,
7261 0x000c41af,
7262 0x000d43b2,
7263 0x000e85b5,
7264 0x000f87b8,
7265 0x0000c9bc,
7266 0x00024cbf,
7267 0x00035303,
7268 0x00045506,
7269 0x0005978a,
7270 0x0006998d,
7271 0x00095b90,
7272 0x000a5d93,
7273 0x000b9f97,
7274 0x000c821a,
7275 0x000d8400,
7276 0x000ec600,
7277 0x000fc800,
7278 0x00010a00,
7279 0x00000000,
7280 0x00000000,
7281 0x00000000,
7282};
7283
7284static const u32 tdi_tbl40_ant0_rev3[] = {
7285 0x0011a346,
7286 0x00136ccf,
7287 0x0014f5d9,
7288 0x001641e2,
7289 0x0017cb6b,
7290 0x00195475,
7291 0x001b2383,
7292 0x001cad0c,
7293 0x001e7616,
7294 0x0000821f,
7295 0x00020ba8,
7296 0x0003d4b2,
7297 0x00056447,
7298 0x00072dd0,
7299 0x0008b6da,
7300 0x000a02e3,
7301 0x000b8c6c,
7302 0x000d15f6,
7303 0x0011e484,
7304 0x0013ae0d,
7305 0x00153717,
7306 0x00168320,
7307 0x00180ca9,
7308 0x00199633,
7309 0x001b6548,
7310 0x001ceed1,
7311 0x001eb7db,
7312 0x0000c3e4,
7313 0x00024d6d,
7314 0x000416f7,
7315 0x0005a585,
7316 0x00076f0f,
7317 0x0008f818,
7318 0x000a4421,
7319 0x000bcdab,
7320 0x000d9734,
7321 0x00122649,
7322 0x0013efd2,
7323 0x001578dc,
7324 0x0016c4e5,
7325 0x00184e6e,
7326 0x001a17f8,
7327 0x001ba686,
7328 0x001d3010,
7329 0x001ef999,
7330 0x00010522,
7331 0x00028eac,
7332 0x00045835,
7333 0x0005e74a,
7334 0x0007b0d3,
7335 0x00093a5d,
7336 0x000a85e6,
7337 0x000c0f6f,
7338 0x000dd8f9,
7339 0x00126787,
7340 0x00143111,
7341 0x0015ba9a,
7342 0x00170623,
7343 0x00188fad,
7344 0x001a5936,
7345 0x001be84b,
7346 0x001db1d4,
7347 0x001f3b5e,
7348 0x000146e7,
7349 0x00031070,
7350 0x000499fa,
7351 0x00062888,
7352 0x0007f212,
7353 0x00097b9b,
7354 0x000ac7a4,
7355 0x000c50ae,
7356 0x000e1a37,
7357 0x0012a94c,
7358 0x001472d5,
7359 0x0015fc5f,
7360 0x00174868,
7361 0x0018d171,
7362 0x001a9afb,
7363 0x001c2989,
7364 0x001df313,
7365 0x001f7c9c,
7366 0x000188a5,
7367 0x000351af,
7368 0x0004db38,
7369 0x0006aa4d,
7370 0x000833d7,
7371 0x0009bd60,
7372 0x000b0969,
7373 0x000c9273,
7374 0x000e5bfc,
7375 0x00132a8a,
7376 0x0014b414,
7377 0x00163d9d,
7378 0x001789a6,
7379 0x001912b0,
7380 0x001adc39,
7381 0x001c6bce,
7382 0x001e34d8,
7383 0x001fbe61,
7384 0x0001ca6a,
7385 0x00039374,
7386 0x00051cfd,
7387 0x0006ec0b,
7388 0x00087515,
7389 0x0009fe9e,
7390 0x000b4aa7,
7391 0x000cd3b1,
7392 0x000e9d3a,
7393 0x00000000,
7394 0x00000000,
7395};
7396
7397static const u32 tdi_tbl40_ant1_rev3[] = {
7398 0x001edb36,
7399 0x000129ca,
7400 0x0002b353,
7401 0x00047cdd,
7402 0x0005c8e6,
7403 0x000791ef,
7404 0x00091bf9,
7405 0x000aaa07,
7406 0x000c3391,
7407 0x000dfd1a,
7408 0x00120923,
7409 0x0013d22d,
7410 0x00155c37,
7411 0x0016eacb,
7412 0x00187454,
7413 0x001a3dde,
7414 0x001b89e7,
7415 0x001d12f0,
7416 0x001f1cfa,
7417 0x00016b88,
7418 0x00033492,
7419 0x0004be1b,
7420 0x00060a24,
7421 0x0007d32e,
7422 0x00095d38,
7423 0x000aec4c,
7424 0x000c7555,
7425 0x000e3edf,
7426 0x00124ae8,
7427 0x001413f1,
7428 0x0015a37b,
7429 0x00172c89,
7430 0x0018b593,
7431 0x001a419c,
7432 0x001bcb25,
7433 0x001d942f,
7434 0x001f63b9,
7435 0x0001ad4d,
7436 0x00037657,
7437 0x0004c260,
7438 0x00068be9,
7439 0x000814f3,
7440 0x0009a47c,
7441 0x000b2d8a,
7442 0x000cb694,
7443 0x000e429d,
7444 0x00128c26,
7445 0x001455b0,
7446 0x0015e4ba,
7447 0x00176e4e,
7448 0x0018f758,
7449 0x001a8361,
7450 0x001c0cea,
7451 0x001dd674,
7452 0x001fa57d,
7453 0x0001ee8b,
7454 0x0003b795,
7455 0x0005039e,
7456 0x0006cd27,
7457 0x000856b1,
7458 0x0009e5c6,
7459 0x000b6f4f,
7460 0x000cf859,
7461 0x000e8462,
7462 0x00130deb,
7463 0x00149775,
7464 0x00162603,
7465 0x0017af8c,
7466 0x00193896,
7467 0x001ac49f,
7468 0x001c4e28,
7469 0x001e17b2,
7470 0x0000a6c7,
7471 0x00023050,
7472 0x0003f9da,
7473 0x00054563,
7474 0x00070eec,
7475 0x00089876,
7476 0x000a2704,
7477 0x000bb08d,
7478 0x000d3a17,
7479 0x001185a0,
7480 0x00134f29,
7481 0x0014d8b3,
7482 0x001667c8,
7483 0x0017f151,
7484 0x00197adb,
7485 0x001b0664,
7486 0x001c8fed,
7487 0x001e5977,
7488 0x0000e805,
7489 0x0002718f,
7490 0x00043b18,
7491 0x000586a1,
7492 0x0007502b,
7493 0x0008d9b4,
7494 0x000a68c9,
7495 0x000bf252,
7496 0x000dbbdc,
7497 0x0011c7e5,
7498 0x001390ee,
7499 0x00151a78,
7500 0x0016a906,
7501 0x00183290,
7502 0x0019bc19,
7503 0x001b4822,
7504 0x001cd12c,
7505 0x001e9ab5,
7506 0x00000000,
7507 0x00000000,
7508};
7509
7510static const u32 pltlut_tbl_rev3[] = {
7511 0x76540213,
7512 0x62407351,
7513 0x76543210,
7514 0x76540213,
7515 0x76540213,
7516 0x76430521,
7517};
7518
7519static const u32 chanest_tbl_rev3[] = {
7520 0x44444444,
7521 0x44444444,
7522 0x44444444,
7523 0x44444444,
7524 0x44444444,
7525 0x44444444,
7526 0x44444444,
7527 0x44444444,
7528 0x10101010,
7529 0x10101010,
7530 0x10101010,
7531 0x10101010,
7532 0x10101010,
7533 0x10101010,
7534 0x10101010,
7535 0x10101010,
7536 0x44444444,
7537 0x44444444,
7538 0x44444444,
7539 0x44444444,
7540 0x44444444,
7541 0x44444444,
7542 0x44444444,
7543 0x44444444,
7544 0x10101010,
7545 0x10101010,
7546 0x10101010,
7547 0x10101010,
7548 0x10101010,
7549 0x10101010,
7550 0x10101010,
7551 0x10101010,
7552 0x44444444,
7553 0x44444444,
7554 0x44444444,
7555 0x44444444,
7556 0x44444444,
7557 0x44444444,
7558 0x44444444,
7559 0x44444444,
7560 0x44444444,
7561 0x44444444,
7562 0x44444444,
7563 0x44444444,
7564 0x44444444,
7565 0x44444444,
7566 0x44444444,
7567 0x44444444,
7568 0x10101010,
7569 0x10101010,
7570 0x10101010,
7571 0x10101010,
7572 0x10101010,
7573 0x10101010,
7574 0x10101010,
7575 0x10101010,
7576 0x10101010,
7577 0x10101010,
7578 0x10101010,
7579 0x10101010,
7580 0x10101010,
7581 0x10101010,
7582 0x10101010,
7583 0x10101010,
7584 0x44444444,
7585 0x44444444,
7586 0x44444444,
7587 0x44444444,
7588 0x44444444,
7589 0x44444444,
7590 0x44444444,
7591 0x44444444,
7592 0x44444444,
7593 0x44444444,
7594 0x44444444,
7595 0x44444444,
7596 0x44444444,
7597 0x44444444,
7598 0x44444444,
7599 0x44444444,
7600 0x10101010,
7601 0x10101010,
7602 0x10101010,
7603 0x10101010,
7604 0x10101010,
7605 0x10101010,
7606 0x10101010,
7607 0x10101010,
7608 0x10101010,
7609 0x10101010,
7610 0x10101010,
7611 0x10101010,
7612 0x10101010,
7613 0x10101010,
7614 0x10101010,
7615 0x10101010,
7616};
7617
7618static const u8 frame_lut_rev3[] = {
7619 0x02,
7620 0x04,
7621 0x14,
7622 0x14,
7623 0x03,
7624 0x05,
7625 0x16,
7626 0x16,
7627 0x0a,
7628 0x0c,
7629 0x1c,
7630 0x1c,
7631 0x0b,
7632 0x0d,
7633 0x1e,
7634 0x1e,
7635 0x06,
7636 0x08,
7637 0x18,
7638 0x18,
7639 0x07,
7640 0x09,
7641 0x1a,
7642 0x1a,
7643 0x0e,
7644 0x10,
7645 0x20,
7646 0x28,
7647 0x0f,
7648 0x11,
7649 0x22,
7650 0x2a,
7651};
7652
7653static const u8 est_pwr_lut_core0_rev3[] = {
7654 0x55,
7655 0x54,
7656 0x54,
7657 0x53,
7658 0x52,
7659 0x52,
7660 0x51,
7661 0x51,
7662 0x50,
7663 0x4f,
7664 0x4f,
7665 0x4e,
7666 0x4e,
7667 0x4d,
7668 0x4c,
7669 0x4c,
7670 0x4b,
7671 0x4a,
7672 0x49,
7673 0x49,
7674 0x48,
7675 0x47,
7676 0x46,
7677 0x46,
7678 0x45,
7679 0x44,
7680 0x43,
7681 0x42,
7682 0x41,
7683 0x40,
7684 0x40,
7685 0x3f,
7686 0x3e,
7687 0x3d,
7688 0x3c,
7689 0x3a,
7690 0x39,
7691 0x38,
7692 0x37,
7693 0x36,
7694 0x35,
7695 0x33,
7696 0x32,
7697 0x31,
7698 0x2f,
7699 0x2e,
7700 0x2c,
7701 0x2b,
7702 0x29,
7703 0x27,
7704 0x25,
7705 0x23,
7706 0x21,
7707 0x1f,
7708 0x1d,
7709 0x1a,
7710 0x18,
7711 0x15,
7712 0x12,
7713 0x0e,
7714 0x0b,
7715 0x07,
7716 0x02,
7717 0xfd,
7718};
7719
7720static const u8 est_pwr_lut_core1_rev3[] = {
7721 0x55,
7722 0x54,
7723 0x54,
7724 0x53,
7725 0x52,
7726 0x52,
7727 0x51,
7728 0x51,
7729 0x50,
7730 0x4f,
7731 0x4f,
7732 0x4e,
7733 0x4e,
7734 0x4d,
7735 0x4c,
7736 0x4c,
7737 0x4b,
7738 0x4a,
7739 0x49,
7740 0x49,
7741 0x48,
7742 0x47,
7743 0x46,
7744 0x46,
7745 0x45,
7746 0x44,
7747 0x43,
7748 0x42,
7749 0x41,
7750 0x40,
7751 0x40,
7752 0x3f,
7753 0x3e,
7754 0x3d,
7755 0x3c,
7756 0x3a,
7757 0x39,
7758 0x38,
7759 0x37,
7760 0x36,
7761 0x35,
7762 0x33,
7763 0x32,
7764 0x31,
7765 0x2f,
7766 0x2e,
7767 0x2c,
7768 0x2b,
7769 0x29,
7770 0x27,
7771 0x25,
7772 0x23,
7773 0x21,
7774 0x1f,
7775 0x1d,
7776 0x1a,
7777 0x18,
7778 0x15,
7779 0x12,
7780 0x0e,
7781 0x0b,
7782 0x07,
7783 0x02,
7784 0xfd,
7785};
7786
7787static const u8 adj_pwr_lut_core0_rev3[] = {
7788 0x00,
7789 0x00,
7790 0x00,
7791 0x00,
7792 0x00,
7793 0x00,
7794 0x00,
7795 0x00,
7796 0x00,
7797 0x00,
7798 0x00,
7799 0x00,
7800 0x00,
7801 0x00,
7802 0x00,
7803 0x00,
7804 0x00,
7805 0x00,
7806 0x00,
7807 0x00,
7808 0x00,
7809 0x00,
7810 0x00,
7811 0x00,
7812 0x00,
7813 0x00,
7814 0x00,
7815 0x00,
7816 0x00,
7817 0x00,
7818 0x00,
7819 0x00,
7820 0x00,
7821 0x00,
7822 0x00,
7823 0x00,
7824 0x00,
7825 0x00,
7826 0x00,
7827 0x00,
7828 0x00,
7829 0x00,
7830 0x00,
7831 0x00,
7832 0x00,
7833 0x00,
7834 0x00,
7835 0x00,
7836 0x00,
7837 0x00,
7838 0x00,
7839 0x00,
7840 0x00,
7841 0x00,
7842 0x00,
7843 0x00,
7844 0x00,
7845 0x00,
7846 0x00,
7847 0x00,
7848 0x00,
7849 0x00,
7850 0x00,
7851 0x00,
7852 0x00,
7853 0x00,
7854 0x00,
7855 0x00,
7856 0x00,
7857 0x00,
7858 0x00,
7859 0x00,
7860 0x00,
7861 0x00,
7862 0x00,
7863 0x00,
7864 0x00,
7865 0x00,
7866 0x00,
7867 0x00,
7868 0x00,
7869 0x00,
7870 0x00,
7871 0x00,
7872 0x00,
7873 0x00,
7874 0x00,
7875 0x00,
7876 0x00,
7877 0x00,
7878 0x00,
7879 0x00,
7880 0x00,
7881 0x00,
7882 0x00,
7883 0x00,
7884 0x00,
7885 0x00,
7886 0x00,
7887 0x00,
7888 0x00,
7889 0x00,
7890 0x00,
7891 0x00,
7892 0x00,
7893 0x00,
7894 0x00,
7895 0x00,
7896 0x00,
7897 0x00,
7898 0x00,
7899 0x00,
7900 0x00,
7901 0x00,
7902 0x00,
7903 0x00,
7904 0x00,
7905 0x00,
7906 0x00,
7907 0x00,
7908 0x00,
7909 0x00,
7910 0x00,
7911 0x00,
7912 0x00,
7913 0x00,
7914 0x00,
7915 0x00,
7916};
7917
7918static const u8 adj_pwr_lut_core1_rev3[] = {
7919 0x00,
7920 0x00,
7921 0x00,
7922 0x00,
7923 0x00,
7924 0x00,
7925 0x00,
7926 0x00,
7927 0x00,
7928 0x00,
7929 0x00,
7930 0x00,
7931 0x00,
7932 0x00,
7933 0x00,
7934 0x00,
7935 0x00,
7936 0x00,
7937 0x00,
7938 0x00,
7939 0x00,
7940 0x00,
7941 0x00,
7942 0x00,
7943 0x00,
7944 0x00,
7945 0x00,
7946 0x00,
7947 0x00,
7948 0x00,
7949 0x00,
7950 0x00,
7951 0x00,
7952 0x00,
7953 0x00,
7954 0x00,
7955 0x00,
7956 0x00,
7957 0x00,
7958 0x00,
7959 0x00,
7960 0x00,
7961 0x00,
7962 0x00,
7963 0x00,
7964 0x00,
7965 0x00,
7966 0x00,
7967 0x00,
7968 0x00,
7969 0x00,
7970 0x00,
7971 0x00,
7972 0x00,
7973 0x00,
7974 0x00,
7975 0x00,
7976 0x00,
7977 0x00,
7978 0x00,
7979 0x00,
7980 0x00,
7981 0x00,
7982 0x00,
7983 0x00,
7984 0x00,
7985 0x00,
7986 0x00,
7987 0x00,
7988 0x00,
7989 0x00,
7990 0x00,
7991 0x00,
7992 0x00,
7993 0x00,
7994 0x00,
7995 0x00,
7996 0x00,
7997 0x00,
7998 0x00,
7999 0x00,
8000 0x00,
8001 0x00,
8002 0x00,
8003 0x00,
8004 0x00,
8005 0x00,
8006 0x00,
8007 0x00,
8008 0x00,
8009 0x00,
8010 0x00,
8011 0x00,
8012 0x00,
8013 0x00,
8014 0x00,
8015 0x00,
8016 0x00,
8017 0x00,
8018 0x00,
8019 0x00,
8020 0x00,
8021 0x00,
8022 0x00,
8023 0x00,
8024 0x00,
8025 0x00,
8026 0x00,
8027 0x00,
8028 0x00,
8029 0x00,
8030 0x00,
8031 0x00,
8032 0x00,
8033 0x00,
8034 0x00,
8035 0x00,
8036 0x00,
8037 0x00,
8038 0x00,
8039 0x00,
8040 0x00,
8041 0x00,
8042 0x00,
8043 0x00,
8044 0x00,
8045 0x00,
8046 0x00,
8047};
8048
8049static const u32 gainctrl_lut_core0_rev3[] = {
8050 0x5bf70044,
8051 0x5bf70042,
8052 0x5bf70040,
8053 0x5bf7003e,
8054 0x5bf7003c,
8055 0x5bf7003b,
8056 0x5bf70039,
8057 0x5bf70037,
8058 0x5bf70036,
8059 0x5bf70034,
8060 0x5bf70033,
8061 0x5bf70031,
8062 0x5bf70030,
8063 0x5ba70044,
8064 0x5ba70042,
8065 0x5ba70040,
8066 0x5ba7003e,
8067 0x5ba7003c,
8068 0x5ba7003b,
8069 0x5ba70039,
8070 0x5ba70037,
8071 0x5ba70036,
8072 0x5ba70034,
8073 0x5ba70033,
8074 0x5b770044,
8075 0x5b770042,
8076 0x5b770040,
8077 0x5b77003e,
8078 0x5b77003c,
8079 0x5b77003b,
8080 0x5b770039,
8081 0x5b770037,
8082 0x5b770036,
8083 0x5b770034,
8084 0x5b770033,
8085 0x5b770031,
8086 0x5b770030,
8087 0x5b77002f,
8088 0x5b77002d,
8089 0x5b77002c,
8090 0x5b470044,
8091 0x5b470042,
8092 0x5b470040,
8093 0x5b47003e,
8094 0x5b47003c,
8095 0x5b47003b,
8096 0x5b470039,
8097 0x5b470037,
8098 0x5b470036,
8099 0x5b470034,
8100 0x5b470033,
8101 0x5b470031,
8102 0x5b470030,
8103 0x5b47002f,
8104 0x5b47002d,
8105 0x5b47002c,
8106 0x5b47002b,
8107 0x5b47002a,
8108 0x5b270044,
8109 0x5b270042,
8110 0x5b270040,
8111 0x5b27003e,
8112 0x5b27003c,
8113 0x5b27003b,
8114 0x5b270039,
8115 0x5b270037,
8116 0x5b270036,
8117 0x5b270034,
8118 0x5b270033,
8119 0x5b270031,
8120 0x5b270030,
8121 0x5b27002f,
8122 0x5b170044,
8123 0x5b170042,
8124 0x5b170040,
8125 0x5b17003e,
8126 0x5b17003c,
8127 0x5b17003b,
8128 0x5b170039,
8129 0x5b170037,
8130 0x5b170036,
8131 0x5b170034,
8132 0x5b170033,
8133 0x5b170031,
8134 0x5b170030,
8135 0x5b17002f,
8136 0x5b17002d,
8137 0x5b17002c,
8138 0x5b17002b,
8139 0x5b17002a,
8140 0x5b170028,
8141 0x5b170027,
8142 0x5b170026,
8143 0x5b170025,
8144 0x5b170024,
8145 0x5b170023,
8146 0x5b070044,
8147 0x5b070042,
8148 0x5b070040,
8149 0x5b07003e,
8150 0x5b07003c,
8151 0x5b07003b,
8152 0x5b070039,
8153 0x5b070037,
8154 0x5b070036,
8155 0x5b070034,
8156 0x5b070033,
8157 0x5b070031,
8158 0x5b070030,
8159 0x5b07002f,
8160 0x5b07002d,
8161 0x5b07002c,
8162 0x5b07002b,
8163 0x5b07002a,
8164 0x5b070028,
8165 0x5b070027,
8166 0x5b070026,
8167 0x5b070025,
8168 0x5b070024,
8169 0x5b070023,
8170 0x5b070022,
8171 0x5b070021,
8172 0x5b070020,
8173 0x5b07001f,
8174 0x5b07001e,
8175 0x5b07001d,
8176 0x5b07001d,
8177 0x5b07001c,
8178};
8179
8180static const u32 gainctrl_lut_core1_rev3[] = {
8181 0x5bf70044,
8182 0x5bf70042,
8183 0x5bf70040,
8184 0x5bf7003e,
8185 0x5bf7003c,
8186 0x5bf7003b,
8187 0x5bf70039,
8188 0x5bf70037,
8189 0x5bf70036,
8190 0x5bf70034,
8191 0x5bf70033,
8192 0x5bf70031,
8193 0x5bf70030,
8194 0x5ba70044,
8195 0x5ba70042,
8196 0x5ba70040,
8197 0x5ba7003e,
8198 0x5ba7003c,
8199 0x5ba7003b,
8200 0x5ba70039,
8201 0x5ba70037,
8202 0x5ba70036,
8203 0x5ba70034,
8204 0x5ba70033,
8205 0x5b770044,
8206 0x5b770042,
8207 0x5b770040,
8208 0x5b77003e,
8209 0x5b77003c,
8210 0x5b77003b,
8211 0x5b770039,
8212 0x5b770037,
8213 0x5b770036,
8214 0x5b770034,
8215 0x5b770033,
8216 0x5b770031,
8217 0x5b770030,
8218 0x5b77002f,
8219 0x5b77002d,
8220 0x5b77002c,
8221 0x5b470044,
8222 0x5b470042,
8223 0x5b470040,
8224 0x5b47003e,
8225 0x5b47003c,
8226 0x5b47003b,
8227 0x5b470039,
8228 0x5b470037,
8229 0x5b470036,
8230 0x5b470034,
8231 0x5b470033,
8232 0x5b470031,
8233 0x5b470030,
8234 0x5b47002f,
8235 0x5b47002d,
8236 0x5b47002c,
8237 0x5b47002b,
8238 0x5b47002a,
8239 0x5b270044,
8240 0x5b270042,
8241 0x5b270040,
8242 0x5b27003e,
8243 0x5b27003c,
8244 0x5b27003b,
8245 0x5b270039,
8246 0x5b270037,
8247 0x5b270036,
8248 0x5b270034,
8249 0x5b270033,
8250 0x5b270031,
8251 0x5b270030,
8252 0x5b27002f,
8253 0x5b170044,
8254 0x5b170042,
8255 0x5b170040,
8256 0x5b17003e,
8257 0x5b17003c,
8258 0x5b17003b,
8259 0x5b170039,
8260 0x5b170037,
8261 0x5b170036,
8262 0x5b170034,
8263 0x5b170033,
8264 0x5b170031,
8265 0x5b170030,
8266 0x5b17002f,
8267 0x5b17002d,
8268 0x5b17002c,
8269 0x5b17002b,
8270 0x5b17002a,
8271 0x5b170028,
8272 0x5b170027,
8273 0x5b170026,
8274 0x5b170025,
8275 0x5b170024,
8276 0x5b170023,
8277 0x5b070044,
8278 0x5b070042,
8279 0x5b070040,
8280 0x5b07003e,
8281 0x5b07003c,
8282 0x5b07003b,
8283 0x5b070039,
8284 0x5b070037,
8285 0x5b070036,
8286 0x5b070034,
8287 0x5b070033,
8288 0x5b070031,
8289 0x5b070030,
8290 0x5b07002f,
8291 0x5b07002d,
8292 0x5b07002c,
8293 0x5b07002b,
8294 0x5b07002a,
8295 0x5b070028,
8296 0x5b070027,
8297 0x5b070026,
8298 0x5b070025,
8299 0x5b070024,
8300 0x5b070023,
8301 0x5b070022,
8302 0x5b070021,
8303 0x5b070020,
8304 0x5b07001f,
8305 0x5b07001e,
8306 0x5b07001d,
8307 0x5b07001d,
8308 0x5b07001c,
8309};
8310
8311static const u32 iq_lut_core0_rev3[] = {
8312 0x00000000,
8313 0x00000000,
8314 0x00000000,
8315 0x00000000,
8316 0x00000000,
8317 0x00000000,
8318 0x00000000,
8319 0x00000000,
8320 0x00000000,
8321 0x00000000,
8322 0x00000000,
8323 0x00000000,
8324 0x00000000,
8325 0x00000000,
8326 0x00000000,
8327 0x00000000,
8328 0x00000000,
8329 0x00000000,
8330 0x00000000,
8331 0x00000000,
8332 0x00000000,
8333 0x00000000,
8334 0x00000000,
8335 0x00000000,
8336 0x00000000,
8337 0x00000000,
8338 0x00000000,
8339 0x00000000,
8340 0x00000000,
8341 0x00000000,
8342 0x00000000,
8343 0x00000000,
8344 0x00000000,
8345 0x00000000,
8346 0x00000000,
8347 0x00000000,
8348 0x00000000,
8349 0x00000000,
8350 0x00000000,
8351 0x00000000,
8352 0x00000000,
8353 0x00000000,
8354 0x00000000,
8355 0x00000000,
8356 0x00000000,
8357 0x00000000,
8358 0x00000000,
8359 0x00000000,
8360 0x00000000,
8361 0x00000000,
8362 0x00000000,
8363 0x00000000,
8364 0x00000000,
8365 0x00000000,
8366 0x00000000,
8367 0x00000000,
8368 0x00000000,
8369 0x00000000,
8370 0x00000000,
8371 0x00000000,
8372 0x00000000,
8373 0x00000000,
8374 0x00000000,
8375 0x00000000,
8376 0x00000000,
8377 0x00000000,
8378 0x00000000,
8379 0x00000000,
8380 0x00000000,
8381 0x00000000,
8382 0x00000000,
8383 0x00000000,
8384 0x00000000,
8385 0x00000000,
8386 0x00000000,
8387 0x00000000,
8388 0x00000000,
8389 0x00000000,
8390 0x00000000,
8391 0x00000000,
8392 0x00000000,
8393 0x00000000,
8394 0x00000000,
8395 0x00000000,
8396 0x00000000,
8397 0x00000000,
8398 0x00000000,
8399 0x00000000,
8400 0x00000000,
8401 0x00000000,
8402 0x00000000,
8403 0x00000000,
8404 0x00000000,
8405 0x00000000,
8406 0x00000000,
8407 0x00000000,
8408 0x00000000,
8409 0x00000000,
8410 0x00000000,
8411 0x00000000,
8412 0x00000000,
8413 0x00000000,
8414 0x00000000,
8415 0x00000000,
8416 0x00000000,
8417 0x00000000,
8418 0x00000000,
8419 0x00000000,
8420 0x00000000,
8421 0x00000000,
8422 0x00000000,
8423 0x00000000,
8424 0x00000000,
8425 0x00000000,
8426 0x00000000,
8427 0x00000000,
8428 0x00000000,
8429 0x00000000,
8430 0x00000000,
8431 0x00000000,
8432 0x00000000,
8433 0x00000000,
8434 0x00000000,
8435 0x00000000,
8436 0x00000000,
8437 0x00000000,
8438 0x00000000,
8439 0x00000000,
8440};
8441
8442static const u32 iq_lut_core1_rev3[] = {
8443 0x00000000,
8444 0x00000000,
8445 0x00000000,
8446 0x00000000,
8447 0x00000000,
8448 0x00000000,
8449 0x00000000,
8450 0x00000000,
8451 0x00000000,
8452 0x00000000,
8453 0x00000000,
8454 0x00000000,
8455 0x00000000,
8456 0x00000000,
8457 0x00000000,
8458 0x00000000,
8459 0x00000000,
8460 0x00000000,
8461 0x00000000,
8462 0x00000000,
8463 0x00000000,
8464 0x00000000,
8465 0x00000000,
8466 0x00000000,
8467 0x00000000,
8468 0x00000000,
8469 0x00000000,
8470 0x00000000,
8471 0x00000000,
8472 0x00000000,
8473 0x00000000,
8474 0x00000000,
8475 0x00000000,
8476 0x00000000,
8477 0x00000000,
8478 0x00000000,
8479 0x00000000,
8480 0x00000000,
8481 0x00000000,
8482 0x00000000,
8483 0x00000000,
8484 0x00000000,
8485 0x00000000,
8486 0x00000000,
8487 0x00000000,
8488 0x00000000,
8489 0x00000000,
8490 0x00000000,
8491 0x00000000,
8492 0x00000000,
8493 0x00000000,
8494 0x00000000,
8495 0x00000000,
8496 0x00000000,
8497 0x00000000,
8498 0x00000000,
8499 0x00000000,
8500 0x00000000,
8501 0x00000000,
8502 0x00000000,
8503 0x00000000,
8504 0x00000000,
8505 0x00000000,
8506 0x00000000,
8507 0x00000000,
8508 0x00000000,
8509 0x00000000,
8510 0x00000000,
8511 0x00000000,
8512 0x00000000,
8513 0x00000000,
8514 0x00000000,
8515 0x00000000,
8516 0x00000000,
8517 0x00000000,
8518 0x00000000,
8519 0x00000000,
8520 0x00000000,
8521 0x00000000,
8522 0x00000000,
8523 0x00000000,
8524 0x00000000,
8525 0x00000000,
8526 0x00000000,
8527 0x00000000,
8528 0x00000000,
8529 0x00000000,
8530 0x00000000,
8531 0x00000000,
8532 0x00000000,
8533 0x00000000,
8534 0x00000000,
8535 0x00000000,
8536 0x00000000,
8537 0x00000000,
8538 0x00000000,
8539 0x00000000,
8540 0x00000000,
8541 0x00000000,
8542 0x00000000,
8543 0x00000000,
8544 0x00000000,
8545 0x00000000,
8546 0x00000000,
8547 0x00000000,
8548 0x00000000,
8549 0x00000000,
8550 0x00000000,
8551 0x00000000,
8552 0x00000000,
8553 0x00000000,
8554 0x00000000,
8555 0x00000000,
8556 0x00000000,
8557 0x00000000,
8558 0x00000000,
8559 0x00000000,
8560 0x00000000,
8561 0x00000000,
8562 0x00000000,
8563 0x00000000,
8564 0x00000000,
8565 0x00000000,
8566 0x00000000,
8567 0x00000000,
8568 0x00000000,
8569 0x00000000,
8570 0x00000000,
8571};
8572
8573static const u16 loft_lut_core0_rev3[] = {
8574 0x0000,
8575 0x0000,
8576 0x0000,
8577 0x0000,
8578 0x0000,
8579 0x0000,
8580 0x0000,
8581 0x0000,
8582 0x0000,
8583 0x0000,
8584 0x0000,
8585 0x0000,
8586 0x0000,
8587 0x0000,
8588 0x0000,
8589 0x0000,
8590 0x0000,
8591 0x0000,
8592 0x0000,
8593 0x0000,
8594 0x0000,
8595 0x0000,
8596 0x0000,
8597 0x0000,
8598 0x0000,
8599 0x0000,
8600 0x0000,
8601 0x0000,
8602 0x0000,
8603 0x0000,
8604 0x0000,
8605 0x0000,
8606 0x0000,
8607 0x0000,
8608 0x0000,
8609 0x0000,
8610 0x0000,
8611 0x0000,
8612 0x0000,
8613 0x0000,
8614 0x0000,
8615 0x0000,
8616 0x0000,
8617 0x0000,
8618 0x0000,
8619 0x0000,
8620 0x0000,
8621 0x0000,
8622 0x0000,
8623 0x0000,
8624 0x0000,
8625 0x0000,
8626 0x0000,
8627 0x0000,
8628 0x0000,
8629 0x0000,
8630 0x0000,
8631 0x0000,
8632 0x0000,
8633 0x0000,
8634 0x0000,
8635 0x0000,
8636 0x0000,
8637 0x0000,
8638 0x0000,
8639 0x0000,
8640 0x0000,
8641 0x0000,
8642 0x0000,
8643 0x0000,
8644 0x0000,
8645 0x0000,
8646 0x0000,
8647 0x0000,
8648 0x0000,
8649 0x0000,
8650 0x0000,
8651 0x0000,
8652 0x0000,
8653 0x0000,
8654 0x0000,
8655 0x0000,
8656 0x0000,
8657 0x0000,
8658 0x0000,
8659 0x0000,
8660 0x0000,
8661 0x0000,
8662 0x0000,
8663 0x0000,
8664 0x0000,
8665 0x0000,
8666 0x0000,
8667 0x0000,
8668 0x0000,
8669 0x0000,
8670 0x0000,
8671 0x0000,
8672 0x0000,
8673 0x0000,
8674 0x0000,
8675 0x0000,
8676 0x0000,
8677 0x0000,
8678 0x0000,
8679 0x0000,
8680 0x0000,
8681 0x0000,
8682 0x0000,
8683 0x0000,
8684 0x0000,
8685 0x0000,
8686 0x0000,
8687 0x0000,
8688 0x0000,
8689 0x0000,
8690 0x0000,
8691 0x0000,
8692 0x0000,
8693 0x0000,
8694 0x0000,
8695 0x0000,
8696 0x0000,
8697 0x0000,
8698 0x0000,
8699 0x0000,
8700 0x0000,
8701 0x0000,
8702};
8703
8704static const u16 loft_lut_core1_rev3[] = {
8705 0x0000,
8706 0x0000,
8707 0x0000,
8708 0x0000,
8709 0x0000,
8710 0x0000,
8711 0x0000,
8712 0x0000,
8713 0x0000,
8714 0x0000,
8715 0x0000,
8716 0x0000,
8717 0x0000,
8718 0x0000,
8719 0x0000,
8720 0x0000,
8721 0x0000,
8722 0x0000,
8723 0x0000,
8724 0x0000,
8725 0x0000,
8726 0x0000,
8727 0x0000,
8728 0x0000,
8729 0x0000,
8730 0x0000,
8731 0x0000,
8732 0x0000,
8733 0x0000,
8734 0x0000,
8735 0x0000,
8736 0x0000,
8737 0x0000,
8738 0x0000,
8739 0x0000,
8740 0x0000,
8741 0x0000,
8742 0x0000,
8743 0x0000,
8744 0x0000,
8745 0x0000,
8746 0x0000,
8747 0x0000,
8748 0x0000,
8749 0x0000,
8750 0x0000,
8751 0x0000,
8752 0x0000,
8753 0x0000,
8754 0x0000,
8755 0x0000,
8756 0x0000,
8757 0x0000,
8758 0x0000,
8759 0x0000,
8760 0x0000,
8761 0x0000,
8762 0x0000,
8763 0x0000,
8764 0x0000,
8765 0x0000,
8766 0x0000,
8767 0x0000,
8768 0x0000,
8769 0x0000,
8770 0x0000,
8771 0x0000,
8772 0x0000,
8773 0x0000,
8774 0x0000,
8775 0x0000,
8776 0x0000,
8777 0x0000,
8778 0x0000,
8779 0x0000,
8780 0x0000,
8781 0x0000,
8782 0x0000,
8783 0x0000,
8784 0x0000,
8785 0x0000,
8786 0x0000,
8787 0x0000,
8788 0x0000,
8789 0x0000,
8790 0x0000,
8791 0x0000,
8792 0x0000,
8793 0x0000,
8794 0x0000,
8795 0x0000,
8796 0x0000,
8797 0x0000,
8798 0x0000,
8799 0x0000,
8800 0x0000,
8801 0x0000,
8802 0x0000,
8803 0x0000,
8804 0x0000,
8805 0x0000,
8806 0x0000,
8807 0x0000,
8808 0x0000,
8809 0x0000,
8810 0x0000,
8811 0x0000,
8812 0x0000,
8813 0x0000,
8814 0x0000,
8815 0x0000,
8816 0x0000,
8817 0x0000,
8818 0x0000,
8819 0x0000,
8820 0x0000,
8821 0x0000,
8822 0x0000,
8823 0x0000,
8824 0x0000,
8825 0x0000,
8826 0x0000,
8827 0x0000,
8828 0x0000,
8829 0x0000,
8830 0x0000,
8831 0x0000,
8832 0x0000,
8833};
8834
8835static const u16 papd_comp_rfpwr_tbl_core0_rev3[] = {
8836 0x0036,
8837 0x0036,
8838 0x0036,
8839 0x0036,
8840 0x0036,
8841 0x0036,
8842 0x0036,
8843 0x0036,
8844 0x0036,
8845 0x0036,
8846 0x0036,
8847 0x0036,
8848 0x0036,
8849 0x002a,
8850 0x002a,
8851 0x002a,
8852 0x002a,
8853 0x002a,
8854 0x002a,
8855 0x002a,
8856 0x002a,
8857 0x002a,
8858 0x002a,
8859 0x002a,
8860 0x001e,
8861 0x001e,
8862 0x001e,
8863 0x001e,
8864 0x001e,
8865 0x001e,
8866 0x001e,
8867 0x001e,
8868 0x001e,
8869 0x001e,
8870 0x001e,
8871 0x001e,
8872 0x001e,
8873 0x001e,
8874 0x001e,
8875 0x001e,
8876 0x000e,
8877 0x000e,
8878 0x000e,
8879 0x000e,
8880 0x000e,
8881 0x000e,
8882 0x000e,
8883 0x000e,
8884 0x000e,
8885 0x000e,
8886 0x000e,
8887 0x000e,
8888 0x000e,
8889 0x000e,
8890 0x000e,
8891 0x000e,
8892 0x000e,
8893 0x000e,
8894 0x01fc,
8895 0x01fc,
8896 0x01fc,
8897 0x01fc,
8898 0x01fc,
8899 0x01fc,
8900 0x01fc,
8901 0x01fc,
8902 0x01fc,
8903 0x01fc,
8904 0x01fc,
8905 0x01fc,
8906 0x01fc,
8907 0x01fc,
8908 0x01ee,
8909 0x01ee,
8910 0x01ee,
8911 0x01ee,
8912 0x01ee,
8913 0x01ee,
8914 0x01ee,
8915 0x01ee,
8916 0x01ee,
8917 0x01ee,
8918 0x01ee,
8919 0x01ee,
8920 0x01ee,
8921 0x01ee,
8922 0x01ee,
8923 0x01ee,
8924 0x01ee,
8925 0x01ee,
8926 0x01ee,
8927 0x01ee,
8928 0x01ee,
8929 0x01ee,
8930 0x01ee,
8931 0x01ee,
8932 0x01d6,
8933 0x01d6,
8934 0x01d6,
8935 0x01d6,
8936 0x01d6,
8937 0x01d6,
8938 0x01d6,
8939 0x01d6,
8940 0x01d6,
8941 0x01d6,
8942 0x01d6,
8943 0x01d6,
8944 0x01d6,
8945 0x01d6,
8946 0x01d6,
8947 0x01d6,
8948 0x01d6,
8949 0x01d6,
8950 0x01d6,
8951 0x01d6,
8952 0x01d6,
8953 0x01d6,
8954 0x01d6,
8955 0x01d6,
8956 0x01d6,
8957 0x01d6,
8958 0x01d6,
8959 0x01d6,
8960 0x01d6,
8961 0x01d6,
8962 0x01d6,
8963 0x01d6,
8964};
8965
8966static const u16 papd_comp_rfpwr_tbl_core1_rev3[] = {
8967 0x0036,
8968 0x0036,
8969 0x0036,
8970 0x0036,
8971 0x0036,
8972 0x0036,
8973 0x0036,
8974 0x0036,
8975 0x0036,
8976 0x0036,
8977 0x0036,
8978 0x0036,
8979 0x0036,
8980 0x002a,
8981 0x002a,
8982 0x002a,
8983 0x002a,
8984 0x002a,
8985 0x002a,
8986 0x002a,
8987 0x002a,
8988 0x002a,
8989 0x002a,
8990 0x002a,
8991 0x001e,
8992 0x001e,
8993 0x001e,
8994 0x001e,
8995 0x001e,
8996 0x001e,
8997 0x001e,
8998 0x001e,
8999 0x001e,
9000 0x001e,
9001 0x001e,
9002 0x001e,
9003 0x001e,
9004 0x001e,
9005 0x001e,
9006 0x001e,
9007 0x000e,
9008 0x000e,
9009 0x000e,
9010 0x000e,
9011 0x000e,
9012 0x000e,
9013 0x000e,
9014 0x000e,
9015 0x000e,
9016 0x000e,
9017 0x000e,
9018 0x000e,
9019 0x000e,
9020 0x000e,
9021 0x000e,
9022 0x000e,
9023 0x000e,
9024 0x000e,
9025 0x01fc,
9026 0x01fc,
9027 0x01fc,
9028 0x01fc,
9029 0x01fc,
9030 0x01fc,
9031 0x01fc,
9032 0x01fc,
9033 0x01fc,
9034 0x01fc,
9035 0x01fc,
9036 0x01fc,
9037 0x01fc,
9038 0x01fc,
9039 0x01ee,
9040 0x01ee,
9041 0x01ee,
9042 0x01ee,
9043 0x01ee,
9044 0x01ee,
9045 0x01ee,
9046 0x01ee,
9047 0x01ee,
9048 0x01ee,
9049 0x01ee,
9050 0x01ee,
9051 0x01ee,
9052 0x01ee,
9053 0x01ee,
9054 0x01ee,
9055 0x01ee,
9056 0x01ee,
9057 0x01ee,
9058 0x01ee,
9059 0x01ee,
9060 0x01ee,
9061 0x01ee,
9062 0x01ee,
9063 0x01d6,
9064 0x01d6,
9065 0x01d6,
9066 0x01d6,
9067 0x01d6,
9068 0x01d6,
9069 0x01d6,
9070 0x01d6,
9071 0x01d6,
9072 0x01d6,
9073 0x01d6,
9074 0x01d6,
9075 0x01d6,
9076 0x01d6,
9077 0x01d6,
9078 0x01d6,
9079 0x01d6,
9080 0x01d6,
9081 0x01d6,
9082 0x01d6,
9083 0x01d6,
9084 0x01d6,
9085 0x01d6,
9086 0x01d6,
9087 0x01d6,
9088 0x01d6,
9089 0x01d6,
9090 0x01d6,
9091 0x01d6,
9092 0x01d6,
9093 0x01d6,
9094 0x01d6,
9095};
9096
9097static const u32 papd_comp_epsilon_tbl_core0_rev3[] = {
9098 0x00000000,
9099 0x00001fa0,
9100 0x00019f78,
9101 0x0001df7e,
9102 0x03fa9f86,
9103 0x03fd1f90,
9104 0x03fe5f8a,
9105 0x03fb1f94,
9106 0x03fd9fa0,
9107 0x00009f98,
9108 0x03fd1fac,
9109 0x03ff9fa2,
9110 0x03fe9fae,
9111 0x00001fae,
9112 0x03fddfb4,
9113 0x03ff1fb8,
9114 0x03ff9fbc,
9115 0x03ffdfbe,
9116 0x03fe9fc2,
9117 0x03fedfc6,
9118 0x03fedfc6,
9119 0x03ff9fc8,
9120 0x03ff5fc6,
9121 0x03fedfc2,
9122 0x03ff9fc0,
9123 0x03ff5fac,
9124 0x03ff5fac,
9125 0x03ff9fa2,
9126 0x03ff9fa6,
9127 0x03ff9faa,
9128 0x03ff5fb0,
9129 0x03ff5fb4,
9130 0x03ff1fca,
9131 0x03ff5fce,
9132 0x03fcdfdc,
9133 0x03fb4006,
9134 0x00000030,
9135 0x03ff808a,
9136 0x03ff80da,
9137 0x0000016c,
9138 0x03ff8318,
9139 0x03ff063a,
9140 0x03fd8bd6,
9141 0x00014ffe,
9142 0x00034ffe,
9143 0x00034ffe,
9144 0x0003cffe,
9145 0x00040ffe,
9146 0x00040ffe,
9147 0x0003cffe,
9148 0x0003cffe,
9149 0x00020ffe,
9150 0x03fe0ffe,
9151 0x03fdcffe,
9152 0x03f94ffe,
9153 0x03f54ffe,
9154 0x03f44ffe,
9155 0x03ef8ffe,
9156 0x03ee0ffe,
9157 0x03ebcffe,
9158 0x03e8cffe,
9159 0x03e74ffe,
9160 0x03e4cffe,
9161 0x03e38ffe,
9162};
9163
9164static const u32 papd_cal_scalars_tbl_core0_rev3[] = {
9165 0x05af005a,
9166 0x0571005e,
9167 0x05040066,
9168 0x04bd006c,
9169 0x047d0072,
9170 0x04430078,
9171 0x03f70081,
9172 0x03cb0087,
9173 0x03870091,
9174 0x035e0098,
9175 0x032e00a1,
9176 0x030300aa,
9177 0x02d800b4,
9178 0x02ae00bf,
9179 0x028900ca,
9180 0x026400d6,
9181 0x024100e3,
9182 0x022200f0,
9183 0x020200ff,
9184 0x01e5010e,
9185 0x01ca011e,
9186 0x01b0012f,
9187 0x01990140,
9188 0x01830153,
9189 0x016c0168,
9190 0x0158017d,
9191 0x01450193,
9192 0x013301ab,
9193 0x012101c5,
9194 0x011101e0,
9195 0x010201fc,
9196 0x00f4021a,
9197 0x00e6011d,
9198 0x00d9012e,
9199 0x00cd0140,
9200 0x00c20153,
9201 0x00b70167,
9202 0x00ac017c,
9203 0x00a30193,
9204 0x009a01ab,
9205 0x009101c4,
9206 0x008901df,
9207 0x008101fb,
9208 0x007a0219,
9209 0x00730239,
9210 0x006d025b,
9211 0x0067027e,
9212 0x006102a4,
9213 0x005c02cc,
9214 0x005602f6,
9215 0x00520323,
9216 0x004d0353,
9217 0x00490385,
9218 0x004503bb,
9219 0x004103f3,
9220 0x003d042f,
9221 0x003a046f,
9222 0x003704b2,
9223 0x003404f9,
9224 0x00310545,
9225 0x002e0596,
9226 0x002b05f5,
9227 0x00290640,
9228 0x002606a4,
9229};
9230
9231static const u32 papd_comp_epsilon_tbl_core1_rev3[] = {
9232 0x00000000,
9233 0x00001fa0,
9234 0x00019f78,
9235 0x0001df7e,
9236 0x03fa9f86,
9237 0x03fd1f90,
9238 0x03fe5f8a,
9239 0x03fb1f94,
9240 0x03fd9fa0,
9241 0x00009f98,
9242 0x03fd1fac,
9243 0x03ff9fa2,
9244 0x03fe9fae,
9245 0x00001fae,
9246 0x03fddfb4,
9247 0x03ff1fb8,
9248 0x03ff9fbc,
9249 0x03ffdfbe,
9250 0x03fe9fc2,
9251 0x03fedfc6,
9252 0x03fedfc6,
9253 0x03ff9fc8,
9254 0x03ff5fc6,
9255 0x03fedfc2,
9256 0x03ff9fc0,
9257 0x03ff5fac,
9258 0x03ff5fac,
9259 0x03ff9fa2,
9260 0x03ff9fa6,
9261 0x03ff9faa,
9262 0x03ff5fb0,
9263 0x03ff5fb4,
9264 0x03ff1fca,
9265 0x03ff5fce,
9266 0x03fcdfdc,
9267 0x03fb4006,
9268 0x00000030,
9269 0x03ff808a,
9270 0x03ff80da,
9271 0x0000016c,
9272 0x03ff8318,
9273 0x03ff063a,
9274 0x03fd8bd6,
9275 0x00014ffe,
9276 0x00034ffe,
9277 0x00034ffe,
9278 0x0003cffe,
9279 0x00040ffe,
9280 0x00040ffe,
9281 0x0003cffe,
9282 0x0003cffe,
9283 0x00020ffe,
9284 0x03fe0ffe,
9285 0x03fdcffe,
9286 0x03f94ffe,
9287 0x03f54ffe,
9288 0x03f44ffe,
9289 0x03ef8ffe,
9290 0x03ee0ffe,
9291 0x03ebcffe,
9292 0x03e8cffe,
9293 0x03e74ffe,
9294 0x03e4cffe,
9295 0x03e38ffe,
9296};
9297
9298static const u32 papd_cal_scalars_tbl_core1_rev3[] = {
9299 0x05af005a,
9300 0x0571005e,
9301 0x05040066,
9302 0x04bd006c,
9303 0x047d0072,
9304 0x04430078,
9305 0x03f70081,
9306 0x03cb0087,
9307 0x03870091,
9308 0x035e0098,
9309 0x032e00a1,
9310 0x030300aa,
9311 0x02d800b4,
9312 0x02ae00bf,
9313 0x028900ca,
9314 0x026400d6,
9315 0x024100e3,
9316 0x022200f0,
9317 0x020200ff,
9318 0x01e5010e,
9319 0x01ca011e,
9320 0x01b0012f,
9321 0x01990140,
9322 0x01830153,
9323 0x016c0168,
9324 0x0158017d,
9325 0x01450193,
9326 0x013301ab,
9327 0x012101c5,
9328 0x011101e0,
9329 0x010201fc,
9330 0x00f4021a,
9331 0x00e6011d,
9332 0x00d9012e,
9333 0x00cd0140,
9334 0x00c20153,
9335 0x00b70167,
9336 0x00ac017c,
9337 0x00a30193,
9338 0x009a01ab,
9339 0x009101c4,
9340 0x008901df,
9341 0x008101fb,
9342 0x007a0219,
9343 0x00730239,
9344 0x006d025b,
9345 0x0067027e,
9346 0x006102a4,
9347 0x005c02cc,
9348 0x005602f6,
9349 0x00520323,
9350 0x004d0353,
9351 0x00490385,
9352 0x004503bb,
9353 0x004103f3,
9354 0x003d042f,
9355 0x003a046f,
9356 0x003704b2,
9357 0x003404f9,
9358 0x00310545,
9359 0x002e0596,
9360 0x002b05f5,
9361 0x00290640,
9362 0x002606a4,
9363};
9364
9365const struct phytbl_info mimophytbl_info_rev3_volatile[] = {
9366 {&ant_swctrl_tbl_rev3,
9367 sizeof(ant_swctrl_tbl_rev3) / sizeof(ant_swctrl_tbl_rev3[0]), 9, 0, 16}
9368 ,
9369};
9370
9371const struct phytbl_info mimophytbl_info_rev3_volatile1[] = {
9372 {&ant_swctrl_tbl_rev3_1,
9373 sizeof(ant_swctrl_tbl_rev3_1) / sizeof(ant_swctrl_tbl_rev3_1[0]), 9, 0,
9374 16}
9375 ,
9376};
9377
9378const struct phytbl_info mimophytbl_info_rev3_volatile2[] = {
9379 {&ant_swctrl_tbl_rev3_2,
9380 sizeof(ant_swctrl_tbl_rev3_2) / sizeof(ant_swctrl_tbl_rev3_2[0]), 9, 0,
9381 16}
9382 ,
9383};
9384
9385const struct phytbl_info mimophytbl_info_rev3_volatile3[] = {
9386 {&ant_swctrl_tbl_rev3_3,
9387 sizeof(ant_swctrl_tbl_rev3_3) / sizeof(ant_swctrl_tbl_rev3_3[0]), 9, 0,
9388 16}
9389 ,
9390};
9391
9392const struct phytbl_info mimophytbl_info_rev3[] = {
9393 {&frame_struct_rev3,
9394 sizeof(frame_struct_rev3) / sizeof(frame_struct_rev3[0]), 10, 0, 32}
9395 ,
9396 {&pilot_tbl_rev3, sizeof(pilot_tbl_rev3) / sizeof(pilot_tbl_rev3[0]),
9397 11, 0, 16}
9398 ,
9399 {&tmap_tbl_rev3, sizeof(tmap_tbl_rev3) / sizeof(tmap_tbl_rev3[0]), 12,
9400 0, 32}
9401 ,
9402 {&intlv_tbl_rev3, sizeof(intlv_tbl_rev3) / sizeof(intlv_tbl_rev3[0]),
9403 13, 0, 32}
9404 ,
9405 {&tdtrn_tbl_rev3, sizeof(tdtrn_tbl_rev3) / sizeof(tdtrn_tbl_rev3[0]),
9406 14, 0, 32}
9407 ,
9408 {&noise_var_tbl_rev3,
9409 sizeof(noise_var_tbl_rev3) / sizeof(noise_var_tbl_rev3[0]), 16, 0, 32}
9410 ,
9411 {&mcs_tbl_rev3, sizeof(mcs_tbl_rev3) / sizeof(mcs_tbl_rev3[0]), 18, 0,
9412 16}
9413 ,
9414 {&tdi_tbl20_ant0_rev3,
9415 sizeof(tdi_tbl20_ant0_rev3) / sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
9416 32}
9417 ,
9418 {&tdi_tbl20_ant1_rev3,
9419 sizeof(tdi_tbl20_ant1_rev3) / sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
9420 32}
9421 ,
9422 {&tdi_tbl40_ant0_rev3,
9423 sizeof(tdi_tbl40_ant0_rev3) / sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
9424 32}
9425 ,
9426 {&tdi_tbl40_ant1_rev3,
9427 sizeof(tdi_tbl40_ant1_rev3) / sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
9428 32}
9429 ,
9430 {&pltlut_tbl_rev3, sizeof(pltlut_tbl_rev3) / sizeof(pltlut_tbl_rev3[0]),
9431 20, 0, 32}
9432 ,
9433 {&chanest_tbl_rev3,
9434 sizeof(chanest_tbl_rev3) / sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
9435 ,
9436 {&frame_lut_rev3, sizeof(frame_lut_rev3) / sizeof(frame_lut_rev3[0]),
9437 24, 0, 8}
9438 ,
9439 {&est_pwr_lut_core0_rev3,
9440 sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
9441 0, 8}
9442 ,
9443 {&est_pwr_lut_core1_rev3,
9444 sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
9445 0, 8}
9446 ,
9447 {&adj_pwr_lut_core0_rev3,
9448 sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
9449 64, 8}
9450 ,
9451 {&adj_pwr_lut_core1_rev3,
9452 sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
9453 64, 8}
9454 ,
9455 {&gainctrl_lut_core0_rev3,
9456 sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
9457 26, 192, 32}
9458 ,
9459 {&gainctrl_lut_core1_rev3,
9460 sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
9461 27, 192, 32}
9462 ,
9463 {&iq_lut_core0_rev3,
9464 sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
9465 ,
9466 {&iq_lut_core1_rev3,
9467 sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
9468 ,
9469 {&loft_lut_core0_rev3,
9470 sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
9471 16}
9472 ,
9473 {&loft_lut_core1_rev3,
9474 sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
9475 16}
9476};
9477
9478const u32 mimophytbl_info_sz_rev3 =
9479 sizeof(mimophytbl_info_rev3) / sizeof(mimophytbl_info_rev3[0]);
9480const u32 mimophytbl_info_sz_rev3_volatile =
9481 sizeof(mimophytbl_info_rev3_volatile) /
9482 sizeof(mimophytbl_info_rev3_volatile[0]);
9483const u32 mimophytbl_info_sz_rev3_volatile1 =
9484 sizeof(mimophytbl_info_rev3_volatile1) /
9485 sizeof(mimophytbl_info_rev3_volatile1[0]);
9486const u32 mimophytbl_info_sz_rev3_volatile2 =
9487 sizeof(mimophytbl_info_rev3_volatile2) /
9488 sizeof(mimophytbl_info_rev3_volatile2[0]);
9489const u32 mimophytbl_info_sz_rev3_volatile3 =
9490 sizeof(mimophytbl_info_rev3_volatile3) /
9491 sizeof(mimophytbl_info_rev3_volatile3[0]);
9492
9493static const u32 tmap_tbl_rev7[] = {
9494 0x8a88aa80,
9495 0x8aaaaa8a,
9496 0x8a8a8aa8,
9497 0x00000888,
9498 0x88000000,
9499 0x8a8a88aa,
9500 0x8aa88888,
9501 0x8888a8a8,
9502 0xf1111110,
9503 0x11111111,
9504 0x11f11111,
9505 0x00000111,
9506 0x11000000,
9507 0x1111f111,
9508 0x11111111,
9509 0x111111f1,
9510 0x8a88aa80,
9511 0x8aaaaa8a,
9512 0x8a8a8aa8,
9513 0x000aa888,
9514 0x88880000,
9515 0x8a8a88aa,
9516 0x8aa88888,
9517 0x8888a8a8,
9518 0xa1111110,
9519 0x11111111,
9520 0x11c11111,
9521 0x00000111,
9522 0x11000000,
9523 0x1111a111,
9524 0x11111111,
9525 0x111111a1,
9526 0xa2222220,
9527 0x22222222,
9528 0x22c22222,
9529 0x00000222,
9530 0x22000000,
9531 0x2222a222,
9532 0x22222222,
9533 0x222222a2,
9534 0xf1111110,
9535 0x11111111,
9536 0x11f11111,
9537 0x00011111,
9538 0x11110000,
9539 0x1111f111,
9540 0x11111111,
9541 0x111111f1,
9542 0xa8aa88a0,
9543 0xa88888a8,
9544 0xa8a8a88a,
9545 0x00088aaa,
9546 0xaaaa0000,
9547 0xa8a8aa88,
9548 0xa88aaaaa,
9549 0xaaaa8a8a,
9550 0xaaa8aaa0,
9551 0x8aaa8aaa,
9552 0xaa8a8a8a,
9553 0x000aaa88,
9554 0x8aaa0000,
9555 0xaaa8a888,
9556 0x8aa88a8a,
9557 0x8a88a888,
9558 0x08080a00,
9559 0x0a08080a,
9560 0x080a0a08,
9561 0x00080808,
9562 0x080a0000,
9563 0x080a0808,
9564 0x080a0808,
9565 0x0a0a0a08,
9566 0xa0a0a0a0,
9567 0x80a0a080,
9568 0x8080a0a0,
9569 0x00008080,
9570 0x80a00000,
9571 0x80a080a0,
9572 0xa080a0a0,
9573 0x8080a0a0,
9574 0x00000000,
9575 0x00000000,
9576 0x00000000,
9577 0x00000000,
9578 0x00000000,
9579 0x00000000,
9580 0x00000000,
9581 0x00000000,
9582 0x00000000,
9583 0x00000000,
9584 0x00000000,
9585 0x00000000,
9586 0x00000000,
9587 0x00000000,
9588 0x00000000,
9589 0x00000000,
9590 0x00000000,
9591 0x00000000,
9592 0x00000000,
9593 0x00000000,
9594 0x00000000,
9595 0x00000000,
9596 0x00000000,
9597 0x00000000,
9598 0x00000000,
9599 0x00000000,
9600 0x00000000,
9601 0x00000000,
9602 0x00000000,
9603 0x00000000,
9604 0x00000000,
9605 0x00000000,
9606 0x00000000,
9607 0x00000000,
9608 0x00000000,
9609 0x00000000,
9610 0x00000000,
9611 0x00000000,
9612 0x00000000,
9613 0x00000000,
9614 0x00000000,
9615 0x00000000,
9616 0x00000000,
9617 0x00000000,
9618 0x00000000,
9619 0x00000000,
9620 0x00000000,
9621 0x00000000,
9622 0x99999000,
9623 0x9b9b99bb,
9624 0x9bb99999,
9625 0x9999b9b9,
9626 0x9b99bb90,
9627 0x9bbbbb9b,
9628 0x9b9b9bb9,
9629 0x00000999,
9630 0x88000000,
9631 0x8a8a88aa,
9632 0x8aa88888,
9633 0x8888a8a8,
9634 0x8a88aa80,
9635 0x8aaaaa8a,
9636 0x8a8a8aa8,
9637 0x00aaa888,
9638 0x22000000,
9639 0x2222b222,
9640 0x22222222,
9641 0x222222b2,
9642 0xb2222220,
9643 0x22222222,
9644 0x22d22222,
9645 0x00000222,
9646 0x11000000,
9647 0x1111a111,
9648 0x11111111,
9649 0x111111a1,
9650 0xa1111110,
9651 0x11111111,
9652 0x11c11111,
9653 0x00000111,
9654 0x33000000,
9655 0x3333b333,
9656 0x33333333,
9657 0x333333b3,
9658 0xb3333330,
9659 0x33333333,
9660 0x33d33333,
9661 0x00000333,
9662 0x22000000,
9663 0x2222a222,
9664 0x22222222,
9665 0x222222a2,
9666 0xa2222220,
9667 0x22222222,
9668 0x22c22222,
9669 0x00000222,
9670 0x99b99b00,
9671 0x9b9b99bb,
9672 0x9bb99999,
9673 0x9999b9b9,
9674 0x9b99bb99,
9675 0x9bbbbb9b,
9676 0x9b9b9bb9,
9677 0x00000999,
9678 0x88000000,
9679 0x8a8a88aa,
9680 0x8aa88888,
9681 0x8888a8a8,
9682 0x8a88aa88,
9683 0x8aaaaa8a,
9684 0x8a8a8aa8,
9685 0x08aaa888,
9686 0x22222200,
9687 0x2222f222,
9688 0x22222222,
9689 0x222222f2,
9690 0x22222222,
9691 0x22222222,
9692 0x22f22222,
9693 0x00000222,
9694 0x11000000,
9695 0x1111f111,
9696 0x11111111,
9697 0x11111111,
9698 0xf1111111,
9699 0x11111111,
9700 0x11f11111,
9701 0x01111111,
9702 0xbb9bb900,
9703 0xb9b9bb99,
9704 0xb99bbbbb,
9705 0xbbbb9b9b,
9706 0xb9bb99bb,
9707 0xb99999b9,
9708 0xb9b9b99b,
9709 0x00000bbb,
9710 0xaa000000,
9711 0xa8a8aa88,
9712 0xa88aaaaa,
9713 0xaaaa8a8a,
9714 0xa8aa88aa,
9715 0xa88888a8,
9716 0xa8a8a88a,
9717 0x0a888aaa,
9718 0xaa000000,
9719 0xa8a8aa88,
9720 0xa88aaaaa,
9721 0xaaaa8a8a,
9722 0xa8aa88a0,
9723 0xa88888a8,
9724 0xa8a8a88a,
9725 0x00000aaa,
9726 0x88000000,
9727 0x8a8a88aa,
9728 0x8aa88888,
9729 0x8888a8a8,
9730 0x8a88aa80,
9731 0x8aaaaa8a,
9732 0x8a8a8aa8,
9733 0x00000888,
9734 0xbbbbbb00,
9735 0x999bbbbb,
9736 0x9bb99b9b,
9737 0xb9b9b9bb,
9738 0xb9b99bbb,
9739 0xb9b9b9bb,
9740 0xb9bb9b99,
9741 0x00000999,
9742 0x8a000000,
9743 0xaa88a888,
9744 0xa88888aa,
9745 0xa88a8a88,
9746 0xa88aa88a,
9747 0x88a8aaaa,
9748 0xa8aa8aaa,
9749 0x0888a88a,
9750 0x0b0b0b00,
9751 0x090b0b0b,
9752 0x0b090b0b,
9753 0x0909090b,
9754 0x09090b0b,
9755 0x09090b0b,
9756 0x09090b09,
9757 0x00000909,
9758 0x0a000000,
9759 0x0a080808,
9760 0x080a080a,
9761 0x080a0a08,
9762 0x080a080a,
9763 0x0808080a,
9764 0x0a0a0a08,
9765 0x0808080a,
9766 0xb0b0b000,
9767 0x9090b0b0,
9768 0x90b09090,
9769 0xb0b0b090,
9770 0xb0b090b0,
9771 0x90b0b0b0,
9772 0xb0b09090,
9773 0x00000090,
9774 0x80000000,
9775 0xa080a080,
9776 0xa08080a0,
9777 0xa0808080,
9778 0xa080a080,
9779 0x80a0a0a0,
9780 0xa0a080a0,
9781 0x00a0a0a0,
9782 0x22000000,
9783 0x2222f222,
9784 0x22222222,
9785 0x222222f2,
9786 0xf2222220,
9787 0x22222222,
9788 0x22f22222,
9789 0x00000222,
9790 0x11000000,
9791 0x1111f111,
9792 0x11111111,
9793 0x111111f1,
9794 0xf1111110,
9795 0x11111111,
9796 0x11f11111,
9797 0x00000111,
9798 0x33000000,
9799 0x3333f333,
9800 0x33333333,
9801 0x333333f3,
9802 0xf3333330,
9803 0x33333333,
9804 0x33f33333,
9805 0x00000333,
9806 0x22000000,
9807 0x2222f222,
9808 0x22222222,
9809 0x222222f2,
9810 0xf2222220,
9811 0x22222222,
9812 0x22f22222,
9813 0x00000222,
9814 0x99000000,
9815 0x9b9b99bb,
9816 0x9bb99999,
9817 0x9999b9b9,
9818 0x9b99bb90,
9819 0x9bbbbb9b,
9820 0x9b9b9bb9,
9821 0x00000999,
9822 0x88000000,
9823 0x8a8a88aa,
9824 0x8aa88888,
9825 0x8888a8a8,
9826 0x8a88aa80,
9827 0x8aaaaa8a,
9828 0x8a8a8aa8,
9829 0x00000888,
9830 0x88888000,
9831 0x8a8a88aa,
9832 0x8aa88888,
9833 0x8888a8a8,
9834 0x8a88aa80,
9835 0x8aaaaa8a,
9836 0x8a8a8aa8,
9837 0x00000888,
9838 0x88000000,
9839 0x8a8a88aa,
9840 0x8aa88888,
9841 0x8888a8a8,
9842 0x8a88aa80,
9843 0x8aaaaa8a,
9844 0x8a8a8aa8,
9845 0x00aaa888,
9846 0x88a88a00,
9847 0x8a8a88aa,
9848 0x8aa88888,
9849 0x8888a8a8,
9850 0x8a88aa88,
9851 0x8aaaaa8a,
9852 0x8a8a8aa8,
9853 0x000aa888,
9854 0x88880000,
9855 0x8a8a88aa,
9856 0x8aa88888,
9857 0x8888a8a8,
9858 0x8a88aa88,
9859 0x8aaaaa8a,
9860 0x8a8a8aa8,
9861 0x08aaa888,
9862 0x11000000,
9863 0x1111a111,
9864 0x11111111,
9865 0x111111a1,
9866 0xa1111110,
9867 0x11111111,
9868 0x11c11111,
9869 0x00000111,
9870 0x11000000,
9871 0x1111a111,
9872 0x11111111,
9873 0x111111a1,
9874 0xa1111110,
9875 0x11111111,
9876 0x11c11111,
9877 0x00000111,
9878 0x88000000,
9879 0x8a8a88aa,
9880 0x8aa88888,
9881 0x8888a8a8,
9882 0x8a88aa80,
9883 0x8aaaaa8a,
9884 0x8a8a8aa8,
9885 0x00000888,
9886 0x88000000,
9887 0x8a8a88aa,
9888 0x8aa88888,
9889 0x8888a8a8,
9890 0x8a88aa80,
9891 0x8aaaaa8a,
9892 0x8a8a8aa8,
9893 0x00000888,
9894 0x00000000,
9895 0x00000000,
9896 0x00000000,
9897 0x00000000,
9898 0x00000000,
9899 0x00000000,
9900 0x00000000,
9901 0x00000000,
9902 0x00000000,
9903 0x00000000,
9904 0x00000000,
9905 0x00000000,
9906 0x00000000,
9907 0x00000000,
9908 0x00000000,
9909 0x00000000,
9910 0x00000000,
9911 0x00000000,
9912 0x00000000,
9913 0x00000000,
9914 0x00000000,
9915 0x00000000,
9916 0x00000000,
9917 0x00000000,
9918 0x00000000,
9919 0x00000000,
9920 0x00000000,
9921 0x00000000,
9922 0x00000000,
9923 0x00000000,
9924 0x00000000,
9925 0x00000000,
9926 0x00000000,
9927 0x00000000,
9928 0x00000000,
9929 0x00000000,
9930 0x00000000,
9931 0x00000000,
9932 0x00000000,
9933 0x00000000,
9934 0x00000000,
9935 0x00000000,
9936 0x00000000,
9937 0x00000000,
9938 0x00000000,
9939 0x00000000,
9940 0x00000000,
9941 0x00000000,
9942};
9943
9944const u32 noise_var_tbl_rev7[] = {
9945 0x020c020c,
9946 0x0000014d,
9947 0x020c020c,
9948 0x0000014d,
9949 0x020c020c,
9950 0x0000014d,
9951 0x020c020c,
9952 0x0000014d,
9953 0x020c020c,
9954 0x0000014d,
9955 0x020c020c,
9956 0x0000014d,
9957 0x020c020c,
9958 0x0000014d,
9959 0x020c020c,
9960 0x0000014d,
9961 0x020c020c,
9962 0x0000014d,
9963 0x020c020c,
9964 0x0000014d,
9965 0x020c020c,
9966 0x0000014d,
9967 0x020c020c,
9968 0x0000014d,
9969 0x020c020c,
9970 0x0000014d,
9971 0x020c020c,
9972 0x0000014d,
9973 0x020c020c,
9974 0x0000014d,
9975 0x020c020c,
9976 0x0000014d,
9977 0x020c020c,
9978 0x0000014d,
9979 0x020c020c,
9980 0x0000014d,
9981 0x020c020c,
9982 0x0000014d,
9983 0x020c020c,
9984 0x0000014d,
9985 0x020c020c,
9986 0x0000014d,
9987 0x020c020c,
9988 0x0000014d,
9989 0x020c020c,
9990 0x0000014d,
9991 0x020c020c,
9992 0x0000014d,
9993 0x020c020c,
9994 0x0000014d,
9995 0x020c020c,
9996 0x0000014d,
9997 0x020c020c,
9998 0x0000014d,
9999 0x020c020c,
10000 0x0000014d,
10001 0x020c020c,
10002 0x0000014d,
10003 0x020c020c,
10004 0x0000014d,
10005 0x020c020c,
10006 0x0000014d,
10007 0x020c020c,
10008 0x0000014d,
10009 0x020c020c,
10010 0x0000014d,
10011 0x020c020c,
10012 0x0000014d,
10013 0x020c020c,
10014 0x0000014d,
10015 0x020c020c,
10016 0x0000014d,
10017 0x020c020c,
10018 0x0000014d,
10019 0x020c020c,
10020 0x0000014d,
10021 0x020c020c,
10022 0x0000014d,
10023 0x020c020c,
10024 0x0000014d,
10025 0x020c020c,
10026 0x0000014d,
10027 0x020c020c,
10028 0x0000014d,
10029 0x020c020c,
10030 0x0000014d,
10031 0x020c020c,
10032 0x0000014d,
10033 0x020c020c,
10034 0x0000014d,
10035 0x020c020c,
10036 0x0000014d,
10037 0x020c020c,
10038 0x0000014d,
10039 0x020c020c,
10040 0x0000014d,
10041 0x020c020c,
10042 0x0000014d,
10043 0x020c020c,
10044 0x0000014d,
10045 0x020c020c,
10046 0x0000014d,
10047 0x020c020c,
10048 0x0000014d,
10049 0x020c020c,
10050 0x0000014d,
10051 0x020c020c,
10052 0x0000014d,
10053 0x020c020c,
10054 0x0000014d,
10055 0x020c020c,
10056 0x0000014d,
10057 0x020c020c,
10058 0x0000014d,
10059 0x020c020c,
10060 0x0000014d,
10061 0x020c020c,
10062 0x0000014d,
10063 0x020c020c,
10064 0x0000014d,
10065 0x020c020c,
10066 0x0000014d,
10067 0x020c020c,
10068 0x0000014d,
10069 0x020c020c,
10070 0x0000014d,
10071 0x020c020c,
10072 0x0000014d,
10073 0x020c020c,
10074 0x0000014d,
10075 0x020c020c,
10076 0x0000014d,
10077 0x020c020c,
10078 0x0000014d,
10079 0x020c020c,
10080 0x0000014d,
10081 0x020c020c,
10082 0x0000014d,
10083 0x020c020c,
10084 0x0000014d,
10085 0x020c020c,
10086 0x0000014d,
10087 0x020c020c,
10088 0x0000014d,
10089 0x020c020c,
10090 0x0000014d,
10091 0x020c020c,
10092 0x0000014d,
10093 0x020c020c,
10094 0x0000014d,
10095 0x020c020c,
10096 0x0000014d,
10097 0x020c020c,
10098 0x0000014d,
10099 0x020c020c,
10100 0x0000014d,
10101 0x020c020c,
10102 0x0000014d,
10103 0x020c020c,
10104 0x0000014d,
10105 0x020c020c,
10106 0x0000014d,
10107 0x020c020c,
10108 0x0000014d,
10109 0x020c020c,
10110 0x0000014d,
10111 0x020c020c,
10112 0x0000014d,
10113 0x020c020c,
10114 0x0000014d,
10115 0x020c020c,
10116 0x0000014d,
10117 0x020c020c,
10118 0x0000014d,
10119 0x020c020c,
10120 0x0000014d,
10121 0x020c020c,
10122 0x0000014d,
10123 0x020c020c,
10124 0x0000014d,
10125 0x020c020c,
10126 0x0000014d,
10127 0x020c020c,
10128 0x0000014d,
10129 0x020c020c,
10130 0x0000014d,
10131 0x020c020c,
10132 0x0000014d,
10133 0x020c020c,
10134 0x0000014d,
10135 0x020c020c,
10136 0x0000014d,
10137 0x020c020c,
10138 0x0000014d,
10139 0x020c020c,
10140 0x0000014d,
10141 0x020c020c,
10142 0x0000014d,
10143 0x020c020c,
10144 0x0000014d,
10145 0x020c020c,
10146 0x0000014d,
10147 0x020c020c,
10148 0x0000014d,
10149 0x020c020c,
10150 0x0000014d,
10151 0x020c020c,
10152 0x0000014d,
10153 0x020c020c,
10154 0x0000014d,
10155 0x020c020c,
10156 0x0000014d,
10157 0x020c020c,
10158 0x0000014d,
10159 0x020c020c,
10160 0x0000014d,
10161 0x020c020c,
10162 0x0000014d,
10163 0x020c020c,
10164 0x0000014d,
10165 0x020c020c,
10166 0x0000014d,
10167 0x020c020c,
10168 0x0000014d,
10169 0x020c020c,
10170 0x0000014d,
10171 0x020c020c,
10172 0x0000014d,
10173 0x020c020c,
10174 0x0000014d,
10175 0x020c020c,
10176 0x0000014d,
10177 0x020c020c,
10178 0x0000014d,
10179 0x020c020c,
10180 0x0000014d,
10181 0x020c020c,
10182 0x0000014d,
10183 0x020c020c,
10184 0x0000014d,
10185 0x020c020c,
10186 0x0000014d,
10187 0x020c020c,
10188 0x0000014d,
10189 0x020c020c,
10190 0x0000014d,
10191 0x020c020c,
10192 0x0000014d,
10193 0x020c020c,
10194 0x0000014d,
10195 0x020c020c,
10196 0x0000014d,
10197 0x020c020c,
10198 0x0000014d,
10199 0x020c020c,
10200 0x0000014d,
10201};
10202
10203static const u32 papd_comp_epsilon_tbl_core0_rev7[] = {
10204 0x00000000,
10205 0x00000000,
10206 0x00016023,
10207 0x00006028,
10208 0x00034036,
10209 0x0003402e,
10210 0x0007203c,
10211 0x0006e037,
10212 0x00070030,
10213 0x0009401f,
10214 0x0009a00f,
10215 0x000b600d,
10216 0x000c8007,
10217 0x000ce007,
10218 0x00101fff,
10219 0x00121ff9,
10220 0x0012e004,
10221 0x0014dffc,
10222 0x0016dff6,
10223 0x0018dfe9,
10224 0x001b3fe5,
10225 0x001c5fd0,
10226 0x001ddfc2,
10227 0x001f1fb6,
10228 0x00207fa4,
10229 0x00219f8f,
10230 0x0022ff7d,
10231 0x00247f6c,
10232 0x0024df5b,
10233 0x00267f4b,
10234 0x0027df3b,
10235 0x0029bf3b,
10236 0x002b5f2f,
10237 0x002d3f2e,
10238 0x002f5f2a,
10239 0x002fff15,
10240 0x00315f0b,
10241 0x0032defa,
10242 0x0033beeb,
10243 0x0034fed9,
10244 0x00353ec5,
10245 0x00361eb0,
10246 0x00363e9b,
10247 0x0036be87,
10248 0x0036be70,
10249 0x0038fe67,
10250 0x0044beb2,
10251 0x00513ef3,
10252 0x00595f11,
10253 0x00669f3d,
10254 0x0078dfdf,
10255 0x00a143aa,
10256 0x01642fff,
10257 0x0162afff,
10258 0x01620fff,
10259 0x0160cfff,
10260 0x015f0fff,
10261 0x015dafff,
10262 0x015bcfff,
10263 0x015bcfff,
10264 0x015b4fff,
10265 0x015acfff,
10266 0x01590fff,
10267 0x0156cfff,
10268};
10269
10270static const u32 papd_cal_scalars_tbl_core0_rev7[] = {
10271 0x0b5e002d,
10272 0x0ae2002f,
10273 0x0a3b0032,
10274 0x09a70035,
10275 0x09220038,
10276 0x08ab003b,
10277 0x081f003f,
10278 0x07a20043,
10279 0x07340047,
10280 0x06d2004b,
10281 0x067a004f,
10282 0x06170054,
10283 0x05bf0059,
10284 0x0571005e,
10285 0x051e0064,
10286 0x04d3006a,
10287 0x04910070,
10288 0x044c0077,
10289 0x040f007e,
10290 0x03d90085,
10291 0x03a1008d,
10292 0x036f0095,
10293 0x033d009e,
10294 0x030b00a8,
10295 0x02e000b2,
10296 0x02b900bc,
10297 0x029200c7,
10298 0x026d00d3,
10299 0x024900e0,
10300 0x022900ed,
10301 0x020a00fb,
10302 0x01ec010a,
10303 0x01d20119,
10304 0x01b7012a,
10305 0x019e013c,
10306 0x0188014e,
10307 0x01720162,
10308 0x015d0177,
10309 0x0149018e,
10310 0x013701a5,
10311 0x012601be,
10312 0x011501d8,
10313 0x010601f4,
10314 0x00f70212,
10315 0x00e90231,
10316 0x00dc0253,
10317 0x00d00276,
10318 0x00c4029b,
10319 0x00b902c3,
10320 0x00af02ed,
10321 0x00a50319,
10322 0x009c0348,
10323 0x0093037a,
10324 0x008b03af,
10325 0x008303e6,
10326 0x007c0422,
10327 0x00750460,
10328 0x006e04a3,
10329 0x006804e9,
10330 0x00620533,
10331 0x005d0582,
10332 0x005805d6,
10333 0x0053062e,
10334 0x004e068c,
10335};
10336
10337static const u32 papd_comp_epsilon_tbl_core1_rev7[] = {
10338 0x00000000,
10339 0x00000000,
10340 0x00016023,
10341 0x00006028,
10342 0x00034036,
10343 0x0003402e,
10344 0x0007203c,
10345 0x0006e037,
10346 0x00070030,
10347 0x0009401f,
10348 0x0009a00f,
10349 0x000b600d,
10350 0x000c8007,
10351 0x000ce007,
10352 0x00101fff,
10353 0x00121ff9,
10354 0x0012e004,
10355 0x0014dffc,
10356 0x0016dff6,
10357 0x0018dfe9,
10358 0x001b3fe5,
10359 0x001c5fd0,
10360 0x001ddfc2,
10361 0x001f1fb6,
10362 0x00207fa4,
10363 0x00219f8f,
10364 0x0022ff7d,
10365 0x00247f6c,
10366 0x0024df5b,
10367 0x00267f4b,
10368 0x0027df3b,
10369 0x0029bf3b,
10370 0x002b5f2f,
10371 0x002d3f2e,
10372 0x002f5f2a,
10373 0x002fff15,
10374 0x00315f0b,
10375 0x0032defa,
10376 0x0033beeb,
10377 0x0034fed9,
10378 0x00353ec5,
10379 0x00361eb0,
10380 0x00363e9b,
10381 0x0036be87,
10382 0x0036be70,
10383 0x0038fe67,
10384 0x0044beb2,
10385 0x00513ef3,
10386 0x00595f11,
10387 0x00669f3d,
10388 0x0078dfdf,
10389 0x00a143aa,
10390 0x01642fff,
10391 0x0162afff,
10392 0x01620fff,
10393 0x0160cfff,
10394 0x015f0fff,
10395 0x015dafff,
10396 0x015bcfff,
10397 0x015bcfff,
10398 0x015b4fff,
10399 0x015acfff,
10400 0x01590fff,
10401 0x0156cfff,
10402};
10403
10404static const u32 papd_cal_scalars_tbl_core1_rev7[] = {
10405 0x0b5e002d,
10406 0x0ae2002f,
10407 0x0a3b0032,
10408 0x09a70035,
10409 0x09220038,
10410 0x08ab003b,
10411 0x081f003f,
10412 0x07a20043,
10413 0x07340047,
10414 0x06d2004b,
10415 0x067a004f,
10416 0x06170054,
10417 0x05bf0059,
10418 0x0571005e,
10419 0x051e0064,
10420 0x04d3006a,
10421 0x04910070,
10422 0x044c0077,
10423 0x040f007e,
10424 0x03d90085,
10425 0x03a1008d,
10426 0x036f0095,
10427 0x033d009e,
10428 0x030b00a8,
10429 0x02e000b2,
10430 0x02b900bc,
10431 0x029200c7,
10432 0x026d00d3,
10433 0x024900e0,
10434 0x022900ed,
10435 0x020a00fb,
10436 0x01ec010a,
10437 0x01d20119,
10438 0x01b7012a,
10439 0x019e013c,
10440 0x0188014e,
10441 0x01720162,
10442 0x015d0177,
10443 0x0149018e,
10444 0x013701a5,
10445 0x012601be,
10446 0x011501d8,
10447 0x010601f4,
10448 0x00f70212,
10449 0x00e90231,
10450 0x00dc0253,
10451 0x00d00276,
10452 0x00c4029b,
10453 0x00b902c3,
10454 0x00af02ed,
10455 0x00a50319,
10456 0x009c0348,
10457 0x0093037a,
10458 0x008b03af,
10459 0x008303e6,
10460 0x007c0422,
10461 0x00750460,
10462 0x006e04a3,
10463 0x006804e9,
10464 0x00620533,
10465 0x005d0582,
10466 0x005805d6,
10467 0x0053062e,
10468 0x004e068c,
10469};
10470
10471const struct phytbl_info mimophytbl_info_rev7[] = {
10472 {&frame_struct_rev3,
10473 sizeof(frame_struct_rev3) / sizeof(frame_struct_rev3[0]), 10, 0, 32}
10474 ,
10475 {&pilot_tbl_rev3, sizeof(pilot_tbl_rev3) / sizeof(pilot_tbl_rev3[0]),
10476 11, 0, 16}
10477 ,
10478 {&tmap_tbl_rev7, sizeof(tmap_tbl_rev7) / sizeof(tmap_tbl_rev7[0]), 12,
10479 0, 32}
10480 ,
10481 {&intlv_tbl_rev3, sizeof(intlv_tbl_rev3) / sizeof(intlv_tbl_rev3[0]),
10482 13, 0, 32}
10483 ,
10484 {&tdtrn_tbl_rev3, sizeof(tdtrn_tbl_rev3) / sizeof(tdtrn_tbl_rev3[0]),
10485 14, 0, 32}
10486 ,
10487 {&noise_var_tbl_rev7,
10488 sizeof(noise_var_tbl_rev7) / sizeof(noise_var_tbl_rev7[0]), 16, 0, 32}
10489 ,
10490 {&mcs_tbl_rev3, sizeof(mcs_tbl_rev3) / sizeof(mcs_tbl_rev3[0]), 18, 0,
10491 16}
10492 ,
10493 {&tdi_tbl20_ant0_rev3,
10494 sizeof(tdi_tbl20_ant0_rev3) / sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
10495 32}
10496 ,
10497 {&tdi_tbl20_ant1_rev3,
10498 sizeof(tdi_tbl20_ant1_rev3) / sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
10499 32}
10500 ,
10501 {&tdi_tbl40_ant0_rev3,
10502 sizeof(tdi_tbl40_ant0_rev3) / sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
10503 32}
10504 ,
10505 {&tdi_tbl40_ant1_rev3,
10506 sizeof(tdi_tbl40_ant1_rev3) / sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
10507 32}
10508 ,
10509 {&pltlut_tbl_rev3, sizeof(pltlut_tbl_rev3) / sizeof(pltlut_tbl_rev3[0]),
10510 20, 0, 32}
10511 ,
10512 {&chanest_tbl_rev3,
10513 sizeof(chanest_tbl_rev3) / sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
10514 ,
10515 {&frame_lut_rev3, sizeof(frame_lut_rev3) / sizeof(frame_lut_rev3[0]),
10516 24, 0, 8}
10517 ,
10518 {&est_pwr_lut_core0_rev3,
10519 sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
10520 0, 8}
10521 ,
10522 {&est_pwr_lut_core1_rev3,
10523 sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
10524 0, 8}
10525 ,
10526 {&adj_pwr_lut_core0_rev3,
10527 sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
10528 64, 8}
10529 ,
10530 {&adj_pwr_lut_core1_rev3,
10531 sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
10532 64, 8}
10533 ,
10534 {&gainctrl_lut_core0_rev3,
10535 sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
10536 26, 192, 32}
10537 ,
10538 {&gainctrl_lut_core1_rev3,
10539 sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
10540 27, 192, 32}
10541 ,
10542 {&iq_lut_core0_rev3,
10543 sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
10544 ,
10545 {&iq_lut_core1_rev3,
10546 sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
10547 ,
10548 {&loft_lut_core0_rev3,
10549 sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
10550 16}
10551 ,
10552 {&loft_lut_core1_rev3,
10553 sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
10554 16}
10555 ,
10556 {&papd_comp_rfpwr_tbl_core0_rev3,
10557 sizeof(papd_comp_rfpwr_tbl_core0_rev3) /
10558 sizeof(papd_comp_rfpwr_tbl_core0_rev3[0]), 26, 576, 16}
10559 ,
10560 {&papd_comp_rfpwr_tbl_core1_rev3,
10561 sizeof(papd_comp_rfpwr_tbl_core1_rev3) /
10562 sizeof(papd_comp_rfpwr_tbl_core1_rev3[0]), 27, 576, 16}
10563 ,
10564 {&papd_comp_epsilon_tbl_core0_rev7,
10565 sizeof(papd_comp_epsilon_tbl_core0_rev7) /
10566 sizeof(papd_comp_epsilon_tbl_core0_rev7[0]), 31, 0, 32}
10567 ,
10568 {&papd_cal_scalars_tbl_core0_rev7,
10569 sizeof(papd_cal_scalars_tbl_core0_rev7) /
10570 sizeof(papd_cal_scalars_tbl_core0_rev7[0]), 32, 0, 32}
10571 ,
10572 {&papd_comp_epsilon_tbl_core1_rev7,
10573 sizeof(papd_comp_epsilon_tbl_core1_rev7) /
10574 sizeof(papd_comp_epsilon_tbl_core1_rev7[0]), 33, 0, 32}
10575 ,
10576 {&papd_cal_scalars_tbl_core1_rev7,
10577 sizeof(papd_cal_scalars_tbl_core1_rev7) /
10578 sizeof(papd_cal_scalars_tbl_core1_rev7[0]), 34, 0, 32}
10579 ,
10580};
10581
10582const u32 mimophytbl_info_sz_rev7 =
10583 sizeof(mimophytbl_info_rev7) / sizeof(mimophytbl_info_rev7[0]);
10584
10585const struct phytbl_info mimophytbl_info_rev16[] = {
10586 {&noise_var_tbl_rev7,
10587 sizeof(noise_var_tbl_rev7) / sizeof(noise_var_tbl_rev7[0]), 16, 0, 32}
10588 ,
10589 {&est_pwr_lut_core0_rev3,
10590 sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
10591 0, 8}
10592 ,
10593 {&est_pwr_lut_core1_rev3,
10594 sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
10595 0, 8}
10596 ,
10597 {&adj_pwr_lut_core0_rev3,
10598 sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
10599 64, 8}
10600 ,
10601 {&adj_pwr_lut_core1_rev3,
10602 sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
10603 64, 8}
10604 ,
10605 {&gainctrl_lut_core0_rev3,
10606 sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
10607 26, 192, 32}
10608 ,
10609 {&gainctrl_lut_core1_rev3,
10610 sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
10611 27, 192, 32}
10612 ,
10613 {&iq_lut_core0_rev3,
10614 sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
10615 ,
10616 {&iq_lut_core1_rev3,
10617 sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
10618 ,
10619 {&loft_lut_core0_rev3,
10620 sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
10621 16}
10622 ,
10623 {&loft_lut_core1_rev3,
10624 sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
10625 16}
10626 ,
10627};
10628
10629const u32 mimophytbl_info_sz_rev16 =
10630 sizeof(mimophytbl_info_rev16) / sizeof(mimophytbl_info_rev16[0]);
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.h b/drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.h
deleted file mode 100644
index dc8a84e8511..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define ANT_SWCTRL_TBL_REV3_IDX (0)
18
19#include <types.h>
20#include "phy_int.h"
21
22extern const struct phytbl_info mimophytbl_info_rev0[],
23 mimophytbl_info_rev0_volatile[];
24
25extern const u32 mimophytbl_info_sz_rev0,
26 mimophytbl_info_sz_rev0_volatile;
27
28extern const struct phytbl_info mimophytbl_info_rev3[],
29 mimophytbl_info_rev3_volatile[],
30 mimophytbl_info_rev3_volatile1[],
31 mimophytbl_info_rev3_volatile2[],
32 mimophytbl_info_rev3_volatile3[];
33
34extern const u32 mimophytbl_info_sz_rev3,
35 mimophytbl_info_sz_rev3_volatile,
36 mimophytbl_info_sz_rev3_volatile1,
37 mimophytbl_info_sz_rev3_volatile2,
38 mimophytbl_info_sz_rev3_volatile3;
39
40extern const u32 noise_var_tbl_rev3[];
41
42extern const struct phytbl_info mimophytbl_info_rev7[];
43
44extern const u32 mimophytbl_info_sz_rev7;
45
46extern const u32 noise_var_tbl_rev7[];
47
48extern const struct phytbl_info mimophytbl_info_rev16[];
49
50extern const u32 mimophytbl_info_sz_rev16;
diff --git a/drivers/staging/brcm80211/brcmsmac/phy_shim.c b/drivers/staging/brcm80211/brcmsmac/phy_shim.c
deleted file mode 100644
index 676222ec2b8..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy_shim.c
+++ /dev/null
@@ -1,226 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*
18 * This is "two-way" interface, acting as the SHIM layer between driver
19 * and PHY layer. The driver can optionally call this translation layer
20 * to do some preprocessing, then reach PHY. On the PHY->driver direction,
21 * all calls go through this layer since PHY doesn't have access to the
22 * driver's brcms_hardware pointer.
23 */
24#include <linux/slab.h>
25#include <net/mac80211.h>
26
27#include "main.h"
28#include "mac80211_if.h"
29#include "phy_shim.h"
30
31/* PHY SHIM module specific state */
32struct phy_shim_info {
33 struct brcms_hardware *wlc_hw; /* pointer to main wlc_hw structure */
34 struct brcms_c_info *wlc; /* pointer to main wlc structure */
35 struct brcms_info *wl; /* pointer to os-specific private state */
36};
37
38struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw,
39 struct brcms_info *wl,
40 struct brcms_c_info *wlc) {
41 struct phy_shim_info *physhim = NULL;
42
43 physhim = kzalloc(sizeof(struct phy_shim_info), GFP_ATOMIC);
44 if (!physhim)
45 return NULL;
46
47 physhim->wlc_hw = wlc_hw;
48 physhim->wlc = wlc;
49 physhim->wl = wl;
50
51 return physhim;
52}
53
54void wlc_phy_shim_detach(struct phy_shim_info *physhim)
55{
56 kfree(physhim);
57}
58
59struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim,
60 void (*fn)(struct brcms_phy *pi),
61 void *arg, const char *name)
62{
63 return (struct wlapi_timer *)
64 brcms_init_timer(physhim->wl, (void (*)(void *))fn,
65 arg, name);
66}
67
68void wlapi_free_timer(struct phy_shim_info *physhim, struct wlapi_timer *t)
69{
70 brcms_free_timer(physhim->wl, (struct brcms_timer *)t);
71}
72
73void
74wlapi_add_timer(struct phy_shim_info *physhim, struct wlapi_timer *t, uint ms,
75 int periodic)
76{
77 brcms_add_timer(physhim->wl, (struct brcms_timer *)t, ms, periodic);
78}
79
80bool wlapi_del_timer(struct phy_shim_info *physhim, struct wlapi_timer *t)
81{
82 return brcms_del_timer(physhim->wl, (struct brcms_timer *)t);
83}
84
85void wlapi_intrson(struct phy_shim_info *physhim)
86{
87 brcms_intrson(physhim->wl);
88}
89
90u32 wlapi_intrsoff(struct phy_shim_info *physhim)
91{
92 return brcms_intrsoff(physhim->wl);
93}
94
95void wlapi_intrsrestore(struct phy_shim_info *physhim, u32 macintmask)
96{
97 brcms_intrsrestore(physhim->wl, macintmask);
98}
99
100void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v)
101{
102 brcms_b_write_shm(physhim->wlc_hw, offset, v);
103}
104
105u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim, uint offset)
106{
107 return brcms_b_read_shm(physhim->wlc_hw, offset);
108}
109
110void
111wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask,
112 u16 val, int bands)
113{
114 brcms_b_mhf(physhim->wlc_hw, idx, mask, val, bands);
115}
116
117void wlapi_bmac_corereset(struct phy_shim_info *physhim, u32 flags)
118{
119 brcms_b_corereset(physhim->wlc_hw, flags);
120}
121
122void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim)
123{
124 brcms_c_suspend_mac_and_wait(physhim->wlc);
125}
126
127void wlapi_switch_macfreq(struct phy_shim_info *physhim, u8 spurmode)
128{
129 brcms_b_switch_macfreq(physhim->wlc_hw, spurmode);
130}
131
132void wlapi_enable_mac(struct phy_shim_info *physhim)
133{
134 brcms_c_enable_mac(physhim->wlc);
135}
136
137void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val)
138{
139 brcms_b_mctrl(physhim->wlc_hw, mask, val);
140}
141
142void wlapi_bmac_phy_reset(struct phy_shim_info *physhim)
143{
144 brcms_b_phy_reset(physhim->wlc_hw);
145}
146
147void wlapi_bmac_bw_set(struct phy_shim_info *physhim, u16 bw)
148{
149 brcms_b_bw_set(physhim->wlc_hw, bw);
150}
151
152u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim)
153{
154 return brcms_b_get_txant(physhim->wlc_hw);
155}
156
157void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim, bool clk)
158{
159 brcms_b_phyclk_fgc(physhim->wlc_hw, clk);
160}
161
162void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim, bool clk)
163{
164 brcms_b_macphyclk_set(physhim->wlc_hw, clk);
165}
166
167void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim, bool on)
168{
169 brcms_b_core_phypll_ctl(physhim->wlc_hw, on);
170}
171
172void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim)
173{
174 brcms_b_core_phypll_reset(physhim->wlc_hw);
175}
176
177void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *physhim)
178{
179 brcms_c_ucode_wake_override_set(physhim->wlc_hw,
180 BRCMS_WAKE_OVERRIDE_PHYREG);
181}
182
183void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *physhim)
184{
185 brcms_c_ucode_wake_override_clear(physhim->wlc_hw,
186 BRCMS_WAKE_OVERRIDE_PHYREG);
187}
188
189void
190wlapi_bmac_write_template_ram(struct phy_shim_info *physhim, int offset,
191 int len, void *buf)
192{
193 brcms_b_write_template_ram(physhim->wlc_hw, offset, len, buf);
194}
195
196u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim, u8 rate)
197{
198 return brcms_b_rate_shm_offset(physhim->wlc_hw, rate);
199}
200
201void wlapi_ucode_sample_init(struct phy_shim_info *physhim)
202{
203}
204
205void
206wlapi_copyfrom_objmem(struct phy_shim_info *physhim, uint offset, void *buf,
207 int len, u32 sel)
208{
209 brcms_b_copyfrom_objmem(physhim->wlc_hw, offset, buf, len, sel);
210}
211
212void
213wlapi_copyto_objmem(struct phy_shim_info *physhim, uint offset, const void *buf,
214 int l, u32 sel)
215{
216 brcms_b_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel);
217}
218
219char *wlapi_getvar(struct phy_shim_info *physhim, enum brcms_srom_id id)
220{
221 return getvar(physhim->wlc_hw->sih, id);
222}
223int wlapi_getintvar(struct phy_shim_info *physhim, enum brcms_srom_id id)
224{
225 return getintvar(physhim->wlc_hw->sih, id);
226}
diff --git a/drivers/staging/brcm80211/brcmsmac/phy_shim.h b/drivers/staging/brcm80211/brcmsmac/phy_shim.h
deleted file mode 100644
index 8de549dfb1c..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/phy_shim.h
+++ /dev/null
@@ -1,185 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*
18 * phy_shim.h: stuff defined in phy_shim.c and included only by the phy
19 */
20
21#ifndef _BRCM_PHY_SHIM_H_
22#define _BRCM_PHY_SHIM_H_
23
24#include "types.h"
25
26#define RADAR_TYPE_NONE 0 /* Radar type None */
27#define RADAR_TYPE_ETSI_1 1 /* ETSI 1 Radar type */
28#define RADAR_TYPE_ETSI_2 2 /* ETSI 2 Radar type */
29#define RADAR_TYPE_ETSI_3 3 /* ETSI 3 Radar type */
30#define RADAR_TYPE_ITU_E 4 /* ITU E Radar type */
31#define RADAR_TYPE_ITU_K 5 /* ITU K Radar type */
32#define RADAR_TYPE_UNCLASSIFIED 6 /* Unclassified Radar type */
33#define RADAR_TYPE_BIN5 7 /* long pulse radar type */
34#define RADAR_TYPE_STG2 8 /* staggered-2 radar */
35#define RADAR_TYPE_STG3 9 /* staggered-3 radar */
36#define RADAR_TYPE_FRA 10 /* French radar */
37
38/* French radar pulse widths */
39#define FRA_T1_20MHZ 52770
40#define FRA_T2_20MHZ 61538
41#define FRA_T3_20MHZ 66002
42#define FRA_T1_40MHZ 105541
43#define FRA_T2_40MHZ 123077
44#define FRA_T3_40MHZ 132004
45#define FRA_ERR_20MHZ 60
46#define FRA_ERR_40MHZ 120
47
48#define ANTSEL_NA 0 /* No boardlevel selection available */
49#define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */
50#define ANTSEL_2x3 2 /* 2x3 CB2 boardlevel selection available */
51
52/* Rx Antenna diversity control values */
53#define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */
54#define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
55#define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
56#define ANT_RX_DIV_START_0 3 /* Choose starting with 0 */
57#define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */
58#define ANT_RX_DIV_DEF ANT_RX_DIV_START_0 /* default antdiv setting */
59
60#define WL_ANT_RX_MAX 2 /* max 2 receive antennas */
61#define WL_ANT_HT_RX_MAX 3 /* max 3 receive antennas/cores */
62#define WL_ANT_IDX_1 0 /* antenna index 1 */
63#define WL_ANT_IDX_2 1 /* antenna index 2 */
64
65/* values for n_preamble_type */
66#define BRCMS_N_PREAMBLE_MIXEDMODE 0
67#define BRCMS_N_PREAMBLE_GF 1
68#define BRCMS_N_PREAMBLE_GF_BRCM 2
69
70#define WL_TX_POWER_RATES_LEGACY 45
71#define WL_TX_POWER_MCS20_FIRST 12
72#define WL_TX_POWER_MCS20_NUM 16
73#define WL_TX_POWER_MCS40_FIRST 28
74#define WL_TX_POWER_MCS40_NUM 17
75
76
77#define WL_TX_POWER_RATES 101
78#define WL_TX_POWER_CCK_FIRST 0
79#define WL_TX_POWER_CCK_NUM 4
80/* Index for first 20MHz OFDM SISO rate */
81#define WL_TX_POWER_OFDM_FIRST 4
82/* Index for first 20MHz OFDM CDD rate */
83#define WL_TX_POWER_OFDM20_CDD_FIRST 12
84/* Index for first 40MHz OFDM SISO rate */
85#define WL_TX_POWER_OFDM40_SISO_FIRST 52
86/* Index for first 40MHz OFDM CDD rate */
87#define WL_TX_POWER_OFDM40_CDD_FIRST 60
88#define WL_TX_POWER_OFDM_NUM 8
89/* Index for first 20MHz MCS SISO rate */
90#define WL_TX_POWER_MCS20_SISO_FIRST 20
91/* Index for first 20MHz MCS CDD rate */
92#define WL_TX_POWER_MCS20_CDD_FIRST 28
93/* Index for first 20MHz MCS STBC rate */
94#define WL_TX_POWER_MCS20_STBC_FIRST 36
95/* Index for first 20MHz MCS SDM rate */
96#define WL_TX_POWER_MCS20_SDM_FIRST 44
97/* Index for first 40MHz MCS SISO rate */
98#define WL_TX_POWER_MCS40_SISO_FIRST 68
99/* Index for first 40MHz MCS CDD rate */
100#define WL_TX_POWER_MCS40_CDD_FIRST 76
101/* Index for first 40MHz MCS STBC rate */
102#define WL_TX_POWER_MCS40_STBC_FIRST 84
103/* Index for first 40MHz MCS SDM rate */
104#define WL_TX_POWER_MCS40_SDM_FIRST 92
105#define WL_TX_POWER_MCS_1_STREAM_NUM 8
106#define WL_TX_POWER_MCS_2_STREAM_NUM 8
107/* Index for 40MHz rate MCS 32 */
108#define WL_TX_POWER_MCS_32 100
109#define WL_TX_POWER_MCS_32_NUM 1
110
111/* sslpnphy specifics */
112/* Index for first 20MHz MCS SISO rate */
113#define WL_TX_POWER_MCS20_SISO_FIRST_SSN 12
114
115/* struct tx_power::flags bits */
116#define WL_TX_POWER_F_ENABLED 1
117#define WL_TX_POWER_F_HW 2
118#define WL_TX_POWER_F_MIMO 4
119#define WL_TX_POWER_F_SISO 8
120
121/* values to force tx/rx chain */
122#define BRCMS_N_TXRX_CHAIN0 0
123#define BRCMS_N_TXRX_CHAIN1 1
124
125struct brcms_phy;
126
127extern struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw,
128 struct brcms_info *wl,
129 struct brcms_c_info *wlc);
130extern void wlc_phy_shim_detach(struct phy_shim_info *physhim);
131
132/* PHY to WL utility functions */
133extern struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim,
134 void (*fn) (struct brcms_phy *pi),
135 void *arg, const char *name);
136extern void wlapi_free_timer(struct phy_shim_info *physhim,
137 struct wlapi_timer *t);
138extern void wlapi_add_timer(struct phy_shim_info *physhim,
139 struct wlapi_timer *t, uint ms, int periodic);
140extern bool wlapi_del_timer(struct phy_shim_info *physhim,
141 struct wlapi_timer *t);
142extern void wlapi_intrson(struct phy_shim_info *physhim);
143extern u32 wlapi_intrsoff(struct phy_shim_info *physhim);
144extern void wlapi_intrsrestore(struct phy_shim_info *physhim,
145 u32 macintmask);
146
147extern void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset,
148 u16 v);
149extern u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim, uint offset);
150extern void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx,
151 u16 mask, u16 val, int bands);
152extern void wlapi_bmac_corereset(struct phy_shim_info *physhim, u32 flags);
153extern void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim);
154extern void wlapi_switch_macfreq(struct phy_shim_info *physhim, u8 spurmode);
155extern void wlapi_enable_mac(struct phy_shim_info *physhim);
156extern void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask,
157 u32 val);
158extern void wlapi_bmac_phy_reset(struct phy_shim_info *physhim);
159extern void wlapi_bmac_bw_set(struct phy_shim_info *physhim, u16 bw);
160extern void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim, bool clk);
161extern void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim, bool clk);
162extern void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim, bool on);
163extern void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim);
164extern void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *
165 physhim);
166extern void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *
167 physhim);
168extern void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim, int o,
169 int len, void *buf);
170extern u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim,
171 u8 rate);
172extern void wlapi_ucode_sample_init(struct phy_shim_info *physhim);
173extern void wlapi_copyfrom_objmem(struct phy_shim_info *physhim, uint,
174 void *buf, int, u32 sel);
175extern void wlapi_copyto_objmem(struct phy_shim_info *physhim, uint,
176 const void *buf, int, u32);
177
178extern void wlapi_high_update_phy_mode(struct phy_shim_info *physhim,
179 u32 phy_mode);
180extern u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim);
181extern char *wlapi_getvar(struct phy_shim_info *physhim, enum brcms_srom_id id);
182extern int wlapi_getintvar(struct phy_shim_info *physhim,
183 enum brcms_srom_id id);
184
185#endif /* _BRCM_PHY_SHIM_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/pmu.c b/drivers/staging/brcm80211/brcmsmac/pmu.c
deleted file mode 100644
index 3b36e3acfd7..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/pmu.c
+++ /dev/null
@@ -1,458 +0,0 @@
1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/delay.h>
18#include <linux/io.h>
19
20#include <brcm_hw_ids.h>
21#include <chipcommon.h>
22#include <brcmu_utils.h>
23#include "pub.h"
24#include "aiutils.h"
25#include "pmu.h"
26
27/*
28 * external LPO crystal frequency
29 */
30#define EXT_ILP_HZ 32768
31
32/*
33 * Duration for ILP clock frequency measurment in milliseconds
34 *
35 * remark: 1000 must be an integer multiple of this duration
36 */
37#define ILP_CALC_DUR 10
38
39/* Fields in pmucontrol */
40#define PCTL_ILP_DIV_MASK 0xffff0000
41#define PCTL_ILP_DIV_SHIFT 16
42#define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
43#define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
44#define PCTL_HT_REQ_EN 0x00000100
45#define PCTL_ALP_REQ_EN 0x00000080
46#define PCTL_XTALFREQ_MASK 0x0000007c
47#define PCTL_XTALFREQ_SHIFT 2
48#define PCTL_ILP_DIV_EN 0x00000002
49#define PCTL_LPO_SEL 0x00000001
50
51/* ILP clock */
52#define ILP_CLOCK 32000
53
54/* ALP clock on pre-PMU chips */
55#define ALP_CLOCK 20000000
56
57/* pmustatus */
58#define PST_EXTLPOAVAIL 0x0100
59#define PST_WDRESET 0x0080
60#define PST_INTPEND 0x0040
61#define PST_SBCLKST 0x0030
62#define PST_SBCLKST_ILP 0x0010
63#define PST_SBCLKST_ALP 0x0020
64#define PST_SBCLKST_HT 0x0030
65#define PST_ALPAVAIL 0x0008
66#define PST_HTAVAIL 0x0004
67#define PST_RESINIT 0x0003
68
69/* PMU resource bit position */
70#define PMURES_BIT(bit) (1 << (bit))
71
72/* PMU corerev and chip specific PLL controls.
73 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
74 * number to differentiate different PLLs controlled by the same PMU rev.
75 */
76/* pllcontrol registers:
77 * ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>,
78 * p1div, p2div, _bypass_sdmod
79 */
80#define PMU1_PLL0_PLLCTL0 0
81#define PMU1_PLL0_PLLCTL1 1
82#define PMU1_PLL0_PLLCTL2 2
83#define PMU1_PLL0_PLLCTL3 3
84#define PMU1_PLL0_PLLCTL4 4
85#define PMU1_PLL0_PLLCTL5 5
86
87/* pmu XtalFreqRatio */
88#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
89#define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
90#define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
91
92/* 4313 resources */
93#define RES4313_BB_PU_RSRC 0
94#define RES4313_ILP_REQ_RSRC 1
95#define RES4313_XTAL_PU_RSRC 2
96#define RES4313_ALP_AVAIL_RSRC 3
97#define RES4313_RADIO_PU_RSRC 4
98#define RES4313_BG_PU_RSRC 5
99#define RES4313_VREG1P4_PU_RSRC 6
100#define RES4313_AFE_PWRSW_RSRC 7
101#define RES4313_RX_PWRSW_RSRC 8
102#define RES4313_TX_PWRSW_RSRC 9
103#define RES4313_BB_PWRSW_RSRC 10
104#define RES4313_SYNTH_PWRSW_RSRC 11
105#define RES4313_MISC_PWRSW_RSRC 12
106#define RES4313_BB_PLL_PWRSW_RSRC 13
107#define RES4313_HT_AVAIL_RSRC 14
108#define RES4313_MACPHY_CLK_AVAIL_RSRC 15
109
110/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
111static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
112{
113 u32 min_mask = 0, max_mask = 0;
114 uint rsrcs;
115
116 /* # resources */
117 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
118
119 /* determine min/max rsrc masks */
120 switch (sih->chip) {
121 case BCM43224_CHIP_ID:
122 case BCM43225_CHIP_ID:
123 /* ??? */
124 break;
125
126 case BCM4313_CHIP_ID:
127 min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
128 PMURES_BIT(RES4313_XTAL_PU_RSRC) |
129 PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
130 PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
131 max_mask = 0xffff;
132 break;
133 default:
134 break;
135 }
136
137 *pmin = min_mask;
138 *pmax = max_mask;
139}
140
141static void
142si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs __iomem *cc,
143 u8 spuravoid)
144{
145 u32 tmp = 0;
146
147 switch (sih->chip) {
148 case BCM43224_CHIP_ID:
149 case BCM43225_CHIP_ID:
150 if (spuravoid == 1) {
151 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
152 W_REG(&cc->pllcontrol_data, 0x11500010);
153 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
154 W_REG(&cc->pllcontrol_data, 0x000C0C06);
155 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
156 W_REG(&cc->pllcontrol_data, 0x0F600a08);
157 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
158 W_REG(&cc->pllcontrol_data, 0x00000000);
159 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
160 W_REG(&cc->pllcontrol_data, 0x2001E920);
161 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
162 W_REG(&cc->pllcontrol_data, 0x88888815);
163 } else {
164 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
165 W_REG(&cc->pllcontrol_data, 0x11100010);
166 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
167 W_REG(&cc->pllcontrol_data, 0x000c0c06);
168 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
169 W_REG(&cc->pllcontrol_data, 0x03000a08);
170 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
171 W_REG(&cc->pllcontrol_data, 0x00000000);
172 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
173 W_REG(&cc->pllcontrol_data, 0x200005c0);
174 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
175 W_REG(&cc->pllcontrol_data, 0x88888815);
176 }
177 tmp = 1 << 10;
178 break;
179
180 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
181 W_REG(&cc->pllcontrol_data, 0x11100008);
182 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
183 W_REG(&cc->pllcontrol_data, 0x0c000c06);
184 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
185 W_REG(&cc->pllcontrol_data, 0x03000a08);
186 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
187 W_REG(&cc->pllcontrol_data, 0x00000000);
188 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
189 W_REG(&cc->pllcontrol_data, 0x200005c0);
190 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
191 W_REG(&cc->pllcontrol_data, 0x88888855);
192
193 tmp = 1 << 10;
194 break;
195
196 default:
197 /* bail out */
198 return;
199 }
200
201 tmp |= R_REG(&cc->pmucontrol);
202 W_REG(&cc->pmucontrol, tmp);
203}
204
205u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
206{
207 uint delay = PMU_MAX_TRANSITION_DLY;
208
209 switch (sih->chip) {
210 case BCM43224_CHIP_ID:
211 case BCM43225_CHIP_ID:
212 case BCM4313_CHIP_ID:
213 delay = 3700;
214 break;
215 default:
216 break;
217 }
218
219 return (u16) delay;
220}
221
222void si_pmu_sprom_enable(struct si_pub *sih, bool enable)
223{
224 struct chipcregs __iomem *cc;
225 uint origidx;
226
227 /* Remember original core before switch to chipc */
228 origidx = ai_coreidx(sih);
229 cc = ai_setcoreidx(sih, SI_CC_IDX);
230
231 /* Return to original core */
232 ai_setcoreidx(sih, origidx);
233}
234
235/* Read/write a chipcontrol reg */
236u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
237{
238 ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, chipcontrol_addr),
239 ~0, reg);
240 return ai_corereg(sih, SI_CC_IDX,
241 offsetof(struct chipcregs, chipcontrol_data), mask,
242 val);
243}
244
245/* Read/write a regcontrol reg */
246u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
247{
248 ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, regcontrol_addr),
249 ~0, reg);
250 return ai_corereg(sih, SI_CC_IDX,
251 offsetof(struct chipcregs, regcontrol_data), mask,
252 val);
253}
254
255/* Read/write a pllcontrol reg */
256u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
257{
258 ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, pllcontrol_addr),
259 ~0, reg);
260 return ai_corereg(sih, SI_CC_IDX,
261 offsetof(struct chipcregs, pllcontrol_data), mask,
262 val);
263}
264
265/* PMU PLL update */
266void si_pmu_pllupd(struct si_pub *sih)
267{
268 ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, pmucontrol),
269 PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
270}
271
272/* query alp/xtal clock frequency */
273u32 si_pmu_alp_clock(struct si_pub *sih)
274{
275 u32 clock = ALP_CLOCK;
276
277 /* bail out with default */
278 if (!(sih->cccaps & CC_CAP_PMU))
279 return clock;
280
281 switch (sih->chip) {
282 case BCM43224_CHIP_ID:
283 case BCM43225_CHIP_ID:
284 case BCM4313_CHIP_ID:
285 /* always 20Mhz */
286 clock = 20000 * 1000;
287 break;
288 default:
289 break;
290 }
291
292 return clock;
293}
294
295void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
296{
297 struct chipcregs __iomem *cc;
298 uint origidx, intr_val;
299
300 /* Remember original core before switch to chipc */
301 cc = (struct chipcregs __iomem *)
302 ai_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
303
304 /* update the pll changes */
305 si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);
306
307 /* Return to original core */
308 ai_restore_core(sih, origidx, intr_val);
309}
310
311/* initialize PMU */
312void si_pmu_init(struct si_pub *sih)
313{
314 struct chipcregs __iomem *cc;
315 uint origidx;
316
317 /* Remember original core before switch to chipc */
318 origidx = ai_coreidx(sih);
319 cc = ai_setcoreidx(sih, SI_CC_IDX);
320
321 if (sih->pmurev == 1)
322 AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
323 else if (sih->pmurev >= 2)
324 OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT);
325
326 /* Return to original core */
327 ai_setcoreidx(sih, origidx);
328}
329
330/* initialize PMU chip controls and other chip level stuff */
331void si_pmu_chip_init(struct si_pub *sih)
332{
333 uint origidx;
334
335 /* Gate off SPROM clock and chip select signals */
336 si_pmu_sprom_enable(sih, false);
337
338 /* Remember original core */
339 origidx = ai_coreidx(sih);
340
341 /* Return to original core */
342 ai_setcoreidx(sih, origidx);
343}
344
345/* initialize PMU switch/regulators */
346void si_pmu_swreg_init(struct si_pub *sih)
347{
348}
349
350/* initialize PLL */
351void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
352{
353 struct chipcregs __iomem *cc;
354 uint origidx;
355
356 /* Remember original core before switch to chipc */
357 origidx = ai_coreidx(sih);
358 cc = ai_setcoreidx(sih, SI_CC_IDX);
359
360 switch (sih->chip) {
361 case BCM4313_CHIP_ID:
362 case BCM43224_CHIP_ID:
363 case BCM43225_CHIP_ID:
364 /* ??? */
365 break;
366 default:
367 break;
368 }
369
370 /* Return to original core */
371 ai_setcoreidx(sih, origidx);
372}
373
374/* initialize PMU resources */
375void si_pmu_res_init(struct si_pub *sih)
376{
377 struct chipcregs __iomem *cc;
378 uint origidx;
379 u32 min_mask = 0, max_mask = 0;
380
381 /* Remember original core before switch to chipc */
382 origidx = ai_coreidx(sih);
383 cc = ai_setcoreidx(sih, SI_CC_IDX);
384
385 /* Determine min/max rsrc masks */
386 si_pmu_res_masks(sih, &min_mask, &max_mask);
387
388 /* It is required to program max_mask first and then min_mask */
389
390 /* Program max resource mask */
391
392 if (max_mask)
393 W_REG(&cc->max_res_mask, max_mask);
394
395 /* Program min resource mask */
396
397 if (min_mask)
398 W_REG(&cc->min_res_mask, min_mask);
399
400 /* Add some delay; allow resources to come up and settle. */
401 mdelay(2);
402
403 /* Return to original core */
404 ai_setcoreidx(sih, origidx);
405}
406
407u32 si_pmu_measure_alpclk(struct si_pub *sih)
408{
409 struct chipcregs __iomem *cc;
410 uint origidx;
411 u32 alp_khz;
412
413 if (sih->pmurev < 10)
414 return 0;
415
416 /* Remember original core before switch to chipc */
417 origidx = ai_coreidx(sih);
418 cc = ai_setcoreidx(sih, SI_CC_IDX);
419
420 if (R_REG(&cc->pmustatus) & PST_EXTLPOAVAIL) {
421 u32 ilp_ctr, alp_hz;
422
423 /*
424 * Enable the reg to measure the freq,
425 * in case it was disabled before
426 */
427 W_REG(&cc->pmu_xtalfreq,
428 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
429
430 /* Delay for well over 4 ILP clocks */
431 udelay(1000);
432
433 /* Read the latched number of ALP ticks per 4 ILP ticks */
434 ilp_ctr =
435 R_REG(&cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
436
437 /*
438 * Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
439 * bit to save power
440 */
441 W_REG(&cc->pmu_xtalfreq, 0);
442
443 /* Calculate ALP frequency */
444 alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
445
446 /*
447 * Round to nearest 100KHz, and at
448 * the same time convert to KHz
449 */
450 alp_khz = (alp_hz + 50000) / 100000 * 100;
451 } else
452 alp_khz = 0;
453
454 /* Return to original core */
455 ai_setcoreidx(sih, origidx);
456
457 return alp_khz;
458}
diff --git a/drivers/staging/brcm80211/brcmsmac/pmu.h b/drivers/staging/brcm80211/brcmsmac/pmu.h
deleted file mode 100644
index 3a08c620640..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/pmu.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18#ifndef _BRCM_PMU_H_
19#define _BRCM_PMU_H_
20
21#include "types.h"
22
23extern u16 si_pmu_fast_pwrup_delay(struct si_pub *sih);
24extern void si_pmu_sprom_enable(struct si_pub *sih, bool enable);
25extern u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
26extern u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
27extern u32 si_pmu_alp_clock(struct si_pub *sih);
28extern void si_pmu_pllupd(struct si_pub *sih);
29extern void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid);
30extern u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
31extern void si_pmu_init(struct si_pub *sih);
32extern void si_pmu_chip_init(struct si_pub *sih);
33extern void si_pmu_pll_init(struct si_pub *sih, u32 xtalfreq);
34extern void si_pmu_res_init(struct si_pub *sih);
35extern void si_pmu_swreg_init(struct si_pub *sih);
36extern u32 si_pmu_measure_alpclk(struct si_pub *sih);
37
38#endif /* _BRCM_PMU_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/pub.h b/drivers/staging/brcm80211/brcmsmac/pub.h
deleted file mode 100644
index 3942f47b15c..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/pub.h
+++ /dev/null
@@ -1,655 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_PUB_H_
18#define _BRCM_PUB_H_
19
20#include <brcmu_wifi.h>
21#include "types.h"
22#include "defs.h"
23
24enum brcms_srom_id {
25 BRCMS_SROM_NULL,
26 BRCMS_SROM_CONT,
27 BRCMS_SROM_AA2G,
28 BRCMS_SROM_AA5G,
29 BRCMS_SROM_AG0,
30 BRCMS_SROM_AG1,
31 BRCMS_SROM_AG2,
32 BRCMS_SROM_AG3,
33 BRCMS_SROM_ANTSWCTL2G,
34 BRCMS_SROM_ANTSWCTL5G,
35 BRCMS_SROM_ANTSWITCH,
36 BRCMS_SROM_BOARDFLAGS2,
37 BRCMS_SROM_BOARDFLAGS,
38 BRCMS_SROM_BOARDNUM,
39 BRCMS_SROM_BOARDREV,
40 BRCMS_SROM_BOARDTYPE,
41 BRCMS_SROM_BW40PO,
42 BRCMS_SROM_BWDUPPO,
43 BRCMS_SROM_BXA2G,
44 BRCMS_SROM_BXA5G,
45 BRCMS_SROM_CC,
46 BRCMS_SROM_CCK2GPO,
47 BRCMS_SROM_CCKBW202GPO,
48 BRCMS_SROM_CCKBW20UL2GPO,
49 BRCMS_SROM_CCODE,
50 BRCMS_SROM_CDDPO,
51 BRCMS_SROM_DEVID,
52 BRCMS_SROM_ET1MACADDR,
53 BRCMS_SROM_EXTPAGAIN2G,
54 BRCMS_SROM_EXTPAGAIN5G,
55 BRCMS_SROM_FREQOFFSET_CORR,
56 BRCMS_SROM_HW_IQCAL_EN,
57 BRCMS_SROM_IL0MACADDR,
58 BRCMS_SROM_IQCAL_SWP_DIS,
59 BRCMS_SROM_LEDBH0,
60 BRCMS_SROM_LEDBH1,
61 BRCMS_SROM_LEDBH2,
62 BRCMS_SROM_LEDBH3,
63 BRCMS_SROM_LEDDC,
64 BRCMS_SROM_LEGOFDM40DUPPO,
65 BRCMS_SROM_LEGOFDMBW202GPO,
66 BRCMS_SROM_LEGOFDMBW205GHPO,
67 BRCMS_SROM_LEGOFDMBW205GLPO,
68 BRCMS_SROM_LEGOFDMBW205GMPO,
69 BRCMS_SROM_LEGOFDMBW20UL2GPO,
70 BRCMS_SROM_LEGOFDMBW20UL5GHPO,
71 BRCMS_SROM_LEGOFDMBW20UL5GLPO,
72 BRCMS_SROM_LEGOFDMBW20UL5GMPO,
73 BRCMS_SROM_MACADDR,
74 BRCMS_SROM_MCS2GPO0,
75 BRCMS_SROM_MCS2GPO1,
76 BRCMS_SROM_MCS2GPO2,
77 BRCMS_SROM_MCS2GPO3,
78 BRCMS_SROM_MCS2GPO4,
79 BRCMS_SROM_MCS2GPO5,
80 BRCMS_SROM_MCS2GPO6,
81 BRCMS_SROM_MCS2GPO7,
82 BRCMS_SROM_MCS32PO,
83 BRCMS_SROM_MCS5GHPO0,
84 BRCMS_SROM_MCS5GHPO1,
85 BRCMS_SROM_MCS5GHPO2,
86 BRCMS_SROM_MCS5GHPO3,
87 BRCMS_SROM_MCS5GHPO4,
88 BRCMS_SROM_MCS5GHPO5,
89 BRCMS_SROM_MCS5GHPO6,
90 BRCMS_SROM_MCS5GHPO7,
91 BRCMS_SROM_MCS5GLPO0,
92 BRCMS_SROM_MCS5GLPO1,
93 BRCMS_SROM_MCS5GLPO2,
94 BRCMS_SROM_MCS5GLPO3,
95 BRCMS_SROM_MCS5GLPO4,
96 BRCMS_SROM_MCS5GLPO5,
97 BRCMS_SROM_MCS5GLPO6,
98 BRCMS_SROM_MCS5GLPO7,
99 BRCMS_SROM_MCS5GPO0,
100 BRCMS_SROM_MCS5GPO1,
101 BRCMS_SROM_MCS5GPO2,
102 BRCMS_SROM_MCS5GPO3,
103 BRCMS_SROM_MCS5GPO4,
104 BRCMS_SROM_MCS5GPO5,
105 BRCMS_SROM_MCS5GPO6,
106 BRCMS_SROM_MCS5GPO7,
107 BRCMS_SROM_MCSBW202GPO,
108 BRCMS_SROM_MCSBW205GHPO,
109 BRCMS_SROM_MCSBW205GLPO,
110 BRCMS_SROM_MCSBW205GMPO,
111 BRCMS_SROM_MCSBW20UL2GPO,
112 BRCMS_SROM_MCSBW20UL5GHPO,
113 BRCMS_SROM_MCSBW20UL5GLPO,
114 BRCMS_SROM_MCSBW20UL5GMPO,
115 BRCMS_SROM_MCSBW402GPO,
116 BRCMS_SROM_MCSBW405GHPO,
117 BRCMS_SROM_MCSBW405GLPO,
118 BRCMS_SROM_MCSBW405GMPO,
119 BRCMS_SROM_MEASPOWER,
120 BRCMS_SROM_OFDM2GPO,
121 BRCMS_SROM_OFDM5GHPO,
122 BRCMS_SROM_OFDM5GLPO,
123 BRCMS_SROM_OFDM5GPO,
124 BRCMS_SROM_OPO,
125 BRCMS_SROM_PA0B0,
126 BRCMS_SROM_PA0B1,
127 BRCMS_SROM_PA0B2,
128 BRCMS_SROM_PA0ITSSIT,
129 BRCMS_SROM_PA0MAXPWR,
130 BRCMS_SROM_PA1B0,
131 BRCMS_SROM_PA1B1,
132 BRCMS_SROM_PA1B2,
133 BRCMS_SROM_PA1HIB0,
134 BRCMS_SROM_PA1HIB1,
135 BRCMS_SROM_PA1HIB2,
136 BRCMS_SROM_PA1HIMAXPWR,
137 BRCMS_SROM_PA1ITSSIT,
138 BRCMS_SROM_PA1LOB0,
139 BRCMS_SROM_PA1LOB1,
140 BRCMS_SROM_PA1LOB2,
141 BRCMS_SROM_PA1LOMAXPWR,
142 BRCMS_SROM_PA1MAXPWR,
143 BRCMS_SROM_PDETRANGE2G,
144 BRCMS_SROM_PDETRANGE5G,
145 BRCMS_SROM_PHYCAL_TEMPDELTA,
146 BRCMS_SROM_RAWTEMPSENSE,
147 BRCMS_SROM_REGREV,
148 BRCMS_SROM_REV,
149 BRCMS_SROM_RSSISAV2G,
150 BRCMS_SROM_RSSISAV5G,
151 BRCMS_SROM_RSSISMC2G,
152 BRCMS_SROM_RSSISMC5G,
153 BRCMS_SROM_RSSISMF2G,
154 BRCMS_SROM_RSSISMF5G,
155 BRCMS_SROM_RXCHAIN,
156 BRCMS_SROM_RXPO2G,
157 BRCMS_SROM_RXPO5G,
158 BRCMS_SROM_STBCPO,
159 BRCMS_SROM_TEMPCORRX,
160 BRCMS_SROM_TEMPOFFSET,
161 BRCMS_SROM_TEMPSENSE_OPTION,
162 BRCMS_SROM_TEMPSENSE_SLOPE,
163 BRCMS_SROM_TEMPTHRESH,
164 BRCMS_SROM_TRI2G,
165 BRCMS_SROM_TRI5GH,
166 BRCMS_SROM_TRI5GL,
167 BRCMS_SROM_TRI5G,
168 BRCMS_SROM_TRISO2G,
169 BRCMS_SROM_TRISO5G,
170 BRCMS_SROM_TSSIPOS2G,
171 BRCMS_SROM_TSSIPOS5G,
172 BRCMS_SROM_TXCHAIN,
173 BRCMS_SROM_TXPID2GA0,
174 BRCMS_SROM_TXPID2GA1,
175 BRCMS_SROM_TXPID2GA2,
176 BRCMS_SROM_TXPID2GA3,
177 BRCMS_SROM_TXPID5GA0,
178 BRCMS_SROM_TXPID5GA1,
179 BRCMS_SROM_TXPID5GA2,
180 BRCMS_SROM_TXPID5GA3,
181 BRCMS_SROM_TXPID5GHA0,
182 BRCMS_SROM_TXPID5GHA1,
183 BRCMS_SROM_TXPID5GHA2,
184 BRCMS_SROM_TXPID5GHA3,
185 BRCMS_SROM_TXPID5GLA0,
186 BRCMS_SROM_TXPID5GLA1,
187 BRCMS_SROM_TXPID5GLA2,
188 BRCMS_SROM_TXPID5GLA3,
189 /*
190 * per-path identifiers (see srom.c)
191 */
192 BRCMS_SROM_ITT2GA0,
193 BRCMS_SROM_ITT2GA1,
194 BRCMS_SROM_ITT2GA2,
195 BRCMS_SROM_ITT2GA3,
196 BRCMS_SROM_ITT5GA0,
197 BRCMS_SROM_ITT5GA1,
198 BRCMS_SROM_ITT5GA2,
199 BRCMS_SROM_ITT5GA3,
200 BRCMS_SROM_MAXP2GA0,
201 BRCMS_SROM_MAXP2GA1,
202 BRCMS_SROM_MAXP2GA2,
203 BRCMS_SROM_MAXP2GA3,
204 BRCMS_SROM_MAXP5GA0,
205 BRCMS_SROM_MAXP5GA1,
206 BRCMS_SROM_MAXP5GA2,
207 BRCMS_SROM_MAXP5GA3,
208 BRCMS_SROM_MAXP5GHA0,
209 BRCMS_SROM_MAXP5GHA1,
210 BRCMS_SROM_MAXP5GHA2,
211 BRCMS_SROM_MAXP5GHA3,
212 BRCMS_SROM_MAXP5GLA0,
213 BRCMS_SROM_MAXP5GLA1,
214 BRCMS_SROM_MAXP5GLA2,
215 BRCMS_SROM_MAXP5GLA3,
216 BRCMS_SROM_PA2GW0A0,
217 BRCMS_SROM_PA2GW0A1,
218 BRCMS_SROM_PA2GW0A2,
219 BRCMS_SROM_PA2GW0A3,
220 BRCMS_SROM_PA2GW1A0,
221 BRCMS_SROM_PA2GW1A1,
222 BRCMS_SROM_PA2GW1A2,
223 BRCMS_SROM_PA2GW1A3,
224 BRCMS_SROM_PA2GW2A0,
225 BRCMS_SROM_PA2GW2A1,
226 BRCMS_SROM_PA2GW2A2,
227 BRCMS_SROM_PA2GW2A3,
228 BRCMS_SROM_PA2GW3A0,
229 BRCMS_SROM_PA2GW3A1,
230 BRCMS_SROM_PA2GW3A2,
231 BRCMS_SROM_PA2GW3A3,
232 BRCMS_SROM_PA5GHW0A0,
233 BRCMS_SROM_PA5GHW0A1,
234 BRCMS_SROM_PA5GHW0A2,
235 BRCMS_SROM_PA5GHW0A3,
236 BRCMS_SROM_PA5GHW1A0,
237 BRCMS_SROM_PA5GHW1A1,
238 BRCMS_SROM_PA5GHW1A2,
239 BRCMS_SROM_PA5GHW1A3,
240 BRCMS_SROM_PA5GHW2A0,
241 BRCMS_SROM_PA5GHW2A1,
242 BRCMS_SROM_PA5GHW2A2,
243 BRCMS_SROM_PA5GHW2A3,
244 BRCMS_SROM_PA5GHW3A0,
245 BRCMS_SROM_PA5GHW3A1,
246 BRCMS_SROM_PA5GHW3A2,
247 BRCMS_SROM_PA5GHW3A3,
248 BRCMS_SROM_PA5GLW0A0,
249 BRCMS_SROM_PA5GLW0A1,
250 BRCMS_SROM_PA5GLW0A2,
251 BRCMS_SROM_PA5GLW0A3,
252 BRCMS_SROM_PA5GLW1A0,
253 BRCMS_SROM_PA5GLW1A1,
254 BRCMS_SROM_PA5GLW1A2,
255 BRCMS_SROM_PA5GLW1A3,
256 BRCMS_SROM_PA5GLW2A0,
257 BRCMS_SROM_PA5GLW2A1,
258 BRCMS_SROM_PA5GLW2A2,
259 BRCMS_SROM_PA5GLW2A3,
260 BRCMS_SROM_PA5GLW3A0,
261 BRCMS_SROM_PA5GLW3A1,
262 BRCMS_SROM_PA5GLW3A2,
263 BRCMS_SROM_PA5GLW3A3,
264 BRCMS_SROM_PA5GW0A0,
265 BRCMS_SROM_PA5GW0A1,
266 BRCMS_SROM_PA5GW0A2,
267 BRCMS_SROM_PA5GW0A3,
268 BRCMS_SROM_PA5GW1A0,
269 BRCMS_SROM_PA5GW1A1,
270 BRCMS_SROM_PA5GW1A2,
271 BRCMS_SROM_PA5GW1A3,
272 BRCMS_SROM_PA5GW2A0,
273 BRCMS_SROM_PA5GW2A1,
274 BRCMS_SROM_PA5GW2A2,
275 BRCMS_SROM_PA5GW2A3,
276 BRCMS_SROM_PA5GW3A0,
277 BRCMS_SROM_PA5GW3A1,
278 BRCMS_SROM_PA5GW3A2,
279 BRCMS_SROM_PA5GW3A3,
280};
281
282#define BRCMS_NUMRATES 16 /* max # of rates in a rateset */
283#define D11_PHY_HDR_LEN 6 /* Phy header length - 6 bytes */
284
285/* phy types */
286#define PHY_TYPE_A 0 /* Phy type A */
287#define PHY_TYPE_G 2 /* Phy type G */
288#define PHY_TYPE_N 4 /* Phy type N */
289#define PHY_TYPE_LP 5 /* Phy type Low Power A/B/G */
290#define PHY_TYPE_SSN 6 /* Phy type Single Stream N */
291#define PHY_TYPE_LCN 8 /* Phy type Single Stream N */
292#define PHY_TYPE_LCNXN 9 /* Phy type 2-stream N */
293#define PHY_TYPE_HT 7 /* Phy type 3-Stream N */
294
295/* bw */
296#define BRCMS_10_MHZ 10 /* 10Mhz nphy channel bandwidth */
297#define BRCMS_20_MHZ 20 /* 20Mhz nphy channel bandwidth */
298#define BRCMS_40_MHZ 40 /* 40Mhz nphy channel bandwidth */
299
300#define BRCMS_RSSI_MINVAL -200 /* Low value, e.g. for forcing roam */
301#define BRCMS_RSSI_NO_SIGNAL -91 /* NDIS RSSI link quality cutoffs */
302#define BRCMS_RSSI_VERY_LOW -80 /* Very low quality cutoffs */
303#define BRCMS_RSSI_LOW -70 /* Low quality cutoffs */
304#define BRCMS_RSSI_GOOD -68 /* Good quality cutoffs */
305#define BRCMS_RSSI_VERY_GOOD -58 /* Very good quality cutoffs */
306#define BRCMS_RSSI_EXCELLENT -57 /* Excellent quality cutoffs */
307
308/* a large TX Power as an init value to factor out of min() calculations,
309 * keep low enough to fit in an s8, units are .25 dBm
310 */
311#define BRCMS_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */
312
313/* rate related definitions */
314#define BRCMS_RATE_FLAG 0x80 /* Flag to indicate it is a basic rate */
315#define BRCMS_RATE_MASK 0x7f /* Rate value mask w/o basic rate flag */
316
317/* legacy rx Antenna diversity for SISO rates */
318#define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */
319#define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
320#define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
321#define ANT_RX_DIV_START_0 3 /* Choose starting with 0 */
322#define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */
323/* default antdiv setting */
324#define ANT_RX_DIV_DEF ANT_RX_DIV_START_0
325
326/* legacy rx Antenna diversity for SISO rates */
327/* Tx on antenna 0, "legacy term Main" */
328#define ANT_TX_FORCE_0 0
329/* Tx on antenna 1, "legacy term Aux" */
330#define ANT_TX_FORCE_1 1
331/* Tx on phy's last good Rx antenna */
332#define ANT_TX_LAST_RX 3
333/* driver's default tx antenna setting */
334#define ANT_TX_DEF 3
335
336/* Tx Chain values */
337/* def bitmap of txchain */
338#define TXCHAIN_DEF 0x1
339/* default bitmap of tx chains for nphy */
340#define TXCHAIN_DEF_NPHY 0x3
341/* default bitmap of tx chains for nphy */
342#define TXCHAIN_DEF_HTPHY 0x7
343/* def bitmap of rxchain */
344#define RXCHAIN_DEF 0x1
345/* default bitmap of rx chains for nphy */
346#define RXCHAIN_DEF_NPHY 0x3
347/* default bitmap of rx chains for nphy */
348#define RXCHAIN_DEF_HTPHY 0x7
349/* no antenna switch */
350#define ANTSWITCH_NONE 0
351/* antenna switch on 4321CB2, 2of3 */
352#define ANTSWITCH_TYPE_1 1
353/* antenna switch on 4321MPCI, 2of3 */
354#define ANTSWITCH_TYPE_2 2
355/* antenna switch on 4322, 2of3 */
356#define ANTSWITCH_TYPE_3 3
357
358#define RXBUFSZ PKTBUFSZ
359
360#define MAX_STREAMS_SUPPORTED 4 /* max number of streams supported */
361
362struct brcm_rateset {
363 /* # rates in this set */
364 u32 count;
365 /* rates in 500kbps units w/hi bit set if basic */
366 u8 rates[WL_NUMRATES];
367};
368
369struct brcms_c_rateset {
370 uint count; /* number of rates in rates[] */
371 /* rates in 500kbps units w/hi bit set if basic */
372 u8 rates[BRCMS_NUMRATES];
373 u8 htphy_membership; /* HT PHY Membership */
374 u8 mcs[MCSSET_LEN]; /* supported mcs index bit map */
375};
376
377/* All the HT-specific default advertised capabilities (including AMPDU)
378 * should be grouped here at one place
379 */
380#define AMPDU_DEF_MPDU_DENSITY 6 /* default mpdu density (110 ==> 4us) */
381
382/* wlc internal bss_info */
383struct brcms_bss_info {
384 u8 BSSID[ETH_ALEN]; /* network BSSID */
385 u16 flags; /* flags for internal attributes */
386 u8 SSID_len; /* the length of SSID */
387 u8 SSID[32]; /* SSID string */
388 s16 RSSI; /* receive signal strength (in dBm) */
389 s16 SNR; /* receive signal SNR in dB */
390 u16 beacon_period; /* units are Kusec */
391 u16 chanspec; /* Channel num, bw, ctrl_sb and band */
392 struct brcms_c_rateset rateset; /* supported rates */
393};
394
395#define MAC80211_PROMISC_BCNS (1 << 0)
396#define MAC80211_SCAN (1 << 1)
397
398/*
399 * Public portion of common driver state structure.
400 * The wlc handle points at this.
401 */
402struct brcms_pub {
403 struct brcms_c_info *wlc;
404 struct ieee80211_hw *ieee_hw;
405 struct scb_ampdu *global_ampdu;
406 uint mac80211_state;
407 uint unit; /* device instance number */
408 uint corerev; /* core revision */
409 struct si_pub *sih; /* SI handle (cookie for siutils calls) */
410 bool up; /* interface up and running */
411 bool hw_off; /* HW is off */
412 bool hw_up; /* one time hw up/down */
413 bool _piomode; /* true if pio mode */
414 uint _nbands; /* # bands supported */
415 uint now; /* # elapsed seconds */
416
417 bool promisc; /* promiscuous destination address */
418 bool delayed_down; /* down delayed */
419 bool associated; /* true:part of [I]BSS, false: not */
420 /* (union of stas_associated, aps_associated) */
421 bool _ampdu; /* ampdu enabled or not */
422 u8 _n_enab; /* bitmap of 11N + HT support */
423
424 u8 cur_etheraddr[ETH_ALEN]; /* our local ethernet address */
425
426 int bcmerror; /* last bcm error */
427
428 u32 radio_disabled; /* bit vector for radio disabled reasons */
429
430 u16 boardrev; /* version # of particular board */
431 u8 sromrev; /* version # of the srom */
432 char srom_ccode[BRCM_CNTRY_BUF_SZ]; /* Country Code in SROM */
433 u32 boardflags; /* Board specific flags from srom */
434 u32 boardflags2; /* More board flags if sromrev >= 4 */
435 bool phy_11ncapable; /* the PHY/HW is capable of 802.11N */
436
437 struct wl_cnt *_cnt; /* low-level counters in driver */
438};
439
440enum wlc_par_id {
441 IOV_MPC = 1,
442 IOV_RTSTHRESH,
443 IOV_QTXPOWER,
444 IOV_BCN_LI_BCN /* Beacon listen interval in # of beacons */
445};
446
447/***********************************************
448 * Feature-related macros to optimize out code *
449 * *********************************************
450 */
451
452#define ENAB_1x1 0x01
453#define ENAB_2x2 0x02
454#define ENAB_3x3 0x04
455#define ENAB_4x4 0x08
456#define SUPPORT_11N (ENAB_1x1|ENAB_2x2)
457#define SUPPORT_HT (ENAB_1x1|ENAB_2x2|ENAB_3x3)
458
459/* WL11N Support */
460#define AMPDU_AGG_HOST 1
461
462/* pri is priority encoded in the packet. This maps the Packet priority to
463 * enqueue precedence as defined in wlc_prec_map
464 */
465extern const u8 wlc_prio2prec_map[];
466#define BRCMS_PRIO_TO_PREC(pri) wlc_prio2prec_map[(pri) & 7]
467
468#define BRCMS_PREC_COUNT 16 /* Max precedence level implemented */
469
470/* Mask to describe all precedence levels */
471#define BRCMS_PREC_BMP_ALL MAXBITVAL(BRCMS_PREC_COUNT)
472
473/*
474 * This maps priority to one precedence higher - Used by PS-Poll response
475 * packets to simulate enqueue-at-head operation, but still maintain the
476 * order on the queue
477 */
478#define BRCMS_PRIO_TO_HI_PREC(pri) min(BRCMS_PRIO_TO_PREC(pri) + 1,\
479 BRCMS_PREC_COUNT - 1)
480
481/* Define a bitmap of precedences comprised by each AC */
482#define BRCMS_PREC_BMP_AC_BE (NBITVAL(BRCMS_PRIO_TO_PREC(PRIO_8021D_BE)) | \
483 NBITVAL(BRCMS_PRIO_TO_HI_PREC(PRIO_8021D_BE)) | \
484 NBITVAL(BRCMS_PRIO_TO_PREC(PRIO_8021D_EE)) | \
485 NBITVAL(BRCMS_PRIO_TO_HI_PREC(PRIO_8021D_EE)))
486#define BRCMS_PREC_BMP_AC_BK (NBITVAL(BRCMS_PRIO_TO_PREC(PRIO_8021D_BK)) | \
487 NBITVAL(BRCMS_PRIO_TO_HI_PREC(PRIO_8021D_BK)) | \
488 NBITVAL(BRCMS_PRIO_TO_PREC(PRIO_8021D_NONE)) | \
489 NBITVAL(BRCMS_PRIO_TO_HI_PREC(PRIO_8021D_NONE)))
490#define BRCMS_PREC_BMP_AC_VI (NBITVAL(BRCMS_PRIO_TO_PREC(PRIO_8021D_CL)) | \
491 NBITVAL(BRCMS_PRIO_TO_HI_PREC(PRIO_8021D_CL)) | \
492 NBITVAL(BRCMS_PRIO_TO_PREC(PRIO_8021D_VI)) | \
493 NBITVAL(BRCMS_PRIO_TO_HI_PREC(PRIO_8021D_VI)))
494#define BRCMS_PREC_BMP_AC_VO (NBITVAL(BRCMS_PRIO_TO_PREC(PRIO_8021D_VO)) | \
495 NBITVAL(BRCMS_PRIO_TO_HI_PREC(PRIO_8021D_VO)) | \
496 NBITVAL(BRCMS_PRIO_TO_PREC(PRIO_8021D_NC)) | \
497 NBITVAL(BRCMS_PRIO_TO_HI_PREC(PRIO_8021D_NC)))
498
499/* network protection config */
500#define BRCMS_PROT_G_SPEC 1 /* SPEC g protection */
501#define BRCMS_PROT_G_OVR 2 /* SPEC g prot override */
502#define BRCMS_PROT_G_USER 3 /* gmode specified by user */
503#define BRCMS_PROT_OVERLAP 4 /* overlap */
504#define BRCMS_PROT_N_USER 10 /* nmode specified by user */
505#define BRCMS_PROT_N_CFG 11 /* n protection */
506#define BRCMS_PROT_N_CFG_OVR 12 /* n protection override */
507#define BRCMS_PROT_N_NONGF 13 /* non-GF protection */
508#define BRCMS_PROT_N_NONGF_OVR 14 /* non-GF protection override */
509#define BRCMS_PROT_N_PAM_OVR 15 /* n preamble override */
510#define BRCMS_PROT_N_OBSS 16 /* non-HT OBSS present */
511
512/*
513 * 54g modes (basic bits may still be overridden)
514 *
515 * GMODE_LEGACY_B
516 * Rateset: 1b, 2b, 5.5, 11
517 * Preamble: Long
518 * Shortslot: Off
519 * GMODE_AUTO
520 * Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
521 * Extended Rateset: 6, 9, 12, 48
522 * Preamble: Long
523 * Shortslot: Auto
524 * GMODE_ONLY
525 * Rateset: 1b, 2b, 5.5b, 11b, 18, 24b, 36, 54
526 * Extended Rateset: 6b, 9, 12b, 48
527 * Preamble: Short required
528 * Shortslot: Auto
529 * GMODE_B_DEFERRED
530 * Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
531 * Extended Rateset: 6, 9, 12, 48
532 * Preamble: Long
533 * Shortslot: On
534 * GMODE_PERFORMANCE
535 * Rateset: 1b, 2b, 5.5b, 6b, 9, 11b, 12b, 18, 24b, 36, 48, 54
536 * Preamble: Short required
537 * Shortslot: On and required
538 * GMODE_LRS
539 * Rateset: 1b, 2b, 5.5b, 11b
540 * Extended Rateset: 6, 9, 12, 18, 24, 36, 48, 54
541 * Preamble: Long
542 * Shortslot: Auto
543 */
544#define GMODE_LEGACY_B 0
545#define GMODE_AUTO 1
546#define GMODE_ONLY 2
547#define GMODE_B_DEFERRED 3
548#define GMODE_PERFORMANCE 4
549#define GMODE_LRS 5
550#define GMODE_MAX 6
551
552/* MCS values greater than this enable multiple streams */
553#define HIGHEST_SINGLE_STREAM_MCS 7
554
555#define MAXBANDS 2 /* Maximum #of bands */
556
557/* max number of antenna configurations */
558#define ANT_SELCFG_MAX 4
559
560struct brcms_antselcfg {
561 u8 ant_config[ANT_SELCFG_MAX]; /* antenna configuration */
562 u8 num_antcfg; /* number of available antenna configurations */
563};
564
565/* common functions for every port */
566struct brcms_c_info *
567brcms_c_attach(struct brcms_info *wl, u16 vendor, u16 device, uint unit,
568 bool piomode, void __iomem *regsva, struct pci_dev *btparam,
569 uint *perr);
570extern uint brcms_c_detach(struct brcms_c_info *wlc);
571extern int brcms_c_up(struct brcms_c_info *wlc);
572extern uint brcms_c_down(struct brcms_c_info *wlc);
573
574extern bool brcms_c_chipmatch(u16 vendor, u16 device);
575extern void brcms_c_init(struct brcms_c_info *wlc);
576extern void brcms_c_reset(struct brcms_c_info *wlc);
577
578extern void brcms_c_intrson(struct brcms_c_info *wlc);
579extern u32 brcms_c_intrsoff(struct brcms_c_info *wlc);
580extern void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask);
581extern bool brcms_c_intrsupd(struct brcms_c_info *wlc);
582extern bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc);
583extern bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded);
584extern void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc,
585 struct sk_buff *sdu,
586 struct ieee80211_hw *hw);
587extern bool brcms_c_aggregatable(struct brcms_c_info *wlc, u8 tid);
588
589/* helper functions */
590extern void brcms_c_statsupd(struct brcms_c_info *wlc);
591extern void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx,
592 int val);
593extern int brcms_c_get_header_len(void);
594extern void brcms_c_mac_bcn_promisc_change(struct brcms_c_info *wlc,
595 bool promisc);
596extern void brcms_c_set_addrmatch(struct brcms_c_info *wlc,
597 int match_reg_offset,
598 const u8 *addr);
599extern void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
600 const struct ieee80211_tx_queue_params *arg,
601 bool suspend);
602extern struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc);
603
604/* common functions for every port */
605extern void brcms_c_mhf(struct brcms_c_info *wlc, u8 idx, u16 mask, u16 val,
606 int bands);
607extern void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
608 struct brcms_c_rateset *rateset);
609extern void brcms_default_rateset(struct brcms_c_info *wlc,
610 struct brcms_c_rateset *rs);
611
612extern void brcms_c_ampdu_flush(struct brcms_c_info *wlc,
613 struct ieee80211_sta *sta, u16 tid);
614extern void brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid,
615 u8 ba_wsize, uint max_rx_ampdu_bytes);
616extern char *getvar(struct si_pub *sih, enum brcms_srom_id id);
617extern int getintvar(struct si_pub *sih, enum brcms_srom_id id);
618
619/* wlc_phy.c helper functions */
620extern void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc);
621extern void brcms_c_mctrl(struct brcms_c_info *wlc, u32 mask, u32 val);
622
623extern int brcms_c_module_register(struct brcms_pub *pub,
624 const char *name, struct brcms_info *hdl,
625 int (*down_fn)(void *handle));
626extern int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
627 struct brcms_info *hdl);
628extern void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc);
629extern void brcms_c_enable_mac(struct brcms_c_info *wlc);
630extern void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state);
631extern void brcms_c_scan_start(struct brcms_c_info *wlc);
632extern void brcms_c_scan_stop(struct brcms_c_info *wlc);
633extern int brcms_c_get_curband(struct brcms_c_info *wlc);
634extern void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc,
635 bool drop);
636
637int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel);
638int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl);
639void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
640 struct brcm_rateset *currs);
641int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs);
642int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period);
643u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx);
644void brcms_c_set_shortslot_override(struct brcms_c_info *wlc,
645 s8 sslot_override);
646void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval);
647int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr);
648int brcms_c_get_tx_power(struct brcms_c_info *wlc);
649void brcms_c_set_radio_mpc(struct brcms_c_info *wlc, bool mpc);
650
651/* helper functions */
652extern bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc);
653extern bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc);
654
655#endif /* _BRCM_PUB_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/rate.c b/drivers/staging/brcm80211/brcmsmac/rate.c
deleted file mode 100644
index 0a0c0ad4f96..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/rate.c
+++ /dev/null
@@ -1,514 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <brcmu_wifi.h>
18#include <brcmu_utils.h>
19
20#include "d11.h"
21#include "pub.h"
22#include "rate.h"
23
24/*
25 * Rate info per rate: It tells whether a rate is ofdm or not and its phy_rate
26 * value
27 */
28const u8 rate_info[BRCM_MAXRATE + 1] = {
29 /* 0 1 2 3 4 5 6 7 8 9 */
30/* 0 */ 0x00, 0x00, 0x0a, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
31/* 10 */ 0x00, 0x37, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x00,
32/* 20 */ 0x00, 0x00, 0x6e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00,
33/* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, 0x00, 0x00,
34/* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00,
35/* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
36/* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
37/* 70 */ 0x00, 0x00, 0x8d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
38/* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
39/* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00,
40/* 100 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8c
41};
42
43/* rates are in units of Kbps */
44const struct brcms_mcs_info mcs_table[MCS_TABLE_SIZE] = {
45 /* MCS 0: SS 1, MOD: BPSK, CR 1/2 */
46 {6500, 13500, CEIL(6500 * 10, 9), CEIL(13500 * 10, 9), 0x00,
47 BRCM_RATE_6M},
48 /* MCS 1: SS 1, MOD: QPSK, CR 1/2 */
49 {13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x08,
50 BRCM_RATE_12M},
51 /* MCS 2: SS 1, MOD: QPSK, CR 3/4 */
52 {19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x0A,
53 BRCM_RATE_18M},
54 /* MCS 3: SS 1, MOD: 16QAM, CR 1/2 */
55 {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x10,
56 BRCM_RATE_24M},
57 /* MCS 4: SS 1, MOD: 16QAM, CR 3/4 */
58 {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x12,
59 BRCM_RATE_36M},
60 /* MCS 5: SS 1, MOD: 64QAM, CR 2/3 */
61 {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0x19,
62 BRCM_RATE_48M},
63 /* MCS 6: SS 1, MOD: 64QAM, CR 3/4 */
64 {58500, 121500, CEIL(58500 * 10, 9), CEIL(121500 * 10, 9), 0x1A,
65 BRCM_RATE_54M},
66 /* MCS 7: SS 1, MOD: 64QAM, CR 5/6 */
67 {65000, 135000, CEIL(65000 * 10, 9), CEIL(135000 * 10, 9), 0x1C,
68 BRCM_RATE_54M},
69 /* MCS 8: SS 2, MOD: BPSK, CR 1/2 */
70 {13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x40,
71 BRCM_RATE_6M},
72 /* MCS 9: SS 2, MOD: QPSK, CR 1/2 */
73 {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x48,
74 BRCM_RATE_12M},
75 /* MCS 10: SS 2, MOD: QPSK, CR 3/4 */
76 {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x4A,
77 BRCM_RATE_18M},
78 /* MCS 11: SS 2, MOD: 16QAM, CR 1/2 */
79 {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0x50,
80 BRCM_RATE_24M},
81 /* MCS 12: SS 2, MOD: 16QAM, CR 3/4 */
82 {78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0x52,
83 BRCM_RATE_36M},
84 /* MCS 13: SS 2, MOD: 64QAM, CR 2/3 */
85 {104000, 216000, CEIL(104000 * 10, 9), CEIL(216000 * 10, 9), 0x59,
86 BRCM_RATE_48M},
87 /* MCS 14: SS 2, MOD: 64QAM, CR 3/4 */
88 {117000, 243000, CEIL(117000 * 10, 9), CEIL(243000 * 10, 9), 0x5A,
89 BRCM_RATE_54M},
90 /* MCS 15: SS 2, MOD: 64QAM, CR 5/6 */
91 {130000, 270000, CEIL(130000 * 10, 9), CEIL(270000 * 10, 9), 0x5C,
92 BRCM_RATE_54M},
93 /* MCS 16: SS 3, MOD: BPSK, CR 1/2 */
94 {19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x80,
95 BRCM_RATE_6M},
96 /* MCS 17: SS 3, MOD: QPSK, CR 1/2 */
97 {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x88,
98 BRCM_RATE_12M},
99 /* MCS 18: SS 3, MOD: QPSK, CR 3/4 */
100 {58500, 121500, CEIL(58500 * 10, 9), CEIL(121500 * 10, 9), 0x8A,
101 BRCM_RATE_18M},
102 /* MCS 19: SS 3, MOD: 16QAM, CR 1/2 */
103 {78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0x90,
104 BRCM_RATE_24M},
105 /* MCS 20: SS 3, MOD: 16QAM, CR 3/4 */
106 {117000, 243000, CEIL(117000 * 10, 9), CEIL(243000 * 10, 9), 0x92,
107 BRCM_RATE_36M},
108 /* MCS 21: SS 3, MOD: 64QAM, CR 2/3 */
109 {156000, 324000, CEIL(156000 * 10, 9), CEIL(324000 * 10, 9), 0x99,
110 BRCM_RATE_48M},
111 /* MCS 22: SS 3, MOD: 64QAM, CR 3/4 */
112 {175500, 364500, CEIL(175500 * 10, 9), CEIL(364500 * 10, 9), 0x9A,
113 BRCM_RATE_54M},
114 /* MCS 23: SS 3, MOD: 64QAM, CR 5/6 */
115 {195000, 405000, CEIL(195000 * 10, 9), CEIL(405000 * 10, 9), 0x9B,
116 BRCM_RATE_54M},
117 /* MCS 24: SS 4, MOD: BPSK, CR 1/2 */
118 {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0xC0,
119 BRCM_RATE_6M},
120 /* MCS 25: SS 4, MOD: QPSK, CR 1/2 */
121 {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0xC8,
122 BRCM_RATE_12M},
123 /* MCS 26: SS 4, MOD: QPSK, CR 3/4 */
124 {78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0xCA,
125 BRCM_RATE_18M},
126 /* MCS 27: SS 4, MOD: 16QAM, CR 1/2 */
127 {104000, 216000, CEIL(104000 * 10, 9), CEIL(216000 * 10, 9), 0xD0,
128 BRCM_RATE_24M},
129 /* MCS 28: SS 4, MOD: 16QAM, CR 3/4 */
130 {156000, 324000, CEIL(156000 * 10, 9), CEIL(324000 * 10, 9), 0xD2,
131 BRCM_RATE_36M},
132 /* MCS 29: SS 4, MOD: 64QAM, CR 2/3 */
133 {208000, 432000, CEIL(208000 * 10, 9), CEIL(432000 * 10, 9), 0xD9,
134 BRCM_RATE_48M},
135 /* MCS 30: SS 4, MOD: 64QAM, CR 3/4 */
136 {234000, 486000, CEIL(234000 * 10, 9), CEIL(486000 * 10, 9), 0xDA,
137 BRCM_RATE_54M},
138 /* MCS 31: SS 4, MOD: 64QAM, CR 5/6 */
139 {260000, 540000, CEIL(260000 * 10, 9), CEIL(540000 * 10, 9), 0xDB,
140 BRCM_RATE_54M},
141 /* MCS 32: SS 1, MOD: BPSK, CR 1/2 */
142 {0, 6000, 0, CEIL(6000 * 10, 9), 0x00, BRCM_RATE_6M},
143};
144
145/*
146 * phycfg for legacy OFDM frames: code rate, modulation scheme, spatial streams
147 * Number of spatial streams: always 1 other fields: refer to table 78 of
148 * section 17.3.2.2 of the original .11a standard
149 */
150struct legacy_phycfg {
151 u32 rate_ofdm; /* ofdm mac rate */
152 /* phy ctl byte 3, code rate, modulation type, # of streams */
153 u8 tx_phy_ctl3;
154};
155
156/* Number of legacy_rate_cfg entries in the table */
157#define LEGACY_PHYCFG_TABLE_SIZE 12
158
159/*
160 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK Data Rate
161 * Eventually MIMOPHY would also be converted to this format
162 * 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps
163 */
164static const struct
165legacy_phycfg legacy_phycfg_table[LEGACY_PHYCFG_TABLE_SIZE] = {
166 {BRCM_RATE_1M, 0x00}, /* CCK 1Mbps, data rate 0 */
167 {BRCM_RATE_2M, 0x08}, /* CCK 2Mbps, data rate 1 */
168 {BRCM_RATE_5M5, 0x10}, /* CCK 5.5Mbps, data rate 2 */
169 {BRCM_RATE_11M, 0x18}, /* CCK 11Mbps, data rate 3 */
170 /* OFDM 6Mbps, code rate 1/2, BPSK, 1 spatial stream */
171 {BRCM_RATE_6M, 0x00},
172 /* OFDM 9Mbps, code rate 3/4, BPSK, 1 spatial stream */
173 {BRCM_RATE_9M, 0x02},
174 /* OFDM 12Mbps, code rate 1/2, QPSK, 1 spatial stream */
175 {BRCM_RATE_12M, 0x08},
176 /* OFDM 18Mbps, code rate 3/4, QPSK, 1 spatial stream */
177 {BRCM_RATE_18M, 0x0A},
178 /* OFDM 24Mbps, code rate 1/2, 16-QAM, 1 spatial stream */
179 {BRCM_RATE_24M, 0x10},
180 /* OFDM 36Mbps, code rate 3/4, 16-QAM, 1 spatial stream */
181 {BRCM_RATE_36M, 0x12},
182 /* OFDM 48Mbps, code rate 2/3, 64-QAM, 1 spatial stream */
183 {BRCM_RATE_48M, 0x19},
184 /* OFDM 54Mbps, code rate 3/4, 64-QAM, 1 spatial stream */
185 {BRCM_RATE_54M, 0x1A},
186};
187
188/* Hardware rates (also encodes default basic rates) */
189
190const struct brcms_c_rateset cck_ofdm_mimo_rates = {
191 12,
192 /* 1b, 2b, 5.5b, 6, 9, 11b, 12, 18, 24, 36, 48, */
193 { 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
194 /* 54 Mbps */
195 0x6c},
196 0x00,
197 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
198 0x00, 0x00, 0x00, 0x00, 0x00}
199};
200
201const struct brcms_c_rateset ofdm_mimo_rates = {
202 8,
203 /* 6b, 9, 12b, 18, 24b, 36, 48, 54 Mbps */
204 { 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
205 0x00,
206 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
207 0x00, 0x00, 0x00, 0x00, 0x00}
208};
209
210/* Default ratesets that include MCS32 for 40BW channels */
211static const struct brcms_c_rateset cck_ofdm_40bw_mimo_rates = {
212 12,
213 /* 1b, 2b, 5.5b, 6, 9, 11b, 12, 18, 24, 36, 48 */
214 { 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
215 /* 54 Mbps */
216 0x6c},
217 0x00,
218 { 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
219 0x00, 0x00, 0x00, 0x00, 0x00}
220};
221
222static const struct brcms_c_rateset ofdm_40bw_mimo_rates = {
223 8,
224 /* 6b, 9, 12b, 18, 24b, 36, 48, 54 Mbps */
225 { 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
226 0x00,
227 { 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
228 0x00, 0x00, 0x00, 0x00, 0x00}
229};
230
231const struct brcms_c_rateset cck_ofdm_rates = {
232 12,
233 /* 1b, 2b, 5.5b, 6, 9, 11b, 12, 18, 24, 36, 48,*/
234 { 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
235 /*54 Mbps */
236 0x6c},
237 0x00,
238 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
239 0x00, 0x00, 0x00, 0x00, 0x00}
240};
241
242const struct brcms_c_rateset gphy_legacy_rates = {
243 4,
244 /* 1b, 2b, 5.5b, 11b Mbps */
245 { 0x82, 0x84, 0x8b, 0x96},
246 0x00,
247 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
248 0x00, 0x00, 0x00, 0x00, 0x00}
249};
250
251const struct brcms_c_rateset ofdm_rates = {
252 8,
253 /* 6b, 9, 12b, 18, 24b, 36, 48, 54 Mbps */
254 { 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
255 0x00,
256 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x00}
258};
259
260const struct brcms_c_rateset cck_rates = {
261 4,
262 /* 1b, 2b, 5.5, 11 Mbps */
263 { 0x82, 0x84, 0x0b, 0x16},
264 0x00,
265 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
266 0x00, 0x00, 0x00, 0x00, 0x00}
267};
268
269/* check if rateset is valid.
270 * if check_brate is true, rateset without a basic rate is considered NOT valid.
271 */
272static bool brcms_c_rateset_valid(struct brcms_c_rateset *rs, bool check_brate)
273{
274 uint idx;
275
276 if (!rs->count)
277 return false;
278
279 if (!check_brate)
280 return true;
281
282 /* error if no basic rates */
283 for (idx = 0; idx < rs->count; idx++) {
284 if (rs->rates[idx] & BRCMS_RATE_FLAG)
285 return true;
286 }
287 return false;
288}
289
290void brcms_c_rateset_mcs_upd(struct brcms_c_rateset *rs, u8 txstreams)
291{
292 int i;
293 for (i = txstreams; i < MAX_STREAMS_SUPPORTED; i++)
294 rs->mcs[i] = 0;
295}
296
297/*
298 * filter based on hardware rateset, and sort filtered rateset with basic
299 * bit(s) preserved, and check if resulting rateset is valid.
300*/
301bool
302brcms_c_rate_hwrs_filter_sort_validate(struct brcms_c_rateset *rs,
303 const struct brcms_c_rateset *hw_rs,
304 bool check_brate, u8 txstreams)
305{
306 u8 rateset[BRCM_MAXRATE + 1];
307 u8 r;
308 uint count;
309 uint i;
310
311 memset(rateset, 0, sizeof(rateset));
312 count = rs->count;
313
314 for (i = 0; i < count; i++) {
315 /* mask off "basic rate" bit, BRCMS_RATE_FLAG */
316 r = (int)rs->rates[i] & BRCMS_RATE_MASK;
317 if ((r > BRCM_MAXRATE) || (rate_info[r] == 0))
318 continue;
319 rateset[r] = rs->rates[i]; /* preserve basic bit! */
320 }
321
322 /* fill out the rates in order, looking at only supported rates */
323 count = 0;
324 for (i = 0; i < hw_rs->count; i++) {
325 r = hw_rs->rates[i] & BRCMS_RATE_MASK;
326 if (rateset[r])
327 rs->rates[count++] = rateset[r];
328 }
329
330 rs->count = count;
331
332 /* only set the mcs rate bit if the equivalent hw mcs bit is set */
333 for (i = 0; i < MCSSET_LEN; i++)
334 rs->mcs[i] = (rs->mcs[i] & hw_rs->mcs[i]);
335
336 if (brcms_c_rateset_valid(rs, check_brate))
337 return true;
338 else
339 return false;
340}
341
342/* calculate the rate of a rx'd frame and return it as a ratespec */
343u32 brcms_c_compute_rspec(struct d11rxhdr *rxh, u8 *plcp)
344{
345 int phy_type;
346 u32 rspec = PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT;
347
348 phy_type =
349 ((rxh->RxChan & RXS_CHAN_PHYTYPE_MASK) >> RXS_CHAN_PHYTYPE_SHIFT);
350
351 if ((phy_type == PHY_TYPE_N) || (phy_type == PHY_TYPE_SSN) ||
352 (phy_type == PHY_TYPE_LCN) || (phy_type == PHY_TYPE_HT)) {
353 switch (rxh->PhyRxStatus_0 & PRXS0_FT_MASK) {
354 case PRXS0_CCK:
355 rspec =
356 cck_phy2mac_rate(
357 ((struct cck_phy_hdr *) plcp)->signal);
358 break;
359 case PRXS0_OFDM:
360 rspec =
361 ofdm_phy2mac_rate(
362 ((struct ofdm_phy_hdr *) plcp)->rlpt[0]);
363 break;
364 case PRXS0_PREN:
365 rspec = (plcp[0] & MIMO_PLCP_MCS_MASK) | RSPEC_MIMORATE;
366 if (plcp[0] & MIMO_PLCP_40MHZ) {
367 /* indicate rspec is for 40 MHz mode */
368 rspec &= ~RSPEC_BW_MASK;
369 rspec |= (PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT);
370 }
371 break;
372 case PRXS0_STDN:
373 /* fallthru */
374 default:
375 /* not supported, error condition */
376 break;
377 }
378 if (plcp3_issgi(plcp[3]))
379 rspec |= RSPEC_SHORT_GI;
380 } else
381 if ((phy_type == PHY_TYPE_A) || (rxh->PhyRxStatus_0 & PRXS0_OFDM))
382 rspec = ofdm_phy2mac_rate(
383 ((struct ofdm_phy_hdr *) plcp)->rlpt[0]);
384 else
385 rspec = cck_phy2mac_rate(
386 ((struct cck_phy_hdr *) plcp)->signal);
387
388 return rspec;
389}
390
391/* copy rateset src to dst as-is (no masking or sorting) */
392void brcms_c_rateset_copy(const struct brcms_c_rateset *src,
393 struct brcms_c_rateset *dst)
394{
395 memcpy(dst, src, sizeof(struct brcms_c_rateset));
396}
397
398/*
399 * Copy and selectively filter one rateset to another.
400 * 'basic_only' means only copy basic rates.
401 * 'rates' indicates cck (11b) and ofdm rates combinations.
402 * - 0: cck and ofdm
403 * - 1: cck only
404 * - 2: ofdm only
405 * 'xmask' is the copy mask (typically 0x7f or 0xff).
406 */
407void
408brcms_c_rateset_filter(struct brcms_c_rateset *src, struct brcms_c_rateset *dst,
409 bool basic_only, u8 rates, uint xmask, bool mcsallow)
410{
411 uint i;
412 uint r;
413 uint count;
414
415 count = 0;
416 for (i = 0; i < src->count; i++) {
417 r = src->rates[i];
418 if (basic_only && !(r & BRCMS_RATE_FLAG))
419 continue;
420 if (rates == BRCMS_RATES_CCK &&
421 is_ofdm_rate((r & BRCMS_RATE_MASK)))
422 continue;
423 if (rates == BRCMS_RATES_OFDM &&
424 is_cck_rate((r & BRCMS_RATE_MASK)))
425 continue;
426 dst->rates[count++] = r & xmask;
427 }
428 dst->count = count;
429 dst->htphy_membership = src->htphy_membership;
430
431 if (mcsallow && rates != BRCMS_RATES_CCK)
432 memcpy(&dst->mcs[0], &src->mcs[0], MCSSET_LEN);
433 else
434 brcms_c_rateset_mcs_clear(dst);
435}
436
437/* select rateset for a given phy_type and bandtype and filter it, sort it
438 * and fill rs_tgt with result
439 */
440void
441brcms_c_rateset_default(struct brcms_c_rateset *rs_tgt,
442 const struct brcms_c_rateset *rs_hw,
443 uint phy_type, int bandtype, bool cck_only,
444 uint rate_mask, bool mcsallow, u8 bw, u8 txstreams)
445{
446 const struct brcms_c_rateset *rs_dflt;
447 struct brcms_c_rateset rs_sel;
448 if ((PHYTYPE_IS(phy_type, PHY_TYPE_HT)) ||
449 (PHYTYPE_IS(phy_type, PHY_TYPE_N)) ||
450 (PHYTYPE_IS(phy_type, PHY_TYPE_LCN)) ||
451 (PHYTYPE_IS(phy_type, PHY_TYPE_SSN))) {
452 if (bandtype == BRCM_BAND_5G)
453 rs_dflt = (bw == BRCMS_20_MHZ ?
454 &ofdm_mimo_rates : &ofdm_40bw_mimo_rates);
455 else
456 rs_dflt = (bw == BRCMS_20_MHZ ?
457 &cck_ofdm_mimo_rates :
458 &cck_ofdm_40bw_mimo_rates);
459 } else if (PHYTYPE_IS(phy_type, PHY_TYPE_LP)) {
460 rs_dflt = (bandtype == BRCM_BAND_5G) ?
461 &ofdm_rates : &cck_ofdm_rates;
462 } else if (PHYTYPE_IS(phy_type, PHY_TYPE_A)) {
463 rs_dflt = &ofdm_rates;
464 } else if (PHYTYPE_IS(phy_type, PHY_TYPE_G)) {
465 rs_dflt = &cck_ofdm_rates;
466 } else {
467 /* should not happen, error condition */
468 rs_dflt = &cck_rates; /* force cck */
469 }
470
471 /* if hw rateset is not supplied, assign selected rateset to it */
472 if (!rs_hw)
473 rs_hw = rs_dflt;
474
475 brcms_c_rateset_copy(rs_dflt, &rs_sel);
476 brcms_c_rateset_mcs_upd(&rs_sel, txstreams);
477 brcms_c_rateset_filter(&rs_sel, rs_tgt, false,
478 cck_only ? BRCMS_RATES_CCK : BRCMS_RATES_CCK_OFDM,
479 rate_mask, mcsallow);
480 brcms_c_rate_hwrs_filter_sort_validate(rs_tgt, rs_hw, false,
481 mcsallow ? txstreams : 1);
482}
483
484s16 brcms_c_rate_legacy_phyctl(uint rate)
485{
486 uint i;
487 for (i = 0; i < LEGACY_PHYCFG_TABLE_SIZE; i++)
488 if (rate == legacy_phycfg_table[i].rate_ofdm)
489 return legacy_phycfg_table[i].tx_phy_ctl3;
490
491 return -1;
492}
493
494void brcms_c_rateset_mcs_clear(struct brcms_c_rateset *rateset)
495{
496 uint i;
497 for (i = 0; i < MCSSET_LEN; i++)
498 rateset->mcs[i] = 0;
499}
500
501void brcms_c_rateset_mcs_build(struct brcms_c_rateset *rateset, u8 txstreams)
502{
503 memcpy(&rateset->mcs[0], &cck_ofdm_mimo_rates.mcs[0], MCSSET_LEN);
504 brcms_c_rateset_mcs_upd(rateset, txstreams);
505}
506
507/* Based on bandwidth passed, allow/disallow MCS 32 in the rateset */
508void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset, u8 bw)
509{
510 if (bw == BRCMS_40_MHZ)
511 setbit(rateset->mcs, 32);
512 else
513 clrbit(rateset->mcs, 32);
514}
diff --git a/drivers/staging/brcm80211/brcmsmac/rate.h b/drivers/staging/brcm80211/brcmsmac/rate.h
deleted file mode 100644
index e7b9dc2f273..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/rate.h
+++ /dev/null
@@ -1,250 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_RATE_H_
18#define _BRCM_RATE_H_
19
20#include "types.h"
21#include "d11.h"
22
23extern const u8 rate_info[];
24extern const struct brcms_c_rateset cck_ofdm_mimo_rates;
25extern const struct brcms_c_rateset ofdm_mimo_rates;
26extern const struct brcms_c_rateset cck_ofdm_rates;
27extern const struct brcms_c_rateset ofdm_rates;
28extern const struct brcms_c_rateset cck_rates;
29extern const struct brcms_c_rateset gphy_legacy_rates;
30extern const struct brcms_c_rateset rate_limit_1_2;
31
32struct brcms_mcs_info {
33 /* phy rate in kbps [20Mhz] */
34 u32 phy_rate_20;
35 /* phy rate in kbps [40Mhz] */
36 u32 phy_rate_40;
37 /* phy rate in kbps [20Mhz] with SGI */
38 u32 phy_rate_20_sgi;
39 /* phy rate in kbps [40Mhz] with SGI */
40 u32 phy_rate_40_sgi;
41 /* phy ctl byte 3, code rate, modulation type, # of streams */
42 u8 tx_phy_ctl3;
43 /* matching legacy ofdm rate in 500bkps */
44 u8 leg_ofdm;
45};
46
47#define BRCMS_MAXMCS 32 /* max valid mcs index */
48#define MCS_TABLE_SIZE 33 /* Number of mcs entries in the table */
49extern const struct brcms_mcs_info mcs_table[];
50
51#define MCS_TXS_MASK 0xc0 /* num tx streams - 1 bit mask */
52#define MCS_TXS_SHIFT 6 /* num tx streams - 1 bit shift */
53
54/* returns num tx streams - 1 */
55static inline u8 mcs_2_txstreams(u8 mcs)
56{
57 return (mcs_table[mcs].tx_phy_ctl3 & MCS_TXS_MASK) >> MCS_TXS_SHIFT;
58}
59
60static inline uint mcs_2_rate(u8 mcs, bool is40, bool sgi)
61{
62 if (sgi) {
63 if (is40)
64 return mcs_table[mcs].phy_rate_40_sgi;
65 return mcs_table[mcs].phy_rate_20_sgi;
66 }
67 if (is40)
68 return mcs_table[mcs].phy_rate_40;
69
70 return mcs_table[mcs].phy_rate_20;
71}
72
73/* Macro to use the rate_info table */
74#define BRCMS_RATE_MASK_FULL 0xff /* Rate value mask with basic rate flag */
75
76/*
77 * rate spec : holds rate and mode specific information required to generate a
78 * tx frame. Legacy CCK and OFDM information is held in the same manner as was
79 * done in the past (in the lower byte) the upper 3 bytes primarily hold MIMO
80 * specific information
81 */
82
83/* rate spec bit fields */
84
85/* Either 500Kbps units or MIMO MCS idx */
86#define RSPEC_RATE_MASK 0x0000007F
87/* mimo MCS is stored in RSPEC_RATE_MASK */
88#define RSPEC_MIMORATE 0x08000000
89/* mimo bw mask */
90#define RSPEC_BW_MASK 0x00000700
91/* mimo bw shift */
92#define RSPEC_BW_SHIFT 8
93/* mimo Space/Time/Frequency mode mask */
94#define RSPEC_STF_MASK 0x00003800
95/* mimo Space/Time/Frequency mode shift */
96#define RSPEC_STF_SHIFT 11
97/* mimo coding type mask */
98#define RSPEC_CT_MASK 0x0000C000
99/* mimo coding type shift */
100#define RSPEC_CT_SHIFT 14
101/* mimo num STC streams per PLCP defn. */
102#define RSPEC_STC_MASK 0x00300000
103/* mimo num STC streams per PLCP defn. */
104#define RSPEC_STC_SHIFT 20
105/* mimo bit indicates adv coding in use */
106#define RSPEC_LDPC_CODING 0x00400000
107/* mimo bit indicates short GI in use */
108#define RSPEC_SHORT_GI 0x00800000
109/* bit indicates override both rate & mode */
110#define RSPEC_OVERRIDE 0x80000000
111/* bit indicates override rate only */
112#define RSPEC_OVERRIDE_MCS_ONLY 0x40000000
113
114static inline bool rspec_active(u32 rspec)
115{
116 return rspec & (RSPEC_RATE_MASK | RSPEC_MIMORATE);
117}
118
119static inline u8 rspec_phytxbyte2(u32 rspec)
120{
121 return (rspec & 0xff00) >> 8;
122}
123
124static inline u32 rspec_get_bw(u32 rspec)
125{
126 return (rspec & RSPEC_BW_MASK) >> RSPEC_BW_SHIFT;
127}
128
129static inline bool rspec_issgi(u32 rspec)
130{
131 return (rspec & RSPEC_SHORT_GI) == RSPEC_SHORT_GI;
132}
133
134static inline bool rspec_is40mhz(u32 rspec)
135{
136 u32 bw = rspec_get_bw(rspec);
137
138 return bw == PHY_TXC1_BW_40MHZ || bw == PHY_TXC1_BW_40MHZ_DUP;
139}
140
141static inline uint rspec2rate(u32 rspec)
142{
143 if (rspec & RSPEC_MIMORATE)
144 return mcs_2_rate(rspec & RSPEC_RATE_MASK, rspec_is40mhz(rspec),
145 rspec_issgi(rspec));
146 return rspec & RSPEC_RATE_MASK;
147}
148
149static inline u8 rspec_mimoplcp3(u32 rspec)
150{
151 return (rspec & 0xf00000) >> 16;
152}
153
154static inline bool plcp3_issgi(u8 plcp)
155{
156 return (plcp & (RSPEC_SHORT_GI >> 16)) != 0;
157}
158
159static inline uint rspec_stc(u32 rspec)
160{
161 return (rspec & RSPEC_STC_MASK) >> RSPEC_STC_SHIFT;
162}
163
164static inline uint rspec_stf(u32 rspec)
165{
166 return (rspec & RSPEC_STF_MASK) >> RSPEC_STF_SHIFT;
167}
168
169static inline bool is_mcs_rate(u32 ratespec)
170{
171 return (ratespec & RSPEC_MIMORATE) != 0;
172}
173
174static inline bool is_ofdm_rate(u32 ratespec)
175{
176 return !is_mcs_rate(ratespec) &&
177 (rate_info[ratespec & RSPEC_RATE_MASK] & BRCMS_RATE_FLAG);
178}
179
180static inline bool is_cck_rate(u32 ratespec)
181{
182 u32 rate = (ratespec & BRCMS_RATE_MASK);
183
184 return !is_mcs_rate(ratespec) && (
185 rate == BRCM_RATE_1M || rate == BRCM_RATE_2M ||
186 rate == BRCM_RATE_5M5 || rate == BRCM_RATE_11M);
187}
188
189static inline bool is_single_stream(u8 mcs)
190{
191 return mcs <= HIGHEST_SINGLE_STREAM_MCS || mcs == 32;
192}
193
194static inline u8 cck_rspec(u8 cck)
195{
196 return cck & RSPEC_RATE_MASK;
197}
198
199/* Convert encoded rate value in plcp header to numerical rates in 500 KHz
200 * increments */
201extern const u8 ofdm_rate_lookup[];
202
203static inline u8 ofdm_phy2mac_rate(u8 rlpt)
204{
205 return ofdm_rate_lookup[rlpt & 0x7];
206}
207
208static inline u8 cck_phy2mac_rate(u8 signal)
209{
210 return signal/5;
211}
212
213/* Rates specified in brcms_c_rateset_filter() */
214#define BRCMS_RATES_CCK_OFDM 0
215#define BRCMS_RATES_CCK 1
216#define BRCMS_RATES_OFDM 2
217
218/* sanitize, and sort a rateset with the basic bit(s) preserved, validate
219 * rateset */
220extern bool
221brcms_c_rate_hwrs_filter_sort_validate(struct brcms_c_rateset *rs,
222 const struct brcms_c_rateset *hw_rs,
223 bool check_brate, u8 txstreams);
224/* copy rateset src to dst as-is (no masking or sorting) */
225extern void brcms_c_rateset_copy(const struct brcms_c_rateset *src,
226 struct brcms_c_rateset *dst);
227
228/* would be nice to have these documented ... */
229extern u32 brcms_c_compute_rspec(struct d11rxhdr *rxh, u8 *plcp);
230
231extern void brcms_c_rateset_filter(struct brcms_c_rateset *src,
232 struct brcms_c_rateset *dst, bool basic_only, u8 rates, uint xmask,
233 bool mcsallow);
234
235extern void
236brcms_c_rateset_default(struct brcms_c_rateset *rs_tgt,
237 const struct brcms_c_rateset *rs_hw, uint phy_type,
238 int bandtype, bool cck_only, uint rate_mask,
239 bool mcsallow, u8 bw, u8 txstreams);
240
241extern s16 brcms_c_rate_legacy_phyctl(uint rate);
242
243extern void brcms_c_rateset_mcs_upd(struct brcms_c_rateset *rs, u8 txstreams);
244extern void brcms_c_rateset_mcs_clear(struct brcms_c_rateset *rateset);
245extern void brcms_c_rateset_mcs_build(struct brcms_c_rateset *rateset,
246 u8 txstreams);
247extern void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset,
248 u8 bw);
249
250#endif /* _BRCM_RATE_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/scb.h b/drivers/staging/brcm80211/brcmsmac/scb.h
deleted file mode 100644
index 51c79c7239b..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/scb.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_SCB_H_
18#define _BRCM_SCB_H_
19
20#include <linux/if_ether.h>
21#include <brcmu_utils.h>
22#include <defs.h>
23#include "types.h"
24
25#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */
26
27#define AMPDU_MAX_SCB_TID NUMPRIO
28
29/* scb flags */
30#define SCB_WMECAP 0x0040
31#define SCB_HTCAP 0x10000 /* HT (MIMO) capable device */
32#define SCB_IS40 0x80000 /* 40MHz capable */
33#define SCB_STBCCAP 0x40000000 /* STBC Capable */
34
35#define SCB_MAGIC 0xbeefcafe
36
37/* structure to store per-tid state for the ampdu initiator */
38struct scb_ampdu_tid_ini {
39 u8 tx_in_transit; /* number of pending mpdus in transit in driver */
40 u8 tid; /* initiator tid for easy lookup */
41 /* tx retry count; indexed by seq modulo */
42 u8 txretry[AMPDU_TX_BA_MAX_WSIZE];
43 struct scb *scb; /* backptr for easy lookup */
44 u8 ba_wsize; /* negotiated ba window size (in pdu) */
45};
46
47struct scb_ampdu {
48 struct scb *scb; /* back pointer for easy reference */
49 u8 mpdu_density; /* mpdu density */
50 u8 max_pdu; /* max pdus allowed in ampdu */
51 u8 release; /* # of mpdus released at a time */
52 u16 min_len; /* min mpdu len to support the density */
53 u32 max_rx_ampdu_bytes; /* max ampdu rcv length; 8k, 16k, 32k, 64k */
54
55 /*
56 * This could easily be a ini[] pointer and we keep this info in wl
57 * itself instead of having mac80211 hold it for us. Also could be made
58 * dynamic per tid instead of static.
59 */
60 /* initiator info - per tid (NUMPRIO): */
61 struct scb_ampdu_tid_ini ini[AMPDU_MAX_SCB_TID];
62};
63
64/* station control block - one per remote MAC address */
65struct scb {
66 u32 magic;
67 u32 flags; /* various bit flags as defined below */
68 u32 flags2; /* various bit flags2 as defined below */
69 u8 state; /* current state bitfield of auth/assoc process */
70 u8 ea[ETH_ALEN]; /* station address */
71 uint fragresid[NUMPRIO];/* #bytes unused in frag buffer per prio */
72
73 u16 seqctl[NUMPRIO]; /* seqctl of last received frame (for dups) */
74 /* seqctl of last received frame (for dups) for non-QoS data and
75 * management */
76 u16 seqctl_nonqos;
77 u16 seqnum[NUMPRIO];/* WME: driver maintained sw seqnum per priority */
78
79 struct scb_ampdu scb_ampdu; /* AMPDU state including per tid info */
80};
81
82#endif /* _BRCM_SCB_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/srom.c b/drivers/staging/brcm80211/brcmsmac/srom.c
deleted file mode 100644
index 99f791048e8..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/srom.c
+++ /dev/null
@@ -1,1298 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/kernel.h>
18#include <linux/string.h>
19#include <linux/io.h>
20#include <linux/etherdevice.h>
21#include <linux/crc8.h>
22#include <stdarg.h>
23
24#include <chipcommon.h>
25#include <brcmu_utils.h>
26#include "pub.h"
27#include "nicpci.h"
28#include "aiutils.h"
29#include "otp.h"
30#include "srom.h"
31
32/*
33 * SROM CRC8 polynomial value:
34 *
35 * x^8 + x^7 +x^6 + x^4 + x^2 + 1
36 */
37#define SROM_CRC8_POLY 0xAB
38
39/* Maximum srom: 6 Kilobits == 768 bytes */
40#define SROM_MAX 768
41
42/* PCI fields */
43#define PCI_F0DEVID 48
44
45#define SROM_WORDS 64
46
47#define SROM_SSID 2
48
49#define SROM_WL1LHMAXP 29
50
51#define SROM_WL1LPAB0 30
52#define SROM_WL1LPAB1 31
53#define SROM_WL1LPAB2 32
54
55#define SROM_WL1HPAB0 33
56#define SROM_WL1HPAB1 34
57#define SROM_WL1HPAB2 35
58
59#define SROM_MACHI_IL0 36
60#define SROM_MACMID_IL0 37
61#define SROM_MACLO_IL0 38
62#define SROM_MACHI_ET1 42
63#define SROM_MACMID_ET1 43
64#define SROM_MACLO_ET1 44
65#define SROM3_MACHI 37
66#define SROM3_MACMID 38
67#define SROM3_MACLO 39
68
69#define SROM_BXARSSI2G 40
70#define SROM_BXARSSI5G 41
71
72#define SROM_TRI52G 42
73#define SROM_TRI5GHL 43
74
75#define SROM_RXPO52G 45
76
77#define SROM_AABREV 46
78/* Fields in AABREV */
79#define SROM_BR_MASK 0x00ff
80#define SROM_CC_MASK 0x0f00
81#define SROM_CC_SHIFT 8
82#define SROM_AA0_MASK 0x3000
83#define SROM_AA0_SHIFT 12
84#define SROM_AA1_MASK 0xc000
85#define SROM_AA1_SHIFT 14
86
87#define SROM_WL0PAB0 47
88#define SROM_WL0PAB1 48
89#define SROM_WL0PAB2 49
90
91#define SROM_LEDBH10 50
92#define SROM_LEDBH32 51
93
94#define SROM_WL10MAXP 52
95
96#define SROM_WL1PAB0 53
97#define SROM_WL1PAB1 54
98#define SROM_WL1PAB2 55
99
100#define SROM_ITT 56
101
102#define SROM_BFL 57
103#define SROM_BFL2 28
104#define SROM3_BFL2 61
105
106#define SROM_AG10 58
107
108#define SROM_CCODE 59
109
110#define SROM_OPO 60
111
112#define SROM3_LEDDC 62
113
114#define SROM_CRCREV 63
115
116/* SROM Rev 4: Reallocate the software part of the srom to accommodate
117 * MIMO features. It assumes up to two PCIE functions and 440 bytes
118 * of usable srom i.e. the usable storage in chips with OTP that
119 * implements hardware redundancy.
120 */
121
122#define SROM4_WORDS 220
123
124#define SROM4_SIGN 32
125#define SROM4_SIGNATURE 0x5372
126
127#define SROM4_BREV 33
128
129#define SROM4_BFL0 34
130#define SROM4_BFL1 35
131#define SROM4_BFL2 36
132#define SROM4_BFL3 37
133#define SROM5_BFL0 37
134#define SROM5_BFL1 38
135#define SROM5_BFL2 39
136#define SROM5_BFL3 40
137
138#define SROM4_MACHI 38
139#define SROM4_MACMID 39
140#define SROM4_MACLO 40
141#define SROM5_MACHI 41
142#define SROM5_MACMID 42
143#define SROM5_MACLO 43
144
145#define SROM4_CCODE 41
146#define SROM4_REGREV 42
147#define SROM5_CCODE 34
148#define SROM5_REGREV 35
149
150#define SROM4_LEDBH10 43
151#define SROM4_LEDBH32 44
152#define SROM5_LEDBH10 59
153#define SROM5_LEDBH32 60
154
155#define SROM4_LEDDC 45
156#define SROM5_LEDDC 45
157
158#define SROM4_AA 46
159
160#define SROM4_AG10 47
161#define SROM4_AG32 48
162
163#define SROM4_TXPID2G 49
164#define SROM4_TXPID5G 51
165#define SROM4_TXPID5GL 53
166#define SROM4_TXPID5GH 55
167
168#define SROM4_TXRXC 61
169#define SROM4_TXCHAIN_MASK 0x000f
170#define SROM4_TXCHAIN_SHIFT 0
171#define SROM4_RXCHAIN_MASK 0x00f0
172#define SROM4_RXCHAIN_SHIFT 4
173#define SROM4_SWITCH_MASK 0xff00
174#define SROM4_SWITCH_SHIFT 8
175
176/* Per-path fields */
177#define MAX_PATH_SROM 4
178#define SROM4_PATH0 64
179#define SROM4_PATH1 87
180#define SROM4_PATH2 110
181#define SROM4_PATH3 133
182
183#define SROM4_2G_ITT_MAXP 0
184#define SROM4_2G_PA 1
185#define SROM4_5G_ITT_MAXP 5
186#define SROM4_5GLH_MAXP 6
187#define SROM4_5G_PA 7
188#define SROM4_5GL_PA 11
189#define SROM4_5GH_PA 15
190
191/* All the miriad power offsets */
192#define SROM4_2G_CCKPO 156
193#define SROM4_2G_OFDMPO 157
194#define SROM4_5G_OFDMPO 159
195#define SROM4_5GL_OFDMPO 161
196#define SROM4_5GH_OFDMPO 163
197#define SROM4_2G_MCSPO 165
198#define SROM4_5G_MCSPO 173
199#define SROM4_5GL_MCSPO 181
200#define SROM4_5GH_MCSPO 189
201#define SROM4_CDDPO 197
202#define SROM4_STBCPO 198
203#define SROM4_BW40PO 199
204#define SROM4_BWDUPPO 200
205
206#define SROM4_CRCREV 219
207
208/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
209 * This is acombined srom for both MIMO and SISO boards, usable in
210 * the .130 4Kilobit OTP with hardware redundancy.
211 */
212#define SROM8_BREV 65
213
214#define SROM8_BFL0 66
215#define SROM8_BFL1 67
216#define SROM8_BFL2 68
217#define SROM8_BFL3 69
218
219#define SROM8_MACHI 70
220#define SROM8_MACMID 71
221#define SROM8_MACLO 72
222
223#define SROM8_CCODE 73
224#define SROM8_REGREV 74
225
226#define SROM8_LEDBH10 75
227#define SROM8_LEDBH32 76
228
229#define SROM8_LEDDC 77
230
231#define SROM8_AA 78
232
233#define SROM8_AG10 79
234#define SROM8_AG32 80
235
236#define SROM8_TXRXC 81
237
238#define SROM8_BXARSSI2G 82
239#define SROM8_BXARSSI5G 83
240#define SROM8_TRI52G 84
241#define SROM8_TRI5GHL 85
242#define SROM8_RXPO52G 86
243
244#define SROM8_FEM2G 87
245#define SROM8_FEM5G 88
246#define SROM8_FEM_ANTSWLUT_MASK 0xf800
247#define SROM8_FEM_ANTSWLUT_SHIFT 11
248#define SROM8_FEM_TR_ISO_MASK 0x0700
249#define SROM8_FEM_TR_ISO_SHIFT 8
250#define SROM8_FEM_PDET_RANGE_MASK 0x00f8
251#define SROM8_FEM_PDET_RANGE_SHIFT 3
252#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
253#define SROM8_FEM_EXTPA_GAIN_SHIFT 1
254#define SROM8_FEM_TSSIPOS_MASK 0x0001
255#define SROM8_FEM_TSSIPOS_SHIFT 0
256
257#define SROM8_THERMAL 89
258
259/* Temp sense related entries */
260#define SROM8_MPWR_RAWTS 90
261#define SROM8_TS_SLP_OPT_CORRX 91
262/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable,
263 * IQSWP: IQ CAL swap disable */
264#define SROM8_FOC_HWIQ_IQSWP 92
265
266/* Temperature delta for PHY calibration */
267#define SROM8_PHYCAL_TEMPDELTA 93
268
269/* Per-path offsets & fields */
270#define SROM8_PATH0 96
271#define SROM8_PATH1 112
272#define SROM8_PATH2 128
273#define SROM8_PATH3 144
274
275#define SROM8_2G_ITT_MAXP 0
276#define SROM8_2G_PA 1
277#define SROM8_5G_ITT_MAXP 4
278#define SROM8_5GLH_MAXP 5
279#define SROM8_5G_PA 6
280#define SROM8_5GL_PA 9
281#define SROM8_5GH_PA 12
282
283/* All the miriad power offsets */
284#define SROM8_2G_CCKPO 160
285
286#define SROM8_2G_OFDMPO 161
287#define SROM8_5G_OFDMPO 163
288#define SROM8_5GL_OFDMPO 165
289#define SROM8_5GH_OFDMPO 167
290
291#define SROM8_2G_MCSPO 169
292#define SROM8_5G_MCSPO 177
293#define SROM8_5GL_MCSPO 185
294#define SROM8_5GH_MCSPO 193
295
296#define SROM8_CDDPO 201
297#define SROM8_STBCPO 202
298#define SROM8_BW40PO 203
299#define SROM8_BWDUPPO 204
300
301/* SISO PA parameters are in the path0 spaces */
302#define SROM8_SISO 96
303
304/* Legacy names for SISO PA paramters */
305#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
306#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
307#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
308#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
309#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
310#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
311#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
312#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
313#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
314#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
315#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
316#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
317#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
318#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
319#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
320
321/* SROM REV 9 */
322#define SROM9_2GPO_CCKBW20 160
323#define SROM9_2GPO_CCKBW20UL 161
324#define SROM9_2GPO_LOFDMBW20 162
325#define SROM9_2GPO_LOFDMBW20UL 164
326
327#define SROM9_5GLPO_LOFDMBW20 166
328#define SROM9_5GLPO_LOFDMBW20UL 168
329#define SROM9_5GMPO_LOFDMBW20 170
330#define SROM9_5GMPO_LOFDMBW20UL 172
331#define SROM9_5GHPO_LOFDMBW20 174
332#define SROM9_5GHPO_LOFDMBW20UL 176
333
334#define SROM9_2GPO_MCSBW20 178
335#define SROM9_2GPO_MCSBW20UL 180
336#define SROM9_2GPO_MCSBW40 182
337
338#define SROM9_5GLPO_MCSBW20 184
339#define SROM9_5GLPO_MCSBW20UL 186
340#define SROM9_5GLPO_MCSBW40 188
341#define SROM9_5GMPO_MCSBW20 190
342#define SROM9_5GMPO_MCSBW20UL 192
343#define SROM9_5GMPO_MCSBW40 194
344#define SROM9_5GHPO_MCSBW20 196
345#define SROM9_5GHPO_MCSBW20UL 198
346#define SROM9_5GHPO_MCSBW40 200
347
348#define SROM9_PO_MCS32 202
349#define SROM9_PO_LOFDM40DUP 203
350
351/* SROM flags (see sromvar_t) */
352
353/* value continues as described by the next entry */
354#define SRFL_MORE 1
355#define SRFL_NOFFS 2 /* value bits can't be all one's */
356#define SRFL_PRHEX 4 /* value is in hexdecimal format */
357#define SRFL_PRSIGN 8 /* value is in signed decimal format */
358#define SRFL_CCODE 0x10 /* value is in country code format */
359#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
360#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
361/* do not generate a nvram param, entry is for mfgc */
362#define SRFL_NOVAR 0x80
363
364/* Max. nvram variable table size */
365#define MAXSZ_NVRAM_VARS 4096
366
367/*
368 * indicates type of value.
369 */
370enum brcms_srom_var_type {
371 BRCMS_SROM_STRING,
372 BRCMS_SROM_SNUMBER,
373 BRCMS_SROM_UNUMBER
374};
375
376/*
377 * storage type for srom variable.
378 *
379 * var_list: for linked list operations.
380 * varid: identifier of the variable.
381 * var_type: type of variable.
382 * buf: variable value when var_type == BRCMS_SROM_STRING.
383 * uval: unsigned variable value when var_type == BRCMS_SROM_UNUMBER.
384 * sval: signed variable value when var_type == BRCMS_SROM_SNUMBER.
385 */
386struct brcms_srom_list_head {
387 struct list_head var_list;
388 enum brcms_srom_id varid;
389 enum brcms_srom_var_type var_type;
390 union {
391 char buf[0];
392 u32 uval;
393 s32 sval;
394 };
395};
396
397struct brcms_sromvar {
398 enum brcms_srom_id varid;
399 u32 revmask;
400 u32 flags;
401 u16 off;
402 u16 mask;
403};
404
405struct brcms_varbuf {
406 char *base; /* pointer to buffer base */
407 char *buf; /* pointer to current position */
408 unsigned int size; /* current (residual) size in bytes */
409};
410
411/*
412 * Assumptions:
413 * - Ethernet address spans across 3 consecutive words
414 *
415 * Table rules:
416 * - Add multiple entries next to each other if a value spans across multiple
417 * words (even multiple fields in the same word) with each entry except the
418 * last having it's SRFL_MORE bit set.
419 * - Ethernet address entry does not follow above rule and must not have
420 * SRFL_MORE bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
421 * - The last entry's name field must be NULL to indicate the end of the table.
422 * Other entries must have non-NULL name.
423 */
424static const struct brcms_sromvar pci_sromvars[] = {
425 {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
426 0xffff},
427 {BRCMS_SROM_BOARDREV, 0x0000000e, SRFL_PRHEX, SROM_AABREV,
428 SROM_BR_MASK},
429 {BRCMS_SROM_BOARDREV, 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
430 {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
431 {BRCMS_SROM_BOARDFLAGS, 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
432 {BRCMS_SROM_BOARDFLAGS, 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
433 0xffff},
434 {BRCMS_SROM_CONT, 0, 0, SROM_BFL2, 0xffff},
435 {BRCMS_SROM_BOARDFLAGS, 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
436 0xffff},
437 {BRCMS_SROM_CONT, 0, 0, SROM3_BFL2, 0xffff},
438 {BRCMS_SROM_BOARDFLAGS, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0,
439 0xffff},
440 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL1, 0xffff},
441 {BRCMS_SROM_BOARDFLAGS, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0,
442 0xffff},
443 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL1, 0xffff},
444 {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
445 0xffff},
446 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
447 {BRCMS_SROM_BOARDFLAGS2, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2,
448 0xffff},
449 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL3, 0xffff},
450 {BRCMS_SROM_BOARDFLAGS2, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2,
451 0xffff},
452 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL3, 0xffff},
453 {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
454 0xffff},
455 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
456 {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
457 {BRCMS_SROM_BOARDNUM, 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
458 {BRCMS_SROM_BOARDNUM, 0x00000008, 0, SROM3_MACLO, 0xffff},
459 {BRCMS_SROM_BOARDNUM, 0x00000010, 0, SROM4_MACLO, 0xffff},
460 {BRCMS_SROM_BOARDNUM, 0x000000e0, 0, SROM5_MACLO, 0xffff},
461 {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
462 {BRCMS_SROM_CC, 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
463 {BRCMS_SROM_REGREV, 0x00000008, 0, SROM_OPO, 0xff00},
464 {BRCMS_SROM_REGREV, 0x00000010, 0, SROM4_REGREV, 0x00ff},
465 {BRCMS_SROM_REGREV, 0x000000e0, 0, SROM5_REGREV, 0x00ff},
466 {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
467 {BRCMS_SROM_LEDBH0, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
468 {BRCMS_SROM_LEDBH1, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
469 {BRCMS_SROM_LEDBH2, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
470 {BRCMS_SROM_LEDBH3, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
471 {BRCMS_SROM_LEDBH0, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
472 {BRCMS_SROM_LEDBH1, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
473 {BRCMS_SROM_LEDBH2, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
474 {BRCMS_SROM_LEDBH3, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
475 {BRCMS_SROM_LEDBH0, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
476 {BRCMS_SROM_LEDBH1, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
477 {BRCMS_SROM_LEDBH2, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
478 {BRCMS_SROM_LEDBH3, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
479 {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
480 {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
481 {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
482 {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
483 {BRCMS_SROM_PA0B0, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
484 {BRCMS_SROM_PA0B1, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
485 {BRCMS_SROM_PA0B2, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
486 {BRCMS_SROM_PA0ITSSIT, 0x0000000e, 0, SROM_ITT, 0x00ff},
487 {BRCMS_SROM_PA0MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
488 {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
489 {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
490 {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
491 {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
492 {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
493 {BRCMS_SROM_OPO, 0x0000000c, 0, SROM_OPO, 0x00ff},
494 {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
495 {BRCMS_SROM_AA2G, 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
496 {BRCMS_SROM_AA2G, 0x000000f0, 0, SROM4_AA, 0x00ff},
497 {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
498 {BRCMS_SROM_AA5G, 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
499 {BRCMS_SROM_AA5G, 0x000000f0, 0, SROM4_AA, 0xff00},
500 {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
501 {BRCMS_SROM_AG0, 0x0000000e, 0, SROM_AG10, 0x00ff},
502 {BRCMS_SROM_AG1, 0x0000000e, 0, SROM_AG10, 0xff00},
503 {BRCMS_SROM_AG0, 0x000000f0, 0, SROM4_AG10, 0x00ff},
504 {BRCMS_SROM_AG1, 0x000000f0, 0, SROM4_AG10, 0xff00},
505 {BRCMS_SROM_AG2, 0x000000f0, 0, SROM4_AG32, 0x00ff},
506 {BRCMS_SROM_AG3, 0x000000f0, 0, SROM4_AG32, 0xff00},
507 {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
508 {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
509 {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
510 {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
511 {BRCMS_SROM_PA1B0, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
512 {BRCMS_SROM_PA1B1, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
513 {BRCMS_SROM_PA1B2, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
514 {BRCMS_SROM_PA1LOB0, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
515 {BRCMS_SROM_PA1LOB1, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
516 {BRCMS_SROM_PA1LOB2, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
517 {BRCMS_SROM_PA1HIB0, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
518 {BRCMS_SROM_PA1HIB1, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
519 {BRCMS_SROM_PA1HIB2, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
520 {BRCMS_SROM_PA1ITSSIT, 0x0000000e, 0, SROM_ITT, 0xff00},
521 {BRCMS_SROM_PA1MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
522 {BRCMS_SROM_PA1LOMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
523 {BRCMS_SROM_PA1HIMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
524 {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
525 {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
526 {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
527 {BRCMS_SROM_PA1LOB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
528 {BRCMS_SROM_PA1LOB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
529 {BRCMS_SROM_PA1LOB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
530 {BRCMS_SROM_PA1HIB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
531 {BRCMS_SROM_PA1HIB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
532 {BRCMS_SROM_PA1HIB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
533 {BRCMS_SROM_PA1ITSSIT, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
534 {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
535 {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
536 {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
537 {BRCMS_SROM_BXA2G, 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
538 {BRCMS_SROM_RSSISAV2G, 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
539 {BRCMS_SROM_RSSISMC2G, 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
540 {BRCMS_SROM_RSSISMF2G, 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
541 {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
542 {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
543 {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
544 {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
545 {BRCMS_SROM_BXA5G, 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
546 {BRCMS_SROM_RSSISAV5G, 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
547 {BRCMS_SROM_RSSISMC5G, 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
548 {BRCMS_SROM_RSSISMF5G, 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
549 {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
550 {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
551 {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
552 {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
553 {BRCMS_SROM_TRI2G, 0x00000008, 0, SROM_TRI52G, 0x00ff},
554 {BRCMS_SROM_TRI5G, 0x00000008, 0, SROM_TRI52G, 0xff00},
555 {BRCMS_SROM_TRI5GL, 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
556 {BRCMS_SROM_TRI5GH, 0x00000008, 0, SROM_TRI5GHL, 0xff00},
557 {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
558 {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
559 {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
560 {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
561 {BRCMS_SROM_RXPO2G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
562 {BRCMS_SROM_RXPO5G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
563 {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
564 {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
565 {BRCMS_SROM_TXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
566 SROM4_TXCHAIN_MASK},
567 {BRCMS_SROM_RXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
568 SROM4_RXCHAIN_MASK},
569 {BRCMS_SROM_ANTSWITCH, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
570 SROM4_SWITCH_MASK},
571 {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
572 SROM4_TXCHAIN_MASK},
573 {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
574 SROM4_RXCHAIN_MASK},
575 {BRCMS_SROM_ANTSWITCH, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
576 SROM4_SWITCH_MASK},
577 {BRCMS_SROM_TSSIPOS2G, 0xffffff00, 0, SROM8_FEM2G,
578 SROM8_FEM_TSSIPOS_MASK},
579 {BRCMS_SROM_EXTPAGAIN2G, 0xffffff00, 0, SROM8_FEM2G,
580 SROM8_FEM_EXTPA_GAIN_MASK},
581 {BRCMS_SROM_PDETRANGE2G, 0xffffff00, 0, SROM8_FEM2G,
582 SROM8_FEM_PDET_RANGE_MASK},
583 {BRCMS_SROM_TRISO2G, 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
584 {BRCMS_SROM_ANTSWCTL2G, 0xffffff00, 0, SROM8_FEM2G,
585 SROM8_FEM_ANTSWLUT_MASK},
586 {BRCMS_SROM_TSSIPOS5G, 0xffffff00, 0, SROM8_FEM5G,
587 SROM8_FEM_TSSIPOS_MASK},
588 {BRCMS_SROM_EXTPAGAIN5G, 0xffffff00, 0, SROM8_FEM5G,
589 SROM8_FEM_EXTPA_GAIN_MASK},
590 {BRCMS_SROM_PDETRANGE5G, 0xffffff00, 0, SROM8_FEM5G,
591 SROM8_FEM_PDET_RANGE_MASK},
592 {BRCMS_SROM_TRISO5G, 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
593 {BRCMS_SROM_ANTSWCTL5G, 0xffffff00, 0, SROM8_FEM5G,
594 SROM8_FEM_ANTSWLUT_MASK},
595 {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
596 {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
597 {BRCMS_SROM_TXPID2GA0, 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
598 {BRCMS_SROM_TXPID2GA1, 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
599 {BRCMS_SROM_TXPID2GA2, 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
600 {BRCMS_SROM_TXPID2GA3, 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
601 {BRCMS_SROM_TXPID5GA0, 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
602 {BRCMS_SROM_TXPID5GA1, 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
603 {BRCMS_SROM_TXPID5GA2, 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
604 {BRCMS_SROM_TXPID5GA3, 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
605 {BRCMS_SROM_TXPID5GLA0, 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
606 {BRCMS_SROM_TXPID5GLA1, 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
607 {BRCMS_SROM_TXPID5GLA2, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
608 {BRCMS_SROM_TXPID5GLA3, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
609 {BRCMS_SROM_TXPID5GHA0, 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
610 {BRCMS_SROM_TXPID5GHA1, 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
611 {BRCMS_SROM_TXPID5GHA2, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
612 {BRCMS_SROM_TXPID5GHA3, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
613
614 {BRCMS_SROM_CCODE, 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
615 {BRCMS_SROM_CCODE, 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
616 {BRCMS_SROM_CCODE, 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
617 {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
618 {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
619 {BRCMS_SROM_MACADDR, 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
620 {BRCMS_SROM_MACADDR, 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
621 {BRCMS_SROM_MACADDR, 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
622 {BRCMS_SROM_IL0MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0,
623 0xffff},
624 {BRCMS_SROM_ET1MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1,
625 0xffff},
626 {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
627 0xffff},
628 {BRCMS_SROM_LEDDC, 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC,
629 0xffff},
630 {BRCMS_SROM_LEDDC, 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC,
631 0xffff},
632 {BRCMS_SROM_LEDDC, 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC,
633 0xffff},
634 {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
635 0x01ff},
636 {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
637 0xfe00},
638 {BRCMS_SROM_TEMPSENSE_SLOPE, 0xffffff00, SRFL_PRHEX,
639 SROM8_TS_SLP_OPT_CORRX, 0x00ff},
640 {BRCMS_SROM_TEMPCORRX, 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
641 0xfc00},
642 {BRCMS_SROM_TEMPSENSE_OPTION, 0xffffff00, SRFL_PRHEX,
643 SROM8_TS_SLP_OPT_CORRX, 0x0300},
644 {BRCMS_SROM_FREQOFFSET_CORR, 0xffffff00, SRFL_PRHEX,
645 SROM8_FOC_HWIQ_IQSWP, 0x000f},
646 {BRCMS_SROM_IQCAL_SWP_DIS, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
647 0x0010},
648 {BRCMS_SROM_HW_IQCAL_EN, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
649 0x0020},
650 {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
651 0x00ff},
652
653 {BRCMS_SROM_CCK2GPO, 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
654 {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
655 {BRCMS_SROM_OFDM2GPO, 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
656 {BRCMS_SROM_CONT, 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
657 {BRCMS_SROM_OFDM5GPO, 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
658 {BRCMS_SROM_CONT, 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
659 {BRCMS_SROM_OFDM5GLPO, 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
660 {BRCMS_SROM_CONT, 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
661 {BRCMS_SROM_OFDM5GHPO, 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
662 {BRCMS_SROM_CONT, 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
663 {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
664 {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
665 {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
666 {BRCMS_SROM_CONT, 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
667 {BRCMS_SROM_OFDM5GLPO, 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
668 {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
669 {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
670 {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
671 {BRCMS_SROM_MCS2GPO0, 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
672 {BRCMS_SROM_MCS2GPO1, 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
673 {BRCMS_SROM_MCS2GPO2, 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
674 {BRCMS_SROM_MCS2GPO3, 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
675 {BRCMS_SROM_MCS2GPO4, 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
676 {BRCMS_SROM_MCS2GPO5, 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
677 {BRCMS_SROM_MCS2GPO6, 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
678 {BRCMS_SROM_MCS2GPO7, 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
679 {BRCMS_SROM_MCS5GPO0, 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
680 {BRCMS_SROM_MCS5GPO1, 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
681 {BRCMS_SROM_MCS5GPO2, 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
682 {BRCMS_SROM_MCS5GPO3, 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
683 {BRCMS_SROM_MCS5GPO4, 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
684 {BRCMS_SROM_MCS5GPO5, 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
685 {BRCMS_SROM_MCS5GPO6, 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
686 {BRCMS_SROM_MCS5GPO7, 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
687 {BRCMS_SROM_MCS5GLPO0, 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
688 {BRCMS_SROM_MCS5GLPO1, 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
689 {BRCMS_SROM_MCS5GLPO2, 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
690 {BRCMS_SROM_MCS5GLPO3, 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
691 {BRCMS_SROM_MCS5GLPO4, 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
692 {BRCMS_SROM_MCS5GLPO5, 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
693 {BRCMS_SROM_MCS5GLPO6, 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
694 {BRCMS_SROM_MCS5GLPO7, 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
695 {BRCMS_SROM_MCS5GHPO0, 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
696 {BRCMS_SROM_MCS5GHPO1, 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
697 {BRCMS_SROM_MCS5GHPO2, 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
698 {BRCMS_SROM_MCS5GHPO3, 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
699 {BRCMS_SROM_MCS5GHPO4, 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
700 {BRCMS_SROM_MCS5GHPO5, 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
701 {BRCMS_SROM_MCS5GHPO6, 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
702 {BRCMS_SROM_MCS5GHPO7, 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
703 {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
704 {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
705 {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
706 {BRCMS_SROM_MCS2GPO3, 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
707 {BRCMS_SROM_MCS2GPO4, 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
708 {BRCMS_SROM_MCS2GPO5, 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
709 {BRCMS_SROM_MCS2GPO6, 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
710 {BRCMS_SROM_MCS2GPO7, 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
711 {BRCMS_SROM_MCS5GPO0, 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
712 {BRCMS_SROM_MCS5GPO1, 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
713 {BRCMS_SROM_MCS5GPO2, 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
714 {BRCMS_SROM_MCS5GPO3, 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
715 {BRCMS_SROM_MCS5GPO4, 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
716 {BRCMS_SROM_MCS5GPO5, 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
717 {BRCMS_SROM_MCS5GPO6, 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
718 {BRCMS_SROM_MCS5GPO7, 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
719 {BRCMS_SROM_MCS5GLPO0, 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
720 {BRCMS_SROM_MCS5GLPO1, 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
721 {BRCMS_SROM_MCS5GLPO2, 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
722 {BRCMS_SROM_MCS5GLPO3, 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
723 {BRCMS_SROM_MCS5GLPO4, 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
724 {BRCMS_SROM_MCS5GLPO5, 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
725 {BRCMS_SROM_MCS5GLPO6, 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
726 {BRCMS_SROM_MCS5GLPO7, 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
727 {BRCMS_SROM_MCS5GHPO0, 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
728 {BRCMS_SROM_MCS5GHPO1, 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
729 {BRCMS_SROM_MCS5GHPO2, 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
730 {BRCMS_SROM_MCS5GHPO3, 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
731 {BRCMS_SROM_MCS5GHPO4, 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
732 {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
733 {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
734 {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
735 {BRCMS_SROM_CDDPO, 0x000000f0, 0, SROM4_CDDPO, 0xffff},
736 {BRCMS_SROM_STBCPO, 0x000000f0, 0, SROM4_STBCPO, 0xffff},
737 {BRCMS_SROM_BW40PO, 0x000000f0, 0, SROM4_BW40PO, 0xffff},
738 {BRCMS_SROM_BWDUPPO, 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
739 {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
740 {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
741 {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
742 {BRCMS_SROM_BWDUPPO, 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
743
744 /* power per rate from sromrev 9 */
745 {BRCMS_SROM_CCKBW202GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
746 {BRCMS_SROM_CCKBW20UL2GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
747 {BRCMS_SROM_LEGOFDMBW202GPO, 0xfffffe00, SRFL_MORE,
748 SROM9_2GPO_LOFDMBW20, 0xffff},
749 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
750 {BRCMS_SROM_LEGOFDMBW20UL2GPO, 0xfffffe00, SRFL_MORE,
751 SROM9_2GPO_LOFDMBW20UL, 0xffff},
752 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
753 {BRCMS_SROM_LEGOFDMBW205GLPO, 0xfffffe00, SRFL_MORE,
754 SROM9_5GLPO_LOFDMBW20, 0xffff},
755 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
756 {BRCMS_SROM_LEGOFDMBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
757 SROM9_5GLPO_LOFDMBW20UL, 0xffff},
758 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
759 {BRCMS_SROM_LEGOFDMBW205GMPO, 0xfffffe00, SRFL_MORE,
760 SROM9_5GMPO_LOFDMBW20, 0xffff},
761 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
762 {BRCMS_SROM_LEGOFDMBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
763 SROM9_5GMPO_LOFDMBW20UL, 0xffff},
764 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
765 {BRCMS_SROM_LEGOFDMBW205GHPO, 0xfffffe00, SRFL_MORE,
766 SROM9_5GHPO_LOFDMBW20, 0xffff},
767 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
768 {BRCMS_SROM_LEGOFDMBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
769 SROM9_5GHPO_LOFDMBW20UL, 0xffff},
770 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
771 {BRCMS_SROM_MCSBW202GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20,
772 0xffff},
773 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
774 {BRCMS_SROM_MCSBW20UL2GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL,
775 0xffff},
776 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
777 {BRCMS_SROM_MCSBW402GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40,
778 0xffff},
779 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
780 {BRCMS_SROM_MCSBW205GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20,
781 0xffff},
782 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
783 {BRCMS_SROM_MCSBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
784 SROM9_5GLPO_MCSBW20UL, 0xffff},
785 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
786 {BRCMS_SROM_MCSBW405GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40,
787 0xffff},
788 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
789 {BRCMS_SROM_MCSBW205GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20,
790 0xffff},
791 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
792 {BRCMS_SROM_MCSBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
793 SROM9_5GMPO_MCSBW20UL, 0xffff},
794 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
795 {BRCMS_SROM_MCSBW405GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40,
796 0xffff},
797 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
798 {BRCMS_SROM_MCSBW205GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20,
799 0xffff},
800 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
801 {BRCMS_SROM_MCSBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
802 SROM9_5GHPO_MCSBW20UL, 0xffff},
803 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
804 {BRCMS_SROM_MCSBW405GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40,
805 0xffff},
806 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
807 {BRCMS_SROM_MCS32PO, 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
808 {BRCMS_SROM_LEGOFDM40DUPPO, 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
809
810 {BRCMS_SROM_NULL, 0, 0, 0, 0}
811};
812
813static const struct brcms_sromvar perpath_pci_sromvars[] = {
814 {BRCMS_SROM_MAXP2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
815 {BRCMS_SROM_ITT2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
816 {BRCMS_SROM_ITT5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
817 {BRCMS_SROM_PA2GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
818 {BRCMS_SROM_PA2GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
819 {BRCMS_SROM_PA2GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
820 {BRCMS_SROM_PA2GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
821 {BRCMS_SROM_MAXP5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
822 {BRCMS_SROM_MAXP5GHA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
823 {BRCMS_SROM_MAXP5GLA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
824 {BRCMS_SROM_PA5GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
825 {BRCMS_SROM_PA5GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
826 {BRCMS_SROM_PA5GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
827 {BRCMS_SROM_PA5GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
828 {BRCMS_SROM_PA5GLW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
829 {BRCMS_SROM_PA5GLW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1,
830 0xffff},
831 {BRCMS_SROM_PA5GLW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2,
832 0xffff},
833 {BRCMS_SROM_PA5GLW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3,
834 0xffff},
835 {BRCMS_SROM_PA5GHW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
836 {BRCMS_SROM_PA5GHW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1,
837 0xffff},
838 {BRCMS_SROM_PA5GHW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2,
839 0xffff},
840 {BRCMS_SROM_PA5GHW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3,
841 0xffff},
842 {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
843 {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
844 {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
845 {BRCMS_SROM_PA2GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
846 {BRCMS_SROM_PA2GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
847 {BRCMS_SROM_PA2GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
848 {BRCMS_SROM_MAXP5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
849 {BRCMS_SROM_MAXP5GHA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
850 {BRCMS_SROM_MAXP5GLA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
851 {BRCMS_SROM_PA5GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
852 {BRCMS_SROM_PA5GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
853 {BRCMS_SROM_PA5GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
854 {BRCMS_SROM_PA5GLW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
855 {BRCMS_SROM_PA5GLW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1,
856 0xffff},
857 {BRCMS_SROM_PA5GLW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2,
858 0xffff},
859 {BRCMS_SROM_PA5GHW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
860 {BRCMS_SROM_PA5GHW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1,
861 0xffff},
862 {BRCMS_SROM_PA5GHW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2,
863 0xffff},
864 {BRCMS_SROM_NULL, 0, 0, 0, 0}
865};
866
867/* crc table has the same contents for every device instance, so it can be
868 * shared between devices. */
869static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
870
871static u16 __iomem *
872srom_window_address(struct si_pub *sih, u8 __iomem *curmap)
873{
874 if (sih->ccrev < 32)
875 return (u16 __iomem *)(curmap + PCI_BAR0_SPROM_OFFSET);
876 if (sih->cccaps & CC_CAP_SROM)
877 return (u16 __iomem *)
878 (curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP);
879
880 return NULL;
881}
882
883/* Parse SROM and create name=value pairs. 'srom' points to
884 * the SROM word array. 'off' specifies the offset of the
885 * first word 'srom' points to, which should be either 0 or
886 * SROM3_SWRG_OFF (full SROM or software region).
887 */
888
889static uint mask_shift(u16 mask)
890{
891 uint i;
892 for (i = 0; i < (sizeof(mask) << 3); i++) {
893 if (mask & (1 << i))
894 return i;
895 }
896 return 0;
897}
898
899static uint mask_width(u16 mask)
900{
901 int i;
902 for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
903 if (mask & (1 << i))
904 return (uint) (i - mask_shift(mask) + 1);
905 }
906 return 0;
907}
908
909static inline void ltoh16_buf(u16 *buf, unsigned int size)
910{
911 size /= 2;
912 while (size--)
913 *(buf + size) = le16_to_cpu(*(__le16 *)(buf + size));
914}
915
916static inline void htol16_buf(u16 *buf, unsigned int size)
917{
918 size /= 2;
919 while (size--)
920 *(__le16 *)(buf + size) = cpu_to_le16(*(buf + size));
921}
922
923/*
924 * convert binary srom data into linked list of srom variable items.
925 */
926static void
927_initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
928{
929 struct brcms_srom_list_head *entry;
930 enum brcms_srom_id id;
931 u16 w;
932 u32 val;
933 const struct brcms_sromvar *srv;
934 uint width;
935 uint flags;
936 u32 sr = (1 << sromrev);
937
938 /* first store the srom revision */
939 entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL);
940 entry->varid = BRCMS_SROM_REV;
941 entry->var_type = BRCMS_SROM_UNUMBER;
942 entry->uval = sromrev;
943 list_add(&entry->var_list, var_list);
944
945 for (srv = pci_sromvars; srv->varid != BRCMS_SROM_NULL; srv++) {
946 enum brcms_srom_var_type type;
947 u8 ea[ETH_ALEN];
948 u8 extra_space = 0;
949
950 if ((srv->revmask & sr) == 0)
951 continue;
952
953 flags = srv->flags;
954 id = srv->varid;
955
956 /* This entry is for mfgc only. Don't generate param for it, */
957 if (flags & SRFL_NOVAR)
958 continue;
959
960 if (flags & SRFL_ETHADDR) {
961 /*
962 * stored in string format XX:XX:XX:XX:XX:XX (17 chars)
963 */
964 ea[0] = (srom[srv->off] >> 8) & 0xff;
965 ea[1] = srom[srv->off] & 0xff;
966 ea[2] = (srom[srv->off + 1] >> 8) & 0xff;
967 ea[3] = srom[srv->off + 1] & 0xff;
968 ea[4] = (srom[srv->off + 2] >> 8) & 0xff;
969 ea[5] = srom[srv->off + 2] & 0xff;
970 /* 17 characters + string terminator - union size */
971 extra_space = 18 - sizeof(s32);
972 type = BRCMS_SROM_STRING;
973 } else {
974 w = srom[srv->off];
975 val = (w & srv->mask) >> mask_shift(srv->mask);
976 width = mask_width(srv->mask);
977
978 while (srv->flags & SRFL_MORE) {
979 srv++;
980 if (srv->off == 0)
981 continue;
982
983 w = srom[srv->off];
984 val +=
985 ((w & srv->mask) >> mask_shift(srv->
986 mask)) <<
987 width;
988 width += mask_width(srv->mask);
989 }
990
991 if ((flags & SRFL_NOFFS)
992 && ((int)val == (1 << width) - 1))
993 continue;
994
995 if (flags & SRFL_CCODE) {
996 type = BRCMS_SROM_STRING;
997 } else if (flags & SRFL_LEDDC) {
998 /* LED Powersave duty cycle has to be scaled:
999 *(oncount >> 24) (offcount >> 8)
1000 */
1001 u32 w32 = /* oncount */
1002 (((val >> 8) & 0xff) << 24) |
1003 /* offcount */
1004 (((val & 0xff)) << 8);
1005 type = BRCMS_SROM_UNUMBER;
1006 val = w32;
1007 } else if ((flags & SRFL_PRSIGN)
1008 && (val & (1 << (width - 1)))) {
1009 type = BRCMS_SROM_SNUMBER;
1010 val |= ~0 << width;
1011 } else
1012 type = BRCMS_SROM_UNUMBER;
1013 }
1014
1015 entry = kzalloc(sizeof(struct brcms_srom_list_head) +
1016 extra_space, GFP_KERNEL);
1017 entry->varid = id;
1018 entry->var_type = type;
1019 if (flags & SRFL_ETHADDR) {
1020 snprintf(entry->buf, 18, "%pM", ea);
1021 } else if (flags & SRFL_CCODE) {
1022 if (val == 0)
1023 entry->buf[0] = '\0';
1024 else
1025 snprintf(entry->buf, 3, "%c%c",
1026 (val >> 8), (val & 0xff));
1027 } else {
1028 entry->uval = val;
1029 }
1030
1031 list_add(&entry->var_list, var_list);
1032 }
1033
1034 if (sromrev >= 4) {
1035 /* Do per-path variables */
1036 uint p, pb, psz;
1037
1038 if (sromrev >= 8) {
1039 pb = SROM8_PATH0;
1040 psz = SROM8_PATH1 - SROM8_PATH0;
1041 } else {
1042 pb = SROM4_PATH0;
1043 psz = SROM4_PATH1 - SROM4_PATH0;
1044 }
1045
1046 for (p = 0; p < MAX_PATH_SROM; p++) {
1047 for (srv = perpath_pci_sromvars;
1048 srv->varid != BRCMS_SROM_NULL; srv++) {
1049 if ((srv->revmask & sr) == 0)
1050 continue;
1051
1052 if (srv->flags & SRFL_NOVAR)
1053 continue;
1054
1055 w = srom[pb + srv->off];
1056 val = (w & srv->mask) >> mask_shift(srv->mask);
1057 width = mask_width(srv->mask);
1058
1059 /* Cheating: no per-path var is more than
1060 * 1 word */
1061 if ((srv->flags & SRFL_NOFFS)
1062 && ((int)val == (1 << width) - 1))
1063 continue;
1064
1065 entry =
1066 kzalloc(sizeof(struct brcms_srom_list_head),
1067 GFP_KERNEL);
1068 entry->varid = srv->varid+p;
1069 entry->var_type = BRCMS_SROM_UNUMBER;
1070 entry->uval = val;
1071 list_add(&entry->var_list, var_list);
1072 }
1073 pb += psz;
1074 }
1075 }
1076}
1077
1078/*
1079 * Read in and validate sprom.
1080 * Return 0 on success, nonzero on error.
1081 */
1082static int
1083sprom_read_pci(struct si_pub *sih, u16 __iomem *sprom, uint wordoff,
1084 u16 *buf, uint nwords, bool check_crc)
1085{
1086 int err = 0;
1087 uint i;
1088
1089 /* read the sprom */
1090 for (i = 0; i < nwords; i++)
1091 buf[i] = R_REG(&sprom[wordoff + i]);
1092
1093 if (check_crc) {
1094
1095 if (buf[0] == 0xffff)
1096 /*
1097 * The hardware thinks that an srom that starts with
1098 * 0xffff is blank, regardless of the rest of the
1099 * content, so declare it bad.
1100 */
1101 return -ENODATA;
1102
1103 /* fixup the endianness so crc8 will pass */
1104 htol16_buf(buf, nwords * 2);
1105 if (crc8(brcms_srom_crc8_table, (u8 *) buf, nwords * 2,
1106 CRC8_INIT_VALUE) !=
1107 CRC8_GOOD_VALUE(brcms_srom_crc8_table))
1108 /* DBG only pci always read srom4 first, then srom8/9 */
1109 err = -EIO;
1110
1111 /* now correct the endianness of the byte array */
1112 ltoh16_buf(buf, nwords * 2);
1113 }
1114 return err;
1115}
1116
1117static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
1118{
1119 u8 *otp;
1120 uint sz = OTP_SZ_MAX / 2; /* size in words */
1121 int err = 0;
1122
1123 otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
1124 if (otp == NULL)
1125 return -ENOMEM;
1126
1127 err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
1128
1129 memcpy(buf, otp, bufsz);
1130
1131 kfree(otp);
1132
1133 /* Check CRC */
1134 if (buf[0] == 0xffff)
1135 /* The hardware thinks that an srom that starts with 0xffff
1136 * is blank, regardless of the rest of the content, so declare
1137 * it bad.
1138 */
1139 return -ENODATA;
1140
1141 /* fixup the endianness so crc8 will pass */
1142 htol16_buf(buf, bufsz);
1143 if (crc8(brcms_srom_crc8_table, (u8 *) buf, SROM4_WORDS * 2,
1144 CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(brcms_srom_crc8_table))
1145 err = -EIO;
1146
1147 /* now correct the endianness of the byte array */
1148 ltoh16_buf(buf, bufsz);
1149
1150 return err;
1151}
1152
1153/*
1154 * Initialize nonvolatile variable table from sprom.
1155 * Return 0 on success, nonzero on error.
1156 */
1157static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1158{
1159 u16 *srom;
1160 u16 __iomem *sromwindow;
1161 u8 sromrev = 0;
1162 u32 sr;
1163 int err = 0;
1164
1165 /*
1166 * Apply CRC over SROM content regardless SROM is present or not.
1167 */
1168 srom = kmalloc(SROM_MAX, GFP_ATOMIC);
1169 if (!srom)
1170 return -ENOMEM;
1171
1172 sromwindow = srom_window_address(sih, curmap);
1173
1174 crc8_populate_lsb(brcms_srom_crc8_table, SROM_CRC8_POLY);
1175 if (ai_is_sprom_available(sih)) {
1176 err = sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
1177 true);
1178
1179 if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
1180 (((sih->buscoretype == PCIE_CORE_ID)
1181 && (sih->buscorerev >= 6))
1182 || ((sih->buscoretype == PCI_CORE_ID)
1183 && (sih->buscorerev >= 0xe)))) {
1184 /* sromrev >= 4, read more */
1185 err = sprom_read_pci(sih, sromwindow, 0, srom,
1186 SROM4_WORDS, true);
1187 sromrev = srom[SROM4_CRCREV] & 0xff;
1188 } else if (err == 0) {
1189 /* srom is good and is rev < 4 */
1190 /* top word of sprom contains version and crc8 */
1191 sromrev = srom[SROM_CRCREV] & 0xff;
1192 /* bcm4401 sroms misprogrammed */
1193 if (sromrev == 0x10)
1194 sromrev = 1;
1195 }
1196 } else {
1197 /* Use OTP if SPROM not available */
1198 err = otp_read_pci(sih, srom, SROM_MAX);
1199 if (err == 0)
1200 /* OTP only contain SROM rev8/rev9 for now */
1201 sromrev = srom[SROM4_CRCREV] & 0xff;
1202 }
1203
1204 if (!err) {
1205 struct si_info *sii = (struct si_info *)sih;
1206
1207 /* Bitmask for the sromrev */
1208 sr = 1 << sromrev;
1209
1210 /*
1211 * srom version check: Current valid versions: 1, 2, 3, 4, 5, 8,
1212 * 9
1213 */
1214 if ((sr & 0x33e) == 0) {
1215 err = -EINVAL;
1216 goto errout;
1217 }
1218
1219 INIT_LIST_HEAD(&sii->var_list);
1220
1221 /* parse SROM into name=value pairs. */
1222 _initvars_srom_pci(sromrev, srom, &sii->var_list);
1223 }
1224
1225errout:
1226 kfree(srom);
1227 return err;
1228}
1229
1230void srom_free_vars(struct si_pub *sih)
1231{
1232 struct si_info *sii;
1233 struct brcms_srom_list_head *entry, *next;
1234
1235 sii = (struct si_info *)sih;
1236 list_for_each_entry_safe(entry, next, &sii->var_list, var_list) {
1237 list_del(&entry->var_list);
1238 kfree(entry);
1239 }
1240}
1241/*
1242 * Initialize local vars from the right source for this platform.
1243 * Return 0 on success, nonzero on error.
1244 */
1245int srom_var_init(struct si_pub *sih, void __iomem *curmap)
1246{
1247 uint len;
1248
1249 len = 0;
1250
1251 if (curmap != NULL)
1252 return initvars_srom_pci(sih, curmap);
1253
1254 return -EINVAL;
1255}
1256
1257/*
1258 * Search the name=value vars for a specific one and return its value.
1259 * Returns NULL if not found.
1260 */
1261char *getvar(struct si_pub *sih, enum brcms_srom_id id)
1262{
1263 struct si_info *sii;
1264 struct brcms_srom_list_head *entry;
1265
1266 sii = (struct si_info *)sih;
1267
1268 list_for_each_entry(entry, &sii->var_list, var_list)
1269 if (entry->varid == id)
1270 return &entry->buf[0];
1271
1272 /* nothing found */
1273 return NULL;
1274}
1275
1276/*
1277 * Search the vars for a specific one and return its value as
1278 * an integer. Returns 0 if not found.-
1279 */
1280int getintvar(struct si_pub *sih, enum brcms_srom_id id)
1281{
1282 struct si_info *sii;
1283 struct brcms_srom_list_head *entry;
1284 unsigned long res;
1285
1286 sii = (struct si_info *)sih;
1287
1288 list_for_each_entry(entry, &sii->var_list, var_list)
1289 if (entry->varid == id) {
1290 if (entry->var_type == BRCMS_SROM_SNUMBER ||
1291 entry->var_type == BRCMS_SROM_UNUMBER)
1292 return (int)entry->sval;
1293 else if (!kstrtoul(&entry->buf[0], 0, &res))
1294 return (int)res;
1295 }
1296
1297 return 0;
1298}
diff --git a/drivers/staging/brcm80211/brcmsmac/srom.h b/drivers/staging/brcm80211/brcmsmac/srom.h
deleted file mode 100644
index 708c43ff51c..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/srom.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_SROM_H_
18#define _BRCM_SROM_H_
19
20#include "types.h"
21
22/* Prototypes */
23extern int srom_var_init(struct si_pub *sih, void __iomem *curmap);
24extern void srom_free_vars(struct si_pub *sih);
25
26extern int srom_read(struct si_pub *sih, uint bus, void *curmap,
27 uint byteoff, uint nbytes, u16 *buf, bool check_crc);
28
29/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
30 * and extract from it into name=value pairs
31 */
32extern int srom_parsecis(u8 **pcis, uint ciscnt,
33 char **vars, uint *count);
34#endif /* _BRCM_SROM_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/stf.c b/drivers/staging/brcm80211/brcmsmac/stf.c
deleted file mode 100644
index f1bd1bf5485..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/stf.c
+++ /dev/null
@@ -1,438 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <net/mac80211.h>
18
19#include "types.h"
20#include "d11.h"
21#include "rate.h"
22#include "phy/phy_hal.h"
23#include "channel.h"
24#include "main.h"
25#include "stf.h"
26
27#define MIN_SPATIAL_EXPANSION 0
28#define MAX_SPATIAL_EXPANSION 1
29
30#define BRCMS_STF_SS_STBC_RX(wlc) (BRCMS_ISNPHY(wlc->band) && \
31 NREV_GT(wlc->band->phyrev, 3) && NREV_LE(wlc->band->phyrev, 6))
32
33#define BRCMS_BITSCNT(x) brcmu_bitcount((u8 *)&(x), sizeof(u8))
34
35#define NSTS_1 1
36#define NSTS_2 2
37#define NSTS_3 3
38#define NSTS_4 4
39
40static const u8 txcore_default[5] = {
41 (0), /* bitmap of the core enabled */
42 (0x01), /* For Nsts = 1, enable core 1 */
43 (0x03), /* For Nsts = 2, enable core 1 & 2 */
44 (0x07), /* For Nsts = 3, enable core 1, 2 & 3 */
45 (0x0f) /* For Nsts = 4, enable all cores */
46};
47
48static void brcms_c_stf_stbc_rx_ht_update(struct brcms_c_info *wlc, int val)
49{
50 /* MIMOPHYs rev3-6 cannot receive STBC with only one rx core active */
51 if (BRCMS_STF_SS_STBC_RX(wlc)) {
52 if ((wlc->stf->rxstreams == 1) && (val != HT_CAP_RX_STBC_NO))
53 return;
54 }
55
56 if (wlc->pub->up) {
57 brcms_c_update_beacon(wlc);
58 brcms_c_update_probe_resp(wlc, true);
59 }
60}
61
62/*
63 * every WLC_TEMPSENSE_PERIOD seconds temperature check to decide whether to
64 * turn on/off txchain.
65 */
66void brcms_c_tempsense_upd(struct brcms_c_info *wlc)
67{
68 struct brcms_phy_pub *pi = wlc->band->pi;
69 uint active_chains, txchain;
70
71 /* Check if the chip is too hot. Disable one Tx chain, if it is */
72 /* high 4 bits are for Rx chain, low 4 bits are for Tx chain */
73 active_chains = wlc_phy_stf_chain_active_get(pi);
74 txchain = active_chains & 0xf;
75
76 if (wlc->stf->txchain == wlc->stf->hw_txchain) {
77 if (txchain && (txchain < wlc->stf->hw_txchain))
78 /* turn off 1 tx chain */
79 brcms_c_stf_txchain_set(wlc, txchain, true);
80 } else if (wlc->stf->txchain < wlc->stf->hw_txchain) {
81 if (txchain == wlc->stf->hw_txchain)
82 /* turn back on txchain */
83 brcms_c_stf_txchain_set(wlc, txchain, true);
84 }
85}
86
87void
88brcms_c_stf_ss_algo_channel_get(struct brcms_c_info *wlc, u16 *ss_algo_channel,
89 u16 chanspec)
90{
91 struct tx_power power;
92 u8 siso_mcs_id, cdd_mcs_id, stbc_mcs_id;
93
94 /* Clear previous settings */
95 *ss_algo_channel = 0;
96
97 if (!wlc->pub->up) {
98 *ss_algo_channel = (u16) -1;
99 return;
100 }
101
102 wlc_phy_txpower_get_current(wlc->band->pi, &power,
103 CHSPEC_CHANNEL(chanspec));
104
105 siso_mcs_id = (CHSPEC_IS40(chanspec)) ?
106 WL_TX_POWER_MCS40_SISO_FIRST : WL_TX_POWER_MCS20_SISO_FIRST;
107 cdd_mcs_id = (CHSPEC_IS40(chanspec)) ?
108 WL_TX_POWER_MCS40_CDD_FIRST : WL_TX_POWER_MCS20_CDD_FIRST;
109 stbc_mcs_id = (CHSPEC_IS40(chanspec)) ?
110 WL_TX_POWER_MCS40_STBC_FIRST : WL_TX_POWER_MCS20_STBC_FIRST;
111
112 /* criteria to choose stf mode */
113
114 /*
115 * the "+3dbm (12 0.25db units)" is to account for the fact that with
116 * CDD, tx occurs on both chains
117 */
118 if (power.target[siso_mcs_id] > (power.target[cdd_mcs_id] + 12))
119 setbit(ss_algo_channel, PHY_TXC1_MODE_SISO);
120 else
121 setbit(ss_algo_channel, PHY_TXC1_MODE_CDD);
122
123 /*
124 * STBC is ORed into to algo channel as STBC requires per-packet SCB
125 * capability check so cannot be default mode of operation. One of
126 * SISO, CDD have to be set
127 */
128 if (power.target[siso_mcs_id] <= (power.target[stbc_mcs_id] + 12))
129 setbit(ss_algo_channel, PHY_TXC1_MODE_STBC);
130}
131
132static bool brcms_c_stf_stbc_tx_set(struct brcms_c_info *wlc, s32 int_val)
133{
134 if ((int_val != AUTO) && (int_val != OFF) && (int_val != ON))
135 return false;
136
137 if ((int_val == ON) && (wlc->stf->txstreams == 1))
138 return false;
139
140 wlc->bandstate[BAND_2G_INDEX]->band_stf_stbc_tx = (s8) int_val;
141 wlc->bandstate[BAND_5G_INDEX]->band_stf_stbc_tx = (s8) int_val;
142
143 return true;
144}
145
146bool brcms_c_stf_stbc_rx_set(struct brcms_c_info *wlc, s32 int_val)
147{
148 if ((int_val != HT_CAP_RX_STBC_NO)
149 && (int_val != HT_CAP_RX_STBC_ONE_STREAM))
150 return false;
151
152 if (BRCMS_STF_SS_STBC_RX(wlc)) {
153 if ((int_val != HT_CAP_RX_STBC_NO)
154 && (wlc->stf->rxstreams == 1))
155 return false;
156 }
157
158 brcms_c_stf_stbc_rx_ht_update(wlc, int_val);
159 return true;
160}
161
162static int brcms_c_stf_txcore_set(struct brcms_c_info *wlc, u8 Nsts,
163 u8 core_mask)
164{
165 BCMMSG(wlc->wiphy, "wl%d: Nsts %d core_mask %x\n",
166 wlc->pub->unit, Nsts, core_mask);
167
168 if (hweight8(core_mask) > wlc->stf->txstreams)
169 core_mask = 0;
170
171 if ((hweight8(core_mask) == wlc->stf->txstreams) &&
172 ((core_mask & ~wlc->stf->txchain)
173 || !(core_mask & wlc->stf->txchain)))
174 core_mask = wlc->stf->txchain;
175
176 wlc->stf->txcore[Nsts] = core_mask;
177 /* Nsts = 1..4, txcore index = 1..4 */
178 if (Nsts == 1) {
179 /* Needs to update beacon and ucode generated response
180 * frames when 1 stream core map changed
181 */
182 wlc->stf->phytxant = core_mask << PHY_TXC_ANT_SHIFT;
183 brcms_b_txant_set(wlc->hw, wlc->stf->phytxant);
184 if (wlc->clk) {
185 brcms_c_suspend_mac_and_wait(wlc);
186 brcms_c_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec);
187 brcms_c_enable_mac(wlc);
188 }
189 }
190
191 return 0;
192}
193
194static int brcms_c_stf_spatial_policy_set(struct brcms_c_info *wlc, int val)
195{
196 int i;
197 u8 core_mask = 0;
198
199 BCMMSG(wlc->wiphy, "wl%d: val %x\n", wlc->pub->unit, val);
200
201 wlc->stf->spatial_policy = (s8) val;
202 for (i = 1; i <= MAX_STREAMS_SUPPORTED; i++) {
203 core_mask = (val == MAX_SPATIAL_EXPANSION) ?
204 wlc->stf->txchain : txcore_default[i];
205 brcms_c_stf_txcore_set(wlc, (u8) i, core_mask);
206 }
207 return 0;
208}
209
210/*
211 * Centralized txant update function. call it whenever wlc->stf->txant and/or
212 * wlc->stf->txchain change.
213 *
214 * Antennas are controlled by ucode indirectly, which drives PHY or GPIO to
215 * achieve various tx/rx antenna selection schemes
216 *
217 * legacy phy, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7
218 * means auto(last rx).
219 * for NREV<3, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7
220 * means last rx and do tx-antenna selection for SISO transmissions
221 * for NREV=3, bit 6 and bit _8_ means antenna 0 and 1 respectively, bit6+bit7
222 * means last rx and do tx-antenna selection for SISO transmissions
223 * for NREV>=7, bit 6 and bit 7 mean antenna 0 and 1 respectively, nit6+bit7
224 * means both cores active
225*/
226static void _brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc)
227{
228 s8 txant;
229
230 txant = (s8) wlc->stf->txant;
231 if (BRCMS_PHY_11N_CAP(wlc->band)) {
232 if (txant == ANT_TX_FORCE_0) {
233 wlc->stf->phytxant = PHY_TXC_ANT_0;
234 } else if (txant == ANT_TX_FORCE_1) {
235 wlc->stf->phytxant = PHY_TXC_ANT_1;
236
237 if (BRCMS_ISNPHY(wlc->band) &&
238 NREV_GE(wlc->band->phyrev, 3)
239 && NREV_LT(wlc->band->phyrev, 7))
240 wlc->stf->phytxant = PHY_TXC_ANT_2;
241 } else {
242 if (BRCMS_ISLCNPHY(wlc->band) ||
243 BRCMS_ISSSLPNPHY(wlc->band))
244 wlc->stf->phytxant = PHY_TXC_LCNPHY_ANT_LAST;
245 else {
246 /* catch out of sync wlc->stf->txcore */
247 WARN_ON(wlc->stf->txchain <= 0);
248 wlc->stf->phytxant =
249 wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
250 }
251 }
252 } else {
253 if (txant == ANT_TX_FORCE_0)
254 wlc->stf->phytxant = PHY_TXC_OLD_ANT_0;
255 else if (txant == ANT_TX_FORCE_1)
256 wlc->stf->phytxant = PHY_TXC_OLD_ANT_1;
257 else
258 wlc->stf->phytxant = PHY_TXC_OLD_ANT_LAST;
259 }
260
261 brcms_b_txant_set(wlc->hw, wlc->stf->phytxant);
262}
263
264int brcms_c_stf_txchain_set(struct brcms_c_info *wlc, s32 int_val, bool force)
265{
266 u8 txchain = (u8) int_val;
267 u8 txstreams;
268 uint i;
269
270 if (wlc->stf->txchain == txchain)
271 return 0;
272
273 if ((txchain & ~wlc->stf->hw_txchain)
274 || !(txchain & wlc->stf->hw_txchain))
275 return -EINVAL;
276
277 /*
278 * if nrate override is configured to be non-SISO STF mode, reject
279 * reducing txchain to 1
280 */
281 txstreams = (u8) hweight8(txchain);
282 if (txstreams > MAX_STREAMS_SUPPORTED)
283 return -EINVAL;
284
285 wlc->stf->txchain = txchain;
286 wlc->stf->txstreams = txstreams;
287 brcms_c_stf_stbc_tx_set(wlc, wlc->band->band_stf_stbc_tx);
288 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
289 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
290 wlc->stf->txant =
291 (wlc->stf->txstreams == 1) ? ANT_TX_FORCE_0 : ANT_TX_DEF;
292 _brcms_c_stf_phy_txant_upd(wlc);
293
294 wlc_phy_stf_chain_set(wlc->band->pi, wlc->stf->txchain,
295 wlc->stf->rxchain);
296
297 for (i = 1; i <= MAX_STREAMS_SUPPORTED; i++)
298 brcms_c_stf_txcore_set(wlc, (u8) i, txcore_default[i]);
299
300 return 0;
301}
302
303/*
304 * update wlc->stf->ss_opmode which represents the operational stf_ss mode
305 * we're using
306 */
307int brcms_c_stf_ss_update(struct brcms_c_info *wlc, struct brcms_band *band)
308{
309 int ret_code = 0;
310 u8 prev_stf_ss;
311 u8 upd_stf_ss;
312
313 prev_stf_ss = wlc->stf->ss_opmode;
314
315 /*
316 * NOTE: opmode can only be SISO or CDD as STBC is decided on a
317 * per-packet basis
318 */
319 if (BRCMS_STBC_CAP_PHY(wlc) &&
320 wlc->stf->ss_algosel_auto
321 && (wlc->stf->ss_algo_channel != (u16) -1)) {
322 upd_stf_ss = (wlc->stf->txstreams == 1 ||
323 isset(&wlc->stf->ss_algo_channel,
324 PHY_TXC1_MODE_SISO)) ?
325 PHY_TXC1_MODE_SISO : PHY_TXC1_MODE_CDD;
326 } else {
327 if (wlc->band != band)
328 return ret_code;
329 upd_stf_ss = (wlc->stf->txstreams == 1) ?
330 PHY_TXC1_MODE_SISO : band->band_stf_ss_mode;
331 }
332 if (prev_stf_ss != upd_stf_ss) {
333 wlc->stf->ss_opmode = upd_stf_ss;
334 brcms_b_band_stf_ss_set(wlc->hw, upd_stf_ss);
335 }
336
337 return ret_code;
338}
339
340int brcms_c_stf_attach(struct brcms_c_info *wlc)
341{
342 wlc->bandstate[BAND_2G_INDEX]->band_stf_ss_mode = PHY_TXC1_MODE_SISO;
343 wlc->bandstate[BAND_5G_INDEX]->band_stf_ss_mode = PHY_TXC1_MODE_CDD;
344
345 if (BRCMS_ISNPHY(wlc->band) &&
346 (wlc_phy_txpower_hw_ctrl_get(wlc->band->pi) != PHY_TPC_HW_ON))
347 wlc->bandstate[BAND_2G_INDEX]->band_stf_ss_mode =
348 PHY_TXC1_MODE_CDD;
349 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
350 brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
351
352 brcms_c_stf_stbc_rx_ht_update(wlc, HT_CAP_RX_STBC_NO);
353 wlc->bandstate[BAND_2G_INDEX]->band_stf_stbc_tx = OFF;
354 wlc->bandstate[BAND_5G_INDEX]->band_stf_stbc_tx = OFF;
355
356 if (BRCMS_STBC_CAP_PHY(wlc)) {
357 wlc->stf->ss_algosel_auto = true;
358 /* Init the default value */
359 wlc->stf->ss_algo_channel = (u16) -1;
360 }
361 return 0;
362}
363
364void brcms_c_stf_detach(struct brcms_c_info *wlc)
365{
366}
367
368void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc)
369{
370 _brcms_c_stf_phy_txant_upd(wlc);
371}
372
373void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc)
374{
375 /* get available rx/tx chains */
376 wlc->stf->hw_txchain = (u8) getintvar(wlc->hw->sih, BRCMS_SROM_TXCHAIN);
377 wlc->stf->hw_rxchain = (u8) getintvar(wlc->hw->sih, BRCMS_SROM_RXCHAIN);
378
379 /* these parameter are intended to be used for all PHY types */
380 if (wlc->stf->hw_txchain == 0 || wlc->stf->hw_txchain == 0xf) {
381 if (BRCMS_ISNPHY(wlc->band))
382 wlc->stf->hw_txchain = TXCHAIN_DEF_NPHY;
383 else
384 wlc->stf->hw_txchain = TXCHAIN_DEF;
385 }
386
387 wlc->stf->txchain = wlc->stf->hw_txchain;
388 wlc->stf->txstreams = (u8) hweight8(wlc->stf->hw_txchain);
389
390 if (wlc->stf->hw_rxchain == 0 || wlc->stf->hw_rxchain == 0xf) {
391 if (BRCMS_ISNPHY(wlc->band))
392 wlc->stf->hw_rxchain = RXCHAIN_DEF_NPHY;
393 else
394 wlc->stf->hw_rxchain = RXCHAIN_DEF;
395 }
396
397 wlc->stf->rxchain = wlc->stf->hw_rxchain;
398 wlc->stf->rxstreams = (u8) hweight8(wlc->stf->hw_rxchain);
399
400 /* initialize the txcore table */
401 memcpy(wlc->stf->txcore, txcore_default, sizeof(wlc->stf->txcore));
402
403 /* default spatial_policy */
404 wlc->stf->spatial_policy = MIN_SPATIAL_EXPANSION;
405 brcms_c_stf_spatial_policy_set(wlc, MIN_SPATIAL_EXPANSION);
406}
407
408static u16 _brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc,
409 u32 rspec)
410{
411 u16 phytxant = wlc->stf->phytxant;
412
413 if (rspec_stf(rspec) != PHY_TXC1_MODE_SISO)
414 phytxant = wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
415 else if (wlc->stf->txant == ANT_TX_DEF)
416 phytxant = wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
417 phytxant &= PHY_TXC_ANT_MASK;
418 return phytxant;
419}
420
421u16 brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc, u32 rspec)
422{
423 return _brcms_c_stf_phytxchain_sel(wlc, rspec);
424}
425
426u16 brcms_c_stf_d11hdrs_phyctl_txant(struct brcms_c_info *wlc, u32 rspec)
427{
428 u16 phytxant = wlc->stf->phytxant;
429 u16 mask = PHY_TXC_ANT_MASK;
430
431 /* for non-siso rates or default setting, use the available chains */
432 if (BRCMS_ISNPHY(wlc->band)) {
433 phytxant = _brcms_c_stf_phytxchain_sel(wlc, rspec);
434 mask = PHY_TXC_HTANT_MASK;
435 }
436 phytxant |= phytxant & mask;
437 return phytxant;
438}
diff --git a/drivers/staging/brcm80211/brcmsmac/stf.h b/drivers/staging/brcm80211/brcmsmac/stf.h
deleted file mode 100644
index 19f6580f69b..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/stf.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_STF_H_
18#define _BRCM_STF_H_
19
20#include "types.h"
21
22extern int brcms_c_stf_attach(struct brcms_c_info *wlc);
23extern void brcms_c_stf_detach(struct brcms_c_info *wlc);
24
25extern void brcms_c_tempsense_upd(struct brcms_c_info *wlc);
26extern void brcms_c_stf_ss_algo_channel_get(struct brcms_c_info *wlc,
27 u16 *ss_algo_channel,
28 u16 chanspec);
29extern int brcms_c_stf_ss_update(struct brcms_c_info *wlc,
30 struct brcms_band *band);
31extern void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc);
32extern int brcms_c_stf_txchain_set(struct brcms_c_info *wlc, s32 int_val,
33 bool force);
34extern bool brcms_c_stf_stbc_rx_set(struct brcms_c_info *wlc, s32 int_val);
35extern void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc);
36extern void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc);
37extern u16 brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc,
38 u32 rspec);
39extern u16 brcms_c_stf_d11hdrs_phyctl_txant(struct brcms_c_info *wlc,
40 u32 rspec);
41
42#endif /* _BRCM_STF_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/types.h b/drivers/staging/brcm80211/brcmsmac/types.h
deleted file mode 100644
index 27a814b0746..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/types.h
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_TYPES_H_
18#define _BRCM_TYPES_H_
19
20#include <linux/types.h>
21#include <linux/io.h>
22
23#define WL_CHAN_FREQ_RANGE_2G 0
24#define WL_CHAN_FREQ_RANGE_5GL 1
25#define WL_CHAN_FREQ_RANGE_5GM 2
26#define WL_CHAN_FREQ_RANGE_5GH 3
27
28/* boardflags */
29
30/* Board has gpio 9 controlling the PA */
31#define BFL_PACTRL 0x00000002
32/* Not ok to power down the chip pll and oscillator */
33#define BFL_NOPLLDOWN 0x00000020
34/* Board supports the Front End Module */
35#define BFL_FEM 0x00000800
36/* Board has an external LNA in 2.4GHz band */
37#define BFL_EXTLNA 0x00001000
38/* Board has no PA */
39#define BFL_NOPA 0x00010000
40/* Power topology uses BUCKBOOST */
41#define BFL_BUCKBOOST 0x00200000
42/* Board has FEM and switch to share antenna w/ BT */
43#define BFL_FEM_BT 0x00400000
44/* Power topology doesn't use CBUCK */
45#define BFL_NOCBUCK 0x00800000
46/* Power topology uses PALDO */
47#define BFL_PALDO 0x02000000
48/* Board has an external LNA in 5GHz band */
49#define BFL_EXTLNA_5GHz 0x10000000
50
51/* boardflags2 */
52
53/* Board has an external rxbb regulator */
54#define BFL2_RXBB_INT_REG_DIS 0x00000001
55/* Flag to implement alternative A-band PLL settings */
56#define BFL2_APLL_WAR 0x00000002
57/* Board permits enabling TX Power Control */
58#define BFL2_TXPWRCTRL_EN 0x00000004
59/* Board supports the 2X4 diversity switch */
60#define BFL2_2X4_DIV 0x00000008
61/* Board supports 5G band power gain */
62#define BFL2_5G_PWRGAIN 0x00000010
63/* Board overrides ASPM and Clkreq settings */
64#define BFL2_PCIEWAR_OVR 0x00000020
65#define BFL2_LEGACY 0x00000080
66/* 4321mcm93 board uses Skyworks FEM */
67#define BFL2_SKWRKFEM_BRD 0x00000100
68/* Board has a WAR for clock-harmonic spurs */
69#define BFL2_SPUR_WAR 0x00000200
70/* Flag to narrow G-band PLL loop b/w */
71#define BFL2_GPLL_WAR 0x00000400
72/* Tx CCK pkts on Ant 0 only */
73#define BFL2_SINGLEANT_CCK 0x00001000
74/* WAR to reduce and avoid clock-harmonic spurs in 2G */
75#define BFL2_2G_SPUR_WAR 0x00002000
76/* Flag to widen G-band PLL loop b/w */
77#define BFL2_GPLL_WAR2 0x00010000
78#define BFL2_IPALVLSHIFT_3P3 0x00020000
79/* Use internal envelope detector for TX IQCAL */
80#define BFL2_INTERNDET_TXIQCAL 0x00040000
81/* Keep the buffered Xtal output from radio "ON". Most drivers will turn it
82 * off without this flag to save power. */
83#define BFL2_XTALBUFOUTEN 0x00080000
84
85/*
86 * board specific GPIO assignment, gpio 0-3 are also customer-configurable
87 * led
88 */
89
90/* bit 9 controls the PA on new 4306 boards */
91#define BOARD_GPIO_PACTRL 0x200
92#define BOARD_GPIO_12 0x1000
93#define BOARD_GPIO_13 0x2000
94
95/* **** Core type/rev defaults **** */
96#define D11CONF 0x0fffffb0 /* Supported D11 revs: 4, 5, 7-27
97 * also need to update wlc.h MAXCOREREV
98 */
99
100#define NCONF 0x000001ff /* Supported nphy revs:
101 * 0 4321a0
102 * 1 4321a1
103 * 2 4321b0/b1/c0/c1
104 * 3 4322a0
105 * 4 4322a1
106 * 5 4716a0
107 * 6 43222a0, 43224a0
108 * 7 43226a0
109 * 8 5357a0, 43236a0
110 */
111
112#define LCNCONF 0x00000007 /* Supported lcnphy revs:
113 * 0 4313a0, 4336a0, 4330a0
114 * 1
115 * 2 4330a0
116 */
117
118#define SSLPNCONF 0x0000000f /* Supported sslpnphy revs:
119 * 0 4329a0/k0
120 * 1 4329b0/4329C0
121 * 2 4319a0
122 * 3 5356a0
123 */
124
125/********************************************************************
126 * Phy/Core Configuration. Defines macros to to check core phy/rev *
127 * compile-time configuration. Defines default core support. *
128 * ******************************************************************
129 */
130
131/* Basic macros to check a configuration bitmask */
132
133#define CONF_HAS(config, val) ((config) & (1 << (val)))
134#define CONF_MSK(config, mask) ((config) & (mask))
135#define MSK_RANGE(low, hi) ((1 << ((hi)+1)) - (1 << (low)))
136#define CONF_RANGE(config, low, hi) (CONF_MSK(config, MSK_RANGE(low, high)))
137
138#define CONF_IS(config, val) ((config) == (1 << (val)))
139#define CONF_GE(config, val) ((config) & (0-(1 << (val))))
140#define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
141#define CONF_LT(config, val) ((config) & ((1 << (val))-1))
142#define CONF_LE(config, val) ((config) & (2*(1 << (val))-1))
143
144/* Wrappers for some of the above, specific to config constants */
145
146#define NCONF_HAS(val) CONF_HAS(NCONF, val)
147#define NCONF_MSK(mask) CONF_MSK(NCONF, mask)
148#define NCONF_IS(val) CONF_IS(NCONF, val)
149#define NCONF_GE(val) CONF_GE(NCONF, val)
150#define NCONF_GT(val) CONF_GT(NCONF, val)
151#define NCONF_LT(val) CONF_LT(NCONF, val)
152#define NCONF_LE(val) CONF_LE(NCONF, val)
153
154#define LCNCONF_HAS(val) CONF_HAS(LCNCONF, val)
155#define LCNCONF_MSK(mask) CONF_MSK(LCNCONF, mask)
156#define LCNCONF_IS(val) CONF_IS(LCNCONF, val)
157#define LCNCONF_GE(val) CONF_GE(LCNCONF, val)
158#define LCNCONF_GT(val) CONF_GT(LCNCONF, val)
159#define LCNCONF_LT(val) CONF_LT(LCNCONF, val)
160#define LCNCONF_LE(val) CONF_LE(LCNCONF, val)
161
162#define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
163#define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask)
164#define D11CONF_IS(val) CONF_IS(D11CONF, val)
165#define D11CONF_GE(val) CONF_GE(D11CONF, val)
166#define D11CONF_GT(val) CONF_GT(D11CONF, val)
167#define D11CONF_LT(val) CONF_LT(D11CONF, val)
168#define D11CONF_LE(val) CONF_LE(D11CONF, val)
169
170#define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
171#define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
172
173#define NREV_IS(var, val) \
174 (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
175
176#define NREV_GE(var, val) \
177 (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
178
179#define NREV_GT(var, val) \
180 (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
181
182#define NREV_LT(var, val) \
183 (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
184
185#define NREV_LE(var, val) \
186 (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
187
188#define LCNREV_IS(var, val) \
189 (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
190
191#define LCNREV_GE(var, val) \
192 (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
193
194#define LCNREV_GT(var, val) \
195 (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
196
197#define LCNREV_LT(var, val) \
198 (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
199
200#define LCNREV_LE(var, val) \
201 (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
202
203#define D11REV_IS(var, val) \
204 (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
205
206#define D11REV_GE(var, val) \
207 (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
208
209#define D11REV_GT(var, val) \
210 (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
211
212#define D11REV_LT(var, val) \
213 (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
214
215#define D11REV_LE(var, val) \
216 (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
217
218#define PHYTYPE_IS(var, val)\
219 (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
220
221/* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
222
223#define _PHYCONF_N (1 << PHY_TYPE_N)
224#define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
225#define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
226
227#define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
228
229/* Utility macro to identify 802.11n (HT) capable PHYs */
230#define PHYTYPE_11N_CAP(phytype) \
231 (PHYTYPE_IS(phytype, PHY_TYPE_N) || \
232 PHYTYPE_IS(phytype, PHY_TYPE_LCN) || \
233 PHYTYPE_IS(phytype, PHY_TYPE_SSN))
234
235/* Last but not least: shorter wlc-specific var checks */
236#define BRCMS_ISNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_N)
237#define BRCMS_ISLCNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_LCN)
238#define BRCMS_ISSSLPNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_SSN)
239
240#define BRCMS_PHY_11N_CAP(band) PHYTYPE_11N_CAP((band)->phytype)
241
242/**********************************************************************
243 * ------------- End of Core phy/rev configuration. ----------------- *
244 * ********************************************************************
245 */
246
247#define BCMMSG(dev, fmt, args...) \
248do { \
249 if (brcm_msg_level & LOG_TRACE_VAL) \
250 wiphy_err(dev, "%s: " fmt, __func__, ##args); \
251} while (0)
252
253/*
254 * Register access macros.
255 *
256 * These macro's take a pointer to the address to read as one of their
257 * arguments. The macro itself deduces the size of the IO transaction (u8, u16
258 * or u32). Advantage of this approach in combination with using a struct to
259 * define the registers in a register block, is that access size and access
260 * location are defined in only one spot. This reduces the risk of the
261 * programmer trying to use an unsupported transaction size on a register.
262 *
263 */
264
265#define R_REG(r) \
266 ({ \
267 __typeof(*(r)) __osl_v; \
268 switch (sizeof(*(r))) { \
269 case sizeof(u8): \
270 __osl_v = readb((u8 __iomem *)(r)); \
271 break; \
272 case sizeof(u16): \
273 __osl_v = readw((u16 __iomem *)(r)); \
274 break; \
275 case sizeof(u32): \
276 __osl_v = readl((u32 __iomem *)(r)); \
277 break; \
278 } \
279 __osl_v; \
280 })
281
282#define W_REG(r, v) do { \
283 switch (sizeof(*(r))) { \
284 case sizeof(u8): \
285 writeb((u8)((v) & 0xFF), (u8 __iomem *)(r)); \
286 break; \
287 case sizeof(u16): \
288 writew((u16)((v) & 0xFFFF), (u16 __iomem *)(r)); \
289 break; \
290 case sizeof(u32): \
291 writel((u32)(v), (u32 __iomem *)(r)); \
292 break; \
293 } \
294 } while (0)
295
296#ifdef CONFIG_BCM47XX
297/*
298 * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
299 * transactions. As a fix, a read after write is performed on certain places
300 * in the code. Older chips and the newer 5357 family don't require this fix.
301 */
302#define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); })
303#else
304#define W_REG_FLUSH(r, v) W_REG((r), (v))
305#endif /* CONFIG_BCM47XX */
306
307#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
308#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
309
310#define SET_REG(r, mask, val) \
311 W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
312
313/* multi-bool data type: set of bools, mbool is true if any is set */
314
315/* set one bool */
316#define mboolset(mb, bit) ((mb) |= (bit))
317/* clear one bool */
318#define mboolclr(mb, bit) ((mb) &= ~(bit))
319/* true if one bool is set */
320#define mboolisset(mb, bit) (((mb) & (bit)) != 0)
321#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
322
323#define CEIL(x, y) (((x) + ((y)-1)) / (y))
324
325/* forward declarations */
326struct wiphy;
327struct ieee80211_sta;
328struct ieee80211_tx_queue_params;
329struct brcms_info;
330struct brcms_c_info;
331struct brcms_hardware;
332struct brcms_txq_info;
333struct brcms_band;
334struct dma_pub;
335struct si_pub;
336struct tx_status;
337struct d11rxhdr;
338struct txpwr_limits;
339
340/* iovar structure */
341struct brcmu_iovar {
342 const char *name; /* name for lookup and display */
343 u16 varid; /* id for switch */
344 u16 flags; /* driver-specific flag bits */
345 u16 type; /* base type of argument */
346 u16 minlen; /* min length for buffer vars */
347};
348
349/* brcm_msg_level is a bit vector with defs in defs.h */
350extern u32 brcm_msg_level;
351
352#endif /* _BRCM_TYPES_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/ucode_loader.c b/drivers/staging/brcm80211/brcmsmac/ucode_loader.c
deleted file mode 100644
index 80e3ccf865e..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/ucode_loader.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <defs.h>
18#include "types.h"
19#include <ucode_loader.h>
20
21enum {
22 D11UCODE_NAMETAG_START = 0,
23 D11LCN0BSINITVALS24,
24 D11LCN0INITVALS24,
25 D11LCN1BSINITVALS24,
26 D11LCN1INITVALS24,
27 D11LCN2BSINITVALS24,
28 D11LCN2INITVALS24,
29 D11N0ABSINITVALS16,
30 D11N0BSINITVALS16,
31 D11N0INITVALS16,
32 D11UCODE_OVERSIGHT16_MIMO,
33 D11UCODE_OVERSIGHT16_MIMOSZ,
34 D11UCODE_OVERSIGHT24_LCN,
35 D11UCODE_OVERSIGHT24_LCNSZ,
36 D11UCODE_OVERSIGHT_BOMMAJOR,
37 D11UCODE_OVERSIGHT_BOMMINOR
38};
39
40int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode)
41{
42 int rc;
43
44 rc = brcms_check_firmwares(wl);
45
46 rc = rc < 0 ? rc :
47 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0bsinitvals24,
48 D11LCN0BSINITVALS24);
49 rc = rc < 0 ?
50 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0initvals24,
51 D11LCN0INITVALS24);
52 rc = rc < 0 ?
53 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1bsinitvals24,
54 D11LCN1BSINITVALS24);
55 rc = rc < 0 ?
56 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1initvals24,
57 D11LCN1INITVALS24);
58 rc = rc < 0 ? rc :
59 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2bsinitvals24,
60 D11LCN2BSINITVALS24);
61 rc = rc < 0 ?
62 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2initvals24,
63 D11LCN2INITVALS24);
64 rc = rc < 0 ?
65 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0absinitvals16,
66 D11N0ABSINITVALS16);
67 rc = rc < 0 ?
68 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0bsinitvals16,
69 D11N0BSINITVALS16);
70 rc = rc < 0 ?
71 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0initvals16,
72 D11N0INITVALS16);
73 rc = rc < 0 ?
74 rc : brcms_ucode_init_buf(wl, (void **)&ucode->bcm43xx_16_mimo,
75 D11UCODE_OVERSIGHT16_MIMO);
76 rc = rc < 0 ?
77 rc : brcms_ucode_init_uint(wl, &ucode->bcm43xx_16_mimosz,
78 D11UCODE_OVERSIGHT16_MIMOSZ);
79 rc = rc < 0 ?
80 rc : brcms_ucode_init_buf(wl, (void **)&ucode->bcm43xx_24_lcn,
81 D11UCODE_OVERSIGHT24_LCN);
82 rc = rc < 0 ?
83 rc : brcms_ucode_init_uint(wl, &ucode->bcm43xx_24_lcnsz,
84 D11UCODE_OVERSIGHT24_LCNSZ);
85 rc = rc < 0 ?
86 rc : brcms_ucode_init_buf(wl, (void **)&ucode->bcm43xx_bommajor,
87 D11UCODE_OVERSIGHT_BOMMAJOR);
88 rc = rc < 0 ?
89 rc : brcms_ucode_init_buf(wl, (void **)&ucode->bcm43xx_bomminor,
90 D11UCODE_OVERSIGHT_BOMMINOR);
91 return rc;
92}
93
94void brcms_ucode_data_free(struct brcms_ucode *ucode)
95{
96 brcms_ucode_free_buf((void *)ucode->d11lcn0bsinitvals24);
97 brcms_ucode_free_buf((void *)ucode->d11lcn0initvals24);
98 brcms_ucode_free_buf((void *)ucode->d11lcn1bsinitvals24);
99 brcms_ucode_free_buf((void *)ucode->d11lcn1initvals24);
100 brcms_ucode_free_buf((void *)ucode->d11lcn2bsinitvals24);
101 brcms_ucode_free_buf((void *)ucode->d11lcn2initvals24);
102 brcms_ucode_free_buf((void *)ucode->d11n0absinitvals16);
103 brcms_ucode_free_buf((void *)ucode->d11n0bsinitvals16);
104 brcms_ucode_free_buf((void *)ucode->d11n0initvals16);
105 brcms_ucode_free_buf((void *)ucode->bcm43xx_16_mimo);
106 brcms_ucode_free_buf((void *)ucode->bcm43xx_24_lcn);
107 brcms_ucode_free_buf((void *)ucode->bcm43xx_bommajor);
108 brcms_ucode_free_buf((void *)ucode->bcm43xx_bomminor);
109}
diff --git a/drivers/staging/brcm80211/brcmsmac/ucode_loader.h b/drivers/staging/brcm80211/brcmsmac/ucode_loader.h
deleted file mode 100644
index 18750a814b4..00000000000
--- a/drivers/staging/brcm80211/brcmsmac/ucode_loader.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#ifndef _BRCM_UCODE_H_
17#define _BRCM_UCODE_H_
18
19#include "types.h" /* forward structure declarations */
20
21#define MIN_FW_SIZE 40000 /* minimum firmware file size in bytes */
22#define MAX_FW_SIZE 150000
23
24#define UCODE_LOADER_API_VER 0
25
26struct d11init;
27
28struct brcms_ucode {
29 struct d11init *d11lcn0bsinitvals24;
30 struct d11init *d11lcn0initvals24;
31 struct d11init *d11lcn1bsinitvals24;
32 struct d11init *d11lcn1initvals24;
33 struct d11init *d11lcn2bsinitvals24;
34 struct d11init *d11lcn2initvals24;
35 struct d11init *d11n0absinitvals16;
36 struct d11init *d11n0bsinitvals16;
37 struct d11init *d11n0initvals16;
38 __le32 *bcm43xx_16_mimo;
39 size_t bcm43xx_16_mimosz;
40 __le32 *bcm43xx_24_lcn;
41 size_t bcm43xx_24_lcnsz;
42 u32 *bcm43xx_bommajor;
43 u32 *bcm43xx_bomminor;
44};
45
46extern int
47brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode);
48
49extern void brcms_ucode_data_free(struct brcms_ucode *ucode);
50
51extern int brcms_ucode_init_buf(struct brcms_info *wl, void **pbuf,
52 unsigned int idx);
53extern int brcms_ucode_init_uint(struct brcms_info *wl, size_t *n_bytes,
54 unsigned int idx);
55extern void brcms_ucode_free_buf(void *);
56extern int brcms_check_firmwares(struct brcms_info *wl);
57
58#endif /* _BRCM_UCODE_H_ */
diff --git a/drivers/staging/brcm80211/brcmutil/Makefile b/drivers/staging/brcm80211/brcmutil/Makefile
deleted file mode 100644
index 6403423c021..00000000000
--- a/drivers/staging/brcm80211/brcmutil/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
1#
2# Makefile fragment for Broadcom 802.11n Networking Device Driver Utilities
3#
4# Copyright (c) 2011 Broadcom Corporation
5#
6# Permission to use, copy, modify, and/or distribute this software for any
7# purpose with or without fee is hereby granted, provided that the above
8# copyright notice and this permission notice appear in all copies.
9#
10# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17
18ccflags-y := \
19 -Idrivers/staging/brcm80211/brcmutil \
20 -Idrivers/staging/brcm80211/include
21
22BRCMUTIL_OFILES := \
23 utils.o \
24 wifi.o
25
26MODULEPFX := brcmutil
27
28obj-$(CONFIG_BRCMUTIL) += $(MODULEPFX).o
29$(MODULEPFX)-objs = $(BRCMUTIL_OFILES)
diff --git a/drivers/staging/brcm80211/brcmutil/utils.c b/drivers/staging/brcm80211/brcmutil/utils.c
deleted file mode 100644
index 62bcc71eadf..00000000000
--- a/drivers/staging/brcm80211/brcmutil/utils.c
+++ /dev/null
@@ -1,600 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/netdevice.h>
18#include <brcmu_utils.h>
19
20MODULE_AUTHOR("Broadcom Corporation");
21MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN driver utilities.");
22MODULE_SUPPORTED_DEVICE("Broadcom 802.11n WLAN cards");
23MODULE_LICENSE("Dual BSD/GPL");
24
25struct sk_buff *brcmu_pkt_buf_get_skb(uint len)
26{
27 struct sk_buff *skb;
28
29 skb = dev_alloc_skb(len);
30 if (skb) {
31 skb_put(skb, len);
32 skb->priority = 0;
33 }
34
35 return skb;
36}
37EXPORT_SYMBOL(brcmu_pkt_buf_get_skb);
38
39/* Free the driver packet. Free the tag if present */
40void brcmu_pkt_buf_free_skb(struct sk_buff *skb)
41{
42 struct sk_buff *nskb;
43 int nest = 0;
44
45 /* perversion: we use skb->next to chain multi-skb packets */
46 while (skb) {
47 nskb = skb->next;
48 skb->next = NULL;
49
50 if (skb->destructor)
51 /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if
52 * destructor exists
53 */
54 dev_kfree_skb_any(skb);
55 else
56 /* can free immediately (even in_irq()) if destructor
57 * does not exist
58 */
59 dev_kfree_skb(skb);
60
61 nest++;
62 skb = nskb;
63 }
64}
65EXPORT_SYMBOL(brcmu_pkt_buf_free_skb);
66
67
68/* copy a buffer into a pkt buffer chain */
69uint brcmu_pktfrombuf(struct sk_buff *p, uint offset, int len,
70 unsigned char *buf)
71{
72 uint n, ret = 0;
73
74 /* skip 'offset' bytes */
75 for (; p && offset; p = p->next) {
76 if (offset < (uint) (p->len))
77 break;
78 offset -= p->len;
79 }
80
81 if (!p)
82 return 0;
83
84 /* copy the data */
85 for (; p && len; p = p->next) {
86 n = min((uint) (p->len) - offset, (uint) len);
87 memcpy(p->data + offset, buf, n);
88 buf += n;
89 len -= n;
90 ret += n;
91 offset = 0;
92 }
93
94 return ret;
95}
96EXPORT_SYMBOL(brcmu_pktfrombuf);
97
98/* return total length of buffer chain */
99uint brcmu_pkttotlen(struct sk_buff *p)
100{
101 uint total;
102
103 total = 0;
104 for (; p; p = p->next)
105 total += p->len;
106 return total;
107}
108EXPORT_SYMBOL(brcmu_pkttotlen);
109
110/*
111 * osl multiple-precedence packet queue
112 * hi_prec is always >= the number of the highest non-empty precedence
113 */
114struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec,
115 struct sk_buff *p)
116{
117 struct pktq_prec *q;
118
119 if (pktq_full(pq) || pktq_pfull(pq, prec))
120 return NULL;
121
122 q = &pq->q[prec];
123
124 if (q->head)
125 q->tail->prev = p;
126 else
127 q->head = p;
128
129 q->tail = p;
130 q->len++;
131
132 pq->len++;
133
134 if (pq->hi_prec < prec)
135 pq->hi_prec = (u8) prec;
136
137 return p;
138}
139EXPORT_SYMBOL(brcmu_pktq_penq);
140
141struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec,
142 struct sk_buff *p)
143{
144 struct pktq_prec *q;
145
146 if (pktq_full(pq) || pktq_pfull(pq, prec))
147 return NULL;
148
149 q = &pq->q[prec];
150
151 if (q->head == NULL)
152 q->tail = p;
153
154 p->prev = q->head;
155 q->head = p;
156 q->len++;
157
158 pq->len++;
159
160 if (pq->hi_prec < prec)
161 pq->hi_prec = (u8) prec;
162
163 return p;
164}
165EXPORT_SYMBOL(brcmu_pktq_penq_head);
166
167struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec)
168{
169 struct pktq_prec *q;
170 struct sk_buff *p;
171
172 q = &pq->q[prec];
173
174 p = q->head;
175 if (p == NULL)
176 return NULL;
177
178 q->head = p->prev;
179 if (q->head == NULL)
180 q->tail = NULL;
181
182 q->len--;
183
184 pq->len--;
185
186 p->prev = NULL;
187
188 return p;
189}
190EXPORT_SYMBOL(brcmu_pktq_pdeq);
191
192struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec)
193{
194 struct pktq_prec *q;
195 struct sk_buff *p, *prev;
196
197 q = &pq->q[prec];
198
199 p = q->head;
200 if (p == NULL)
201 return NULL;
202
203 for (prev = NULL; p != q->tail; p = p->prev)
204 prev = p;
205
206 if (prev)
207 prev->prev = NULL;
208 else
209 q->head = NULL;
210
211 q->tail = prev;
212 q->len--;
213
214 pq->len--;
215
216 return p;
217}
218EXPORT_SYMBOL(brcmu_pktq_pdeq_tail);
219
220void
221brcmu_pktq_pflush(struct pktq *pq, int prec, bool dir,
222 bool (*fn)(struct sk_buff *, void *), void *arg)
223{
224 struct pktq_prec *q;
225 struct sk_buff *p, *prev = NULL;
226
227 q = &pq->q[prec];
228 p = q->head;
229 while (p) {
230 if (fn == NULL || (*fn) (p, arg)) {
231 bool head = (p == q->head);
232 if (head)
233 q->head = p->prev;
234 else
235 prev->prev = p->prev;
236 p->prev = NULL;
237 brcmu_pkt_buf_free_skb(p);
238 q->len--;
239 pq->len--;
240 p = (head ? q->head : prev->prev);
241 } else {
242 prev = p;
243 p = p->prev;
244 }
245 }
246
247 if (q->head == NULL)
248 q->tail = NULL;
249}
250EXPORT_SYMBOL(brcmu_pktq_pflush);
251
252void brcmu_pktq_flush(struct pktq *pq, bool dir,
253 bool (*fn)(struct sk_buff *, void *), void *arg)
254{
255 int prec;
256 for (prec = 0; prec < pq->num_prec; prec++)
257 brcmu_pktq_pflush(pq, prec, dir, fn, arg);
258}
259EXPORT_SYMBOL(brcmu_pktq_flush);
260
261void brcmu_pktq_init(struct pktq *pq, int num_prec, int max_len)
262{
263 int prec;
264
265 /* pq is variable size; only zero out what's requested */
266 memset(pq, 0,
267 offsetof(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec));
268
269 pq->num_prec = (u16) num_prec;
270
271 pq->max = (u16) max_len;
272
273 for (prec = 0; prec < num_prec; prec++)
274 pq->q[prec].max = pq->max;
275}
276EXPORT_SYMBOL(brcmu_pktq_init);
277
278struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out)
279{
280 int prec;
281
282 if (pq->len == 0)
283 return NULL;
284
285 for (prec = 0; prec < pq->hi_prec; prec++)
286 if (pq->q[prec].head)
287 break;
288
289 if (prec_out)
290 *prec_out = prec;
291
292 return pq->q[prec].tail;
293}
294EXPORT_SYMBOL(brcmu_pktq_peek_tail);
295
296/* Return sum of lengths of a specific set of precedences */
297int brcmu_pktq_mlen(struct pktq *pq, uint prec_bmp)
298{
299 int prec, len;
300
301 len = 0;
302
303 for (prec = 0; prec <= pq->hi_prec; prec++)
304 if (prec_bmp & (1 << prec))
305 len += pq->q[prec].len;
306
307 return len;
308}
309EXPORT_SYMBOL(brcmu_pktq_mlen);
310
311/* Priority dequeue from a specific set of precedences */
312struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp,
313 int *prec_out)
314{
315 struct pktq_prec *q;
316 struct sk_buff *p;
317 int prec;
318
319 if (pq->len == 0)
320 return NULL;
321
322 while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
323 pq->hi_prec--;
324
325 while ((prec_bmp & (1 << prec)) == 0 || pq->q[prec].head == NULL)
326 if (prec-- == 0)
327 return NULL;
328
329 q = &pq->q[prec];
330
331 p = q->head;
332 if (p == NULL)
333 return NULL;
334
335 q->head = p->prev;
336 if (q->head == NULL)
337 q->tail = NULL;
338
339 q->len--;
340
341 if (prec_out)
342 *prec_out = prec;
343
344 pq->len--;
345
346 p->prev = NULL;
347
348 return p;
349}
350EXPORT_SYMBOL(brcmu_pktq_mdeq);
351
352#if defined(BCMDBG)
353/* pretty hex print a pkt buffer chain */
354void brcmu_prpkt(const char *msg, struct sk_buff *p0)
355{
356 struct sk_buff *p;
357
358 if (msg && (msg[0] != '\0'))
359 printk(KERN_DEBUG "%s:\n", msg);
360
361 for (p = p0; p; p = p->next)
362 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, p->data, p->len);
363}
364EXPORT_SYMBOL(brcmu_prpkt);
365#endif /* defined(BCMDBG) */
366
367/*
368 * Traverse a string of 1-byte tag/1-byte length/variable-length value
369 * triples, returning a pointer to the substring whose first element
370 * matches tag
371 */
372struct brcmu_tlv *brcmu_parse_tlvs(void *buf, int buflen, uint key)
373{
374 struct brcmu_tlv *elt;
375 int totlen;
376
377 elt = (struct brcmu_tlv *) buf;
378 totlen = buflen;
379
380 /* find tagged parameter */
381 while (totlen >= 2) {
382 int len = elt->len;
383
384 /* validate remaining totlen */
385 if ((elt->id == key) && (totlen >= (len + 2)))
386 return elt;
387
388 elt = (struct brcmu_tlv *) ((u8 *) elt + (len + 2));
389 totlen -= (len + 2);
390 }
391
392 return NULL;
393}
394EXPORT_SYMBOL(brcmu_parse_tlvs);
395
396
397#if defined(BCMDBG)
398int
399brcmu_format_flags(const struct brcmu_bit_desc *bd, u32 flags, char *buf,
400 int len)
401{
402 int i;
403 char *p = buf;
404 char hexstr[16];
405 int slen = 0, nlen = 0;
406 u32 bit;
407 const char *name;
408
409 if (len < 2 || !buf)
410 return 0;
411
412 buf[0] = '\0';
413
414 for (i = 0; flags != 0; i++) {
415 bit = bd[i].bit;
416 name = bd[i].name;
417 if (bit == 0 && flags != 0) {
418 /* print any unnamed bits */
419 snprintf(hexstr, 16, "0x%X", flags);
420 name = hexstr;
421 flags = 0; /* exit loop */
422 } else if ((flags & bit) == 0)
423 continue;
424 flags &= ~bit;
425 nlen = strlen(name);
426 slen += nlen;
427 /* count btwn flag space */
428 if (flags != 0)
429 slen += 1;
430 /* need NULL char as well */
431 if (len <= slen)
432 break;
433 /* copy NULL char but don't count it */
434 strncpy(p, name, nlen + 1);
435 p += nlen;
436 /* copy btwn flag space and NULL char */
437 if (flags != 0)
438 p += snprintf(p, 2, " ");
439 len -= slen;
440 }
441
442 /* indicate the str was too short */
443 if (flags != 0) {
444 if (len < 2)
445 p -= 2 - len; /* overwrite last char */
446 p += snprintf(p, 2, ">");
447 }
448
449 return (int)(p - buf);
450}
451EXPORT_SYMBOL(brcmu_format_flags);
452
453/*
454 * print bytes formatted as hex to a string. return the resulting
455 * string length
456 */
457int brcmu_format_hex(char *str, const void *bytes, int len)
458{
459 int i;
460 char *p = str;
461 const u8 *src = (const u8 *)bytes;
462
463 for (i = 0; i < len; i++) {
464 p += snprintf(p, 3, "%02X", *src);
465 src++;
466 }
467 return (int)(p - str);
468}
469EXPORT_SYMBOL(brcmu_format_hex);
470#endif /* defined(BCMDBG) */
471
472char *brcmu_chipname(uint chipid, char *buf, uint len)
473{
474 const char *fmt;
475
476 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
477 snprintf(buf, len, fmt, chipid);
478 return buf;
479}
480EXPORT_SYMBOL(brcmu_chipname);
481
482uint brcmu_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
483{
484 uint len;
485
486 len = strlen(name) + 1;
487
488 if ((len + datalen) > buflen)
489 return 0;
490
491 strncpy(buf, name, buflen);
492
493 /* append data onto the end of the name string */
494 memcpy(&buf[len], data, datalen);
495 len += datalen;
496
497 return len;
498}
499EXPORT_SYMBOL(brcmu_mkiovar);
500
501/* Quarter dBm units to mW
502 * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
503 * Table is offset so the last entry is largest mW value that fits in
504 * a u16.
505 */
506
507#define QDBM_OFFSET 153 /* Offset for first entry */
508#define QDBM_TABLE_LEN 40 /* Table size */
509
510/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
511 * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
512 */
513#define QDBM_TABLE_LOW_BOUND 6493 /* Low bound */
514
515/* Largest mW value that will round down to the last table entry,
516 * QDBM_OFFSET + QDBM_TABLE_LEN-1.
517 * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) +
518 * mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
519 */
520#define QDBM_TABLE_HIGH_BOUND 64938 /* High bound */
521
522static const u16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
523/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
524/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
525/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
526/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
527/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
528/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
529};
530
531u16 brcmu_qdbm_to_mw(u8 qdbm)
532{
533 uint factor = 1;
534 int idx = qdbm - QDBM_OFFSET;
535
536 if (idx >= QDBM_TABLE_LEN)
537 /* clamp to max u16 mW value */
538 return 0xFFFF;
539
540 /* scale the qdBm index up to the range of the table 0-40
541 * where an offset of 40 qdBm equals a factor of 10 mW.
542 */
543 while (idx < 0) {
544 idx += 40;
545 factor *= 10;
546 }
547
548 /* return the mW value scaled down to the correct factor of 10,
549 * adding in factor/2 to get proper rounding.
550 */
551 return (nqdBm_to_mW_map[idx] + factor / 2) / factor;
552}
553EXPORT_SYMBOL(brcmu_qdbm_to_mw);
554
555u8 brcmu_mw_to_qdbm(u16 mw)
556{
557 u8 qdbm;
558 int offset;
559 uint mw_uint = mw;
560 uint boundary;
561
562 /* handle boundary case */
563 if (mw_uint <= 1)
564 return 0;
565
566 offset = QDBM_OFFSET;
567
568 /* move mw into the range of the table */
569 while (mw_uint < QDBM_TABLE_LOW_BOUND) {
570 mw_uint *= 10;
571 offset -= 40;
572 }
573
574 for (qdbm = 0; qdbm < QDBM_TABLE_LEN - 1; qdbm++) {
575 boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm + 1] -
576 nqdBm_to_mW_map[qdbm]) / 2;
577 if (mw_uint < boundary)
578 break;
579 }
580
581 qdbm += (u8) offset;
582
583 return qdbm;
584}
585EXPORT_SYMBOL(brcmu_mw_to_qdbm);
586
587uint brcmu_bitcount(u8 *bitmap, uint length)
588{
589 uint bitcount = 0, i;
590 u8 tmp;
591 for (i = 0; i < length; i++) {
592 tmp = bitmap[i];
593 while (tmp) {
594 bitcount++;
595 tmp &= (tmp - 1);
596 }
597 }
598 return bitcount;
599}
600EXPORT_SYMBOL(brcmu_bitcount);
diff --git a/drivers/staging/brcm80211/brcmutil/wifi.c b/drivers/staging/brcm80211/brcmutil/wifi.c
deleted file mode 100644
index 509e25c9c86..00000000000
--- a/drivers/staging/brcm80211/brcmutil/wifi.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#include <brcmu_wifi.h>
17
18/*
19 * Verify the chanspec is using a legal set of parameters, i.e. that the
20 * chanspec specified a band, bw, ctl_sb and channel and that the
21 * combination could be legal given any set of circumstances.
22 * RETURNS: true is the chanspec is malformed, false if it looks good.
23 */
24bool brcmu_chspec_malformed(u16 chanspec)
25{
26 /* must be 2G or 5G band */
27 if (!CHSPEC_IS5G(chanspec) && !CHSPEC_IS2G(chanspec))
28 return true;
29 /* must be 20 or 40 bandwidth */
30 if (!CHSPEC_IS40(chanspec) && !CHSPEC_IS20(chanspec))
31 return true;
32
33 /* 20MHZ b/w must have no ctl sb, 40 must have a ctl sb */
34 if (CHSPEC_IS20(chanspec)) {
35 if (!CHSPEC_SB_NONE(chanspec))
36 return true;
37 } else if (!CHSPEC_SB_UPPER(chanspec) && !CHSPEC_SB_LOWER(chanspec)) {
38 return true;
39 }
40
41 return false;
42}
43EXPORT_SYMBOL(brcmu_chspec_malformed);
44
45/*
46 * This function returns the channel number that control traffic is being sent
47 * on, for legacy channels this is just the channel number, for 40MHZ channels
48 * it is the upper or lower 20MHZ sideband depending on the chanspec selected.
49 */
50u8 brcmu_chspec_ctlchan(u16 chspec)
51{
52 u8 ctl_chan;
53
54 /* Is there a sideband ? */
55 if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_NONE) {
56 return CHSPEC_CHANNEL(chspec);
57 } else {
58 /*
59 * we only support 40MHZ with sidebands. chanspec channel holds
60 * the centre frequency, use that and the side band information
61 * to reconstruct the control channel number
62 */
63 if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_UPPER)
64 /*
65 * control chan is the upper 20 MHZ SB of the
66 * 40MHZ channel
67 */
68 ctl_chan = upper_20_sb(CHSPEC_CHANNEL(chspec));
69 else
70 /*
71 * control chan is the lower 20 MHZ SB of the
72 * 40MHZ channel
73 */
74 ctl_chan = lower_20_sb(CHSPEC_CHANNEL(chspec));
75 }
76
77 return ctl_chan;
78}
79EXPORT_SYMBOL(brcmu_chspec_ctlchan);
80
81/*
82 * Return the channel number for a given frequency and base frequency.
83 * The returned channel number is relative to the given base frequency.
84 * If the given base frequency is zero, a base frequency of 5 GHz is assumed for
85 * frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
86 *
87 * Frequency is specified in MHz.
88 * The base frequency is specified as (start_factor * 500 kHz).
89 * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
90 * 2.4 GHz and 5 GHz bands.
91 *
92 * The returned channel will be in the range [1, 14] in the 2.4 GHz band
93 * and [0, 200] otherwise.
94 * -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
95 * frequency is not a 2.4 GHz channel, or if the frequency is not and even
96 * multiple of 5 MHz from the base frequency to the base plus 1 GHz.
97 *
98 * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
99 */
100int brcmu_mhz2channel(uint freq, uint start_factor)
101{
102 int ch = -1;
103 uint base;
104 int offset;
105
106 /* take the default channel start frequency */
107 if (start_factor == 0) {
108 if (freq >= 2400 && freq <= 2500)
109 start_factor = WF_CHAN_FACTOR_2_4_G;
110 else if (freq >= 5000 && freq <= 6000)
111 start_factor = WF_CHAN_FACTOR_5_G;
112 }
113
114 if (freq == 2484 && start_factor == WF_CHAN_FACTOR_2_4_G)
115 return 14;
116
117 base = start_factor / 2;
118
119 /* check that the frequency is in 1GHz range of the base */
120 if ((freq < base) || (freq > base + 1000))
121 return -1;
122
123 offset = freq - base;
124 ch = offset / 5;
125
126 /* check that frequency is a 5MHz multiple from the base */
127 if (offset != (ch * 5))
128 return -1;
129
130 /* restricted channel range check for 2.4G */
131 if (start_factor == WF_CHAN_FACTOR_2_4_G && (ch < 1 || ch > 13))
132 return -1;
133
134 return ch;
135}
136EXPORT_SYMBOL(brcmu_mhz2channel);
diff --git a/drivers/staging/brcm80211/include/brcm_hw_ids.h b/drivers/staging/brcm80211/include/brcm_hw_ids.h
deleted file mode 100644
index 5fb17d53c9b..00000000000
--- a/drivers/staging/brcm80211/include/brcm_hw_ids.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_HW_IDS_H_
18#define _BRCM_HW_IDS_H_
19
20#define BCM4325_D11DUAL_ID 0x431b
21#define BCM4325_D11G_ID 0x431c
22#define BCM4325_D11A_ID 0x431d
23
24#define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
25#define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
26#define BCM4329_D11NDUAL_ID 0x432e
27
28#define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */
29#define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */
30#define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
31
32#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
33#define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db */
34
35#define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
36
37#define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
38#define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
39
40#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
41
42/* Chip IDs */
43#define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
44#define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */
45
46#define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
47#define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
48#define BCM43421_CHIP_ID 43421 /* 43421 chipcommon chipid */
49#define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
50#define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
51#define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */
52#define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */
53#define BCM4325_CHIP_ID 0x4325 /* 4325 chipcommon chipid */
54#define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */
55#define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */
56#define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */
57#define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */
58
59#endif /* _BRCM_HW_IDS_H_ */
diff --git a/drivers/staging/brcm80211/include/brcmu_utils.h b/drivers/staging/brcm80211/include/brcmu_utils.h
deleted file mode 100644
index a7d3df23661..00000000000
--- a/drivers/staging/brcm80211/include/brcmu_utils.h
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCMU_UTILS_H_
18#define _BRCMU_UTILS_H_
19
20#include <linux/skbuff.h>
21
22/*
23 * Spin at most 'us' microseconds while 'exp' is true.
24 * Caller should explicitly test 'exp' when this completes
25 * and take appropriate error action if 'exp' is still true.
26 */
27#define SPINWAIT(exp, us) { \
28 uint countdown = (us) + 9; \
29 while ((exp) && (countdown >= 10)) {\
30 udelay(10); \
31 countdown -= 10; \
32 } \
33}
34
35/* osl multi-precedence packet queue */
36#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */
37#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */
38
39#define BCME_STRLEN 64 /* Max string length for BCM errors */
40
41/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
42#define PKTBUFSZ 2048
43
44#ifndef setbit
45#ifndef NBBY /* the BSD family defines NBBY */
46#define NBBY 8 /* 8 bits per byte */
47#endif /* #ifndef NBBY */
48#define setbit(a, i) (((u8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
49#define clrbit(a, i) (((u8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
50#define isset(a, i) (((const u8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
51#define isclr(a, i) ((((const u8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
52#endif /* setbit */
53
54#define NBITS(type) (sizeof(type) * 8)
55#define NBITVAL(nbits) (1 << (nbits))
56#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
57#define NBITMASK(nbits) MAXBITVAL(nbits)
58#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
59
60/* crc defines */
61#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
62#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
63
64/* 18-bytes of Ethernet address buffer length */
65#define ETHER_ADDR_STR_LEN 18
66
67struct pktq_prec {
68 struct sk_buff *head; /* first packet to dequeue */
69 struct sk_buff *tail; /* last packet to dequeue */
70 u16 len; /* number of queued packets */
71 u16 max; /* maximum number of queued packets */
72};
73
74/* multi-priority pkt queue */
75struct pktq {
76 u16 num_prec; /* number of precedences in use */
77 u16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
78 u16 max; /* total max packets */
79 u16 len; /* total number of packets */
80 /*
81 * q array must be last since # of elements can be either
82 * PKTQ_MAX_PREC or 1
83 */
84 struct pktq_prec q[PKTQ_MAX_PREC];
85};
86
87/* operations on a specific precedence in packet queue */
88
89static inline int pktq_plen(struct pktq *pq, int prec)
90{
91 return pq->q[prec].len;
92}
93
94static inline int pktq_pavail(struct pktq *pq, int prec)
95{
96 return pq->q[prec].max - pq->q[prec].len;
97}
98
99static inline bool pktq_pfull(struct pktq *pq, int prec)
100{
101 return pq->q[prec].len >= pq->q[prec].max;
102}
103
104static inline bool pktq_pempty(struct pktq *pq, int prec)
105{
106 return pq->q[prec].len == 0;
107}
108
109static inline struct sk_buff *pktq_ppeek(struct pktq *pq, int prec)
110{
111 return pq->q[prec].head;
112}
113
114static inline struct sk_buff *pktq_ppeek_tail(struct pktq *pq, int prec)
115{
116 return pq->q[prec].tail;
117}
118
119extern struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec,
120 struct sk_buff *p);
121extern struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec,
122 struct sk_buff *p);
123extern struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec);
124extern struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec);
125
126/* packet primitives */
127extern struct sk_buff *brcmu_pkt_buf_get_skb(uint len);
128extern void brcmu_pkt_buf_free_skb(struct sk_buff *skb);
129
130/* Empty the queue at particular precedence level */
131/* callback function fn(pkt, arg) returns true if pkt belongs to if */
132extern void brcmu_pktq_pflush(struct pktq *pq, int prec,
133 bool dir, bool (*fn)(struct sk_buff *, void *), void *arg);
134
135/* operations on a set of precedences in packet queue */
136
137extern int brcmu_pktq_mlen(struct pktq *pq, uint prec_bmp);
138extern struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp,
139 int *prec_out);
140
141/* operations on packet queue as a whole */
142
143static inline int pktq_len(struct pktq *pq)
144{
145 return (int)pq->len;
146}
147
148static inline int pktq_max(struct pktq *pq)
149{
150 return (int)pq->max;
151}
152
153static inline int pktq_avail(struct pktq *pq)
154{
155 return (int)(pq->max - pq->len);
156}
157
158static inline bool pktq_full(struct pktq *pq)
159{
160 return pq->len >= pq->max;
161}
162
163static inline bool pktq_empty(struct pktq *pq)
164{
165 return pq->len == 0;
166}
167
168extern void brcmu_pktq_init(struct pktq *pq, int num_prec, int max_len);
169/* prec_out may be NULL if caller is not interested in return value */
170extern struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out);
171extern void brcmu_pktq_flush(struct pktq *pq, bool dir,
172 bool (*fn)(struct sk_buff *, void *), void *arg);
173
174/* externs */
175/* packet */
176extern uint brcmu_pktfrombuf(struct sk_buff *p,
177 uint offset, int len, unsigned char *buf);
178extern uint brcmu_pkttotlen(struct sk_buff *p);
179
180/* ip address */
181struct ipv4_addr;
182
183#ifdef BCMDBG
184extern void brcmu_prpkt(const char *msg, struct sk_buff *p0);
185#else
186#define brcmu_prpkt(a, b)
187#endif /* BCMDBG */
188
189/* brcmu_format_flags() bit description structure */
190struct brcmu_bit_desc {
191 u32 bit;
192 const char *name;
193};
194
195/* tag_ID/length/value_buffer tuple */
196struct brcmu_tlv {
197 u8 id;
198 u8 len;
199 u8 data[1];
200};
201
202/* externs */
203/* format/print */
204#if defined(BCMDBG)
205extern int brcmu_format_flags(const struct brcmu_bit_desc *bd, u32 flags,
206 char *buf, int len);
207extern int brcmu_format_hex(char *str, const void *bytes, int len);
208#endif
209
210extern char *brcmu_chipname(uint chipid, char *buf, uint len);
211
212extern struct brcmu_tlv *brcmu_parse_tlvs(void *buf, int buflen,
213 uint key);
214
215/* power conversion */
216extern u16 brcmu_qdbm_to_mw(u8 qdbm);
217extern u8 brcmu_mw_to_qdbm(u16 mw);
218
219extern uint brcmu_mkiovar(char *name, char *data, uint datalen,
220 char *buf, uint len);
221extern uint brcmu_bitcount(u8 *bitmap, uint bytelength);
222
223#endif /* _BRCMU_UTILS_H_ */
diff --git a/drivers/staging/brcm80211/include/brcmu_wifi.h b/drivers/staging/brcm80211/include/brcmu_wifi.h
deleted file mode 100644
index e98ed50c67c..00000000000
--- a/drivers/staging/brcm80211/include/brcmu_wifi.h
+++ /dev/null
@@ -1,275 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCMU_WIFI_H_
18#define _BRCMU_WIFI_H_
19
20#include <linux/if_ether.h> /* for ETH_ALEN */
21#include <linux/ieee80211.h> /* for WLAN_PMKID_LEN */
22
23/*
24 * A chanspec (u16) holds the channel number, band, bandwidth and control
25 * sideband
26 */
27
28/* channel defines */
29#define CH_UPPER_SB 0x01
30#define CH_LOWER_SB 0x02
31#define CH_EWA_VALID 0x04
32#define CH_20MHZ_APART 4
33#define CH_10MHZ_APART 2
34#define CH_5MHZ_APART 1 /* 2G band channels are 5 Mhz apart */
35#define CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */
36#define BRCM_MAX_2G_CHANNEL CH_MAX_2G_CHANNEL /* legacy define */
37
38/* bandstate array indices */
39#define BAND_2G_INDEX 0 /* wlc->bandstate[x] index */
40#define BAND_5G_INDEX 1 /* wlc->bandstate[x] index */
41
42/*
43 * max # supported channels. The max channel no is 216, this is that + 1
44 * rounded up to a multiple of NBBY (8). DO NOT MAKE it > 255: channels are
45 * u8's all over
46*/
47#define MAXCHANNEL 224
48
49#define WL_CHANSPEC_CHAN_MASK 0x00ff
50#define WL_CHANSPEC_CHAN_SHIFT 0
51
52#define WL_CHANSPEC_CTL_SB_MASK 0x0300
53#define WL_CHANSPEC_CTL_SB_SHIFT 8
54#define WL_CHANSPEC_CTL_SB_LOWER 0x0100
55#define WL_CHANSPEC_CTL_SB_UPPER 0x0200
56#define WL_CHANSPEC_CTL_SB_NONE 0x0300
57
58#define WL_CHANSPEC_BW_MASK 0x0C00
59#define WL_CHANSPEC_BW_SHIFT 10
60#define WL_CHANSPEC_BW_10 0x0400
61#define WL_CHANSPEC_BW_20 0x0800
62#define WL_CHANSPEC_BW_40 0x0C00
63
64#define WL_CHANSPEC_BAND_MASK 0xf000
65#define WL_CHANSPEC_BAND_SHIFT 12
66#define WL_CHANSPEC_BAND_5G 0x1000
67#define WL_CHANSPEC_BAND_2G 0x2000
68#define INVCHANSPEC 255
69
70/* used to calculate the chan_freq = chan_factor * 500Mhz + 5 * chan_number */
71#define WF_CHAN_FACTOR_2_4_G 4814 /* 2.4 GHz band, 2407 MHz */
72#define WF_CHAN_FACTOR_5_G 10000 /* 5 GHz band, 5000 MHz */
73#define WF_CHAN_FACTOR_4_G 8000 /* 4.9 GHz band for Japan */
74
75#define CHSPEC_CHANNEL(chspec) ((u8)((chspec) & WL_CHANSPEC_CHAN_MASK))
76#define CHSPEC_BAND(chspec) ((chspec) & WL_CHANSPEC_BAND_MASK)
77
78#define CHSPEC_CTL_SB(chspec) ((chspec) & WL_CHANSPEC_CTL_SB_MASK)
79#define CHSPEC_BW(chspec) ((chspec) & WL_CHANSPEC_BW_MASK)
80
81#define CHSPEC_IS10(chspec) \
82 (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
83
84#define CHSPEC_IS20(chspec) \
85 (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
86
87#ifndef CHSPEC_IS40
88#define CHSPEC_IS40(chspec) \
89 (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
90#endif
91
92#define CHSPEC_IS5G(chspec) \
93 (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
94
95#define CHSPEC_IS2G(chspec) \
96 (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
97
98#define CHSPEC_SB_NONE(chspec) \
99 (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE)
100
101#define CHSPEC_SB_UPPER(chspec) \
102 (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER)
103
104#define CHSPEC_SB_LOWER(chspec) \
105 (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER)
106
107#define CHSPEC_CTL_CHAN(chspec) \
108 ((CHSPEC_SB_LOWER(chspec)) ? \
109 (lower_20_sb(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \
110 (upper_20_sb(((chspec) & WL_CHANSPEC_CHAN_MASK))))
111
112#define CHSPEC2BAND(chspec) (CHSPEC_IS5G(chspec) ? BRCM_BAND_5G : BRCM_BAND_2G)
113
114#define CHANSPEC_STR_LEN 8
115
116static inline int lower_20_sb(int channel)
117{
118 return channel > CH_10MHZ_APART ? (channel - CH_10MHZ_APART) : 0;
119}
120
121static inline int upper_20_sb(int channel)
122{
123 return (channel < (MAXCHANNEL - CH_10MHZ_APART)) ?
124 channel + CH_10MHZ_APART : 0;
125}
126
127static inline int chspec_bandunit(u16 chspec)
128{
129 return CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX;
130}
131
132static inline u16 ch20mhz_chspec(int channel)
133{
134 u16 rc = channel <= CH_MAX_2G_CHANNEL ?
135 WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G;
136
137 return (u16)((u16)channel | WL_CHANSPEC_BW_20 |
138 WL_CHANSPEC_CTL_SB_NONE | rc);
139}
140
141static inline int next_20mhz_chan(int channel)
142{
143 return channel < (MAXCHANNEL - CH_20MHZ_APART) ?
144 channel + CH_20MHZ_APART : 0;
145}
146
147/* defined rate in 500kbps */
148#define BRCM_MAXRATE 108 /* in 500kbps units */
149#define BRCM_RATE_1M 2 /* in 500kbps units */
150#define BRCM_RATE_2M 4 /* in 500kbps units */
151#define BRCM_RATE_5M5 11 /* in 500kbps units */
152#define BRCM_RATE_11M 22 /* in 500kbps units */
153#define BRCM_RATE_6M 12 /* in 500kbps units */
154#define BRCM_RATE_9M 18 /* in 500kbps units */
155#define BRCM_RATE_12M 24 /* in 500kbps units */
156#define BRCM_RATE_18M 36 /* in 500kbps units */
157#define BRCM_RATE_24M 48 /* in 500kbps units */
158#define BRCM_RATE_36M 72 /* in 500kbps units */
159#define BRCM_RATE_48M 96 /* in 500kbps units */
160#define BRCM_RATE_54M 108 /* in 500kbps units */
161
162#define BRCM_2G_25MHZ_OFFSET 5 /* 2.4GHz band channel offset */
163
164#define MCSSET_LEN 16
165
166static inline bool ac_bitmap_tst(u8 bitmap, int prec)
167{
168 return (bitmap & (1 << (prec))) != 0;
169}
170
171/*
172 * Verify the chanspec is using a legal set of parameters, i.e. that the
173 * chanspec specified a band, bw, ctl_sb and channel and that the
174 * combination could be legal given any set of circumstances.
175 * RETURNS: true is the chanspec is malformed, false if it looks good.
176 */
177extern bool brcmu_chspec_malformed(u16 chanspec);
178
179/*
180 * This function returns the channel number that control traffic is being sent
181 * on, for legacy channels this is just the channel number, for 40MHZ channels
182 * it is the upper or lower 20MHZ sideband depending on the chanspec selected.
183 */
184extern u8 brcmu_chspec_ctlchan(u16 chspec);
185
186/*
187 * Return the channel number for a given frequency and base frequency.
188 * The returned channel number is relative to the given base frequency.
189 * If the given base frequency is zero, a base frequency of 5 GHz is assumed for
190 * frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
191 *
192 * Frequency is specified in MHz.
193 * The base frequency is specified as (start_factor * 500 kHz).
194 * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
195 * 2.4 GHz and 5 GHz bands.
196 *
197 * The returned channel will be in the range [1, 14] in the 2.4 GHz band
198 * and [0, 200] otherwise.
199 * -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
200 * frequency is not a 2.4 GHz channel, or if the frequency is not and even
201 * multiple of 5 MHz from the base frequency to the base plus 1 GHz.
202 *
203 * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
204 */
205extern int brcmu_mhz2channel(uint freq, uint start_factor);
206
207/* Enumerate crypto algorithms */
208#define CRYPTO_ALGO_OFF 0
209#define CRYPTO_ALGO_WEP1 1
210#define CRYPTO_ALGO_TKIP 2
211#define CRYPTO_ALGO_WEP128 3
212#define CRYPTO_ALGO_AES_CCM 4
213#define CRYPTO_ALGO_AES_RESERVED1 5
214#define CRYPTO_ALGO_AES_RESERVED2 6
215#define CRYPTO_ALGO_NALG 7
216
217/* wireless security bitvec */
218
219#define WEP_ENABLED 0x0001
220#define TKIP_ENABLED 0x0002
221#define AES_ENABLED 0x0004
222#define WSEC_SWFLAG 0x0008
223/* to go into transition mode without setting wep */
224#define SES_OW_ENABLED 0x0040
225
226/* WPA authentication mode bitvec */
227#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
228#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
229#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
230#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
231#define WPA_AUTH_RESERVED1 0x0008
232#define WPA_AUTH_RESERVED2 0x0010
233
234#define WPA2_AUTH_RESERVED1 0x0020
235#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
236#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
237#define WPA2_AUTH_RESERVED3 0x0200
238#define WPA2_AUTH_RESERVED4 0x0400
239#define WPA2_AUTH_RESERVED5 0x0800
240
241/* pmkid */
242#define MAXPMKID 16
243
244#define DOT11_DEFAULT_RTS_LEN 2347
245#define DOT11_DEFAULT_FRAG_LEN 2346
246
247#define DOT11_ICV_AES_LEN 8
248#define DOT11_QOS_LEN 2
249#define DOT11_IV_MAX_LEN 8
250#define DOT11_A4_HDR_LEN 30
251
252#define HT_CAP_RX_STBC_NO 0x0
253#define HT_CAP_RX_STBC_ONE_STREAM 0x1
254
255struct pmkid {
256 u8 BSSID[ETH_ALEN];
257 u8 PMKID[WLAN_PMKID_LEN];
258};
259
260struct pmkid_list {
261 u32 npmkid;
262 struct pmkid pmkid[1];
263};
264
265struct pmkid_cand {
266 u8 BSSID[ETH_ALEN];
267 u8 preauth;
268};
269
270struct pmkid_cand_list {
271 u32 npmkid_cand;
272 struct pmkid_cand pmkid_cand[1];
273};
274
275#endif /* _BRCMU_WIFI_H_ */
diff --git a/drivers/staging/brcm80211/include/chipcommon.h b/drivers/staging/brcm80211/include/chipcommon.h
deleted file mode 100644
index fefabc39e64..00000000000
--- a/drivers/staging/brcm80211/include/chipcommon.h
+++ /dev/null
@@ -1,284 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _SBCHIPC_H
18#define _SBCHIPC_H
19
20#include "defs.h" /* for PAD macro */
21
22struct chipcregs {
23 u32 chipid; /* 0x0 */
24 u32 capabilities;
25 u32 corecontrol; /* corerev >= 1 */
26 u32 bist;
27
28 /* OTP */
29 u32 otpstatus; /* 0x10, corerev >= 10 */
30 u32 otpcontrol;
31 u32 otpprog;
32 u32 otplayout; /* corerev >= 23 */
33
34 /* Interrupt control */
35 u32 intstatus; /* 0x20 */
36 u32 intmask;
37
38 /* Chip specific regs */
39 u32 chipcontrol; /* 0x28, rev >= 11 */
40 u32 chipstatus; /* 0x2c, rev >= 11 */
41
42 /* Jtag Master */
43 u32 jtagcmd; /* 0x30, rev >= 10 */
44 u32 jtagir;
45 u32 jtagdr;
46 u32 jtagctrl;
47
48 /* serial flash interface registers */
49 u32 flashcontrol; /* 0x40 */
50 u32 flashaddress;
51 u32 flashdata;
52 u32 PAD[1];
53
54 /* Silicon backplane configuration broadcast control */
55 u32 broadcastaddress; /* 0x50 */
56 u32 broadcastdata;
57
58 /* gpio - cleared only by power-on-reset */
59 u32 gpiopullup; /* 0x58, corerev >= 20 */
60 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
61 u32 gpioin; /* 0x60 */
62 u32 gpioout; /* 0x64 */
63 u32 gpioouten; /* 0x68 */
64 u32 gpiocontrol; /* 0x6C */
65 u32 gpiointpolarity; /* 0x70 */
66 u32 gpiointmask; /* 0x74 */
67
68 /* GPIO events corerev >= 11 */
69 u32 gpioevent;
70 u32 gpioeventintmask;
71
72 /* Watchdog timer */
73 u32 watchdog; /* 0x80 */
74
75 /* GPIO events corerev >= 11 */
76 u32 gpioeventintpolarity;
77
78 /* GPIO based LED powersave registers corerev >= 16 */
79 u32 gpiotimerval; /* 0x88 */
80 u32 gpiotimeroutmask;
81
82 /* clock control */
83 u32 clockcontrol_n; /* 0x90 */
84 u32 clockcontrol_sb; /* aka m0 */
85 u32 clockcontrol_pci; /* aka m1 */
86 u32 clockcontrol_m2; /* mii/uart/mipsref */
87 u32 clockcontrol_m3; /* cpu */
88 u32 clkdiv; /* corerev >= 3 */
89 u32 gpiodebugsel; /* corerev >= 28 */
90 u32 capabilities_ext; /* 0xac */
91
92 /* pll delay registers (corerev >= 4) */
93 u32 pll_on_delay; /* 0xb0 */
94 u32 fref_sel_delay;
95 u32 slow_clk_ctl; /* 5 < corerev < 10 */
96 u32 PAD;
97
98 /* Instaclock registers (corerev >= 10) */
99 u32 system_clk_ctl; /* 0xc0 */
100 u32 clkstatestretch;
101 u32 PAD[2];
102
103 /* Indirect backplane access (corerev >= 22) */
104 u32 bp_addrlow; /* 0xd0 */
105 u32 bp_addrhigh;
106 u32 bp_data;
107 u32 PAD;
108 u32 bp_indaccess;
109 u32 PAD[3];
110
111 /* More clock dividers (corerev >= 32) */
112 u32 clkdiv2;
113 u32 PAD[2];
114
115 /* In AI chips, pointer to erom */
116 u32 eromptr; /* 0xfc */
117
118 /* ExtBus control registers (corerev >= 3) */
119 u32 pcmcia_config; /* 0x100 */
120 u32 pcmcia_memwait;
121 u32 pcmcia_attrwait;
122 u32 pcmcia_iowait;
123 u32 ide_config;
124 u32 ide_memwait;
125 u32 ide_attrwait;
126 u32 ide_iowait;
127 u32 prog_config;
128 u32 prog_waitcount;
129 u32 flash_config;
130 u32 flash_waitcount;
131 u32 SECI_config; /* 0x130 SECI configuration */
132 u32 PAD[3];
133
134 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
135 u32 eci_output; /* 0x140 */
136 u32 eci_control;
137 u32 eci_inputlo;
138 u32 eci_inputmi;
139 u32 eci_inputhi;
140 u32 eci_inputintpolaritylo;
141 u32 eci_inputintpolaritymi;
142 u32 eci_inputintpolarityhi;
143 u32 eci_intmasklo;
144 u32 eci_intmaskmi;
145 u32 eci_intmaskhi;
146 u32 eci_eventlo;
147 u32 eci_eventmi;
148 u32 eci_eventhi;
149 u32 eci_eventmasklo;
150 u32 eci_eventmaskmi;
151 u32 eci_eventmaskhi;
152 u32 PAD[3];
153
154 /* SROM interface (corerev >= 32) */
155 u32 sromcontrol; /* 0x190 */
156 u32 sromaddress;
157 u32 sromdata;
158 u32 PAD[17];
159
160 /* Clock control and hardware workarounds (corerev >= 20) */
161 u32 clk_ctl_st; /* 0x1e0 */
162 u32 hw_war;
163 u32 PAD[70];
164
165 /* UARTs */
166 u8 uart0data; /* 0x300 */
167 u8 uart0imr;
168 u8 uart0fcr;
169 u8 uart0lcr;
170 u8 uart0mcr;
171 u8 uart0lsr;
172 u8 uart0msr;
173 u8 uart0scratch;
174 u8 PAD[248]; /* corerev >= 1 */
175
176 u8 uart1data; /* 0x400 */
177 u8 uart1imr;
178 u8 uart1fcr;
179 u8 uart1lcr;
180 u8 uart1mcr;
181 u8 uart1lsr;
182 u8 uart1msr;
183 u8 uart1scratch;
184 u32 PAD[126];
185
186 /* PMU registers (corerev >= 20) */
187 u32 pmucontrol; /* 0x600 */
188 u32 pmucapabilities;
189 u32 pmustatus;
190 u32 res_state;
191 u32 res_pending;
192 u32 pmutimer;
193 u32 min_res_mask;
194 u32 max_res_mask;
195 u32 res_table_sel;
196 u32 res_dep_mask;
197 u32 res_updn_timer;
198 u32 res_timer;
199 u32 clkstretch;
200 u32 pmuwatchdog;
201 u32 gpiosel; /* 0x638, rev >= 1 */
202 u32 gpioenable; /* 0x63c, rev >= 1 */
203 u32 res_req_timer_sel;
204 u32 res_req_timer;
205 u32 res_req_mask;
206 u32 PAD;
207 u32 chipcontrol_addr; /* 0x650 */
208 u32 chipcontrol_data; /* 0x654 */
209 u32 regcontrol_addr;
210 u32 regcontrol_data;
211 u32 pllcontrol_addr;
212 u32 pllcontrol_data;
213 u32 pmustrapopt; /* 0x668, corerev >= 28 */
214 u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
215 u32 PAD[100];
216 u16 sromotp[768];
217};
218
219/* chipid */
220#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
221#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
222#define CID_REV_SHIFT 16 /* Chip Revision shift */
223#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
224#define CID_PKG_SHIFT 20 /* Package Option shift */
225#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
226#define CID_CC_SHIFT 24
227#define CID_TYPE_MASK 0xf0000000 /* Chip Type */
228#define CID_TYPE_SHIFT 28
229
230/* capabilities */
231#define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
232#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
233#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
234/* UARTs are driven by internal divided clock */
235#define CC_CAP_UINTCLK 0x00000008
236#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
237#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
238#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
239#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
240#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
241#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
242#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
243#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
244#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
245#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
246#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
247#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
248#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
249#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
250#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
251#define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
252/* Nand flash present, rev >= 35 */
253#define CC_CAP_NFLASH 0x80000000
254
255#define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
256/* GSIO (spi/i2c) present, rev >= 37 */
257#define CC_CAP2_GSIO 0x00000002
258
259/* pmucapabilities */
260#define PCAP_REV_MASK 0x000000ff
261#define PCAP_RC_MASK 0x00001f00
262#define PCAP_RC_SHIFT 8
263#define PCAP_TC_MASK 0x0001e000
264#define PCAP_TC_SHIFT 13
265#define PCAP_PC_MASK 0x001e0000
266#define PCAP_PC_SHIFT 17
267#define PCAP_VC_MASK 0x01e00000
268#define PCAP_VC_SHIFT 21
269#define PCAP_CC_MASK 0x1e000000
270#define PCAP_CC_SHIFT 25
271#define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
272#define PCAP5_PC_SHIFT 17
273#define PCAP5_VC_MASK 0x07c00000
274#define PCAP5_VC_SHIFT 22
275#define PCAP5_CC_MASK 0xf8000000
276#define PCAP5_CC_SHIFT 27
277
278/*
279* Maximum delay for the PMU state transition in us.
280* This is an upper bound intended for spinwaits etc.
281*/
282#define PMU_MAX_TRANSITION_DLY 15000
283
284#endif /* _SBCHIPC_H */
diff --git a/drivers/staging/brcm80211/include/defs.h b/drivers/staging/brcm80211/include/defs.h
deleted file mode 100644
index 1e5f310af1e..00000000000
--- a/drivers/staging/brcm80211/include/defs.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_DEFS_H_
18#define _BRCM_DEFS_H_
19
20#include <linux/types.h>
21
22#define SI_BUS 0
23#define PCI_BUS 1
24#define PCMCIA_BUS 2
25#define SDIO_BUS 3
26#define JTAG_BUS 4
27#define USB_BUS 5
28#define SPI_BUS 6
29
30#define OFF 0
31#define ON 1 /* ON = 1 */
32#define AUTO (-1) /* Auto = -1 */
33
34/*
35 * Priority definitions according 802.1D
36 */
37#define PRIO_8021D_NONE 2
38#define PRIO_8021D_BK 1
39#define PRIO_8021D_BE 0
40#define PRIO_8021D_EE 3
41#define PRIO_8021D_CL 4
42#define PRIO_8021D_VI 5
43#define PRIO_8021D_VO 6
44#define PRIO_8021D_NC 7
45
46#define MAXPRIO 7
47#define NUMPRIO (MAXPRIO + 1)
48
49#define WL_NUMRATES 16 /* max # of rates in a rateset */
50
51#define BRCM_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NUL */
52
53#define BRCM_SET_CHANNEL 30
54#define BRCM_SET_SRL 32
55#define BRCM_SET_LRL 34
56#define BRCM_SET_BCNPRD 76
57
58#define BRCM_GET_CURR_RATESET 114 /* current rateset */
59#define BRCM_GET_PHYLIST 180
60
61/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
62
63#define WL_RADIO_SW_DISABLE (1<<0)
64#define WL_RADIO_HW_DISABLE (1<<1)
65#define WL_RADIO_MPC_DISABLE (1<<2)
66/* some countries don't support any channel */
67#define WL_RADIO_COUNTRY_DISABLE (1<<3)
68
69/* Override bit for SET_TXPWR. if set, ignore other level limits */
70#define WL_TXPWR_OVERRIDE (1U<<31)
71
72/* band types */
73#define BRCM_BAND_AUTO 0 /* auto-select */
74#define BRCM_BAND_5G 1 /* 5 Ghz */
75#define BRCM_BAND_2G 2 /* 2.4 Ghz */
76#define BRCM_BAND_ALL 3 /* all bands */
77
78/* Values for PM */
79#define PM_OFF 0
80#define PM_MAX 1
81
82/* Message levels */
83#define LOG_ERROR_VAL 0x00000001
84#define LOG_TRACE_VAL 0x00000002
85
86#define PM_OFF 0
87#define PM_MAX 1
88#define PM_FAST 2
89
90/*
91 * Sonics Configuration Space Registers.
92 */
93
94/* core sbconfig regs are top 256bytes of regs */
95#define SBCONFIGOFF 0xf00
96
97/* cpp contortions to concatenate w/arg prescan */
98#ifndef PAD
99#define _PADLINE(line) pad ## line
100#define _XSTR(line) _PADLINE(line)
101#define PAD _XSTR(__LINE__)
102#endif
103
104#endif /* _BRCM_DEFS_H_ */
diff --git a/drivers/staging/brcm80211/include/soc.h b/drivers/staging/brcm80211/include/soc.h
deleted file mode 100644
index 4fcb956ad9e..00000000000
--- a/drivers/staging/brcm80211/include/soc.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_SOC_H
18#define _BRCM_SOC_H
19
20#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
21
22/* core codes */
23#define NODEV_CORE_ID 0x700 /* Invalid coreid */
24#define CC_CORE_ID 0x800 /* chipcommon core */
25#define ILINE20_CORE_ID 0x801 /* iline20 core */
26#define SRAM_CORE_ID 0x802 /* sram core */
27#define SDRAM_CORE_ID 0x803 /* sdram core */
28#define PCI_CORE_ID 0x804 /* pci core */
29#define MIPS_CORE_ID 0x805 /* mips core */
30#define ENET_CORE_ID 0x806 /* enet mac core */
31#define CODEC_CORE_ID 0x807 /* v90 codec core */
32#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
33#define ADSL_CORE_ID 0x809 /* ADSL core */
34#define ILINE100_CORE_ID 0x80a /* iline100 core */
35#define IPSEC_CORE_ID 0x80b /* ipsec core */
36#define UTOPIA_CORE_ID 0x80c /* utopia core */
37#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
38#define SOCRAM_CORE_ID 0x80e /* internal memory core */
39#define MEMC_CORE_ID 0x80f /* memc sdram core */
40#define OFDM_CORE_ID 0x810 /* OFDM phy core */
41#define EXTIF_CORE_ID 0x811 /* external interface core */
42#define D11_CORE_ID 0x812 /* 802.11 MAC core */
43#define APHY_CORE_ID 0x813 /* 802.11a phy core */
44#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
45#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
46#define MIPS33_CORE_ID 0x816 /* mips3302 core */
47#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
48#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
49#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
50#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
51#define SDIOH_CORE_ID 0x81b /* sdio host core */
52#define ROBO_CORE_ID 0x81c /* roboswitch core */
53#define ATA100_CORE_ID 0x81d /* parallel ATA core */
54#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
55#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
56#define PCIE_CORE_ID 0x820 /* pci express core */
57#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
58#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
59#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
60#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
61#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
62#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
63#define PMU_CORE_ID 0x827 /* PMU core */
64#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
65#define SDIOD_CORE_ID 0x829 /* SDIO device core */
66#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
67#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
68#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
69#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
70#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
71#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
72#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
73#define SC_CORE_ID 0x831 /* shared common core */
74#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
75#define SPIH_CORE_ID 0x833 /* SPI host core */
76#define I2S_CORE_ID 0x834 /* I2S core */
77#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
78#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
79#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
80/* Default component, in ai chips it maps all unused address ranges */
81#define DEF_AI_COMP 0xfff
82
83/* Common core control flags */
84#define SICF_BIST_EN 0x8000
85#define SICF_PME_EN 0x4000
86#define SICF_CORE_BITS 0x3ffc
87#define SICF_FGC 0x0002
88#define SICF_CLOCK_EN 0x0001
89
90#endif /* _BRCM_SOC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 07:44:11 -0400