aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/staging
diff options
context:
space:
mode:
authorOmar Ramirez Luna <omar.ramirez@copitl.com>2012-12-24 09:10:25 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-01-07 18:03:56 -0500
commite16a922a27ec352537a8027cadc32dc156534ca5 (patch)
treed446a3eb71095a6519d1e5c84b46679b3da03a71 /drivers/staging
parentfe02508529a937faa7f978d10c7d0565f3879cb0 (diff)
staging: tidspbridge: use prepare/unprepare on dsp clocks
This solves runtime failures while trying to enable WDT3 related functionality on firmware load, however it does affect other clocks controlled by the driver. Seen on 3.8-rc1. CCF provides clk_prepare and clk_unprepare for enable and disable operations respectively, this needs to be called in the correct order while handling clocks. Code path to enable/disable dsp clocks can still be reached from an atomic context, hence we can't use clk_prepare_enable and clk_disable_unprepare yet. Signed-off-by: Omar Ramirez Luna <omar.ramirez@copitl.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging')
-rw-r--r--drivers/staging/tidspbridge/core/dsp-clock.c13
-rw-r--r--drivers/staging/tidspbridge/core/wdt.c12
2 files changed, 22 insertions, 3 deletions
diff --git a/drivers/staging/tidspbridge/core/dsp-clock.c b/drivers/staging/tidspbridge/core/dsp-clock.c
index b647207928b..2f084e181d3 100644
--- a/drivers/staging/tidspbridge/core/dsp-clock.c
+++ b/drivers/staging/tidspbridge/core/dsp-clock.c
@@ -121,9 +121,13 @@ void dsp_clk_exit(void)
121 for (i = 0; i < DM_TIMER_CLOCKS; i++) 121 for (i = 0; i < DM_TIMER_CLOCKS; i++)
122 omap_dm_timer_free(timer[i]); 122 omap_dm_timer_free(timer[i]);
123 123
124 clk_unprepare(iva2_clk);
124 clk_put(iva2_clk); 125 clk_put(iva2_clk);
126 clk_unprepare(ssi.sst_fck);
125 clk_put(ssi.sst_fck); 127 clk_put(ssi.sst_fck);
128 clk_unprepare(ssi.ssr_fck);
126 clk_put(ssi.ssr_fck); 129 clk_put(ssi.ssr_fck);
130 clk_unprepare(ssi.ick);
127 clk_put(ssi.ick); 131 clk_put(ssi.ick);
128} 132}
129 133
@@ -145,14 +149,21 @@ void dsp_clk_init(void)
145 iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck"); 149 iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
146 if (IS_ERR(iva2_clk)) 150 if (IS_ERR(iva2_clk))
147 dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk); 151 dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
152 else
153 clk_prepare(iva2_clk);
148 154
149 ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck"); 155 ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck");
150 ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck"); 156 ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck");
151 ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick"); 157 ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick");
152 158
153 if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick)) 159 if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick)) {
154 dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n", 160 dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n",
155 ssi.sst_fck, ssi.ssr_fck, ssi.ick); 161 ssi.sst_fck, ssi.ssr_fck, ssi.ick);
162 } else {
163 clk_prepare(ssi.sst_fck);
164 clk_prepare(ssi.ssr_fck);
165 clk_prepare(ssi.ick);
166 }
156} 167}
157 168
158/** 169/**
diff --git a/drivers/staging/tidspbridge/core/wdt.c b/drivers/staging/tidspbridge/core/wdt.c
index 1dce36fb828..7ff0e6c9803 100644
--- a/drivers/staging/tidspbridge/core/wdt.c
+++ b/drivers/staging/tidspbridge/core/wdt.c
@@ -63,11 +63,15 @@ int dsp_wdt_init(void)
63 dsp_wdt.fclk = clk_get(NULL, "wdt3_fck"); 63 dsp_wdt.fclk = clk_get(NULL, "wdt3_fck");
64 64
65 if (!IS_ERR(dsp_wdt.fclk)) { 65 if (!IS_ERR(dsp_wdt.fclk)) {
66 clk_prepare(dsp_wdt.fclk);
67
66 dsp_wdt.iclk = clk_get(NULL, "wdt3_ick"); 68 dsp_wdt.iclk = clk_get(NULL, "wdt3_ick");
67 if (IS_ERR(dsp_wdt.iclk)) { 69 if (IS_ERR(dsp_wdt.iclk)) {
68 clk_put(dsp_wdt.fclk); 70 clk_put(dsp_wdt.fclk);
69 dsp_wdt.fclk = NULL; 71 dsp_wdt.fclk = NULL;
70 ret = -EFAULT; 72 ret = -EFAULT;
73 } else {
74 clk_prepare(dsp_wdt.iclk);
71 } 75 }
72 } else 76 } else
73 ret = -EFAULT; 77 ret = -EFAULT;
@@ -95,10 +99,14 @@ void dsp_wdt_exit(void)
95 free_irq(INT_34XX_WDT3_IRQ, &dsp_wdt); 99 free_irq(INT_34XX_WDT3_IRQ, &dsp_wdt);
96 tasklet_kill(&dsp_wdt.wdt3_tasklet); 100 tasklet_kill(&dsp_wdt.wdt3_tasklet);
97 101
98 if (dsp_wdt.fclk) 102 if (dsp_wdt.fclk) {
103 clk_unprepare(dsp_wdt.fclk);
99 clk_put(dsp_wdt.fclk); 104 clk_put(dsp_wdt.fclk);
100 if (dsp_wdt.iclk) 105 }
106 if (dsp_wdt.iclk) {
107 clk_unprepare(dsp_wdt.iclk);
101 clk_put(dsp_wdt.iclk); 108 clk_put(dsp_wdt.iclk);
109 }
102 110
103 dsp_wdt.fclk = NULL; 111 dsp_wdt.fclk = NULL;
104 dsp_wdt.iclk = NULL; 112 dsp_wdt.iclk = NULL;